diff --git a/arch/arc/nsim/em/gcc/port.h b/arch/arc/arcem/port.h similarity index 99% rename from arch/arc/nsim/em/gcc/port.h rename to arch/arc/arcem/port.h index c18491fa..af36a6c7 100644 --- a/arch/arc/nsim/em/gcc/port.h +++ b/arch/arc/arcem/port.h @@ -273,6 +273,8 @@ __PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); __PORT__ void port_cpu_reset(void); +__PORT__ uint32_t port_cpu_clz(uint32_t); + __PORT__ void port_sched_start(void) __NO_RETURN__; __PORT__ void port_context_switch(void); diff --git a/arch/arc/nsim/em/gcc/port_c.c b/arch/arc/arcem/port_c.c similarity index 98% rename from arch/arc/nsim/em/gcc/port_c.c rename to arch/arc/arcem/port_c.c index cca0812e..ab27396b 100644 --- a/arch/arc/nsim/em/gcc/port_c.c +++ b/arch/arc/arcem/port_c.c @@ -52,7 +52,7 @@ __PORT__ void port_cpu_reset(void) __PORT__ void port_systick_config(uint32_t cycle_per_tick) // Configure SysTick to generate an interrupt every cycle_per_tick { - timer_int_clear(0); // nsim #define BOARD_SYS_TIMER_ID TIMER_0 + arc_timer_int_clear(0); // nsim #define BOARD_SYS_TIMER_ID TIMER_0 board_timer_update(cycle_per_tick); // board.c } __PORT__ void port_systick_priority_set(uint32_t prio) // Sets the int priority diff --git a/arch/arc/nsim/em/gcc/port_config.h b/arch/arc/arcem/port_config.h similarity index 80% rename from arch/arc/nsim/em/gcc/port_config.h rename to arch/arc/arcem/port_config.h index a363b793..6a15bfd4 100644 --- a/arch/arc/nsim/em/gcc/port_config.h +++ b/arch/arc/arcem/port_config.h @@ -21,15 +21,10 @@ #define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32 #define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32 #define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING -// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32 -#define TOS_CFG_CPU_HRTIMER_EN 0u -#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 1u +#define TOS_CFG_CPU_HRTIMER_EN 0u +#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u -#if (defined(__VFP_FP__) && !defined(__SOFTFP__)) -#define TOS_CFG_CPU_ARM_FPU_EN 1u -#else -#define TOS_CFG_CPU_ARM_FPU_EN 0u -#endif +#define TOS_CFG_CPU_ARM_FPU_EN 0u #endif /* _PORT_CONFIG_H_ */ diff --git a/arch/arc/arcem/port_s.s b/arch/arc/arcem/port_s.s new file mode 100644 index 00000000..7918c93e --- /dev/null +++ b/arch/arc/arcem/port_s.s @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2020, Synopsys, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define __ASSEMBLY__ +#include "arc.h" +#include "arc_asm_common.h" + +.global k_curr_task +.global k_next_task + +.global g_exc_nest_count +.global g_context_switch_reqflg + +.global tos_knl_irq_enter +.global tos_knl_irq_leave + + .text + .align 4 +dispatcher: + st sp, [r0] // ld r0, [k_curr_task] + ld sp, [r1] // ld r1, [k_next_task] +# k_curr_task = k_next_task; + st r1, [k_curr_task] + pop r0 + j [r0] + +/* return routine when task dispatch happened in task context */ +dispatch_r: + RESTORE_NONSCRATCH_REGS + j [blink] + +/* + * void port_int_disable(void); + */ + .global port_int_disable + .align 4 +port_int_disable: + clri + j [blink] + +/* + * void port_int_enable(void); + */ + .global port_int_enable + .align 4 +port_int_enable: + seti + j [blink] + +/* + * cpu_cpsr_t port_cpsr_save(void); + */ + .global port_cpsr_save + .align 4 +port_cpsr_save: + clri r0 + j [blink] + +/* + * void port_cpsr_restore(cpu_cpsr_t cpsr); + */ + .global port_cpsr_restore + .align 4 +port_cpsr_restore: + seti r0 + j [blink] + +/* + * uint32_t port_cpu_clz(uint32_t val) + * r0 --> val + */ + .global port_cpu_clz + .align 4 +port_cpu_clz: + breq r0, 0, cpu_clz_return + ffs r1, r0 + add r0, r1, 1 +cpu_clz_return: + j [blink] + +/* + * void port_sched_start(void) + */ + .global port_sched_start + .align 4 +port_sched_start: + ld r0, [k_curr_task] + ld sp, [r0] + pop r0 + j [r0] + + +/* + * void port_context_switch(void) + */ + .global port_context_switch + .align 4 +port_context_switch: + SAVE_NONSCRATCH_REGS + mov r2, dispatch_r + push r2 + ld r0, [k_curr_task] + ld r1, [k_next_task] + b dispatcher + +/* + * void port_irq_context_switch(void) + */ + .global port_irq_context_switch + .align 4 +port_irq_context_switch: + mov r0, 1 + st r0, [g_context_switch_reqflg] + j [blink] + + +/* + * void start_r(void) + */ + .global start_r + .align 4 +start_r: + pop blink; + pop r1 + pop r2 + pop r0 + + j_s.d [r1] + kflag r2 + +/****** exceptions and interrupts handing ******/ +/****** entry for exception handling ******/ + .global exc_entry_cpu + .align 4 +exc_entry_cpu: + + EXCEPTION_PROLOGUE + + mov blink, sp + mov r3, sp /* as exception handler's para(p_excinfo) */ + + ld r0, [g_exc_nest_count] + add r1, r0, 1 + st r1, [g_exc_nest_count] + brne r0, 0, exc_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +exc_handler_1: + PUSH blink + + jl tos_knl_irq_enter + + lr r0, [AUX_ECR] + lsr r0, r0, 16 + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] + + mov r0, r3 + jl [r2] + + jl tos_knl_irq_leave + +/* interrupts are not allowed */ +ret_exc: + POP sp + mov r1, g_exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] + brne r0, 0, ret_exc_1 /* nest exception case */ + lr r1, [AUX_IRQ_ACT] /* nest interrupt case */ + brne r1, 0, ret_exc_1 + + ld r0, [g_context_switch_reqflg] + brne r0, 0, ret_exc_2 +ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */ + EXCEPTION_EPILOGUE + rtie + +/* there is a dispatch request */ +ret_exc_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [g_context_switch_reqflg] + + SAVE_CALLEE_REGS /* save callee save registers */ + + /* clear exception bit to do exception exit by SW */ + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_AE + kflag r0 + + mov r1, ret_exc_r /* save return address */ + PUSH r1 + + ld r0, [k_curr_task] + ld r1, [k_next_task] + b dispatcher + +ret_exc_r: + /* recover exception status */ + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_AE + kflag r0 + + RESTORE_CALLEE_REGS + EXCEPTION_EPILOGUE + rtie + +/****** entry for normal interrupt exception handling ******/ + .global exc_entry_int /* entry for interrupt handling */ + .align 4 +exc_entry_int: +#if ARC_FEATURE_FIRQ == 1 +/* check whether it is P0 interrupt */ +#if ARC_FEATURE_RGF_NUM_BANKS > 1 + lr r0, [AUX_IRQ_ACT] + btst r0, 0 + jnz exc_entry_firq +#else + PUSH r10 + lr r10, [AUX_IRQ_ACT] + btst r10, 0 + POP r10 + jnz exc_entry_firq +#endif +#endif + INTERRUPT_PROLOGUE + + mov blink, sp + + clri /* disable interrupt */ + ld r3, [g_exc_nest_count] + add r2, r3, 1 + st r2, [g_exc_nest_count] + seti /* enable higher priority interrupt */ + + brne r3, 0, irq_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif +irq_handler_1: + PUSH blink + + jl tos_knl_irq_enter + + lr r0, [AUX_IRQ_CAUSE] + sr r0, [AUX_IRQ_SELECT] + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d irq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +irq_hint_handled: + lr r3, [AUX_IRQ_PRIORITY] + PUSH r3 /* save irq priority */ + + jl [r2] /* jump to interrupt handler */ + + jl tos_knl_irq_leave + +ret_int: + clri /* disable interrupt */ + POP r3 /* irq priority */ + POP sp + mov r1, g_exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */ + lr r0, [AUX_IRQ_CAUSE] + sr r0, [AUX_IRQ_SELECT] + lr r3, [AUX_IRQ_PRIORITY] + lr r1, [AUX_IRQ_ACT] + bclr r2, r1, r3 + brne r2, 0, ret_int_1 + + ld r0, [g_context_switch_reqflg] + brne r0, 0, ret_int_2 +ret_int_1: /* return from non-task context */ + INTERRUPT_EPILOGUE + rtie +/* there is a dispatch request */ +ret_int_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [g_context_switch_reqflg] + + /* interrupt return by SW */ + lr r10, [AUX_IRQ_ACT] + PUSH r10 + bclr r10, r10, r3 /* clear related bits in IRQ_ACT */ + sr r10, [AUX_IRQ_ACT] + + SAVE_CALLEE_REGS /* save callee save registers */ + mov r1, ret_int_r /* save return address */ + PUSH r1 + + ld r0, [k_curr_task] + ld r1, [k_next_task] + b dispatcher + +ret_int_r: + RESTORE_CALLEE_REGS + /* recover AUX_IRQ_ACT to restore the interrup status */ + POPAX AUX_IRQ_ACT + INTERRUPT_EPILOGUE + rtie + +/****** entry for fast irq exception handling ******/ + .global exc_entry_firq + .align 4 +exc_entry_firq: + SAVE_FIQ_EXC_REGS + + jl tos_knl_irq_enter + + lr r0, [AUX_IRQ_CAUSE] + mov r1, exc_int_handler_table +/* r2 = _kernel_exc_tbl + irqno *4 */ + ld.as r2, [r1, r0] + +/* for the case of software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d firq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +firq_hint_handled: +/* jump to interrupt handler */ + mov r0, sp + jl [r2] + + jl tos_knl_irq_leave + +firq_return: + RESTORE_FIQ_EXC_REGS + rtie + + + + + + diff --git a/arch/arc/nsim/common/include/tos_cpu.h b/arch/arc/common/include/tos_cpu.h similarity index 98% rename from arch/arc/nsim/common/include/tos_cpu.h rename to arch/arc/common/include/tos_cpu.h index 4aae13df..1b092a08 100644 --- a/arch/arc/nsim/common/include/tos_cpu.h +++ b/arch/arc/common/include/tos_cpu.h @@ -140,7 +140,7 @@ __KNL__ void cpu_fault_diagnosis(void); /* Restore CPU status word. */ #define TOS_CPU_INT_ENABLE() \ do { \ - __builtin_arc_seti(cpu_cpsr); \ + tos_cpu_cpsr_restore(cpu_cpsr); \ } while (0) #endif /* _TOS_CPU_H_ */ diff --git a/arch/arc/nsim/common/include/tos_cpu_def.h b/arch/arc/common/include/tos_cpu_def.h similarity index 100% rename from arch/arc/nsim/common/include/tos_cpu_def.h rename to arch/arc/common/include/tos_cpu_def.h diff --git a/arch/arc/nsim/common/include/tos_cpu_types.h b/arch/arc/common/include/tos_cpu_types.h similarity index 100% rename from arch/arc/nsim/common/include/tos_cpu_types.h rename to arch/arc/common/include/tos_cpu_types.h diff --git a/arch/arc/nsim/common/include/tos_fault.h b/arch/arc/common/include/tos_fault.h similarity index 100% rename from arch/arc/nsim/common/include/tos_fault.h rename to arch/arc/common/include/tos_fault.h diff --git a/arch/arc/nsim/common/tos_cpu.c b/arch/arc/common/tos_cpu.c similarity index 85% rename from arch/arc/nsim/common/tos_cpu.c rename to arch/arc/common/tos_cpu.c index fcb7e3f4..5ab6fe3f 100644 --- a/arch/arc/nsim/common/tos_cpu.c +++ b/arch/arc/common/tos_cpu.c @@ -16,7 +16,13 @@ *---------------------------------------------------------------------------*/ #include -#include "arc/arc_exception.h" +#include "embARC.h" + +void tos_cup_tick_handler(void) +{ + arc_timer_int_clear(BOARD_OS_TIMER_ID); + tos_tick_handler(); +} __API__ uint32_t tos_cpu_clz(uint32_t val) { @@ -100,14 +106,18 @@ __KNL__ void cpu_context_switch(void) __KNL__ void cpu_irq_context_switch(void) { - // port_irq_context_switch(); - // DO NOTHING + port_irq_context_switch(); } __KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { - port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); - port_systick_config(cycle_per_tick); + int_disable(BOARD_OS_TIMER_INTNO); /* disable os timer interrupt */ + arc_timer_stop(BOARD_OS_TIMER_ID); + arc_timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cycle_per_tick); + + int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER_T)tos_cup_tick_handler); + int_pri_set(BOARD_OS_TIMER_INTNO, INT_PRI_MIN + 1); + int_enable(BOARD_OS_TIMER_INTNO); } #if TOS_CFG_TICKLESS_EN > 0u @@ -188,7 +198,18 @@ __KNL__ void cpu_standby_mode_enter(void) } #endif /* TOS_CFG_PWR_MGR_EN */ + +uint32_t g_context_switch_reqflg; +uint32_t g_exc_nest_count; + extern void start_r(void); + +#if ARC_FEATURE_STACK_CHECK +#define ARC_INIT_STATUS ((1 << AUX_STATUS_BIT_SC) | AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE) +#else +#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE) +#endif + __KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, @@ -206,7 +227,7 @@ __KNL__ k_stack_t *cpu_task_stk_init(void *entry, regs->pc = (cpu_data_t)start_r; regs->blink = (cpu_data_t)exit; regs->task = (cpu_data_t)entry; - regs->status32 = (cpu_data_t)(AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE); + regs->status32 = ARC_INIT_STATUS; regs->r0 = (cpu_data_t)arg; diff --git a/arch/arc/nsim/common/tos_fault.c b/arch/arc/common/tos_fault.c similarity index 100% rename from arch/arc/nsim/common/tos_fault.c rename to arch/arc/common/tos_fault.c diff --git a/arch/arc/nsim/em/gcc/port_s.S b/arch/arc/nsim/em/gcc/port_s.S deleted file mode 100644 index b1e50326..00000000 --- a/arch/arc/nsim/em/gcc/port_s.S +++ /dev/null @@ -1,107 +0,0 @@ - .global port_int_disable - .global port_int_enable - - .global port_cpsr_save - .global port_cpsr_restore - - .global port_sched_start - .global port_context_switch - - .global start_r - - - .extern k_curr_task - .extern k_next_task - - - .text - .align 4 - - -.type port_int_disable, %function -port_int_disable: - clri - j [blink] - - -.type port_int_enable, %function -port_int_enable: - seti - j [blink] - -.type port_cpsr_save, %function -port_cpsr_save: - clri r0 - j [blink] - - -.type port_cpsr_restore, %function -port_cpsr_restore: - seti r0 - j [blink] - -.type port_sched_start, %function -port_sched_start: - ld r0, [k_curr_task] - ld r1, [k_next_task] - ld r2, [r1] - st r2, [r0] /*k_curr_task=k_next_task*/ - ld r0, [r2] - ld sp, [r0] - pop r3 - j [r3] - - -.type start_r, %function -start_r: - pop blink; - pop r1 - pop r2 - pop r0 - - j_s.d [r1] - kflag r2 - -.type port_context_switch, %function -port_context_switch: - pop r15 - pop r14 - pop r13 - pop blink - pop fp - pop gp - j [blink] - - - - -.type PendSV_Handler, %function -TaskSwitchContext: - clri - push gp - push fp - push blink - push r13 - push r14 - push r15 - mov r2, dispatch_r - push r2 - mov r5, k_curr_task - ld r6, [r5] - st r0, [r6] - mov r1, k_next_task - ld r2, [r1] - st r2, [r5] - ld r0, [r2] - ld sp, [r0] - seti - j [r0] - -dispatch_r: - pop r15 - pop r14 - pop r13 - pop blink - pop fp - pop gp - j [blink] diff --git a/board/ARC_NSIM_EM/BSP/Inc/core_config.h b/board/ARC_NSIM_EM/BSP/Inc/core_config.h deleted file mode 100644 index 6aca332e..00000000 --- a/board/ARC_NSIM_EM/BSP/Inc/core_config.h +++ /dev/null @@ -1,253 +0,0 @@ -#ifndef H_CORE_CONFIG - #define H_CORE_CONFIG - #define core_config_cir_identity 0x00000043 - #define core_config_cir_identity_chipid 0 - #define core_config_cir_identity_arcnum 0 - #define core_config_cir_identity_arcver 67 - #define core_config_cir_identity_family 4 - #define core_config_cir_identity_corever 3 - #define core_config_cir_aux_dccm 0x80000000 - #define core_config_bcr_bcr_ver 0x00000002 - #define core_config_bcr_bcr_ver_version 2 - #define core_config_bcr_vecbase_ac_build 0x00000010 - #define core_config_bcr_mpu_build 0x00010002 - #define core_config_bcr_mpu_build_i 0 - #define core_config_bcr_mpu_build_s 0 - #define core_config_bcr_mpu_build_regions 16 - #define core_config_bcr_mpu_build_version 2 - #define core_config_bcr_rf_build 0x0000c902 - #define core_config_bcr_rf_build_version 2 - #define core_config_bcr_rf_build_p 1 - #define core_config_bcr_rf_build_e 0 - #define core_config_bcr_rf_build_r 0 - #define core_config_bcr_rf_build_b 1 - #define core_config_bcr_rf_build_d 3 - #define core_config_bcr_d_cache_build 0x00215104 - #define core_config_bcr_d_cache_build_version 4 - #define core_config_bcr_d_cache_build_assoc 1 - #define core_config_bcr_d_cache_build_capacity 5 - #define core_config_bcr_d_cache_build_bsize 1 - #define core_config_bcr_d_cache_build_fl 2 - #define core_config_bcr_d_cache_build_ioc 0 - #define core_config_bcr_d_cache_build_cp 0 - #define core_config_bcr_d_cache_build_u 0 - #define core_config_bcr_d_cache_build_cycles 0 - #define core_config_bcr_dccm_build 0x00010904 - #define core_config_bcr_dccm_build_cycles 0 - #define core_config_bcr_dccm_build_interleave 1 - #define core_config_bcr_dccm_build_size1 0 - #define core_config_bcr_dccm_build_size0 9 - #define core_config_bcr_dccm_build_version 4 - #define core_config_bcr_timer_build 0x00010304 - #define core_config_bcr_timer_build_sp1 0 - #define core_config_bcr_timer_build_sp0 0 - #define core_config_bcr_timer_build_p1 0 - #define core_config_bcr_timer_build_p0 1 - #define core_config_bcr_timer_build_st1 0 - #define core_config_bcr_timer_build_st0 0 - #define core_config_bcr_timer_build_rtc 0 - #define core_config_bcr_timer_build_rtsc_ver 1 - #define core_config_bcr_timer_build_rtsc 0 - #define core_config_bcr_timer_build_t0 1 - #define core_config_bcr_timer_build_t1 1 - #define core_config_bcr_timer_build_version 4 - #define core_config_bcr_ap_build 0x00000405 - #define core_config_bcr_ap_build_version 5 - #define core_config_bcr_ap_build_type 4 - #define core_config_bcr_i_cache_build 0x00225104 - #define core_config_bcr_i_cache_build_assoc 1 - #define core_config_bcr_i_cache_build_version 4 - #define core_config_bcr_i_cache_build_capacity 5 - #define core_config_bcr_i_cache_build_bsize 2 - #define core_config_bcr_i_cache_build_fl 2 - #define core_config_bcr_i_cache_build_d 0 - #define core_config_bcr_iccm_build 0x00000a04 - #define core_config_bcr_iccm_build_iccm1_size1 0 - #define core_config_bcr_iccm_build_iccm0_size1 0 - #define core_config_bcr_iccm_build_iccm1_size0 0 - #define core_config_bcr_iccm_build_iccm0_size0 10 - #define core_config_bcr_iccm_build_version 4 - #define core_config_bcr_xy_build 0x00001520 - #define core_config_bcr_xy_build_memsize 1 - #define core_config_bcr_xy_build_interleaved 1 - #define core_config_bcr_xy_build_config 1 - #define core_config_bcr_xy_build_version 32 - #define core_config_bcr_dsp_build 0x00003521 - #define core_config_bcr_dsp_build_wide 0 - #define core_config_bcr_dsp_build_itu_pa 0 - #define core_config_bcr_dsp_build_acc_shift 2 - #define core_config_bcr_dsp_build_comp 1 - #define core_config_bcr_dsp_build_divsqrt 1 - #define core_config_bcr_dsp_build_version 33 - #define core_config_bcr_multiply_build 0x00022a06 - #define core_config_bcr_multiply_build_version16x16 2 - #define core_config_bcr_multiply_build_dsp 2 - #define core_config_bcr_multiply_build_cyc 2 - #define core_config_bcr_multiply_build_type 2 - #define core_config_bcr_multiply_build_version32x32 6 - #define core_config_bcr_swap_build 0x00000003 - #define core_config_bcr_swap_build_version 3 - #define core_config_bcr_norm_build 0x00000003 - #define core_config_bcr_norm_build_version 3 - #define core_config_bcr_minmax_build 0x00000002 - #define core_config_bcr_minmax_build_version 2 - #define core_config_bcr_barrel_build 0x00000303 - #define core_config_bcr_barrel_build_version 3 - #define core_config_bcr_barrel_build_shift_option 3 - #define core_config_bcr_isa_config 0x12047402 - #define core_config_bcr_isa_config_d 1 - #define core_config_bcr_isa_config_c 2 - #define core_config_bcr_isa_config_l 0 - #define core_config_bcr_isa_config_n 0 - #define core_config_bcr_isa_config_a 0 - #define core_config_bcr_isa_config_b 0 - #define core_config_bcr_isa_config_addr_size 4 - #define core_config_bcr_isa_config_lpc_size 7 - #define core_config_bcr_isa_config_pc_size 4 - #define core_config_bcr_isa_config_version 2 - #define core_config_bcr_fpu_build 0x01000f02 - #define core_config_bcr_fpu_build_da 1 - #define core_config_bcr_fpu_build_dd 0 - #define core_config_bcr_fpu_build_dc 0 - #define core_config_bcr_fpu_build_df 0 - #define core_config_bcr_fpu_build_dp 0 - #define core_config_bcr_fpu_build_fd 0 - #define core_config_bcr_fpu_build_fm 0 - #define core_config_bcr_fpu_build_sd 1 - #define core_config_bcr_fpu_build_sc 1 - #define core_config_bcr_fpu_build_sf 1 - #define core_config_bcr_fpu_build_sp 1 - #define core_config_bcr_fpu_build_version 2 - #define core_config_bcr_bs_build 0x00000002 - #define core_config_bcr_bs_build_version 2 - #define core_config_bcr_agu_build 0x01988c02 - #define core_config_bcr_agu_build_accordian 1 - #define core_config_bcr_agu_build_wb_size 4 - #define core_config_bcr_agu_build_num_modifier 24 - #define core_config_bcr_agu_build_num_offset 8 - #define core_config_bcr_agu_build_num_addr 12 - #define core_config_bcr_agu_build_version 2 - #define core_config_bcr_stack_region_build 0x00000002 - #define core_config_bcr_dmac_build 0x000a0101 - #define core_config_bcr_dmac_build_int_cfg 1 - #define core_config_bcr_dmac_build_fifo 1 - #define core_config_bcr_dmac_build_chan_mem 0 - #define core_config_bcr_dmac_build_channels 1 - #define core_config_bcr_dmac_build_version 1 - #define core_config_bcr_core_config 0x00000101 - #define core_config_bcr_core_config_turbo_boost 1 - #define core_config_bcr_core_config_version 1 - #define core_config_bcr_irq_build 0x13101401 - #define core_config_bcr_irq_build_raz 0 - #define core_config_bcr_irq_build_f 1 - #define core_config_bcr_irq_build_p 3 - #define core_config_bcr_irq_build_exts 16 - #define core_config_bcr_irq_build_irqs 20 - #define core_config_bcr_irq_build_version 1 - #define core_config_bcr_pct_build 0x08080102 - #define core_config_bcr_pct_build_version 2 - #define core_config_bcr_pct_build_s 1 - #define core_config_bcr_pct_build_i 0 - #define core_config_bcr_pct_build_c 8 - #define core_config_bcr_cc_build 0x006f0004 - #define core_config_bcr_cc_build_version 4 - #define core_config_bcr_cc_build_cc 111 - #define core_config_bcr_smart_build 0x00002003 - #define core_config_bcr_smart_build_version 3 - #define core_config_bcr_smart_build_stack_size 8 - #define core_config_cir_aux_iccm 0x00000000 - #define core_config_cir_dmp_peripheral 0xf0000000 - #define core_config_mpu_present 1 - #define core_config_mpu 1 - #define core_config_mpu_regions 16 - #define core_config_family 4 - #define core_config_core_version 2 - #define core_config_family_name "arcv2em" - #define core_config_rgf_num_banks 2 - #define core_config_rgf_banked_regs 32 - #define core_config_rgf_num_wr_ports 2 - #define core_config_endian "little" - #define core_config_endian_little 1 - #define core_config_endian_big 0 - #define core_config_lpc_size 32 - #define core_config_pc_size 32 - #define core_config_addr_size 32 - #define core_config_code_density 1 - #define core_config_div_rem "radix2" - #define core_config_div_rem_radix2 1 - #define core_config_dsp_itu 1 - #define core_config_turbo_boost 1 - #define core_config_swap 1 - #define core_config_bitscan 1 - #define core_config_mpy_option "mpyd" - #define core_config_mpy_option_num 8 - #define core_config_shift_assist 1 - #define core_config_barrel_shifter 1 - #define core_config_dsp 1 - #define core_config_dsp2 1 - #define core_config_dsp_complex 1 - #define core_config_dsp_divsqrt "radix2" - #define core_config_dsp_divsqrt_radix2 1 - #define core_config_dsp_accshift "full" - #define core_config_dsp_accshift_full 1 - #define core_config_agu_large 1 - #define core_config_agu_wb_depth 4 - #define core_config_agu_accord 1 - #define core_config_xy 1 - #define core_config_xy_config "dccm_y" - #define core_config_xy_config_dccm_y 1 - #define core_config_xy_size 8192 - #define core_config_xy_size_KM "8K" - #define core_config_xy_interleave 1 - #define core_config_xy_y_base 0xe0000000 - #define core_config_fpus_div 1 - #define core_config_fpu_mac 1 - #define core_config_fpus_mpy_fast 1 - #define core_config_fpus_div_slow 1 - #define core_config_bitstream 1 - #define core_config_timer0 1 - #define core_config_timer0_level 1 - #define core_config_timer0_vector 16 - #define core_config_timer1 1 - #define core_config_timer1_level 0 - #define core_config_timer1_vector 17 - #define core_config_action_points 2 - #define core_config_stack_check 1 - #define core_config_smart_stack_entries 8 - #define core_config_interrupts_present 1 - #define core_config_interrupts_number 20 - #define core_config_interrupts_priorities 4 - #define core_config_interrupts_externals 16 - #define core_config_interrupts 20 - #define core_config_interrupt_priorities 4 - #define core_config_ext_interrupts 16 - #define core_config_interrupts_firq 1 - #define core_config_interrupts_base 0x0 - #define core_config_dcache_present 1 - #define core_config_dcache_size 16384 - #define core_config_dcache_line_size 32 - #define core_config_dcache_ways 2 - #define core_config_dcache_feature 2 - #define core_config_icache_present 1 - #define core_config_icache_size 16384 - #define core_config_icache_line_size 32 - #define core_config_icache_ways 2 - #define core_config_icache_feature 2 - #define core_config_dccm_present 1 - #define core_config_dccm_size 0x80000 - #define core_config_dccm_base 0x80000000 - #define core_config_dccm_interleave 1 - #define core_config_iccm_present 1 - #define core_config_iccm0_present 1 - #define core_config_iccm_size 0x80000 - #define core_config_iccm0_size 0x40000 - #define core_config_iccm_base 0x00000000 - #define core_config_iccm0_base 0x00000000 - #define core_config_pct_counters 8 - #define core_config_dmac 1 - #define core_config_dmac_channels 2 - #define core_config_dmac_registers 0 - #define core_config_dmac_fifo_depth 2 - #define core_config_dmac_int_config "single_internal" -#endif /* H_CORE_CONFIG */ - diff --git a/board/ARC_NSIM_EM/BSP/Inc/nsim.h b/board/ARC_NSIM_EM/BSP/Inc/nsim.h deleted file mode 100644 index 4562f87a..00000000 --- a/board/ARC_NSIM_EM/BSP/Inc/nsim.h +++ /dev/null @@ -1,73 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_NSIM -#define H_NSIM - -#include "arc/arc_feature_config.h" -#include "arc/arc_em.h" -#include "arc/arc_timer.h" -#include "nsim_uart_obj.h" - -/** CPU Clock Frequency definition */ -#if defined(BOARD_CPU_FREQ) -/*!< Get cpu clock frequency definition from build system */ - #define CLK_CPU (BOARD_CPU_FREQ) -#elif defined(ARC_FEATURE_CPU_CLOCK_FREQ) -/*!< Get cpu clock frequency definition from tcf file */ - #define CLK_CPU (ARC_FEATURE_CPU_CLOCK_FREQ) -#else -/*!< Default cpu clock frequency */ - #define CLK_CPU (1000000) -#endif - -/* common macros must be defined by all boards */ - -#define BOARD_CONSOLE_UART_ID NSIM_UART_0_ID -#define BOARD_CONSOLE_UART_BAUD 115200 - -#define BOARD_SYS_TIMER_ID TIMER_0 -#define BOARD_SYS_TIMER_INTNO INTNO_TIMER0 -#define BOARD_SYS_TIMER_HZ (1000) - -/** board timer 1ms means what HZ count */ -#define BOARD_SYS_TIMER_MS_HZ (1000) -/** board ms counter convention based on the global timer counter */ -#define BOARD_SYS_TIMER_MS_CONV (BOARD_SYS_TIMER_MS_HZ / BOARD_SYS_TIMER_HZ) - -#define BOARD_OS_TIMER_ID TIMER_0 -#define BOARD_OS_TIMER_INTNO INTNO_TIMER0 - -#define BOARD_CPU_CLOCK CLK_CPU - -#define button_read(x) 1 -#define led_write(x, y) EMBARC_PRINTF("led out: %x, %x\r\n", x, y) -#define BOARD_LED_MASK 0xff - -#endif /* H_NSIM */ diff --git a/board/ARC_NSIM_EM/BSP/Inc/nsim_uart_obj.h b/board/ARC_NSIM_EM/BSP/Inc/nsim_uart_obj.h deleted file mode 100644 index 84f137fb..00000000 --- a/board/ARC_NSIM_EM/BSP/Inc/nsim_uart_obj.h +++ /dev/null @@ -1,58 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_NSIM_UART_OBJ -#define H_NSIM_UART_OBJ - -#include "device/ip_hal/dev_uart.h" - -/** - * NSIM UART Object Number - */ -#define DW_UART_NUM (1) /*!< NSIM UART valid number */ - -/** - * NSIM UART Object ID Macros - */ -#define NSIM_UART_0_ID (0) /*!< uart 0 id macro */ - -/** - * NSIM UART Object Control Macros - */ -#define USE_NSIM_UART_0 (1) /*!< enable use nsim uart 0 (stdio) */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* H_NSIM_UART_OBJ */ diff --git a/board/ARC_NSIM_EM/BSP/Inc/tos_config.h b/board/ARC_NSIM_EM/BSP/Inc/tos_config.h new file mode 100644 index 00000000..a7ffe2e7 --- /dev/null +++ b/board/ARC_NSIM_EM/BSP/Inc/tos_config.h @@ -0,0 +1,47 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "stddef.h" +#include "embARC.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u // 配置TencentOS tiny默认支持的最大优先级数量 + +#define TOS_CFG_ROUND_ROBIN_EN 1u // 配置TencentOS tiny的内核是否开启时间片轮转 + +#define TOS_CFG_OBJECT_VERIFY 0u // 配置TencentOS tiny是否校验指针合法 + +#define TOS_CFG_EVENT_EN 1u // TencentOS tiny 事件模块功能宏 + +#define TOS_CFG_MMHEAP_EN 1u // 配置TencentOS tiny是否开启动态内存模块 + +#define TOS_CFG_MMHEAP_POOL_SIZE (1024*20) // 配置TencentOS tiny动态内存池大小 + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE (1024*20) // 配置TencentOS tiny动态内存池大小 + +#define TOS_CFG_MUTEX_EN 1u // 配置TencentOS tiny是否开启互斥锁模块 + +#define TOS_CFG_QUEUE_EN 1u // 配置TencentOS tiny是否开启队列模块 + +#define TOS_CFG_TIMER_EN 1u // 配置TencentOS tiny是否开启软件定时器模块 + +#define TOS_CFG_SEM_EN 1u // 配置TencentOS tiny是否开启信号量模块 + +#define TOS_CFG_MMBLK_EN 1u + +#if (TOS_CFG_QUEUE_EN > 0u) +#define TOS_CFG_MSG_EN 1u +#else +#define TOS_CFG_MSG_EN 0u +#endif + +#define TOS_CFG_MSG_POOL_SIZE 10u // 配置TencentOS tiny消息队列大小 + +#define TOS_CFG_IDLE_TASK_STK_SIZE 256u // 配置TencentOS tiny空闲任务栈大小 + +#define TOS_CFG_CPU_TICK_PER_SECOND 100u // 配置TencentOS tiny的tick频率 + +#define TOS_CFG_CPU_CLOCK BOARD_CPU_CLOCK // 配置TencentOS tiny CPU频率 + +#define TOS_CFG_TIMER_AS_PROC 1u // 配置是否将TIMER配置成函数模式 + +#endif \ No newline at end of file diff --git a/board/ARC_NSIM_EM/BSP/Src/core_config.s b/board/ARC_NSIM_EM/BSP/Src/core_config.s deleted file mode 100644 index 0e55be22..00000000 --- a/board/ARC_NSIM_EM/BSP/Src/core_config.s +++ /dev/null @@ -1,252 +0,0 @@ -.ifndef __core_config_s - .define __core_config_s, 1 - .define core_config_cir_identity,0x00000043 - .define core_config_cir_identity_chipid,0 - .define core_config_cir_identity_arcnum,0 - .define core_config_cir_identity_arcver,67 - .define core_config_cir_identity_family,4 - .define core_config_cir_identity_corever,3 - .define core_config_cir_aux_dccm,0x80000000 - .define core_config_bcr_bcr_ver,0x00000002 - .define core_config_bcr_bcr_ver_version,2 - .define core_config_bcr_vecbase_ac_build,0x00000010 - .define core_config_bcr_mpu_build,0x00010002 - .define core_config_bcr_mpu_build_i,0 - .define core_config_bcr_mpu_build_s,0 - .define core_config_bcr_mpu_build_regions,16 - .define core_config_bcr_mpu_build_version,2 - .define core_config_bcr_rf_build,0x0000c902 - .define core_config_bcr_rf_build_version,2 - .define core_config_bcr_rf_build_p,1 - .define core_config_bcr_rf_build_e,0 - .define core_config_bcr_rf_build_r,0 - .define core_config_bcr_rf_build_b,1 - .define core_config_bcr_rf_build_d,3 - .define core_config_bcr_d_cache_build,0x00215104 - .define core_config_bcr_d_cache_build_version,4 - .define core_config_bcr_d_cache_build_assoc,1 - .define core_config_bcr_d_cache_build_capacity,5 - .define core_config_bcr_d_cache_build_bsize,1 - .define core_config_bcr_d_cache_build_fl,2 - .define core_config_bcr_d_cache_build_ioc,0 - .define core_config_bcr_d_cache_build_cp,0 - .define core_config_bcr_d_cache_build_u,0 - .define core_config_bcr_d_cache_build_cycles,0 - .define core_config_bcr_dccm_build,0x00010904 - .define core_config_bcr_dccm_build_cycles,0 - .define core_config_bcr_dccm_build_interleave,1 - .define core_config_bcr_dccm_build_size1,0 - .define core_config_bcr_dccm_build_size0,11 - .define core_config_bcr_dccm_build_version,4 - .define core_config_bcr_timer_build,0x00010304 - .define core_config_bcr_timer_build_sp1,0 - .define core_config_bcr_timer_build_sp0,0 - .define core_config_bcr_timer_build_p1,0 - .define core_config_bcr_timer_build_p0,1 - .define core_config_bcr_timer_build_st1,0 - .define core_config_bcr_timer_build_st0,0 - .define core_config_bcr_timer_build_rtc,0 - .define core_config_bcr_timer_build_rtsc_ver,1 - .define core_config_bcr_timer_build_rtsc,0 - .define core_config_bcr_timer_build_t0,1 - .define core_config_bcr_timer_build_t1,1 - .define core_config_bcr_timer_build_version,4 - .define core_config_bcr_ap_build,0x00000405 - .define core_config_bcr_ap_build_version,5 - .define core_config_bcr_ap_build_type,4 - .define core_config_bcr_i_cache_build,0x00225104 - .define core_config_bcr_i_cache_build_assoc,1 - .define core_config_bcr_i_cache_build_version,4 - .define core_config_bcr_i_cache_build_capacity,5 - .define core_config_bcr_i_cache_build_bsize,2 - .define core_config_bcr_i_cache_build_fl,2 - .define core_config_bcr_i_cache_build_d,0 - .define core_config_bcr_iccm_build,0x00000a04 - .define core_config_bcr_iccm_build_iccm1_size1,0 - .define core_config_bcr_iccm_build_iccm0_size1,0 - .define core_config_bcr_iccm_build_iccm1_size0,0 - .define core_config_bcr_iccm_build_iccm0_size0,11 - .define core_config_bcr_iccm_build_version,4 - .define core_config_bcr_xy_build,0x00001520 - .define core_config_bcr_xy_build_memsize,1 - .define core_config_bcr_xy_build_interleaved,1 - .define core_config_bcr_xy_build_config,1 - .define core_config_bcr_xy_build_version,32 - .define core_config_bcr_dsp_build,0x00003521 - .define core_config_bcr_dsp_build_wide,0 - .define core_config_bcr_dsp_build_itu_pa,0 - .define core_config_bcr_dsp_build_acc_shift,2 - .define core_config_bcr_dsp_build_comp,1 - .define core_config_bcr_dsp_build_divsqrt,1 - .define core_config_bcr_dsp_build_version,33 - .define core_config_bcr_multiply_build,0x00022a06 - .define core_config_bcr_multiply_build_version16x16,2 - .define core_config_bcr_multiply_build_dsp,2 - .define core_config_bcr_multiply_build_cyc,2 - .define core_config_bcr_multiply_build_type,2 - .define core_config_bcr_multiply_build_version32x32,6 - .define core_config_bcr_swap_build,0x00000003 - .define core_config_bcr_swap_build_version,3 - .define core_config_bcr_norm_build,0x00000003 - .define core_config_bcr_norm_build_version,3 - .define core_config_bcr_minmax_build,0x00000002 - .define core_config_bcr_minmax_build_version,2 - .define core_config_bcr_barrel_build,0x00000303 - .define core_config_bcr_barrel_build_version,3 - .define core_config_bcr_barrel_build_shift_option,3 - .define core_config_bcr_isa_config,0x12047402 - .define core_config_bcr_isa_config_d,1 - .define core_config_bcr_isa_config_c,2 - .define core_config_bcr_isa_config_l,0 - .define core_config_bcr_isa_config_n,0 - .define core_config_bcr_isa_config_a,0 - .define core_config_bcr_isa_config_b,0 - .define core_config_bcr_isa_config_addr_size,4 - .define core_config_bcr_isa_config_lpc_size,7 - .define core_config_bcr_isa_config_pc_size,4 - .define core_config_bcr_isa_config_version,2 - .define core_config_bcr_fpu_build,0x01000f02 - .define core_config_bcr_fpu_build_da,1 - .define core_config_bcr_fpu_build_dd,0 - .define core_config_bcr_fpu_build_dc,0 - .define core_config_bcr_fpu_build_df,0 - .define core_config_bcr_fpu_build_dp,0 - .define core_config_bcr_fpu_build_fd,0 - .define core_config_bcr_fpu_build_fm,0 - .define core_config_bcr_fpu_build_sd,1 - .define core_config_bcr_fpu_build_sc,1 - .define core_config_bcr_fpu_build_sf,1 - .define core_config_bcr_fpu_build_sp,1 - .define core_config_bcr_fpu_build_version,2 - .define core_config_bcr_agu_build,0x01988c02 - .define core_config_bcr_agu_build_accordian,1 - .define core_config_bcr_agu_build_wb_size,4 - .define core_config_bcr_agu_build_num_modifier,24 - .define core_config_bcr_agu_build_num_offset,8 - .define core_config_bcr_agu_build_num_addr,12 - .define core_config_bcr_agu_build_version,2 - .define core_config_bcr_stack_region_build,0x00000002 - .define core_config_bcr_dmac_build,0x000a0101 - .define core_config_bcr_dmac_build_int_cfg,1 - .define core_config_bcr_dmac_build_fifo,1 - .define core_config_bcr_dmac_build_chan_mem,0 - .define core_config_bcr_dmac_build_channels,1 - .define core_config_bcr_dmac_build_version,1 - .define core_config_bcr_core_config,0x00000101 - .define core_config_bcr_core_config_turbo_boost,1 - .define core_config_bcr_core_config_version,1 - .define core_config_bcr_irq_build,0x13101401 - .define core_config_bcr_irq_build_raz,0 - .define core_config_bcr_irq_build_f,1 - .define core_config_bcr_irq_build_p,3 - .define core_config_bcr_irq_build_exts,16 - .define core_config_bcr_irq_build_irqs,20 - .define core_config_bcr_irq_build_version,1 - .define core_config_bcr_pct_build,0x08080102 - .define core_config_bcr_pct_build_version,2 - .define core_config_bcr_pct_build_s,1 - .define core_config_bcr_pct_build_i,0 - .define core_config_bcr_pct_build_c,8 - .define core_config_bcr_cc_build,0x006f0004 - .define core_config_bcr_cc_build_version,4 - .define core_config_bcr_cc_build_cc,111 - .define core_config_bcr_smart_build,0x00002003 - .define core_config_bcr_smart_build_version,3 - .define core_config_bcr_smart_build_stack_size,8 - .define core_config_cir_aux_iccm,0x00000000 - .define core_config_cir_dmp_peripheral,0xf0000000 - .define core_config_family,4 - .define core_config_core_version,2 - .define core_config_family_name,"arcv2em" - .define core_config_rgf_num_banks,2 - .define core_config_rgf_banked_regs,32 - .define core_config_rgf_num_wr_ports,2 - .define core_config_endian,"little" - .define core_config_endian_little,1 - .define core_config_endian_big,0 - .define core_config_lpc_size,32 - .define core_config_pc_size,32 - .define core_config_addr_size,32 - .define core_config_code_density,1 - .define core_config_div_rem,"radix2" - .define core_config_div_rem_radix2,1 - .define core_config_dsp_itu,1 - .define core_config_turbo_boost,1 - .define core_config_swap,1 - .define core_config_bitscan,1 - .define core_config_mpy_option,"mpyd" - .define core_config_mpy_option_num,8 - .define core_config_shift_assist,1 - .define core_config_barrel_shifter,1 - .define core_config_mpu_present,1 - .define core_config_mpu,1 - .define core_config_mpu_regions,16 - .define core_config_dsp,1 - .define core_config_dsp2,1 - .define core_config_dsp_complex,1 - .define core_config_dsp_divsqrt,"radix2" - .define core_config_dsp_divsqrt_radix2,1 - .define core_config_dsp_accshift,"full" - .define core_config_dsp_accshift_full,1 - .define core_config_agu_large,1 - .define core_config_agu_wb_depth,4 - .define core_config_agu_accord,1 - .define core_config_xy,1 - .define core_config_xy_config,"dccm_y" - .define core_config_xy_config_dccm_y,1 - .define core_config_xy_size,8192 - .define core_config_xy_size_KM,"8K" - .define core_config_xy_interleave,1 - .define core_config_xy_y_base,0xe0000000 - .define core_config_fpus_div,1 - .define core_config_fpu_mac,1 - .define core_config_fpuda,1 - .define core_config_fpus_mpy_slow,1 - .define core_config_fpus_div_slow,1 - .define core_config_bitstream,1 - .define core_config_timer0,1 - .define core_config_timer0_level,1 - .define core_config_timer0_vector,16 - .define core_config_timer1,1 - .define core_config_timer1_level,0 - .define core_config_timer1_vector,17 - .define core_config_action_points,2 - .define core_config_stack_check,1 - .define core_config_smart_stack_entries,8 - .define core_config_interrupts_present,1 - .define core_config_interrupts_number,20 - .define core_config_interrupts_priorities,4 - .define core_config_interrupts_externals,16 - .define core_config_interrupts,20 - .define core_config_interrupt_priorities,4 - .define core_config_ext_interrupts,16 - .define core_config_interrupts_firq,1 - .define core_config_interrupts_base,0x0 - .define core_config_dcache_present,1 - .define core_config_dcache_size,16384 - .define core_config_dcache_line_size,32 - .define core_config_dcache_ways,2 - .define core_config_dcache_feature,2 - .define core_config_icache_present,1 - .define core_config_icache_size,16384 - .define core_config_icache_line_size,32 - .define core_config_icache_ways,2 - .define core_config_icache_feature,2 - .define core_config_dccm_present,1 - .define core_config_dccm_size,0x80000 - .define core_config_dccm_base,0x80000000 - .define core_config_dccm_interleave,1 - .define core_config_iccm_present,1 - .define core_config_iccm0_present,1 - .define core_config_iccm_size,0x80000 - .define core_config_iccm0_size,0x80000 - .define core_config_iccm_base,0x00000000 - .define core_config_iccm0_base,0x00000000 - .define core_config_pct_counters,8 - .define core_config_dmac,1 - .define core_config_dmac_channels,2 - .define core_config_dmac_registers,0 - .define core_config_dmac_fifo_depth,2 - .define core_config_dmac_int_config,"single_internal" -.endif ; __core_config_s - diff --git a/board/ARC_NSIM_EM/BSP/Src/main.c b/board/ARC_NSIM_EM/BSP/Src/main.c index ec93341c..40b558cf 100644 --- a/board/ARC_NSIM_EM/BSP/Src/main.c +++ b/board/ARC_NSIM_EM/BSP/Src/main.c @@ -1,22 +1,17 @@ #include "cmsis_os.h" - -#define APPLICATION_TASK_STK_SIZE 1024*64 +#include extern void application_entry(void *arg); -osThreadDef(application_entry, osPriorityNormal, 1, APPLICATION_TASK_STK_SIZE); - -EMBARC_WEAK void application_entry(void *arg) -{ - while (1) { - printf("This is a demo task,please use your task entry!\r\n"); - tos_task_delay(1000); - } -} int main(void) { - printf("Welcome to TencentOS tiny\r\n"); - osKernelInitialize(); // TOS Tiny kernel initialize - osThreadCreate(osThread(application_entry), NULL); // Create TOS Tiny task - osKernelStart(); // Start TOS Tiny + printf("hello world\r\n"); + printf("***I am task\r\n"); + osKernelInitialize(); //TOS Tiny kernel initialize + application_entry(NULL); + osKernelStart(); //Start TOS Tiny + + while (1) + { + } } diff --git a/board/ARC_NSIM_EM/BSP/Src/nsim_init.c b/board/ARC_NSIM_EM/BSP/Src/nsim_init.c deleted file mode 100644 index 7e37d17c..00000000 --- a/board/ARC_NSIM_EM/BSP/Src/nsim_init.c +++ /dev/null @@ -1,41 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "arc/arc_timer.h" -#include "board.h" - -/** - * @brief necessary board hardware initialization - * @note It is better to disable interrupts when calling this function - * remember to enable interrupt when you want to use them - */ -void board_init(void) -{ - arc_timer_init(); -} diff --git a/board/ARC_NSIM_EM/BSP/Src/nsim_uart_obj.c b/board/ARC_NSIM_EM/BSP/Src/nsim_uart_obj.c deleted file mode 100644 index 32c6bb14..00000000 --- a/board/ARC_NSIM_EM/BSP/Src/nsim_uart_obj.c +++ /dev/null @@ -1,129 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include -#include "nsim.h" - -/** - * NSIM UART 0 Object Instantiation - */ -#if (USE_NSIM_UART_0) - -static DEV_UART nsim_uart_0; /*!< nsim uart object */ - -/** nsim uart 0 open */ -static int32_t nsim_uart_0_open(uint32_t baud) -{ - /* no need to open, stdio is used */ - return 0; -} -/** nsim uart 0 close */ -static int32_t nsim_uart_0_close(void) -{ - return 0; -} -/** nsim uart 0 control */ -static int32_t nsim_uart_0_control(uint32_t ctrl_cmd, void *param) -{ - return 0; -} -/** nsim uart 0 write */ -static int32_t nsim_uart_0_write(const void *data, uint32_t len) -{ - return fwrite(data, len, sizeof(uint8_t), stdout); -} -/** nsim uart 0 close */ -static int32_t nsim_uart_0_read(void *data, uint32_t len) -{ - uint32_t i; - int32_t c; - - for (i = 0; i < len; i++) { - c = getchar(); - if (c < 0) { - break; - } - if (c == 10) { - c = 13; - } - *((uint8_t *)data) = (uint8_t)c; - data++; - } - - return i; -} - -/** install nsim uart 0 to system */ -static void nsim_uart_0_install(void) -{ - DEV_UART *nsim_uart_ptr = &nsim_uart_0; - - /** uart dev init */ - nsim_uart_ptr->uart_open = nsim_uart_0_open; - nsim_uart_ptr->uart_close = nsim_uart_0_close; - nsim_uart_ptr->uart_control = nsim_uart_0_control; - nsim_uart_ptr->uart_write = nsim_uart_0_write; - nsim_uart_ptr->uart_read = nsim_uart_0_read; - -} -#endif /* USE_DW_UART_0 */ - -/** - * \brief install all uart objects - * \note \b MUST be called during system init - */ -static void nsim_uart_all_install(void) -{ -#if (USE_NSIM_UART_0) - nsim_uart_0_install(); -#endif -} - -/** get one uart device structure */ -DEV_UART_PTR uart_get_dev(int32_t uart_id) -{ - static uint32_t install_flag = 0; - - /* intall device objects */ - if (install_flag == 0) { - install_flag = 1; - nsim_uart_all_install(); - } - - switch (uart_id) { -#if (USE_NSIM_UART_0) - case NSIM_UART_0_ID: - return &nsim_uart_0; - break; -#endif - default: - break; - } - return NULL; -} diff --git a/board/ARC_NSIM_EM/GCC/hello_world/.cproject b/board/ARC_NSIM_EM/GCC/hello_world/.cproject deleted file mode 100644 index c34a0fc6..00000000 --- a/board/ARC_NSIM_EM/GCC/hello_world/.cproject +++ /dev/null @@ -1,259 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/board/ARC_NSIM_EM/GCC/hello_world/IDE调试步骤.md b/board/ARC_NSIM_EM/GCC/hello_world/IDE调试步骤.md deleted file mode 100644 index 6533512d..00000000 --- a/board/ARC_NSIM_EM/GCC/hello_world/IDE调试步骤.md +++ /dev/null @@ -1,14 +0,0 @@ -### 运行IDE步骤 - -1. 修改文件`.project`中tencentos-tiny的路径 - -``` - - - TencentOS_ROOT - file:/C:/Users/jingru/Documents/git/tencentos/TencentOS-tiny - - -``` -2. 打开ide，点击**File->Open Projects From File system**, 添加`hello_world`根路径。 -3. 点击**Denug**启动调试 \ No newline at end of file diff --git a/board/ARC_NSIM_EM/GCC/hello_world/Makefile b/board/ARC_NSIM_EM/GCC/hello_world/Makefile deleted file mode 100644 index 9c05f7f3..00000000 --- a/board/ARC_NSIM_EM/GCC/hello_world/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [3.3.0] date: [Mon Aug 05 10:29:11 CST 2019] -########################################################################################################################## - -# ------------------------------------------------ -# Generic Makefile (based on gcc) -# -# ChangeLog : -# 2017-02-10 - Several enhancements + project update mode -# 2015-07-22 - first version -# ------------------------------------------------ - -###################################### -# target -###################################### -TARGET = TencentOS_tiny - - -###################################### -# building variables -###################################### -# debug build? -DEBUG = 1 -# optimization -OPT = -O0 - -TOP_DIR = ../../../../ -####################################### -# paths -####################################### -# Build path -BUILD_DIR = build - -###################################### -# source -###################################### -# C sources -KERNEL_SRC = \ - ${wildcard $(TOP_DIR)/kernel/core/*.c} - C_SOURCES += $(KERNEL_SRC) - -ARCH_SRC = \ - ${wildcard $(TOP_DIR)/arch/arc/nsim/em/gcc/*.c} \ - ${wildcard $(TOP_DIR)/arch/arc/nsim/common/*.c} - C_SOURCES += $(ARCH_SRC) - -CMSIS_SRC = \ - ${wildcard $(TOP_DIR)/osal/cmsis_os/*.c} - C_SOURCES += $(CMSIS_SRC) - -HAL_DRIVER_SRC = \ - $(TOP_DIR)/board/ARC_NSIM_EM/BSP/Src/main.c \ - $(TOP_DIR)/board/ARC_NSIM_EM/BSP/Src/nsim_init.c \ - $(TOP_DIR)/board/ARC_NSIM_EM/BSP/Src/nsim_uart_obj.c \ - $(TOP_DIR)/examples/hello_world/hello_world.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/board/board.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/startup/arc_cxx_support.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_cache.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_connect.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_exception.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_mp.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_mpu.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_timer.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_udma.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_util.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library/clib/embARC_sbrk.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library/console/xprintf/xprintf.c \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library/console/console_io.c - C_SOURCES += $(HAL_DRIVER_SRC) - -# ASM sources -ASM_SOURCES = \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/startup/arc_startup.s \ - $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_exc_asm.s - - -ASM_SOURCES_S = \ -$(TOP_DIR)/arch/arc/nsim/em/gcc/port_s.S - - -####################################### -# binaries -####################################### -PREFIX = arc-elf32- -# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) -# either it can be added to the PATH environment variable. -ifdef GCC_PATH -CC = $(GCC_PATH)/$(PREFIX)gcc -AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp -CP = $(GCC_PATH)/$(PREFIX)objcopy -SZ = $(GCC_PATH)/$(PREFIX)size -else -CC = $(PREFIX)gcc -AS = $(PREFIX)gcc -x assembler-with-cpp -CP = $(PREFIX)objcopy -SZ = $(PREFIX)size -endif -HEX = $(CP) -O ihex -BIN = $(CP) -O binary -S - -####################################### -# CFLAGS -####################################### -# cpu -# CPU = -mcpu=cortex-m4 - -# # fpu -# FPU = -mfpu=fpv4-sp-d16 - -# # float-abi -# FLOAT-ABI = -mfloat-abi=hard - -# # mcu -# MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) - -# macros for gcc -# AS defines -AS_DEFS = - -# C defines -DLIB_CONSOLE -C_DEFS = \ --DLIB_CONSOLE \ --DBOARD_NSIM \ --DCURRENT_CORE=arcem \ --DEMBARC_TCF_GENERATED \ --DHW_VERSION=10 \ --DLIB_CLIB \ --D_HAVE_LIBGLOSS_ \ --D_HEAPSIZE=8192 \ --D_HOSTLINK_ \ --D_NSIM_ \ --D_STACKSIZE=2048 \ --D__GNU__ - - - -# AS includes -AS_INCLUDES = - -# C includes -KERNEL_INC = \ - -I $(TOP_DIR)/kernel/core/include \ - -I $(TOP_DIR)/kernel/pm/include \ - -I $(TOP_DIR)/kernel/hal/include \ - -I $(TOP_DIR)/arch/arc/nsim/common/include \ - -I $(TOP_DIR)/arch/arc/nsim/em/gcc \ - -I $(TOP_DIR)/board/ARC_NSIM_EM/TOS-CONFIG - C_INCLUDES += $(KERNEL_INC) -CMSIS_INC = \ - -I $(TOP_DIR)/osal/cmsis_os - C_INCLUDES += $(CMSIS_INC) - -HAL_DRIVER_INC = \ - -I $(TOP_DIR)/board/ARC_NSIM_EM/BSP/Inc \ - -I $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/include \ - -I $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/board \ - -I $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library - C_INCLUDES += $(HAL_DRIVER_INC) - -# compile gcc flags -ASFLAGS = -mcpu=em4_dmips -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter --param l1-cache-size=16384 --param l1-cache-line-size=32 $(C_DEFS) $(C_INCLUDES) $(OPT) -fdata-sections -ffunction-sections -mno-sdata -g - -CFLAGS = -mcpu=em4_dmips -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter --param l1-cache-size=16384 --param l1-cache-line-size=32 $(C_DEFS) $(C_INCLUDES) $(OPT) -fdata-sections -ffunction-sections -mno-sdata -g -std=gnu99 - -# ifeq ($(DEBUG), 1) -# CFLAGS += -g -gdwarf-2 -# endif - - -# Generate dependency information -CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" - - -####################################### -# LDFLAGS -####################################### -# link script -LDSCRIPT = linker_template_gnu.ldf - -# libraries -lc -lm -lnosys -LIBS = -lc -lgcc -LIBDIR = -LDFLAGS = --specs=nsim.specs -mcpu=em4_dmips -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter --param l1-cache-size=16384 --param l1-cache-line-size=32 $(LIBDIR) $(LIBS) -mno-sdata -nostartfiles -Wl,-M,-Map=$(BUILD_DIR)/$(TARGET).map -lm -Wl,--script=$(LDSCRIPT) - -# default action: build all -all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin - - -####################################### -# build the application -####################################### -# list of objects -OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) -vpath %.c $(sort $(dir $(C_SOURCES))) -# list of ASM program objects -OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) -vpath %.s $(sort $(dir $(ASM_SOURCES))) -OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES_S:.S=.o))) -vpath %.S $(sort $(dir $(ASM_SOURCES_S))) - -$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) - $(CC) -c $(CFLAGS) $< -o $@ - -$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) - $(AS) -c $(CFLAGS) $< -o $@ - -$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) - $(AS) -c $(CFLAGS) $< -o $@ - -$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile - $(CC) $(OBJECTS) $(LDFLAGS) -o $@ - $(SZ) $@ - -$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) - $(HEX) $< $@ - -$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) - $(BIN) $< $@ - -$(BUILD_DIR): - mkdir $@ - -####################################### -# clean up -####################################### -clean: - -rm -fR $(BUILD_DIR) - -run : build/TencentOS_tiny.elf - nsimdrv -p nsim_emt=1 -propsfile nsim.props build/TencentOS_tiny.elf -####################################### -# dependencies -####################################### --include $(wildcard $(BUILD_DIR)/*.d) - -# *** EOF *** \ No newline at end of file diff --git a/board/ARC_NSIM_EM/GCC/hello_world/blinky-arcem.launch b/board/ARC_NSIM_EM/GCC/hello_world/blinky-arcem.launch deleted file mode 100644 index fc5527c1..00000000 --- a/board/ARC_NSIM_EM/GCC/hello_world/blinky-arcem.launch +++ /dev/null @@ -1,92 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/board/ARC_NSIM_EM/GCC/hello_world/linker_template_gnu.ldf b/board/ARC_NSIM_EM/GCC/hello_world/linker_template_gnu.ldf deleted file mode 100644 index 077f1a15..00000000 --- a/board/ARC_NSIM_EM/GCC/hello_world/linker_template_gnu.ldf +++ /dev/null @@ -1,104 +0,0 @@ -MEMORY -{ - REGION_ICCM : ORIGIN = 0x00000000, LENGTH = 0x80000 - REGION_DCCM : ORIGIN = 0x80000000, LENGTH = 0x80000 - REGION_YCCM : ORIGIN = 0xe0000000, LENGTH = 8192 -} -ENTRY(_start) -SECTIONS -{ - .init : - { - . = . + 0x0; - _f_init = .; - KEEP (*(.init_vector .init_vector.*)) - KEEP (*(.init_bootstrap .init_bootstrap.*)) - _e_init = .; - } > REGION_ICCM - .vector : ALIGN(1024) - { - _f_vector = .; - *(.vector .vector.*) - _e_vector = .; - } > REGION_ICCM - .y_ccm (NOLOAD) : ALIGN(8) - { - _f_y_ccm = .; - *(.y_ccm .y_ccm.*) - _e_y_ccm = .; - } > REGION_YCCM - .text : ALIGN(4) - { - _f_text = .; - *(.text .text.* .gnu.linkonce.t.*) - _e_text = .; - } > REGION_ICCM - .rodata : ALIGN(4) - { - _f_rodata = .; - . = ALIGN(4); - __CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - KEEP(*(SORT_BY_NAME(".ctors*"))) - LONG(0) - __CTOR_END__ = .; - . = ALIGN(4); - __init_array_start = .; - KEEP(*(SORT_BY_NAME(".init_array*"))) - __init_array_end = .; - . = ALIGN(4); - __DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - KEEP(*(SORT_BY_NAME(".dtors*"))) - LONG(0) - __DTOR_END__ = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - _e_rodata = .; - } > REGION_ICCM - .data : ALIGN(4) - { - _f_data = .; - *(.data .data.* .gnu.linkonce.d.*) - _f_sdata = .; - __SDATA_BEGIN__ = .; - *(.sdata .sdata.* .gnu.linkonce.s.*) - PROVIDE (__sbss_start = .); - PROVIDE (___sbss_start = .); - _f_sbss = .; - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - _e_sbss = .; - PROVIDE (__sbss_end = .); - PROVIDE (___sbss_end = .); - _e_sdata = .; - _e_data = .; - } > REGION_DCCM AT > REGION_ICCM - .bss (NOLOAD) : ALIGN(8) - { - _f_bss = .; - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - _e_bss = .; - } > REGION_DCCM - .stack (NOLOAD) : - { - . = ALIGN(4); - _f_stack = .; - . = . + 2048; - _e_stack = .; - } > REGION_DCCM - .heap (NOLOAD) : - { - . = ALIGN(4); - __start_heap = . ; - _f_heap = .; - . = . + 8192; - _e_heap = .; - __end_heap = . ; - } > REGION_DCCM - _load_addr_text = LOADADDR(.text); - _load_addr_rodata = LOADADDR(.rodata); - _load_addr_data = LOADADDR(.data); -} diff --git a/board/ARC_NSIM_EM/GCC/hello_world/nsim.props b/board/ARC_NSIM_EM/GCC/hello_world/nsim.props deleted file mode 100644 index 66599ad0..00000000 --- a/board/ARC_NSIM_EM/GCC/hello_world/nsim.props +++ /dev/null @@ -1,68 +0,0 @@ - nsim_isa_family=av2em - nsim_isa_core=3 - arcver=0x3 - nsim_isa_rgf_num_banks=2 - nsim_isa_rgf_banked_regs=32 - nsim_isa_rgf_num_regs=32 - nsim_isa_rgf_num_wr_ports=2 - nsim_isa_big_endian=0 - nsim_isa_lpc_size=32 - nsim_isa_pc_size=32 - nsim_isa_addr_size=32 - nsim_isa_code_density_option=2 - nsim_isa_div_rem_option=1 - nsim_isa_turbo_boost=1 - nsim_isa_swap_option=1 - nsim_isa_bitscan_option=1 - nsim_isa_mpy_option=8 - nsim_isa_shift_option=3 - mpu_regions=16 - mpu_version=2 - nsim_isa_dsp_option=2 - nsim_isa_dsp_complex_option=1 - nsim_isa_dsp_divsqrt_option=1 - nsim_isa_dsp_itu_option=1 - nsim_isa_dsp_itu_option=1 - nsim_isa_dsp_accshift_option=2 - nsim_isa_agu_size=large - nsim_isa_agu_wb_depth=4 - nsim_isa_agu_accord=1 - nsim_isa_xy=1 - nsim_isa_xy_config=dccm_y - nsim_isa_xy_size=8K - nsim_isa_xy_interleave=1 - nsim_isa_xy_y_base=0xe0000000 - nsim_isa_fpus_div_option=1 - nsim_isa_fpu_mac_option=1 - nsim_isa_fpuda_option=1 - nsim_isa_fpu_fast_mpy_option=0 - nsim_isa_fpu_fast_div_option=0 - nsim_isa_bitstream_option=1 - nsim_isa_enable_timer_0=1 - nsim_isa_timer_0_int_level=1 - nsim_isa_enable_timer_1=1 - nsim_isa_timer_1_int_level=0 - nsim_isa_num_actionpoints=2 - nsim_isa_stack_checking=1 - nsim_isa_has_dmp_peripheral=1 - nsim_isa_smart_stack_entries=8 - nsim_isa_number_of_interrupts=20 - nsim_isa_number_of_levels=4 - nsim_isa_number_of_external_interrupts=16 - nsim_isa_fast_irq=1 - nsim_isa_intvbase_preset=0x0 - dcache=16384,32,2,a - nsim_isa_dc_feature_level=2 - icache=16384,32,2,a - nsim_isa_ic_feature_level=2 - dccm_size=0x80000 - dccm_base=0x80000000 - nsim_isa_dccm_interleave=1 - iccm0_size=0x80000 - iccm0_base=0x00000000 - nsim_isa_pct_counters=8 - nsim_isa_dmac_option=1 - nsim_isa_dmac_channels=2 - nsim_isa_dmac_registers=0 - nsim_isa_dmac_fifo_depth=2 - nsim_isa_dmac_int_config=single_internal diff --git a/board/ARC_NSIM_EM/TOS-CONFIG/tos_config.h b/board/ARC_NSIM_EM/TOS-CONFIG/tos_config.h deleted file mode 100644 index 99f8c5d3..00000000 --- a/board/ARC_NSIM_EM/TOS-CONFIG/tos_config.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef _TOS_CONFIG_H_ -#define _TOS_CONFIG_H_ - -#include "nsim.h" - -#define TOS_CFG_TASK_PRIO_MAX 10u - -#define TOS_CFG_ROUND_ROBIN_EN 0u - -#define TOS_CFG_OBJECT_VERIFY_EN 1u - -#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 1u - -#define TOS_CFG_EVENT_EN 1u - -#define TOS_CFG_MMBLK_EN 1u - -#define TOS_CFG_MMHEAP_EN 1u - -#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u - -#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x8000 - -#define TOS_CFG_MUTEX_EN 1u - -#define TOS_CFG_MESSAGE_QUEUE_EN 1u - -#define TOS_CFG_MAIL_QUEUE_EN 1u - -#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u - -#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 1u - -#define TOS_CFG_TIMER_EN 1u - -#define TOS_CFG_PWR_MGR_EN 0u - -#define TOS_CFG_TICKLESS_EN 0u - -#define TOS_CFG_SEM_EN 1u - -#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u - -#define TOS_CFG_FAULT_BACKTRACE_EN 0u - -#define TOS_CFG_IDLE_TASK_STK_SIZE 128u - -#define TOS_CFG_CPU_TICK_PER_SECOND 1000u - -#define TOS_CFG_CPU_CLOCK (CLK_CPU) - -#define TOS_CFG_TIMER_AS_PROC 1u - -#endif - diff --git a/board/ARC_NSIM_EM/GCC/hello_world/.project b/board/ARC_NSIM_EM/hello_world/.project similarity index 100% rename from board/ARC_NSIM_EM/GCC/hello_world/.project rename to board/ARC_NSIM_EM/hello_world/.project diff --git a/board/ARC_NSIM_EM/hello_world/.sc.project/.sc.project.windows b/board/ARC_NSIM_EM/hello_world/.sc.project/.sc.project.windows new file mode 100644 index 00000000..704db57b --- /dev/null +++ b/board/ARC_NSIM_EM/hello_world/.sc.project/.sc.project.windows @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/board/ARC_NSIM_EM/hello_world/.sc.project/.sc.project.xml b/board/ARC_NSIM_EM/hello_world/.sc.project/.sc.project.xml new file mode 100644 index 00000000..87374e27 --- /dev/null +++ b/board/ARC_NSIM_EM/hello_world/.sc.project/.sc.project.xml @@ -0,0 +1,5 @@ + + + + C:\Users\zhiwei\Desktop\embARC_Workspace\TencentOS\TencentOS-tiny\board\ARC_NSIM_EM\hello_world\.sc.project\.sc.project.windows + diff --git a/board/ARC_NSIM_EM/hello_world/.sc.project/.sc2.properties b/board/ARC_NSIM_EM/hello_world/.sc.project/.sc2.properties new file mode 100644 index 00000000..1579d6c3 --- /dev/null +++ b/board/ARC_NSIM_EM/hello_world/.sc.project/.sc2.properties @@ -0,0 +1,90 @@ +A6_mpu=1 +AC600_dcache=1 +AC600_icache=1 +AC_dcache=1 +AC_dcache_line_size=32 +AC_dcache_repalg=Random +AC_dcache_size=16384 +AC_dcache_ways=2 +AC_icache=1 +AC_icache_line_size=32 +AC_icache_repalg=Random +AC_icache_size=16384 +AC_icache_ways=2 +ACa7_dcache=1 +ACa7_icache=1 +ARC5_Core_Version=3 +ARC6_Core_Version=3 +ARC7_Core_Version=3 +ARC_DSP_memory=ARC_xy +ARC_agu=large +ARC_agu_accord=1 +ARC_agu_write=4 +ARC_barrel_shifter=1 +ARC_bitscan=1 +ARC_code_density=1 +ARC_dcache_feature=2 +ARC_dccm_interleave=1 +ARC_default_ext_interrupts=0 +ARC_default_interrupts=0 +ARC_div_rem=radix2 +ARC_dma=1 +ARC_dmac_channels=2 +ARC_dmac_fifo_depth=2 +ARC_dmac_int_config=single_internal +ARC_dmac_registers=0 +ARC_dsp2=1 +ARC_dsp_accshift=full +ARC_dsp_complex=1 +ARC_dsp_divsqrt=radix2 +ARC_dsp_itu=1 +ARC_ext_interrupt_num=16 +ARC_fast_interrupt=1 +ARC_fsfpus_div=Slow +ARC_fsfpus_mpy=Slow +ARC_icache_feature=2 +ARC_interrupt_baseaddr=0x0 +ARC_interrupt_num=20 +ARC_interrupt_priorities=4 +ARC_interrupt_vector_count=20 +ARC_mpu_region=16 +ARC_mpu_version=-mpu +ARC_mpy_emoption=mpyd +ARC_mpy_hsoption=mpyd +ARC_parallel_port_address=0x378 +ARC_pct_counters=8 +ARC_reset_on_restart=1 +ARC_rgf_num_wr_ports=2 +ARC_shift_assist=1 +ARC_smart_stack_entries=8 +ARC_swap=1 +ARC_target=ARCSIM +ARC_timer0=1 +ARC_timer0_level=1 +ARC_timer1=1 +ARC_timer1_level=0 +ARC_turbo_boost=1 +ARC_xy_config=dccm_y +ARC_xy_interleave=1 +ARC_xy_size=8K +ARC_xy_ybase=0xe0000000 +Execute_to_main=0 +Local_symbols=1 +Program_toggles_off=binary_stdin,binary_stdout,flush_pipe,cr_for_more +Program_toggles_on=load_at_paddr +cmd_line_option=-OKN -action_points\=2 -dmp_peripheral -OKN -action_points\=2 -dmp_peripheral -OKN -action_points\=2 -dmp_peripheral +dccm_base=0x80000000 +dccm_size=0x80000 +fpu_mac=1 +fpuda=1 +fpus_div=1 +hw_stack_checking=1 +iccm0_base=0x00000000 +iccm0_size=0x80000 +iss_av2_override=0 +program=build/TencentOS_tiny.elf +v2em_core_register_per_bank=32 +v2em_core_version=3 +v2em_regis_bank=2 +v2hs_core_version=3 +which_arc=ARCV2EM diff --git a/board/ARC_NSIM_EM/hello_world/Makefile b/board/ARC_NSIM_EM/hello_world/Makefile new file mode 100644 index 00000000..8a5ab471 --- /dev/null +++ b/board/ARC_NSIM_EM/hello_world/Makefile @@ -0,0 +1,269 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.3.0] date: [Mon Aug 05 10:29:11 CST 2019] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = TencentOS_tiny + +APPLICATION = hello_world + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -O0 + +TOP_DIR = ../../.. + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +####################################### +# embarc_bsp relative conifg +####################################### + +BOARD ?= nsim +BD_VER ?= 10 +CUR_CORE ?= arcem +TOOLCHAIN ?= mw +OLEVEL ?= O0 +OUT_DIR_ROOT ?= $(BUILD_DIR) + +export BOARD +export BD_VER +export CUR_CORE +export TOOLCHAIN +export OUT_DIR_ROOT +export OLEVEL + +EMBARC_BSP_ROOT = $(TOP_DIR)/platform/vendor_bsp/Synopsys/ARC/embarc_bsp + +EMBARC_BSP_TEST_FILE = $(EMBARC_BSP_ROOT)/arc/startup/arc_startup.s + +ifeq ($(wildcard $(EMBARC_BSP_TEST_FILE)),) +$(info ) +$(info ) +$(info ) +$(info ######################################################################################################) +$(info # #) +$(info # embarc_bsp not exist!!! #) +$(info # please git embarc_bsp from github #) +$(info # run cmd blew in folder /platform/vendor_bsp/Synopsys/ARC>: #) +$(info # git clone https://github.com/foss-for-synopsys-dwc-arc-processors/embarc_bsp.git -b upstream #) +$(info # #) +$(info ######################################################################################################) +$(info ) +$(info ) +$(info ) +$(error [Makefile.error]: embarc_bsp not exist!!!) +endif + +EMBARC_ROOT = $(EMBARC_BSP_ROOT) +export EMBARC_ROOT + +EMBARC_OUT_DIR = $(OUT_DIR_ROOT)/obj_$(BOARD)_$(BD_VER)/$(TOOLCHAIN)_$(CUR_CORE) + +ifeq ($(TOOLCHAIN),mw) +COMPILER_ARG_FILE := $(EMBARC_OUT_DIR)/embARC_generated/ccac.arg +LDF_FILE := $(EMBARC_OUT_DIR)/linker_mw.ldf +MDB_ARG_FILE := $(EMBARC_OUT_DIR)/embARC_generated/mdb.arg +else +COMPILER_ARG_FILE := $(EMBARC_OUT_DIR)/embARC_generated/gcc.arg +LDF_FILE := $(EMBARC_OUT_DIR)/linker_gnu.ldf +endif + +###################################### +# source +###################################### +# C sources +KERNEL_SRC = \ + ${wildcard $(TOP_DIR)/kernel/core/*.c} +C_SOURCES += $(KERNEL_SRC) + +ARCH_SRC = \ + ${wildcard $(TOP_DIR)/arch/arc/arcem/*.c} \ + ${wildcard $(TOP_DIR)/arch/arc/common/*.c} +C_SOURCES += $(ARCH_SRC) + +CMSIS_SRC = \ + ${wildcard $(TOP_DIR)/osal/cmsis_os/*.c} +C_SOURCES += $(CMSIS_SRC) + +APPLICATION_SRC = \ + ${wildcard $(TOP_DIR)/board/ARC_NSIM_EM/BSP/Src/*.c} \ + ${wildcard $(TOP_DIR)/examples/$(APPLICATION)/*.c} + +C_SOURCES += $(APPLICATION_SRC) + +# ASM sources +ASM_SOURCES = \ + $(TOP_DIR)/arch/arc/arcem/port_s.s + +ifeq ($(TOOLCHAIN),mw) +PREFIX = +CC = $(PREFIX)ccac +AS = $(PREFIX)ccac + +SZ = $(PREFIX)size + +OBJCOPY = $(PREFIX)elf2bin +ELF2HEX = $(PREFIX)elf2hex + +ELF2HEX_INOPT = -Q -I +ELF2HEX_OUTOPT = -o +ELF2BIN_OPT = +else + +endif + +####################################### +# CFLAGS +####################################### + +# C defines + +NSIM_STACK_CHECK := -DARC_FEATURE_STACK_CHECK=0 +# 1: enable hardware stack check, 0 disable hardware stack check + +ifeq ($(TOOLCHAIN),mw) +TOOLCHAIN_DEF := -D__MW__ +else +TOOLCHAIN_DEF := -D__GNU__ -D_HAVE_LIBGLOSS_ +endif + +C_DEFS = \ + $(TOOLCHAIN_DEF) \ + $(NSIM_STACK_CHECK) \ + -DBOARD_NSIM \ + -DCURRENT_CORE=$(CUR_CORE) \ + -DEMBARC_TCF_GENERATED \ + -DHW_VERSION=$(BD_VER) \ + -DLIB_CONSOLE \ + -DLIB_CLIB \ + -D_HEAPSIZE=8192 \ + -D_HOSTLINK_ \ + -D_NSIM_ \ + -D_STACKSIZE=2048 \ + -DARC_FEATURE_STACK_CHECK=0 + +# include dirs +ARCH_INC = \ + -I $(TOP_DIR)/arch/arc/arcem \ + -I $(TOP_DIR)/arch/arc/common/include +C_INCLUDES += $(ARCH_INC) + +BOARD_INC = \ + -I $(TOP_DIR)/board/ARC_NSIM_EM/BSP/Inc +C_INCLUDES += $(BOARD_INC) + +KERNEL_INC = \ + -I $(TOP_DIR)/kernel/core/include \ + -I $(TOP_DIR)/kernel/pm/include \ + -I $(TOP_DIR)/kernel/hal/include +C_INCLUDES += $(KERNEL_INC) + +CMSIS_INC = \ + -I $(TOP_DIR)/osal/cmsis_os +C_INCLUDES += $(CMSIS_INC) + +EMBARC_BSP_INC = \ + -I $(EMBARC_BSP_ROOT)/board \ + -I $(EMBARC_BSP_ROOT)/board/nsim/configs/10 \ + -I $(EMBARC_BSP_ROOT)/include \ + -I $(EMBARC_BSP_ROOT)/include/arc \ + -I $(EMBARC_BSP_ROOT)/include/device/designware \ + -I $(EMBARC_BSP_ROOT)/include/device/subsystem \ + -I $(EMBARC_BSP_ROOT)/library \ + -I $(EMBARC_OUT_DIR)/embARC_generated +C_INCLUDES += $(EMBARC_BSP_INC) + +ifeq ($(TOOLCHAIN),mw) +ASFLAGS = @$(COMPILER_ARG_FILE) -Hnoccm -Hnosdata -Wincompatible-pointer-types -Hnocopyr -Hasmcpp -$(OLEVEL) -g $(C_DEFS) $(C_INCLUDES) -MMD -MT $@ -MF $@.d + +CFLAGS = @$(COMPILER_ARG_FILE) -Hnoccm -Hnosdata -Wincompatible-pointer-types -Hnocopyr -Hnocplus -$(OLEVEL) -g $(C_DEFS) $(C_INCLUDES) -MMD -MT $@ -MF $@.d + +LDFLAGS = -Hhostlink @$(COMPILER_ARG_FILE) -Hnocopyr -Hnosdata -Hnocrt -Hldopt=-Coutput=$(BUILD_DIR)/mw_arcem.map -Hldopt=-Csections -Hldopt=-Ccrossfunc -Hldopt=-Csize -zstdout $(LDF_FILE) +else + +endif +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES_S:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES_S))) + +# EMBARC_PREBUILT_LIBRARY = -Hldopt=-Bgrouplib +EMBARC_PREBUILT_LIBRARY = $(EMBARC_OUT_DIR)/libembarc.a +# EMBARC_PREBUILT_LIBRARY += $(EMBARC_OUT_DIR)/board/board.o +# EMBARC_PREBUILT_LIBRARY += $(EMBARC_OUT_DIR)/arc/startup/arc_startup.o +# EMBARC_PREBUILT_LIBRARY += $(EMBARC_OUT_DIR)/arc/startup/arc_cxx_support.o +# EMBARC_PREBUILT_LIBRARY += $(EMBARC_OUT_DIR)/libboard_nsim.a +# EMBARC_PREBUILT_LIBRARY += $(EMBARC_OUT_DIR)/libcpuarc.a +# EMBARC_PREBUILT_LIBRARY += $(EMBARC_OUT_DIR)/libembarc_libc.a +# EMBARC_PREBUILT_LIBRARY += $(EMBARC_OUT_DIR)/libembarc_console.a + +build_embarc_lib: | $(BUILD_DIR) + make -f $(EMBARC_BSP_ROOT)/options/options.mk V=1 embarc_lib + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(ASFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(AS) -c $(ASFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: build_embarc_lib $(OBJECTS) Makefile + $(CC) $(LDFLAGS) $(OBJECTS) $(EMBARC_PREBUILT_LIBRARY) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(ELF2HEX) $(ELF2HEX_INOPT) $< $(ELF2HEX_OUTOPT) $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(OBJCOPY) $(ELF2BIN_OPT) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +nsim_debug : $(BUILD_DIR)/$(TARGET).elf + mdb -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim -off=binary_stdin -off=binary_stdout -on=load_at_paddr -on=reset_upon_restart -off=flush_pipe -off=cr_for_more -OKN @$(MDB_ARG_FILE) $< +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** \ No newline at end of file diff --git a/board/ARC_NSIM_EM/hello_world/mw.log b/board/ARC_NSIM_EM/hello_world/mw.log new file mode 100644 index 00000000..6a3d4eaf Binary files /dev/null and b/board/ARC_NSIM_EM/hello_world/mw.log differ diff --git a/examples/hello_world/hello_world.c b/examples/hello_world/hello_world.c index f68f2736..72445b2d 100644 --- a/examples/hello_world/hello_world.c +++ b/examples/hello_world/hello_world.c @@ -1,10 +1,10 @@ #include "cmsis_os.h" -#define TASK1_STK_SIZE 512 +#define TASK1_STK_SIZE 1024 void task1(void *arg); osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE); -#define TASK2_STK_SIZE 512 +#define TASK2_STK_SIZE 1024 void task2(void *arg); osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE); diff --git a/platform/vendor_bsp/Synopsys/ARC/embarc_bsp b/platform/vendor_bsp/Synopsys/ARC/embarc_bsp new file mode 160000 index 00000000..7595aae3 --- /dev/null +++ b/platform/vendor_bsp/Synopsys/ARC/embarc_bsp @@ -0,0 +1 @@ +Subproject commit 7595aae3c2cec9cd4f2b4fe4de60b7a625545345 diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_cache.c b/platform/vendor_bsp/embarc_bsp/arc/arc_cache.c deleted file mode 100644 index 456dccfd..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_cache.c +++ /dev/null @@ -1,403 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC_CACHE - * @brief Cache manipulation - * - * This module contains functions for manipulation caches. - */ - -#include "arc/arc_cache.h" - -struct cache_config { - uint8_t ver; /* Version */ - uint8_t assoc; /* Cache Associativity */ - uint16_t line; /* Cache line/block size */ - uint32_t capacity; /* Capacity */ -}; - -static struct cache_config icache_config, dcache_config; - -/** - * @brief Invalidate instruction cache lines - * - * @param start_addr Start address in instruction cache - * @param size Bytes to be invalidated - * @return 0, succeeded, -1, failed - */ -int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size) -{ - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - - if ((size == 0) || (size > icache_config.capacity)) { - return -1; - } - - line_size = (uint32_t)(icache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - arc_aux_write(AUX_IC_IVIL, start_addr); - arc_nop(); - arc_nop(); - arc_nop(); - start_addr += line_size; - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return 0; -} - -/** - * @brief Lock instruction cache lines - * - * @param start_addr Start address in instruction cache - * @param size Bytes to be locked - * @return 0, succeeded, -1, failed (cache already locked or other reasons) - */ -int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size) -{ - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - int32_t ercd = 0; - - if ((size == 0) || (size > icache_config.capacity)) { - return -1; - } - - line_size = (uint32_t)(icache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - arc_aux_write(AUX_IC_LIL, start_addr); - if (arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) { - start_addr += line_size; - } else { - ercd = -1; /* the operation failed */ - break; - } - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return ercd; -} - -#if ARC_FEATURE_ICACHE_FEATURE == 2 -/** - * @brief Directly write icache internal ram - * - * @param cache_addr Icache internal address(way+index+offset) - * @param tag Cache tag to write (tag+lock bit+valid bit) - * @param data Cache data to write - * @return 0, succeeded, -1, failed - */ -int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data) -{ - if (arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) { - return -1; - } - arc_aux_write(AUX_IC_RAM_ADDR, cache_addr); - arc_aux_write(AUX_IC_TAG, tag); - arc_aux_write(AUX_IC_DATA, data); - - return 0; -} - -/** - * @brief Directly read icache internal ram - * - * @param cache_addr Icache internal address(way+index+offset) - * @param tag Cache tag to read (tag+index+lock bit+valid bit) - * @param data Cache data to read - * @return 0, succeeded, -1, failed - */ -int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data) -{ - if (arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) { - return -1; - } - arc_aux_write(AUX_IC_RAM_ADDR, cache_addr); - *tag = arc_aux_read(AUX_IC_TAG); - *data = arc_aux_read(AUX_IC_DATA); - - return 0; -} - -/** - * @brief Indirectly read icache internal ram - * - * @param mem_addr Memory address - * @param tag Cache tag to read - * @param data Cache data to read - * @return 0, succeeded, -1, failed - */ -int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data) -{ - if (!(arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS)) { - return -1; - } - arc_aux_write(AUX_IC_RAM_ADDR, mem_addr); - if (arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) { - *tag = arc_aux_read(AUX_IC_TAG); - *data = arc_aux_read(AUX_IC_DATA); - } else { - return -1; /* the specified memory is not in icache */ - } - return 0; -} -#endif - -/** - * @brief Invalidate data cache lines - * - * @param start_addr Start address in data cache - * @param size Bytes to be invalidated - * @return 0, succeeded, -1, failed - */ -int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size) -{ - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - - if ((size == 0) || (size > dcache_config.capacity)) { - return -1; - } - - line_size = (uint32_t)(dcache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - arc_aux_write(AUX_DC_IVDL, start_addr); - arc_nop(); - arc_nop(); - arc_nop(); - /* wait for flush completion */ - while (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { - ; - } - start_addr += line_size; - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return 0; - -} - -/** - * @brief Flush data cache lines to memory - * - * @param start_addr Start address - * @param size Bytes to be flushed - * @return 0, succeeded, -1, failed - */ -int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size) -{ - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - - if ((size == 0) || (size > dcache_config.capacity)) { - return -1; - } - - line_size = (uint32_t)(dcache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - arc_aux_write(AUX_DC_FLDL, start_addr); - arc_nop(); - arc_nop(); - arc_nop(); - /* wait for flush completion */ - while (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { - ; - } - start_addr += line_size; - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return 0; -} - -/** - * @brief Lock data cache lines - * - * @param start_addr Start address in data cache - * @param size Bytes to be locked - * @return 0, succeeded, -1, failed - */ -int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size) -{ - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - int32_t ercd = 0; - - if ((size == 0) || (size > dcache_config.capacity)) { - return -1; - } - - line_size = (uint32_t)(dcache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - arc_aux_write(AUX_DC_LDL, start_addr); - arc_nop(); - if (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) { - start_addr += line_size; - } else { - ercd = -1; /* the operation failed */ - break; - } - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return ercd; -} - -/** - * @brief Directly write dcache internal ram - * - * @param cache_addr Dcache internal address(way+index+offset) - * @param tag Cache tag to write - * @param data Cache data to write - * @return 0, succeeded, -1, failed - */ -int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data) -{ - if (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) { - return -1; - } - - arc_aux_write(AUX_DC_RAM_ADDR, cache_addr); - arc_aux_write(AUX_DC_TAG, tag); - arc_aux_write(AUX_DC_DATA, data); - - return 0; -} - -/** - * @brief Directly read dcache internal ram - * - * @param cache_addr Dcache internal address(way+index+offset) - * @param tag Cache tag to read - * @param data Cache data to read - * @return 0, succeeded, -1, failed - */ -int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data) -{ - if (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) { - return -1; - } - - arc_aux_write(AUX_DC_RAM_ADDR, cache_addr); - *tag = arc_aux_read(AUX_DC_TAG); - *data = arc_aux_read(AUX_DC_DATA); - - return 0; -} - -/** - * @brief Indirectly read dcache internal ram - * - * @param mem_addr Memory address(tag+index+offset) - * @param tag Cache tag to read - * @param data Cache data to read - * @return 0, succeeded, -1, failed - */ -int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data) -{ - if (!(arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS)) { - return -1; - } - - arc_aux_write(AUX_DC_RAM_ADDR, mem_addr); - if (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) { - *tag = arc_aux_read(AUX_DC_TAG); - *data = arc_aux_read(AUX_DC_DATA); - } else { - return -1; /* the specified memory is not in dcache */ - } - - return 0; -} - -/** - * @brief Initialize cache - * 1. invalidate icache and dcache - * 2. Only support ARCv2 cache - */ -void arc_cache_init(void) -{ - uint32_t build_cfg; - - build_cfg = arc_aux_read(AUX_BCR_D_CACHE); - - dcache_config.ver = build_cfg & 0xff; - - if (dcache_config.ver >= 0x04) { /* ARCv2 */ - dcache_enable(DC_CTRL_DISABLE_FLUSH_LOCKED | - DC_CTRL_INDIRECT_ACCESS | DC_CTRL_INVALID_FLUSH); - dcache_invalidate(); - dcache_config.assoc = 1 << ((build_cfg >> 8) & 0xf); - dcache_config.capacity = 512 << ((build_cfg >> 12) & 0xf); - dcache_config.line = 16 << ((build_cfg >> 16) & 0xf); - } - - build_cfg = arc_aux_read(AUX_BCR_I_CACHE); - - icache_config.ver = build_cfg & 0xff; - - if (icache_config.ver >= 0x04) { /* ARCv2 */ - icache_config.assoc = 1 << ((build_cfg >> 8) & 0xf); - icache_config.capacity = 512 << ((build_cfg >> 12) & 0xf); - icache_config.line = 8 << ((build_cfg >> 16) & 0xf); - - icache_enable(IC_CTRL_IC_ENABLE); - icache_invalidate(); - } - -} diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_connect.c b/platform/vendor_bsp/embarc_bsp/arc/arc_connect.c deleted file mode 100644 index ad08a7b7..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_connect.c +++ /dev/null @@ -1,964 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC_CONNECT - * @brief ar connect driver - * - * This module contains functions for arc connect module. - */ - -#include "arc/arc_connect.h" -#include "arc/arc_mp.h" - -static ARC_SPINLOCK_T arc_connect_lock; - -/** - * @brief Execute arc connect command - * - * @param op Pointer to arc connect operation - * @return Result of arc connect command - */ -static uint32_t arc_connect_cmd_execute(ARC_CONNECT_OP_T *op) -{ - uint32_t regval = 0; - - if (!op) { - return 0; - } - - regval = op->cmd | ((op->param) << 8); - - arc_spinlock_get(&arc_connect_lock); - - switch (op->type) { - case ARC_CONNECT_CMD_TYPE_CMD_ONLY: - arc_aux_write(AUX_CONNECT_CMD, regval); - break; - case ARC_CONNECT_CMD_TYPE_CMD_RETURN: - arc_aux_write(AUX_CONNECT_CMD, regval); - break; - case ARC_CONNECT_CMD_TYPE_CMD_WDATA: - arc_aux_write(AUX_CONNECT_WDATA, op->wdata); - arc_aux_write(AUX_CONNECT_CMD, regval); - break; - case ARC_CONNECT_CMD_TYPE_CMD_WDATA_RETURN: - arc_aux_write(AUX_CONNECT_WDATA, op->wdata); - arc_aux_write(AUX_CONNECT_CMD, regval); - break; - default: - break; - } - - regval = arc_aux_read(AUX_CONNECT_READBACK); - - arc_spinlock_release(&arc_connect_lock); - - return regval; -} - -/** - * @brief Get the core id in arc connect - * - * @return Core id - */ -uint32_t arc_connect_check_core_id(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_CHECK_CORE_ID, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Enable interrupt distribute unit - * - */ -void arc_connect_idu_enable(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_IDU_ENABLE, 0); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief Disable interrupt distribute unit - * - */ -void arc_connect_idu_disable(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_IDU_DISABLE, 0); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief Read interrupt distribute enable status - * - * @return Enable status - */ -uint32_t arc_connect_idu_read_enable(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_IDU_READ_ENABLE, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Set the mode of irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @param trigger_mode Trigger mode, level or pulse - * @param distri_mode Distribute mode - */ -void arc_connect_idu_set_mode(uint32_t irq_num, uint16_t trigger_mode, uint16_t distri_mode) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_IDU_SET_MODE, \ - irq_num, (distri_mode | (trigger_mode << 4))); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief Read the mode of irq connected to idu - * - * @param irq_num Number of irq connected to idu - * - */ -uint32_t arc_connect_idu_read_mode(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_IDU_READ_ENABLE, irq_num); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Set the target core to handle the irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @param target_core Target core - */ -void arc_connect_idu_set_dest(uint32_t irq_num, uint32_t target_core) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_IDU_SET_DEST, irq_num, target_core); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief Read the target core to handle the irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @return Target core - */ -uint32_t arc_connect_idu_read_dest(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_IDU_READ_DEST, irq_num); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Generate the irq connected to idu in software - * - * @param irq_num Number of irq connected to idu - */ -void arc_connect_idu_gen_cirq(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_IDU_GEN_CIRQ, irq_num); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief Acknowledge irq connected to idu - * - * @param irq_num Number of irq connected to idu - */ -void arc_connect_idu_ack_cirq(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_IDU_ACK_CIRQ, irq_num); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief Check the status of irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @return Status of irq connected to idu - */ -uint32_t arc_connect_idu_check_status(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_IDU_CHECK_STATUS, irq_num); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Check the source of irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @return Source of irq connected to idu - */ -uint32_t arc_connect_idu_check_source(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_IDU_CHECK_SOURCE, irq_num); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Set the interrupt mask of irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @param mask Interrupt mask - */ -void arc_connect_idu_set_mask(uint32_t irq_num, uint32_t mask) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_IDU_SET_MASK, irq_num, mask); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief Read the interrupt mask of irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @return Interrupt mask - */ -uint32_t arc_connect_idu_read_mask(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_IDU_READ_MASK, irq_num); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Check the first core to handle the irq connected to idu - * - * @param irq_num Number of irq connected to idu - * @return Core number - */ -uint32_t arc_connect_idu_check_first(uint32_t irq_num) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_IDU_CHECK_FIRST, irq_num); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief Configure the irq connected to idu - * - * @param core Target core to handle the irq - * @param irq_num Number of irq connected to idu - * @param trigger_mode Trigger mode - * @param distri_mode Distribute mode - */ -void arc_connect_idu_config_irq(uint32_t core, uint32_t irq_num, uint16_t trigger_mode, uint16_t distri_mode) -{ - arc_connect_idu_disable(); - arc_connect_idu_set_mode(irq_num, trigger_mode, distri_mode); - arc_connect_idu_set_dest(irq_num, core); - arc_connect_idu_set_mask(irq_num, 0x0); - arc_connect_idu_enable(); -} - -/** - * @brief generate inter-core interrupt - * the calling core will raise an interrupt to the target core - * @param core_id the target core - */ -void arc_connect_ici_generate(uint32_t core_id) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ, core_id); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief acknowledge the raised inter-core interrupt - * - * @param core_id the core rasing the inter-core interrupt - */ -void arc_connect_ici_ack(uint32_t core_id) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_INTRPT_GENERATE_ACK, core_id); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the status of inter-core interrupt - * - * @param core_id the target core - * @return 1 the inter-core interrupt is pending, 0 the inter-core interrupt - * is acknowledged - */ -uint32_t arc_connect_ici_read_status(uint32_t core_id) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_INTRPT_READ_STATUS, core_id); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief check the source of inter-core interrupt - * - * @return the source of inter-core interrupt - */ -uint32_t arc_connect_ici_check_src(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief taka a inter-core semaphore - * - * @param sem_id semaphore id - * @return 0 failed, 1 success - */ -uint32_t arc_connect_ics_take(uint32_t sem_id) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_SEMA_CLAIM_AND_READ, sem_id); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief release a inter-core semaphore - * - * @param sem_id semaphore id - */ -void arc_connect_ics_release(uint32_t sem_id) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_SEMA_RELEASE, sem_id); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief compulsively release and make available a semaphore - * - * @param sem_id semaphore id - */ -void arc_connect_ics_force_release(uint32_t sem_id) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_SEMA_FORCE_RELEASE, sem_id); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief set the address of message-passing sram for subsequent read or - write sram operations - * - * @param addr sram address - */ -void arc_connect_icm_addr_set(uint32_t addr) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR, addr); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the value of internal MSG_ADDR reg - * - * @return value of MSG_ADDR reg - */ -uint32_t arc_connect_icm_addr_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief set the offset address of message-passing sram for subsequent read or - write sram operations - * - * @param offset address offset - */ -void arc_connect_icm_addr_offset_set(uint32_t offset) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR_OFFSET, offset); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the value of address offset reg - * - * @return value of address offset reg - */ -uint32_t arc_connect_icm_addr_offset_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR_OFFSET, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief write data to the message-passing sram - * - * @param data data to write - */ -void arc_connect_icm_msg_write(uint32_t data) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_WRITE, 0, data); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief incremental write to the message-passing sram - * - * @param data data to write - */ -void arc_connect_icm_msg_inc_write(uint32_t data) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_WRITE_INC, 0, data); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief write data into the message passing sram with the address - * specified by an immediate value. - * - * @param addr the specified address - * @param data data to write - */ -void arc_connect_icm_msg_imm_write(uint32_t addr, uint32_t data) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_WRITE_IMM, addr, data); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read data from the message passing sram - * - * @return read data - */ -uint32_t arc_connect_icm_msg_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_READ, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief incremental read data from the message passing sram - * - * @return read data - */ -uint32_t arc_connect_icm_msg_inc_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_READ_INC, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief read data at the specified address from the message passing sram - * - * @param addr the specified address - * @return read data - */ -uint32_t arc_connect_icm_msg_imm_read(uint32_t addr) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_READ_IMM, addr); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief enable or disable ECC or parity protection on the message data - * - * @param val 0 = enable protection, 1= disable protection - */ -void arc_connect_icm_ecc_ctrl_set(uint32_t val) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_SET_ECC_CTRL, 0, val); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the status ofECC or parity protection on the message data - * - * @return 0 = enable protection, 1= disable protection - */ -uint32_t arc_connect_icm_ecc_ctrl_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_MSG_SRAM_READ_ECC_CTRL, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief generate reset request to cores in the system. - * - * @param cores the target cores - */ -void arc_connect_debug_reset(uint32_t cores) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_RESET, 0, cores); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief generate halt request to cores in the system. - * - * @param cores the target cores - */ -void arc_connect_debug_halt(uint32_t cores) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_HALT, 0, cores); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief generate run request to cores in the system. - * - * @param cores the target cores - */ -void arc_connect_debug_run(uint32_t cores) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_RUN, 0, cores); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief set the internal MASK reg in ICD - * the MASK register determines whether a global halt is triggered - * if a core is halted in response to one of the following events: - * core halt, actionpoint halt, self-halt, and breakpoint halt - * @param cores the cores for which the MASK register should be updated - * @param mask mask bits - */ -void arc_connect_debug_mask_set(uint32_t cores, uint32_t mask) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_SET_MASK, mask, cores); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the internal MASK reg in ICD - * - * @param cores the cores for which the MASK register should be read - * @return mask bits - */ -uint32_t arc_connect_debug_mask_read(uint32_t cores) -{ - - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_RUN, 0, cores); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief select cores that should be halted if the core issuing the command is halted - * - * @param cores cores to select - */ -void arc_connect_debug_select_set(uint32_t cores) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_SET_SELECT, 0, cores); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief ead the internal SELECT register in ICD - * - * @return SELECT register value - */ -uint32_t arc_connect_debug_select_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_READ_SELECT, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief read the status, halt or run,of all cores - * - * @return bits: 1 running, 0 halted - */ -uint32_t arc_connect_debug_en_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_READ_EN, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief check the last command sent to ICD. - * - * @return ICD command - */ -uint32_t arc_connect_debug_cmd_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_READ_CMD, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief read the value of internal MCD_CORE register in ICD - * - * @return MCD_CORE register - */ -uint32_t arc_connect_debug_core_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_DEBUG_READ_CORE, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief clear the global free running counter - * - */ -void arc_connect_gfrc_clear(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_GFRC_CLEAR, 0); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read low 32-bit of gfrc - * - * @return low 32-bit of gfrc - */ -uint32_t arc_connect_gfrc_lo_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_GFRC_READ_LO, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief read high 32-bit of gfrc - * - * @return high 32-bit of gfrc - */ -uint32_t arc_connect_gfrc_hi_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_GFRC_READ_HI, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief enable gfrc - * - */ -void arc_connect_gfrc_enable(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_GFRC_ENABLE, 0); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief disable gfrc - * - */ -void arc_connect_gfrc_disable(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_ONLY_OP_SET(&op, ARC_CONNECT_CMD_GFRC_DISABLE, 0); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief set the relevant cores to halt the GFRC - * - * @param cores the relevant cores - */ -void arc_connect_gfrc_core_set(uint32_t cores) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_GFRC_SET_CORE, 0, cores); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the status of gfrc - * - * @return gfrc status - */ -uint32_t arc_connect_gfrc_halt_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_GFRC_READ_HALT, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief read the internal CORE register - * - * @return CORE register value - */ -uint32_t arc_connect_gfrc_core_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_GFRC_READ_CORE, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief set the power mode for specific ARConnect group - * - * @param group the ARConnect group - * @param cmd power mode - */ -void arc_connect_pdm_pm_set(uint32_t group, uint32_t cmd) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_PDM_SET_PM, group, cmd); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the internal PM register of the specified ARConnect group. - * - * @param group the ARConnect group - * @return status value - */ -uint32_t arc_connect_pdm_pdstatus_read(uint32_t group) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_PDM_READ_PSTATUS, group); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief set PUCNT - * - * @param cnt cnt to set - */ -void arc_connect_pmu_pucnt_set(uint32_t cnt) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_PMU_SET_PUCNT, 0, cnt); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read the PUNCNT - * - * @return PUNCNT's value - */ -uint32_t arc_connect_pmu_pucnt_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_PMU_READ_PUCNT, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief set RSTCNT - * - * @param cnt cnt to set - */ -void arc_connect_pmu_rstcnt_set(uint32_t cnt) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_PMU_SET_RSTCNT, 0, cnt); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read RSTCNT - * - * @return RSTCNT's value - */ -uint32_t arc_connect_pmu_rstcnt_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_PMU_READ_RSTCNT, 0); - - return arc_connect_cmd_execute(&op); -} - -/** - * @brief set PDCCNT - * - * @param cnt cnt to set - */ -void arc_connect_pmu_pdccnt_set(uint32_t cnt) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_WDATA_OP_SET(&op, ARC_CONNECT_CMD_PMU_SET_PDCNT, 0, cnt); - - arc_connect_cmd_execute(&op); -} - -/** - * @brief read PDCCNT - * - * @return PDCCNT's vaule - */ -uint32_t arc_connect_pmu_pdccnt_read(void) -{ - ARC_CONNECT_OP_T op; - - ARC_CONNECT_CMD_RETURN_OP_SET(&op, ARC_CONNECT_CMD_PMU_READ_PDCNT, 0); - - return arc_connect_cmd_execute(&op); -} diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_exc_asm.s b/platform/vendor_bsp/embarc_bsp/arc/arc_exc_asm.s deleted file mode 100644 index 3334c2e9..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_exc_asm.s +++ /dev/null @@ -1,159 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_EXCEPTION_CPU - * @brief Assembly part of exception and interrupt processing - */ - -/** - * @addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - */ - -/* function documentation */ -/** - * @fn void exc_entry_cpu(void) - * @brief Default entry of CPU exceptions, such as TLB miss and swap. - * - * @fn void exc_entry_int(void) - * @brief Normal interrupt exception entry. - * In default, all interrupt exceptions are installed with normal entry. - * If FIRQ is required, exc_entry_firq should be the entry. - * - * @fn void exc_entry_firq(void) - * @brief firq exception entry - */ -/** }@ */ - -/** @cond EXCEPTION_ASM */ - -#define __ASSEMBLY__ -#include "arc/arc.h" -#include "arc/arc_asm_common.h" - - .file "arc_exc_asm.s" - -/****** entry for cpu exception handling *******/ - .text - .global exc_entry_cpu - .weak exc_entry_cpu - .align 4 -exc_entry_cpu: - - EXCEPTION_PROLOGUE - -/* find the exception cause */ - lr r0, [AUX_ECR] - lsr r0, r0, 16 - bmsk r0, r0, 7 - mov r1, exc_int_handler_table - ld.as r2, [r1, r0] - -/* jump to exception handler where interrupts are not allowed! */ - mov r0, sp - jl [r2] -exc_return: - - EXCEPTION_EPILOGUE - rtie - -/****** entry for normal interrupt exception handling ******/ - .global exc_entry_int - .weak exc_entry_int - .align 4 -exc_entry_int: -#if ARC_FEATURE_FIRQ == 1 -#if ARC_FEATURE_RGF_NUM_BANKS > 1 -/* check whether it is P0 interrupt */ - lr r0, [AUX_IRQ_ACT] - btst r0, 0 - bnz exc_entry_firq -#else - PUSH r10 - lr r10, [AUX_IRQ_ACT] - btst r10, 0 - POP r10 - bnz exc_entry_firq -#endif -#endif -/* save scratch regs */ - INTERRUPT_PROLOGUE - -/* critical area */ - lr r0, [AUX_IRQ_CAUSE] - mov r1, exc_int_handler_table -/* r2 = _kernel_exc_tbl + irqno *4 */ - ld.as r2, [r1, r0] - -/* for the case of software triggered interrupt */ - lr r3, [AUX_IRQ_HINT] - cmp r3, r0 - bne.d irq_hint_handled - xor r3, r3, r3 - sr r3, [AUX_IRQ_HINT] -irq_hint_handled: - -/* jump to interrupt handler */ - mov r0, sp - jl [r2] -int_return: - INTERRUPT_EPILOGUE - rtie - -/****** entry for fast irq exception handling ******/ - .global exc_entry_firq - .weak exc_entry_firq - .align 4 -exc_entry_firq: - SAVE_FIQ_EXC_REGS - - lr r0, [AUX_IRQ_CAUSE] - mov r1, exc_int_handler_table -/* r2 = _kernel_exc_tbl + irqno *4 */ - ld.as r2, [r1, r0] - -/* for the case of software triggered interrupt */ - lr r3, [AUX_IRQ_HINT] - cmp r3, r0 - bne.d firq_hint_handled - xor r3, r3, r3 - sr r3, [AUX_IRQ_HINT] -firq_hint_handled: -/* jump to interrupt handler */ - mov r0, sp - jl [r2] - -firq_return: - RESTORE_FIQ_EXC_REGS - rtie - -/** @endcond */ diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_exception.c b/platform/vendor_bsp/embarc_bsp/arc/arc_exception.c deleted file mode 100644 index 7292b02d..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_exception.c +++ /dev/null @@ -1,812 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT - * @brief ARC interrupt and exception handling - */ -#include "arc/arc_exception.h" -#include "arc/arc_cache.h" - -#define DBG_LESS -#include "embARC_debug.h" - -/** - * @addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - * @var EXC_ENTRY_T exc_entry_table - * @brief exception entry table - * - * Install exception entry table to ARC_AUX_INT_VECT_BASE in startup. - * According to ARCv2 ISA, vectors are fetched in instruction space and thus - * may be present in ICCM, Instruction Cache, or - * main memory accessed by instruction fetch logic. - * So it is put into a specific section .vector. - * - * Please note that the exc_entry_table maybe cached in ARC. Some functions is - * defined in .s files. - * - */ - -#ifdef CONFIG_ARC_EXCEPTION_DEBUG -/* For EV_ProtV, the numbering/semantics of the parameter are consistent across - * several codes, although not all combination will be reported. - * - * These codes and parameters do not have associated* names in - * the technical manual, just switch on the values in Table 6-5 - */ -static void dump_protv_access_err(uint32_t parameter) -{ - switch (parameter) { - case 0x1: - EMBARC_PRINTF("code protection scheme"); - break; - case 0x2: - EMBARC_PRINTF("stack checking scheme"); - break; - case 0x4: - EMBARC_PRINTF("MPU"); - break; - case 0x8: - EMBARC_PRINTF("MMU"); - break; - case 0x10: - EMBARC_PRINTF("NVM"); - break; - case 0x24: - EMBARC_PRINTF("Secure MPU"); - break; - case 0x44: - EMBARC_PRINTF("Secure MPU with SID mismatch"); - break; - default: - EMBARC_PRINTF("unknown parameter"); - break; - } -} - -static void dump_protv_exception(uint32_t cause, uint32_t parameter) -{ - switch (cause) { - case 0x0: - EMBARC_PRINTF("Instruction fetch violation: "); - dump_protv_access_err(parameter); - break; - case 0x1: - EMBARC_PRINTF("Memory read protection violation: "); - dump_protv_access_err(parameter); - break; - case 0x2: - EMBARC_PRINTF("Memory write protection violation: "); - dump_protv_access_err(parameter); - break; - case 0x3: - EMBARC_PRINTF("Memory read-modify-write violation: "); - dump_protv_access_err(parameter); - break; - case 0x10: - EMBARC_PRINTF("Normal vector table in secure memory"); - break; - case 0x11: - EMBARC_PRINTF("NS handler code located in S memory"); - break; - case 0x12: - EMBARC_PRINTF("NSC Table Range Violation"); - break; - default: - EMBARC_PRINTF("unknown cause"); - break; - } -} - -static void dump_machine_check_exception(uint32_t cause, uint32_t parameter) -{ - switch (cause) { - case 0x0: - EMBARC_PRINTF("double fault"); - break; - case 0x1: - EMBARC_PRINTF("overlapping TLB entries"); - break; - case 0x2: - EMBARC_PRINTF("fatal TLB error"); - break; - case 0x3: - EMBARC_PRINTF("fatal cache error"); - break; - case 0x4: - EMBARC_PRINTF("internal memory error on instruction fetch"); - break; - case 0x5: - EMBARC_PRINTF("internal memory error on data fetch"); - break; - case 0x6: - EMBARC_PRINTF("illegal overlapping MPU entries"); - if (parameter == 0x1) { - EMBARC_PRINTF(" (jump and branch target)"); - } - break; - case 0x10: - EMBARC_PRINTF("secure vector table not located in secure memory"); - break; - case 0x11: - EMBARC_PRINTF("NSC jump table not located in secure memory"); - break; - case 0x12: - EMBARC_PRINTF("secure handler code not located in secure memory"); - break; - case 0x13: - EMBARC_PRINTF("NSC target address not located in secure memory"); - break; - case 0x80: - EMBARC_PRINTF("uncorrectable ECC or parity error in vector memory"); - break; - default: - EMBARC_PRINTF("unknown cause"); - break; - } -} - -static void dump_privilege_exception(uint32_t cause, uint32_t parameter) -{ - switch (cause) { - case 0x0: - EMBARC_PRINTF("Privilege violation"); - break; - case 0x1: - EMBARC_PRINTF("disabled extension"); - break; - case 0x2: - EMBARC_PRINTF("action point hit"); - break; - case 0x10: - switch (parameter) { - case 0x1: - EMBARC_PRINTF("N to S return using incorrect return mechanism"); - break; - case 0x2: - EMBARC_PRINTF("N to S return with incorrect operating mode"); - break; - case 0x3: - EMBARC_PRINTF("IRQ/exception return fetch from wrong mode"); - break; - case 0x4: - EMBARC_PRINTF("attempt to halt secure processor in NS mode"); - break; - case 0x20: - EMBARC_PRINTF("attempt to access secure resource from normal mode"); - break; - case 0x40: - EMBARC_PRINTF("SID violation on resource access (APEX/UAUX/key NVM)"); - break; - default: - EMBARC_PRINTF("unknown parameter"); - break; - } - break; - case 0x13: - switch (parameter) { - case 0x20: - EMBARC_PRINTF("attempt to access secure APEX feature from NS mode"); - break; - case 0x40: - EMBARC_PRINTF("SID violation on access to APEX feature"); - break; - default: - EMBARC_PRINTF("unknown parameter"); - break; - } - break; - default: - EMBARC_PRINTF("unknown cause"); - break; - } -} - -static void dump_exception_info(uint32_t vector, uint32_t cause, uint32_t param) -{ - /* Names are exactly as they appear in Designware ARCv2 ISA - * Programmer's reference manual for easy searching - */ - switch (vector) { - case EXC_NO_RESET: - EMBARC_PRINTF("Reset"); - break; - case EXC_NO_MEM_ERR: - EMBARC_PRINTF("Memory Error"); - break; - case EXC_NO_INS_ERR: - EMBARC_PRINTF("Instruction Error"); - break; - case EXC_NO_MAC_CHK: - EMBARC_PRINTF("EV_MachineCheck: "); - dump_machine_check_exception(cause, param); - break; - case EXC_NO_TLB_MISS_I: - EMBARC_PRINTF("EV_TLBMissI"); - break; - case EXC_NO_TLB_MISS_D: - EMBARC_PRINTF("EV_TLBMissD"); - break; - case EXC_NO_PRO_VIO: - EMBARC_PRINTF("EV_ProtV: "); - dump_protv_exception(cause, param); - break; - case EXC_NO_PRI_VIO: - EMBARC_PRINTF("EV_PrivilegeV: "); - dump_privilege_exception(cause, param); - break; - case EXC_NO_SWI: - EMBARC_PRINTF("EV_SWI"); - break; - case EXC_NO_TRAP: - EMBARC_PRINTF("EV_Trap"); - break; - case EXC_NO_EXT: - EMBARC_PRINTF("EV_Extension"); - break; - case EXC_NO_DIV_ZER0: - EMBARC_PRINTF("EV_DivZero"); - break; - case EXC_NO_DC_ERR: - EMBARC_PRINTF("EV_DCError"); - break; - case EXC_NO_MAL_ALIGN: - EMBARC_PRINTF("EV_Misaligned"); - break; - case EXC_NO_VEC_UNIT: - EMBARC_PRINTF("EV_VecUnit"); - break; - default: - EMBARC_PRINTF("unknown exception vector"); - break; - } - - EMBARC_PRINTF("\n"); -} - -#endif /* CONFIG_ARC_EXCEPTION_DEBUG */ - -/** - * @ingroup ARC_HAL_EXCEPTION_CPU - * @brief Install default cpu exception handler - * @param p_excinf Pointer to the exception frame - */ -static void exc_handler_default(void *p_excinf) -{ - uint32_t excpt_cause_reg = 0; - uint32_t excpt_ret_reg = 0; - uint32_t exc_no = 0; - uint32_t exc_cause = 0; - uint32_t exc_param = 0; - - excpt_cause_reg = arc_aux_read(AUX_ECR); - excpt_ret_reg = arc_aux_read(AUX_ERRET); - exc_no = (excpt_cause_reg >> 16) & 0xff; - exc_cause = (excpt_cause_reg >> 8) & 0xff; - exc_param = (excpt_cause_reg >> 0) & 0xff; - - dbg_printf(DBG_LESS_INFO, "default cpu exception handler\r\n"); - dbg_printf(DBG_LESS_INFO, "exc_no:%d, last sp:0x%08x, ecr:0x%08x, eret:0x%08x\r\n", - exc_no, p_excinf, excpt_cause_reg, excpt_ret_reg); -#ifdef CONFIG_ARC_EXCEPTION_DEBUG - dump_exception_info(exc_no, exc_cause, exc_param); -#endif - -#ifndef EMBARC_UNIT_TEST - arc_kflag(1); -#endif -} - -/** - * @ingroup ARC_HAL_EXCEPTION_INTERRUPT - * @brief Register default interrupt handler - * @param p_excinf Information for interrupt handler - */ -static void int_handler_default(void *p_excinf) -{ - uint32_t int_cause_reg = 0; - - int_cause_reg = arc_aux_read(AUX_IRQ_CAUSE); - dbg_printf(DBG_LESS_INFO, "default interrupt handler\r\n"); - dbg_printf(DBG_LESS_INFO, "last sp:0x%08x, icause:0x%08x\r\n", p_excinf, int_cause_reg); - arc_kflag(1); -} - -/* Enforcement of 1024 byte alignment */ -__attribute__ ((aligned(1024), section(".vector"))) - -/** - * @cond Doxygen_Suppress - */ -EXC_ENTRY_T exc_entry_table[NUM_EXC_ALL] = { [0] = exc_entry_reset, - [1 ... NUM_EXC_CPU - 1] = exc_entry_cpu, - [NUM_EXC_CPU ... NUM_EXC_ALL - 1] = exc_entry_int -}; -/** - * @var EXC_HANDLER_T exc_int_handler_table - * @brief CPU exception and interrupt exception handler table - * called in exc_entry_default and exc_entry_int - */ -EXC_HANDLER_T exc_int_handler_table[NUM_EXC_ALL] = { - [0 ... NUM_EXC_CPU - 1] = exc_handler_default, - [NUM_EXC_CPU ... NUM_EXC_ALL - 1] = int_handler_default -}; - -/** - * @endcond - */ -typedef struct { - /* note: little endian */ - uint32_t save_nr_gpr_pairs : 5; /** Indicates number of general-purpose register pairs saved, from 0 to 8/16 */ - uint32_t res : 4; /** Reserved */ - uint32_t save_blink : 1; /** Indicates whether to save and restore BLINK */ - uint32_t save_lp_regs : 1; /** Indicates whether to save and restore loop registers (LP_COUNT, LP_START, LP_END) */ - uint32_t save_u_to_u : 1; /** Indicates if user context is saved to user stack */ - uint32_t res2 : 1; /** Reserved */ - uint32_t save_idx_regs : 1; /** Indicates whether to save and restore code-density registers (EI_BASE, JLI_BASE, LDI_BASE) */ - uint32_t res3 : 18; /** Reserved */ -} AUX_IRQ_CTRL_FIELD_T; - -typedef union { - AUX_IRQ_CTRL_FIELD_T bits; - uint32_t value; -} AUX_IRQ_CTRL_T; - -extern uint8_t _f_stack[]; -/** - * @ingroup ARC_HAL_EXCEPTION_INTERRUPT - * @brief Initialize the exception and interrupt handling - */ -void exc_int_init(void) -{ - uint32_t i; - uint32_t status; - AUX_IRQ_CTRL_T ictrl; - - ictrl.value = 0; - -#ifndef ARC_FEATURE_RF16 - ictrl.bits.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ -#else - ictrl.bits.save_nr_gpr_pairs = 3; /* r0 to r3, r10, r11 */ -#endif - ictrl.bits.save_blink = 1; - ictrl.bits.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ - ictrl.bits.save_u_to_u = 0; /* user ctxt saved on kernel stack */ - -#if ARC_FEATURE_CODE_DENSITY - ictrl.bits.save_idx_regs = 1; /* JLI, LDI, EI */ -#endif - - status = arc_lock_save(); - for (i = NUM_EXC_CPU; i < NUM_EXC_ALL; i++) { - /* interrupt level triggered, disabled, priority is the lowest */ - arc_aux_write(AUX_IRQ_SELECT, i); - arc_aux_write(AUX_IRQ_ENABLE, 0); - arc_aux_write(AUX_IRQ_TRIGGER, 0); -#if defined(ARC_FEATURE_SEC_PRESENT) - arc_aux_write(AUX_IRQ_PRIORITY, (1 << AUX_IRQ_PRIORITY_BIT_S)|(INT_PRI_MAX - INT_PRI_MIN)); -#else - arc_aux_write(AUX_IRQ_PRIORITY, INT_PRI_MAX - INT_PRI_MIN); -#endif - } - arc_aux_write(AUX_IRQ_CTRL, ictrl.value); - - arc_unlock_restore(status); - - /** ipm should be set after cpu unlock restore to avoid reset of the status32 value */ - arc_int_ipm_set((INT_PRI_MAX - INT_PRI_MIN)); - -#if ARC_FEATURE_RGF_BANKED_REGS >= 16 && ARC_FEATURE_FIRQ == 1 -#if _STACKSIZE < 512 -#error "not enough stack size for irq and firq" -#endif - /* top 256 bytes of stack used as firq stack */ - arc_firq_stack_set(_f_stack + 256); -#endif -} - -/** - * @ingroup ARC_HAL_EXCEPTION_CPU - * @brief Install a CPU exception entry - * @param excno Exception number - * @param entry Exception entry to install - */ -int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY_T entry) -{ - uint32_t status; - EXC_ENTRY_T *table; - -#if defined(ARC_FEATURE_SEC_PRESENT) - table = (EXC_ENTRY_T *)arc_aux_read(AUX_INT_VECT_BASE_S); -#else - table = (EXC_ENTRY_T *)arc_aux_read(AUX_INT_VECT_BASE); -#endif - - if (excno < NUM_EXC_ALL && entry != NULL - && table[excno] != entry) { - status = cpu_lock_save(); - /* directly write to mem, as arc gets exception handler from mem not from cache */ - /* FIXME, here maybe icache is dirty, need to be invalidated */ - table[excno] = entry; - - if (arc_aux_read(AUX_BCR_D_CACHE) > 0x2) { - /* dcache is available */ - dcache_flush_line((uint32_t)&table[excno]); - } - - if (arc_aux_read(AUX_BCR_D_CACHE) > 0x2) { - /* icache is available */ - icache_invalidate_line((uint32_t)&table[excno]); - } - cpu_unlock_restore(status); - return 0; - } - return -1; -} - -/** - * @ingroup ARC_HAL_EXCEPTION_CPU - * @brief Get the installed CPU exception entry - * @param excno Exception number - * @return The installed CPU exception entry - */ -EXC_ENTRY_T exc_entry_get(const uint32_t excno) -{ - if (excno < NUM_EXC_ALL) { - return exc_entry_table[excno]; - } - return NULL; -} - -/** - * @ingroup ARC_HAL_EXCEPTION_CPU - * @brief Install an exception handler - * @param excno Exception number - * @param handler The installed CPU exception handler - */ -int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER_T handler) -{ - if (excno < NUM_EXC_ALL && handler != NULL) { - exc_int_handler_table[excno] = handler; - return 0; - } - - return -1; -} - -/** - * @ingroup ARC_HAL_EXCEPTION_CPU - * @brief Get the installed exception handler - * @param excno Exception number - * @return The installed exception handler or NULL - */ -EXC_HANDLER_T exc_handler_get(const uint32_t excno) -{ - if (excno < NUM_EXC_ALL) { - return exc_int_handler_table[excno]; - } - - return NULL; -} - -#ifndef EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT -/** - * @brief Disable interrupt - * - * @param intno Interrupt number - */ -int32_t int_disable(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_disable(intno); - return 0; - } - - return -1; -} - -/** - * @brief Enable interrupt - * - * @param intno Interrupt number - */ -int32_t int_enable(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_enable(intno); - return 0; - } - - return -1; -} - -/** - * @brief Get interrupt enable state - * - * @param intno Interrupt number - * @return 0 disabled, 1 enabled, < 0 error - */ -int32_t int_enabled(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_aux_write(AUX_IRQ_SELECT, intno); - return arc_aux_read(AUX_IRQ_ENABLE); - } - - return -1; -} - -/** - * @brief Get interrupt priority masking threshold - * - * @returns Interrupt priority masking threshold, negative num - */ -int32_t int_ipm_get(void) -{ - return ((int32_t)arc_int_ipm_get() + INT_PRI_MIN); -} - -/** - * @brief Set interrupt priority masking threshold - * - * @param intpri Interrupt priority masking threshold - */ -int32_t int_ipm_set(int32_t intpri) -{ - if (intpri >= INT_PRI_MIN && intpri <= INT_PRI_MAX) { - arc_int_ipm_set(intpri - INT_PRI_MIN); - return 0; - } - - return -1; -} - -/** - * @brief Get current interrupt priority masking threshold - * - * @param intno Interrupt number - * @return < 0 interrupt priority, 0 error - */ -int32_t int_pri_get(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - return (int32_t)arc_int_pri_get(intno) + INT_PRI_MIN; - } - - return 0; -} - -/** - * @brief Set interrupt priority - * - * @param intno Interrupt number - * @param intpri Interrupt priority - * @return < 0 error, 0 ok - */ -int32_t int_pri_set(const uint32_t intno, int32_t intpri) -{ - uint32_t status; - - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - status = cpu_lock_save(); - intpri = intpri - INT_PRI_MIN; - arc_int_pri_set(intno, (uint32_t)intpri); - cpu_unlock_restore(status); - return 0; - } - return -1; -} - -/** - * @brief Set interrupt secure or not secure - * @param intno Interrupt number - * @param secure 0 for normal, > 0 for secure - * @return < 0 error, 0 ok - */ -int32_t int_secure_set(const uint32_t intno, uint32_t secure) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_secure_set(intno, secure); - return 0; - } - return -1; - -} - -/** - * @brief Probe interrupt pending state - * - * @param intno Interrupt number - * - * @returns 1 pending, 0 no pending, -1 error - */ -int32_t int_probe(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - return arc_int_probe(intno); - } - return -1; -} - -/** - * @brief Trigger interrupt through software - * - * @param intno Interrupt number - * @return 0 ok, -1 error - */ -int32_t int_sw_trigger(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_sw_trigger(intno); - return 0; - } - return -1; -} - -/** - * @brief Configure interrupt trigger mode - * - * @param intno Interrupt number - * @param level 0-level triggered, 1-pulse triggered - * @return 0 ok, -1 error - */ -int32_t int_level_config(const uint32_t intno, const uint32_t level) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_level_config(intno, level); - return 0; - } - return -1; -} - -/** - * \brief Get interrupt request mode - * - * @param intno Interrupt number - */ -int32_t int_level_get(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - return (int32_t)arc_int_level_get(intno); - } - return -1; -} - -/** - * @brief lock cpu, disable interrupts - */ -void cpu_lock(void) -{ - arc_lock(); -} - -/** - * @brief Unlock cpu to enable interrupts - */ -void cpu_unlock(void) -{ - arc_unlock(); -} - -/** - * @brief Lock cpu and return status - * - * @returns CPU status - */ -uint32_t cpu_lock_save(void) -{ - return arc_lock_save(); -} - -/** - * @brief Unlock cpu with the specific status - * - * @param status CPU status saved by cpu_lock_save - */ -void cpu_unlock_restore(const uint32_t status) -{ - arc_unlock_restore(status); -} - -/** - * @ingroup ARC_HAL_EXCEPTION_INTERRUPT - * @brief Install interrupt handler - * @param intno Interrupt number - * @param handler Interrupt handler - */ -int32_t int_handler_install(const uint32_t intno, INT_HANDLER_T handler) -{ - /*!< @todo parameter check ? */ - if (intno >= NUM_EXC_CPU) { - return exc_handler_install(intno, handler); - } - - return -1; -} - -/** - * @ingroup ARC_HAL_EXCEPTION_INTERRUPT - * @brief Get the installed interrupt handler - * @param intno Interrupt number - * @return The installed interrupt handler or NULL - */ -INT_HANDLER_T int_handler_get(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU) { - return exc_handler_get(intno); - } - - return NULL; -} - -#endif /* EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT */ - -/** - * @brief Set the stack pointer for firq handling - * - * @param firq_sp stack pointer - */ -void arc_firq_stack_set(uint8_t *firq_sp) -{ - uint32_t status; - - if (firq_sp == NULL) { - return; - } - - status = arc_lock_save(); - - Asm( -/* only ilink will not be banked, so use ilink as channel - * between 2 banks - */ - "mov %%ilink, %0 \n\t" - "lr %0, [%1] \n\t" - "or %0, %0, %2 \n\t" - "kflag %0 \n\t" - "mov %%sp, %%ilink \n\t" -/* switch back to bank0, use ilink to avoid the pollution of - * bank1's gp regs. - */ - "lr %%ilink, [%1] \n\t" - "and %%ilink, %%ilink, %3 \n\t" - "kflag %%ilink \n\t" - : - : "r" (firq_sp), "i" (AUX_STATUS32), - "i" (AUX_STATUS_RB(1)), - "i" (~AUX_STATUS_RB(7)) - ); - - arc_unlock_restore(status); -} -/** @} end of group ARC_HAL_EXCEPTION_CPU */ diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_mp.c b/platform/vendor_bsp/embarc_bsp/arc/arc_mp.c deleted file mode 100644 index 9154491f..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_mp.c +++ /dev/null @@ -1,89 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "arc/arc_mp.h" - -static volatile struct { - void (*fn)(uint32_t, void *); - void *arg; -} arc_cpu_init[ARC_FEATURE_MP_NUM_CPUS]; - -/* - * arc_cpu_wake_flag is used to sync up master core and slave cores - * Slave core will spin for arc_cpu_wake_flag until master core sets - * it to the core id of slave core. Then, slave core clears it to notify - * master core that it's waken - * - */ -volatile uint32_t arc_cpu_wake_flag; - -volatile uint8_t *arc_cpu_sp; - -/** - * @brief Start slave cpu - * master core call this function to start slave cpu - * @param cpu_num Slave cpu number - * @param stack The pointer to stack area of slave cpu - * @param sz Stack size - * @param fn Function that slave cpu execute - * @param arg Argument for slave cpu - */ -void arc_start_slave_cpu(uint32_t cpu_num, uint8_t *stack, uint32_t sz, - void (*fn)(uint32_t, void *), void *arg) -{ - arc_cpu_init[cpu_num].fn = fn; - arc_cpu_init[cpu_num].arg = arg; - - /* set the initial sp of target sp through arc_cpu_sp - * arc_cpu_wake_flag will protect arc_cpu_sp that - * only one slave cpu can read it per time - */ - arc_cpu_sp = stack + sz; - - arc_cpu_wake_flag = cpu_num; - - /* wait slave cpu to start */ - while (arc_cpu_wake_flag != 0) { - ; - } -} - -/** - * @brief The C entry of slave cpu - * - * @param cpu_num Slave cpu id - */ -void arc_slave_start(uint32_t cpu_num) -{ - void (*fn)(uint32_t, void *); - - fn = arc_cpu_init[cpu_num].fn; - - fn(cpu_num, arc_cpu_init[cpu_num].arg); -} diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_mpu.c b/platform/vendor_bsp/embarc_bsp/arc/arc_mpu.c deleted file mode 100644 index d3dceafe..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_mpu.c +++ /dev/null @@ -1,198 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "arc/arc_mpu.h" - -#define CALC_REGION_END_ADDR(start, size) \ - (start + size - (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS)) - -/** - * @brief Enable the memory protection unit - * - */ -void arc_mpu_enable(void) -{ -#if ARC_FEATURE_MPU_VERSION == 2 - arc_aux_write(AUX_MPU_EN, arc_aux_read(AUX_MPU_EN) | AUX_MPU_EN_ENABLE); -#elif ARC_FEATURE_MPU_VERSION == 4 - arc_mpu_default(0); -#endif -} - -/** - * @brief Disable the memory protection unit - * - */ -void arc_mpu_disable(void) -{ -#if ARC_FEATURE_MPU_VERSION == 2 - arc_aux_write(AUX_MPU_EN, arc_aux_read(AUX_MPU_EN) & AUX_MPU_EN_DISABLE); -#elif ARC_FEATURE_MPU_VERSION == 4 - arc_mpu_default(ARC_MPU_REGION_ALL_ATTR | AUX_MPU_ATTR_S | AUX_MPU_ATTR_SID(1)); -#endif -} - -/** - * @brief Configure the given mpu region - * - * @param index Region index to be configured - * @param base Base address for the region - * @param size Region size of the region to be configured - * @param region_attr Attribute value of mpu region - */ -void arc_mpu_region_config(uint32_t index, uint32_t base, uint32_t size, uint32_t region_attr) -{ - if (index >= ARC_FEATURE_MPU_REGIONS) { - return; - } - - region_attr &= AUX_MPU_ATTR_MASK; - - /* ARC MPU version 2 and version 3 have different aux reg interface */ -#if ARC_FEATURE_MPU_VERSION == 2 - uint8_t bits = arc_find_msb(size) - 1; - - if (bits < ARC_FEATURE_MPU_ALIGNMENT_BITS) { - bits = ARC_FEATURE_MPU_ALIGNMENT_BITS; - } - - if ((1 << bits) < size) { - bits++; - } - - if (size > 0) { - region_attr |= AUX_MPU_RDP_REGION_SIZE(bits); - base |= AUX_MPU_VALID_MASK; - } else { - base = 0; - } - - arc_aux_write(2 * index + AUX_MPU_RDP0, region_attr); - arc_aux_write(2 * index + AUX_MPU_RDB0, base); - -#elif ARC_FEATURE_MPU_VERSION == 4 - if (size < (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS)) { - size = (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS); - } - - if (region_attr) { - region_attr |= AUX_MPU_VALID_MASK; - } - - arc_aux_write(AUX_MPU_INDEX, index); - arc_aux_write(AUX_MPU_RSTART, base); - arc_aux_write(AUX_MPU_REND, CALC_REGION_END_ADDR(base, size)); - arc_aux_write(AUX_MPU_RPER, region_attr); -#endif -} - -/** - * @brief Set default attribute of mpu region - * - * @param region_attr Attribute value - */ -void arc_mpu_default(uint32_t region_attr) -{ - uint32_t val = arc_aux_read(AUX_MPU_EN) & - (~AUX_MPU_ATTR_MASK); - - arc_aux_write(AUX_MPU_EN, (region_attr & AUX_MPU_ATTR_MASK) | val); -} - -/** - * @brief Check whether [start, start+size] in the given mpu region - * - * @param index Region index - * @param start Start address of memory - * @param size Size of memory - * @return 1 in the given mpu region, 0 not in - */ -int32_t arc_mpu_in_region(uint32_t index, uint32_t start, uint32_t size) -{ -#if ARC_FEATURE_MPU_VERSION == 2 - uint32_t r_addr_start; - uint32_t r_addr_end; - uint32_t r_size_lshift; - - r_addr_start = arc_aux_read(AUX_MPU_RDB0 + 2 * index) & (~AUX_MPU_VALID_MASK); - r_size_lshift = arc_aux_read(AUX_MPU_RDP0 + 2 * index) & AUX_MPU_ATTR_MASK; - r_size_lshift = (r_size_lshift & 0x3) | ((r_size_lshift >> 7) & 0x1C); - r_addr_end = r_addr_start + (1 << (r_size_lshift + 1)); - - if (start >= r_addr_start && (start + size) < r_addr_end) { - return 1; - } - -#elif ARC_FEATURE_MPU_VERSION == 4 - - if ((index == arc_mpu_probe(start)) && - (index == arc_mpu_probe(start + size))) { - return 1; - } -#endif - - return 0; -} - -/** - * @brief Probe whether the given address in mpu entries - * - * @param addr The given address - * @return -1 not in mpu entries, -2 mpu version error, >= 0 mpu entry number - */ -int32_t arc_mpu_probe(uint32_t addr) -{ - -#if ARC_FEATURE_MPU_VERSION == 2 - uint32_t index; - uint32_t regions = ARC_FEATURE_MPU_REGIONS; - - for (index = 0; index < regions; index++) { - if (arc_mpu_in_region(index, addr, 0)) { - return (int32_t)index; - } - } - - return -1; - -#elif ARC_FEATURE_MPU_VERSION == 4 - uint32_t index; - arc_aux_write(AUX_MPU_PROBE, addr); - index = arc_aux_read(AUX_MPU_INDEX); - - /* if no match or multiple regions match, return error */ - if (index & (AUX_MPU_INDEX_DEFAULT | AUX_MPU_INDEX_MULT)) { - return -1; - } else { - return (int32_t)index; - } -#else - return -2; -#endif -} diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_timer.c b/platform/vendor_bsp/embarc_bsp/arc/arc_timer.c deleted file mode 100644 index 90539620..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_timer.c +++ /dev/null @@ -1,447 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC_TIMER - * @brief Internal timer implementation - * @todo RTC support should be improved if RTC is enabled - */ -#include "arc/arc_timer.h" -#include "arc/arc_exception.h" - -#define LPS_PREC 8 - -static volatile uint64_t gl_loops_per_jiffy = 1; -static volatile uint32_t gl_count = 1; - -/** - * @brief Check whether the specific timer present - * @param no Timer number - * @return 1 present, 0 not present - */ -int32_t timer_present(const uint32_t no) -{ - uint32_t bcr = arc_aux_read(AUX_BCR_TIMERS); - - switch (no) { - case TIMER_0: - bcr = (bcr >> 8) & 1; - break; - case TIMER_1: - bcr = (bcr >> 9) & 1; - break; - case TIMER_RTC: - bcr = (bcr >> 10) & 1; - break; - default: - bcr = 0; - /* illegal argument so return false */ - break; - } - - return (int32_t)bcr; -} - -/** - * @brief Start a timer - * @param no Timer number - * @param mode Timer mode - * @param val Timer limit value (not for RTC) - * @return 0 success, -1 failure - */ -int32_t timer_start(const uint32_t no, const uint32_t mode, const uint32_t val) -{ - int32_t ercd = 0; - - switch (no) { - case TIMER_0: - arc_aux_write(AUX_TIMER0_CTRL, 0); - arc_aux_write(AUX_TIMER0_LIMIT, val); - arc_aux_write(AUX_TIMER0_CTRL, mode); - arc_aux_write(AUX_TIMER0_CNT, 0); - break; - case TIMER_1: - arc_aux_write(AUX_TIMER1_CTRL, 0); - arc_aux_write(AUX_TIMER1_LIMIT, val); - arc_aux_write(AUX_TIMER1_CTRL, mode); - arc_aux_write(AUX_TIMER1_CNT, 0); - break; - case TIMER_RTC: - arc_aux_write(AUX_RTC_CTRL, mode); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Stop timer - * - * @param no Timer number - * @return 0 success, -1 failure - */ -int32_t timer_stop(const uint32_t no) -{ - int32_t ercd = 0; - - switch (no) { - case TIMER_0: - arc_aux_write(AUX_TIMER0_CTRL, 0); - arc_aux_write(AUX_TIMER0_LIMIT, 0); - arc_aux_write(AUX_TIMER0_CNT, 0); - break; - case TIMER_1: - arc_aux_write(AUX_TIMER1_CTRL, 0); - arc_aux_write(AUX_TIMER1_LIMIT, 0); - arc_aux_write(AUX_TIMER1_CNT, 0); - break; - case TIMER_RTC: - arc_aux_write(AUX_RTC_CTRL, TIMER_RTC_CLEAR); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Get timer current tick - * - * @param no Timer number - * @param val Timer current tick value - * @return 0 success, -1 failure - */ -int32_t timer_current(const uint32_t no, void *val) -{ - int32_t ercd = 0; - - switch (no) { - case TIMER_0: - *((uint32_t *)val) = arc_aux_read(AUX_TIMER0_CNT); - break; - case TIMER_1: - *((uint32_t *)val) = arc_aux_read(AUX_TIMER1_CNT); - break; - case TIMER_RTC: - *((uint64_t *)val) = arc_aux_read(AUX_RTC_LOW); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Clear the interrupt pending bit of timer - * - * @param no Timer number - * @return 0 success, -1 failure - */ -int32_t timer_int_clear(const uint32_t no) -{ - int32_t ercd = 0; - - switch (no) { - case TIMER_0: - arc_aux_write(AUX_TIMER0_CTRL, - arc_aux_read(AUX_TIMER0_CTRL) & (~TIMER_CTRL_IP)); - break; - case TIMER_1: - arc_aux_write(AUX_TIMER1_CTRL, - arc_aux_read(AUX_TIMER1_CTRL) & (~TIMER_CTRL_IP)); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Initialize internal timer - */ -void arc_timer_init(void) -{ - if (timer_present(TIMER_0)) { - timer_stop(TIMER_0); - } - - if (timer_present(TIMER_1)) { - timer_stop(TIMER_1); - } - - if (timer_present(TIMER_RTC)) { - timer_stop(TIMER_RTC); - } -} - -#if defined(ARC_FEATURE_SEC_TIMER1_PRESENT) || defined(ARC_FEATURE_SEC_TIMER0_PRESENT) -/** - * @brief Check whether the specific secure timer present - * @param no Timer number - * @return 1 present, 0 not present - */ -int32_t secure_timer_present(const uint32_t no) -{ - uint32_t bcr = arc_aux_read(AUX_BCR_TIMERS); - - switch (no) { - case SECURE_TIMER_0: - bcr = (bcr >> 11) & 1; - break; - case SECURE_TIMER_1: - bcr = (bcr >> 12) & 1; - break; - default: - bcr = 0; - /* illegal argument so return false */ - break; - } - - return (int32_t)bcr; -} - -/** - * @brief Start an secure timer - * @param no Timer number - * @param mode Timer mode - * @param val Timer limit value (not for RTC) - * @return 0 success, -1 failure - */ -int32_t secure_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val) -{ - int32_t ercd = 0; - - switch (no) { - case SECURE_TIMER_0: - arc_aux_write(AUX_SECURE_TIMER0_CTRL, 0); - arc_aux_write(AUX_SECURE_TIMER0_LIMIT, val); - arc_aux_write(AUX_SECURE_TIMER0_CTRL, mode); - arc_aux_write(AUX_SECURE_TIMER0_CNT, 0); - break; - case SECURE_TIMER_1: - arc_aux_write(AUX_SECURE_TIMER1_CTRL, 0); - arc_aux_write(AUX_SECURE_TIMER1_LIMIT, val); - arc_aux_write(AUX_SECURE_TIMER1_CTRL, mode); - arc_aux_write(AUX_SECURE_TIMER1_CNT, 0); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Stop and clear a secure timer - * - * @param no Timer number - * @return 0 success, -1 failure - */ -int32_t secure_timer_stop(const uint32_t no) -{ - int32_t ercd = 0; - - switch (no) { - case SECURE_TIMER_0: - arc_aux_write(AUX_SECURE_TIMER0_CTRL, 0); - arc_aux_write(AUX_SECURE_TIMER0_LIMIT, 0); - arc_aux_write(AUX_SECURE_TIMER0_CNT, 0); - break; - case SECURE_TIMER_1: - arc_aux_write(AUX_SECURE_TIMER1_CTRL, 0); - arc_aux_write(AUX_SECURE_TIMER1_LIMIT, 0); - arc_aux_write(AUX_SECURE_TIMER1_CNT, 0); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Get secure timer current tick - * - * @param no Timer number - * @param val Timer value - * @return 0 success, -1 failure - */ -int32_t secure_timer_current(const uint32_t no, void *val) -{ - int32_t ercd = 0; - - switch (no) { - case SECURE_TIMER_0: - *((uint32_t *)val) = arc_aux_read(AUX_SECURE_TIMER0_CNT); - break; - case SECURE_TIMER_1: - *((uint32_t *)val) = arc_aux_read(AUX_SECURE_TIMER1_CNT); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Clear the interrupt pending bit of timer - * - * @param no Timer number - * @return 0 success, -1 failure - */ -int32_t secure_timer_int_clear(const uint32_t no) -{ - int32_t ercd = 0; - - switch (no) { - case SECURE_TIMER_0: - arc_aux_write(AUX_SECURE_TIMER0_CTRL, - arc_aux_read(AUX_SECURE_TIMER0_CTRL) & (~TIMER_CTRL_IP)); - break; - case SECURE_TIMER_1: - arc_aux_write(AUX_SECURE_TIMER1_CTRL, - arc_aux_read(AUX_SECURE_TIMER1_CTRL) & (~TIMER_CTRL_IP)); - break; - default: - ercd = -1; - break; - } - - return ercd; -} - -/** - * @brief Initialize internal secure timer - */ -void secure_timer_init(void) -{ - if (secure_timer_present(SECURE_TIMER_0)) { - secure_timer_stop(SECURE_TIMER_0); - } - - if (secure_timer_present(SECURE_TIMER_1)) { - secure_timer_stop(SECURE_TIMER_1); - } -} -#endif /* ARC_FEATURE_SEC_TIMER1_PRESENT && ARC_FEATURE_SEC_TIMER0_PRESENT */ - -/** - * @brief Function for delaying execution for number of microseconds - * - * @param usecs Number of us - */ -void arc_delay_us(uint32_t usecs) -{ - if (usecs == 0) { - return; - } - - usecs = usecs * gl_loops_per_jiffy / gl_count; - - __asm__ __volatile__ ( - " .align 4 \n" - " mov %%lp_count, %0 \n" - " lp 1f \n" - " nop \n" - "1: \n" - : - : "r" (usecs) - : "lp_count"); -} - -/** - * @brief Get calibration values for a given cpu clock source - * - * @param cpu_clock board CPU clock source to calibrate - * @return loops_per_jiffy Calibration value - */ -uint64_t timer_calibrate_delay(uint32_t cpu_clock) -{ - uint64_t loopbit; - int32_t lps_precision = LPS_PREC; - volatile uint64_t loops_per_jiffy; - uint32_t timer0_limit; - uint32_t status; - - gl_loops_per_jiffy = 1; - gl_count = 1; - - cpu_clock /= 1000; - - status = cpu_lock_save(); - - timer0_limit = arc_aux_read(AUX_TIMER0_LIMIT); - arc_aux_write(AUX_TIMER0_LIMIT, 0xFFFFFFFF); - - loops_per_jiffy = (1 << 4); - while ((loops_per_jiffy <<= 1) != 0) { - - arc_aux_write(AUX_TIMER0_CNT, 0); - arc_delay_us(loops_per_jiffy); - if (arc_aux_read(AUX_TIMER0_CNT) > cpu_clock) { - break; - } - } - - loops_per_jiffy >>= 1; - loopbit = loops_per_jiffy; - while (lps_precision-- && (loopbit >>= 1)) { - - loops_per_jiffy |= loopbit; - arc_aux_write(AUX_TIMER0_CNT, 0); - arc_delay_us(loops_per_jiffy); - if (arc_aux_read(AUX_TIMER0_CNT) > cpu_clock) { - loops_per_jiffy &= ~loopbit; - } - } - - gl_loops_per_jiffy = loops_per_jiffy; - gl_count = 1000; - - arc_aux_write(AUX_TIMER0_CNT, 0); - arc_aux_write(AUX_TIMER0_LIMIT, timer0_limit); - cpu_unlock_restore(status); - - return loops_per_jiffy; -} diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_udma.c b/platform/vendor_bsp/embarc_bsp/arc/arc_udma.c deleted file mode 100644 index 91202db9..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_udma.c +++ /dev/null @@ -1,1060 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/** - * @file - * @ingroup ARC_HAL_MISC_UDMA - * @brief ARC DMA Controller implementation - */ - -/** - * @addtogroup ARC_HAL_MISC_UDMA - * @{ - */ -#include "arc/arc_udma.h" - -/* pointer to DMA controller instance, only one dma controller is supported now */ -static DMA_STATE_T *g_dmac = NULL; - -#if ARC_FEATURE_DCACHE_PRESENT -#define DCACHE_FLUSH_MLINES(addr, size) dcache_flush_mlines((uint32_t)(addr), (uint32_t)(size)) -#else -#define DCACHE_FLUSH_MLINES(addr, size) -#endif -#define MEMORY_FENCE arc_sync() - -#define DMA_INT_LEVEL_SENS 0 - -#if DMA_MULTI_IRQ /* Multiple-Internal interrupt case */ -#define DMA_INT_OK_VECTOR(channel) ((channel) + DMA_IRQ_NUM_START) -#define DMA_INT_ERR_VECTOR(channel) ((channel) + DMA_IRQ_NUM_START + DMA_ALL_CHANNEL_NUM) -#else /* Single-Internal interrupt case */ -#define DMA_INT_OK_VECTOR(channel) ((channel) + DMA_IRQ_NUM_START) -#define DMA_INT_ERR_VECTOR(channel) ((channel) + DMA_IRQ_NUM_START + 1) -#endif - -/*! Interrupt about DMA transaction completion - *! Sets the the "complete" status for completed DMA transaction and - *! starts next transaction from queue. Reset DMA completion IRQ flags - */ -static void dmac_interrupt_completed(void *ptr); -static void dmac_interrupt_completed_channel(uint32_t channel); - -/*! Interrupt about DMA transaction completion with error - *! Sets the the "complete with error" status for completed DMA transaction - *! Reset the DMA channel. - */ -static void dmac_interrupt_error(void *ptr); -static void dmac_interrupt_error_channel(uint32_t channel); - - -/** - * @fn void dmac_enable(void) - */ -Inline void dmac_enable(void) -{ - arc_aux_write(AUX_DMACTRL, 1); -#ifdef DMA_MEMORY_HEADER - arc_aux_write(AUX_DMACBASE, (uint32_t) (g_dmac->mem_dma_descs)); -#endif -#if CORE_DMAC_INTERNAL_VERSION > 1 - arc_aux_write(AUX_DMACBASE, (uint32_t) (g_dmac->mem_dma_ptrs)); -#endif -} - -/** - * @fn void dmac_disable(void) - */ -Inline void dmac_disable(void) -{ - arc_aux_write(AUX_DMACTRL, 0); -} - -/** - * @fn void dmac_enable_channel(uint32_t channel) - */ -Inline void dmac_enable_channel(uint32_t channel) -{ - uint32_t mask = DMACHANNEL(channel); - - arc_aux_write(AUX_DMACENB, mask); -} - -/** - * @fn void dmac_enable_channels(uint32_t mask) - */ -Inline void dmac_enable_channels(uint32_t mask) -{ - arc_aux_write(AUX_DMACENB, mask); -} - -/** - * @fn void dmac_enable_all_channels(void) - */ -Inline void dmac_enable_all_channels(void) -{ - arc_aux_write(AUX_DMACENB, DMA_ALL_CHANNEL_MASK); -} - -/** - * @fn void dmac_disable_channel(uint32_t channel) - */ -Inline void dmac_disable_channel(uint32_t channel) -{ - uint32_t mask = DMACHANNEL(channel); - - arc_aux_write(AUX_DMACDSB, mask); -} - -/** - * @fn void dmac_disable_channels(uint32_t mask) - */ -Inline void dmac_disable_channels(uint32_t mask) -{ - arc_aux_write(AUX_DMACDSB, mask); -} - -/** - * @fn void dmac_disable_all_channels(void) - */ -Inline void dmac_disable_all_channels(void) -{ - arc_aux_write(AUX_DMACDSB, DMA_ALL_CHANNEL_MASK); -} - -/** - * @fn void dmac_reset_channel(uint32_t channel) - */ -Inline void dmac_reset_channel(uint32_t channel) -{ - uint32_t mask = DMACHANNEL(channel); - - arc_aux_write(AUX_DMACRST, mask); -} - -/** - * @fn void dmac_reset_channels(uint32_t mask) - */ -Inline void dmac_reset_channels(uint32_t mask) -{ - arc_aux_write(AUX_DMACRST, mask); -} - -/** - * @fn void dmac_reset_all_channels(void) - */ -Inline void dmac_reset_all_channels(void) -{ - arc_aux_write(AUX_DMACRST, DMA_ALL_CHANNEL_MASK); -} - -/** - * @fn uint32_t dmac_reset_status(void) - */ -Inline uint32_t dmac_reset_status(void) -{ - return arc_aux_read(AUX_DMACRST); -} - -/** - * @fn void dmac_set_high_pri_channels(uint32_t mask) - */ -Inline void dmac_set_high_pri_channels(uint32_t mask) -{ - arc_aux_write(AUX_DMACHPRI, mask); -} - -/** - * @fn void dmac_set_normal_pri_channels(uint32_t mask) - */ -Inline void dmac_set_normal_pri_channels(uint32_t mask) -{ - arc_aux_write(AUX_DMACNPRI, mask); -} - -/** - * @fn void dmac_start_trigger(uint32_t channel) - */ -Inline void dmac_start_trigger(uint32_t channel) -{ - arc_aux_write(AUX_DMACREQ, DMACHANNEL(channel)); -} - -/** - * @fn void dmac_start_trigger_mask(uint32_t mask) - */ -Inline void dmac_start_trigger_mask(uint32_t mask) -{ - arc_aux_write(AUX_DMACREQ, mask); -} - -/** - * @fn void dmac_irq_clear(uint32_t channel) - */ -Inline void dmac_irq_clear(uint32_t channel) -{ - arc_aux_write(AUX_DMACIRQ, DMACHANNEL(channel)); -} - -/** - * @fn void dmac_irq_clear_all(void) - */ -Inline void dmac_irq_clear_all(void) -{ - arc_aux_write(AUX_DMACIRQ, DMA_ALL_CHANNEL_MASK); -} - -/** - * @fn uint32_t dmac_irq_status(void) - */ -Inline uint32_t dmac_irq_status(void) -{ - return arc_aux_read(AUX_DMACIRQ); -} - -/** - * @fn uint32_t dmac_channel_status(void) - */ -Inline uint32_t dmac_channel_status(void) -{ - return arc_aux_read(AUX_DMACSTAT0); -} - -/** - * @fn uint32_t dmac_complete_status(void) - */ -Inline uint32_t dmac_complete_status(void) -{ - return arc_aux_read(AUX_DMACSTAT1); -} - -/** - * @fn void dmac_clear_error(uint32_t channel) - */ -Inline void dmac_clear_error(uint32_t channel) -{ - arc_aux_write(AUX_DMACSTAT1, DMACHANNEL(channel) << 16); -} - -/** - * @fn void dmac_clear_all_error(void) - */ -Inline void dmac_clear_all_error(void) -{ - arc_aux_write(AUX_DMACSTAT1, 0xFFFF0000); -} - -static uint32_t dmac_wait_channel_status(uint32_t channel) -{ - uint32_t status = arc_aux_read(AUX_DMACSTAT1); - uint32_t mask = DMACHANNEL(channel); - uint32_t ret = DMA_BUSY; - - if (arc_compiler_usually(status & mask)) { - if (arc_compiler_rarely(status & (mask << 16))) { - ret = DMA_ERROR; - } else { - status = arc_aux_read(AUX_DMACSTAT0); - if (arc_compiler_rarely(status & mask)) { - ret = DMA_BUSY; - } else { - ret = DMA_IDLE; - } - } - } - - return ret; -} - -static uint32_t dmac_wait_mask(uint32_t mask) -{ - uint32_t status = arc_aux_read(AUX_DMACSTAT1); - uint32_t ret = DMA_BUSY; - - if (arc_compiler_rarely(status & mask)) { - if (arc_compiler_rarely(status & (mask << 16))) { - ret = DMA_ERROR; - } else { - ret = DMA_IDLE; - } - } - - return ret; -} - -/* calc the true size of dma area, e.g. data width: 1 byte, address inc: 2 bytes - * ---data0--- - * ---gap0--- - * --data1--- - * --gap1--- - * case: 1 byte, address inc: 4 bytes - * ---data0--- - * ---gap0--- - * ---gap0--- - * ---gap0--- - * ---data1--- - * ---gap1--- - * ---gap1--- - * ---gap1--- - */ -static uint32_t dmac_memory_addr_gap(uint32_t dmac_mode) -{ - uint32_t size = (dmac_mode & DMACTRLx_SIZE_MASK) >> DMACTRLx_SIZE_OFS; - uint32_t dwinc = (dmac_mode & DMACTRLx_DWINC_MASK) >> DMACTRLx_DWINC_OFS; - - switch (dwinc) { - /* the following are cases needed to be adjusted */ - case DMA_DW1INC2: - size <<= 1; - break; - case DMA_DW1INC4: - size <<= 2; - break; - case DMA_DW2INC2: - size &= ~0x1; - break; - case DMA_DW2INC4: - size &= ~0x1; - size <<= 1; - break; - case DMA_DW4INC4: - size &= ~0x3; - break; - case DMA_DW8INC8: - size &= ~0x7; - break; - case DMA_DW1INC1: - case DMA_DWINC_CLR: - default: - break; - } - return size; -} - -/* calc the real size in aux address space */ -static uint32_t dmac_aux_addr_gap(uint32_t dmac_mode) -{ - uint32_t size = (dmac_mode & DMACTRLx_SIZE_MASK) >> DMACTRLx_SIZE_OFS; - uint32_t dwinc = (dmac_mode & DMACTRLx_DWINC_MASK) >> DMACTRLx_DWINC_OFS; - - switch (dwinc) { - case DMA_DW2INC2: - case DMA_DW2INC4: - size >>= 1; - break; - case DMA_DW4INC4: - case DMA_DW8INC8: - size >>= 2; - break; - case DMA_DW1INC1: - case DMA_DW1INC2: - case DMA_DW1INC4: - case DMA_DWINC_CLR: - default: - break; - } - return size; -} - -static uint32_t dmac_calc_dst_endaddr(uint32_t dst_addr, uint32_t dmac_mode) -{ - uint32_t addr = dst_addr; - - /* - * Destination address is not incremented - */ - if (arc_compiler_rarely((dmac_mode & DMACTRLx_AM(2)) == 0)) { - return addr; - } - - if (arc_compiler_rarely(DMACTRLx_DTT(0x1) & dmac_mode)) { /* Destination is Auxiliary */ - addr = dst_addr + dmac_aux_addr_gap(dmac_mode); - } else { /* Destination is Memory */ - addr = dst_addr + dmac_memory_addr_gap(dmac_mode); - } - return addr; -} - -static uint32_t dmac_calc_src_endaddr(uint32_t src_addr, uint32_t dmac_mode) -{ - uint32_t addr = src_addr; - - /* - * Source address is not incremented - */ - if (arc_compiler_rarely((dmac_mode & DMACTRLx_AM(1)) == 0)) { - return addr; - } - - if (arc_compiler_rarely(DMACTRLx_DTT(0x2) & dmac_mode)) { /* Source is Auxiliary */ - addr = src_addr + dmac_aux_addr_gap(dmac_mode); - } else { /* Source is Memory */ - addr = src_addr + dmac_memory_addr_gap(dmac_mode); - } - - return addr; -} - -static void dmac_set_desc(DMA_DESC_T *desc, uint32_t *source, uint32_t *dest, uint32_t size, - uint32_t dmac_mode) -{ - uint32_t src_addr, dst_addr; - - size = DMA_CTRL_BLKSZ(size); - dmac_mode &= ~DMACTRLx_SIZE_MASK; - dmac_mode |= DMACTRLx_SIZE(size); - - src_addr = dmac_calc_src_endaddr((uint32_t)source, dmac_mode); - dst_addr = dmac_calc_dst_endaddr((uint32_t)dest, dmac_mode); - - desc->DMACTRLx = dmac_mode; - desc->DMASARx = src_addr; - desc->DMADARx = dst_addr; - desc->DMALLPx = 0; -} - -static void dmac_fill_descriptor(uint32_t channel, DMA_DESC_T *desc) -{ - if (arc_compiler_usually(DMA_CHECK_REGISTER(channel))) { - uint32_t channel_shift = 3 * channel; - arc_aux_write(AUX_DMACTRL0 + channel_shift, desc->DMACTRLx); - arc_aux_write(AUX_DMASAR0 + channel_shift, desc->DMASARx); - arc_aux_write(AUX_DMADAR0 + channel_shift, desc->DMADARx); -#if CORE_DMAC_INTERNAL_VERSION > 1 - uint32_t *dma_llps = (uint32_t *) arc_aux_read(AUX_DMACBASE); - dma_llps[channel] = desc->DMALLPx; - MEMORY_FENCE; - DCACHE_FLUSH_MLINES(&dma_llps[channel], sizeof(uint32_t)); -#endif - } else { -#if CORE_DMAC_INTERNAL_VERSION > 1 - uint32_t *dma_ptrs = (uint32_t *) arc_aux_read(AUX_DMACBASE); - dma_ptrs[channel] = (uint32_t)desc; - MEMORY_FENCE; - DCACHE_FLUSH_MLINES(&dma_ptrs[channel], sizeof(uint32_t)); -#else - DMA_DESC_T *dmac_desc = (DMA_DESC_T *) arc_aux_read(AUX_DMACBASE); - dmac_desc = (DMA_DESC_T *) (&dmac_desc[channel]); - /* more efficient to let compiler do this copy */ - *dmac_desc = *desc; - MEMORY_FENCE; - DCACHE_FLUSH_MLINES(dmac_desc, sizeof(DMA_DESC_T)); -#endif - } -} - -/** - * @brief Initialize uDMA controller with a valid DMA_STATE_T structure - * - * If you want to use this uDMA driver, you need to call the dmac_init function - * with a valid state, dmac will init the valid state. If initialized successfully, - * you can use the other uDMA APIs. - * - * @param state DMA state structure to maintain uDMA resources, this should not be NULL - * - * @retval -1 State is NULL - * @retval 0 Initialize successfully - */ -int32_t dmac_init(DMA_STATE_T *state) -{ - if (state == NULL) { - return -1; - } - - g_dmac = state; - - memset((void *) g_dmac, 0, sizeof(DMA_STATE_T)); - - dmac_disable(); - dmac_disable_all_channels(); -#if CORE_DMAC_INTERNAL_VERSION > 1 - dmac_reset_all_channels(); -#endif - dmac_enable(); - -#if !DMA_MULTI_IRQ - int_level_config(DMA_INT_OK_VECTOR(0), DMA_INT_LEVEL_SENS); - int_enable(DMA_INT_OK_VECTOR(0)); - int_handler_install(DMA_INT_OK_VECTOR(0), dmac_interrupt_completed); - int_pri_set(DMA_INT_OK_VECTOR(0), DMA_IRQ_PRIO); - - int_level_config(DMA_INT_ERR_VECTOR(0), DMA_INT_LEVEL_SENS); - int_enable(DMA_INT_ERR_VECTOR(0)); - int_handler_install(DMA_INT_ERR_VECTOR(0), dmac_interrupt_error); - int_pri_set(DMA_INT_ERR_VECTOR(0), DMA_IRQ_PRIO); -#else - for (int32_t i = 0; i < DMA_ALL_CHANNEL_NUM; i++) { - int_level_config(DMA_INT_OK_VECTOR(i), DMA_INT_LEVEL_SENS); - int_enable(DMA_INT_OK_VECTOR(i)); - int_handler_install(DMA_INT_OK_VECTOR(i), dmac_interrupt_completed); - int_pri_set(DMA_INT_OK_VECTOR(i), DMA_IRQ_PRIO); - - int_level_config(DMA_INT_ERR_VECTOR(i), DMA_INT_LEVEL_SENS); - int_enable(DMA_INT_ERR_VECTOR(i)); - int_handler_install(DMA_INT_ERR_VECTOR(i), dmac_interrupt_error); - int_pri_set(DMA_INT_ERR_VECTOR(i), DMA_IRQ_PRIO); - } - -#endif - return 0; -} - -static void dmac_process_desc(DMA_DESC_T *desc, uint32_t ienable) -{ - do { - if (arc_compiler_rarely(desc->DMALLPx)) { - /* - * Force it to be auto-linked transfer when it is not - * DMA_MANUAL_LINKED_TRANSFER - */ - if (arc_compiler_usually(((desc->DMACTRLx & DMACTRLx_OP_MASK) >> DMACTRLx_OP_OFS) != - DMA_MANUAL_LINKED_TRANSFER)) { - desc->DMACTRLx &= ~DMACTRLx_OP_MASK; - desc->DMACTRLx |= DMACTRLx_OP(DMA_AUTO_LINKED_TRANSFER); - } - } else { - desc->DMACTRLx &= ~DMACTRLx_OP_MASK; - desc->DMACTRLx |= DMACTRLx_OP(DMA_SINGLE_TRANSFER); - /* Only forcely change the interrupt bit of the last dma descriptor */ - desc->DMACTRLx &= ~DMACTRLx_INT_MASK; - desc->DMACTRLx |= DMACTRLx_INT(ienable); - } - /* - * TODO: Make sure all linked DMA channel descriptors - * stored into memory, not just in data cache - */ - MEMORY_FENCE; - DCACHE_FLUSH_MLINES(desc, sizeof(DMA_DESC_T)); - desc = (DMA_DESC_T *) desc->DMALLPx; - } while (desc != 0); -} - -static int32_t dmac_valid_channel(int32_t channel, DMA_DESC_T *desc) -{ -#if CORE_DMAC_INTERNAL_VERSION == 1 - if (DMA_CHECK_REGISTER(channel)) { - if (arc_compiler_rarely(desc->DMALLPx)) { - /** For AUX Mapped registers, Linked transfer is not supported */ - return -1; - } - } -#endif - return 0; -} - -static void dmac_interrupt_completed_channel(uint32_t channel) -{ - dmac_irq_clear(channel); - dmac_disable_channel(channel); - - if (channel >= DMA_ALL_CHANNEL_NUM) { - return; - } - - DMA_CHANNEL_T *dma_chn = (DMA_CHANNEL_T *) g_dmac->dma_chns[channel]; - dma_chn->status = DMA_IDLE; - if (arc_compiler_usually(dma_chn->callback)) { - dma_chn->callback((void *) dma_chn); - } -} - -static void dmac_interrupt_error_channel(uint32_t channel) -{ - dmac_irq_clear(channel); - dmac_clear_error(channel); - dmac_disable_channel(channel); - - if (channel >= DMA_ALL_CHANNEL_NUM) { - return; - } - - DMA_CHANNEL_T *dma_chn = (DMA_CHANNEL_T *) g_dmac->dma_chns[channel]; - dma_chn->status = DMA_ERROR; - if (arc_compiler_usually(dma_chn->callback)) { - dma_chn->callback((void *) dma_chn); - } -} - -static void dma_claim_channel(int32_t channel, DMA_CHANNEL_T *dma_chn, - uint32_t source) -{ - g_dmac->dma_chns[channel] = dma_chn; - dma_chn->source = source; - dma_chn->callback = NULL; - dma_chn->status = DMA_IDLE; - dma_chn->channel = channel; -} - -#if !DMA_MULTI_IRQ -static void dmac_interrupt_completed(void *ptr) -{ - /* In complete interrupt, the DMACIRQ and DMACSTAT1 complete bit are both set */ - uint32_t status = dmac_complete_status(); - - for (int32_t channel = 0; channel < DMA_ALL_CHANNEL_NUM; - ++channel, status >>= 1) { - if (arc_compiler_rarely(status & 0x1)) { - dmac_interrupt_completed_channel(channel); - } - } -} - -static void dmac_interrupt_error(void *ptr) -{ - /* In error interrupt, the DMACIRQ is not set, only the DMACSTAT1 error bit is set */ - uint32_t status = dmac_complete_status() >> 16; - - for (int32_t channel = 0; channel < DMA_ALL_CHANNEL_NUM; - ++channel, status >>= 1) { - if (arc_compiler_rarely(status & 0x1)) { - dmac_interrupt_error_channel(channel); - } - } -} -#else -static void dmac_interrupt_completed(void *ptr) -{ - uint32_t channel; - - channel = arc_aux_read(AUX_IRQ_CAUSE) - DMA_IRQ_NUM_START; - - dmac_interrupt_completed_channel(channel); -} - -static void dmac_interrupt_error(void *ptr) -{ - uint32_t channel; - - channel = arc_aux_read(AUX_IRQ_CAUSE) - DMA_IRQ_NUM_START - - DMA_ALL_CHANNEL_NUM; - - dmac_interrupt_error_channel(channel); -} -#endif - -/** - * @brief Close uDMA controller - * - * @details This function disable all DMA channels. - */ -void dmac_close(void) -{ - if (arc_compiler_rarely(!g_dmac)) { - return; - } - - dmac_disable_all_channels(); -#if CORE_DMAC_INTERNAL_VERSION > 1 - dmac_reset_all_channels(); -#endif - dmac_disable(); -} - -/** - * @brief Configure uDMA descriptor with source/destination address, - * transfer size in bytes and ctrl mode. - * - * @param desc uDMA descriptor, this should not be NULL - * @param src Source address for the uDMA transfer - * @param dst Destination address for the uDMA transfer - * @param size Actual transfer size in bytes - * @param ctrl uDMA channel control value - * - * @retval -1 desc is NULL - * @retval 0 OK - * @note The DMALLPx of desc will be set to NULL in this function, and DMACTRLx - * of desc will be set with right transfer size - */ -int32_t dmac_config_desc(DMA_DESC_T *desc, void *src, void *dst, uint32_t size, - DMA_CTRL_T *ctrl) -{ - if (arc_compiler_rarely(desc == NULL)) { - return -1; - } - - dmac_set_desc(desc, src, dst, size, ctrl->value); - - return 0; -} - -/** - * @brief Set uDMA channel linked-list pointer register, head -> next - * - * @param head uDMA descriptor, should not be NULL - * @param next uDMA descriptor, could be NULL - * - * @retval -1 head is NULL - * @retval 0 OK - */ -int32_t dmac_desc_add_linked(DMA_DESC_T *head, DMA_DESC_T *next) -{ - if (arc_compiler_rarely(head == NULL)) { - return -1; - } - head->DMALLPx = (uint32_t) next; - return 0; -} - -/** - * @brief Initialize a channel for DMA transfer - * - * @param dma_chn Data structure containing the default configuration for the selected channel, should not be NULL - * - * @retval -1 dma_chn is NULL - * @retval 0 OK - * @note Channel will be set to DMA_CHN_INVALID - */ -int32_t dmac_init_channel(DMA_CHANNEL_T *dma_chn) -{ - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - - dma_chn->desc = NULL; - dma_chn->source = DMA_REQ_SOFT; - dma_chn->callback = NULL; - dma_chn->status = DMA_IDLE; - dma_chn->channel = DMA_CHN_INVALID; - return 0; -} - -/** - * @brief Configure channel for DMA transfer - * - * @param dma_chn Data structure containing the intended configuration for the selected channel, should not be NULL - * @param desc uDMA descriptor - * - * @retval -1 dma_chn is NULL - * @retval 0 OK - */ -int32_t dmac_config_channel(DMA_CHANNEL_T *dma_chn, DMA_DESC_T *desc) -{ - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - - dma_chn->desc = desc; - return 0; -} - -/** - * @brief Reserve a DMA channel, bind it with dma_chn, and set the dma - * trigger source - * - * @param channel This can be DMA_CHN_ANY or any valid - * channel id. For DMA_CHN_ANY, it will try - * to peek an available channel. For any - * valid channel id, it will try to reserve - * that channel. - * @param dma_chn uDMA channel structure, should not be NULL - * @param source DMA trigger source, this can be any value in uint32_t enum - * - * @retval DMA_CHN_INVALID dma_chn is NULL, or channel is not a - * valid one, or there is no channel available now - * @retval 0-DMA_ALL_CHANNEL_NUM The channel id that reserved - */ -int32_t dmac_reserve_channel(int32_t channel, DMA_CHANNEL_T *dma_chn, - uint32_t source) -{ - if (arc_compiler_rarely(dma_chn == NULL)) { - return DMA_CHN_INVALID; - } - - if (arc_compiler_usually(channel == DMA_CHN_ANY)) { - for (int32_t i = 0; i < DMA_ALL_CHANNEL_NUM; i++) { - if (arc_compiler_usually(!g_dmac->dma_chns[i])) { - g_dmac->dma_chns[i] = dma_chn; - dma_claim_channel(i, dma_chn, source); - return i; - } - } - return DMA_CHN_INVALID; - } - if (arc_compiler_rarely((uint32_t) channel >= DMA_ALL_CHANNEL_NUM)) { - return DMA_CHN_INVALID; - } - - if (arc_compiler_usually(!g_dmac->dma_chns[channel])) { - dma_claim_channel(channel, dma_chn, source); - return channel; - } - - return DMA_CHN_INVALID; -} - -/** - * @brief Start uDMA transfer for dma_chn, set handler function for uDAM callback and transfer - * priority - * - * @param dma_chn uDMA channel structure, should not be NULL - * @param callback Handler function, when DMA transfer is done, it will - * be called with parameter which value is dma_chn - * @param priority uDMA transfer priority - * - * @retval -1 dma_chn is NULL or dma_chn->desc is NULL or channel of - * dma_chn is not a valid one or dma_chn is still in transfer - * @retval -2 When channel is a aux-based channel, the dma descriptor should - * not be a linked list - * @retval 0 OK - * @note When callback is NULL, then all INT field in DMA descriptor will be set - * to interrupt disable, otherwise it will be set to interrupt enable - */ -int32_t dmac_start_channel(DMA_CHANNEL_T *dma_chn, DMA_CALLBACK_T callback, - uint32_t priority) -{ - int32_t channel; - - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - if (arc_compiler_rarely(dma_chn->desc == NULL)) { - return -1; - } - - channel = dma_chn->channel; - - if (arc_compiler_rarely(!((uint32_t) channel < DMA_ALL_CHANNEL_NUM))) { - return -1; - } - - if (arc_compiler_rarely(dma_chn->status == DMA_BUSY)) { - return -1; - } - /** Check if aux based registers and linked transfer is not supported */ - - if (arc_compiler_rarely(dmac_valid_channel(channel, dma_chn->desc) != 0)) { - return -2; - } - - dma_chn->callback = callback; - dma_chn->priority = priority; - /* - * When callback function is NULL, disable interrupt, use simple poll - * instead - */ - if (arc_compiler_rarely(callback)) { - dma_chn->int_en = DMA_INT_ENABLE; - } else { - dma_chn->int_en = DMA_INT_DISABLE; - } - if (arc_compiler_usually(priority == DMA_CHN_HIGH_PRIO)) { - dmac_set_high_pri_channels(DMACHANNEL(channel)); - } else { - dmac_set_normal_pri_channels(DMACHANNEL(channel)); - } - - dmac_process_desc(dma_chn->desc, dma_chn->int_en); - dmac_fill_descriptor(channel, dma_chn->desc); - dmac_clear_error(channel); -#if CORE_DMAC_INTERNAL_VERSION > 1 - dmac_reset_channel(channel); -#endif - dmac_disable_channel(channel); - dmac_enable_channel(channel); - dma_chn->status = DMA_BUSY; - /* - * only trigger when software - */ - if (arc_compiler_usually(dma_chn->source == DMA_REQ_SOFT)) { - dmac_start_trigger(channel); - } - return 0; -} - -/** - * @brief Stop uDMA transfer - * - * @param dma_chn uDMA channel structure, should not be NULL - * - * @retval -1 dma_chn is NULL or dma_chn->desc is NULL or channel of - * dma_chn is not a valid one - * @retval 0 OK - */ -int32_t dmac_stop_channel(DMA_CHANNEL_T *dma_chn) -{ - int32_t channel; - - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - if (arc_compiler_rarely(dma_chn->desc == NULL)) { - return -1; - } - - channel = dma_chn->channel; - - if (arc_compiler_rarely(!((uint32_t) channel < DMA_ALL_CHANNEL_NUM))) { - return -1; - } - - dmac_disable_channel(channel); - dmac_clear_error(channel); - if (arc_compiler_usually(dma_chn->status == DMA_BUSY)) { - dma_chn->status = DMA_STOP; - } - return 0; -} - -/** - * @brief Clear channel transfer status and set it to DMA_IDLE - * - * @param dma_chn uDMA channel structure, should not be NULL - * - * @retval -1 dma_chn is NULL or dma_chn->desc is NULL or channel of - * dma_chn is not a valid one - * @retval 0 OK - */ -int32_t dmac_clear_channel(DMA_CHANNEL_T *dma_chn) -{ - int32_t channel; - - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - if (arc_compiler_rarely(dma_chn->desc == NULL)) { - return -1; - } - - channel = dma_chn->channel; - - if (arc_compiler_rarely(!((uint32_t) channel < DMA_ALL_CHANNEL_NUM))) { - return -1; - } - - dmac_clear_error(channel); - dmac_disable_channel(channel); - dmac_enable_channel(channel); - dma_chn->status = DMA_IDLE; - - return 0; -} - -/** - * @brief Release an uDMA channel - * - * @param dma_chn Channel tansfer structure of uDMA channel to be released, should not be NULL - * - * @retval -1 dma_chn is NULL or dma_chn->desc is NULL or channel of - * dma_chn is not a valid one - * @retval 0 OK - */ -int32_t dmac_release_channel(DMA_CHANNEL_T *dma_chn) -{ - int32_t channel; - - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - if (arc_compiler_rarely(dma_chn->desc == NULL)) { - return -1; - } - channel = dma_chn->channel; - - if (arc_compiler_rarely(!((uint32_t) channel < DMA_ALL_CHANNEL_NUM))) { - return -1; - } - - dmac_clear_error(channel); - dmac_disable_channel(channel); - g_dmac->dma_chns[channel] = NULL; - dma_chn->channel = DMA_CHN_INVALID; - - return 0; -} - -/** - * @brief Wait until uDMA channel job is completed - * - * @param dma_chn Channel tansfer structure of uDMA channel, should not be NULL - * - * @retval -1 dma_chn is NULL or dma_chn->desc is NULL or channel - * of dma_chn is not a valid one - * @retval DMA_IDLE Transfer is done without error - * @retval DMA_ERROR Transfer is done with error - */ -int32_t dmac_wait_channel(DMA_CHANNEL_T *dma_chn) -{ - int32_t channel; - - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - if (arc_compiler_rarely(dma_chn->desc == NULL)) { - return -1; - } - - channel = dma_chn->channel; - - if (arc_compiler_rarely(!((uint32_t) channel < DMA_ALL_CHANNEL_NUM))) { - return -1; - } - - while (dma_chn->status == DMA_BUSY) { - if (arc_compiler_usually(dma_chn->int_en == DMA_INT_DISABLE)) { - dma_chn->status = dmac_wait_channel_status(channel); - } - } - return dma_chn->status; -} - -/** - * @brief Check channel transfer status - * - * @param dma_chn Channel tansfer structure of uDMA channel, should not be NULL - * - * @retval -1 dma_chn is NULL or dma_chn->desc is NULL or channel - * of dma_chn is not a valid one - * @retval DMA_BUSY Still in transfer state - * @retval DMA_IDLE Transfer is done without error - * @retval DMA_ERROR Transfer is done with error - */ -int32_t dmac_check_channel(DMA_CHANNEL_T *dma_chn) -{ - int32_t channel; - - if (arc_compiler_rarely(dma_chn == NULL)) { - return -1; - } - if (arc_compiler_rarely(dma_chn->desc == NULL)) { - return -1; - } - - channel = dma_chn->channel; - - if (arc_compiler_rarely(!((uint32_t) channel < DMA_ALL_CHANNEL_NUM))) { - return -1; - } - - if (arc_compiler_usually(dma_chn->int_en == DMA_INT_DISABLE)) { - dma_chn->status = dmac_wait_channel_status(channel); - } - return dma_chn->status; -} - -/** @} end of group ARC_HAL_MISC_UDMA */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/arc/arc_util.s b/platform/vendor_bsp/embarc_bsp/arc/arc_util.s deleted file mode 100644 index 58ba5a19..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/arc_util.s +++ /dev/null @@ -1,93 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ - -#define __ASSEMBLY__ -#include "arc/arc.h" -#include "arc/arc_asm_common.h" - - .file "arc_utils.s" - -/** - * @brief Go to user mode - * - * @param target Target address to run in user mode, 0 means next - * line of code - * @param sp Stack where the target address runs, 0 means using - * current stack - */ - .text - .global arc_goto_usermode - .align 4 -arc_goto_usermode: - cmp r0, 0 - mov.z r0, blink - cmp r1, 0 - mov.nz sp, r1 -#if defined(ARC_FEATURE_SEC_PRESENT) - sr (1 << AUX_ERSEC_STAT_BIT_ERM), [AUX_ERSEC_STAT] - sr sp, [AUX_SEC_U_SP] -#else - sr sp, [AUX_USER_SP] -#endif - lr r1, [AUX_STATUS32] - bset r1, r1, AUX_STATUS_BIT_U - sr r1, [AUX_ERSTATUS] - lr r1, [AUX_STATUS32] - bset r1, r1, AUX_STATUS_BIT_AE - kflag r1 - sr r0, [AUX_ERRET] - rtie - -/** - * @brief go to kernel mode - * this function uses trap exception to do switch from user mode to kernel mode, - * please install exc_entry_arc_goto_kernelmode for trap exception before call this - * function - * @param target, the target address to run in kernel mode, 0 means next line of code - * @param sp, the stack where the target address runs, 0 means using current stack - */ - .text - .global arc_goto_kernelmode - .global exc_entry_arc_goto_kernelmode - .align 4 -arc_goto_kernelmode: - cmp r0, 0 - mov.z r0, blink - cmp r1, 0 - mov.z r1, sp - trap_s 0 - .align 4 -exc_entry_arc_goto_kernelmode: - mov sp, r1 - sr r0, [AUX_ERRET] - lr r0, [AUX_ERSTATUS] - bclr r0, r0, AUX_STATUS_BIT_U - sr r0, [AUX_ERSTATUS] - rtie diff --git a/platform/vendor_bsp/embarc_bsp/arc/startup/arc_cxx_support.c b/platform/vendor_bsp/embarc_bsp/arc/startup/arc_cxx_support.c deleted file mode 100644 index 4dac9b33..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/startup/arc_cxx_support.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2012-2014 Wind River Systems, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_STARTUP - * @brief C++ support module for ARC - */ - -#if defined(__GNU__) -#include "embarc_toolchain.h" -/* embARC's GNU C++ support takes reference from Zephyr (cpp_xxx.c) */ - -/** - * @brief - * The ctors section contains a list of function pointers that execute the - * C++ constructors of static global objects. These must be executed before - * the application's main() routine. - * - * NOTE: Not all compilers put those function pointers into the ctors section; - * some put them into the init_array section instead. - */ - -/* What a constructor function pointer looks like */ - -typedef void (*CTOR_FUNC_PTR_T)(void); - -/* Constructor function pointer list is generated by the linker script. */ - -extern CTOR_FUNC_PTR_T __CTOR_LIST__[]; -extern CTOR_FUNC_PTR_T __CTOR_END__[]; - -/** - * - * @brief Invoke all C++ style global object constructors - * - * This routine is invoked before the execution of the - * application's main(). - */ -void arc_gnu_do_global_ctors_aux(void) -{ - uint32_t num_ctors; - - num_ctors = (uint32_t)__CTOR_LIST__[0]; - - while (num_ctors >= 1) { - __CTOR_LIST__[num_ctors--](); - } -} - -typedef void (*DTOR_FUNC_PTR_T)(void); - -extern DTOR_FUNC_PTR_T __DTOR_LIST__[]; -extern DTOR_FUNC_PTR_T __DTOR_END__[]; - -/** - * - * @brief Invoke all C++ style global object destructors - * - * This routine is invoked after the execution of the - * application's main(). - */ -void arc_gnu_do_global_dtors_aux(void) -{ - uint32_t nDtors; - uint32_t i; - - nDtors = (uint32_t)__DTOR_LIST__[0]; - i = 1; - - while (i <= nDtors) { - __DTOR_LIST__[i++](); - } -} - -void *__dso_handle = 0; - -/** - * @brief Register destructor for a global object - * - * @param destructor the global object destructor function - * @param objptr global object pointer - * @param dso Dynamic Shared Object handle for shared libraries - * - * Function does nothing at the moment, assuming the global objects - * do not need to be deleted - * - * @return N/A - */ -int32_t __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso) -{ - return 0; -} - -typedef void (*FUNC_PTR_T)(void); - -extern FUNC_PTR_T __init_array_start[0]; -extern FUNC_PTR_T __init_array_end[0]; - -/** - * @brief Execute initialization routines referenced in .init_array section - * - * @return N/A - */ -void arc_gnu_do_init_array_aux(void) -{ - for (FUNC_PTR_T *func = __init_array_start; - func < __init_array_end; - func++) { - (*func)(); - } -} - -/** - * @brief Stub for pure virtual functions - * - * This routine is needed for linking C++ code that uses pure virtual - * functions. - * - * @return N/A - */ -void __cxa_pure_virtual(void) -{ - while (1) { - ; - } -} -#endif \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/arc/startup/arc_startup.s b/platform/vendor_bsp/embarc_bsp/arc/startup/arc_startup.s deleted file mode 100644 index 7cbe6ce3..00000000 --- a/platform/vendor_bsp/embarc_bsp/arc/startup/arc_startup.s +++ /dev/null @@ -1,233 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_STARTUP - * @brief Assembly part of startup process - */ - -/** - * @addtogroup ARC_HAL_STARTUP - * @{ - */ -/** @cond STARTUP_ASM */ - -#define __ASSEMBLY__ -#include "arc/arc.h" -#include "arc/arc_asm_common.h" - - .file "arc_startup.s" - -.weak _f_sdata /* start of small data, defined in link script */ -.weak init_hardware_hook /* app hardware init hook */ - -.extern board_main -.extern exc_entry_table - -/* initial vector table */ - .section .init_vector, "a" - .long exc_entry_reset - .section .init_bootstrap, "ax" - .global exc_entry_reset - .global _start - .align 4 -_start: -exc_entry_reset: -_arc_reset_stage1: - kflag STATUS32_RESET_VALUE - -/* STAGE 1 */ - -/* necessary hardware should be done first to speed up initialization - 1. system clk - 2. mem controller must be initialized before any access to external - mem. - 3. others -*/ -_arc_cache_init_start: - lr r0, [AUX_BCR_D_CACHE] - cmp r0, 2 - /* invalidate dcache */ - jle _arc_icache_init - mov r0, 1 - sr r0, [AUX_DC_IVDC] - sr r0, [AUX_DC_CTRL] -_arc_icache_init: - lr r0, [AUX_BCR_I_CACHE] - cmp r0, 2 - jle _arc_cache_init_end - /* invalidate icache */ - mov r0, 1 - sr r0, [AUX_IC_IVIC] - nop_s - nop_s - nop_s - sr r0, [AUX_IC_CTRL] - -_arc_cache_init_end: - mov r0, init_hardware_hook - cmp r0, 0 - jlne [r0] - -/* STAGE 2: init necessary registers */ - -_arc_reset_stage2: - mov r0, 0 - -/* interrupt related init */ - sr r0, [AUX_IRQ_ACT] - sr r0, [AUX_IRQ_CTRL] - sr r0, [AUX_IRQ_HINT] - -/* use the new vector table to replace the old one */ -#if defined(ARC_FEATURE_SEC_PRESENT) - sr exc_entry_table, [AUX_INT_VECT_BASE_S] -#else - sr exc_entry_table, [AUX_INT_VECT_BASE] -#endif - mov gp, _f_sdata /* init small-data base register */ - mov fp, 0 /* init fp register */ - -#if ARC_FEATURE_MP_NUM_CPUS > 1 - GET_CORE_ID r0 - breq r0, 0, _master_core_startup - -_slave_core_wait: - ld r1, [arc_cpu_wake_flag] - brne r0, r1, _slave_core_wait - - ld sp, [arc_cpu_sp] - /* signal master core that slave core runs */ - st 0, [arc_cpu_wake_flag] - - j arc_slave_start - -_master_core_startup: -#endif - mov sp, _e_stack /* init stack pointer */ - -_arc_reset_stage3: -_s3_copy_text: - mov r0, _f_text - mov r1, _load_addr_text - cmp r0, r1 - -/* if load addr == run addr, no need to copy */ - jeq _s3_copy_rodata - mov r3, _e_text -_s3_copy_text_loop: - ld.ab r2, [r1, 4] - st.ab r2, [r0, 4] - cmp r0, r3 - jlt _s3_copy_text_loop -_s3_copy_rodata: - mov r0, _f_rodata - mov r1, _load_addr_rodata - cmp r0, r1 - -/* if load addr == run addr, no need to copy */ - jeq _s3_copy_data - mov r3, _e_rodata -_s3_copy_rodata_loop: - ld.ab r2, [r1, 4] - st.ab r2, [r0, 4] - cmp r0, r3 - jlt _s3_copy_rodata_loop -_s3_copy_data: - mov r0, _f_data - mov r1, _load_addr_data - cmp r0, r1 - jeq _s3_clear_bss - -/* if load addr == run addr, no need to copy */ - mov r3, _e_data -_s3_copy_data_loop: - ld.ab r2, [r1, 4] - st.ab r2, [r0, 4] - cmp r0, r3 - jlt _s3_copy_data_loop -_s3_clear_bss: - mov r0, _f_bss - mov r1, _e_bss - cmp r0, r1 - jge _arc_reset_call_main - mov r2, 0 -_s3_clear_bss_loop: - st.ab r2, [r0, 4] - cmp r0, r1 - jlt _s3_clear_bss_loop - -/* STAGE 3: go to next level initialization */ -_arc_reset_call_main: - - jl board_main /* board-level main */ - b _exit_loop - - .global _exit_loop - .global _exit_halt - .align 4 -_exit_halt: -_exit_loop: - flag AUX_STATUS_MASK_HALT - nop - nop - nop - b _exit_loop - -#if defined(__MW__) - .global arc_mwdt_init, arc_mwdt_fini - .section ".init",text -arc_mwdt_init: - .cfa_bf arc_mwdt_init - push %blink - .cfa_push {%blink} - - .section ".init$999999", text, 1, 2, check_text_align=0 - pop %blink - .cfa_pop {%blink} - j [%blink] - .cfa_ef - - .section ".fini", text -arc_mwdt_fini: - .cfa_bf _fini - push %blink - .cfa_push {%blink} - - .section ".fini$999999", text, 1, 2, check_text_align=0 - pop %blink - .cfa_pop {%blink} - j [%blink] - .cfa_ef -#endif -/** @endcond */ - -/** }@*/ diff --git a/platform/vendor_bsp/embarc_bsp/board/board.c b/platform/vendor_bsp/embarc_bsp/board/board.c deleted file mode 100644 index d95ee740..00000000 --- a/platform/vendor_bsp/embarc_bsp/board/board.c +++ /dev/null @@ -1,259 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "embARC.h" -#include "embARC_debug.h" - -#define MAX_SYS_COUNTER_VALUE (0xffffffff) - -#ifndef BOARD_SYS_TIMER_HZ -#define BOARD_SYS_TIMER_HZ (1000) -#endif - -#ifndef EMBARC_BANNER_TYPE -#define EMBARC_BANNER_TYPE 1 -#endif - -static const char *embarc_banner = -#if EMBARC_BANNER_TYPE == 1 - "----------------------------------------------------------- \r\n\ - ____ _ ____ \r\n\ -| _ \\ _____ _____ _ __ ___ __| | __ ) _ _ \r\n\ -| |_) / _ \\ \\ /\\ / / _ \\ '__/ _ \\/ _` | _ \\| | | | \r\n\ -| __/ (_) \\ V V / __/ | | __/ (_| | |_) | |_| | \r\n\ -|_| \\___/ \\_/\\_/ \\___|_| \\___|\\__,_|____/ \\__, | \r\n\ - |___/ \r\n\ - _ _ ____ ____ \r\n\ - ___ _ __ ___ | |__ / \\ | _ \\ / ___| \r\n\ - / _ \\ '_ ` _ \\| '_ \\ / _ \\ | |_) | | \r\n\ - | __/ | | | | | |_) / ___ \\| _ <| |___ \r\n\ - \\___|_| |_| |_|_.__/_/ \\_\\_| \\_\\\\____| \r\n\ ------------------------------------------------------------- \r\n\ -"; -#else - "-----------------------------------------------------------------------------------------------\r\n\ - _/_/_/ _/ _/_/_/ \r\n\ - _/ _/ _/_/ _/ _/ _/ _/_/ _/ _/_/ _/_/ _/_/_/ _/ _/ _/ _/ \r\n\ - _/_/_/ _/ _/ _/ _/ _/ _/_/_/_/ _/_/ _/_/_/_/ _/ _/ _/_/_/ _/ _/ \r\n\ - _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ \r\n\ - _/ _/_/ _/ _/ _/_/_/ _/ _/_/_/ _/_/_/ _/_/_/ _/_/_/ \r\n\ - _/ \r\n\ - _/_/ \r\n\ - _/ _/_/ _/_/_/ _/_/_/ \r\n\ - _/_/ _/_/_/ _/_/ _/_/_/ _/ _/ _/ _/ _/ \r\n\ - _/_/_/_/ _/ _/ _/ _/ _/ _/_/_/_/ _/_/_/ _/ \r\n\ - _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ \r\n\ - _/_/_/ _/ _/ _/ _/_/_/ _/ _/ _/ _/ _/_/_/ \r\n\ -------------------------------------------------------------------------------------------------\r\n\ -"; -#endif - -/** board timer interrupt reset count */ -static uint32_t cyc_hz_count = (BOARD_CPU_CLOCK / BOARD_SYS_TIMER_HZ); - -/** board timer counter in timer interrupt */ -static volatile uint64_t gl_sys_hz_cnt = 0; -/** board 1ms counter */ -static volatile uint32_t gl_ms_cnt = 0; - -#define HZ_COUNT_CONV(precision, base) ((precision) / (base)) - -/** - * @brief Board bare-metal timer interrupt. - * Interrupt frequency is based on the defined @ref BOARD_SYS_TIMER_HZ - */ -static void board_timer_isr(void *ptr) -{ - timer_int_clear(BOARD_SYS_TIMER_ID); - - board_timer_update(BOARD_SYS_TIMER_HZ); -} - -/** - * @brief Initialise bare-metal board timer and interrupt - * @details - * This function is called in @ref board_init, and - * it initializes the 1-MS timer interrupt for bare-metal mode - */ -static void board_timer_init(void) -{ - if (timer_present(BOARD_SYS_TIMER_ID)) { - int_disable(BOARD_SYS_TIMER_INTNO); /* disable first then enable */ - int_handler_install(BOARD_SYS_TIMER_INTNO, board_timer_isr); - timer_start(BOARD_SYS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc_hz_count); /* start 1ms timer interrupt */ - - int_enable(BOARD_SYS_TIMER_INTNO); - } -} - -static void platform_print_banner(void) -{ - EMBARC_PRINTF("%s\r\n", embarc_banner); - EMBARC_PRINTF("embARC Build Time: %s, %s\r\n", __DATE__, __TIME__); -#if defined(__GNU__) - EMBARC_PRINTF("Compiler Version: ARC GNU, %s\r\n", __VERSION__); -#else - EMBARC_PRINTF("Compiler Version: Metaware, %s\r\n\r\n", __VERSION__); -#endif -} - -EMBARC_WEAK void platform_main(void) -{ -#ifdef LIB_CONSOLE - xprintf_setup(); -#endif - platform_print_banner(); - arc_goto_main(0, NULL); -} - -EMBARC_WEAK void board_main(void) -{ -#if defined(__MW__) -/* Metaware toolchain C++ init */ - arc_mwdt_init(); -#elif defined(__GNU__) -/* ARC GNU toolchain C++ init */ - - arc_gnu_do_global_ctors_aux(); - arc_gnu_do_init_array_aux(); -#endif - /* init core level interrupt & exception management */ - exc_int_init(); - /* init cache */ - arc_cache_init(); - /* necessary board level init */ - board_init(); - /* Initialise bare-metal board timer and interrupt */ - board_timer_init(); - /* platform (e.g RTOS, baremetal)level init */ - platform_main(); -#if defined(__MW__) - arc_mwdt_fini(); -#elif defined(__GNU__) - arc_gnu_do_global_dtors_aux(); -#endif -} - -/** - * @brief Update timer counter and other MS period operation - * in cycling interrupt and must be called periodically. - * @param precision interrupt-period precision in Hz - */ -void board_timer_update(uint32_t precision) -{ - static uint32_t sys_hz_update = 0; - static uint32_t sys_ms_update = 0; - uint32_t hz_conv = 0; - - /** count sys hz */ - hz_conv = HZ_COUNT_CONV(precision, BOARD_SYS_TIMER_HZ); - sys_hz_update++; - if (sys_hz_update >= hz_conv) { - sys_hz_update = 0; - gl_sys_hz_cnt++; - } - - /** count ms */ - hz_conv = HZ_COUNT_CONV(precision, BOARD_SYS_TIMER_MS_HZ); - sys_ms_update++; - if (sys_ms_update >= hz_conv) { - sys_ms_update = 0; - gl_ms_cnt++; - } -} - -/** - * @brief Get current timer's counter value in ticks - * @retval Ticks count in 64 bit format - */ -uint64_t board_get_hwticks(void) -{ - uint32_t sub_ticks; - uint64_t total_ticks; - - timer_current(TIMER_0, &sub_ticks); - - total_ticks = (uint64_t)GET_CUR_MS() * (BOARD_CPU_CLOCK / BOARD_SYS_TIMER_HZ); - total_ticks += (uint64_t)sub_ticks; - - return total_ticks; -} - -/** - * @brief Get current passed us since timer init - * @retval us Count in 64 bit format - */ -uint64_t board_get_cur_us(void) -{ - uint32_t sub_us; - uint64_t total_us; - - timer_current(TIMER_0, &sub_us); - - sub_us = ((uint64_t)sub_us * 1000000) / BOARD_CPU_CLOCK; - total_us = ((uint64_t)GET_CUR_MS()) * 1000 + (uint64_t)sub_us; - - return total_us; -} - -/** - * @brief Get current passed ms since timer init - * @retval ms Count in 32 bit format - */ -uint32_t board_get_cur_ms(void) -{ - return gl_ms_cnt; -} - -/** - * @brief Get board timer counter in timer interrupt - * @retval Count in 64 bit format - */ -uint64_t board_get_cur_syshz(void) -{ - return gl_sys_hz_cnt; -} - -/** - * @brief Function for delaying execution for number of milliseconds - * @details - * This function needs a 1-MS timer interrupt to work. - * For bare-metal, it is implemented in this file. - * @param ms Delay in milliseconds - */ -void board_delay_ms(uint32_t ms) -{ - uint64_t start_us, us_delayed; - - us_delayed = ((uint64_t)ms * 1000); - start_us = board_get_cur_us(); - while ((board_get_cur_us() - start_us) < us_delayed) { - ; - } -} diff --git a/platform/vendor_bsp/embarc_bsp/board/board.h b/platform/vendor_bsp/embarc_bsp/board/board.h deleted file mode 100644 index b3411372..00000000 --- a/platform/vendor_bsp/embarc_bsp/board/board.h +++ /dev/null @@ -1,106 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/** - * - * @file - * @ingroup BOARD_COMMON - * @brief Common board definitions used with all boards - * @details - * - This header file will contain board related settings for different boards. - * - Each board configurations are put in its own header file, like emsk/emsk.h - * - If you want to change the configuration, you need to go to related header file, e.g. - * if you want to change EMSK board settings, you need to go to emsk/emsk.h - */ - -/** - * @addtogroup BOARD_COMMON - * @{ - */ -#ifndef H_BOARD -#define H_BOARD -/** - * @todo add comments and documents to describe the macros - * @note the following macros must use the same name, because - * they are used by middleware and other applications - */ -/** here is a sample of EMSK board resource definitions */ -#ifdef BOARD_EMSK -#include "emsk/emsk.h" -#endif /* BOARD_EMSK */ - -/** you can add your board configuration as BOARD_EMSK defined up */ - -/** nsim related definition */ -#ifdef BOARD_NSIM -#include "nsim.h" -#endif /* BOARD_NSIM */ - -#ifdef BOARD_AXS -#include "axs/axs.h" -#endif /* BOARD_AXS */ - -#ifdef BOARD_HSDK -#include "hsdk/hsdk.h" -#endif /* BOARD_HSDK */ - -#ifdef BOARD_IOTDK -#include "iotdk/iotdk.h" -#endif /* BOARD_IOTDK */ - -#ifdef BOARD_EMSDP -#include "emsdp/emsdp.h" -#endif /* BOARD_EMDK */ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void board_init(void); -extern void board_timer_update(uint32_t precision); -extern void board_delay_ms(uint32_t ms); -extern uint64_t board_get_hwticks(void); -extern uint64_t board_get_cur_us(void); -extern uint64_t board_get_cur_syshz(void); -extern uint32_t board_get_cur_ms(void); -extern void platform_main(void); -extern void board_main(void); - -#ifdef __cplusplus -} -#endif - -#define GET_CUR_SYSHZ() bord_get_cur_syshz() -#define GET_CUR_MS() board_get_cur_ms() -#define GET_CUR_US() board_get_cur_us() -#define GET_CUR_HWTICKS() board_get_hwticks() - -#endif /* H_BOARD */ - -/** @} end of group BOARD_COMMON */ diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/gpio/dw_gpio.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/gpio/dw_gpio.c deleted file mode 100644 index c9335616..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/gpio/dw_gpio.c +++ /dev/null @@ -1,539 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "arc/arc_exception.h" - -#include "device/designware/dw_gpio.h" - -/** check expressions used in DesignWare GPIO driver implementation */ -#define DW_GPIO_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of uart info object */ -#define VALID_CHK_GPIO_INFO_OBJECT(gpioinfo_obj_ptr) { \ - DW_GPIO_CHECK_EXP((gpioinfo_obj_ptr) != NULL, E_OBJ); \ - DW_GPIO_CHECK_EXP(((gpioinfo_obj_ptr)->gpio_ctrl) != NULL, E_OBJ); \ -} -#endif - -/** - * @defgroup DEVICE_DW_GPIO_STATIC DesignWare GPIO Driver Static Functions - * @ingroup DEVICE_DW_GPIO - * @brief Static or inline functions, variables for DesignWare GPIO handle GPIO operations, - * only used in this file. - * @{ - */ - -/** - * @fn uint32_t dw_gpio_read_ext(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_read_ext(DW_GPIO_PORT_PTR port) -{ - return port->regs->EXT_PORTS[port->no]; -} - -/** - * @fn uint32_t dw_gpio_read_dir(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_read_dir(DW_GPIO_PORT_PTR port) -{ - return port->regs->SWPORTS[port->no].DDR; -} - -/** - * @fn uint32_t dw_gpio_read_dr(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_read_dr(DW_GPIO_PORT_PTR port) -{ - return port->regs->SWPORTS[port->no].DR; -} - -/** - * @fn uint32_t dw_gpio_read_mthd(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_read_mthd(DW_GPIO_PORT_PTR port) -{ - return port->regs->INTEN; -} - -/** - * @fn void dw_gpio_int_enable(DW_GPIO_PORT_PTR port, uint32_t bit_mask) - */ -Inline void dw_gpio_int_enable(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTEN |= bit_mask; -} - -/** - * @fn void dw_gpio_int_disable(DW_GPIO_PORT_PTR port, uint32_t bit_mask) - */ -Inline void dw_gpio_int_disable(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTEN &= (~bit_mask); -} - -/** - * @fn void dw_gpio_int_mask(DW_GPIO_PORT_PTR port, uint32_t bit_mask) - */ -Inline void dw_gpio_int_mask(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTMASK |= bit_mask; -} - -/** - * @fn void dw_gpio_int_unmask(DW_GPIO_PORT_PTR port, uint32_t bit_mask) - */ -Inline void dw_gpio_int_unmask(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTMASK &= (~bit_mask); -} - -/** - * @fn uint32_t dw_gpio_int_read_level(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_int_read_level(DW_GPIO_PORT_PTR port) -{ - return port->regs->INTTYPE_LEVEL; -} - -/** - * @fn uint32_t dw_gpio_int_read_polarity(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_int_read_polarity(DW_GPIO_PORT_PTR port) -{ - return port->regs->INT_POLARITY; -} - -/** - * @fn uint32_t dw_gpio_int_read_debounce(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_int_read_debounce(DW_GPIO_PORT_PTR port) -{ - return port->regs->DEBOUNCE; -} - -/** - * @fn uint32_t dw_gpio_int_read_status(DW_GPIO_PORT_PTR port) - */ -Inline uint32_t dw_gpio_int_read_status(DW_GPIO_PORT_PTR port) -{ - return port->regs->INTSTATUS; -} - -/** - * @fn void dw_gpio_int_clear(DW_GPIO_PORT_PTR port, uint32_t bit_mask) - */ -Inline void dw_gpio_int_clear(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->PORTA_EOI = bit_mask; -} - -static void dw_gpio_int_write_level(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_level) -{ - uint32_t reg_val; - - reg_val = port->regs->INTTYPE_LEVEL; - reg_val &= (~bit_mask); - bit_level &= bit_mask; - reg_val |= bit_level; - - port->regs->INTTYPE_LEVEL = reg_val; -} - -static void dw_gpio_int_write_polarity(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_polarity) -{ - uint32_t reg_val; - - reg_val = port->regs->INT_POLARITY; - - reg_val &= (~bit_mask); - bit_polarity &= bit_mask; - reg_val |= bit_polarity; - - port->regs->INT_POLARITY = reg_val; -} - -static void dw_gpio_int_write_debounce(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_debounce) -{ - uint32_t reg_val; - - reg_val = port->regs->DEBOUNCE; - - reg_val &= (~bit_mask); - bit_debounce &= bit_mask; - reg_val |= bit_debounce; - - port->regs->DEBOUNCE = reg_val; -} - -static void dw_gpio_set_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg) -{ - dw_gpio_int_write_level(port, int_cfg->int_bit_mask, int_cfg->int_bit_type); - dw_gpio_int_write_polarity(port, int_cfg->int_bit_mask, int_cfg->int_bit_polarity); - dw_gpio_int_write_debounce(port, int_cfg->int_bit_mask, int_cfg->int_bit_debounce); -} - -static void dw_gpio_get_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg) -{ - int_cfg->int_bit_type = dw_gpio_int_read_level(port) & int_cfg->int_bit_mask; - int_cfg->int_bit_polarity = dw_gpio_int_read_polarity(port) & int_cfg->int_bit_mask; - int_cfg->int_bit_debounce = dw_gpio_int_read_debounce(port) & int_cfg->int_bit_mask; -} - -static void dw_gpio_write_dr(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val) -{ - uint32_t temp_reg; - - temp_reg = port->regs->SWPORTS[port->no].DR; - temp_reg &= ~bit_mask; - val &= bit_mask; - temp_reg |= val; - - port->regs->SWPORTS[port->no].DR = temp_reg; -} - -static void dw_gpio_toggle_dr(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - uint32_t temp_reg1, temp_reg2; - - temp_reg1 = port->regs->SWPORTS[port->no].DR; - // save unmasked bits value - temp_reg2 = temp_reg1 & (~bit_mask); - // toggle masked bits value - temp_reg1 = (~temp_reg1) & bit_mask; - // combine both masked and unmasked bits - temp_reg1 |= temp_reg2; - - port->regs->SWPORTS[port->no].DR = temp_reg1; -} - -static void dw_gpio_write_dir(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val) -{ - uint32_t temp_reg; - - temp_reg = port->regs->SWPORTS[port->no].DDR; - temp_reg &= ~bit_mask; - val &= bit_mask; - temp_reg |= val; - - port->regs->SWPORTS[port->no].DDR = temp_reg; -} - -static uint32_t dw_gpio_read_val(DW_GPIO_PORT_PTR port) -{ - uint32_t val; - - val = dw_gpio_read_ext(port) & (~dw_gpio_read_dir(port)); - val |= dw_gpio_read_dr(port) & dw_gpio_read_dir(port); - - return val; -} - -/** @} end of group DEVICE_DW_GPIO_STATIC */ - -/* interface for DEV_GPIO */ -/** Open designware gpio device with specified io direction configuration */ -int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - - port_info_ptr->opn_cnt++; - if (port_info_ptr->opn_cnt > 1) { /* opened before */ - if (dir == port_info_ptr->direction) { /* direction is the same */ - return E_OK; - } else { /* open with different direction */ - return E_OPNED; - } - } - - dw_gpio_write_dir(port, port->valid_bit_mask, dir); - - if (port->no == DW_GPIO_PORT_A) { - dw_gpio_int_clear(port, DW_GPIO_MASK_ALL); - dw_gpio_int_disable(port, DW_GPIO_MASK_ALL); - dw_gpio_int_unmask(port, DW_GPIO_MASK_ALL); - /* install gpio interrupt handler */ - if (port->intno != DW_GPIO_INVALID_INTNO) { // Handle Bit ISR 1-1 map to vector table - int_handler_install(port->intno, port->int_handler); - int_disable(port->intno); - } - /** Set int type, int polarity and debounce configuration to default settings of device gpio */ - dw_gpio_set_int_cfg(port, (DEV_GPIO_INT_CFG *)(&gpio_int_cfg_default)); - port_info_ptr->method = dw_gpio_read_mthd(port); - } else { - port_info_ptr->method = DEV_GPIO_BITS_MTHD_DEFAULT; - } - - dw_gpio_write_dr(port, port->valid_bit_mask, 0); - - port_info_ptr->direction = dir; - port_info_ptr->extra = NULL; - port_info_ptr->bitofs = 0; - -error_exit: - return ercd; -} - -/** Close designware gpio device */ -int32_t dw_gpio_close(DEV_GPIO *gpio_obj) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_OK); - - port_info_ptr->opn_cnt--; - port_info_ptr->bitofs = 0; - if (port_info_ptr->opn_cnt == 0) { - dw_gpio_write_dr(port, port->valid_bit_mask, 0); - dw_gpio_write_dir(port, port->valid_bit_mask, 0); - if (port->no == DW_GPIO_PORT_A) { - dw_gpio_int_clear(port, DW_GPIO_MASK_ALL); - dw_gpio_int_disable(port, DW_GPIO_MASK_ALL); - if (port->intno != DW_GPIO_INVALID_INTNO) { - int_disable(port->intno); - } - } - - port_info_ptr->direction = 0; - port_info_ptr->method = 0; - port_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** Read designware gpio device value */ -int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - - DW_GPIO_CHECK_EXP(val != NULL, E_PAR); - - // *val = dw_gpio_read_ext(port) & mask; - *val = dw_gpio_read_val(port) & mask; - -error_exit: - return ercd; -} - -/** Write designware gpio device value */ -int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - - dw_gpio_write_dr(port, mask, val); - -error_exit: - return ercd; -} - -/** Control designware gpio device */ -int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - - uint32_t val32; /** to receive unsigned int value */ - - if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_INPUT) { - val32 = (uint32_t)param; - dw_gpio_write_dir(port, val32, DW_GPIO_INPUT_ALL); - port_info_ptr->direction = dw_gpio_read_dir(port); - } else if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_OUTPUT) { - val32 = (uint32_t)param; - dw_gpio_write_dir(port, val32, DW_GPIO_OUTPUT_ALL); - port_info_ptr->direction = dw_gpio_read_dir(port); - } else if (ctrl_cmd == GPIO_CMD_GET_BIT_DIR) { - DW_GPIO_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_info_ptr->direction = dw_gpio_read_dir(port); - *((int32_t *)param) = port_info_ptr->direction; - } else if (ctrl_cmd == GPIO_CMD_TOGGLE_BITS) { - val32 = (uint32_t)param; - // Only mask the output bits - val32 &= port_info_ptr->direction; - dw_gpio_toggle_dr(port, val32); - } else { - DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT); - /* output pin cannot be used as interrupt */ - DEV_GPIO_INT_CFG *gpio_int_cfg; - DEV_GPIO_BIT_ISR *port_bit_isr; - - switch (ctrl_cmd) { - case GPIO_CMD_SET_BIT_INT_CFG: - DW_GPIO_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - gpio_int_cfg = (DEV_GPIO_INT_CFG *)param; - dw_gpio_set_int_cfg(port, gpio_int_cfg); - break; - case GPIO_CMD_GET_BIT_INT_CFG: - DW_GPIO_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - gpio_int_cfg = (DEV_GPIO_INT_CFG *)param; - /** read configuration, each bit stands for different configuration */ - dw_gpio_get_int_cfg(port, gpio_int_cfg); - break; - case GPIO_CMD_SET_BIT_ISR: - DW_GPIO_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_bit_isr = (DEV_GPIO_BIT_ISR *)param; - if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) { - port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs] = port_bit_isr->int_bit_handler; - } else { - ercd = E_PAR; - } - break; - case GPIO_CMD_GET_BIT_ISR: - DW_GPIO_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_bit_isr = (DEV_GPIO_BIT_ISR *)param; - if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) { - port_bit_isr->int_bit_handler = port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs]; - } else { - ercd = E_PAR; - } - break; - case GPIO_CMD_ENA_BIT_INT: - val32 = (uint32_t)param; - dw_gpio_int_enable(port, val32); - port_info_ptr->method = dw_gpio_read_mthd(port); - if (port_info_ptr->method) { - if (port->intno != DW_GPIO_INVALID_INTNO) { - int_enable(port->intno); - } - } - break; - case GPIO_CMD_DIS_BIT_INT: - val32 = (uint32_t)param; - dw_gpio_int_disable(port, val32); - port_info_ptr->method = dw_gpio_read_mthd(port); - if (port_info_ptr->method == 0) { - if (port->intno != DW_GPIO_INVALID_INTNO) { - int_disable(port->intno); - } - } - break; - case GPIO_CMD_GET_BIT_MTHD: - DW_GPIO_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_info_ptr->method = dw_gpio_read_mthd(port); - *((int32_t *)param) = port_info_ptr->method; - break; - default: - ercd = E_NOSPT; - break; - } - } -error_exit: - return ercd; -} - -/** designware gpio interrupt process */ -int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT); - - uint32_t i, gpio_bit_isr_state; - uint32_t max_int_bit_count = 0; - - /** read interrupt status */ - gpio_bit_isr_state = dw_gpio_int_read_status(port); - - if (port->gpio_bit_isr) { - max_int_bit_count = (port->gpio_bit_isr->int_bit_max_cnt); - } else { - /* this code cannot never be reached */ - /* coverity[dead_error_line] */ - dw_gpio_int_clear(port, gpio_bit_isr_state); - } - - for (i = 0; i < max_int_bit_count; i++) { - if (gpio_bit_isr_state & (1 << i)) { - /* this bit interrupt enabled */ - port_info_ptr->bitofs = i; - if (port->gpio_bit_isr->int_bit_handler_ptr[i]) { - port->gpio_bit_isr->int_bit_handler_ptr[i](gpio_obj); - } - dw_gpio_int_clear(port, (1 << i)); /** clear this bit interrupt */ - } - } - -error_exit: - return ercd; -} \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/i2s/dw_i2s.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/i2s/dw_i2s.c deleted file mode 100644 index 0b7b9f0f..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/i2s/dw_i2s.c +++ /dev/null @@ -1,2142 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include - -#include "embARC_toolchain.h" -#include "embARC_error.h" - -#include "arc/arc_exception.h" - -#include "device/designware/dw_i2s_hal.h" -#include "device/designware/dw_i2s.h" - -/** check expressions used in DesignWare I2S driver implementation */ -#define DW_I2S_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#define DW_I2S_CHANNEL_CHECK(val, channels) (((val == DW_I2S_CHANNEL0) && (channels & DW_I2S_CHANNEL0_SUPPORTED)) || \ - ((val == DW_I2S_CHANNEL1) && (channels & DW_I2S_CHANNEL1_SUPPORTED)) || \ - ((val == DW_I2S_CHANNEL2) && (channels & DW_I2S_CHANNEL2_SUPPORTED)) || \ - ((val == DW_I2S_CHANNEL3) && (channels & DW_I2S_CHANNEL3_SUPPORTED))) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of I2S info object */ -#define VALID_CHK_I2S_INFO_OBJECT(i2sinfo_obj_ptr) { \ - DW_I2S_CHECK_EXP((i2sinfo_obj_ptr) != NULL, E_OBJ); \ - DW_I2S_CHECK_EXP(((i2sinfo_obj_ptr)->i2s_ctrl) != NULL, E_OBJ); \ -} -#endif - -/** - * @name DesignWare I2S Interrupt Callback Routine Select Marcos - * @brief DesignWare I2S interrupt callback routines select macros definitions - * @{ - */ -#define DW_I2S_TX_RDY_SND (0) /*!< TX ready to send callback */ -#define DW_I2S_RX_RDY_RCV (1) /*!< RX ready to receive callback */ - -/** @} */ - -/** - * @defgroup DEVICE_DW_I2S_STATIC DesignWare I2S Driver Static Functions - * @ingroup DEVICE_DW_I2S - * @brief Static or inline functions, variables for DesignWare I2S handle I2S operations, - * only used in this file. - * @{ - */ - -/** - * @fn void dw_i2s_rx_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Disable DesignWare I2S RX and flush all FIFOs - */ -Inline void dw_i2s_rx_disable(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - i2s_rx_reg_ptr->IER &= ~DW_I2S_IER_IEN; -} - -/** - * @fn void dw_i2s_rx_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Enable DesignWare I2S RX IP - */ -Inline void dw_i2s_rx_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - i2s_rx_reg_ptr->IER |= DW_I2S_IER_IEN; -} - -/** - * @fn void dw_i2s_tx_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Disable DesignWare I2S TX and flush all FIFOs - */ -Inline void dw_i2s_tx_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - i2s_tx_reg_ptr->IER &= ~DW_I2S_IER_IEN; -} - -/** - * @fn void dw_i2s_tx_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Enable DesignWare I2S TX IP - */ -Inline void dw_i2s_tx_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - i2s_tx_reg_ptr->IER |= DW_I2S_IER_IEN; -} - -/** - * @fn void dw_i2s_rx_block_disable(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Disable DesignWare I2S RX block - */ -Inline void dw_i2s_rx_block_disable(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - i2s_rx_reg_ptr->IRER &= ~DW_I2S_IRER_RXEN; -} - -/** - * @fn void dw_i2s_rx_block_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Enable DesignWare I2S RX block - */ -Inline void dw_i2s_rx_block_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - i2s_rx_reg_ptr->IRER |= DW_I2S_IRER_RXEN; -} - -/** - * @fn void dw_i2s_tx_block_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Disable DesignWare I2S TX block - */ -Inline void dw_i2s_tx_block_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - i2s_tx_reg_ptr->ITER &= ~DW_I2S_ITER_TXEN; -} - -/** - * @fn void dw_i2s_tx_block_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Enable DesignWare I2S TX block - */ -Inline void dw_i2s_tx_block_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - i2s_tx_reg_ptr->ITER |= DW_I2S_ITER_TXEN; -} - -/** - * @fn void dw_i2s_rx_channel_disable(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) - * @brief Disable DesignWare I2S RX channel - */ -Inline void dw_i2s_rx_channel_disable(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_rx_reg_ptr->RER0 &= ~DW_I2S_RERX_RXCHENX; - break; - case DW_I2S_CHANNEL1: - i2s_rx_reg_ptr->RER1 &= ~DW_I2S_RERX_RXCHENX; - break; - case DW_I2S_CHANNEL2: - i2s_rx_reg_ptr->RER2 &= ~DW_I2S_RERX_RXCHENX; - break; - case DW_I2S_CHANNEL3: - i2s_rx_reg_ptr->RER3 &= ~DW_I2S_RERX_RXCHENX; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_rx_channel_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) - * @brief Enable DesignWare I2S RX channel - */ -Inline void dw_i2s_rx_channel_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_rx_reg_ptr->RER0 |= DW_I2S_RERX_RXCHENX; - break; - case DW_I2S_CHANNEL1: - i2s_rx_reg_ptr->RER1 |= DW_I2S_RERX_RXCHENX; - break; - case DW_I2S_CHANNEL2: - i2s_rx_reg_ptr->RER2 |= DW_I2S_RERX_RXCHENX; - break; - case DW_I2S_CHANNEL3: - i2s_rx_reg_ptr->RER3 |= DW_I2S_RERX_RXCHENX; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_tx_channel_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) - * @brief Disable DesignWare I2S TX channel - */ -Inline void dw_i2s_tx_channel_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_tx_reg_ptr->TER0 &= ~DW_I2S_TERX_TXCHENX; - break; - case DW_I2S_CHANNEL1: - i2s_tx_reg_ptr->TER1 &= ~DW_I2S_TERX_TXCHENX; - break; - case DW_I2S_CHANNEL2: - i2s_tx_reg_ptr->TER2 &= ~DW_I2S_TERX_TXCHENX; - break; - case DW_I2S_CHANNEL3: - i2s_tx_reg_ptr->TER3 &= ~DW_I2S_TERX_TXCHENX; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_tx_channel_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) - * @brief Enable DesignWare I2S TX channel - */ -Inline void dw_i2s_tx_channel_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) -{ - uint32_t tar_channel = channel; - - switch (tar_channel) { - case DW_I2S_CHANNEL0: - i2s_tx_reg_ptr->TER0 |= DW_I2S_TERX_TXCHENX; - break; - case DW_I2S_CHANNEL1: - i2s_tx_reg_ptr->TER1 |= DW_I2S_TERX_TXCHENX; - break; - case DW_I2S_CHANNEL2: - i2s_tx_reg_ptr->TER2 |= DW_I2S_TERX_TXCHENX; - break; - case DW_I2S_CHANNEL3: - i2s_tx_reg_ptr->TER3 |= DW_I2S_TERX_TXCHENX; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_rx_clear_overrun_interrupt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) - * @brief Clear DesignWare I2S RX overrun interrupt - */ -Inline void dw_i2s_rx_clear_overrun_interrupt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - (void)i2s_rx_reg_ptr->ROR0; - break; - case DW_I2S_CHANNEL1: - (void)i2s_rx_reg_ptr->ROR1; - break; - case DW_I2S_CHANNEL2: - (void)i2s_rx_reg_ptr->ROR2; - break; - case DW_I2S_CHANNEL3: - (void)i2s_rx_reg_ptr->ROR3; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_tx_clear_overrun_interrupt(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) - * @brief Clear DesignWare I2S TX overrun interrupt - */ -Inline void dw_i2s_tx_clear_overrun_interrupt(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - (void)i2s_tx_reg_ptr->TOR0; - break; - case DW_I2S_CHANNEL1: - (void)i2s_tx_reg_ptr->TOR1; - break; - case DW_I2S_CHANNEL2: - (void)i2s_tx_reg_ptr->TOR2; - break; - case DW_I2S_CHANNEL3: - (void)i2s_tx_reg_ptr->TOR3; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_rx_unmask_interrupt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t mask, uint32_t channel) - * @brief Enable DesignWare I2S RX bit interrupt with mask - */ -Inline void dw_i2s_rx_unmask_interrupt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t mask, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_rx_reg_ptr->IMR0 &= ~mask; - break; - case DW_I2S_CHANNEL1: - i2s_rx_reg_ptr->IMR1 &= ~mask; - break; - case DW_I2S_CHANNEL2: - i2s_rx_reg_ptr->IMR2 &= ~mask; - break; - case DW_I2S_CHANNEL3: - i2s_rx_reg_ptr->IMR3 &= ~mask; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_rx_mask_interrupt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t mask, uint32_t channel) - * @brief Disable DesignWare I2S RX bit interrupt with mask - */ -Inline void dw_i2s_rx_mask_interrupt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t mask, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_rx_reg_ptr->IMR0 |= mask; - break; - case DW_I2S_CHANNEL1: - i2s_rx_reg_ptr->IMR1 |= mask; - break; - case DW_I2S_CHANNEL2: - i2s_rx_reg_ptr->IMR2 |= mask; - break; - case DW_I2S_CHANNEL3: - i2s_rx_reg_ptr->IMR3 |= mask; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_tx_unmask_interrupt(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t mask, uint32_t channel) - * @brief Enable DesignWare I2S TX bit interrupt with mask - */ -Inline void dw_i2s_tx_unmask_interrupt(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t mask, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_tx_reg_ptr->IMR0 &= ~mask; - break; - case DW_I2S_CHANNEL1: - i2s_tx_reg_ptr->IMR1 &= ~mask; - break; - case DW_I2S_CHANNEL2: - i2s_tx_reg_ptr->IMR2 &= ~mask; - break; - case DW_I2S_CHANNEL3: - i2s_tx_reg_ptr->IMR3 &= ~mask; - break; - default: - break; - } -} - -/** - * @fn void dw_i2s_tx_mask_interrupt(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t mask, uint32_t channel) - * @brief Disable DesignWare I2S TX bit interrupt with mask - */ -Inline void dw_i2s_tx_mask_interrupt(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t mask, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_tx_reg_ptr->IMR0 |= mask; - break; - case DW_I2S_CHANNEL1: - i2s_tx_reg_ptr->IMR1 |= mask; - break; - case DW_I2S_CHANNEL2: - i2s_tx_reg_ptr->IMR2 |= mask; - break; - case DW_I2S_CHANNEL3: - i2s_tx_reg_ptr->IMR3 |= mask; - break; - default: - break; - } -} - -/** - * @fn uint32_t dw_i2s_tx_get_txchet(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) - * @brief Get DesignWare I2S Transmit Channel Empty Trigger (TXCHET) - */ -Inline uint32_t dw_i2s_tx_get_txchet(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t channel) -{ - uint32_t len = 0; - - switch (channel) { - case DW_I2S_CHANNEL0: - len = i2s_tx_reg_ptr->TFCR0 & 0x0f; - break; - case DW_I2S_CHANNEL1: - len = i2s_tx_reg_ptr->TFCR1 & 0x0f; - break; - case DW_I2S_CHANNEL2: - len = i2s_tx_reg_ptr->TFCR2 & 0x0f; - break; - case DW_I2S_CHANNEL3: - len = i2s_tx_reg_ptr->TFCR3 & 0x0f; - break; - default: - break; - } - return len; -} - -/** - * @fn void dw_i2s_tx_set_txchet(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t level, uint32_t channel) - * @brief Set DesignWare I2S Transmit Channel Empty Trigger (TXCHET) - */ -Inline void dw_i2s_tx_set_txchet(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t level, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_tx_reg_ptr->TFCR0 = level & 0x0f; - break; - case DW_I2S_CHANNEL1: - i2s_tx_reg_ptr->TFCR1 = level & 0x0f; - break; - case DW_I2S_CHANNEL2: - i2s_tx_reg_ptr->TFCR2 = level & 0x0f; - break; - case DW_I2S_CHANNEL3: - i2s_tx_reg_ptr->TFCR3 = level & 0x0f; - break; - default: - break; - } -} - -/** - * @fn uint32_t dw_i2s_rx_get_rxchdt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) - * @brief Get DesignWare I2S Receive Channel Data Available Trigger (RXCHDT) - */ -Inline uint32_t dw_i2s_rx_get_rxchdt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t channel) -{ - uint32_t len = 0; - - switch (channel) { - case DW_I2S_CHANNEL0: - len = i2s_rx_reg_ptr->RFCR0 & 0x0f; - break; - case DW_I2S_CHANNEL1: - len = i2s_rx_reg_ptr->RFCR1 & 0x0f; - break; - case DW_I2S_CHANNEL2: - len = i2s_rx_reg_ptr->RFCR2 & 0x0f; - break; - case DW_I2S_CHANNEL3: - len = i2s_rx_reg_ptr->RFCR3 & 0x0f; - break; - default: - break; - } - return len; -} - -/** - * @fn void dw_i2s_rx_set_rxchdt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t level, uint32_t channel) - * @brief Set DesignWare I2S Receiver Channel Data Available Trigger (RXCHDT) - */ -Inline void dw_i2s_rx_set_rxchdt(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t level, uint32_t channel) -{ - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_rx_reg_ptr->RFCR0 = level & 0x0f; - break; - case DW_I2S_CHANNEL1: - i2s_rx_reg_ptr->RFCR1 = level & 0x0f; - break; - case DW_I2S_CHANNEL2: - i2s_rx_reg_ptr->RFCR2 = level & 0x0f; - break; - case DW_I2S_CHANNEL3: - i2s_rx_reg_ptr->RFCR3 = level & 0x0f; - break; - } -} - -/** - * @fn void dw_i2s_tx_clock_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Enable DesignWare I2S TX clock generation - */ -Inline void dw_i2s_tx_clock_enable(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - i2s_tx_reg_ptr->CER |= DW_I2S_CER_CLKEN; -} - -/** - * @fn void dw_i2s_tx_clock_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Disable DesignWare I2S TX clock generation - */ -Inline void dw_i2s_tx_clock_disable(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - i2s_tx_reg_ptr->CER &= ~DW_I2S_CER_CLKEN; -} - -/** - * @fn void dw_i2s_rx_clock_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Enable DesignWare I2S RX clock generation - */ -Inline void dw_i2s_rx_clock_enable(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - i2s_rx_reg_ptr->CER |= DW_I2S_CER_CLKEN; -} - -/** - * @fn void dw_i2s_rx_clock_disable(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Disable DesignWare I2S RX clock generation - */ -Inline void dw_i2s_rx_clock_disable(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - i2s_rx_reg_ptr->CER &= ~DW_I2S_CER_CLKEN; -} - -/** - * @fn void dw_i2s_tx_set_wss(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t word_select) - * @brief Set DesignWare I2S TX clock configuration word select line (ws_out) - */ -Inline void dw_i2s_tx_set_wss(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t word_select) -{ - i2s_tx_reg_ptr->CCR &= DW_I2S_CCR_WSS(0) | 0x07; - i2s_tx_reg_ptr->CCR |= DW_I2S_CCR_WSS(word_select); -} - -/** - * @fn void dw_i2s_rx_set_wss(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t word_select) - * @brief Set DesignWare I2S RX clock configuration word select line (ws_out) - */ -Inline void dw_i2s_rx_set_wss(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t word_select) -{ - i2s_rx_reg_ptr->CCR &= DW_I2S_CCR_WSS(0) | 0x07; - i2s_rx_reg_ptr->CCR |= DW_I2S_CCR_WSS(word_select); -} - -/** - * @fn void dw_i2s_rx_flush_fifo(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Reset DesignWare I2S RX FIFO, flush all the RX FIFOs (a self clearing bit) - */ -Inline void dw_i2s_rx_flush_fifo(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - i2s_rx_reg_ptr->RXFFR |= DW_I2S_RXFFR_RXFFR; -} - -/** - * @fn void dw_i2s_tx_flush_fifo(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Reset DesignWare I2S TX FIFO, flush all the TX FIFOs (a self clearing bit) - */ -Inline void dw_i2s_tx_flush_fifo(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - i2s_tx_reg_ptr->TXFFR |= DW_I2S_TXFFR_TXFFR; -} - -/** - * @fn uint32_t dw_i2s_rx_get_fifo_len(DW_I2S_RX_REG *i2s_rx_reg_ptr) - * @brief Get RX FIFO length - */ -Inline uint32_t dw_i2s_rx_get_fifo_len(DW_I2S_RX_REG *i2s_rx_reg_ptr) -{ - uint32_t len = 0; - - switch ((((i2s_rx_reg_ptr->I2S_COMP_PARAM_1) >> 2) & 0x03)) { - case 0: - len = 2; - break; - case 1: - len = 4; - break; - case 2: - len = 8; - break; - case 3: - len = 16; - break; - default: - break; - } - return len; -} - -/** - * @fn uint32_t dw_i2s_tx_get_fifo_len(DW_I2S_TX_REG *i2s_tx_reg_ptr) - * @brief Get TX FIFO length - */ -Inline uint32_t dw_i2s_tx_get_fifo_len(DW_I2S_TX_REG *i2s_tx_reg_ptr) -{ - uint32_t len = 0; - - switch ((((i2s_tx_reg_ptr->I2S_COMP_PARAM_1) >> 2) & 0x03)) { - case 0: - len = 2; - break; - case 1: - len = 4; - break; - case 2: - len = 8; - break; - case 3: - len = 16; - break; - default: - break; - } - return len; -} - -/** - * @fn void dw_i2s_tx_set_sclkg(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t clkg) - * @brief Set DesignWare I2S TX clock configuration SCLKG (gating of sclk) - */ -Inline void dw_i2s_tx_set_sclkg(DW_I2S_TX_REG *i2s_tx_reg_ptr, uint32_t clkg) -{ - i2s_tx_reg_ptr->CCR &= DW_I2S_CCR_SCLKG(0) | 0x18; - i2s_tx_reg_ptr->CCR |= DW_I2S_CCR_SCLKG(clkg); -} - -/** - * @fn void dw_i2s_rx_set_sclkg(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t clkg) - * @brief Set DesignWare I2S RX clock configuration SCLKG (gating of sclk) - */ -Inline void dw_i2s_rx_set_sclkg(DW_I2S_RX_REG *i2s_rx_reg_ptr, uint32_t clkg) -{ - i2s_rx_reg_ptr->CCR &= DW_I2S_CCR_SCLKG(0) | 0x18; - i2s_rx_reg_ptr->CCR |= DW_I2S_CCR_SCLKG(clkg); -} - -/** - * @fn uint32_t dw_i2s_get_wlen_bits(uint32_t resolution) - * @brief Set RX/TX WLEN - */ -Inline uint32_t dw_i2s_get_wlen_bits(uint32_t resolution) -{ - uint32_t wlen_bits = 0; - - switch (resolution) { - case I2S_AUD_DATA_NA: - wlen_bits = 0; - break; - case I2S_AUD_DATA_12B: - wlen_bits = 0x01; - break; - case I2S_AUD_DATA_16B: - wlen_bits = 0x02; - break; - case I2S_AUD_DATA_20B: - wlen_bits = 0x03; - break; - case I2S_AUD_DATA_24B: - wlen_bits = 0x04; - break; - case I2S_AUD_DATA_32B: - wlen_bits = 0x05; - break; - default: - wlen_bits = 0; - break; - } - return wlen_bits; -} -static void dw_i2s_rx_set_wlen(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - uint32_t wlen_bits; - DW_I2S_CONFIG *i2s_config_ptr; - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr; - DW_I2S_RX_REG *i2s_rx_reg_ptr; - - i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_reg_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - switch (channel) { - case DW_I2S_CHANNEL0: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[0]); - i2s_rx_reg_ptr->RCR0 = DW_I2S_RCRX_WLEN(wlen_bits); - break; - case DW_I2S_CHANNEL1: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[1]); - i2s_rx_reg_ptr->RCR1 = DW_I2S_RCRX_WLEN(wlen_bits); - break; - case DW_I2S_CHANNEL2: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[2]); - i2s_rx_reg_ptr->RCR2 = DW_I2S_RCRX_WLEN(wlen_bits); - break; - case DW_I2S_CHANNEL3: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[3]); - i2s_rx_reg_ptr->RCR3 = DW_I2S_RCRX_WLEN(wlen_bits); - break; - default: - break; - } -} -static void dw_i2s_tx_set_wlen(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - uint32_t wlen_bits; - DW_I2S_CONFIG *i2s_config_ptr; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr; - DW_I2S_TX_REG *i2s_tx_reg_ptr; - - i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_reg_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - switch (channel) { - case DW_I2S_CHANNEL0: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[0]); - i2s_tx_reg_ptr->TCR0 = DW_I2S_TCRX_WLEN(wlen_bits); - break; - case DW_I2S_CHANNEL1: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[1]); - i2s_tx_reg_ptr->TCR1 = DW_I2S_TCRX_WLEN(wlen_bits); - break; - case DW_I2S_CHANNEL2: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[2]); - i2s_tx_reg_ptr->TCR2 = DW_I2S_TCRX_WLEN(wlen_bits); - break; - case DW_I2S_CHANNEL3: - wlen_bits = dw_i2s_get_wlen_bits(i2s_config_ptr->data_res[3]); - i2s_tx_reg_ptr->TCR3 = DW_I2S_TCRX_WLEN(wlen_bits); - break; - default: - break; - } -} - -/* Disable I2S interrupt */ -static void dw_i2s_rx_disable_interrupt(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - uint16_t da_intr = 0; - uint16_t or_intr = 0; - DW_I2S_CONFIG *i2s_config_ptr; - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr; - DW_I2S_RX_REG *i2s_rx_reg_ptr; - - i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_reg_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - da_intr = i2s_config_ptr->intno[channel] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[channel] & 0xffff0000) >> 16; - /* disable I2S interrupt */ - dw_i2s_rx_mask_interrupt(i2s_rx_reg_ptr, DW_I2S_IMRX_RXFOM | DW_I2S_IMRX_RXDAM, channel); - if ((i2s_rx_ctrl_ptr->int_status[channel] & DW_I2S_GINT_ENABLE) == 1) { - i2s_rx_ctrl_ptr->int_status[channel] &= ~DW_I2S_GINT_ENABLE; - int_disable(da_intr); - int_disable(or_intr); - } -} -static void dw_i2s_tx_disable_interrupt(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - uint16_t da_intr = 0; - uint16_t or_intr = 0; - DW_I2S_CONFIG *i2s_config_ptr; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr; - DW_I2S_TX_REG *i2s_tx_reg_ptr; - - i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_reg_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - da_intr = i2s_config_ptr->intno[channel] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[channel] & 0xffff0000) >> 16; - /* disable I2S interrupt */ - dw_i2s_tx_mask_interrupt(i2s_tx_reg_ptr, DW_I2S_IMRX_TXFOM | DW_I2S_IMRX_TXFEM, channel); - if ((i2s_tx_ctrl_ptr->int_status[channel] & DW_I2S_GINT_ENABLE) == 1) { - i2s_tx_ctrl_ptr->int_status[channel] &= ~DW_I2S_GINT_ENABLE; - int_disable(da_intr); - int_disable(or_intr); - } -} - -/* Disable RX/TX device interrupt */ -static void dw_i2s_disable_dev_intr(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - dw_i2s_rx_disable_interrupt(i2s_info_ptr, channel); - } else { - dw_i2s_tx_disable_interrupt(i2s_info_ptr, channel); - } - -} - -/* Enable I2S interrupt */ -static void dw_i2s_rx_enable_interrupt(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - uint16_t da_intr = 0; - uint16_t or_intr = 0; - DW_I2S_CONFIG *i2s_config_ptr; - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr; - DW_I2S_RX_REG *i2s_rx_reg_ptr; - - i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_reg_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - da_intr = i2s_config_ptr->intno[channel] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[channel] & 0xffff0000) >> 16; - /* Unmask I2S interrupt */ - dw_i2s_rx_unmask_interrupt(i2s_rx_reg_ptr, DW_I2S_IMRX_RXFOM | DW_I2S_IMRX_RXDAM, channel); - if ((i2s_rx_ctrl_ptr->int_status[channel] & DW_I2S_GINT_ENABLE) == 0) { - i2s_rx_ctrl_ptr->int_status[channel] |= DW_I2S_GINT_ENABLE; - int_enable(da_intr); - int_enable(or_intr); - } -} -static void dw_i2s_tx_enable_interrupt(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - uint16_t da_intr = 0; - uint16_t or_intr = 0; - DW_I2S_CONFIG *i2s_config_ptr; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr; - DW_I2S_TX_REG *i2s_tx_reg_ptr; - - i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_reg_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - da_intr = i2s_config_ptr->intno[channel] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[channel] & 0xffff0000) >> 16; - /* Unmask I2S interrupt */ - dw_i2s_tx_unmask_interrupt(i2s_tx_reg_ptr, DW_I2S_IMRX_TXFOM | DW_I2S_IMRX_TXFEM, channel); - if ((i2s_tx_ctrl_ptr->int_status[channel] & DW_I2S_GINT_ENABLE) == 0) { - i2s_tx_ctrl_ptr->int_status[channel] |= DW_I2S_GINT_ENABLE; - int_enable(da_intr); - int_enable(or_intr); - } -} - -/* Enable RX/TX device interrupt */ -static void dw_i2s_enable_dev_intr(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - dw_i2s_rx_enable_interrupt(i2s_info_ptr, channel); - } else { - dw_i2s_tx_enable_interrupt(i2s_info_ptr, channel); - } -} - -/* Enable I2S device and channel */ -static void dw_i2s_enable_device(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - /* Enable I2S block */ - dw_i2s_rx_block_enable(i2s_rx_regs_ptr); - /* Enable target channel */ - dw_i2s_rx_channel_enable(i2s_rx_regs_ptr, channel); - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - /* Enable I2S block */ - dw_i2s_tx_block_enable(i2s_tx_regs_ptr); - /* Enable all available channels */ - dw_i2s_tx_channel_enable(i2s_tx_regs_ptr, channel); - } -} - -/* Disable I2S device and channel */ -static void dw_i2s_disable_device(DEV_I2S_INFO *i2s_info_ptr, uint32_t channel) -{ - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - /* Disable target channel */ - dw_i2s_rx_channel_disable(i2s_rx_regs_ptr, channel); - /* Disable I2S block */ - dw_i2s_rx_block_disable(i2s_rx_regs_ptr); - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - /* Disable all available channels */ - dw_i2s_tx_channel_disable(i2s_tx_regs_ptr, channel); - /* Disable I2S block */ - dw_i2s_tx_block_disable(i2s_tx_regs_ptr); - } -} - -/* Disable I2S device all available channel */ -static void dw_i2s_disable_device_all(DEV_I2S_INFO *i2s_info_ptr) -{ - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - uint32_t channels = i2s_config_ptr->channels; - - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - /* Disable all available channels */ - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - dw_i2s_rx_channel_disable(i2s_rx_regs_ptr, DW_I2S_CHANNEL0); - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - dw_i2s_rx_channel_disable(i2s_rx_regs_ptr, DW_I2S_CHANNEL1); - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - dw_i2s_rx_channel_disable(i2s_rx_regs_ptr, DW_I2S_CHANNEL2); - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - dw_i2s_rx_channel_disable(i2s_rx_regs_ptr, DW_I2S_CHANNEL3); - } - /* Disable I2S block */ - dw_i2s_rx_block_disable(i2s_rx_regs_ptr); - /* Not Disable I2S IP */ - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - /* Disable all available channels */ - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - dw_i2s_tx_channel_disable(i2s_tx_regs_ptr, DW_I2S_CHANNEL0); - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - dw_i2s_tx_channel_disable(i2s_tx_regs_ptr, DW_I2S_CHANNEL1); - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - dw_i2s_tx_channel_disable(i2s_tx_regs_ptr, DW_I2S_CHANNEL2); - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - dw_i2s_tx_channel_disable(i2s_tx_regs_ptr, DW_I2S_CHANNEL3); - } - /* Enable I2S block */ - dw_i2s_tx_block_disable(i2s_tx_regs_ptr); - /* Not Disable I2S IP */ - } -} - -/* Reset I2S device */ -static void dw_i2s_reset_device(DEV_I2S_INFO *i2s_info_ptr) -{ - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - uint32_t channels = i2s_config_ptr->channels; - - dw_i2s_disable_device_all(i2s_info_ptr); - i2s_info_ptr->cur_state = I2S_FREE; - i2s_info_ptr->err_state = I2S_ERR_NONE; - /* Clear FIFO overrun interrupt */ - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - /* Disable all available channels */ - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - dw_i2s_rx_clear_overrun_interrupt(i2s_rx_regs_ptr, DW_I2S_CHANNEL0); - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - dw_i2s_rx_clear_overrun_interrupt(i2s_rx_regs_ptr, DW_I2S_CHANNEL1); - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - dw_i2s_rx_clear_overrun_interrupt(i2s_rx_regs_ptr, DW_I2S_CHANNEL2); - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - dw_i2s_rx_clear_overrun_interrupt(i2s_rx_regs_ptr, DW_I2S_CHANNEL3); - } - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - /* Disable all available channels */ - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - dw_i2s_tx_clear_overrun_interrupt(i2s_tx_regs_ptr, DW_I2S_CHANNEL0); - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - dw_i2s_tx_clear_overrun_interrupt(i2s_tx_regs_ptr, DW_I2S_CHANNEL1); - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - dw_i2s_tx_clear_overrun_interrupt(i2s_tx_regs_ptr, DW_I2S_CHANNEL2); - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - dw_i2s_tx_clear_overrun_interrupt(i2s_tx_regs_ptr, DW_I2S_CHANNEL3); - } - } -} - -/* Flush FIFO */ -static void dw_i2s_flush(DEV_I2S_INFO *i2s_info_ptr) -{ - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - dw_i2s_rx_block_disable(i2s_rx_regs_ptr); - dw_i2s_rx_flush_fifo(i2s_rx_regs_ptr); - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - dw_i2s_tx_block_disable(i2s_tx_regs_ptr); - dw_i2s_tx_flush_fifo(i2s_tx_regs_ptr); - } -} - -/* Enable interrupt for all available channels */ -static void dw_i2s_enable_all_channel_intr(DEV_I2S_INFO *i2s_info_ptr) -{ - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - uint32_t channels = i2s_config_ptr->channels; - - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - dw_i2s_enable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL0); - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - dw_i2s_enable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL1); - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - dw_i2s_enable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL2); - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - dw_i2s_enable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL3); - } -} - -/* Disable interrupt for all available channels */ -static void dw_i2s_disable_all_channel_intr(DEV_I2S_INFO *i2s_info_ptr) -{ - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - uint32_t channels = i2s_config_ptr->channels; - - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL0); - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL1); - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL2); - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL3); - } -} - -/* Disable I2S send or receive interrupt in interrupt routine */ -static void dw_i2s_dis_cbr(DEV_I2S_INFO *i2s_info_ptr, uint32_t cbrtn, uint32_t channel) -{ - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - if (cbrtn == DW_I2S_RX_RDY_RCV) { - dw_i2s_rx_disable_interrupt(i2s_info_ptr, channel); - i2s_rx_ctrl_ptr->int_status[channel] &= ~DW_I2S_RXINT_ENABLE; - } - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - if (cbrtn == DW_I2S_TX_RDY_SND) { - dw_i2s_tx_disable_interrupt(i2s_info_ptr, channel); - i2s_tx_ctrl_ptr->int_status[channel] &= ~DW_I2S_TXINT_ENABLE; - } - } -} - -/* Write left holding register */ -static void dw_i2s_tx_write_left_hold_reg(DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr, uint32_t data, uint32_t channel) -{ - DW_I2S_TX_REG *i2s_tx_regs_ptr; - - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_tx_regs_ptr->LTHR0 = DW_I2S_LTHR0_LTHR0(data); - break; - /* Todo: add more channel support */ - default: - break; - } -} - -/* Write right holding register */ -static void dw_i2s_tx_write_right_hold_reg(DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr, uint32_t data, uint32_t channel) -{ - DW_I2S_TX_REG *i2s_tx_regs_ptr; - - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - switch (channel) { - case DW_I2S_CHANNEL0: - i2s_tx_regs_ptr->RTHR0 = DW_I2S_RTHR0_RTHR0(data); - break; - /* Todo: add more channel support */ - default: - break; - } -} - -/* Read left holding register */ -static void dw_i2s_rx_read_left_hold_reg(DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr, uint32_t *data, uint32_t channel) -{ - DW_I2S_RX_REG *i2s_rx_regs_ptr; - - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - switch (channel) { - case DW_I2S_CHANNEL0: - *data = (uint32_t)DW_I2S_LRBR0_LRBR0(i2s_rx_regs_ptr->LRBR0); - /* Todo: add more channel support */ - default: - break; - } -} - -/* Read right holding register */ -static void dw_i2s_rx_read_right_hold_reg(DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr, uint32_t *data, uint32_t channel) -{ - DW_I2S_RX_REG *i2s_rx_regs_ptr; - - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - switch (channel) { - case DW_I2S_CHANNEL0: - *data = (uint32_t)DW_I2S_RRBR0_RRBR0(i2s_rx_regs_ptr->RRBR0); - /* Todo: add more channel support */ - default: - break; - } -} - -/* - * @brief I2S TX write samples into FIFO - * @param[in] i2s_info_ptr Pointer to I2S device information - * @param[in] count Count of stereo data (two as left + right) - * @param[in] channel Target channel of transmitter - * @retval Remaining sample count for the next transmitting in TX FIFO - */ -static uint32_t dw_i2s_tx_write_samples(DEV_I2S_INFO *i2s_info_ptr, uint32_t count, uint32_t channel) -{ - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - - uint32_t empty_trig = dw_i2s_tx_get_txchet(i2s_tx_regs_ptr, channel); - uint32_t remain_cnt = 0; - uint32_t avail_cnt = i2s_tx_ctrl_ptr->dw_i2s_buf.len - i2s_tx_ctrl_ptr->dw_i2s_buf.ofs; - int32_t i = 0; - #ifdef DW_I2S_DATA_LENGTH_16 - uint16_t *buff = i2s_tx_ctrl_ptr->dw_i2s_buf.buf; - #else - uint32_t *buff = i2s_tx_ctrl_ptr->dw_i2s_buf.buf; - #endif - uint32_t count_pair = count >> 1; - - if (count_pair < avail_cnt) { /* enough space in TX FIFO */ - avail_cnt = count_pair; - remain_cnt = 0; - } else { /* remaining data */ - remain_cnt = count - avail_cnt * 2; - } - /* fill I2S buffer with REG buffer */ - for (i = 0; i < avail_cnt; i++) { - dw_i2s_tx_write_left_hold_reg(i2s_tx_ctrl_ptr, buff[2 * i], channel); - dw_i2s_tx_write_right_hold_reg(i2s_tx_ctrl_ptr, buff[1 + 2 * i], channel); - } - /*the ofs is used to judge the next number of data to send to fifos*/ - if (remain_cnt == 0) { - i2s_tx_ctrl_ptr->dw_i2s_buf.ofs = 0; - } else { - i2s_tx_ctrl_ptr->dw_i2s_buf.ofs = empty_trig; - } - - return remain_cnt; - -} - -/* - * @brief I2S RX read samples from FIFO - * @param[in] i2s_info_ptr Pointer to I2S device information - * @param[in] count Available count of stereo data (two as left + right) - * @param[in] channel Target channel of transmitter - * @retval Remaining count in the buffer - */ -static uint32_t dw_i2s_rx_read_samples(DEV_I2S_INFO *i2s_info_ptr, uint32_t count, uint32_t channel) -{ - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - - uint32_t avail_trig = dw_i2s_rx_get_rxchdt(i2s_rx_regs_ptr, channel); - uint32_t remain_cnt = 0; - uint32_t avail_cnt = avail_trig; - int32_t i = 0; - uint32_t buf = 0; -#ifdef DW_I2S_DATA_LENGTH_16 - uint16_t *buff = i2s_rx_ctrl_ptr->dw_i2s_buf.buf; -#else - uint32_t *buff = i2s_rx_ctrl_ptr->dw_i2s_buf.buf; -#endif - uint32_t count_pair = count >> 1; - - if (count_pair < avail_cnt) { /* not enough space in buffer */ - avail_cnt = count_pair; - remain_cnt = 0; - } else { /* remaining data */ - remain_cnt = count - avail_cnt * 2; - } - /* Read I2S buffer and send it to buff */ - for (i = 0; i < avail_cnt; i++) { -#ifdef DW_I2S_DATA_LENGTH_16 - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buf, channel); - buff[2 * i] = (uint16_t)buf; - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buf, channel); - buff[1 + 2 * i] = (uint16_t)buf; -#else - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buff[2 * i], channel); - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buff[1 + 2 * i], channel); -#endif - } - - /* accumulation of sending data count */ - i2s_rx_ctrl_ptr->dw_i2s_buf.ofs += avail_cnt; - - return remain_cnt; - -} - -/** @} end of group DEVICE_DW_I2S_STATIC */ - -static void delay(uint32_t delay_cycle) -{ - uint32_t i, j; - - for (j = 0; j < delay_cycle; j++) { - for (i = 0; i < 100; i++) { - arc_nop(); - } - } -} - -/* - * @brief I2S write data in interrupt - * @param[in] i2s_obj Pointer to I2S device - */ -static void dw_i2s_mst_int_write(DEV_I2S *i2s_obj) -{ - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - DW_I2S_TX_REG *i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - - uint32_t empty_trig = 16 - dw_i2s_tx_get_txchet(i2s_tx_regs_ptr, 0); - int32_t i = 0, buf_ofs = i2s_info_ptr->tx_buf.ofs * empty_trig; - int32_t count_pair; - -#ifdef DW_I2S_DATA_LENGTH_16 - uint16_t *buff = (uint16_t *)i2s_info_ptr->tx_buf.buf; -#else - uint32_t *buff = (uint32_t *)i2s_info_ptr->tx_buf.buf; -#endif - - dw_i2s_dis_cbr(i2s_info_ptr, DW_I2S_TX_RDY_SND, DW_I2S_CHANNEL0); - uint16_t isr0 = i2s_tx_regs_ptr->ISR0; - if (buff != NULL) { - if ((isr0 & DW_I2S_ISRX_TXFO) != 0) { - i2s_info_ptr->cur_state = I2S_FREE; - if (i2s_info_ptr->i2s_cbs.err_cb != NULL) { - i2s_info_ptr->i2s_cbs.err_cb(i2s_obj); - } - } - if ((isr0 & DW_I2S_ISRX_TXFE) != 0) { - if (i2s_info_ptr->tx_buf.len >= empty_trig * 2) { - /* fill I2S buffer with REG buffer */ - for (i = 0; i < empty_trig; i++) { - dw_i2s_tx_write_left_hold_reg(i2s_tx_ctrl_ptr, buff[2 * (i + buf_ofs)], DW_I2S_CHANNEL0); - dw_i2s_tx_write_right_hold_reg(i2s_tx_ctrl_ptr, buff[1 + 2 * (i + buf_ofs)], DW_I2S_CHANNEL0); - } - i2s_info_ptr->tx_buf.ofs += 1; - i2s_info_ptr->tx_buf.len -= empty_trig * 2; - dw_i2s_tx_clear_overrun_interrupt(i2s_tx_regs_ptr, DW_I2S_CHANNEL0); - dw_i2s_tx_enable_interrupt(i2s_info_ptr, DW_I2S_CHANNEL0); - } else { - count_pair = i2s_info_ptr->tx_buf.len >> 1; - for (i = 0; i < count_pair; i++) { - dw_i2s_tx_write_left_hold_reg(i2s_tx_ctrl_ptr, buff[2 * (i + buf_ofs)], DW_I2S_CHANNEL0); - dw_i2s_tx_write_right_hold_reg(i2s_tx_ctrl_ptr, buff[1 + 2 * (i + buf_ofs)], DW_I2S_CHANNEL0); - } - /* if the length of remainning data is less than empty_trig*2,fill 0 */ - for (i = count_pair; i < empty_trig; i++) { - dw_i2s_tx_write_left_hold_reg(i2s_tx_ctrl_ptr, 0, DW_I2S_CHANNEL0); - dw_i2s_tx_write_right_hold_reg(i2s_tx_ctrl_ptr, 0, DW_I2S_CHANNEL0); - } - i2s_info_ptr->tx_buf.len = 0; - dw_i2s_tx_clear_overrun_interrupt(i2s_tx_regs_ptr, DW_I2S_CHANNEL0); - } - /*the ofs is used to judge the next number of data to send to fifos*/ - // empty_trig = dw_i2s_tx_get_txchet(i2s_tx_regs_ptr, DW_I2S_CHANNEL0); - // i2s_tx_ctrl_ptr->dw_i2s_buf.ofs = empty_trig; - i2s_info_ptr->cur_state = I2S_FREE; - if ((i2s_info_ptr->tx_buf.len == 0) && (i2s_info_ptr->i2s_cbs.tx_cb != NULL)) { - i2s_info_ptr->i2s_cbs.tx_cb(i2s_obj); - } - } - } -} - -/* - * @brief I2S read data in interrupt - * @param[in] i2s_obj Pointer to I2S device - */ -static void dw_i2s_mst_int_rx(DEV_I2S *i2s_obj) -{ - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - DW_I2S_RX_REG *i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - - uint32_t empty_trig = dw_i2s_rx_get_rxchdt(i2s_rx_regs_ptr, 0), buf; - int32_t i = 0, buf_ofs = i2s_info_ptr->rx_buf.ofs * empty_trig; - int32_t count_pair; - -#ifdef DW_I2S_DATA_LENGTH_16 - uint16_t *buff = (uint16_t *)i2s_info_ptr->rx_buf.buf; -#else - uint32_t *buff = (uint32_t *)i2s_info_ptr->rx_buf.buf; -#endif - dw_i2s_dis_cbr(i2s_info_ptr, DW_I2S_RX_RDY_RCV, DW_I2S_CHANNEL0); - uint16_t isr0 = i2s_rx_regs_ptr->ISR0; - if (buff != NULL) { - /* over run interrupt,read all data in fifo */ - if ((isr0 & DW_I2S_ISRX_RXFO) != 0) { - i2s_info_ptr->cur_state = I2S_FREE; - for (i = 0; i < 16; i++) { -#ifdef DW_I2S_DATA_LENGTH_16 - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - buff[2 * (i + buf_ofs)] = (uint16_t)buf; - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - buff[1 + 2 * (i + buf_ofs)] = (uint16_t)buf; -#else - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buff[2 * (i + buf_ofs)], DW_I2S_CHANNEL0); - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buff[1 + 2 * (i + buf_ofs)], DW_I2S_CHANNEL0); -#endif - } - } - if ((isr0 & DW_I2S_ISRX_RXDA) != 0) { - if (i2s_info_ptr->rx_buf.len >= empty_trig * 2) { - for (i = 0; i < empty_trig; i++) { -#ifdef DW_I2S_DATA_LENGTH_16 - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - buff[2 * (i + buf_ofs)] = (uint16_t)buf; - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - buff[1 + 2 * (i + buf_ofs)] = (uint16_t)buf; -#else - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buff[2 * (i + buf_ofs)], DW_I2S_CHANNEL0); - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buff[1 + 2 * (i + buf_ofs)], DW_I2S_CHANNEL0); -#endif - } - i2s_info_ptr->rx_buf.ofs += 1; - i2s_info_ptr->rx_buf.len -= empty_trig * 2; - dw_i2s_rx_clear_overrun_interrupt(i2s_rx_regs_ptr, DW_I2S_CHANNEL0); - dw_i2s_rx_enable_interrupt(i2s_info_ptr, DW_I2S_CHANNEL0); - } else { - count_pair = i2s_info_ptr->rx_buf.len >> 1; - for (i = 0; i < count_pair; i++) { -#ifdef DW_I2S_DATA_LENGTH_16 - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - buff[2 * (i + buf_ofs)] = (uint16_t)buf; - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - buff[1 + 2 * (i + buf_ofs)] = (uint16_t)buf; -#else - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buff[2 * (i + buf_ofs)], DW_I2S_CHANNEL0); - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buff[1 + 2 * (i + buf_ofs)], DW_I2S_CHANNEL0); -#endif - } - /* if the length of remainning data is less than empty_trig*2,fill 0 */ - for (i = count_pair; i < empty_trig; i++) { - dw_i2s_rx_read_left_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - dw_i2s_rx_read_right_hold_reg(i2s_rx_ctrl_ptr, &buf, DW_I2S_CHANNEL0); - } - i2s_info_ptr->rx_buf.len = 0; - dw_i2s_rx_clear_overrun_interrupt(i2s_rx_regs_ptr, DW_I2S_CHANNEL0); - } - /*the ofs is used to judge the next number of data to send to fifos*/ - // empty_trig = dw_i2s_tx_get_txchet(i2s_tx_regs_ptr, DW_I2S_CHANNEL0); - // i2s_tx_ctrl_ptr->dw_i2s_buf.ofs = empty_trig; - i2s_info_ptr->cur_state = I2S_FREE; - if ((i2s_info_ptr->rx_buf.len == 0) && (i2s_info_ptr->i2s_cbs.rx_cb != NULL)) { - i2s_info_ptr->i2s_cbs.rx_cb(i2s_obj); - } - } - } else { - printf("The buffer of receiver is NULL !\n"); - } -} -/* Clear interrupt */ - -/** - * @defgroup DEVICE_DW_I2S_IMPLEMENT DesignWare I2S Driver Function API Implement - * @ingroup DEVICE_DW_I2S - * @brief HAL I2S implemention with DesignWare I2S - * @{ - */ - -/** - * @brief Open a designware i2s device - * @param[in] i2s_obj I2S device object pointer - * @param[in] mode Working mode (@ref DEV_MASTER_MODE "master" or @ref DEV_SLAVE_MODE "slave") - * @param[in] param Device type (@ref I2S_DEVICE_TRANSMITTER "transmitter" OR @ref I2S_DEVICE_RECEIVER "receiver") - * @retval E_OK Open successfully without any issues - * @retval E_OPNED Device was opened before - * @retval E_OBJ Device object is not valid - * @retval E_SYS Device initialized parameters are different with parameters in IP - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ -int32_t dw_i2s_open(DEV_I2S *i2s_obj, uint32_t mode, uint32_t param) -{ - int32_t ercd = E_OK; - uint32_t support_modes; - uint32_t channels = 0; - uint16_t da_intr = 0; - uint16_t or_intr = 0; - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - - /* START ERROR CHECK */ - VALID_CHK_I2S_INFO_OBJECT(i2s_info_ptr); - DW_I2S_CHECK_EXP((mode == DEV_MASTER_MODE) || (mode == DEV_SLAVE_MODE), E_PAR); - DW_I2S_CHECK_EXP((param == I2S_DEVICE_TRANSMITTER) || (param == I2S_DEVICE_RECEIVER), E_PAR); - DW_I2S_CHECK_EXP(i2s_info_ptr->device == param, E_PAR); - /* END OF ERROR CHECK */ - - /** Check FIFO length */ - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - if (i2s_config_ptr->fifo_len != dw_i2s_rx_get_fifo_len(i2s_rx_regs_ptr)) { - return E_SYS; - } - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - if (i2s_config_ptr->fifo_len != dw_i2s_tx_get_fifo_len(i2s_tx_regs_ptr)) { - return E_SYS; - } - } - - /* Check supported modes, master or slave */ - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - support_modes = i2s_config_ptr->support_modes; - } else { - support_modes = i2s_config_ptr->support_modes; - } - DW_I2S_CHECK_EXP((((support_modes) & DW_I2S_MASTER_SUPPORTED) && (mode == DEV_MASTER_MODE)) || \ - (((support_modes) & DW_I2S_SLAVE_SUPPORTED) && (mode == DEV_SLAVE_MODE)), E_NOSPT); - - /** Check opened before use case */ - if (i2s_info_ptr->opn_cnt > 0) { - return E_OPNED; - } - - /* auto increase open count */ - i2s_info_ptr->opn_cnt++; - i2s_info_ptr->mode = mode; - - channels = i2s_config_ptr->channels; - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - /* Disable device before init it */ - dw_i2s_rx_block_disable(i2s_rx_regs_ptr); - dw_i2s_rx_disable(i2s_rx_regs_ptr); - /* Flush FIFO */ - dw_i2s_rx_flush_fifo(i2s_rx_regs_ptr); - /* Set WSS and SCLKG */ - if (i2s_info_ptr->mode == DEV_MASTER_MODE) { - dw_i2s_rx_clock_disable(i2s_rx_regs_ptr); - dw_i2s_rx_set_wss(i2s_rx_regs_ptr, i2s_config_ptr->ws_length); - dw_i2s_rx_set_sclkg(i2s_rx_regs_ptr, i2s_config_ptr->sclk_gate); - } - /* Set data resolution for channels and disable I2S device interrupt */ - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_rx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL0); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL0); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL0] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL0] & 0xffff0000) >> 16; - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_rx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL1); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL1); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL1] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL1] & 0xffff0000) >> 16; - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_rx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL2); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL2); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL2] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL2] & 0xffff0000) >> 16; - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_rx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL3); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL3); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL3] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL3] & 0xffff0000) >> 16; - } - int_handler_install(da_intr, i2s_config_ptr->dw_i2s_int_handler); - int_handler_install(or_intr, i2s_config_ptr->dw_i2s_int_handler); - /* Clean I2S buffer in ctrl */ - memset(&(i2s_rx_ctrl_ptr->dw_i2s_buf), 0, sizeof(DW_I2S_BUFFER)); - } else { - /* Disable device before init it */ - dw_i2s_tx_block_disable(i2s_tx_regs_ptr); - dw_i2s_tx_disable(i2s_tx_regs_ptr); - /* Flush FIFO */ - dw_i2s_tx_flush_fifo(i2s_tx_regs_ptr); - /* Set WSS and SCLKG */ - if (i2s_info_ptr->mode == DEV_MASTER_MODE) { - dw_i2s_tx_clock_disable(i2s_tx_regs_ptr); - dw_i2s_tx_set_wss(i2s_tx_regs_ptr, i2s_config_ptr->ws_length); - dw_i2s_tx_set_sclkg(i2s_tx_regs_ptr, i2s_config_ptr->sclk_gate); - } - /* Set data resolution for channels and disable I2S device interrupt */ - if (channels & DW_I2S_CHANNEL0_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_tx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL0); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL0); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL0] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL0] & 0xffff0000) >> 16; - } - if (channels & DW_I2S_CHANNEL1_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_tx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL1); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL1); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL1] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL1] & 0xffff0000) >> 16; - } - if (channels & DW_I2S_CHANNEL2_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_tx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL2); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL2); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL2] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL2] & 0xffff0000) >> 16; - } - if (channels & DW_I2S_CHANNEL3_SUPPORTED) { - /* Set data resolution for channels */ - dw_i2s_tx_set_wlen(i2s_info_ptr, DW_I2S_CHANNEL3); - /* Disable I2S device interrupt */ - dw_i2s_disable_dev_intr(i2s_info_ptr, DW_I2S_CHANNEL3); - da_intr = i2s_config_ptr->intno[DW_I2S_CHANNEL3] & 0x0000ffff; - or_intr = (i2s_config_ptr->intno[DW_I2S_CHANNEL3] & 0xffff0000) >> 16; - } - int_handler_install(da_intr, i2s_config_ptr->dw_i2s_int_handler); - int_handler_install(or_intr, i2s_config_ptr->dw_i2s_int_handler); - /* Clean I2S buffer in ctrl */ - memset(&(i2s_tx_ctrl_ptr->dw_i2s_buf), 0, sizeof(DW_I2S_BUFFER)); - } - - /* Need to check parameters of ws_length, sample_rate and data_res and - initialize sclk divider according to sample_rate in board layer */ - - i2s_info_ptr->status = DEV_ENABLED; - i2s_info_ptr->cur_state = I2S_FREE; - i2s_info_ptr->err_state = I2S_ERR_NONE; - i2s_info_ptr->extra = NULL; - i2s_info_ptr->i2s_cbs.tx_cb = NULL; - i2s_info_ptr->i2s_cbs.rx_cb = NULL; - i2s_info_ptr->i2s_cbs.err_cb = NULL; - - /** Clear I2S TX/RX buffer and callback */ - memset(&(i2s_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(i2s_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - - /* Enable I2S TX/RX IP */ - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - dw_i2s_rx_enable(i2s_rx_regs_ptr); - } else { - dw_i2s_tx_enable(i2s_tx_regs_ptr); - } - -error_exit: - return ercd; -} - -/** - * @brief Close a designware i2s device - * @param[in] i2s_obj I2S device object pointer - * @retval E_OK Close successfully without any issues (including that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_I2S_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ -int32_t dw_i2s_close(DEV_I2S *i2s_obj) -{ - int32_t ercd = E_OK; - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - uint32_t channels = 0; - - /* START ERROR CHECK */ - VALID_CHK_I2S_INFO_OBJECT(i2s_info_ptr); - DW_I2S_CHECK_EXP(i2s_info_ptr->opn_cnt > 0, E_OK); - /* END OF ERROR CHECK */ - - i2s_info_ptr->opn_cnt--; - if (i2s_info_ptr->opn_cnt == 0) { - channels = i2s_config_ptr->channels; - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - /* Disable device */ - dw_i2s_rx_block_disable(i2s_rx_regs_ptr); - dw_i2s_rx_disable(i2s_rx_regs_ptr); - /* Flush FIFO */ - dw_i2s_rx_flush_fifo(i2s_rx_regs_ptr); - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - /* Disable device */ - dw_i2s_tx_block_disable(i2s_tx_regs_ptr); - dw_i2s_tx_disable(i2s_tx_regs_ptr); - /* Flush FIFO */ - dw_i2s_tx_flush_fifo(i2s_tx_regs_ptr); - } - dw_i2s_disable_all_channel_intr(i2s_info_ptr); - - i2s_info_ptr->status = DEV_DISABLED; - i2s_info_ptr->cur_state = I2S_FREE; - i2s_info_ptr->err_state = I2S_ERR_NONE; - i2s_info_ptr->extra = NULL; - i2s_info_ptr->i2s_cbs.tx_cb = NULL; - i2s_info_ptr->i2s_cbs.rx_cb = NULL; - i2s_info_ptr->i2s_cbs.err_cb = NULL; - - /** Clear I2S TX/RX buffer and callback */ - memset(&(i2s_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(i2s_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** - * @brief Control i2s by ctrl command - * @param[in] i2s_obj I2S device object pointer - * @param[in] ctrl_cmd @ref DEVICE_HAL_I2S_CTRLCMD "control command", to change or get some thing related to i2s - * @param[in,out] param Parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ -int32_t dw_i2s_control(DEV_I2S *i2s_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = NULL; - DW_I2S_TX_REG *i2s_tx_regs_ptr = NULL; - uint32_t val32; - uint32_t val16_0 = 0; - uint32_t val16_1 = 0; - uint32_t channels = 0; - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - DEV_BUFFER *devbuf; - - /* START ERROR CHECK */ - VALID_CHK_I2S_INFO_OBJECT(i2s_info_ptr); - DW_I2S_CHECK_EXP(i2s_info_ptr->opn_cnt > 0, E_CLSED); - /* END OF ERROR CHECK */ - - channels = i2s_config_ptr->channels; - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - } else { - i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - } - - /* check whether current device is disabled */ - if ((i2s_info_ptr->status & DEV_ENABLED) == 0) { - /** When device is disabled, - * only I2S_CMD_ENA_DEV, I2S_CMD_DIS_DEV, I2S_CMD_GET_STATUS, I2S_CMD_RESET - * are available, other commands will return E_SYS - */ - if ((ctrl_cmd != I2S_CMD_ENA_DEV) && \ - (ctrl_cmd != I2S_CMD_DIS_DEV) && \ - (ctrl_cmd != I2S_CMD_GET_STATUS) && \ - (ctrl_cmd != I2S_CMD_RESET)) { - return E_SYS; - } - } - - /* - * To add command check for transmitter and receiver seperately - */ - - switch (ctrl_cmd) { - /* Commmon commands for both TX and RX mode */ - case I2S_CMD_GET_STATUS: - DW_I2S_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = i2s_info_ptr->status; - break; - case I2S_CMD_ENA_DEV: - val32 = (uint32_t)param; - if (DW_I2S_CHANNEL_CHECK(val16_1, channels)) { - dw_i2s_enable_device(i2s_info_ptr, val32); - i2s_info_ptr->status = DEV_ENABLED; - } else { - ercd = E_PAR; - } - break; - case I2S_CMD_DIS_DEV: - val32 = (uint32_t)param; - if (DW_I2S_CHANNEL_CHECK(val16_1, channels)) { - dw_i2s_disable_device(i2s_info_ptr, val32); - i2s_info_ptr->status = DEV_DISABLED; - } else { - ercd = E_PAR; - } - break; - case I2S_CMD_RESET: - dw_i2s_reset_device(i2s_info_ptr); - break; - case I2S_CMD_FLUSH_TX: - dw_i2s_flush(i2s_info_ptr); - break; - case I2S_CMD_FLUSH_RX: - dw_i2s_flush(i2s_info_ptr); - break; - case I2S_CMD_SET_TXCB: - DW_I2S_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - i2s_info_ptr->i2s_cbs.tx_cb = param; - break; - case I2S_CMD_SET_RXCB: - DW_I2S_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - i2s_info_ptr->i2s_cbs.rx_cb = param; - break; - case I2S_CMD_SET_ERRCB: - DW_I2S_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - i2s_info_ptr->i2s_cbs.err_cb = param; - break; - case I2S_CMD_SET_TXINT: - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_TRANSMITTER, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state != I2S_IN_RX, E_CTX); - val32 = (uint32_t)param; - /* Set all available channels */ - if (val32 == 0) { - dw_i2s_disable_all_channel_intr(i2s_info_ptr); - } else { - dw_i2s_enable_all_channel_intr(i2s_info_ptr); - } - break; - case I2S_CMD_SET_RXINT: - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_RECEIVER, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state != I2S_IN_TX, E_CTX); - val32 = (uint32_t)param; - /* Set all available channels */ - if (val32 == 0) { - dw_i2s_disable_all_channel_intr(i2s_info_ptr); - } else { - dw_i2s_enable_all_channel_intr(i2s_info_ptr); - } - break; - case I2S_CMD_SET_TXINT_BUF: - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_TRANSMITTER, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state == I2S_FREE, E_CTX); - DW_I2S_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - i2s_info_ptr->tx_buf = *devbuf; - i2s_info_ptr->tx_buf.ofs = 0; - i2s_tx_ctrl_ptr->dw_i2s_buf.ofs = 0; - i2s_tx_ctrl_ptr->dw_i2s_buf.len = devbuf->len; - } else { - i2s_info_ptr->tx_buf.buf = NULL; - i2s_info_ptr->tx_buf.len = 0; - i2s_info_ptr->tx_buf.ofs = 0; - i2s_tx_ctrl_ptr->dw_i2s_buf.ofs = 0; - i2s_tx_ctrl_ptr->dw_i2s_buf.len = 0; - } - break; - case I2S_CMD_SET_RXINT_BUF: - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_RECEIVER, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state == I2S_FREE, E_CTX); - DW_I2S_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - i2s_info_ptr->rx_buf = *devbuf; - i2s_info_ptr->rx_buf.ofs = 0; - i2s_rx_ctrl_ptr->dw_i2s_buf.ofs = 0; - i2s_rx_ctrl_ptr->dw_i2s_buf.len = devbuf->len; - } else { - i2s_info_ptr->rx_buf.buf = NULL; - i2s_info_ptr->rx_buf.len = 0; - i2s_info_ptr->rx_buf.ofs = 0; - i2s_rx_ctrl_ptr->dw_i2s_buf.ofs = 0; - i2s_rx_ctrl_ptr->dw_i2s_buf.len = 0; - } - break; - case I2S_CMD_SET_TXCHET_BUF: - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_TRANSMITTER, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state == I2S_FREE, E_CTX); - DW_I2S_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - val32 = (uint32_t)param; - val16_0 = (uint16_t)((val32 & 0xffff0000) >> 16); // trigger level - val16_1 = (uint16_t)(val32 & 0x0000ffff); // channel number - DW_I2S_CHECK_EXP((val16_0 >= 0) && (val16_0 < 16), E_PAR); - if (!DW_I2S_CHANNEL_CHECK(val16_1, channels)) { - return E_PAR; - } - dw_i2s_tx_channel_disable(i2s_tx_regs_ptr, val16_1); - dw_i2s_tx_set_txchet(i2s_tx_regs_ptr, val16_0, val16_1); - dw_i2s_tx_channel_enable(i2s_tx_regs_ptr, val16_1); - break; - case I2S_CMD_SET_RXCHDT_BUF: - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_RECEIVER, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state == I2S_FREE, E_CTX); - DW_I2S_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - val32 = (uint32_t)param; - val16_0 = (uint16_t)((val32 & 0xffff0000) >> 16); // trigger level - val16_1 = (uint16_t)(val32 & 0x0000ffff); // channel number - DW_I2S_CHECK_EXP((val16_0 >= 0) && (val16_0 < 16), E_PAR); - if (!DW_I2S_CHANNEL_CHECK(val16_1, channels)) { - return E_PAR; - } - dw_i2s_rx_channel_disable(i2s_rx_regs_ptr, val16_1); - dw_i2s_rx_set_rxchdt(i2s_rx_regs_ptr, val16_0, val16_1); - dw_i2s_rx_channel_enable(i2s_rx_regs_ptr, val16_1); - break; - /* Master mode only commands */ - case I2S_CMD_MST_SET_CLK: - DW_I2S_CHECK_EXP(i2s_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - val32 = (uint32_t)param; - if (val32 == 0) { - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - dw_i2s_rx_clock_disable(i2s_rx_ctrl_ptr->dw_i2s_regs); - } else { - dw_i2s_tx_clock_disable(i2s_tx_ctrl_ptr->dw_i2s_regs); - } - } else { - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - dw_i2s_rx_clock_enable(i2s_rx_ctrl_ptr->dw_i2s_regs); - } else { - dw_i2s_tx_clock_enable(i2s_tx_ctrl_ptr->dw_i2s_regs); - } - } - break; - case I2S_CMD_MST_SET_WSS: - DW_I2S_CHECK_EXP(i2s_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - val32 = (uint32_t)param; - DW_I2S_CHECK_EXP(((val32 == DW_I2S_WSS_16_CLK) || \ - (val32 == DW_I2S_WSS_24_CLK) || \ - (val32 == DW_I2S_WSS_32_CLK)), E_PAR); - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - dw_i2s_rx_clock_disable(i2s_rx_ctrl_ptr->dw_i2s_regs); - dw_i2s_rx_set_wss(i2s_rx_ctrl_ptr->dw_i2s_regs, val32); - i2s_config_ptr->ws_length = val32; - } else { - dw_i2s_tx_clock_disable(i2s_tx_ctrl_ptr->dw_i2s_regs); - dw_i2s_tx_set_wss(i2s_tx_ctrl_ptr->dw_i2s_regs, val32); - i2s_config_ptr->ws_length = val32; - } - break; - case I2S_CMD_MST_SET_SCLKG: - DW_I2S_CHECK_EXP(i2s_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - val32 = (uint32_t)param; - DW_I2S_CHECK_EXP(((val32 == DW_I2S_SCLKG_NO) || \ - (val32 == DW_I2S_SCLKG_12_CLK) || \ - (val32 == DW_I2S_SCLKG_16_CLK) || \ - (val32 == DW_I2S_SCLKG_20_CLK) || \ - (val32 == DW_I2S_SCLKG_24_CLK)), E_PAR); - if (i2s_info_ptr->device == I2S_DEVICE_RECEIVER) { - dw_i2s_rx_clock_disable(i2s_rx_ctrl_ptr->dw_i2s_regs); - dw_i2s_rx_set_sclkg(i2s_rx_ctrl_ptr->dw_i2s_regs, val32); - i2s_config_ptr->sclk_gate = val32; - } else { - dw_i2s_tx_clock_disable(i2s_tx_ctrl_ptr->dw_i2s_regs); - dw_i2s_tx_set_sclkg(i2s_tx_ctrl_ptr->dw_i2s_regs, val32); - i2s_config_ptr->sclk_gate = val32; - } - break; - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** - * @brief Poll transmit data through designware i2s as master or slave - * @param[in] i2s_obj I2S device object pointer - * @param[in] data Data to send - * @param[in] len Data length to send, no timeout check - * @param[in] channel Send data via specified channel - * @retval >0 Byte count that was successfully sent for poll method, - * it might can't send that much due to @ref DEV_I2S_INFO::err_state "I2S_ERROR_STATE". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_CTX Device is still in transfer state - * @retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ -int32_t dw_i2s_write(DEV_I2S *i2s_obj, const void *data, uint32_t len, uint32_t channel) -{ - int32_t ercd = E_OK; - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_TX_CTRL *i2s_tx_ctrl_ptr = (DW_I2S_TX_CTRL *)(i2s_info_ptr->i2s_ctrl); - DW_I2S_TX_REG *i2s_tx_regs_ptr = i2s_tx_ctrl_ptr->dw_i2s_regs; - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - - uint32_t remain_cnt = 0; - uint32_t remain_pro = 0; - uint32_t trans_cnt = 0; - int32_t error_state = I2S_ERR_NONE; - - #ifdef DW_I2S_DATA_LENGTH_16 - uint16_t *p_buf = (uint16_t *)data; - #else - uint32_t *p_buf = (uint32_t *)data; - #endif - - /* START ERROR CHECK */ - VALID_CHK_I2S_INFO_OBJECT(i2s_info_ptr); - DW_I2S_CHECK_EXP(i2s_info_ptr->opn_cnt > 0, E_CLSED); - DW_I2S_CHECK_EXP(i2s_info_ptr->status & DEV_ENABLED, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_TRANSMITTER, E_OBJ); - DW_I2S_CHECK_EXP(data != NULL, E_PAR); - - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state == I2S_FREE, E_CTX); - /* END OF ERROR CHECK */ - - remain_cnt = len; - remain_pro = len; - if (i2s_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode transmit data */ - /* Start state Check */ - DW_I2S_CHECK_EXP(channel == DW_I2S_CHANNEL0, E_PAR); // only support channel 0 - /* End state Check */ - /* Send data point to I2S control buffer */ - i2s_tx_ctrl_ptr->dw_i2s_buf.buf = p_buf; - i2s_tx_ctrl_ptr->dw_i2s_buf.len = i2s_config_ptr->fifo_len; - i2s_tx_ctrl_ptr->dw_i2s_buf.ofs = 0; - i2s_info_ptr->cur_state = I2S_IN_TX; - dw_i2s_enable_device(i2s_info_ptr, channel); - dw_i2s_tx_clock_enable(i2s_tx_regs_ptr); - while (remain_cnt != 0) { - remain_cnt = dw_i2s_tx_write_samples(i2s_info_ptr, remain_pro, channel); - // EMBARC_PRINTF("The while is ENTER!\n"); - while ((i2s_tx_regs_ptr->ISR0 & DW_I2S_ISRX_TXFE) == 0) { - ; - } - // EMBARC_PRINTF("The while is OK!\n"); - // delay(100); - trans_cnt += (remain_pro - remain_cnt); - if (remain_cnt == 0) { - i2s_tx_ctrl_ptr->dw_i2s_buf.buf = &p_buf[trans_cnt - 1]; - } else { - i2s_tx_ctrl_ptr->dw_i2s_buf.buf = &p_buf[trans_cnt]; - } - remain_pro = remain_cnt; - } - // delay(20); - } else { - // Slave mode is not support in this version - DW_I2S_CHECK_EXP(i2s_info_ptr->mode != DEV_SLAVE_MODE, E_SYS); - } - - i2s_info_ptr->cur_state = I2S_FREE; - i2s_info_ptr->err_state = error_state; - - ercd = trans_cnt; -error_exit: - return ercd; -} - -/** - * @brief Read data through designware i2s as master or slave - * @param[in] i2s_obj I2S device object pointer - * @param[out] data Data received (data must be uint32_t type), uint32_t(left) and uint32_t(right) alternating - * @param[in] len I2S device channel to read - * @param[in] channel Data length need to read - * @retval >0 Byte count that was successfully received for poll method, - * it might can't send that much due to @ref DEV_I2S_INFO::err_state "I2S_ERROR_STATE". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_CTX Device is still in receive state - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't read data from hardware due to hardware issues, such as device is disabled - */ -int32_t dw_i2s_read(DEV_I2S *i2s_obj, void *data, uint32_t len, uint32_t channel) -{ - int32_t ercd = E_OK; - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_RX_CTRL *i2s_rx_ctrl_ptr = NULL; - DW_I2S_RX_REG *i2s_rx_regs_ptr = NULL; - - uint32_t remain_cnt = 0; - uint32_t remain_pro = 0; - uint32_t trans_cnt = 0; - int32_t error_state = I2S_ERR_NONE; - - #ifdef DW_I2S_DATA_LENGTH_16 - uint16_t *p_buf = (uint16_t *)data; - #else - uint32_t *p_buf = (uint32_t *)data; - #endif - i2s_rx_ctrl_ptr = (DW_I2S_RX_CTRL *)(i2s_info_ptr->i2s_ctrl); - i2s_rx_regs_ptr = i2s_rx_ctrl_ptr->dw_i2s_regs; - - /* START ERROR CHECK */ - VALID_CHK_I2S_INFO_OBJECT(i2s_info_ptr); - DW_I2S_CHECK_EXP(i2s_info_ptr->opn_cnt > 0, E_CLSED); - DW_I2S_CHECK_EXP(i2s_info_ptr->status & DEV_ENABLED, E_SYS); - DW_I2S_CHECK_EXP(i2s_info_ptr->device == I2S_DEVICE_RECEIVER, E_OBJ); - DW_I2S_CHECK_EXP(data != NULL, E_PAR); - DW_I2S_CHECK_EXP(i2s_info_ptr->cur_state == I2S_FREE, E_CTX); - /* END OF ERROR CHECK */ - - remain_cnt = len; - remain_pro = len; - if (i2s_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode receive data */ - /* Start state Check */ - DW_I2S_CHECK_EXP(channel == DW_I2S_CHANNEL0, E_PAR); // only support channel 0 - /* End state Check */ - /* Send data point to I2S control buffer */ - i2s_rx_ctrl_ptr->dw_i2s_buf.buf = p_buf; - i2s_rx_ctrl_ptr->dw_i2s_buf.len = len; - i2s_rx_ctrl_ptr->dw_i2s_buf.ofs = 0; - i2s_info_ptr->cur_state = I2S_IN_RX; - dw_i2s_enable_device(i2s_info_ptr, channel); - dw_i2s_rx_clock_enable(i2s_rx_regs_ptr); - while (remain_cnt != 0) { - while ((i2s_rx_regs_ptr->ISR0 & DW_I2S_ISRX_RXDA) == 0) { - ; - } - remain_cnt = dw_i2s_rx_read_samples(i2s_info_ptr, remain_pro, channel); - trans_cnt += remain_pro - remain_cnt; - if (remain_cnt == 0) { - i2s_rx_ctrl_ptr->dw_i2s_buf.buf = &p_buf[trans_cnt - 1]; - } else { - i2s_rx_ctrl_ptr->dw_i2s_buf.buf = &p_buf[trans_cnt]; - } - remain_pro = remain_cnt; - } - } else { - // Slave mode is not support in this version - DW_I2S_CHECK_EXP(i2s_info_ptr->mode != DEV_SLAVE_MODE, E_SYS); - } - - i2s_info_ptr->cur_state = I2S_FREE; - i2s_info_ptr->err_state = error_state; - - ercd = trans_cnt; -error_exit: - return ercd; -} - -/** - * @brief DesignWare i2s tx interrupt handler - * @param[in] i2s_obj I2S device pointer - * @param[in] ptr Extra information - */ -void dw_i2s_isr_tx(DEV_I2S *i2s_obj, void *ptr) -{ - int ercd = E_OK; - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - - uint32_t channels = i2s_config_ptr->channels; - - DW_I2S_CHECK_EXP((i2s_info_ptr->cur_state == I2S_FREE), E_CTX) - /* END OF ERROR CHECK */ - DW_I2S_CHECK_EXP(((channels & DW_I2S_CHANNEL0_SUPPORTED) == 1) && \ - ((channels & DW_I2S_CHANNEL1_SUPPORTED) == 0) && \ - ((channels & DW_I2S_CHANNEL2_SUPPORTED) == 0) && \ - ((channels & DW_I2S_CHANNEL3_SUPPORTED) == 0), E_PAR); - /* End state Check */ - - i2s_info_ptr->cur_state = I2S_IN_TX; - dw_i2s_mst_int_write(i2s_obj); -error_exit: - return; -} - -/** - * @brief DesignWare i2s rx interrupt handler - * @param[in] i2s_obj I2S device pointer - * @param[in] ptr extra information - */ -void dw_i2s_isr_rx(DEV_I2S *i2s_obj, void *ptr) -{ - int ercd = E_OK; - DEV_I2S_INFO *i2s_info_ptr = &(i2s_obj->i2s_info); - DW_I2S_CONFIG *i2s_config_ptr = (DW_I2S_CONFIG *)(i2s_info_ptr->i2s_config); - - uint32_t channels = i2s_config_ptr->channels; - - DW_I2S_CHECK_EXP((i2s_info_ptr->cur_state == I2S_FREE), E_CTX) - /* END OF ERROR CHECK */ - DW_I2S_CHECK_EXP(((channels & DW_I2S_CHANNEL0_SUPPORTED) == 1) && \ - ((channels & DW_I2S_CHANNEL1_SUPPORTED) == 0) && \ - ((channels & DW_I2S_CHANNEL2_SUPPORTED) == 0) && \ - ((channels & DW_I2S_CHANNEL3_SUPPORTED) == 0), E_PAR); - /* End state Check */ - - i2s_info_ptr->cur_state = I2S_IN_RX; - dw_i2s_mst_int_rx(i2s_obj); -error_exit: - return; -} -/** @} */ diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/iic/dw_iic.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/iic/dw_iic.c deleted file mode 100644 index 1da2cbd5..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/iic/dw_iic.c +++ /dev/null @@ -1,1779 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include - -#include "embARC_toolchain.h" -#include "embARC_error.h" - -#include "arc/arc_exception.h" - -#include "device/designware/dw_iic_hal.h" -#include "device/designware/dw_iic.h" - -/** check expressions used in DesignWare IIC driver implementation */ -#define DW_IIC_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of iic info object */ -#define VALID_CHK_IIC_INFO_OBJECT(iicinfo_obj_ptr) { \ - DW_IIC_CHECK_EXP((iicinfo_obj_ptr) != NULL, E_OBJ); \ - DW_IIC_CHECK_EXP(((iicinfo_obj_ptr)->iic_ctrl) != NULL, E_OBJ); \ -} -#endif - -/** - * @name DesignWare IIC Interrupt Callback Routine Select Marcos - * @brief DesignWare IIC interrupt callback routines select macros definitions - * @{ - */ -#define DW_IIC_RDY_SND (1U) /*!< ready to send callback */ -#define DW_IIC_RDY_RCV (2U) /*!< ready to receive callback */ -/** @} */ - -/** - * @defgroup DEVICE_DW_IIC_STATIC DesignWare IIC Driver Static Functions - * @ingroup DEVICE_DW_IIC - * @brief Static or inline functions, variables for DesignWare IIC handle iic operations, - * only used in this file. - * @{ - */ - -/** - * @fn void dw_iic_disable(DW_IIC_REG *iic_reg_ptr) - * @brief Disable designware iic device - */ -Inline void dw_iic_disable(DW_IIC_REG *iic_reg_ptr) -{ - iic_reg_ptr->IC_ENABLE = DW_IIC_DISABLE; -} - -/** - * @fn void dw_iic_enable(DW_IIC_REG *iic_reg_ptr) - * @brief Enable designware iic device - */ -Inline void dw_iic_enable(DW_IIC_REG *iic_reg_ptr) -{ - iic_reg_ptr->IC_ENABLE = DW_IIC_ENABLE; -} - -/** - * @fn void dw_iic_clear_interrupt_all(DW_IIC_REG *iic_reg_ptr) - * @brief Clear all designware iic interrupt - */ -Inline void dw_iic_clear_interrupt_all(DW_IIC_REG *iic_reg_ptr) -{ - (void)iic_reg_ptr->IC_CLR_INTR; -} - -/** - * @fn int32_t dw_iic_putready(DW_IIC_REG *iic_reg_ptr) - * @brief test whether iic is ready to write, 1 ready, 0 not ready - */ -Inline int32_t dw_iic_putready(DW_IIC_REG *iic_reg_ptr) -{ - return ((iic_reg_ptr->IC_STATUS & IC_STATUS_TFNF) != 0); -} - -/** - * @fn int32_t dw_iic_getready(DW_IIC_REG *iic_reg_ptr) - * @brief test whether iic is ready to receive, 1 ready, 0 not ready - */ -Inline int32_t dw_iic_getready(DW_IIC_REG *iic_reg_ptr) -{ - return ((iic_reg_ptr->IC_STATUS & IC_STATUS_RFNE) != 0); -} - -/** - * @fn void dw_iic_putdata(DW_IIC_REG *iic_reg_ptr, uint32_t data) - * @brief Write data into IIC TX FIFO with STOP/RESTART Condition, and R/W bit - */ -Inline void dw_iic_putdata(DW_IIC_REG *iic_reg_ptr, uint32_t data) -{ - iic_reg_ptr->IC_DATA_CMD = data; -} - -/** - * @fn uint32_t dw_iic_getdata(DW_IIC_REG *iic_reg_ptr) - * @brief Read Data from IIC RX FIFO - */ -Inline uint32_t dw_iic_getdata(DW_IIC_REG *iic_reg_ptr) -{ - return (iic_reg_ptr->IC_DATA_CMD) & 0xff; -} - -/** - * @fn void dw_iic_unmask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask) - * @brief Enable designware iic bit interrupt with mask - */ -Inline void dw_iic_unmask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask) -{ - iic_reg_ptr->IC_INTR_MASK |= mask; -} - -/** - * @fn void dw_iic_mask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask) - * @brief Disable designware iic bit interrupt with mask - */ -Inline void dw_iic_mask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask) -{ - iic_reg_ptr->IC_INTR_MASK &= ~mask; -} - -/** - * @fn uint32_t dw_iic_get_txfifo_len(DW_IIC_REG *iic_reg_ptr) - * @brief Get TX FIFO Length - */ -Inline uint32_t dw_iic_get_txfifo_len(DW_IIC_REG *iic_reg_ptr) -{ - uint32_t txfifolen; - - txfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 16) & 0xff) + 1; - - return txfifolen; -} - -/** - * @fn uint32_t dw_iic_get_rxfifo_len(DW_IIC_REG *iic_reg_ptr) - * @brief Get RX FIFO Length - */ -Inline uint32_t dw_iic_get_rxfifo_len(DW_IIC_REG *iic_reg_ptr) -{ - uint32_t rxfifolen; - - rxfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 8) & 0xff) + 1; - - return rxfifolen; -} - -/** - * @fn void dw_iic_set_mstaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) - * @brief Set designware iic transfer in 7bit of 10bit addressing mode as a master - */ -Inline void dw_iic_set_mstaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) -{ -#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT - if (mode == IIC_7BIT_ADDRESS) { - iic_reg_ptr->IC_TAR &= ~IC_10BITADDR_MASTER; - } else { - iic_reg_ptr->IC_TAR |= IC_10BITADDR_MASTER; - } -#else - dw_iic_disable(iic_reg_ptr); - if (mode == IIC_7BIT_ADDRESS) { - iic_reg_ptr->IC_CON &= ~MST_10_BIT_ADDR_MODE; - } else { - iic_reg_ptr->IC_CON |= MST_10_BIT_ADDR_MODE; - } - dw_iic_enable(iic_reg_ptr); -#endif -} - -/** - * @fn void dw_iic_set_slvaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) - * @brief Set designware iic transfer in 7bit of 10bit addressing mode as a slave - */ -Inline void dw_iic_set_slvaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) -{ - dw_iic_disable(iic_reg_ptr); - if (mode == IIC_7BIT_ADDRESS) { - iic_reg_ptr->IC_CON &= ~SLV_10_BIT_ADDR_MODE; - } else { - iic_reg_ptr->IC_CON |= SLV_10_BIT_ADDR_MODE; - } - dw_iic_enable(iic_reg_ptr); -} - -/** - * @fn void dw_iic_set_taraddr(DW_IIC_REG *iic_reg_ptr, uint32_t address) - * @brief Set designware iic transfer target address for addressing any iic slave device as a master - */ -/** Set designware iic transfer target address for addressing any iic slave device as a master */ -Inline void dw_iic_set_taraddr(DW_IIC_REG *iic_reg_ptr, uint32_t address) -{ -#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT - iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK); - iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address); -#else - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK); - iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address); - dw_iic_enable(iic_reg_ptr); -#endif -} - -/** - * @fn void dw_iic_set_slvaddr(DW_IIC_REG *iic_reg_ptr, uint32_t address) - * @brief Set designware iic slave address as a slave - */ -Inline void dw_iic_set_slvaddr(DW_IIC_REG *iic_reg_ptr, uint32_t address) -{ - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_SAR &= ~(IC_SAR_10BIT_ADDR_MASK); - iic_reg_ptr->IC_SAR |= (IC_SAR_10BIT_ADDR_MASK & address); - dw_iic_enable(iic_reg_ptr); -} - -/** - * @fn uint32_t dw_iic_select_speedmode(uint32_t speedmode) - * @brief Select speed mode, and return proper speed mode configuration - */ -Inline uint32_t dw_iic_select_speedmode(uint32_t speedmode) -{ - uint32_t speedcfg; - - if (speedmode == IIC_SPEED_STANDARD) { - speedcfg = IC_CON_SPEED_STANDARD; - } else if (speedmode == IIC_SPEED_FAST) { - speedcfg = IC_CON_SPEED_FAST; - } else if (speedmode == IIC_SPEED_FASTPLUS) { - speedcfg = IC_CON_SPEED_FAST; - } else if (speedmode == IIC_SPEED_HIGH) { - speedcfg = IC_CON_SPEED_HIGH; - } else { - speedcfg = IC_CON_SPEED_HIGH; - } - return speedcfg; -} - -/** - * @fn void dw_iic_set_speedmode(DW_IIC_REG *iic_reg_ptr, uint32_t speedmode) - * @brief Set designware iic speed mode - */ -Inline void dw_iic_set_speedmode(DW_IIC_REG *iic_reg_ptr, uint32_t speedmode) -{ - uint32_t ic_con_val; - - dw_iic_disable(iic_reg_ptr); - ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_SPEED_MASK); - ic_con_val |= dw_iic_select_speedmode(speedmode); - iic_reg_ptr->IC_CON = ic_con_val; - dw_iic_enable(iic_reg_ptr); -} - -/** - * @fn void dw_iic_set_working_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) - * @brief Set designware working mode as master or slave - */ -Inline void dw_iic_set_working_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) -{ - uint32_t ic_con_val; - - dw_iic_disable(iic_reg_ptr); - ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_MST_SLV_MODE_MASK); - if (mode == DEV_MASTER_MODE) { - ic_con_val |= IC_CON_ENA_MASTER_MODE; - } else { - ic_con_val |= IC_CON_ENA_SLAVE_MODE; - } - dw_iic_enable(iic_reg_ptr); -} - -/** - * @fn void dw_iic_set_scl_cnt(DW_IIC_REG *iic_reg_ptr, DW_IIC_SCL_CNT *scl_cnt) - * @brief Set IC_CLK frequency by configuration the *CNT registers for different speed modes - */ -Inline void dw_iic_set_scl_cnt(DW_IIC_REG *iic_reg_ptr, DW_IIC_SCL_CNT *scl_cnt) -{ - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_SS_SCL_HCNT = scl_cnt->ss_scl_hcnt; - iic_reg_ptr->IC_SS_SCL_LCNT = scl_cnt->ss_scl_lcnt; - iic_reg_ptr->IC_FS_SCL_HCNT = scl_cnt->fs_scl_hcnt; - iic_reg_ptr->IC_FS_SCL_LCNT = scl_cnt->fs_scl_lcnt; - iic_reg_ptr->IC_HS_SCL_HCNT = scl_cnt->hs_scl_hcnt; - iic_reg_ptr->IC_HS_SCL_LCNT = scl_cnt->hs_scl_lcnt; - dw_iic_enable(iic_reg_ptr); -} - -void dw_iic_calc_spklen(uint32_t clk_khz, DW_IIC_SPKLEN *spklen) -{ - uint32_t clk_ns; - - spklen->fs_spklen = 0; - spklen->hs_spklen = 0; - - if (clk_khz <= 1000000) { - clk_ns = 1000000 / clk_khz; - spklen->fs_spklen = DW_IIC_FS_SPKLEN_NS / clk_ns; - if ((DW_IIC_FS_SPKLEN_NS % clk_ns) != 0) { - spklen->fs_spklen += 1; - } - spklen->hs_spklen = DW_IIC_HS_SPKLEN_NS / clk_ns; - if ((DW_IIC_HS_SPKLEN_NS % clk_ns) != 0) { - spklen->hs_spklen += 1; - } - } else { - clk_ns = clk_khz / 1000000; - spklen->fs_spklen = DW_IIC_FS_SPKLEN_NS * clk_ns; - spklen->hs_spklen = DW_IIC_HS_SPKLEN_NS * clk_ns; - } -} - -void dw_iic_calc_sclcnt(uint32_t clk_khz, uint32_t caploading, DW_IIC_SCL_CNT *scl_cnt, DW_IIC_SPKLEN *spklen) -{ - uint32_t clk_ns; - - clk_ns = 1000000 / clk_khz; - - if (clk_khz <= 1000000) { - // Calculate CNT values for SS - scl_cnt->ss_scl_hcnt = MIN_DW_IIC_SS_HIGH_TIME_NS / clk_ns; - if ((MIN_DW_IIC_SS_HIGH_TIME_NS % clk_ns) != 0) { - scl_cnt->ss_scl_hcnt += 1; - } - scl_cnt->ss_scl_lcnt = MIN_DW_IIC_SS_LOW_TIME_NS / clk_ns; - if ((MIN_DW_IIC_SS_LOW_TIME_NS % clk_ns) != 0) { - scl_cnt->ss_scl_lcnt += 1; - } - // Calculate CNT values for FS - scl_cnt->fs_scl_hcnt = MIN_DW_IIC_FS_HIGH_TIME_NS / clk_ns; - if ((MIN_DW_IIC_FS_HIGH_TIME_NS % clk_ns) != 0) { - scl_cnt->fs_scl_hcnt += 1; - } - scl_cnt->fs_scl_lcnt = MIN_DW_IIC_FS_LOW_TIME_NS / clk_ns; - if ((MIN_DW_IIC_FS_LOW_TIME_NS % clk_ns) != 0) { - scl_cnt->fs_scl_lcnt += 1; - } - // Calculate CNT values for HS - if (caploading == DW_IIC_CAP_LOADING_100PF) { - scl_cnt->hs_scl_hcnt = MIN_DW_IIC_HS_100PF_HIGH_TIME_NS / clk_ns; - if ((MIN_DW_IIC_HS_100PF_HIGH_TIME_NS % clk_ns) != 0) { - scl_cnt->hs_scl_hcnt += 1; - } - scl_cnt->hs_scl_lcnt = MIN_DW_IIC_HS_100PF_LOW_TIME_NS / clk_ns; - if ((MIN_DW_IIC_HS_100PF_LOW_TIME_NS % clk_ns) != 0) { - scl_cnt->hs_scl_lcnt += 1; - } - } else { - scl_cnt->hs_scl_hcnt = MIN_DW_IIC_HS_400PF_HIGH_TIME_NS / clk_ns; - if ((MIN_DW_IIC_HS_400PF_HIGH_TIME_NS % clk_ns) != 0) { - scl_cnt->hs_scl_hcnt += 1; - } - scl_cnt->hs_scl_lcnt = MIN_DW_IIC_HS_400PF_LOW_TIME_NS / clk_ns; - if ((MIN_DW_IIC_HS_400PF_LOW_TIME_NS % clk_ns) != 0) { - scl_cnt->hs_scl_lcnt += 1; - } - } - } else { - // Calculate CNT values for SS - scl_cnt->ss_scl_hcnt = MIN_DW_IIC_SS_HIGH_TIME_NS * clk_ns; - scl_cnt->ss_scl_lcnt = MIN_DW_IIC_SS_LOW_TIME_NS * clk_ns; - // Calculate CNT values for FS - scl_cnt->fs_scl_hcnt = MIN_DW_IIC_FS_HIGH_TIME_NS * clk_ns; - scl_cnt->fs_scl_lcnt = MIN_DW_IIC_FS_LOW_TIME_NS * clk_ns; - // Calculate CNT values for HS - if (caploading == DW_IIC_CAP_LOADING_100PF) { - scl_cnt->hs_scl_hcnt = MIN_DW_IIC_HS_100PF_HIGH_TIME_NS * clk_ns; - scl_cnt->hs_scl_lcnt = MIN_DW_IIC_HS_100PF_LOW_TIME_NS * clk_ns; - } else { - scl_cnt->hs_scl_hcnt = MIN_DW_IIC_HS_400PF_HIGH_TIME_NS * clk_ns; - scl_cnt->hs_scl_lcnt = MIN_DW_IIC_HS_400PF_LOW_TIME_NS * clk_ns; - } - } - if (scl_cnt->ss_scl_hcnt < MIN_DW_IIC_SS_SCL_HCNT(spklen->fs_spklen)) { - scl_cnt->ss_scl_hcnt = MIN_DW_IIC_SS_SCL_HCNT(spklen->fs_spklen); - } - if (scl_cnt->ss_scl_lcnt < MIN_DW_IIC_SS_SCL_LCNT(spklen->fs_spklen)) { - scl_cnt->ss_scl_lcnt = MIN_DW_IIC_SS_SCL_LCNT(spklen->fs_spklen); - } - if (scl_cnt->fs_scl_hcnt < MIN_DW_IIC_FS_SCL_HCNT(spklen->fs_spklen)) { - scl_cnt->fs_scl_hcnt = MIN_DW_IIC_FS_SCL_HCNT(spklen->fs_spklen); - } - if (scl_cnt->fs_scl_lcnt < MIN_DW_IIC_FS_SCL_LCNT(spklen->fs_spklen)) { - scl_cnt->fs_scl_lcnt = MIN_DW_IIC_FS_SCL_LCNT(spklen->fs_spklen); - } - if (scl_cnt->hs_scl_hcnt < MIN_DW_IIC_HS_SCL_HCNT(spklen->hs_spklen)) { - scl_cnt->hs_scl_hcnt = MIN_DW_IIC_HS_SCL_HCNT(spklen->hs_spklen); - } - if (scl_cnt->hs_scl_lcnt < MIN_DW_IIC_HS_SCL_LCNT(spklen->hs_spklen)) { - scl_cnt->hs_scl_lcnt = MIN_DW_IIC_HS_SCL_LCNT(spklen->hs_spklen); - } -} - -/** - * @fn void dw_iic_set_spike_len(DW_IIC_REG *iic_reg_ptr, DW_IIC_SPKLEN *spklen) - * @brief Set spike suppression configuration - */ -Inline void dw_iic_set_spike_len(DW_IIC_REG *iic_reg_ptr, DW_IIC_SPKLEN *spklen) -{ - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_FS_SPKLEN = spklen->fs_spklen; - iic_reg_ptr->IC_HS_SPKLEN = spklen->hs_spklen; - dw_iic_enable(iic_reg_ptr); -} - -/** - * @fn void dw_iic_flush_tx(DW_IIC_REG *iic_reg_ptr) - */ -Inline void dw_iic_flush_tx(DW_IIC_REG *iic_reg_ptr) -{ - (void)iic_reg_ptr->IC_CLR_INTR; -} - -/** - * @fn void dw_iic_flush_rx(DW_IIC_REG *iic_reg_ptr) - */ -Inline void dw_iic_flush_rx(DW_IIC_REG *iic_reg_ptr) -{ -} - -static uint32_t dw_iic_get_slv_state(DW_IIC_REG *iic_reg_ptr) -{ - uint32_t status; - uint32_t slv_state = IIC_SLAVE_STATE_FREE; - - status = iic_reg_ptr->IC_RAW_INTR_STAT; - if (status & IC_INTR_STAT_GEN_CALL) { - /* General Call address is received and it is acknowledged */ - slv_state |= IIC_SLAVE_STATE_GC_REQ; - } - if (status & IC_INTR_STAT_RX_FULL) { - /* master is attempting to write data to this slave */ - slv_state |= IIC_SLAVE_STATE_WR_REQ; - } - if (status & IC_INTR_STAT_RD_REQ) { - /* master is attempting to read data from this slave */ - slv_state |= IIC_SLAVE_STATE_RD_REQ; - } - if (status & IC_INTR_STAT_RX_DONE) { - /* master does not acknowledge a transmitted byte, and transmission is done */ - slv_state |= IIC_SLAVE_STATE_RD_DONE; - status = iic_reg_ptr->IC_CLR_RX_DONE; - } - if (status & IC_INTR_STAT_START_DET) { - /* a START or RESTART condition has occurred */ - slv_state |= IIC_SLAVE_STATE_START; - status = iic_reg_ptr->IC_CLR_START_DET; /* Clear it when read */ - } - if (status & IC_INTR_STAT_STOP_DET) { - /* a STOP condition has occurred */ - slv_state |= IIC_SLAVE_STATE_STOP; - status = iic_reg_ptr->IC_CLR_STOP_DET; /* Clear it when read */ - } - if (status & (IC_INTR_STAT_TX_ABRT | IC_INTR_STAT_TX_OVER \ - | IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER)) { - /* error case */ - slv_state |= IIC_SLAVE_STATE_ERROR; - status = iic_reg_ptr->IC_CLR_TX_ABRT; /* Clear it when read */ - status = iic_reg_ptr->IC_CLR_TX_OVER; - status = iic_reg_ptr->IC_CLR_RX_OVER; - status = iic_reg_ptr->IC_CLR_RX_UNDER; - } - - return slv_state; -} - -/** Init Designware IIC Device into Master mode */ -static void dw_iic_master_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t speed_mode, uint32_t addr_mode, uint32_t tar_addr) -{ - uint32_t ic_con_val = 0; - DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs; - - dw_iic_disable(iic_reg_ptr); - - /* disable all iic interrupt */ - iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL; - - /* Set to 7bit addressing and update target address */ - iic_reg_ptr->IC_TAR = (tar_addr & IC_TAR_10BIT_ADDR_MASK) | IC_TAR_SPECIAL | IC_TAR_GC_OR_START; - /* master mode, restart enabled */ - ic_con_val = dw_iic_select_speedmode(speed_mode) | IC_CON_ENA_MASTER_MODE | IC_CON_RESTART_EN; - -#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT - if (addr_mode == IIC_10BIT_ADDRESS) { - iic_reg_ptr->IC_TAR |= MST_10_BIT_ADDR_MODE; - } -#else - if (addr_mode == IIC_10BIT_ADDRESS) { - ic_con_val |= MST_10_BIT_ADDR_MODE; - } -#endif - /* Set final IC_CON value */ - iic_reg_ptr->IC_CON = ic_con_val; - /* FIFO threshold settings */ - iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD; - iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD; - /* Master code settings */ - iic_reg_ptr->IC_HS_MADDR = iic_ctrl_ptr->iic_master_code; - dw_iic_enable(iic_reg_ptr); - - /* Clock Settings */ - dw_iic_set_spike_len(iic_reg_ptr, &(iic_ctrl_ptr->iic_spklen)); - dw_iic_set_scl_cnt(iic_reg_ptr, &(iic_ctrl_ptr->iic_scl_cnt)); -} - -/** Init Designware IIC Device into Slave mode */ -static void dw_iic_slave_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t addr_mode, uint32_t slv_addr) -{ - uint32_t ic_con_val = 0; - DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs; - - dw_iic_disable(iic_reg_ptr); - - /* disable all iic interrupt */ - iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL; - - /* Set slave device address as a slave */ - iic_reg_ptr->IC_SAR = slv_addr & IC_SAR_10BIT_ADDR_MASK; - /* slave mode, 7 bit slave address */ - ic_con_val = IC_CON_ENA_SLAVE_MODE; - /* If addr mode select to be 10 bit address mode */ - if (addr_mode == IIC_10BIT_ADDRESS) { - ic_con_val |= SLV_10_BIT_ADDR_MODE; - } - - /* Set final IC_CON value */ - iic_reg_ptr->IC_CON = ic_con_val; - /* FIFO threshold settings */ - iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD; - iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD; - - dw_iic_enable(iic_reg_ptr); -} - -/** Check error for IIC master device */ -static int32_t dw_iic_mst_chkerr(DW_IIC_CTRL *iic_ctrl_ptr) -{ - uint32_t status; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - status = iic_reg_ptr->IC_RAW_INTR_STAT; - if (status & IC_INTR_STAT_TX_ABRT) { - status = iic_reg_ptr->IC_TX_ABRT_SOURCE; - if (status & IIC_MST_ABRT_LOST_BUS) { - ercd = IIC_ERR_LOST_BUS; - } else if (status & IIC_MST_ABRT_ADDR_NOACK) { - ercd = IIC_ERR_ADDR_NOACK; - } else if (status & IIC_MST_ABRT_DATA_NOACK) { - ercd = IIC_ERR_DATA_NOACK; - } else { - ercd = IIC_ERR_UNDEF; - } - status = iic_reg_ptr->IC_CLR_TX_ABRT; - } else { - if (status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over++; - status = iic_reg_ptr->IC_CLR_TX_OVER; - } - if (status & (IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over++; - status = iic_reg_ptr->IC_CLR_RX_OVER; - status = iic_reg_ptr->IC_CLR_RX_UNDER; - } - } - return ercd; -} - -/** Check error for IIC slave device */ -static int32_t dw_iic_slv_chkerr(DW_IIC_CTRL *iic_ctrl_ptr) -{ - uint32_t status; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - status = iic_reg_ptr->IC_RAW_INTR_STAT; - if (status & IC_INTR_STAT_TX_ABRT) { - status = iic_reg_ptr->IC_TX_ABRT_SOURCE; - if (status & IIC_SLV_ABRT_LOST_BUS) { - ercd = IIC_ERR_LOST_BUS; - } else if (status & IC_TX_ABRT_SLVFLUSH_TXFIFO) { - /* Flush tx fifo */ - status = iic_reg_ptr->IC_TX_ABRT_SOURCE; - } else { - ercd = IIC_ERR_UNDEF; - } - status = iic_reg_ptr->IC_CLR_TX_ABRT; - } else { - if (status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over++; - status = iic_reg_ptr->IC_CLR_TX_OVER; - } - if (status & (IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over++; - status = iic_reg_ptr->IC_CLR_RX_OVER; - status = iic_reg_ptr->IC_CLR_RX_UNDER; - } - } - return ercd; -} - -/** enable designware iic */ -static void dw_iic_enable_device(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - if ((iic_info_ptr->status & DEV_ENABLED) == 0) { - dw_iic_enable(iic_reg_ptr); - iic_info_ptr->status |= DEV_ENABLED; - } -} - -/** disable designware iic */ -static void dw_iic_disable_device(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - uint32_t i; - - for (i = 0; i < DW_IIC_DISABLE_MAX_T_POLL_CNT; i++) { - dw_iic_disable(iic_reg_ptr); - if ((iic_reg_ptr->IC_ENABLE_STATUS & IC_ENABLE_STATUS_IC_EN) == 0) { - break; - } - } - iic_info_ptr->status &= ~DEV_ENABLED; -} - -static void dw_iic_reset_device(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - dw_iic_disable_device(iic_info_ptr); - dw_iic_clear_interrupt_all(iic_reg_ptr); - iic_info_ptr->next_cond = IIC_MODE_STOP; - iic_info_ptr->cur_state = IIC_FREE; - iic_info_ptr->err_state = IIC_ERR_NONE; - iic_ctrl_ptr->iic_tx_over = 0; - iic_ctrl_ptr->iic_rx_over = 0; - dw_iic_enable_device(iic_info_ptr); -} - -/** Disable iic master interrupt for transmit or receive */ -static void dw_iic_mst_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE; - break; - case DW_IIC_RDY_RCV: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE; - break; - default: - break; - } -} - -/** Disable iic slave interrupt for transmit or receive */ -static void dw_iic_slv_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE; - break; - case DW_IIC_RDY_RCV: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE; - break; - default: - break; - } -} - -/** Enable iic master interrupt for transmit or receive */ -static void dw_iic_mst_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE); - break; - case DW_IIC_RDY_RCV: - iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE); - break; - default: - break; - } -} - -/** Enable iic slave interrupt for transmit or receive */ -static void dw_iic_slv_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE); - break; - case DW_IIC_RDY_RCV: - iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE); - break; - default: - break; - } -} - -/** - * \brief disable designware iic send or receive interrupt - * \param[in] iic_info_ptr IIC device information pointer - * \param[in] cbrtn control code of callback routine of send or receive - */ -static void dw_iic_dis_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - dw_iic_mst_dis_cbr(iic_ctrl_ptr, cbrtn); - } else { - dw_iic_slv_dis_cbr(iic_ctrl_ptr, cbrtn); - } - - if (iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) { - if ((iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE | DW_IIC_TXINT_ENABLE)) == 0) { - if (iic_ctrl_ptr->intno != DW_IIC_INVALID_INTNO) { - int_disable(iic_ctrl_ptr->intno); - } - iic_ctrl_ptr->int_status &= ~DW_IIC_GINT_ENABLE; - } - } -} - -/** - * @brief Enable DesignWare IIC send or receive interrupt - * @param[in] iic_info_ptr IIC device information pointer - * @param[in] cbrtn Control code of callback routine - */ -static void dw_iic_ena_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - dw_iic_mst_ena_cbr(iic_ctrl_ptr, cbrtn); - } else { - dw_iic_slv_ena_cbr(iic_ctrl_ptr, cbrtn); - } - - if ((iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) == 0) { - if (iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE | DW_IIC_TXINT_ENABLE)) { - iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE; - if (iic_ctrl_ptr->intno != DW_IIC_INVALID_INTNO) { - int_enable(iic_ctrl_ptr->intno); - } - } - } -} - -/** - * @brief Enable designware iic interrupt - * @param iic_info_ptr IIC information structure pointer - */ -static void dw_iic_enable_interrupt(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_ctrl_ptr->intno != DW_IIC_INVALID_INTNO) { - int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler); - iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE; - int_enable(iic_ctrl_ptr->intno); /** enable iic interrupt */ - } else { - iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE; - } -} -/** - * @brief Disable designware iic interrupt - * @param iic_info_ptr IIC information structure pointer - */ -static void dw_iic_disable_interrupt(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - /** disable iic send&receive interrupt after disable iic interrupt */ - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - if (iic_ctrl_ptr->intno != DW_IIC_INVALID_INTNO) { - /* disable iic interrupt */ - int_disable(iic_ctrl_ptr->intno); - } - iic_ctrl_ptr->int_status &= ~(DW_IIC_GINT_ENABLE | DW_IIC_TXINT_ENABLE | DW_IIC_RXINT_ENABLE); -} - -/** abort current interrupt transmit transfer */ -static void dw_iic_abort_tx(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_ctrl_ptr->int_status & DW_IIC_TXINT_ENABLE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->status |= DEV_IN_TX_ABRT; - if (iic_info_ptr->iic_cbs.tx_cb != NULL) { - iic_info_ptr->iic_cbs.tx_cb(iic_obj); - } - iic_info_ptr->status &= ~(DEV_IN_TX_ABRT); - } -} - -/** abort current interrupt receive transfer */ -static void dw_iic_abort_rx(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_ctrl_ptr->int_status & DW_IIC_RXINT_ENABLE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->status |= DEV_IN_RX_ABRT; - if (iic_info_ptr->iic_cbs.rx_cb != NULL) { - iic_info_ptr->iic_cbs.rx_cb(iic_obj); - } - iic_info_ptr->status &= ~(DEV_IN_RX_ABRT); - } -} - -/** Get available transmit fifo count */ -static int32_t dw_iic_get_txavail(DW_IIC_CTRL *iic_ctrl_ptr) -{ - int32_t tx_avail = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - if (iic_ctrl_ptr->tx_fifo_len <= 1) { - if (dw_iic_putready(iic_reg_ptr) == 1) { - tx_avail = 1; - } else { - tx_avail = 0; - } - } else { - tx_avail = iic_ctrl_ptr->tx_fifo_len - iic_reg_ptr->IC_TXFLR; - } - return tx_avail; -} - -/** Get available receive fifo count */ -static int32_t dw_iic_get_rxavail(DW_IIC_CTRL *iic_ctrl_ptr) -{ - int32_t rx_avail = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - if (iic_ctrl_ptr->rx_fifo_len <= 1) { - if (dw_iic_getready(iic_reg_ptr) == 1) { - rx_avail = 1; - } else { - rx_avail = 0; - } - } else { - rx_avail = iic_reg_ptr->IC_RXFLR; - } - return rx_avail; -} - -/** - * IIC Master device transmit 1 data, - * next_cond can be @ref IC_DATA_CMD_STOP, - * @ref IC_DATA_CMD_RESTART and ref IC_DATA_CMD_NONE - */ -static int32_t dw_iic_mst_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data, uint32_t next_cond) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - while (dw_iic_putready(iic_reg_ptr) == 0) { - if (i++ > iic_ctrl_ptr->retry_cnt) { - return IIC_ERR_TIMEOUT; - } - ercd = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) { - return ercd; - } - } - dw_iic_putdata(iic_reg_ptr, data | IC_DATA_CMD_WRITE_REQ | next_cond); - - return ercd; -} - -/** IIC Slave device transmit 1 data */ -static int32_t dw_iic_slv_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - uint32_t slv_state, temp; - uint32_t ready2send = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) { - ercd = dw_iic_slv_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) { - return ercd; - } - slv_state = iic_reg_ptr->IC_RAW_INTR_STAT; - if (slv_state & IC_INTR_STAT_RD_REQ) { - if (dw_iic_putready(iic_reg_ptr)) { - temp = iic_reg_ptr->IC_CLR_RD_REQ; - ready2send = 1; - break; - } - } else if (slv_state & IC_INTR_STAT_RX_DONE) { /* Put RX Done before STOP */ - temp = iic_reg_ptr->IC_CLR_RX_DONE; - return IIC_ERR_MSTSTOP; - } else if (slv_state & IC_INTR_STAT_STOP_DET) { - temp = iic_reg_ptr->IC_CLR_STOP_DET; - return IIC_ERR_MSTSTOP; - } - } - if (ready2send) { - dw_iic_putdata(iic_reg_ptr, data | IC_DATA_CMD_WRITE_REQ); - } else { - ercd = IIC_ERR_TIMEOUT; - } - - return ercd; -} - -/** - * IIC Master device receive 1 data, - * next_cond can be @ref IC_DATA_CMD_STOP, - * @ref IC_DATA_CMD_RESTART and @ref IC_DATA_CMD_NONE - */ -static int32_t dw_iic_mst_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data, uint32_t next_cond) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - /* Issue a read request */ - while (dw_iic_putready(iic_reg_ptr) == 0) { - if (i++ > iic_ctrl_ptr->retry_cnt) { - return IIC_ERR_TIMEOUT; - } - ercd = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) { - return ercd; - } - } - dw_iic_putdata(iic_reg_ptr, next_cond | IC_DATA_CMD_READ_REQ); - /* Wait to read data */ - i = 0; - while (dw_iic_getready(iic_reg_ptr) == 0) { - if (i++ > iic_ctrl_ptr->retry_cnt) { - return IIC_ERR_TIMEOUT; - } - ercd = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) { - return ercd; - } - } - *data = dw_iic_getdata(iic_reg_ptr); - return ercd; -} - -/** IIC Slave device receive 1 data */ -static int32_t dw_iic_slv_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - uint32_t slv_state, temp; - uint32_t ready2read = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) { - ercd = dw_iic_slv_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) { - return ercd; - } - slv_state = iic_reg_ptr->IC_RAW_INTR_STAT; - if (slv_state & IC_INTR_STAT_START_DET) { - temp = iic_reg_ptr->IC_CLR_START_DET; - } - if (slv_state & IC_INTR_STAT_RX_FULL) { - if (dw_iic_getready(iic_reg_ptr)) { - ready2read = 1; - break; - } - } else if (slv_state & IC_INTR_STAT_STOP_DET) { - temp = iic_reg_ptr->IC_CLR_STOP_DET; - return IIC_ERR_MSTSTOP; - } - } - if (ready2read) { - *data = dw_iic_getdata(iic_reg_ptr); - } else { - ercd = IIC_ERR_TIMEOUT; - } - - return ercd; -} - -/** IIC Master transmit called in interrupt */ -static void dw_iic_mst_int_write(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs); - uint32_t iic_int_status; /** iic interrupt status */ - uint32_t last_cond, xmit_data, xmit_end = 0; - DEV_BUFFER *buf_ptr; - uint8_t *p_charbuf; - - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - iic_int_status = (iic_reg_ptr->IC_INTR_STAT); - buf_ptr = &(iic_info_ptr->tx_buf); - p_charbuf = (uint8_t *)buf_ptr->buf; - if (p_charbuf) { - if (iic_int_status & IC_INTR_STAT_TX_EMPTY) { - xmit_end = 0; - while (dw_iic_putready(iic_reg_ptr)) { - xmit_data = (uint32_t)(p_charbuf[buf_ptr->ofs]) | IC_DATA_CMD_WRITE_REQ; - if (buf_ptr->ofs == (buf_ptr->len - 1)) { - xmit_end = 1; - xmit_data |= last_cond; - } else { - xmit_data |= IC_DATA_CMD_NONE; - } - buf_ptr->ofs++; - dw_iic_putdata(iic_reg_ptr, xmit_data); - if (xmit_end) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.tx_cb) { - iic_info_ptr->iic_cbs.tx_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - break; - } - } - } - if (iic_int_status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over++; - } - if (iic_int_status & IC_INTR_STAT_TX_ABRT) { - iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (iic_info_ptr->err_state != IIC_ERR_NONE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.err_cb) { - iic_info_ptr->iic_cbs.err_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - } - } - } else { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - } - /* Clear Interrupt */ - iic_int_status = iic_reg_ptr->IC_CLR_INTR; -} - -/** IIC Master receive called in interrupt */ -static void dw_iic_mst_int_read(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs); - uint32_t iic_int_status; /** iic interrupt status */ - uint32_t last_cond, xmit_data; - DEV_BUFFER *buf_ptr; - DW_IIC_BUFFER *dw_iic_rxbuf_ptr; - uint8_t *p_charbuf; - - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - iic_int_status = (iic_reg_ptr->IC_INTR_STAT); - buf_ptr = &(iic_info_ptr->rx_buf); - p_charbuf = (uint8_t *)buf_ptr->buf; - if (p_charbuf) { - dw_iic_rxbuf_ptr = &(iic_ctrl_ptr->dw_iic_rxbuf); - if (iic_int_status & IC_INTR_STAT_TX_EMPTY) { - while (dw_iic_putready(iic_reg_ptr)) { - if (dw_iic_rxbuf_ptr->ofs >= dw_iic_rxbuf_ptr->len) { - dw_iic_mask_interrupt(iic_reg_ptr, IC_INTR_STAT_TX_EMPTY); - break; - } - xmit_data = IC_DATA_CMD_READ_REQ; - if (dw_iic_rxbuf_ptr->ofs == (dw_iic_rxbuf_ptr->len - 1)) { - xmit_data |= last_cond; - } else { - xmit_data |= IC_DATA_CMD_NONE; - } - dw_iic_rxbuf_ptr->ofs++; - dw_iic_putdata(iic_reg_ptr, xmit_data); - } - } - if (iic_int_status & IC_INTR_STAT_RX_FULL) { - while (dw_iic_getready(iic_reg_ptr)) { - p_charbuf[buf_ptr->ofs] = dw_iic_getdata(iic_reg_ptr); - buf_ptr->ofs++; - if (buf_ptr->ofs >= buf_ptr->len) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.rx_cb) { - iic_info_ptr->iic_cbs.rx_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - dw_iic_rxbuf_ptr->ofs = 0; - dw_iic_rxbuf_ptr->len = 0; - break; - } - } - } - if (iic_int_status & (IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over++; - } - if (iic_int_status & IC_INTR_STAT_TX_ABRT) { - iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (iic_info_ptr->err_state != IIC_ERR_NONE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.err_cb) { - iic_info_ptr->iic_cbs.err_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - dw_iic_rxbuf_ptr->ofs = 0; - dw_iic_rxbuf_ptr->len = 0; - } - } - } else { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->cur_state = IIC_FREE; - } - /* Clear Interrupt */ - iic_int_status = iic_reg_ptr->IC_CLR_INTR; -} - -/** IIC Slave transmit called in interrupt */ -static void dw_iic_slv_int_process(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs); - uint32_t iic_int_status; /** iic interrupt status */ - - iic_int_status = (iic_reg_ptr->IC_INTR_STAT); - if (iic_int_status & IC_INTR_STAT_RD_REQ) { /* Read request from master */ - if (iic_info_ptr->iic_cbs.tx_cb) { - iic_info_ptr->iic_cbs.tx_cb(iic_obj); - } else { /* When tx callback function is not set disable this tx int for slave */ - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - } - } - if (iic_int_status & IC_INTR_STAT_RX_FULL) { /* Write request from master */ - if (iic_info_ptr->iic_cbs.rx_cb) { - iic_info_ptr->iic_cbs.rx_cb(iic_obj); - } else { /* When rx callback function is not set disable this rx int for slave */ - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - } - } - if (iic_int_status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over++; - } - if (iic_int_status & (IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over++; - } - if (iic_int_status & IC_INTR_STAT_TX_ABRT) { - iic_info_ptr->err_state = dw_iic_slv_chkerr(iic_ctrl_ptr); - if (iic_info_ptr->err_state != IIC_ERR_NONE) { - if (iic_info_ptr->iic_cbs.err_cb) { - iic_info_ptr->iic_cbs.err_cb(iic_obj); - } - } - } - /* Clear Interrupt */ - iic_int_status = iic_reg_ptr->IC_CLR_INTR; -} - -/** @} end of group DEVICE_DW_IIC_STATIC */ - -/** - * @defgroup DEVICE_DW_IIC_IMPLEMENT DesignWare IIC Driver Function API Implement - * @ingroup DEVICE_DW_IIC - * @brief HAL IIC implemention with DesignWare IIC - * @{ - */ - -/** - * @brief Open a designware iic device - * @param[in] iic_obj IIC device object pointer - * @param[in] mode IIC working mode (master or slave) - * @param[in] param When mode is @ref DEV_MASTER_MODE, param stands for @ref DEV_IIC_INFO::speed_mode "speed mode", - * when mode is @ref DEV_SLAVE_MODE, param stands for @ref DEV_IIC_INFO::slv_addr "slave device 7bit address" - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_IIC_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ -int32_t dw_iic_open(DEV_IIC *iic_obj, uint32_t mode, uint32_t param) -{ - int32_t ercd = E_OK; - uint32_t support_modes; - uint32_t param2check; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP((mode == DEV_MASTER_MODE) || (mode == DEV_SLAVE_MODE), E_PAR); - if (mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP((param >= IIC_SPEED_STANDARD) && (param <= IIC_SPEED_ULTRA), E_PAR); - } - /* END OF ERROR CHECK */ - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - /* Check supported modes, master or slave */ - support_modes = iic_ctrl_ptr->support_modes; - DW_IIC_CHECK_EXP((((support_modes) & DW_IIC_MASTER_SUPPORTED) && (mode == DEV_MASTER_MODE)) || \ - (((support_modes) & DW_IIC_SLAVE_SUPPORTED) && (mode == DEV_SLAVE_MODE)), E_NOSPT); - - /** Check opened before use case */ - if (iic_info_ptr->opn_cnt > 0) { - if (mode != iic_info_ptr->mode) { - /* current working mode is different from passing mode */ - return E_SYS; - } - if (mode == DEV_MASTER_MODE) { /* param is speed_mode when as master */ - param2check = iic_info_ptr->speed_mode; - } else { /* param is slv_addr when as slave */ - param2check = iic_info_ptr->slv_addr; - } - iic_info_ptr->opn_cnt++; - if (param != param2check) { /* open with different speed mode */ - return E_OPNED; - } else { - return E_OK; - } - } - /* auto increase open count */ - iic_info_ptr->opn_cnt++; - - iic_info_ptr->mode = mode; - if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) { - iic_info_ptr->tar_addr &= IIC_7BIT_ADDRESS_MASK; - iic_info_ptr->slv_addr &= IIC_7BIT_ADDRESS_MASK; - } else { - iic_info_ptr->addr_mode = IIC_10BIT_ADDRESS; - iic_info_ptr->tar_addr &= IIC_10BIT_ADDRESS_MASK; - iic_info_ptr->slv_addr &= IIC_10BIT_ADDRESS_MASK; - } - -/* Do FIFO Length get before init */ -#if DW_IIC_CALC_FIFO_LEN_ENABLE - iic_ctrl_ptr->tx_fifo_len = dw_iic_get_txfifo_len(iic_ctrl_ptr->dw_iic_regs); - iic_ctrl_ptr->rx_fifo_len = dw_iic_get_rxfifo_len(iic_ctrl_ptr->dw_iic_regs); -#endif - - dw_iic_calc_spklen(iic_ctrl_ptr->ic_clkhz / 1000, &(iic_ctrl_ptr->iic_spklen)); - dw_iic_calc_sclcnt(iic_ctrl_ptr->ic_clkhz / 1000, iic_ctrl_ptr->ic_caploading, \ - &(iic_ctrl_ptr->iic_scl_cnt), &(iic_ctrl_ptr->iic_spklen)); - /* Disable device before init it */ - dw_iic_disable_device(iic_info_ptr); - - if (mode == DEV_MASTER_MODE) { - iic_info_ptr->speed_mode = param; - dw_iic_master_init(iic_ctrl_ptr, param, iic_info_ptr->addr_mode, iic_info_ptr->tar_addr); - } else { - iic_info_ptr->slv_addr = param; - dw_iic_slave_init(iic_ctrl_ptr, iic_info_ptr->addr_mode, param); - } - iic_info_ptr->status = DEV_ENABLED; - iic_info_ptr->cur_state = IIC_FREE; - iic_info_ptr->err_state = IIC_ERR_NONE; - iic_info_ptr->next_cond = IIC_MODE_STOP; - iic_info_ptr->extra = NULL; - - iic_ctrl_ptr->iic_tx_over = 0; - iic_ctrl_ptr->iic_rx_over = 0; - iic_ctrl_ptr->int_status = 0; - memset(&(iic_ctrl_ptr->dw_iic_rxbuf), 0, sizeof(DW_IIC_BUFFER)); - iic_ctrl_ptr->dw_iic_rxbuf.buf = &(iic_info_ptr->rx_buf); - /** install iic interrupt into system */ - dw_iic_disable_interrupt(iic_info_ptr); - if (iic_ctrl_ptr->intno != DW_IIC_INVALID_INTNO) { - int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler); - } - memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS)); - -error_exit: - return ercd; -} - -/** - * @brief Close a DesignWare IIC device - * @param[in] iic_obj IIC device object pointer - * @retval E_OK Close successfully without any issues(including secenary that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_IIC_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ -int32_t dw_iic_close(DEV_IIC *iic_obj) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_OK); - /* END OF ERROR CHECK */ - - iic_info_ptr->opn_cnt--; - if (iic_info_ptr->opn_cnt == 0) { - dw_iic_disable_interrupt(iic_info_ptr); - dw_iic_abort_tx(iic_obj); - dw_iic_abort_rx(iic_obj); - memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS)); - dw_iic_disable_device(iic_info_ptr); - iic_info_ptr->status = DEV_DISABLED; - iic_info_ptr->next_cond = IIC_MODE_STOP; - iic_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** - * @brief Control iic by ctrl command - * @param[in] iic_obj IIC device object pointer - * @param[in] ctrl_cmd @ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic - * @param[in,out] param Parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ -int32_t dw_iic_control(DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED); - /* END OF ERROR CHECK */ - - uint32_t val32; /** to receive unsigned int value */ - DEV_BUFFER *devbuf; - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - /* check whether current device is disabled */ - if ((iic_info_ptr->status & DEV_ENABLED) == 0) { - /** When device is disabled, - * only IIC_CMD_ENA_DEV, IIC_CMD_DIS_DEV, IIC_CMD_GET_STATUS, IIC_CMD_RESET - * are available, other commands will return E_SYS - */ - if ((ctrl_cmd != IIC_CMD_ENA_DEV) && \ - (ctrl_cmd != IIC_CMD_DIS_DEV) && \ - (ctrl_cmd != IIC_CMD_GET_STATUS) && \ - (ctrl_cmd != IIC_CMD_RESET)) { - return E_SYS; - } - } - - switch (ctrl_cmd) { - /* Commmon commands for both master and slave mode */ - case IIC_CMD_GET_STATUS: - DW_IIC_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = iic_info_ptr->status; - break; - case IIC_CMD_ENA_DEV: - dw_iic_enable_device(iic_info_ptr); - break; - case IIC_CMD_DIS_DEV: - dw_iic_disable_device(iic_info_ptr); - break; - case IIC_CMD_RESET: - dw_iic_reset_device(iic_info_ptr); - break; - case IIC_CMD_FLUSH_TX: - dw_iic_flush_tx(iic_reg_ptr); - break; - case IIC_CMD_FLUSH_RX: - dw_iic_flush_rx(iic_reg_ptr); - break; - case IIC_CMD_SET_ADDR_MODE: - val32 = (uint32_t)param; - DW_IIC_CHECK_EXP((val32 == IIC_7BIT_ADDRESS) || (val32 == IIC_10BIT_ADDRESS), E_PAR); - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - dw_iic_set_mstaddr_mode(iic_reg_ptr, val32); - } else { - dw_iic_set_slvaddr_mode(iic_reg_ptr, val32); - } - iic_info_ptr->addr_mode = val32; - break; - case IIC_CMD_GET_RXAVAIL: - DW_IIC_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_iic_get_rxavail(iic_ctrl_ptr); - break; - case IIC_CMD_GET_TXAVAIL: - DW_IIC_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_iic_get_txavail(iic_ctrl_ptr); - break; - case IIC_CMD_SET_TXCB: - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - iic_info_ptr->iic_cbs.tx_cb = param; - break; - case IIC_CMD_SET_RXCB: - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - iic_info_ptr->iic_cbs.rx_cb = param; - break; - case IIC_CMD_SET_ERRCB: - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - iic_info_ptr->iic_cbs.err_cb = param; - break; - case IIC_CMD_ABORT_TX: - dw_iic_abort_tx(iic_obj); - if ((iic_info_ptr->mode == DEV_MASTER_MODE) \ - && (iic_info_ptr->cur_state == IIC_IN_TX)) { - iic_info_ptr->cur_state = IIC_FREE; - } - break; - case IIC_CMD_ABORT_RX: - dw_iic_abort_rx(iic_obj); - if ((iic_info_ptr->mode == DEV_MASTER_MODE) \ - && (iic_info_ptr->cur_state == IIC_IN_RX)) { - iic_info_ptr->cur_state = IIC_FREE; - } - break; - case IIC_CMD_SET_TXINT: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX); - } - val32 = (uint32_t)param; - if (val32 == 0) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - } else { - iic_info_ptr->cur_state = IIC_IN_TX; - dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_SND); - } - break; - case IIC_CMD_SET_RXINT: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX); - } - val32 = (uint32_t)param; - if (val32 == 0) { - iic_info_ptr->cur_state = IIC_FREE; - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - } else { - iic_info_ptr->cur_state = IIC_IN_RX; - dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - } - break; - case IIC_CMD_SET_TXINT_BUF: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX); - } - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - iic_info_ptr->tx_buf = *devbuf; - iic_info_ptr->tx_buf.ofs = 0; - } else { - iic_info_ptr->tx_buf.buf = NULL; - iic_info_ptr->tx_buf.len = 0; - iic_info_ptr->tx_buf.ofs = 0; - } - break; - case IIC_CMD_SET_RXINT_BUF: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX); - } - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - iic_info_ptr->rx_buf = *devbuf; - iic_info_ptr->rx_buf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.len = devbuf->len; - } else { - iic_info_ptr->rx_buf.buf = NULL; - iic_info_ptr->rx_buf.len = 0; - iic_info_ptr->rx_buf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.len = 0; - } - break; - - /* Master mode only commands */ - case IIC_CMD_MST_SET_SPEED_MODE: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - val32 = (uint32_t)param; - DW_IIC_CHECK_EXP((val32 >= IIC_SPEED_STANDARD) && (val32 <= IIC_SPEED_ULTRA), E_PAR); - dw_iic_set_speedmode(iic_reg_ptr, val32); - iic_info_ptr->speed_mode = val32; - break; - case IIC_CMD_MST_SET_TAR_ADDR: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) { - val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK; - } else { - val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK; - } - if (val32 != iic_info_ptr->tar_addr) { - dw_iic_set_taraddr(iic_reg_ptr, val32); - iic_info_ptr->tar_addr = val32; - } - break; - case IIC_CMD_MST_SET_NEXT_COND: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - val32 = (uint32_t)param; - DW_IIC_CHECK_EXP((val32 == IIC_MODE_STOP) || (val32 == IIC_MODE_RESTART), E_PAR); - iic_info_ptr->next_cond = (uint32_t)param; - break; - - /* Slave mode only commands */ - case IIC_CMD_SLV_SET_SLV_ADDR: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT); - if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) { - val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK; - } else { - val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK; - } - dw_iic_set_slvaddr(iic_reg_ptr, val32); - iic_info_ptr->slv_addr = val32; - break; - case IIC_CMD_SLV_GET_SLV_STATE: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT); - DW_IIC_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((uint32_t *)param) = dw_iic_get_slv_state(iic_reg_ptr); - break; - - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** - * @brief Poll transmit data through DesignWare IIC as master or slave - * @param[in] iic_obj IIC device object pointer - * @param[in] data Data to send (data must be uint8_t type) - * @param[in] len Data length to send - * @retval > 0 Byte count that was successfully sent for poll method, - * it might can't send that much due to @ref DEV_IIC_INFO::err_state "different error state". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_CTX Device is still in transfer state - * @retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ -int32_t dw_iic_write(DEV_IIC *iic_obj, const void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED); - DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS); - DW_IIC_CHECK_EXP(data != NULL, E_PAR); - DW_IIC_CHECK_EXP(len > 0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - uint32_t last_cond = 0; /* Last data for transmit, STOP or RESTART */ - int32_t error_state = IIC_ERR_NONE; - const uint8_t *p_charbuf = (const uint8_t *)data; - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode transmit data */ - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - - /* Try to transmit 0 -> (len-1) data */ - len = len - 1; /* Last data write differently */ - while (i < len) { - error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i]), IC_DATA_CMD_NONE); - if (error_state != IIC_ERR_NONE) { - break; - } - i++; - } - /* Try to transmit the last data with STOP or RESTART condition */ - if (error_state == IIC_ERR_NONE) { - error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[len]), last_cond); - if (error_state == IIC_ERR_NONE) { - i = i + 1; /* Add last data into send count */ - } - } - } else { /* Slave mode transmit data */ - while (i < len) { - error_state = dw_iic_slv_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i])); - if (error_state != IIC_ERR_NONE) { - break; - } - i++; - } - } - iic_info_ptr->err_state = error_state; - ercd = i; - -error_exit: - return ercd; -} - -/** - * @brief Read data through DesignWare IIC - * @param[in] iic_obj IIC device object pointer - * @param[out] data Data that need to read (data must be uint8_t type) - * @param[in] len Data length need to read - * @retval > 0 Byte count that was successfully received for poll method, - * it might can't send that much due to @ref DEV_IIC_INFO::err_state "different error state". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_CTX Device is still in transfer state - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -int32_t dw_iic_read(DEV_IIC *iic_obj, void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED); - DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS); - DW_IIC_CHECK_EXP(data != NULL, E_PAR); - DW_IIC_CHECK_EXP(len > 0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - uint32_t last_cond = 0; /* Last data for receive, STOP or RESTART */ - uint32_t val32 = 0; - int32_t error_state = IIC_ERR_NONE; - uint8_t *p_charbuf = (uint8_t *)data; - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode receive data */ - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - - /* Try to receive 0 -> (len-1) data */ - len = len - 1; /* Last data write differently */ - while (i < len) { - error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, IC_DATA_CMD_NONE); - if (error_state != IIC_ERR_NONE) { - break; - } else { - p_charbuf[i] = (uint8_t)val32; - } - i++; - } - /* Try to receive the last data with STOP or RESTART condition */ - if (error_state == IIC_ERR_NONE) { - error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, last_cond); - if (error_state == IIC_ERR_NONE) { - p_charbuf[len] = (uint8_t)val32; - i = i + 1; /* Add last data into send count */ - } - } - } else { /* Slave mode receive data */ - while (i < len) { - error_state = dw_iic_slv_read_data(iic_ctrl_ptr, &val32); - if (error_state != IIC_ERR_NONE) { - break; - } else { - p_charbuf[i] = (uint8_t)val32; - } - i++; - } - } - iic_info_ptr->err_state = error_state; - ercd = i; - -error_exit: - return ercd; -} - -/** - * @brief DesignWare IIC interrupt processing handler - * @param[in] iic_obj IIC device pointer - * @param[in] ptr Extra information - */ -void dw_iic_isr(DEV_IIC *iic_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - /* END OF ERROR CHECK */ - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - if (iic_info_ptr->cur_state == IIC_IN_TX) { - dw_iic_mst_int_write(iic_obj); - } else { - dw_iic_mst_int_read(iic_obj); - } - } else { - dw_iic_slv_int_process(iic_obj); - } - -error_exit: - return; -} -/** @} end of group DEVICE_DW_IIC_IMPLEMENT */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/pwm_timer/dw_pwm_timer.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/pwm_timer/dw_pwm_timer.c deleted file mode 100644 index 58fd1098..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/pwm_timer/dw_pwm_timer.c +++ /dev/null @@ -1,400 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "arc/arc_exception.h" - -#include "device/designware/dw_pwm_timer.h" - -/** check expressions used in DesignWare PWM_TIMER driver implementation */ -#define DW_PWM_TIMER_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of uart info object */ -#define VALID_CHK_PWM_TIMER_INFO_OBJECT(pwm_timerinfo_obj_ptr) { \ - DW_PWM_TIMER_CHECK_EXP((pwm_timerinfo_obj_ptr) != NULL, E_OBJ); \ - DW_PWM_TIMER_CHECK_EXP(((pwm_timerinfo_obj_ptr)->pwm_timer_ctrl) != NULL, E_OBJ); \ -} -#endif - -/** - * @fn uint32_t dw_pwm_timer_int_read_status(DW_PWM_TIMER_CTRL_PTR port) - */ -Inline uint32_t dw_pwm_timer_int_read_status(DW_PWM_TIMER_CTRL_PTR port) -{ - return port->regs->PWM_TIMERS_INT_STATUS; -} - -/** - * @fn void dw_pwm_timer_timer_enable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) - */ -Inline void dw_pwm_timer_timer_enable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) -{ - port->regs->CTRL[ch].CONTROL_REG |= 0x03; -} - -/** - * @fn void dw_pwm_timer_timer_disable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) - */ -Inline void dw_pwm_timer_timer_disable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) -{ - port->regs->CTRL[ch].CONTROL_REG &= (~0x03); -} - -/** - * @fn void dw_pwm_timer_pwm_enable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) - */ -Inline void dw_pwm_timer_pwm_enable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) -{ - port->regs->CTRL[ch].CONTROL_REG |= 0x08; -} - -/** - * @fn void dw_pwm_timer_pwm_disable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) - */ -Inline void dw_pwm_timer_pwm_disable(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) -{ - port->regs->CTRL[ch].CONTROL_REG &= (~0x08); -} - -/** - * @fn void dw_pwm_timer_count_set(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch, uint16_t val) - */ -Inline void dw_pwm_timer_count_set(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch, uint16_t val) -{ - port->regs->CTRL[ch].LOAD_COUNT = val; -} - -/** - * @fn uint16_t dw_pwm_timer_count_get(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch) - */ -Inline uint16_t dw_pwm_timer_count_get(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch) -{ - return port->regs->CTRL[ch].LOAD_COUNT; -} - -/** - * @fn void dw_pwm_timer_count2_set(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch, uint16_t val) - */ -Inline void dw_pwm_timer_count2_set(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch, uint16_t val) -{ - port->regs->LOAD_COUNT2[ch] = val; -} - -/** - * @fn uint16_t dw_pwm_timer_count2_get(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch) - */ -Inline uint16_t dw_pwm_timer_count2_get(DW_PWM_TIMER_CTRL_PTR port, uint8_t ch) -{ - return port->regs->LOAD_COUNT2[ch]; -} - -static void dw_pwm_timer_int_clear_all(DW_PWM_TIMER_CTRL_PTR port) -{ - int32_t reg_val; - - reg_val = port->regs->PWM_TIMERS_EOI; -} - -static void dw_pwm_timer_int_clear(DW_PWM_TIMER_CTRL_PTR port, uint32_t ch) -{ - int32_t reg_val; - - reg_val = port->regs->CTRL[ch].EOI; -} - -/* interface for DEV_PWM_TIMER */ -/** Open designware pwm_timer device */ -int32_t dw_pwm_timer_open(DEV_PWM_TIMER *pwm_timer_obj) -{ - int32_t ercd = E_OK; - DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info); - - /* START ERROR CHECK */ - VALID_CHK_PWM_TIMER_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl); - - port_info_ptr->opn_cnt++; - if (port_info_ptr->opn_cnt > 1) { /* opened before */ - return E_OPNED; - } - - if (port->intno != DW_PWM_TIMER_INVALID_INTNO) { - for (uint8_t i = 0; i < port->ch_num; i++) { - dw_pwm_timer_timer_disable(port, i); - dw_pwm_timer_pwm_disable(port, i); - int_disable(port->intno + i); - int_handler_install(port->intno + i, port->int_handler); - } - } - -error_exit: - return ercd; -} - -/** Close designware pwm_timer device */ -int32_t dw_pwm_timer_close(DEV_PWM_TIMER *pwm_timer_obj) -{ - int32_t ercd = E_OK; - DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info); - - /* START ERROR CHECK */ - VALID_CHK_PWM_TIMER_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl); - - DW_PWM_TIMER_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_OK); - - port_info_ptr->opn_cnt--; - if (port_info_ptr->opn_cnt == 0) { - - if (port->intno != DW_PWM_TIMER_INVALID_INTNO) { - for (uint8_t i = 0; i < port->ch_num; i++) { - dw_pwm_timer_timer_disable(port, i); - dw_pwm_timer_pwm_disable(port, i); - int_disable(port->intno + i); - } - } - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** Read designware pwm_timer device value */ -int32_t dw_pwm_timer_read(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc) -{ - int32_t ercd = E_OK; - DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info); - - /* START ERROR CHECK */ - VALID_CHK_PWM_TIMER_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl); - DW_PWM_TIMER_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - DW_PWM_TIMER_CHECK_EXP((ch >= 0) && (ch < port->ch_num), E_PAR); - - int32_t count_low = dw_pwm_timer_count_get(port, ch); - int32_t count_high = dw_pwm_timer_count2_get(port, ch); - - *mode = port->mode[ch]; - if (*mode == DEV_PWM_TIMER_MODE_TIMER) { - *dc = 100; - if (count_low != 0) { - *freq = port->clock / (count_low * 2); - } else { - *freq = 0; - } - } else if (*mode == DEV_PWM_TIMER_MODE_PWM) { - if (count_low == 0 && count_high == 0) { - *dc = 0; - *freq = 0; - } else { - *dc = (count_high * 100) / (count_high + count_low); - *freq = port->clock / (count_high + count_low); - } - } else { - *dc = 0; - *freq = 0; - } - -error_exit: - return ercd; -} - -/** Write designware pwm_timer device value */ -int32_t dw_pwm_timer_write(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc) -{ - int32_t ercd = E_OK; - int32_t count, count_high; - DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info); - - /* START ERROR CHECK */ - VALID_CHK_PWM_TIMER_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl); - DW_PWM_TIMER_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - DW_PWM_TIMER_CHECK_EXP((ch >= 0) && (ch < port->ch_num), E_PAR); - DW_PWM_TIMER_CHECK_EXP((dc >= 0) && (dc <= 100), E_PAR); - - if (mode == DEV_PWM_TIMER_MODE_TIMER) { - DW_PWM_TIMER_CHECK_EXP(freq > 0, E_PAR); - port->mode[ch] = mode; - - count = port->clock / freq; - dw_pwm_timer_count_set(port, ch, count / 2); - dw_pwm_timer_count2_set(port, ch, 0); - - dw_pwm_timer_timer_enable(port, ch); - dw_pwm_timer_pwm_disable(port, ch); - int_enable(port->intno + ch); - } else if (mode == DEV_PWM_TIMER_MODE_PWM) { - DW_PWM_TIMER_CHECK_EXP(freq > 0, E_PAR); - port->mode[ch] = mode; - - count = port->clock / freq; - count_high = (count * dc) / 100; - dw_pwm_timer_count_set(port, ch, count - count_high); - dw_pwm_timer_count2_set(port, ch, count_high); - dw_pwm_timer_timer_enable(port, ch); - dw_pwm_timer_pwm_enable(port, ch); - int_disable(port->intno + ch); - } else if (mode == DEV_PWM_TIMER_MODE_CLOSE) { - port->mode[ch] = mode; - dw_pwm_timer_count_set(port, ch, 0); - dw_pwm_timer_count2_set(port, ch, 0); - dw_pwm_timer_timer_disable(port, ch); - dw_pwm_timer_pwm_disable(port, ch); - int_disable(port->intno + ch); - } -error_exit: - return ercd; -} - -/** Control designware pwm_timer device */ -int32_t dw_pwm_timer_control(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t ctrl_cmd, void *par) -{ - int32_t ercd = E_OK; - DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info); - - /* START ERROR CHECK */ - VALID_CHK_PWM_TIMER_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl); - DW_PWM_TIMER_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - DW_PWM_TIMER_CHECK_EXP((ch >= 0) && (ch < port->ch_num), E_PAR); - - DEV_PWM_TIMER_CFG *cfg_ptr; - switch (ctrl_cmd) { - case PWM_TIMER_CMD_SET_CFG: - cfg_ptr = (DEV_PWM_TIMER_CFG *) par; - - dw_pwm_timer_count_set(port, ch, cfg_ptr->count_low); - dw_pwm_timer_count2_set(port, ch, cfg_ptr->count_high); - if (cfg_ptr->isr_hander != NULL) { - port->ch_isr->int_ch_handler_ptr[ch] = cfg_ptr->isr_hander; - } - if (cfg_ptr->mode == DEV_PWM_TIMER_MODE_TIMER) { - port->mode[ch] = cfg_ptr->mode; - dw_pwm_timer_timer_enable(port, ch); - int_enable(port->intno + ch); - } else if (cfg_ptr->mode == DEV_PWM_TIMER_MODE_PWM) { - port->mode[ch] = cfg_ptr->mode; - dw_pwm_timer_timer_enable(port, ch); - dw_pwm_timer_pwm_enable(port, ch); - } else if (cfg_ptr->mode == DEV_PWM_TIMER_MODE_CLOSE) { - port->mode[ch] = cfg_ptr->mode; - dw_pwm_timer_timer_disable(port, ch); - dw_pwm_timer_pwm_disable(port, ch); - } - break; - case PWM_TIMER_CMD_GET_CFG: - cfg_ptr = (DEV_PWM_TIMER_CFG *) par; - cfg_ptr->count_low = dw_pwm_timer_count_get(port, ch); - cfg_ptr->count_high = dw_pwm_timer_count2_get(port, ch); - if (cfg_ptr->isr_hander != NULL) { - cfg_ptr->isr_hander = port->ch_isr->int_ch_handler_ptr[ch]; - } - cfg_ptr->mode = port->mode[ch]; - break; - case PWM_TIMER_CMD_DIS_CH: - dw_pwm_timer_timer_disable(port, ch); - break; - case PWM_TIMER_CMD_ENA_CH: - dw_pwm_timer_timer_enable(port, ch); - break; - case PWM_TIMER_CMD_DIS_ISR: - int_disable(port->intno + ch); - break; - case PWM_TIMER_CMD_ENA_ISR: - int_enable(port->intno + ch); - break; - case PWM_TIMER_CMD_SET_ISR: - DW_PWM_TIMER_CHECK_EXP((par != NULL) && CHECK_ALIGN_4BYTES(par), E_PAR); - port->ch_isr->int_ch_handler_ptr[ch] = (DEV_PWM_TIMER_HANDLER)par; - break; - case PWM_TIMER_CMD_GET_ISR: - DW_PWM_TIMER_CHECK_EXP((par != NULL) && CHECK_ALIGN_4BYTES(par), E_PAR); - par = (void *)(port->ch_isr->int_ch_handler_ptr[ch]); - break; - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** designware pwm_timer interrupt process */ -int32_t dw_pwm_timer_isr_handler(DEV_PWM_TIMER *pwm_timer_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info); - - /* START ERROR CHECK */ - VALID_CHK_PWM_TIMER_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl); - - uint32_t i, pwm_timer_bit_isr_state; - uint32_t max_int_bit_count = 0; - - /** read interrupt status */ - pwm_timer_bit_isr_state = dw_pwm_timer_int_read_status(port); - - if (port->ch_isr) { - max_int_bit_count = (port->ch_isr->int_ch_max_cnt); - } else { - dw_pwm_timer_int_clear_all(port); - } - - for (i = 0; i < max_int_bit_count; i++) { - if (pwm_timer_bit_isr_state & (1 << i)) { - /* this bit interrupt enabled */ - if (port->ch_isr->int_ch_handler_ptr[i]) { - port->ch_isr->int_ch_handler_ptr[i](pwm_timer_obj); - } - dw_pwm_timer_int_clear(port, i); /** clear this bit interrupt */ - } - } - -error_exit: - return ercd; -} diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/sdio/dw_sdio.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/sdio/dw_sdio.c deleted file mode 100644 index 6a70f2fa..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/sdio/dw_sdio.c +++ /dev/null @@ -1,594 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "arc/arc_exception.h" -#include "board.h" -#include "device/designware/dw_sdio_hal.h" -#include "device/designware/dw_sdio.h" -#include "embARC_debug.h" - -#define min(a, b) (((a) < (b)) ? (a) : (b)) - -/** - * @fn void dw_sdio_enable_card_threshold(DW_SDIO_CTRL_PTR sdio, uint32_t threshold) - */ -Inline void dw_sdio_enable_card_threshold(DW_SDIO_CTRL_PTR sdio, uint32_t threshold) -{ - /* according to datasheet, write threshold is only applicable for HS400 mode */ - uint32_t reg; - - reg = dw_sdio_reg_read(sdio, DWSDIO_REG_CARD_THR_CTRL); - reg |= 0x1; - dw_sdio_reg_write(sdio, DWSDIO_REG_CARD_THR_CTRL, reg); -} - -/** - * @fn void dw_sdio_block_size_set(DW_SDIO_CTRL_PTR sdio, uint32_t bytes, uint32_t blksz) - */ -Inline void dw_sdio_block_size_set(DW_SDIO_CTRL_PTR sdio, uint32_t bytes, uint32_t blksz) -{ - dw_sdio_reg_write(sdio, DWSDIO_REG_BYTCNT, bytes); - dw_sdio_reg_write(sdio, DWSDIO_REG_BLKSIZ, blksz); -} - -/** - * @fn void dw_sdio_fifo_read_poll(DW_SDIO_CTRL_PTR sdio, uint32_t *buf, uint32_t size) - */ -Inline void dw_sdio_fifo_read_poll(DW_SDIO_CTRL_PTR sdio, uint32_t *buf, uint32_t size) -{ - uint32_t len; - uint32_t i; - - while (size) { - do { - len = dw_sdio_reg_read(sdio, DWSDIO_REG_STATUS); - } while (len & DWSDIO_STATUS_FIFO_EMPTY); - - len = (len & DWSDIO_STATUS_MASK_FIFO) >> DWSDIO_STATUS_BIT_FIFO; - - len = min(size, len); - - for (i = 0; i < len; i++) { - *buf++ = dw_sdio_reg_read(sdio, DWSDIO_REG_DATA); - } - size = size > len ? (size - len) : 0; - } -} - -/** - * @fn void dw_sdio_clk_enable(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) - */ -Inline void dw_sdio_clk_enable(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) -{ - uint32_t reg; - - reg = dw_sdio_reg_read(sdio, DWSDIO_REG_CLKENA); - reg |= (1 << card_number); - dw_sdio_reg_write(sdio, DWSDIO_REG_CLKENA, reg); -} - -/** - * @fn dw_sdio_clk_disable(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) - */ -Inline void dw_sdio_clk_disable(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) -{ - uint32_t reg; - - reg = dw_sdio_reg_read(sdio, DWSDIO_REG_CLKENA); - reg &= ~(1 << card_number); - dw_sdio_reg_write(sdio, DWSDIO_REG_CLKENA, reg); -} - -/** - * @fn void dw_sdio_fifo_write_poll(DW_SDIO_CTRL_PTR sdio, uint32_t *buf, uint32_t size) - */ -Inline void dw_sdio_fifo_write_poll(DW_SDIO_CTRL_PTR sdio, uint32_t *buf, uint32_t size) -{ - uint32_t len; - uint32_t i; - uint32_t fifo_depth = sdio->fifo_depth; - - while (size) { - do { - len = dw_sdio_reg_read(sdio, DWSDIO_REG_STATUS); - } while (len & DWSDIO_STATUS_FIFO_FULL); - - len = fifo_depth - ((len & DWSDIO_STATUS_MASK_FIFO) >> DWSDIO_STATUS_BIT_FIFO); - len = min(size, len); - - for (i = 0; i < len; i++) { - dw_sdio_reg_write(sdio, DWSDIO_REG_DATA, *buf++); - } - size = size > len ? (size - len) : 0; - } -} - -/** - * @fn void dw_sdio_power_on(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) - */ -Inline void dw_sdio_power_on(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) -{ - dw_sdio_reg_write(sdio, DWSDIO_REG_PWREN, (1 << card_number)); -} - -/** - * @fn void dw_sdio_power_off(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) - */ -Inline void dw_sdio_power_off(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) -{ - uint32_t reg = dw_sdio_reg_read(sdio, DWSDIO_REG_PWREN); - - reg &= ~(1 << card_number); - dw_sdio_reg_write(sdio, DWSDIO_REG_PWREN, reg); -} - -/** - * @fn void dw_sdio_reset(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) - */ -Inline void dw_sdio_reset(DW_SDIO_CTRL_PTR sdio, uint32_t card_number) -{ - uint32_t reg; - - reg = dw_sdio_reg_read(sdio, DWSDIO_REG_RST_N); - reg &= ~(1 << card_number); - dw_sdio_reg_write(sdio, DWSDIO_REG_RST_N, reg); - reg |= (1 << card_number); - dw_sdio_reg_write(sdio, DWSDIO_REG_RST_N, reg); -} - -/** - * @fn void dw_sdio_bus_type_set(DW_SDIO_CTRL_PTR sdio, uint32_t card_number, uint32_t width) - */ -Inline void dw_sdio_bus_type_set(DW_SDIO_CTRL_PTR sdio, uint32_t card_number, uint32_t width) -{ - uint32_t reg; - - reg = dw_sdio_reg_read(sdio, DWSDIO_REG_CTYPE); - - reg &= ~((1 << card_number) | (1 << (card_number + 16))); - - switch (width) { - case 1: break; - case 4: reg |= (1 << card_number); break; - case 8: reg |= (1 << (card_number + 16)); break; - default: break; - } - - dw_sdio_reg_write(sdio, DWSDIO_REG_CTYPE, reg); -} - -/** - * @fn void dw_sdio_ref_clk_set(DW_SDIO_CTRL_PTR sdio, uint32_t ref_clk) - */ -Inline void dw_sdio_ref_clk_set(DW_SDIO_CTRL_PTR sdio, uint32_t ref_clk) -{ - /* 0: 25 Mhz, 1: 50 Mhz, 2: 100 Mhz */ - uint32_t reg; - - if (ref_clk == 50000000) { - ref_clk = 1; - } else if (ref_clk == 100000000) { - ref_clk = 2; - } else { - ref_clk = 0; - } - - reg = dw_sdio_reg_read(sdio, DWSDIO_REG_UHS_REG_EXT); - reg &= ~(DWSDIO_UHS_REG_EXT_MASK_REFCLK); - reg |= (ref_clk << DWSDIO_UHS_REG_EXT_BIT_REFCLK); - dw_sdio_reg_write(sdio, DWSDIO_REG_UHS_REG_EXT, reg); -} - -static int32_t dw_sdio_bus_freq_set(DW_SDIO_CTRL_PTR sdio, uint32_t card_number, uint32_t freq) -{ - uint32_t clk; - uint32_t div; - uint32_t status; - int32_t timeout = 10000; - - clk = sdio->ref_clk; - - if (freq == clk) { - div = 0; - } else { - div = DIV_ROUND_UP(clk, 2 * freq); - } - - dw_sdio_clk_disable(sdio, card_number); - - dw_sdio_reg_write(sdio, DWSDIO_REG_CLKSRC, 0); - dw_sdio_reg_write(sdio, DWSDIO_REG_CLKDIV, div); - - dw_sdio_reg_write(sdio, DWSDIO_REG_CMD, DWSDIO_CMD_PRV_DAT_WAIT | - DWSDIO_CMD_UPD_CLK | DWSDIO_CMD_START | DWSDIO_CMD_USE_HOLD_REG); - - do { - status = dw_sdio_reg_read(sdio, DWSDIO_REG_CMD); - if (timeout-- < 0) { - DBG("%s: Timeout!\n", __func__); - return E_TMOUT; - } - } while (status & DWSDIO_CMD_START); - - dw_sdio_clk_enable(sdio, card_number); - - dw_sdio_reg_write(sdio, DWSDIO_REG_CMD, DWSDIO_CMD_PRV_DAT_WAIT | - DWSDIO_CMD_UPD_CLK | DWSDIO_CMD_START | DWSDIO_CMD_USE_HOLD_REG); - - timeout = 10000; - do { - status = dw_sdio_reg_read(sdio, DWSDIO_REG_CMD); - if (timeout-- < 0) { - DBG("%s: Timeout!\n", __func__); - return E_TMOUT; - } - } while (status & DWSDIO_CMD_START); - - return E_OK; -} - -static int32_t dw_sdio_reset_wait(DW_SDIO_CTRL_PTR sdio, uint32_t reset_val) -{ - uint32_t try = 1000; - uint32_t ctrl; - - dw_sdio_reg_write(sdio, DWSDIO_REG_CTRL, reset_val); - - while (try--) { - ctrl = dw_sdio_reg_read(sdio, DWSDIO_REG_CTRL); - if (!(ctrl & DWSDIO_CTRL_RESET_ALL)) { - return E_SYS; - } - } - - return E_OK; -} - -static int32_t dw_sdio_cmd_set(DW_SDIO_CTRL_PTR sdio, SDIO_CMD_PTR cmd, SDIO_DATA_PTR data) -{ - uint32_t reg = 0; - - dw_sdio_reg_write(sdio, DWSDIO_REG_CMDARG, cmd->arg); - - if (data) { - reg |= DWSDIO_CMD_DATA_EXP; - - if (data->flags & SDIO_DATA_WRITE) { - reg |= DWSDIO_CMD_RW; - } - } - - if ((cmd->resp_type & SDIO_RSP_136) && (cmd->resp_type & SDIO_RSP_BUSY)) { - return -1; - } - - /* to fix */ - if (cmd->cmdidx == 12) { - reg |= DWSDIO_CMD_ABORT_STOP; - } else { - reg |= DWSDIO_CMD_PRV_DAT_WAIT; - } - - if (cmd->resp_type & SDIO_RSP_PRESENT) { - reg |= DWSDIO_CMD_RESP_EXP; - if (cmd->resp_type & SDIO_RSP_136) { - reg |= DWSDIO_CMD_RESP_LENGTH; - } - } - - if (cmd->resp_type & SDIO_RSP_CRC) { - reg |= DWSDIO_CMD_CHECK_CRC; - } - - reg |= (cmd->cmdidx | (cmd->card << DWSDIO_CMD_BIT_CARD_NO) | DWSDIO_CMD_START - | DWSDIO_CMD_USE_HOLD_REG); - - DBG("Sending CMD%d to card %d \r\n", cmd->cmdidx, cmd->card); - - dw_sdio_reg_write(sdio, DWSDIO_REG_CMD, reg); - - return 0; -} - -static int32_t dw_sdio_data_transfer_poll(DW_SDIO_CTRL_PTR sdio, SDIO_DATA_PTR data) -{ - uint32_t size; - uint32_t status; - uint32_t timeout = 1000; - uint32_t start = GET_CUR_MS(); - - size = data->blksz * data->blkcnt / 4; - - for (;;) { - status = dw_sdio_reg_read(sdio, DWSDIO_REG_RINTSTS); - - if (status & (DWSDIO_INT_DATA_ERR | DWSDIO_INT_DATA_TMO)) { - DBG("%s:, data transfer error!\r\n", __func__); - return E_SYS; - } - - if (status & DWSDIO_INT_DTO) { - return E_OK; - } - - if (data->flags == SDIO_DATA_READ && (status & DWSDIO_INT_RXDR) && size) { - dw_sdio_fifo_read_poll(sdio, (uint32_t *)data->in, size); - size = 0; - dw_sdio_reg_write(sdio, DWSDIO_REG_RINTSTS, DWSDIO_INT_RXDR); - } else if (data->flags == SDIO_DATA_WRITE && (status & DWSDIO_INT_TXDR) && size) { - dw_sdio_fifo_write_poll(sdio, (uint32_t *)data->out, size); - size = 0; - dw_sdio_reg_write(sdio, DWSDIO_REG_RINTSTS, DWSDIO_INT_TXDR); - } - - if ((GET_CUR_MS() - start) > timeout) { - DBG("%s: timeout on data transfer\r\n", __func__); - return E_TMOUT; - } - } -} - -void dw_sdio_isr(DEV_SDIO *sdio_obj, void *ptr) -{ - uint32_t int_status; - - DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); - DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - - int_status = dw_sdio_reg_read(sdio, DWSDIO_REG_MINTSTS); - - if (int_status & DWSDIO_INT_CAD) { - DBG("SDIO card detected\r\n"); - } - - if (int_status & DWSDIO_INT_RE) { - DBG("SDIO response error\r\n"); - } - - if (int_status & DWSDIO_INT_CD) { - DBG("SDIO cmd done\r\n"); - } - - if (int_status & DWSDIO_INT_TXDR) { - DBG("SDIO tx data request\r\n"); - } - - if (int_status & DWSDIO_INT_RXDR) { - DBG("SDIO rx data request\r\n"); - } - - /* clear interrupt */ - dw_sdio_reg_write(sdio, DWSDIO_REG_RINTSTS, int_status); - - /* \todo dma based interrupt */ -} - -int32_t dw_sdio_cmd_poll(DEV_SDIO *sdio_obj, SDIO_CMD_PTR cmd, SDIO_DATA_PTR data) -{ - DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); - DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - - uint32_t start = GET_CUR_MS(); - uint32_t timeout = 500; - uint32_t retry = 100000; - uint32_t mask; - uint32_t i; - - while (dw_sdio_reg_read(sdio, DWSDIO_REG_STATUS) & DWSDIO_STATUS_DATA_BUSY) { - if ((GET_CUR_MS() - start) > timeout) { - DBG("%s: timeout on data busy\r\n", __func__); - return E_TMOUT; - } - } - - dw_sdio_reg_write(sdio, DWSDIO_REG_RINTSTS, DWSDIO_INT_ALL); - - if (data) { - dw_sdio_enable_card_threshold(sdio, 1); - dw_sdio_block_size_set(sdio, data->blksz * data->blkcnt, data->blksz); - dw_sdio_reset_wait(sdio, DWSDIO_CTRL_RESET_FIFO); - } - - if (dw_sdio_cmd_set(sdio, cmd, data) < 0) { - return E_SYS; - } - - for (i = 0; i < retry; i++) { - mask = dw_sdio_reg_read(sdio, DWSDIO_REG_RINTSTS); - if (mask & DWSDIO_INT_CD) { - if (!data) { - dw_sdio_reg_write(sdio, DWSDIO_REG_RINTSTS, mask); - } - break; - } - } - - if (i == retry) { - DBG("%s: Timeout.\n", __func__); - return E_TMOUT; - } - - if (mask & DWSDIO_INT_RTO) { - /* - * Timeout here is not necessarily fatal. (e)MMC cards - * will splat here when they receive CMD55 as they do - * not support this command and that is exactly the way - * to tell them apart from SD cards. Thus, this output - * below shall be debug(). eMMC cards also do not favor - * CMD8, please keep that in mind. - */ - DBG("%s: Response Timeout:%x.\r\n", __func__, mask); - return E_TMOUT; - } else if (mask & DWSDIO_INT_RE) { - DBG("%s: Response Error:%x.\r\n", __func__, mask); - return E_SYS; - } - - if (cmd->resp_type & SDIO_RSP_PRESENT) { - if (cmd->resp_type & SDIO_RSP_136) { - cmd->resp[0] = dw_sdio_reg_read(sdio, DWSDIO_REG_RESP3); - cmd->resp[1] = dw_sdio_reg_read(sdio, DWSDIO_REG_RESP2); - cmd->resp[2] = dw_sdio_reg_read(sdio, DWSDIO_REG_RESP1); - cmd->resp[3] = dw_sdio_reg_read(sdio, DWSDIO_REG_RESP0); - } else { - cmd->resp[0] = dw_sdio_reg_read(sdio, DWSDIO_REG_RESP0); - } - } - - if (data) { - return dw_sdio_data_transfer_poll(sdio, data); - } - - return E_OK; -} - -int32_t dw_sdio_open(DEV_SDIO *sdio_obj, uint32_t card_number) -{ - uint32_t fifo_depth; - DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); - DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - - if (sdio_info_ptr->opn_cnt > 0) { - dw_sdio_power_on(sdio, card_number); - dw_sdio_reset(sdio, card_number); - dw_sdio_bus_freq_set(sdio, card_number, DWSDIO_ENUMERATION_FREQ); - - sdio_info_ptr->opn_cnt++; - return E_OPNED; - } - - sdio_info_ptr->opn_cnt++; - - dw_sdio_reset_wait(sdio, DWSDIO_CTRL_RESET_ALL); - dw_sdio_ref_clk_set(sdio, sdio->ref_clk); - - dw_sdio_power_on(sdio, card_number); - dw_sdio_reset(sdio, card_number); - - dw_sdio_bus_type_set(sdio, card_number, 1); - dw_sdio_bus_freq_set(sdio, card_number, DWSDIO_ENUMERATION_FREQ); - - if (sdio->fifo_depth == 0) { - fifo_depth = dw_sdio_reg_read(sdio, DWSDIO_REG_FIFOTH); - fifo_depth = ((fifo_depth & DWSDIO_FIFOTH_MASK_RX_WMARK) >> - DWSDIO_FIFOTH_BIT_RX_WMARK) + 1; - sdio->fifo_depth = fifo_depth; - } - - fifo_depth = DWSDIO_FIFOTH_M_SIZE(0x2) | DWSDIO_FIFOTH_RX_WMASK(sdio->fifo_depth / 2 - 1) | - DWSDIO_FIFOTH_TX_WMASK(sdio->fifo_depth / 2); - dw_sdio_reg_write(sdio, DWSDIO_REG_FIFOTH, fifo_depth); - - return E_OK; -} - -int32_t dw_sdio_close(DEV_SDIO *sdio_obj, uint32_t card_number) -{ - int32_t ret = E_OK; - DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); - DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - - sdio_info_ptr->opn_cnt--; - - dw_sdio_power_off(sdio, card_number); - if (sdio_info_ptr->opn_cnt == 0) { - dw_sdio_reset_wait(sdio, DWSDIO_CTRL_RESET_ALL); - } else { - ret = E_OPNED; - } - - return ret; -} - -int32_t dw_sdio_cd(DEV_SDIO *sdio_obj, uint32_t card_number) -{ - uint32_t val; - - DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); - DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - - /* the card detect depends on the specific PCB lay out. - * Some use 1 (CD pin to VDD) to indicate card detect. - * Some use 0 (CD pin to GNU) to indicate card detect. - */ -#ifdef DWSDIO_CARD_DETECT_HIGH_LEVEL - val = dw_sdio_reg_read(sdio, DWSDIO_REG_CDETECT); -#else - val = ~dw_sdio_reg_read(sdio, DWSDIO_REG_CDETECT); -#endif - - if ((val & (1 << card_number)) == (1 << card_number)) { - return 1; /* the specific card detected */ - } - - return 0; -} - -int32_t dw_sdio_wp(DEV_SDIO *sdio_obj, uint32_t card_number) -{ - uint32_t val; - - DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); - DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - - val = dw_sdio_reg_read(sdio, DWSDIO_REG_WRTPRT); - - if ((val & (1 << card_number)) == (1 << card_number)) { - return 1; /* the specific card is write-protect */ - } - - return 0; -} - -int32_t dw_sdio_control(DEV_SDIO *sdio_obj, SDIO_CTRL_CMD_PTR ctrl_cmd, void *param) -{ - int32_t ret = E_OK; - uint32_t cmd, card; - - DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); - DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - - cmd = ctrl_cmd->cmd; - card = ctrl_cmd->card; - - switch (cmd) { - case SDIO_CMD_SET_BUS_WIDTH: - dw_sdio_bus_type_set(sdio, card, (uint32_t)param); - break; - case SDIO_CMD_SET_BUS_FREQ: - dw_sdio_bus_freq_set(sdio, card, (uint32_t)param); - break; - /* \todo add more cmds */ - default: - ret = E_PAR; - } - return ret; -} \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/spi/dw_spi.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/spi/dw_spi.c deleted file mode 100644 index 4c39ca2c..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/spi/dw_spi.c +++ /dev/null @@ -1,1477 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include - -#include "embARC_toolchain.h" -#include "embARC_error.h" - -#include "arc/arc_exception.h" - -#include "device/designware/dw_spi_hal.h" -#include "device/designware/dw_spi.h" - -/** - * DesignWare SPI driver macros used in spi driver - */ -/** check expressions used in DesignWare SPI driver implementation */ -#define DW_SPI_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -/** convert DesignWare frequence to divisor */ -#define DW_SPI_FREQ2DV(perifreq, spifreq) ((perifreq) / (spifreq)) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of spi info object */ -#define VALID_CHK_SPI_INFO_OBJECT(spiinfo_obj_ptr) { \ - DW_SPI_CHECK_EXP((spiinfo_obj_ptr) != NULL, E_OBJ); \ - DW_SPI_CHECK_EXP(((spiinfo_obj_ptr)->spi_ctrl) != NULL, E_OBJ); \ -} -#endif - -/** - * DesignWare SPI interrupt callback routines select macros definitions - */ -#define DW_SPI_RDY_SND (1U) /*!< ready to send callback */ -#define DW_SPI_RDY_RCV (2U) /*!< ready to receive callback */ -#define DW_SPI_RDY_XFER (3U) /*!< ready to transfer callback */ - -/** - * @defgroup DEVICE_DW_SPI_STATIC DesignWare SPI Driver Static Functions - * @ingroup DEVICE_DW_SPI - * @brief Static or inline functions, variables for DesignWare SPI handle SPI operations, - * only used in this file. - * @{ - */ - -/** - * @fn void dw_spi_disable(DW_SPI_REG *spi_reg_ptr) - * @brief Disable designware spi device - */ -Inline void dw_spi_disable(DW_SPI_REG *spi_reg_ptr) -{ -/** disable spi operations, then program spi control regs is possible */ - spi_reg_ptr->SSIENR = DW_SPI_SSI_DISABLE; -} - -/** - * @fn void dw_spi_enable(DW_SPI_REG *spi_reg_ptr) - * @brief Enable designware spi device - */ -Inline void dw_spi_enable(DW_SPI_REG *spi_reg_ptr) -{ - spi_reg_ptr->SSIENR = DW_SPI_SSI_ENABLE; -} - -/** - * @fn void dw_spi_clear_interrupt_all(DW_SPI_REG *spi_reg_ptr) - * @brief Clear all designware spi interrupt - */ -Inline void dw_spi_clear_interrupt_all(DW_SPI_REG *spi_reg_ptr) -{ - (void)spi_reg_ptr->ICR; -} - -/** - * @fn int32_t dw_spi_busy(DW_SPI_REG *spi_reg_ptr) - * @brief Test whether spi is busy, busy return 1, else 0 - */ -Inline int32_t dw_spi_busy(DW_SPI_REG *spi_reg_ptr) -{ - return ((spi_reg_ptr->SR & DW_SPI_SR_BUSY) != 0); -} - -/** - * @fn int32_t dw_spi_putready(DW_SPI_REG *spi_reg_ptr) - * @brief Test whether spi is ready to send, 1 ready, 0 not ready - */ -Inline int32_t dw_spi_putready(DW_SPI_REG *spi_reg_ptr) -{ - return ((spi_reg_ptr->SR & DW_SPI_SR_TFNF) != 0); -} - -/** - * @fn int32_t dw_spi_getready(DW_SPI_REG *spi_reg_ptr) - * @brief Test whether spi is read to receive, 1 ready, 0 not ready - */ -Inline int32_t dw_spi_getready(DW_SPI_REG *spi_reg_ptr) -{ - return ((spi_reg_ptr->SR & DW_SPI_SR_RFNE) != 0); -} - -/** - * @fn void dw_spi_putdata(DW_SPI_REG *spi_reg_ptr, int32_t data) - * @brief Write data to spi send fifo - */ -Inline void dw_spi_putdata(DW_SPI_REG *spi_reg_ptr, int32_t data) -{ - spi_reg_ptr->DATAREG = (uint32_t)data; -} - -/** - * @fn int32_t dw_spi_getdata(DW_SPI_REG *spi_reg_ptr) - * @brief Read data from spi receive fifo, return data received - */ -Inline int32_t dw_spi_getdata(DW_SPI_REG *spi_reg_ptr) -{ - return (int32_t)spi_reg_ptr->DATAREG; -} - -/** - * @fn int32_t dw_spi_rxflr(DW_SPI_REG *spi_reg_ptr) - * @brief Get receive FIFO level - */ -Inline int32_t dw_spi_rxflr(DW_SPI_REG *spi_reg_ptr) -{ - return (int32_t)spi_reg_ptr->RXFLR; -} -/** - * @fn int32_t dw_spi_snd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data) - * @brief Send data through designware spi when available, - * mostly used in interrupt method, non-blocked function - * @param[in] spi_reg_ptr Spi register structure pointer - * @param[in] data data to sent - * @retval E_OK Send successfully without any issues - * @retval E_OBJ Device object is not ready to send data - */ -Inline int32_t dw_spi_snd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data) -{ - if (dw_spi_putready(spi_reg_ptr)) { - dw_spi_putdata(spi_reg_ptr, data); - return E_OK; - } - return E_OBJ; -} -/** - * @fn int32_t dw_spi_rcv_dat(DW_SPI_REG *spi_reg_ptr) - * @brief Receive one char through designware spi, - * mostly used in interrupt routine, non-blocked function - * @param[in] spi_reg_ptr Spi register structure pointer - * @return Data received - */ -Inline int32_t dw_spi_rcv_dat(DW_SPI_REG *spi_reg_ptr) -{ - return dw_spi_getdata(spi_reg_ptr); -} -/** - * @fn void dw_spi_psnd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data) - * @brief Send char through designware spi spi in poll method, blocked function - * @param[in] spi_reg_ptr Spi register structure pointer - * @param[in] data Data to send - */ -Inline void dw_spi_psnd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data) -{ - /** wait until spi is ready to send */ - while (!dw_spi_putready(spi_reg_ptr)) { - ; /* blocked */ - } - /** send char */ - dw_spi_putdata(spi_reg_ptr, data); -} -/** - * @fn int32_t dw_spi_prcv_dat(DW_SPI_REG *spi_reg_ptr) - * @brief Receive one char through designware spi in poll method, blocked function - * @param[in] spi_reg_ptr Spi register structure pointer - * @return Data received - */ -Inline int32_t dw_spi_prcv_dat(DW_SPI_REG *spi_reg_ptr) -{ - /** wait until spi is ready to receive */ - while (!dw_spi_getready(spi_reg_ptr)) { - ; /* blocked */ - } - /** receive data */ - return dw_spi_getdata(spi_reg_ptr); -} - -/** - * @fn void dw_spi_reset_fifo(DW_SPI_REG *spi_reg_ptr) - * @brief Reset designware FIFO by disable spi device, then enable device - */ -Inline void dw_spi_reset_fifo(DW_SPI_REG *spi_reg_ptr) -{ - dw_spi_disable(spi_reg_ptr); - dw_spi_enable(spi_reg_ptr); -} - -/** - * @fn void dw_spi_unmask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask) - * @brief Enable designware spi bit interrupt with mask - */ -Inline void dw_spi_unmask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask) -{ - spi_reg_ptr->IMR |= mask; -} - -/** - * @fn void dw_spi_mask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask) - * @brief Disable designware spi bit interrupt with mask - */ -Inline void dw_spi_mask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask) -{ - spi_reg_ptr->IMR &= ~mask; -} - -/** - * @fn void dw_spi_set_freq(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t freq) - * @brief Set designware spi device frequency - */ -Inline void dw_spi_set_freq(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t freq) -{ - uint32_t sck_divisor; - DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs; - - dw_spi_disable(spi_reg_ptr); - - sck_divisor = DW_SPI_FREQ2DV(spi_ctrl_ptr->dw_apb_bus_freq, freq); - spi_reg_ptr->BAUDR = sck_divisor; - dw_spi_enable(spi_reg_ptr); -} - -/** Set designware spi device data frame size */ -static int32_t dw_spi_set_dfs(DW_SPI_REG *spi_reg_ptr, uint32_t dfs) -{ - uint32_t ctrl0_reg; - - if ((dfs <= 3) || (dfs > 16)) { - return -1; - } - - dw_spi_disable(spi_reg_ptr); - ctrl0_reg = spi_reg_ptr->CTRLR0; - ctrl0_reg &= ~(DW_SPI_CTRLR0_DFS_MASK); - spi_reg_ptr->CTRLR0 = ctrl0_reg | (dfs - 1); - dw_spi_enable(spi_reg_ptr); - - return 0; -} - -/** Designware spi enable quad mode*/ -static void dw_spi_quad_enable(DW_SPI_REG *spi_reg_ptr, uint32_t len) -{ - dw_spi_disable(spi_reg_ptr); - - spi_reg_ptr->CTRLR0 |= ((0x2 << 21) | (0x2 << 8));// Quad Frame Format. - spi_reg_ptr->SPI_CTRLR0 = (0x8 << 11) | (0x2 << 8) | (0x6 << 2) | (0x0 << 0); - // 8 wait cycles | 8bit instruction | 24bit address | instruction and address sent in standard mode. - spi_reg_ptr->CTRLR1 = len; - - dw_spi_enable(spi_reg_ptr); -} - -/** Designware spi disable quad mode*/ -static void dw_spi_quad_disable(DW_SPI_REG *spi_reg_ptr) -{ - dw_spi_disable(spi_reg_ptr); - - spi_reg_ptr->CTRLR0 &= ~((0x3 << 21) | (0x3 << 8)); - spi_reg_ptr->CTRLR1 = 0; - spi_reg_ptr->CTRLR0 = 0; - - dw_spi_enable(spi_reg_ptr); -} - -/** Choose proper designware spi clock mode setting value */ -Inline uint32_t dw_spi_select_clockmode(uint32_t clk_mode) -{ - return (clk_mode << DW_SPI_CTRLR0_SC_OFS); -} - -/** Set designware spi clock mode */ -Inline int32_t dw_spi_set_clockmode(DW_SPI_REG *spi_reg_ptr, uint32_t clk_mode) -{ - if (clk_mode > SPI_CPOL_1_CPHA_1) { - return -1; - } - dw_spi_disable(spi_reg_ptr); - spi_reg_ptr->CTRLR0 &= ~(DW_SPI_CTRLR0_SC_MASK); - spi_reg_ptr->CTRLR0 |= dw_spi_select_clockmode(clk_mode); - dw_spi_enable(spi_reg_ptr); - return 0; -} - -/** Select a spi slave with slv_line */ -Inline int32_t dw_spi_select_slave(DW_SPI_REG *spi_reg_ptr, uint32_t slv_line) -{ - /* check if spi busy */ - if (dw_spi_busy(spi_reg_ptr)) { - return -1; - } - - spi_reg_ptr->SER = 1 << slv_line; - return 0; -} - -/** Deselect a spi device */ -Inline int32_t dw_spi_deselect_slave(DW_SPI_REG *spi_reg_ptr, uint32_t slv_line) -{ - /* check if spi busy */ - if (dw_spi_busy(spi_reg_ptr)) { - return -1; - } - - spi_reg_ptr->SER = 0; - return 0; -} - -Inline void dw_spi_flush_tx(DW_SPI_REG *spi_reg_ptr) -{ - dw_spi_reset_fifo(spi_reg_ptr); -} - -Inline void dw_spi_flush_rx(DW_SPI_REG *spi_reg_ptr) -{ - dw_spi_reset_fifo(spi_reg_ptr); -} - -/** Get TX FIFO Length. - * calculate spi fifo length using fifo threshold method - * If you attempt to set bits [7:0] of this register to - * a value greater than or equal to the depth of the FIFO, - * this field is not written and retains its current value. - */ -static uint32_t dw_spi_get_txfifo_len(DW_SPI_REG *spi_reg_ptr) -{ - uint32_t fifo_thr_lev_tmp, left, right, i; - - fifo_thr_lev_tmp = spi_reg_ptr->TXFTLR; - - if (fifo_thr_lev_tmp != 0) { - left = fifo_thr_lev_tmp; - } else { - left = DW_SPI_MIN_FIFO_LENGTH; - } - right = DW_SPI_MAX_FIFO_LENGTH + 1; - - for (i = left; i <= right; i++) { - spi_reg_ptr->TXFTLR = i; - if (spi_reg_ptr->TXFTLR != i) { - break; - } - } - spi_reg_ptr->TXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */ - - return (i); -} - -/** Get RX FIFO Length */ -static uint32_t dw_spi_get_rxfifo_len(DW_SPI_REG *spi_reg_ptr) -{ - uint32_t fifo_thr_lev_tmp, left, right, i; - - fifo_thr_lev_tmp = spi_reg_ptr->RXFTLR; - - if (fifo_thr_lev_tmp != 0) { - left = fifo_thr_lev_tmp; - } else { - left = DW_SPI_MIN_FIFO_LENGTH; - } - right = DW_SPI_MAX_FIFO_LENGTH + 1; - - for (i = left; i <= right; i++) { - spi_reg_ptr->RXFTLR = i; - if (spi_reg_ptr->RXFTLR != i) { - break; - } - } - spi_reg_ptr->RXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */ - - return (i); -} - -/** Init Designware SPI Hardware */ -static void dw_spi_hw_init(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t clk_mode, uint32_t dfs) -{ - uint32_t ctrl0_reg = 0; - DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs; - - dw_spi_disable(spi_reg_ptr); - - /* Clear interrupts */ - ctrl0_reg = spi_reg_ptr->ICR; - /* Mask all interrupts */ - spi_reg_ptr->IMR = 0; - - ctrl0_reg = DW_SPI_CTRLR0_FRF_MOTOROLA | DW_SPI_TMOD_TRANSMIT_RECEIVE \ - | dw_spi_select_clockmode(clk_mode) | (dfs - 1) | DW_SPI_CTRLR0_SLV_OE_ENABLE; - spi_reg_ptr->CTRLR0 = ctrl0_reg; - spi_reg_ptr->CTRLR1 = 0; - - /* deselect slaves */ - spi_reg_ptr->SER = 0; - - /* Set threshold values for both tx and rx */ - spi_reg_ptr->TXFTLR = 0; - spi_reg_ptr->RXFTLR = 0; - - spi_reg_ptr->RX_SAMPLE_DLY = spi_ctrl_ptr->rx_sampledly; - - dw_spi_enable(spi_reg_ptr); -} - -/** enable designware spi */ -static void dw_spi_enable_device(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - if ((spi_info_ptr->status & DEV_ENABLED) == 0) { - dw_spi_enable(spi_reg_ptr); - spi_info_ptr->status |= DEV_ENABLED; - } -} - -/** disable designware spi */ -static void dw_spi_disable_device(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - dw_spi_disable(spi_reg_ptr); - spi_info_ptr->status &= ~DEV_ENABLED; -} - -/** - * @brief Disable designware spi send or receive interrupt - * @param[in] spi_info_ptr Informations about spi open state, working state, - * frequency, spi registers, working method, interrupt number - * @param[in] cbrtn Control code of callback routine - */ -static int32_t dw_spi_dis_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - int32_t ercd = E_OK; - - if ((spi_info_ptr->status & DW_SPI_IN_XFER) != 0) { /* only in transfer need do check */ - switch (cbrtn) { - case DW_SPI_RDY_SND: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX); - spi_info_ptr->status &= ~(DW_SPI_IN_TX); - break; - case DW_SPI_RDY_RCV: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX); - spi_info_ptr->status &= ~(DW_SPI_IN_RX); - break; - case DW_SPI_RDY_XFER: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX); - spi_info_ptr->status &= ~(DW_SPI_IN_XFER); - break; - default: - break; - } - } - - dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER); - - if (spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) { - if (spi_ctrl_ptr->intno != DW_SPI_INVALID_INTNO) { - int_disable(spi_ctrl_ptr->intno); - } - spi_ctrl_ptr->int_status &= ~DW_SPI_GINT_ENABLE; - } - -error_exit: - return ercd; -} - -/** - * @brief Enable DesignWare SPI send or receive interrupt - * @param[in] spi_info_ptr Informations about spi open state, working state, - * frequency, spi registers, working method, interrupt number - * @param[in] cbrtn Control code of callback routine - */ -static int32_t dw_spi_ena_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == 0, E_CTX); - switch (cbrtn) { - case DW_SPI_RDY_SND: - spi_info_ptr->status |= DW_SPI_IN_TX; - break; - case DW_SPI_RDY_RCV: - spi_info_ptr->status |= DW_SPI_IN_RX; - break; - case DW_SPI_RDY_XFER: - spi_info_ptr->status |= DW_SPI_IN_XFER; - break; - default: - break; - } - dw_spi_unmask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER); - - if ((spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) == 0) { - spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE; - if (spi_ctrl_ptr->intno != DW_SPI_INVALID_INTNO) { - int_enable(spi_ctrl_ptr->intno); - } - } - -error_exit: - return ercd; -} - -/** - * @brief Enable designware spi interrupt - * @param spi_info_ptr Spi information structure pointer - */ -static void dw_spi_enable_interrupt(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - - if (spi_ctrl_ptr->intno != DW_SPI_INVALID_INTNO) { - int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler); - spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE; - /** enable spi interrupt */ - int_enable(spi_ctrl_ptr->intno); - } else { - spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE; - } -} -/** - * @brief Disable designware spi interrupt - * @param spi_info_ptr Dpi information structure pointer - */ -static void dw_spi_disable_interrupt(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - - /** disable spi send&receive interrupt after disable spi interrupt */ - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - /* disable spi interrupt */ - dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER); - spi_info_ptr->status &= ~DW_SPI_IN_XFER; - if (spi_ctrl_ptr->intno != DW_SPI_INVALID_INTNO) { - int_disable(spi_ctrl_ptr->intno); - } - spi_ctrl_ptr->int_status &= ~(DW_SPI_GINT_ENABLE); -} - -static void dw_spi_reset_device(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - dw_spi_disable_device(spi_info_ptr); - dw_spi_disable_interrupt(spi_info_ptr); - dw_spi_clear_interrupt_all(spi_reg_ptr); - dw_spi_enable_device(spi_info_ptr); -} - -/** abort current interrupt transmit transfer */ -static int32_t dw_spi_abort_tx(DEV_SPI *spi_obj) -{ - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX); - - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - spi_info_ptr->status |= DEV_IN_TX_ABRT; - if (spi_info_ptr->spi_cbs.tx_cb != NULL) { - spi_info_ptr->spi_cbs.tx_cb(spi_obj); - } - spi_info_ptr->status &= ~(DEV_IN_TX_ABRT); - -error_exit: - return ercd; -} - -/** abort current interrupt receive transfer */ -static int32_t dw_spi_abort_rx(DEV_SPI *spi_obj) -{ - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX); - - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - spi_info_ptr->status |= DEV_IN_RX_ABRT; - if (spi_info_ptr->spi_cbs.rx_cb != NULL) { - spi_info_ptr->spi_cbs.rx_cb(spi_obj); - } - spi_info_ptr->status &= ~(DEV_IN_RX_ABRT); - -error_exit: - return ercd; -} - -/** abort current interrupt transfer */ -static int32_t dw_spi_abort_xfer(DEV_SPI *spi_obj) -{ - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX); - - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - spi_info_ptr->status |= DEV_IN_XFER_ABRT; - if (spi_info_ptr->spi_cbs.xfer_cb != NULL) { - spi_info_ptr->spi_cbs.xfer_cb(spi_obj); - } - spi_info_ptr->status &= ~(DEV_IN_XFER_ABRT); - -error_exit: - return ercd; -} - -/** Get available transmit fifo count */ -static int32_t dw_spi_get_txavail(DW_SPI_CTRL *spi_ctrl_ptr) -{ - int32_t tx_avail = 0; - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - -#if DW_SPI_CALC_FIFO_LEN_ENABLE - if (spi_ctrl_ptr->tx_fifo_len <= 1) { - if (dw_spi_putready(spi_reg_ptr) == 1) { - tx_avail = 1; - } else { - tx_avail = 0; - } - } else -#endif - { - tx_avail = spi_ctrl_ptr->tx_fifo_len - spi_reg_ptr->TXFLR; - } - return tx_avail; -} - -/** Get available receive fifo count */ -static int32_t dw_spi_get_rxavail(DW_SPI_CTRL *spi_ctrl_ptr) -{ - int32_t rx_avail = 0; - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - -#if DW_SPI_CALC_FIFO_LEN_ENABLE - if (spi_ctrl_ptr->rx_fifo_len <= 1) { - if (dw_spi_getready(spi_reg_ptr) == 1) { - rx_avail = 1; - } else { - rx_avail = 0; - } - } else -#endif - { - rx_avail = spi_reg_ptr->RXFLR; - } - return rx_avail; -} - -static uint32_t dw_spi_tx_max(DW_SPI_CTRL *spi_ctrl_ptr) -{ - uint32_t tx_left, tx_room; - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - tx_left = (xfer->xfer_len - xfer->tx_idx) / xfer->nbytes; - tx_room = dw_spi_get_txavail(spi_ctrl_ptr); - - return (tx_left < tx_room) ? tx_left : tx_room; -} - -static uint32_t dw_spi_rx_max(DW_SPI_CTRL *spi_ctrl_ptr) -{ - uint32_t rx_left, rx_room; - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - rx_left = (xfer->xfer_len - xfer->rx_idx) / xfer->nbytes; - rx_room = dw_spi_get_rxavail(spi_ctrl_ptr); - - return (rx_left < rx_room) ? rx_left : rx_room; -} - -Inline int32_t dw_spi_rx_end(DW_SPI_CTRL *spi_ctrl_ptr) -{ - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - return (xfer->rx_idx >= xfer->xfer_len); -} - -Inline int32_t dw_spi_tx_end(DW_SPI_CTRL *spi_ctrl_ptr) -{ - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - return (xfer->tx_idx >= xfer->xfer_len); -} - -/** 1 for end, 0 for not end */ -Inline int32_t dw_spi_xfer_end(DW_SPI_CTRL *spi_ctrl_ptr) -{ - return (dw_spi_tx_end(spi_ctrl_ptr) && dw_spi_rx_end(spi_ctrl_ptr)); -} - -static int32_t dw_spi_writer(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - uint32_t tx_max = dw_spi_tx_max(spi_ctrl_ptr); - int32_t tx_w; - uint32_t tx_cnt = tx_max; - - if (dw_xfer->tx_xfer == NULL) { - return 0; - } - while (tx_max) { - if (dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tot_len) { - dw_xfer->tx_xfer = dw_xfer->tx_xfer->next; - if (dw_xfer->tx_xfer == NULL) { - break; - } - } - if ((dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tx_ofs) \ - && (dw_xfer->tx_xfer->tx_idx < dw_xfer->tx_xfer->tx_totlen)) { - if (dw_xfer->nbytes == 1) { - tx_w = (int32_t)(*(int8_t *)(dw_xfer->tx_xfer->tx_buf)); - } else { - tx_w = (int32_t)(*(int16_t *)(dw_xfer->tx_xfer->tx_buf)); - } - dw_xfer->tx_xfer->tx_buf += dw_xfer->nbytes; - } else { - tx_w = spi_info_ptr->dummy; - } - dw_spi_putdata(spi_reg_ptr, tx_w); - dw_xfer->tx_xfer->tx_idx += dw_xfer->nbytes; - dw_xfer->tx_idx += dw_xfer->nbytes; - tx_max--; - } - return ((tx_cnt - tx_max) * dw_xfer->nbytes); -} - -static int32_t dw_spi_reader(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - uint32_t rx_max = dw_spi_rx_max(spi_ctrl_ptr); - int32_t rx_w; - uint32_t rx_cnt = rx_max; - - if (dw_xfer->rx_xfer == NULL) { - return 0; - } - while (rx_max) { - if (dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->tot_len) { - dw_xfer->rx_xfer = dw_xfer->rx_xfer->next; - if (dw_xfer->rx_xfer == NULL) { - break; - } - } - rx_w = dw_spi_getdata(spi_reg_ptr); - if ((dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->rx_ofs) \ - && (dw_xfer->rx_xfer->rx_idx < dw_xfer->rx_xfer->rx_totlen)) { - if (dw_xfer->nbytes == 1) { - *(int8_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w; - } else { - *(int16_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w; - } - dw_xfer->rx_xfer->rx_buf += dw_xfer->nbytes; - } - dw_xfer->rx_xfer->rx_idx += dw_xfer->nbytes; - dw_xfer->rx_idx += dw_xfer->nbytes; - rx_max--; - } - return ((rx_cnt - rx_max) * dw_xfer->nbytes); -} - -Inline uint32_t dw_spi_nbytes(uint32_t dfs) -{ - uint32_t nbytes = 1; - - if (dfs > 8) { - nbytes = 2; - } - return nbytes; -} - -static void dw_spi_init_transfer(DW_SPI_CTRL *spi_ctrl_ptr, DEV_SPI_TRANSFER *xfer, uint32_t dfs) -{ - DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer); - uint32_t tot_len = 0; - - dw_xfer->tx_xfer = xfer; - dw_xfer->rx_xfer = xfer; - dw_xfer->tx_idx = 0; - dw_xfer->rx_idx = 0; - dw_xfer->nbytes = dw_spi_nbytes(dfs); - - /** Calculate all transfer length */ - while (xfer) { - DEV_SPI_XFER_INIT(xfer); - tot_len += xfer->tot_len; - xfer = xfer->next; - } - dw_xfer->xfer_len = tot_len; -} - -/* Check buffer align status, 0 for aligned, -1 for not-aligned */ -static int32_t dw_spi_chk_xfer_aligned(DEV_SPI_TRANSFER *xfer, uint32_t dfs) -{ - uint32_t align_bytes = 1; - - if (xfer == NULL) { - return -1; - } - - if (dfs > 8) { - align_bytes = 2; - } else { - return 0; - } - - while (xfer) { - /* check tx buffer align status */ - if (xfer->tx_len != 0) { - if (xfer->tx_len % align_bytes) { - return -1; - } - if (xfer->tx_ofs % align_bytes) { - return -1; - } - if (!CHECK_ALIGN_BYTES(xfer->tx_buf, align_bytes)) { - return -1; - } - } - /* check tx buffer align status */ - if (xfer->rx_len != 0) { - if (xfer->rx_len % align_bytes) { - return -1; - } - if (xfer->rx_ofs % align_bytes) { - return -1; - } - if (!CHECK_ALIGN_BYTES(xfer->rx_buf, align_bytes)) { - return -1; - } - } - xfer = xfer->next; - } - return 0; -} - -static uint32_t dw_spi_poll_transfer(DEV_SPI_INFO *spi_info_ptr) -{ - uint32_t len = 0; - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - - spi_info_ptr->status |= DEV_IN_XFER; - while (!dw_spi_xfer_end(spi_ctrl_ptr)) { - len += dw_spi_writer(spi_info_ptr); - len += dw_spi_reader(spi_info_ptr); - } - spi_info_ptr->status &= ~DEV_IN_XFER; - - return len >> 1; -} - -static uint32_t dw_spi_quad_receive(DEV_SPI_INFO *spi_info_ptr, DEV_SPI_PAK_PTR pak) -{ - uint32_t len = 0; - uint8_t i = 0; - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - spi_info_ptr->status |= DEV_IN_XFER; - - dw_spi_quad_enable(spi_reg_ptr, pak->data_len - 1); - - dw_spi_psnd_dat(spi_reg_ptr, pak->cmd); - dw_spi_psnd_dat(spi_reg_ptr, pak->addr32); - - for (i = 0; i < pak->data_len; i++) { - dw_spi_psnd_dat(spi_reg_ptr, 0xFF); - while (dw_spi_busy(spi_reg_ptr)) { - ; - } - - if (dw_spi_getready(spi_reg_ptr)) { - while (dw_spi_rxflr(spi_reg_ptr)) { - pak->data_ptr[len++] = (uint8_t)dw_spi_getdata(spi_reg_ptr); - if (len == pak->data_len) { - break; - } - } - } - if (len == pak->data_len) { - break; - } - } - - dw_spi_quad_disable(spi_reg_ptr); - spi_info_ptr->status &= ~DEV_IN_XFER; - return len; -} - -/** @} */ - -/** - * @brief Open a designware spi device - * @param[in] spi_obj Spi object structure pointer - * @param[in] mode Spi working mode (master or slave) - * @param[in] param Parameter, for master, param is the freq, for slave, param is dfs - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_SPI_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ -int32_t dw_spi_open(DEV_SPI *spi_obj, uint32_t mode, uint32_t param) -{ - int32_t ercd = E_OK; - uint32_t param2check; - uint32_t clk_mode, dfs_val; - uint32_t support_modes; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP((mode == DEV_MASTER_MODE) || (mode == DEV_SLAVE_MODE), E_PAR); - if (mode == DEV_SLAVE_MODE) { /* clock mode should be in the enum structure */ - DW_SPI_CHECK_EXP((param >= SPI_CPOL_0_CPHA_0) && (param <= SPI_CPOL_1_CPHA_1), E_PAR); - } else { /* frequence should > 0 */ - DW_SPI_CHECK_EXP(param > 0, E_PAR); - } - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - - /* Check supported modes, master or slave */ - support_modes = spi_ctrl_ptr->support_modes; - DW_SPI_CHECK_EXP((((support_modes) & DW_SPI_MASTER_SUPPORTED) && (mode == DEV_MASTER_MODE)) || \ - (((support_modes) & DW_SPI_SLAVE_SUPPORTED) && (mode == DEV_SLAVE_MODE)), E_NOSPT); - - /** Check opened before use case */ - if (spi_info_ptr->opn_cnt > 0) { - if (mode != spi_info_ptr->mode) { - /* current working mode is different from passing mode */ - return E_SYS; - } - if (mode == DEV_MASTER_MODE) { /* param is freq when as master */ - param2check = spi_info_ptr->freq; - } else { /* param is clk_mode when as slave */ - param2check = spi_info_ptr->clk_mode; - } - spi_info_ptr->opn_cnt++; - if (param != param2check) { /* open with different speed mode */ - return E_OPNED; - } else { - return E_OK; - } - } - /* auto increase open count */ - spi_info_ptr->opn_cnt++; - - /* Do FIFO Length get before init */ -#if DW_SPI_CALC_FIFO_LEN_ENABLE - spi_ctrl_ptr->tx_fifo_len = dw_spi_get_txfifo_len(spi_ctrl_ptr->dw_spi_regs); - spi_ctrl_ptr->rx_fifo_len = dw_spi_get_rxfifo_len(spi_ctrl_ptr->dw_spi_regs); -#endif - /* hardware init */ - spi_info_ptr->mode = mode; - clk_mode = SPI_CLK_MODE_DEFAULT; - dfs_val = SPI_DFS_DEFAULT; - if (mode == DEV_SLAVE_MODE) { - clk_mode = param; - } - spi_info_ptr->dfs = dfs_val; - spi_info_ptr->clk_mode = clk_mode; - dw_spi_hw_init(spi_ctrl_ptr, clk_mode, dfs_val); - if (mode == DEV_MASTER_MODE) { /* Deselect all slaves, and set frequence */ - dw_spi_deselect_slave(spi_ctrl_ptr->dw_spi_regs, 0); - dw_spi_set_freq(spi_ctrl_ptr, param); - spi_info_ptr->freq = param; - } - - spi_info_ptr->status = DEV_ENABLED; - spi_info_ptr->extra = NULL; - spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED; - spi_info_ptr->dummy = 0xff; - - spi_ctrl_ptr->int_status = 0; - dw_spi_init_transfer(spi_ctrl_ptr, NULL, dfs_val); - - /** install spi interrupt into system */ - dw_spi_disable_interrupt(spi_info_ptr); - if (spi_ctrl_ptr->intno != DW_SPI_INVALID_INTNO) { - int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler); - } - memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER)); - memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS)); - -error_exit: - return ercd; -} - -/** - * @brief Close a DesignWare SPI device - * @param[in] spi_obj Spi object pointer - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_SPI_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ -int32_t dw_spi_close(DEV_SPI *spi_obj) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_OK); - /* END OF ERROR CHECK */ - - spi_info_ptr->opn_cnt--; - if (spi_info_ptr->opn_cnt == 0) { - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - - dw_spi_disable_interrupt(spi_info_ptr); - dw_spi_abort_tx(spi_obj); - dw_spi_abort_rx(spi_obj); - memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER)); - memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS)); - memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER)); - dw_spi_disable_device(spi_info_ptr); - spi_info_ptr->status = DEV_DISABLED; - spi_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** - * @brief Control spi by ctrl command - * @param[in] spi_obj Spi object pointer - * @param[in] ctrl_cmd @ref DEVICE_HAL_SPI_CTRLCMD "control command", to change or get some thing related to spi - * @param[in,out] param Parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ -int32_t dw_spi_control(DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED); - /* END OF ERROR CHECK */ - - uint32_t val32; /** to receive unsigned int value */ - DEV_BUFFER *devbuf; - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - DEV_SPI_TRANSFER *spi_xfer = &(spi_info_ptr->xfer); - - /* check whether current device is disabled */ - if ((spi_info_ptr->status & DEV_ENABLED) == 0) { - /** When device is disabled, - * only SPI_CMD_ENA_DEV, SPI_CMD_DIS_DEV, SPI_CMD_GET_STATUS, SPI_CMD_RESET - * are available, other commands will return E_SYS - */ - if ((ctrl_cmd != SPI_CMD_ENA_DEV) && \ - (ctrl_cmd != SPI_CMD_DIS_DEV) && \ - (ctrl_cmd != SPI_CMD_GET_STATUS) && \ - (ctrl_cmd != SPI_CMD_RESET)) { - return E_SYS; - } - } - - switch (ctrl_cmd) { - /* Commmon commands for both master and slave mode */ - case SPI_CMD_GET_STATUS: - DW_SPI_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = spi_info_ptr->status; - break; - case SPI_CMD_SET_CLK_MODE: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - DW_SPI_CHECK_EXP((val32 >= SPI_CPOL_0_CPHA_0) && (val32 <= SPI_CPOL_1_CPHA_1), E_PAR); - if (dw_spi_set_clockmode(spi_reg_ptr, val32) == 0) { - spi_info_ptr->clk_mode = val32; - } else { - ercd = E_SYS; - } - break; - case SPI_CMD_ENA_DEV: - dw_spi_enable_device(spi_info_ptr); - break; - case SPI_CMD_DIS_DEV: - dw_spi_disable_device(spi_info_ptr); - break; - case SPI_CMD_RESET: - dw_spi_reset_device(spi_info_ptr); - break; - case SPI_CMD_FLUSH_TX: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - dw_spi_flush_tx(spi_reg_ptr); - break; - case SPI_CMD_FLUSH_RX: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - dw_spi_flush_rx(spi_reg_ptr); - break; - case SPI_CMD_SET_DFS: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - DW_SPI_CHECK_EXP(val32 > 0, E_PAR); - if (dw_spi_set_dfs(spi_reg_ptr, val32) == 0) { - spi_info_ptr->dfs = val32; - } else { - ercd = E_SYS; - } - break; - case SPI_CMD_SET_DUMMY_DATA: - val32 = (uint32_t)param; - spi_info_ptr->dummy = val32; - break; - case SPI_CMD_GET_RXAVAIL: /* Notice in bytes unit */ - DW_SPI_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_spi_get_rxavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs); - break; - case SPI_CMD_GET_TXAVAIL: /* Notice in bytes unit */ - DW_SPI_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_spi_get_txavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs); - break; - case SPI_CMD_SET_TXCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.tx_cb = param; - break; - case SPI_CMD_SET_RXCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.rx_cb = param; - break; - case SPI_CMD_SET_XFERCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.xfer_cb = param; - break; - case SPI_CMD_SET_ERRCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.err_cb = param; - break; - case SPI_CMD_ABORT_TX: - ercd = dw_spi_abort_tx(spi_obj); - break; - case SPI_CMD_ABORT_RX: - ercd = dw_spi_abort_rx(spi_obj); - break; - case SPI_CMD_ABORT_XFER: - ercd = dw_spi_abort_xfer(spi_obj); - break; - case SPI_CMD_SET_TXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - } else { - ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_SND); - } - break; - case SPI_CMD_SET_RXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - } else { - ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - } - break; - case SPI_CMD_SET_TXINT_BUF: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - DEV_SPI_XFER_SET_TXBUF(spi_xfer, devbuf->buf, 0, devbuf->len); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, devbuf->len, 0); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - } else { - DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs); - } - break; - case SPI_CMD_SET_RXINT_BUF: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, devbuf->len, 0); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, devbuf->buf, 0, devbuf->len); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - } else { - DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs); - } - break; - case SPI_CMD_TRANSFER_POLLING: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - if (param != NULL) { - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR); - *spi_xfer = *((DEV_SPI_TRANSFER *)param); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - /* Transfer data by poll */ - dw_spi_poll_transfer(spi_info_ptr); - } else { - ercd = E_PAR; - } - break; - case SPI_CMD_QUAD_READ: - dw_spi_quad_receive(spi_info_ptr, (DEV_SPI_PAK_PTR)param); - break; - case SPI_CMD_TRANSFER_INT: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR); - *spi_xfer = *((DEV_SPI_TRANSFER *)param); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - /* Transfer data by interrupt */ - ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - } else { - ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - } - break; - - /* Master mode only commands */ - case SPI_CMD_MST_SET_FREQ: - DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - DW_SPI_CHECK_EXP(val32 > 0, E_PAR); - dw_spi_set_freq(spi_ctrl_ptr, val32); - spi_info_ptr->freq = val32; - break; - case SPI_CMD_MST_SEL_DEV: - DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - if (dw_spi_select_slave(spi_reg_ptr, val32) == 0) { - spi_info_ptr->slave = val32; - } else { - ercd = E_SYS; - } - break; - case SPI_CMD_MST_DSEL_DEV: - DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - if (dw_spi_deselect_slave(spi_reg_ptr, val32) == 0) { - spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED; - } else { - ercd = E_SYS; - } - break; - - /* Slave mode only commands */ - - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** - * @brief Send data through DesignWare SPI - * @param[in] spi_obj Spi device object pointer - * @param[in] data Data to send - * @param[in] len Data length to send - * @retval > 0 Byte count that was successfully sent for poll method - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_CTX Device is still in transfer state - * @retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ -int32_t dw_spi_write(DEV_SPI *spi_obj, const void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED); - DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - DW_SPI_CHECK_EXP(data != NULL, E_PAR); - DW_SPI_CHECK_EXP(len > 0, E_PAR); - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DEV_SPI_TRANSFER spi_xfer; - - /* Master and Slave transmit */ - DEV_SPI_XFER_SET_TXBUF(&spi_xfer, data, 0, len); - DEV_SPI_XFER_SET_RXBUF(&spi_xfer, NULL, len, 0); - DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL); - - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - - dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs); - - ercd = dw_spi_poll_transfer(spi_info_ptr); - -error_exit: - return ercd; -} - -/** - * @brief Read data through designware spi - * @param[in] spi_obj SPI device pointer - * @param[out] data Data received (data must be char type) - * @param[in] len Data length need to read - * @retval >= 0 Data that was successfully received - * @retval E_PAR Parameter is not valid - * @retval E_OBJ Device object is not valid or not exists - * @retval E_CLSED Device is not opened - * @retval < 0 Other error code not defined here - */ -int32_t dw_spi_read(DEV_SPI *spi_obj, void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED); - DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - DW_SPI_CHECK_EXP(data != NULL, E_PAR); - DW_SPI_CHECK_EXP(len > 0, E_PAR); - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DEV_SPI_TRANSFER spi_xfer; - - /* Master and Slave transmit */ - DEV_SPI_XFER_SET_TXBUF(&spi_xfer, NULL, len, 0); - DEV_SPI_XFER_SET_RXBUF(&spi_xfer, data, 0, len); - DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL); - - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - - dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs); - - ercd = dw_spi_poll_transfer(spi_info_ptr); - -error_exit: - return ercd; -} - -/** - * @brief DesignWare SPI interrupt handler - * @param[in] spi_obj SPI device pointer - * @param[in] ptr Extra information - */ -void dw_spi_isr(DEV_SPI *spi_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - uint32_t isr_status; - - isr_status = spi_reg_ptr->ISR; - - if (!isr_status) { - return; - } - if (spi_ctrl_ptr->dw_xfer.xfer_len == 0) { - dw_spi_disable_interrupt(spi_info_ptr); - } else { - if (isr_status & (DW_SPI_IMR_TXOIM | DW_SPI_IMR_RXOIM | DW_SPI_IMR_RXUIM)) { - dw_spi_clear_interrupt_all(spi_reg_ptr); - dw_spi_disable_interrupt(spi_info_ptr); - if (spi_info_ptr->spi_cbs.err_cb) { - spi_info_ptr->spi_cbs.err_cb(spi_obj); - } - memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER)); - } - dw_spi_reader(spi_info_ptr); - if (isr_status & DW_SPI_IMR_TXEIM) { - dw_spi_writer(spi_info_ptr); - } - if (dw_spi_xfer_end(spi_ctrl_ptr)) { - if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX) { - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - if (spi_info_ptr->spi_cbs.tx_cb) { - spi_info_ptr->spi_cbs.tx_cb(spi_obj); - } - } else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX) { - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - if (spi_info_ptr->spi_cbs.rx_cb) { - spi_info_ptr->spi_cbs.rx_cb(spi_obj); - } - } else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER) { - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - if (spi_info_ptr->spi_cbs.xfer_cb) { - spi_info_ptr->spi_cbs.xfer_cb(spi_obj); - } - } else { - dw_spi_disable_interrupt(spi_info_ptr); - } - memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER)); - } - } - -error_exit: - return; -} diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/trng/dw_nist_trng.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/trng/dw_nist_trng.c deleted file mode 100644 index d254cc65..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/trng/dw_nist_trng.c +++ /dev/null @@ -1,364 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "arc/arc_exception.h" -#include "string.h" - -#include "device/designware/dw_nist_trng.h" - -#ifdef TRNG_VERSION_NIST - -#define DBG_LESS -#include "embARC_debug.h" - -#define DW_TRNG_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of trng info object */ -#define VALID_CHK_TRNG_INFO_OBJECT(trnginfo_obj_ptr) { \ - DW_TRNG_CHECK_EXP((trnginfo_obj_ptr) != NULL, E_OBJ); \ - DW_TRNG_CHECK_EXP(((trnginfo_obj_ptr)->trng_ctrl) != NULL, E_OBJ); \ -} -#endif - -#define DW_TRNG_CMD_NOP (0x0) -#define DW_TRNG_CMD_GEN_NOISE (0x1) -#define DW_TRNG_CMD_GEN_NONCE (0x2) -#define DW_TRNG_CMD_CREATE_STATE (0x3) -#define DW_TRNG_CMD_RENEW_STATE (0x4) -#define DW_TRNG_CMD_REFRESH_ADDIN (0x5) -#define DW_TRNG_CMD_GEN_RANDOM (0x6) -#define DW_TRNG_CMD_ADVANCE_STATE (0x7) -#define DW_TRNG_CMD_RUN_KAT (0x8) -#define DW_TRNG_CMD_ZEROIZE (0xF) - -/** - * @fn dw_trng_unmask_reg_interrupt(DW_TRNG_REG_PTR trng_reg, uint32_t mask) - * @brief Enable designware trng bit interrupt with mask - */ -Inline void dw_trng_unmask_reg_interrupt(DW_TRNG_REG_PTR trng_reg, uint32_t mask) -{ - trng_reg->IE |= mask; -} - -/** - * @fn void dw_trng_mask_reg_interrupt(DW_TRNG_REG_PTR trng_reg, uint32_t mask) - * @brief Disable designware trng bit interrupt with mask - */ -Inline void dw_trng_mask_reg_interrupt(DW_TRNG_REG_PTR trng_reg, uint32_t mask) -{ - trng_reg->IE &= ~mask; -} - -/** - * @fn void dw_trng_wait_till_idle(DW_TRNG_REG_PTR trng_reg) - */ -Inline void dw_trng_wait_till_idle(DW_TRNG_REG_PTR trng_reg) -{ - while (trng_reg->stat.busy) { - ; - } -} - -static int32_t dw_trng_cmd(DEV_TRNG_INFO_PTR trng_info_ptr, uint32_t cmd) -{ - int32_t ercd = E_OK; - DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - - dw_trng_wait_till_idle(trng_reg_ptr); - switch (cmd) { - case DW_TRNG_CMD_NOP: - case DW_TRNG_CMD_GEN_NOISE: - case DW_TRNG_CMD_GEN_NONCE: - case DW_TRNG_CMD_CREATE_STATE: - case DW_TRNG_CMD_RENEW_STATE: - case DW_TRNG_CMD_REFRESH_ADDIN: - case DW_TRNG_CMD_GEN_RANDOM: - case DW_TRNG_CMD_ADVANCE_STATE: - case DW_TRNG_CMD_RUN_KAT: - case DW_TRNG_CMD_ZEROIZE: - trng_reg_ptr->CTRL |= cmd; break; - default: - ercd = E_PAR; break; - } - return ercd; -} - -static void dw_trng_enable_sys_interrupt(DEV_TRNG_INFO_PTR trng_info_ptr) -{ - DW_TRNG_CTRL_PTR trng_ctrl_ptr = (DW_TRNG_CTRL_PTR)(trng_info_ptr->trng_ctrl); - - trng_ctrl_ptr->int_status |= DW_TRNG_GINT_ENABLE; - if (trng_ctrl_ptr->intno != DW_TRNG_INVALID_INTNO) { - int_handler_install(trng_ctrl_ptr->intno, trng_ctrl_ptr->dw_trng_int_handler); - int_enable(trng_ctrl_ptr->intno); - } -} - -static void dw_trng_disable_sys_interrupt(DEV_TRNG_INFO_PTR trng_info_ptr) -{ - DW_TRNG_CTRL_PTR trng_ctrl_ptr = (DW_TRNG_CTRL_PTR)(trng_info_ptr->trng_ctrl); - - if (trng_ctrl_ptr->intno != DW_TRNG_INVALID_INTNO) { - int_disable(trng_ctrl_ptr->intno); - } - trng_ctrl_ptr->int_status = DW_TRNG_GINT_DISABLE; -} - -static int32_t dw_trng_zeroize(DEV_TRNG_INFO_PTR trng_info_ptr) -{ - int32_t ercd = E_OK; - - // DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - // DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - dw_trng_enable_sys_interrupt(trng_info_ptr); - ercd = dw_trng_cmd(trng_info_ptr, DW_TRNG_CMD_ZEROIZE); - return ercd; -} - -static int32_t dw_trng_reseed(DEV_TRNG_INFO_PTR trng_info_ptr, uint32_t *nonce_buf) -{ - DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - - if (nonce_buf != NULL) {// Nonce Reseed cmd, need to be run 2~3 time with new nonce depending on chosen security algorithm - uint8_t i; - volatile uint32_t *npa_data_ptr = &(trng_reg_ptr->NPA_DATA0); - dw_trng_wait_till_idle(trng_reg_ptr); - for (i = 0; i < 16; i++) { - npa_data_ptr[i] = nonce_buf[i]; - } - dw_trng_cmd(trng_info_ptr, DW_TRNG_CMD_GEN_NONCE); - } else {// Random Reseed cmd - dw_trng_cmd(trng_info_ptr, DW_TRNG_CMD_GEN_NOISE); - } - return E_OK; -} - -static void dw_trng_get_rand(DW_TRNG_REG_PTR trng_reg_ptr, uint32_t *data) // read from rand0~3 -{ - if (data != NULL) { - data[0] = trng_reg_ptr->RAND0; - data[1] = trng_reg_ptr->RAND1; - data[2] = trng_reg_ptr->RAND2; - data[3] = trng_reg_ptr->RAND3; - } else { - dbg_printf(DBG_LESS_INFO, "\r\n!DW_TRNG meet invalid memory error: LAST_CMD=0x%x\r\n", trng_reg_ptr->stat.last_cmd); - } -} - -static void dw_iic_mst_int_read(DEV_TRNG_PTR trng_obj) -{ - DEV_TRNG_INFO_PTR trng_info_ptr = &trng_obj->trng_info; - DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - DEV_BUFFER *buf_ptr = &(trng_info_ptr->out_buf); - uint32_t *p_buf = (uint32_t *)buf_ptr->buf; - - if (p_buf != NULL && buf_ptr->len >= buf_ptr->ofs + 4) {// check if buffer has enough space (needs 4 uint32_t per read) - dw_trng_get_rand(trng_reg_ptr, p_buf); - buf_ptr->ofs += 4; - } - if (trng_info_ptr->trng_cbs.out_cb) { - trng_info_ptr->trng_cbs.out_cb(trng_info_ptr); - } -} - -int32_t dw_trng_open(DEV_TRNG_PTR trng_obj) // reseed with internal random seed generator -{ - int32_t ercd = E_OK; - - DW_TRNG_CHECK_EXP(trng_obj != NULL, E_OBJ); - DEV_TRNG_INFO_PTR trng_info_ptr = &trng_obj->trng_info; - VALID_CHK_TRNG_INFO_OBJECT(trng_info_ptr); - DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - - trng_reg_ptr->smode.secure_en = 1;// enable mission mode (secure) - /** - * trng interrupt related init - */ - dw_trng_disable_sys_interrupt(trng_info_ptr); - dw_trng_unmask_reg_interrupt(trng_reg_ptr, DW_TRNG_INT_ALL); - dw_trng_zeroize(trng_info_ptr); - // can do a KAT test here to ensure DRBGs are running correctly, need to zeroize afterwards - dw_trng_reseed(trng_info_ptr, NULL); - - ercd = dw_trng_cmd(trng_info_ptr, DW_TRNG_CMD_CREATE_STATE); - -error_exit: - return ercd; -} - -int32_t dw_trng_close(DEV_TRNG_PTR trng_obj) -{ - int32_t ercd = E_OK; - - DW_TRNG_CHECK_EXP(trng_obj != NULL, E_OBJ); - DEV_TRNG_INFO_PTR trng_info_ptr = &trng_obj->trng_info; - VALID_CHK_TRNG_INFO_OBJECT(trng_info_ptr); - DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - - dw_trng_mask_reg_interrupt(trng_reg_ptr, DW_TRNG_INT_ALL); - dw_trng_disable_sys_interrupt(trng_info_ptr); - // clean/release in buffer and out buffer - memset(&(trng_info_ptr->in_buf), 0, sizeof(DEV_BUFFER)); - memset(&(trng_info_ptr->out_buf), 0, sizeof(DEV_BUFFER)); - memset(&(trng_info_ptr->trng_cbs), 0, sizeof(DEV_TRNG_CBS)); - - // Do a zeroize for security - dw_trng_cmd(trng_info_ptr, DW_TRNG_CMD_ZEROIZE); - while (!trng_reg_ptr->istat.zeroized) { - ; // wait until secure data cleaned - } - trng_reg_ptr->istat.zeroized = 1; - -error_exit: - return E_OK; -} - -int32_t dw_trng_control(DEV_TRNG_PTR trng_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - - DW_TRNG_CHECK_EXP(trng_obj != NULL, E_OBJ); - DEV_TRNG_INFO_PTR trng_info_ptr = &trng_obj->trng_info; - VALID_CHK_TRNG_INFO_OBJECT(trng_info_ptr); - - // uint32_t val32; /** to receive unsigned int value */ - - switch (ctrl_cmd) { - case TRNG_CMD_SET_RAND_RESEED_AUTO: - ercd = dw_trng_cmd(trng_info_ptr, DW_TRNG_CMD_RENEW_STATE); - break; - case TRNG_CMD_SET_RAND_RESEED_NONCE: - ercd = dw_trng_reseed(trng_info_ptr, param); - break; - case TRNG_CMD_SET_IN_CB: - DW_TRNG_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - trng_info_ptr->trng_cbs.in_cb = param; - break; - case TRNG_CMD_SET_OUT_CB: - DW_TRNG_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - trng_info_ptr->trng_cbs.out_cb = param; - break; - case TRNG_CMD_SET_ERR_CB: - DW_TRNG_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - trng_info_ptr->trng_cbs.err_cb = param; - break; - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -int32_t dw_trng_read(DEV_TRNG_PTR trng_obj, uint32_t *data_buf) -{ - int32_t ercd = E_OK; - - DW_TRNG_CHECK_EXP(trng_obj != NULL, E_OBJ); - DEV_TRNG_INFO_PTR trng_info_ptr = &trng_obj->trng_info; - VALID_CHK_TRNG_INFO_OBJECT(trng_info_ptr); - DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - - dw_trng_cmd(trng_info_ptr, DW_TRNG_CMD_GEN_RANDOM); - if (data_buf != NULL) { - dw_trng_wait_till_idle(trng_reg_ptr); - dw_trng_get_rand(trng_reg_ptr, data_buf); - } - -error_exit: - return ercd; -} - -void dw_trng_isr(DEV_TRNG_PTR trng_obj, void *ptr) -{ - int32_t ercd = E_OK; - - DW_TRNG_CHECK_EXP(trng_obj != NULL, E_OBJ); - DEV_TRNG_INFO_PTR trng_info_ptr = &(trng_obj->trng_info); - - /* START ERROR CHECK */ - VALID_CHK_TRNG_INFO_OBJECT(trng_info_ptr); - /* END OF ERROR CHECK */ - DW_TRNG_CTRL_PTR trng_ctrl_ptr = trng_info_ptr->trng_ctrl; - DW_TRNG_REG_PTR trng_reg_ptr = (DW_TRNG_REG_PTR) trng_ctrl_ptr->dw_trng_regs; - dbg_printf(DBG_MORE_INFO, "dw_trng_isr "); - - if (trng_reg_ptr->alarms.illegal_cmd_seq) { - dbg_printf(DBG_LESS_INFO, "\r\n!DW_TRNG meet illegal_cmd_seq error: LAST_CMD=0x%x\r\n", trng_reg_ptr->stat.last_cmd); - dw_trng_disable_sys_interrupt(trng_info_ptr); - trng_reg_ptr->alarms.illegal_cmd_seq = 1;// Write 1 to clear bit - if (trng_info_ptr->trng_cbs.err_cb) { - trng_info_ptr->trng_cbs.err_cb(trng_info_ptr); - } - } - - if (trng_reg_ptr->istat.zeroized) { // zeroize operations can interrupt other operations - trng_reg_ptr->istat.zeroized = 1; // Write 1 to clear bit - dbg_printf(DBG_MORE_INFO, "zeroized"); - } - if (trng_reg_ptr->istat.noise_rdy) { - trng_reg_ptr->istat.noise_rdy = 1;// Write 1 to clear bit - dbg_printf(DBG_MORE_INFO, "noise_rdy"); - } - if (trng_reg_ptr->istat.done) { - trng_reg_ptr->istat.done = 1;// Write 1 to clear bit - dbg_printf(DBG_MORE_INFO, "done"); - if (trng_reg_ptr->stat.last_cmd == DW_TRNG_CMD_GEN_RANDOM) { - dbg_printf(DBG_MORE_INFO, " --- GEN RANDOM done"); - trng_info_ptr->byte_generated += 4;// TODO: once too many bytes have been generated, prompt to reseed - dw_iic_mst_int_read(trng_obj); - } - } - if (trng_reg_ptr->istat.alarms) { - trng_reg_ptr->istat.alarms = 1;// Write 1 to clear bit - dbg_printf(DBG_MORE_INFO, "alarms"); - } - if (trng_reg_ptr->istat.kat_completed) { - trng_reg_ptr->istat.kat_completed = 1;// Write 1 to clear bit - dbg_printf(DBG_MORE_INFO, "kat_completed"); - } - - dbg_printf(DBG_MORE_INFO, " #\r\n"); - -error_exit: - return; -} - -#endif /* TRNG_VERSION_NIST */ diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/trng/dw_trng.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/trng/dw_trng.c deleted file mode 100644 index 3c16b0f0..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/trng/dw_trng.c +++ /dev/null @@ -1,226 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "device/designware/dw_trng.h" - -#ifndef TRNG_VERSION_NIST - -#define DW_TRNG_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#define DW_TRNG_MODE_R256 0x08 -#define DW_TRNG_MODE_R256_OFFSET 3 - -#define DW_TRNG_ISTAT_RAND_RDY 0x01 -#define DW_TRNG_ISTAT_RAND_RDY_OFFSET 0 -#define DW_TRNG_ISTAT_SEED_DONE 0x02 -#define DW_TRNG_ISTAT_SEED_DONE_OFFSET 1 -#define DW_TRNG_ISTAT_AGE_ALARM 0x04 -#define DW_TRNG_ISTAT_AGE_ALARM_OFFSET 2 -#define DW_TRNG_ISTAT_RQST_ALARM 0x08 -#define DW_TRNG_ISTAT_RQST_ALARM_OFFSET 3 -#define DW_TRNG_ISTAT_LFSR_LOCKUP 0x10 -#define DW_TRNG_ISTAT_LFSR_LOCKUP_OFFSET 4 - -#define DW_TRNG_CMD_GEN 1 -#define DW_TRNG_CMD_RESEED 2 -#define DW_TRNG_CMD_NONCE 3 - -static int32_t dw_trng_cmd(DW_TRNG_REG_PTR trng_reg, uint32_t cmd) -{ - int32_t ercd = E_OK; - - switch (cmd) { - case DW_TRNG_CMD_GEN: - trng_reg->CTRL |= cmd; - break; - - case DW_TRNG_CMD_RESEED: - trng_reg->CTRL |= cmd; - break; - - case DW_TRNG_CMD_NONCE: - trng_reg->CTRL |= cmd; - break; - - default: - ercd = E_PAR; break; - } - return ercd; -} - -inline static int32_t dw_trng_get_mode(DW_TRNG_REG_PTR trng_reg) -{ - return (trng_reg->MODE & DW_TRNG_MODE_R256) >> 3; -} - -inline static void dw_trng_set_mode(DW_TRNG_REG_PTR trng_reg, uint32_t r256) -{ - if (r256) { - trng_reg->MODE |= DW_TRNG_MODE_R256; - } else { - trng_reg->MODE &= ~DW_TRNG_MODE_R256; - } -} - -inline static int32_t dw_trng_get_istat_rand_rdy(DW_TRNG_REG_PTR trng_reg) -{ - return (trng_reg->ISTAT & DW_TRNG_ISTAT_RAND_RDY) >> DW_TRNG_ISTAT_RAND_RDY_OFFSET; -} - -inline static void dw_trng_clear_istat_rand_rdy(DW_TRNG_REG_PTR trng_reg) -{ - trng_reg->ISTAT = DW_TRNG_ISTAT_RAND_RDY;// write 1 to clear register bits -} - -inline static int32_t dw_trng_get_istat_seed_done(DW_TRNG_REG_PTR trng_reg) -{ - return (trng_reg->ISTAT & DW_TRNG_ISTAT_SEED_DONE) >> DW_TRNG_ISTAT_SEED_DONE_OFFSET; -} - -inline static void dw_trng_clear_istat_seed_done(DW_TRNG_REG_PTR trng_reg) -{ - trng_reg->ISTAT = DW_TRNG_ISTAT_SEED_DONE;// write 1 to clear register bits -} - -static void dw_trng_get_rand(DW_TRNG_REG_PTR trng_reg, uint32_t *data) // read from rand0~3 or rand0~7 -{ - data[0] = trng_reg->RAND0; - data[1] = trng_reg->RAND1; - data[2] = trng_reg->RAND2; - data[3] = trng_reg->RAND3; - // if(dw_trng_get_mode(trng_reg) == 1 ) - data[4] = trng_reg->RAND4; - data[5] = trng_reg->RAND5; - data[6] = trng_reg->RAND6; - data[7] = trng_reg->RAND7; - return; -} - -static void dw_trng_get_stat(DW_TRNG_REG_PTR trng_reg, uint32_t *stat) -{ - *stat = trng_reg->STAT; - return; -} - -static int32_t dw_trng_reseed(DW_TRNG_REG_PTR trng_reg, uint32_t *nonce_buf) -{ - if (nonce_buf != NULL) {// Nonce Reseed cmd - dw_trng_cmd(trng_reg, DW_TRNG_CMD_NONCE); - // TODO - } else {// Random Reseed cmd - dw_trng_cmd(trng_reg, DW_TRNG_CMD_RESEED); - while (!dw_trng_get_istat_seed_done(trng_reg)) { - // do nothing, wait until reseed is ready - } - dw_trng_clear_istat_seed_done(trng_reg);// clear ISTAT.RAND_RDY bit to acknowledge - } - return E_OK; -} - -int32_t dw_trng_open(DEV_TRNG_PTR trng_obj) // reseed with internal random seed generator -{ - int32_t ercd = E_OK; - DEV_TRNG_INFO_PTR ptrng_info = &trng_obj->trng_info; - DW_TRNG_CTRL_PTR dw_trng_ctrl_ptr = ptrng_info->trng_ctrl; - DW_TRNG_REG_PTR ptrng = (DW_TRNG_REG_PTR) dw_trng_ctrl_ptr->dw_trng_regs; - - dw_trng_reseed(ptrng, NULL); - -error_exit: - return ercd; -} - -int32_t dw_trng_close(DEV_TRNG_PTR trng_obj) // do nothing -{ - return E_OK; -} - -int32_t dw_trng_control(DEV_TRNG_PTR trng_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_TRNG_INFO_PTR ptrng_info = &trng_obj->trng_info; - DW_TRNG_CTRL_PTR dw_trng_ctrl_ptr = ptrng_info->trng_ctrl; - DW_TRNG_REG_PTR ptrng = (DW_TRNG_REG_PTR) dw_trng_ctrl_ptr->dw_trng_regs; - - // uint32_t val32; /** to receive unsigned int value */ - - switch (ctrl_cmd) { - case TRNG_CMD_SET_RAND_128_BIT_OUTPUT: - dw_trng_set_mode(ptrng, 0); - break; - case TRNG_CMD_SET_RAND_256_BIT_OUTPUT: - dw_trng_set_mode(ptrng, 1); - break; - case TRNG_CMD_SET_RAND_RESEED_AUTO: - dw_trng_reseed(ptrng, NULL); - break; - case TRNG_CMD_SET_RAND_RESEED_NONCE: - if (param == NULL) { - ercd = E_PAR; - break; - } - dw_trng_reseed(ptrng, param); - break; - - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -int32_t dw_trng_read(DEV_TRNG_PTR trng_obj, uint32_t *data_buf) -{ - int32_t ercd = E_OK; - DEV_TRNG_INFO_PTR ptrng_info = &trng_obj->trng_info; - DW_TRNG_CTRL_PTR dw_trng_ctrl_ptr = ptrng_info->trng_ctrl; - DW_TRNG_REG_PTR ptrng = (DW_TRNG_REG_PTR) dw_trng_ctrl_ptr->dw_trng_regs; - - dw_trng_cmd(ptrng, DW_TRNG_CMD_GEN); - while (!dw_trng_get_istat_rand_rdy(ptrng)) { - // do nothing, wait until random numbers are ready - } - dw_trng_clear_istat_rand_rdy(ptrng);// clear ISTAT.RAND_RDY bit to acknowledge - dw_trng_get_rand(ptrng, data_buf); - -error_exit: - return ercd; -} - -void dw_trng_isr(DEV_TRNG_PTR trng_obj, void *ptr) -{ - // polling mode, isr not implemented -} - -#endif /* TRNG_VERSION_NIST */ diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/designware/uart/dw_uart.c b/platform/vendor_bsp/embarc_bsp/device/ip/designware/uart/dw_uart.c deleted file mode 100644 index 98d0465a..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/designware/uart/dw_uart.c +++ /dev/null @@ -1,958 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include - -#include "embARC_toolchain.h" -#include "embARC_error.h" - -#include "arc/arc_exception.h" - -#include "device/designware/dw_uart_hal.h" -#include "device/designware/dw_uart.h" - -/** - * DesignWare UART driver macros used in uart driver - */ -/** check expressions used in DesignWare UART driver implementation */ -#define DW_UART_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of uart info object */ -#define VALID_CHK_UART_INFO_OBJECT(uartinfo_obj_ptr) { \ - DW_UART_CHECK_EXP((uartinfo_obj_ptr) != NULL, E_OBJ); \ - DW_UART_CHECK_EXP(((uartinfo_obj_ptr)->uart_ctrl) != NULL, E_OBJ); \ -} -#endif - -/** convert DesignWare baudrate to divisor */ -#define DW_UART_BAUD2DIV(perifreq, baud) ((perifreq) / ((baud) * 16)) - -/** - * DesignWare UART interrupt callback routines select macros definitions - */ -#define DW_UART_RDY_SND (1U) /*!< ready to send callback */ -#define DW_UART_RDY_RCV (2U) /*!< ready to receive callback */ - -/** - * @defgroup DEVICE_DW_UART_STATIC DesignWare UART Driver Static Functions - * @ingroup DEVICE_DW_UART - * @brief Static or inline functions, variables for DesignWare UART handle UART operations, - * only used in this file. - * @{ - */ -const uint8_t dw_uart_databits[] = { \ - DW_UART_LCR_WORD_LEN5, DW_UART_LCR_WORD_LEN6, \ - DW_UART_LCR_WORD_LEN7, DW_UART_LCR_WORD_LEN8 -}; -const uint8_t dw_uart_parity[] = { - DW_UART_LCR_PARITY_NONE, DW_UART_LCR_PARITY_ODD, - DW_UART_LCR_PARITY_EVEN, DW_UART_LCR_PARITY_MASK, - DW_UART_LCR_PARITY_SPACE -}; -const uint8_t dw_uart_stopbits[] = { - DW_UART_LCR_1_STOP_BIT, DW_UART_LCR_1D5_STOP_BIT, - DW_UART_LCR_2_STOP_BIT -}; - -/** - * @fn int32_t dw_uart_putready(DW_UART_REG *uart_reg_ptr) - * @brief Test whether uart is ready to send, 1 ready, 0 not ready - */ -Inline int32_t dw_uart_putready(DW_UART_REG *uart_reg_ptr) -{ - if (uart_reg_ptr->CPR & DW_UART_CPR_FIFO_STAT) { - return ((uart_reg_ptr->USR & DW_UART_USR_TFNF) != 0); - } else { - return ((uart_reg_ptr->LSR & DW_UART_LSR_TXD_EMPTY) != 0); - } -} - -/** - * @fn int32_t dw_uart_getready(DW_UART_REG *uart_reg_ptr) - * @brief Test whether uart is ready to receive, 1 ready, 0 not ready - */ -Inline int32_t dw_uart_getready(DW_UART_REG *uart_reg_ptr) -{ - if (uart_reg_ptr->CPR & DW_UART_CPR_FIFO_STAT) { - return ((uart_reg_ptr->USR & DW_UART_USR_RFNE) != 0); - } else { - return ((uart_reg_ptr->LSR & DW_UART_LSR_DR) != 0); - } -} - -/** - * @fn void dw_uart_putchar(DW_UART_REG *uart_reg_ptr, char chr) - * @brief Write char to uart send fifo - */ -Inline void dw_uart_putchar(DW_UART_REG *uart_reg_ptr, char chr) -{ - uart_reg_ptr->DATA = chr; -} - -/** - * @fn int32_t dw_uart_getchar(DW_UART_REG *uart_reg_ptr) - * @brief Read data from uart receive fifo, return data received - */ -Inline int32_t dw_uart_getchar(DW_UART_REG *uart_reg_ptr) -{ - return (int32_t)uart_reg_ptr->DATA; -} -/** - * @fn int32_t dw_uart_snd_chr(DW_UART_REG *uart_reg_ptr, char chr) - * @brief Send char through designware uart when available, - * mostly used in interrupt method, non-blocked function - * @param[in] uart_reg_ptr Uart register structure pointer - * @param[in] chr char to sent - * @retval E_OK Send successfully without any issues - * @retval E_OBJ Device object is not ready to send data - */ -Inline int32_t dw_uart_snd_chr(DW_UART_REG *uart_reg_ptr, char chr) -{ - if (dw_uart_putready(uart_reg_ptr)) { - dw_uart_putchar(uart_reg_ptr, chr); - return E_OK; - } - return E_OBJ; -} -/** - * @fn int32_t dw_uart_rcv_chr(DW_UART_REG *uart_reg_ptr) - * @brief Receive one char through designware uart, - * mostly used in interrupt routine, non-blocked function - * @param[in] uart_reg_ptr Uart register structure pointer - * @return Data received - */ -Inline int32_t dw_uart_rcv_chr(DW_UART_REG *uart_reg_ptr) -{ - return dw_uart_getchar(uart_reg_ptr); -} -/** - * @fn void dw_uart_psnd_chr(DW_UART_REG *uart_reg_ptr, char chr) - * @brief Send char through designware uart in poll method, blocked function - * @param[in] uart_reg_ptr Uart register structure pointer - * @param[in] chr Char to sent - */ -Inline void dw_uart_psnd_chr(DW_UART_REG *uart_reg_ptr, char chr) -{ - /** wait until uart is ready to send */ - while (!dw_uart_putready(uart_reg_ptr)) { - ; /* blocked */ - } - /** send char */ - dw_uart_putchar(uart_reg_ptr, chr); -} -/** - * @fn int32_t dw_uart_prcv_chr(DW_UART_REG *uart_reg_ptr) - * @brief Receive one char through designware uart in poll method, blocked function - * @param[in] uart_reg_ptr Uart register structure pointer - * @return Data received - */ -Inline int32_t dw_uart_prcv_chr(DW_UART_REG *uart_reg_ptr) -{ - /** wait until uart is ready to receive */ - while (!dw_uart_getready(uart_reg_ptr)) { - ; /* blocked */ - } - /** receive data */ - return dw_uart_getchar(uart_reg_ptr); -} - -/** - * @brief Set designware uart DPS value - * @param uart_reg_ptr Uart register structure pointer - * @param dps Data bits/parity bit/stop bits parameter - * @retval 0 Set ok - * @retval !0 Set failed - */ -static int32_t dw_uart_set_dps(DW_UART_REG *uart_reg_ptr, UART_DPS_FORMAT *dps) -{ - uint32_t dps_value = 0; - - /* data bits check */ - if ((dps->databits < 5) || (dps->databits > 8)) { - return -1; - } - /* stop bits check */ - if (dps->stopbits > UART_STPBITS_TWO) { - return -1; - } - /* parity bit type check */ - if (dps->parity > UART_PARITY_SPACE) { - return -1; - } - - dps_value |= (uint32_t)dw_uart_databits[dps->databits - 5]; - dps_value |= (uint32_t)dw_uart_stopbits[dps->stopbits]; - dps_value |= (uint32_t)dw_uart_parity[dps->parity]; - - /* clear dps bits */ - uart_reg_ptr->LCR &= (~DW_UART_LCR_DPS_MASK); - /* set dps bits */ - uart_reg_ptr->LCR |= dps_value; - - return 0; -} - -/** - * @brief Set designware uart baudrate - * @param uart_reg_ptr Uart register structure pointer - * @param baud_divisor Uart baudrate divisor - */ -static void dw_uart_set_baud(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor) -{ - /* enable uart baudrate update */ - uart_reg_ptr->LCR |= DW_UART_LCR_DLAB; - /** - * setting uart baudrate registers - */ - uart_reg_ptr->DATA = baud_divisor & 0xff; /*!< DLL */ - uart_reg_ptr->IER = (baud_divisor >> 8) & 0xff; /*!< DLH */ - /** disable DLAB */ - uart_reg_ptr->LCR &= ~(DW_UART_LCR_DLAB); -} - -/** - * @fn void dw_uart_software_reset(DW_UART_REG *uart_reg_ptr) - * @brief Do uart software reset - * @param uart_reg_ptr Uart register structure pointer - */ -Inline void dw_uart_software_reset(DW_UART_REG *uart_reg_ptr) -{ - uart_reg_ptr->SRR = DW_UART_SRR_UR | DW_UART_SRR_RFR | DW_UART_SRR_XFR; - while (uart_reg_ptr->USR & DW_UART_USR_BUSY) { - ; /* wait until software reset completed */ - } -} - -/** - * @brief Set designware uart baudrate - * @param uart_reg_ptr Uart register structure pointer - * @param hwfc Uart hardware flow control type - * @note Need to set corresponding pin functions - */ -static void dw_uart_set_hwfc(DW_UART_REG *uart_reg_ptr, UART_HW_FLOW_CONTROL hwfc) -{ - if (hwfc == UART_FC_NONE) { - uart_reg_ptr->MCR &= ~(DW_UART_MCR_AFCE | DW_UART_MCR_RTS); - } - if ((hwfc == UART_FC_RTS) || (hwfc == UART_FC_BOTH)) { - uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE | DW_UART_MCR_RTS); - } - if ((hwfc == UART_FC_CTS) || (hwfc == UART_FC_BOTH)) { - uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE); - } -} - -/** - * @fn void dw_spi_disable(DW_SPI_REG *spi_reg_ptr) - */ -Inline void dw_uart_set_break(DW_UART_REG *uart_reg_ptr) -{ - uart_reg_ptr->LCR |= DW_UART_LCR_BREAK; -} - -/** - * @fn void dw_uart_clr_break(DW_UART_REG *uart_reg_ptr) - */ -Inline void dw_uart_clr_break(DW_UART_REG *uart_reg_ptr) -{ - uart_reg_ptr->LCR &= ~DW_UART_LCR_BREAK; -} - -/** - * @brief Initialise designware uart with selected baud rate - * @param[in] uart_reg_ptr Uart register structure pointer - * @param[in] baud_divisor Baud rate - * @param[in] dps Uart databits/parity/stopbits - * @param[in] hwfc Uart flow control method - */ -static void dw_uart_init(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor, UART_DPS_FORMAT *dps, UART_HW_FLOW_CONTROL hwfc) -{ - dw_uart_software_reset(uart_reg_ptr); - - dw_uart_set_hwfc(uart_reg_ptr, hwfc); - dw_uart_set_dps(uart_reg_ptr, dps); - dw_uart_set_baud(uart_reg_ptr, baud_divisor); - - uart_reg_ptr->IIR = 0x1; /** enable uart fifo (FCR IIR is the same) */ - uart_reg_ptr->IER = 0x0; /** disable all uart interrupt */ -} - -/** - * @brief Set designware uart baud rate - * @param uart_info_ptr Uart information structure pointer - */ -static void dw_uart_flush_output(DEV_UART_INFO *uart_info_ptr) -{ - uint32_t i; - char *p_charbuf; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - if (uart_info_ptr->tx_buf.buf != NULL) { - p_charbuf = (char *)(uart_info_ptr->tx_buf.buf); - for (i = uart_info_ptr->tx_buf.ofs; i < uart_info_ptr->tx_buf.len; i++) { - dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i]); - } - /* clear transmit buffer */ - uart_info_ptr->tx_buf.buf = NULL; - uart_info_ptr->tx_buf.len = 0; - uart_info_ptr->tx_buf.ofs = 0; - } - if (uart_reg_ptr->CPR & DW_UART_CPR_FIFO_STAT) { - /* wait until transmit fifo is empty */ - while ((uart_reg_ptr->USR & DW_UART_USR_TFE) == 0) { - ; - } - } - while (uart_reg_ptr->USR & DW_UART_USR_BUSY) { - ; - } -} - -/** - * @brief Disable designware uart send or receive interrupt - * @param[in] uart_info_ptr Uart information structure pointer - * @param[in] cbrtn Control code of callback routine - */ -static void dw_uart_dis_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - switch (cbrtn) { - case DW_UART_RDY_SND: - uart_reg_ptr->IER &= ~DW_UART_IER_XMIT_EMPTY; - uart_ctrl_ptr->int_status &= ~DW_UART_TXINT_ENABLE; - break; - case DW_UART_RDY_RCV: - uart_reg_ptr->IER &= ~DW_UART_IER_DATA_AVAIL; - uart_ctrl_ptr->int_status &= ~DW_UART_RXINT_ENABLE; - break; - default: - break; - } - if (uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) { - if ((uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE | DW_UART_TXINT_ENABLE)) == 0) { - if (uart_ctrl_ptr->intno != DW_UART_INVALID_INTNO) { - int_disable(uart_ctrl_ptr->intno); - } - uart_ctrl_ptr->int_status &= ~DW_UART_GINT_ENABLE; - } - } -} - -/** - * @brief Enable DesignWare UART send or receive interrupt - * @param[in] uart_info_ptr Uart information structure pointer - * @param[in] cbrtn Control code of callback routine - */ -static void dw_uart_ena_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - switch (cbrtn) { - case DW_UART_RDY_SND: - uart_ctrl_ptr->int_status |= DW_UART_TXINT_ENABLE; - uart_reg_ptr->IER |= DW_UART_IER_XMIT_EMPTY; - break; - case DW_UART_RDY_RCV: - uart_ctrl_ptr->int_status |= DW_UART_RXINT_ENABLE; - uart_reg_ptr->IER |= DW_UART_IER_DATA_AVAIL; - break; - default: - break; - } - if ((uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) == 0) { - if (uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE | DW_UART_TXINT_ENABLE)) { - uart_ctrl_ptr->int_status |= DW_UART_GINT_ENABLE; - if (uart_ctrl_ptr->intno != DW_UART_INVALID_INTNO) { - int_enable(uart_ctrl_ptr->intno); - } - } - } -} - -/** - * @brief Disable designware uart interrupt - * @param uart_info_ptr Uart information structure pointer - */ -static void dw_uart_disable_interrupt(DEV_UART_INFO *uart_info_ptr) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - - /** disable uart send&receive interrupt after disable uart interrupt */ - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - /* disable uart interrupt */ - if (uart_ctrl_ptr->intno != DW_UART_INVALID_INTNO) { - int_disable(uart_ctrl_ptr->intno); - } - uart_ctrl_ptr->int_status &= ~(DW_UART_GINT_ENABLE | DW_UART_TXINT_ENABLE | DW_UART_RXINT_ENABLE); -} - -/** enable designware uart */ -static void dw_uart_enable_device(DEV_UART_INFO *uart_info_ptr) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - if ((uart_info_ptr->status & DEV_ENABLED) == 0) { - dw_uart_set_baud(uart_reg_ptr, uart_info_ptr->baudrate); - uart_info_ptr->status |= DEV_ENABLED; - } -} - -/** disable designware uart */ -static void dw_uart_disable_device(DEV_UART_INFO *uart_info_ptr) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - if ((uart_info_ptr->status & DEV_ENABLED) == DEV_ENABLED) { - dw_uart_set_baud(uart_reg_ptr, 0); - uart_info_ptr->status &= ~DEV_ENABLED; - } -} - -/** abort current interrupt transmit transfer */ -static void dw_uart_abort_tx(DEV_UART *uart_obj) -{ - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - - if (uart_ctrl_ptr->int_status & DW_UART_TXINT_ENABLE) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - uart_info_ptr->status |= DEV_IN_TX_ABRT; - if (uart_info_ptr->uart_cbs.tx_cb != NULL) { - uart_info_ptr->uart_cbs.tx_cb(uart_obj); - } - uart_info_ptr->status &= ~(DEV_IN_TX_ABRT); - } -} - -/** abort current interrupt receive transfer */ -static void dw_uart_abort_rx(DEV_UART *uart_obj) -{ - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - - if (uart_ctrl_ptr->int_status & DW_UART_RXINT_ENABLE) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - uart_info_ptr->status |= DEV_IN_RX_ABRT; - if (uart_info_ptr->uart_cbs.rx_cb != NULL) { - uart_info_ptr->uart_cbs.rx_cb(uart_obj); - } - uart_info_ptr->status &= ~(DEV_IN_RX_ABRT); - } -} - -/** Get available transmit fifo count */ -static int32_t dw_uart_get_txavail(DW_UART_CTRL *uart_ctrl_ptr) -{ - int32_t tx_avail = 0; - DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase); - - if (uart_ctrl_ptr->tx_fifo_len <= 1) { - if (dw_uart_putready(uart_reg_ptr) == 1) { - tx_avail = 1; - } else { - tx_avail = 0; - } - } else { - tx_avail = uart_ctrl_ptr->tx_fifo_len - uart_reg_ptr->TFL; - } - return tx_avail; -} - -/** Get available receive fifo count */ -static int32_t dw_uart_get_rxavail(DW_UART_CTRL *uart_ctrl_ptr) -{ - int32_t rx_avail = 0; - DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase); - - if (uart_ctrl_ptr->rx_fifo_len <= 1) { - if (dw_uart_getready(uart_reg_ptr) == 1) { - rx_avail = 1; - } else { - rx_avail = 0; - } - } else { - rx_avail = uart_reg_ptr->RFL; - } - return rx_avail; -} - -/** @} end of group DEVICE_DW_UART_STATIC */ - -/** - * @brief Open a designware uart device - * @param[in] uart_obj Uart object structure pointer - * @param[in] baud Baud rate - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different baudrate, then return E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ -int32_t dw_uart_open(DEV_UART *uart_obj, uint32_t baud) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(baud > 0, E_PAR); - /* END OF ERROR CHECK */ - - uart_info_ptr->opn_cnt++; - if (uart_info_ptr->opn_cnt > 1) { /* opened before */ - if (baud == uart_info_ptr->baudrate) { /* baudrate is the same */ - return E_OK; - } else { /* open with different baudrate */ - return E_OPNED; - } - } - - int32_t baud_divisor = 0; - uint32_t uart_cpr; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - uart_cpr = uart_reg_ptr->CPR; - - /* Get FIFO Length */ - if (uart_cpr & DW_UART_CPR_FIFO_STAT) { - uart_ctrl_ptr->tx_fifo_len = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4; - uart_ctrl_ptr->rx_fifo_len = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4; - } else { - uart_ctrl_ptr->tx_fifo_len = 0; - uart_ctrl_ptr->rx_fifo_len = 0; - } - - /** init uart */ - uart_info_ptr->baudrate = baud; - baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, baud); - UART_DPS_FORMAT_DEFAULT(uart_info_ptr->dps_format); - uart_info_ptr->hwfc = UART_FC_DEFAULT; - dw_uart_init(uart_reg_ptr, baud_divisor, &(uart_info_ptr->dps_format), uart_info_ptr->hwfc); - - uart_info_ptr->status = DEV_ENABLED; - uart_info_ptr->extra = NULL; - - /** - * uart interrupt related init - */ - dw_uart_disable_interrupt(uart_info_ptr); - /** install uart interrupt into system */ - if (uart_ctrl_ptr->intno != DW_UART_INVALID_INTNO) { - int_handler_install(uart_ctrl_ptr->intno, uart_ctrl_ptr->dw_uart_int_handler); - } - - memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS)); - -error_exit: - return ercd; -} - -/** - * @brief Close a DesignWare UART device - * @param[in] uart_obj Uart object structure pointer - * @retval E_OK Open successfully without any issues - * @retval E_OPNED Device is still opened, the device opn_cnt decreased by 1 - * @retval E_OBJ Device object is not valid - */ -int32_t dw_uart_close(DEV_UART *uart_obj) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_OK); - /* END OF ERROR CHECK */ - - uart_info_ptr->opn_cnt--; - if (uart_info_ptr->opn_cnt == 0) { - dw_uart_disable_interrupt(uart_info_ptr); - dw_uart_abort_tx(uart_obj); - dw_uart_abort_rx(uart_obj); - dw_uart_flush_output(uart_info_ptr); - memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS)); - dw_uart_disable_device(uart_info_ptr); - uart_info_ptr->status = 0; - uart_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** - * @brief Control uart by ctrl command - * @param[in] uart_obj Uart object structure pointer - * @param[in] ctrl_cmd @ref DEVICE_HAL_UART_CTRLCMD "control command", to change or get some thing related to uart - * @param[in,out] param Parameters used to control uart or return something - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_DIS Device is disabled - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ -int32_t dw_uart_control(DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED); - /* END OF ERROR CHECK */ - - uint32_t val32; /** to receive unsigned int value */ - int32_t baud_divisor = 0; - DEV_BUFFER *devbuf; - UART_DPS_FORMAT *dps_ptr; - UART_HW_FLOW_CONTROL hwfc_local; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - /* check whether current device is disabled */ - if ((uart_info_ptr->status & DEV_ENABLED) == 0) { - /** When device is disabled, - * only UART_CMD_ENA_DEV, UART_CMD_DIS_DEV, UART_CMD_GET_STATUS - * are available, other commands will return E_SYS - */ - if ((ctrl_cmd != UART_CMD_ENA_DEV) && \ - (ctrl_cmd != UART_CMD_DIS_DEV) && \ - (ctrl_cmd != UART_CMD_GET_STATUS)) { - return E_SYS; - } - } - - switch (ctrl_cmd) { - case UART_CMD_SET_BAUD: - val32 = (uint32_t)param; - DW_UART_CHECK_EXP(val32 > 0, E_PAR); - if (val32 != uart_info_ptr->baudrate) { - baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, val32); - dw_uart_set_baud(uart_reg_ptr, baud_divisor); - uart_info_ptr->baudrate = val32; - } - break; - case UART_CMD_GET_STATUS: - DW_UART_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = uart_info_ptr->status; - break; - case UART_CMD_ENA_DEV: - dw_uart_enable_device(uart_info_ptr); - break; - case UART_CMD_DIS_DEV: - dw_uart_disable_device(uart_info_ptr); - break; - case UART_CMD_FLUSH_OUTPUT: - dw_uart_flush_output(uart_info_ptr); - break; - case UART_CMD_GET_RXAVAIL: - DW_UART_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_uart_get_rxavail(uart_ctrl_ptr); - break; - case UART_CMD_GET_TXAVAIL: - DW_UART_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_uart_get_txavail(uart_ctrl_ptr); - break; - case UART_CMD_BREAK_SET: - dw_uart_set_break(uart_reg_ptr); - break; - case UART_CMD_BREAK_CLR: - dw_uart_clr_break(uart_reg_ptr); - break; - case UART_CMD_SET_DPS_FORMAT: - DW_UART_CHECK_EXP(param != NULL, E_PAR); - dps_ptr = (UART_DPS_FORMAT *)param; - if (dw_uart_set_dps(uart_reg_ptr, dps_ptr) == 0) { - uart_info_ptr->dps_format = *dps_ptr; - } else { - ercd = E_PAR; - } - break; - case UART_CMD_SET_HWFC: - hwfc_local = (UART_HW_FLOW_CONTROL)param; - DW_UART_CHECK_EXP(((hwfc_local >= UART_FC_NONE) && (hwfc_local <= UART_FC_BOTH)), E_PAR); - dw_uart_set_hwfc(uart_reg_ptr, hwfc_local); - uart_info_ptr->hwfc = hwfc_local; - break; - case UART_CMD_SET_TXCB: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - uart_info_ptr->uart_cbs.tx_cb = param; - break; - case UART_CMD_SET_RXCB: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - uart_info_ptr->uart_cbs.rx_cb = param; - break; - case UART_CMD_SET_ERRCB: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - uart_info_ptr->uart_cbs.err_cb = param; - break; - case UART_CMD_ABORT_TX: - dw_uart_abort_tx(uart_obj); - break; - case UART_CMD_ABORT_RX: - dw_uart_abort_rx(uart_obj); - break; - case UART_CMD_SET_TXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - } else { - dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_SND); - } - break; - case UART_CMD_SET_RXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - } else { - dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_RCV); - } - break; - case UART_CMD_SET_TXINT_BUF: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - uart_info_ptr->tx_buf = *devbuf; - uart_info_ptr->tx_buf.ofs = 0; - } else { - uart_info_ptr->tx_buf.buf = NULL; - uart_info_ptr->tx_buf.len = 0; - uart_info_ptr->tx_buf.ofs = 0; - } - break; - case UART_CMD_SET_RXINT_BUF: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - uart_info_ptr->rx_buf = *devbuf; - uart_info_ptr->rx_buf.ofs = 0; - } else { - uart_info_ptr->rx_buf.buf = NULL; - uart_info_ptr->rx_buf.len = 0; - uart_info_ptr->rx_buf.ofs = 0; - } - break; - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** - * @brief Send data through DesignWare UART - * @param[in] uart_obj Uart object structure pointer - * @param[in] data Data to send (data must be char type) - * @param[in] len Data length to send - * @retval > 0 Byte count that was successfully sent for poll method - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Can't write data to hardware due to hardware issues - */ -int32_t dw_uart_write(DEV_UART *uart_obj, const void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED); - DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS); - DW_UART_CHECK_EXP(data != NULL, E_PAR); - DW_UART_CHECK_EXP(len > 0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - const char *p_charbuf = (const char *)data; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - while (i < len) { - dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i++]); - } - ercd = i; - -error_exit: - return ercd; -} - -/** - * @brief Read data through DesignWare UART - * @param[in] uart_obj Uart object structure pointer - * @param[out] data Data that need to read (data must be char type) - * @param[in] len Data count to read - * @retval > 0 Byte count that was successfully sent for poll method - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -int32_t dw_uart_read(DEV_UART *uart_obj, void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED); - DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS); - DW_UART_CHECK_EXP(data != NULL, E_PAR); - DW_UART_CHECK_EXP(len > 0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - char *p_charbuf = (char *)data; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - while (i < len) { - p_charbuf[i++] = dw_uart_prcv_chr(uart_reg_ptr); - } - ercd = i; - -error_exit: - return ercd; -} - -/** - * @brief DesignWare UART interrupt processing routine - * @param[in] uart_obj Uart object structure pointer - * @param[in] ptr Extra information - */ -void dw_uart_isr(DEV_UART *uart_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - /* END OF ERROR CHECK */ - - uint32_t uart_int_status; /** uart interrupt status */ - volatile uint32_t temp; /** read error status to clear interrupt */ - DEV_BUFFER *buf_ptr; - char *p_charbuf; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - /** get uart interrupt status */ - uart_int_status = (uart_reg_ptr->IIR) & DW_UART_IIR_INT_ID_MASK; - - switch (uart_int_status) { - case DW_UART_IIR_MDM_STATUS: - temp = (volatile uint32_t)(uart_reg_ptr->MSR); - break; - case DW_UART_IIR_LINE_STATUS: - if (uart_info_ptr->uart_cbs.err_cb) { - uart_info_ptr->uart_cbs.err_cb(uart_info_ptr); - } - temp = (volatile uint32_t)(uart_reg_ptr->LSR); - break; - case DW_UART_IIR_XMIT_EMPTY: - buf_ptr = &(uart_info_ptr->tx_buf); - p_charbuf = (char *)buf_ptr->buf; - if (p_charbuf != NULL) { - while (dw_uart_putready(uart_reg_ptr)) { - dw_uart_putchar(uart_reg_ptr, p_charbuf[buf_ptr->ofs]); - buf_ptr->ofs++; - if (buf_ptr->ofs >= buf_ptr->len) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - if (uart_info_ptr->uart_cbs.tx_cb) { - uart_info_ptr->uart_cbs.tx_cb(uart_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - break; - } - } - } else { - if (uart_info_ptr->uart_cbs.tx_cb) { - uart_info_ptr->uart_cbs.tx_cb(uart_obj); - } - } - break; - case DW_UART_IIR_RX_TIMEOUT: - temp = dw_uart_getchar(uart_reg_ptr); - break; - case DW_UART_IIR_DATA_AVAIL: - buf_ptr = &(uart_info_ptr->rx_buf); - p_charbuf = (char *)buf_ptr->buf; - if (p_charbuf != NULL) { - while (dw_uart_getready(uart_reg_ptr)) { - p_charbuf[buf_ptr->ofs] = (char)dw_uart_getchar(uart_reg_ptr); - buf_ptr->ofs++; - if (buf_ptr->ofs >= buf_ptr->len) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - if (uart_info_ptr->uart_cbs.rx_cb) { - uart_info_ptr->uart_cbs.rx_cb(uart_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - break; - } - } - } else { - if (uart_info_ptr->uart_cbs.rx_cb) { - uart_info_ptr->uart_cbs.rx_cb(uart_obj); - } - } - break; - default: - temp = (volatile uint32_t)(uart_reg_ptr->USR); - break; - } - -error_exit: - return; -} diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/creg/creg_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/creg/creg_master.c deleted file mode 100644 index a430c870..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/creg/creg_master.c +++ /dev/null @@ -1,91 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-2.1.13 - * ========================================================================== */ - -#include -#include "device/subsystem/creg_master.h" -#include "io_config.h" -#include "apexextensions.h" - -/* determine whether there is at least a single CREG master instance */ -#ifdef IO_CREG_MST0_PRESENT -#define CREG_MASTER_DEV_PRESENT -#endif -#ifdef IO_CREG_MST1_PRESENT -#define CREG_MASTER_DEV_PRESENT -#endif -#ifdef IO_CREG_MST2_PRESENT -#define CREG_MASTER_DEV_PRESENT -#endif -#ifdef IO_CREG_MST3_PRESENT -#define CREG_MASTER_DEV_PRESENT -#endif - -#ifdef CREG_MASTER_DEV_PRESENT - -/* Addresses of CREG master instances */ -static const uint32_t creg_masters[4] = { -#ifdef IO_CREG_MST0_PRESENT - AR_IO_CREG_MST0_CTRL, -#else - 0, -#endif -#ifdef IO_CREG_MST1_PRESENT - AR_IO_CREG_MST1_CTRL, -#else - 0, -#endif -#ifdef IO_CREG_MST2_PRESENT - AR_IO_CREG_MST2_CTRL, -#else - 0, -#endif -#ifdef IO_CREG_MST3_PRESENT - AR_IO_CREG_MST3_CTRL, -#else - 0, -#endif -}; - -#define CREG_WRITE(x) _sr((unsigned)(x), (unsigned)creg_masters[dev_id]) -#define CREG_READ( ) _lr((unsigned)creg_masters[dev_id]) - -void io_creg_master_read(uint32_t dev_id, uint32_t *reg_val) -{ - *reg_val = CREG_READ(); -} - -void io_creg_master_write(uint32_t dev_id, uint32_t reg_val) -{ - CREG_WRITE(reg_val); -} - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/creg/creg_slave.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/creg/creg_slave.c deleted file mode 100644 index ef284880..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/creg/creg_slave.c +++ /dev/null @@ -1,85 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-2.1.13 - * ========================================================================== */ - -#include -#include "device/subsystem/creg_slave.h" -#include "io_config.h" -#include "apexextensions.h" - -/* determine whether there is at least a single CREG master instance */ -#ifdef IO_CREG_SLV0_PRESENT -#define CREG_SLAVE_DEV_PRESENT -#endif -#ifdef IO_CREG_SLV1_PRESENT -#define CREG_SLAVE_DEV_PRESENT -#endif -#ifdef IO_CREG_SLV2_PRESENT -#define CREG_SLAVE_DEV_PRESENT -#endif -#ifdef IO_CREG_SLV3_PRESENT -#define CREG_SLAVE_DEV_PRESENT -#endif - -#ifdef CREG_SLAVE_DEV_PRESENT - -/* Addresses of CREG slave instances */ -static const uint32_t creg_slaves[4] = { -#ifdef IO_CREG_SLV0_PRESENT - AR_IO_CREG_SLV0_OBSR, -#else - 0, -#endif -#ifdef IO_CREG_SLV1_PRESENT - AR_IO_CREG_SLV1_OBSR, -#else - 0, -#endif -#ifdef IO_CREG_SLV2_PRESENT - AR_IO_CREG_SLV2_OBSR, -#else - 0, -#endif -#ifdef IO_CREG_SLV3_PRESENT - AR_IO_CREG_SLV3_OBSR -#else - 0, -#endif -}; - -#define CREG_READ( ) _lr((unsigned)creg_slaves[dev_id]) - -void io_creg_slave_read(uint32_t dev_id, uint32_t *reg_val) -{ - *reg_val = CREG_READ(); -} - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/gpio/gpio.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/gpio/gpio.c deleted file mode 100644 index 864ba304..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/gpio/gpio.c +++ /dev/null @@ -1,417 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/gpio.h" -#include "io_config.h" -#include "apexextensions.h" - -/* EIA GPIO device registers */ -#define SWPORTA_DR (0x00) /* GPIO Port A Data Register */ -#define SWPORTA_DDR (0x04) /* GPIO Port A Data Direction Register */ -#define INTEN (0x30) /* GPIO Interrupt Enable Register */ -#define INTMASK (0x34) /* GPIO Interrupt Mask Register */ -#define INTTYPE_LEVEL (0x38) /* GPIO Interrupt Type Register */ -#define INT_POLARITY (0x3c) /* GPIO Interrupt Polarity Register */ -#define INTSTATUS (0x44) /* GPIO Interrupt Status Register */ -#define DEBOUNCE (0x48) /* GPIO Debounce Enable Register */ -#define PORTA_EOI (0x4c) /* GPIO Port A Clear Interrupt Register */ -#define EXT_PORTA (0x50) /* GPIO External Port A Register */ -#define LS_SYNC (0x60) /* GPIO Level-Sensitive Sync Enable Register */ -#define INT_BOTHEDGE (0x68) /* GPIO Both Edge Register */ -#define CLKEN (0x80) /* GPIO Clock Enable Register */ - -typedef _Interrupt void (*ISR) (); - -/* Private data structure maintained by the driver. */ -typedef struct gpio_info_struct { - uint32_t reg_base; /* base address of device register set */ - /* Callbacks */ - IO_CB_FUNC rx_cb; - uint8_t opened; - uint8_t instID; - /* Interrupt numbers and handlers */ - uint8_t vector; /* GPIO ISR vector */ - ISR isr; /* GPIO ISR */ - /* Config option */ - uint8_t enableDebounce; -} gpio_info_t, *gpio_info_pt; - -#ifdef IO_GPIO0_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO1_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO2_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO3_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_8B0_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_8B1_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_8B2_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_8B3_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_4B0_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_4B1_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_4B2_PRESENT -#define GPIO_DEV_PRESENT -#endif -#ifdef IO_GPIO_4B3_PRESENT -#define GPIO_DEV_PRESENT -#endif - -#ifdef GPIO_DEV_PRESENT - -#define GPIO_32_MAX_CNT (4) -#define GPIO_8B_MAX_CNT (4) -#define GPIO_4B_MAX_CNT (4) -#define GPIO_MAX_CNT ((GPIO_32_MAX_CNT) + (GPIO_8B_MAX_CNT) + (GPIO_4B_MAX_CNT)) - -static void gpio_ISR_proc(uint32_t dev_id); - -#ifdef IO_GPIO0_PRESENT -static _Interrupt void gpio0_ISR() -{ - gpio_ISR_proc(0); -} -#endif -#ifdef IO_GPIO1_PRESENT -static _Interrupt void gpio1_ISR() -{ - gpio_ISR_proc(1); -} -#endif -#ifdef IO_GPIO2_PRESENT -static _Interrupt void gpio2_ISR() -{ - gpio_ISR_proc(2); -} -#endif -#ifdef IO_GPIO3_PRESENT -static _Interrupt void gpio3_ISR() -{ - gpio_ISR_proc(3); -} -#endif - -#ifdef IO_GPIO_8B0_PRESENT -static _Interrupt void gpio_8B_0_ISR() -{ - gpio_ISR_proc(0 + GPIO_32_MAX_CNT); -} -#endif -#ifdef IO_GPIO_8B1_PRESENT -static _Interrupt void gpio_8B_1_ISR() -{ - gpio_ISR_proc(1 + GPIO_32_MAX_CNT); -} -#endif -#ifdef IO_GPIO_8B2_PRESENT -static _Interrupt void gpio_8B_2_ISR() -{ - gpio_ISR_proc(2 + GPIO_32_MAX_CNT); -} -#endif -#ifdef IO_GPIO_8B3_PRESENT -static _Interrupt void gpio_8B_3_ISR() -{ - gpio_ISR_proc(3 + GPIO_32_MAX_CNT); -} -#endif - -#ifdef IO_GPIO_4B0_PRESENT -static _Interrupt void gpio_4B_0_ISR() -{ - gpio_ISR_proc(0 + GPIO_32_MAX_CNT + GPIO_8B_MAX_CNT); -} -#endif -#ifdef IO_GPIO_4B1_PRESENT -static _Interrupt void gpio_4B_1_ISR() -{ - gpio_ISR_proc(1 + GPIO_32_MAX_CNT + GPIO_8B_MAX_CNT); -} -#endif -#ifdef IO_GPIO_4B2_PRESENT -static _Interrupt void gpio_4B_2_ISR() -{ - gpio_ISR_proc(2 + GPIO_32_MAX_CNT + GPIO_8B_MAX_CNT); -} -#endif -#ifdef IO_GPIO_4B3_PRESENT -static _Interrupt void gpio_4B_3_ISR() -{ - gpio_ISR_proc(3 + GPIO_32_MAX_CNT + GPIO_8B_MAX_CNT); -} -#endif - -/* GPIO devices private data structures */ -static gpio_info_pt gpio_handles[GPIO_MAX_CNT] = { 0 }; - -static gpio_info_t gpio_devs[] = { -#ifdef IO_GPIO0_PRESENT - { .instID = IO_GPIO_DEV_ID(0, 32), - .reg_base = AR_IO_GPIO0_SWPORTA_DR, - .vector = IO_GPIO0_INT_INTR_FLAG, - .isr = gpio0_ISR, - .enableDebounce = IO_GPIO0_DEBOUNCE }, -#endif -#ifdef IO_GPIO1_PRESENT - { .instID = IO_GPIO_DEV_ID(1, 32), - .reg_base = AR_IO_GPIO1_SWPORTA_DR, - .vector = IO_GPIO1_INT_INTR_FLAG, - .isr = gpio1_ISR, - .enableDebounce = IO_GPIO1_DEBOUNCE }, -#endif -#ifdef IO_GPIO2_PRESENT - { .instID = IO_GPIO_DEV_ID(2, 32), - .reg_base = AR_IO_GPIO2_SWPORTA_DR, - .vector = IO_GPIO2_INT_INTR_FLAG, - .isr = gpio2_ISR, - .enableDebounce = IO_GPIO2_DEBOUNCE }, -#endif -#ifdef IO_GPIO3_PRESENT - { .instID = IO_GPIO_DEV_ID(3, 32), - .reg_base = AR_IO_GPIO3_SWPORTA_DR, - .vector = IO_GPIO3_INT_INTR_FLAG, - .isr = gpio3_ISR, - .enableDebounce = IO_GPIO3_DEBOUNCE }, -#endif - -#ifdef IO_GPIO_8B0_PRESENT - { .instID = IO_GPIO_DEV_ID(0, 8), - .reg_base = AR_IO_GPIO_8B0_SWPORTA_DR, - .vector = IO_GPIO_8B0_INT_INTR_FLAG, - .isr = gpio_8B_0_ISR, - .enableDebounce = IO_GPIO_8B0_DEBOUNCE }, -#endif -#ifdef IO_GPIO_8B1_PRESENT - { .instID = IO_GPIO_DEV_ID(1, 8), - .reg_base = AR_IO_GPIO_8B1_SWPORTA_DR, - .vector = IO_GPIO_8B1_INT_INTR_FLAG, - .isr = gpio_8B_1_ISR, - .enableDebounce = IO_GPIO_8B1_DEBOUNCE }, -#endif -#ifdef IO_GPIO_8B2_PRESENT - { .instID = IO_GPIO_DEV_ID(2, 8), - .reg_base = AR_IO_GPIO_8B2_SWPORTA_DR, - .vector = IO_GPIO_8B2_INT_INTR_FLAG, - .isr = gpio_8B_2_ISR, - .enableDebounce = IO_GPIO_8B2_DEBOUNCE }, -#endif -#ifdef IO_GPIO_8B3_PRESENT - { .instID = IO_GPIO_DEV_ID(3, 8), - .reg_base = AR_IO_GPIO_8B3_SWPORTA_DR, - .vector = IO_GPIO_8B3_INT_INTR_FLAG, - .isr = gpio_8B_3_ISR, - .enableDebounce = IO_GPIO_8B3_DEBOUNCE }, -#endif - -#ifdef IO_GPIO_4B0_PRESENT - { .instID = IO_GPIO_DEV_ID(0, 4), - .reg_base = AR_IO_GPIO_4B0_SWPORTA_DR, - .vector = IO_GPIO_4B0_INT_INTR_FLAG, - .isr = gpio_4B_0_ISR, - .enableDebounce = IO_GPIO_4B0_DEBOUNCE }, -#endif -#ifdef IO_GPIO_4B1_PRESENT - { .instID = IO_GPIO_DEV_ID(1, 4), - .reg_base = AR_IO_GPIO_4B1_SWPORTA_DR, - .vector = IO_GPIO_4B1_INT_INTR_FLAG, - .isr = gpio_4B_1_ISR, - .enableDebounce = IO_GPIO_4B1_DEBOUNCE }, -#endif -#ifdef IO_GPIO_4B2_PRESENT - { .instID = IO_GPIO_DEV_ID(2, 4), - .reg_base = AR_IO_GPIO_4B2_SWPORTA_DR, - .vector = IO_GPIO_4B2_INT_INTR_FLAG, - .isr = gpio_4B_2_ISR, - .enableDebounce = IO_GPIO_4B2_DEBOUNCE }, -#endif -#ifdef IO_GPIO_4B3_PRESENT - { .instID = IO_GPIO_DEV_ID(3, 4), - .reg_base = AR_IO_GPIO_4B3_SWPORTA_DR, - .vector = IO_GPIO_4B3_INT_INTR_FLAG, - .isr = gpio_4B_3_ISR, - .enableDebounce = IO_GPIO_4B3_DEBOUNCE }, -#endif - - { .instID = GPIO_MAX_CNT } -}; - -#define REG_WRITE(reg, x) _sr((unsigned)(x), (unsigned)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((unsigned)(dev->reg_base + reg)) - -uint32_t io_gpio_open(uint32_t dev_id) -{ - uint32_t h = 0; - gpio_info_pt dev; - - h = 0; - while ((gpio_devs[h].instID != dev_id) - && (gpio_devs[h].instID != GPIO_MAX_CNT)) { - h++; - } - if ((gpio_devs[h].instID == GPIO_MAX_CNT) || (0 != gpio_handles[dev_id])) { /* dev_id not part of design, or still open */ - return 1; - } - gpio_handles[dev_id] = &gpio_devs[h]; - dev = gpio_handles[dev_id]; - - dev->opened = 1; - /* enable the clock and enable synchronization */ - REG_WRITE(CLKEN, 0x1); - REG_WRITE(LS_SYNC, 0x1); - _setvecti(dev->vector, dev->isr); - - return 0; -} - -void io_gpio_close(uint32_t dev_id) -{ - gpio_info_pt dev = gpio_handles[dev_id]; - - REG_WRITE(INTEN, 0x0); - REG_WRITE(LS_SYNC, 0x0); - REG_WRITE(CLKEN, 0x0); - _setvecti(dev->vector, NULL); - dev->rx_cb = NULL; - dev->opened = 0; - gpio_handles[dev_id] = 0; -} - -void io_gpio_read(uint32_t dev_id, uint32_t *data) -{ - gpio_info_pt dev = gpio_handles[dev_id]; - - *data = REG_READ(EXT_PORTA); -} - -void io_gpio_write(uint32_t dev_id, uint32_t data) -{ - gpio_info_pt dev = gpio_handles[dev_id]; - - REG_WRITE(SWPORTA_DR, data); -} - -void io_gpio_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - gpio_info_pt dev = gpio_handles[dev_id]; - - switch (cmd) { - case IO_SET_CB_RX: - dev->rx_cb = ((io_cb_t *) arg)->cb; - break; - - case IO_GPIO_SET_DIRECTION: - REG_WRITE(SWPORTA_DDR, *((uint32_t *) arg)); - break; - - case IO_GPIO_SET_INT_ENABLE: - REG_WRITE(INTEN, *((uint32_t *) arg)); - break; - - case IO_GPIO_GET_INT_ENABLE: - *((uint32_t *) arg) = REG_READ(INTEN); - break; - - case IO_GPIO_SET_INT_MASK: - REG_WRITE(INTMASK, *((uint32_t *) arg)); - break; - - case IO_GPIO_GET_INT_MASK: - *((uint32_t *) arg) = REG_READ(INTMASK); - break; - - case IO_GPIO_SET_INT_TYPE: - REG_WRITE(INTTYPE_LEVEL, *((uint32_t *) arg)); - break; - - case IO_GPIO_SET_INT_POLARITY: - REG_WRITE(INT_POLARITY, *((uint32_t *) arg)); - break; - - case IO_GPIO_SET_INT_BOTHEDGE: - REG_WRITE(INT_BOTHEDGE, *((uint32_t *) arg)); - break; - - case IO_GPIO_SET_DEBOUNCE: - if (dev->enableDebounce == 1) { - REG_WRITE(DEBOUNCE, *((uint32_t *) arg)); - } - break; - - case IO_GPIO_GET_DIRECTION: - *((uint32_t *) arg) = REG_READ(SWPORTA_DDR); - break; - - case IO_GPIO_GET_GPO: - *((uint32_t *) arg) = REG_READ(SWPORTA_DR); - break; - - default: - break; - } -} - -static void gpio_ISR_proc(uint32_t dev_id) -{ - gpio_info_pt dev = gpio_handles[dev_id]; - uint32_t status = REG_READ(INTSTATUS); - - if (!status) { - return; /* Spurious interrupts. */ - - } - if (_Usually(NULL != dev->rx_cb)) { - dev->rx_cb(status); - } - - REG_WRITE(PORTA_EOI, status); /* clear status register. */ -} - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/gpio/ss_gpio.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/gpio/ss_gpio.c deleted file mode 100644 index f6eff574..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/gpio/ss_gpio.c +++ /dev/null @@ -1,210 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/* the wrapper of subsystem gpio driver */ - -#include "embARC_error.h" -#include "embARC_toolchain.h" - -#include "device/subsystem/gpio.h" -#include "device/subsystem/ss_gpio.h" - -int32_t ss_gpio_open(SS_GPIO_DEV_CONTEXT *ctx, uint32_t dir) -{ - DEV_GPIO_INFO *info = ctx->info; - int32_t ret = E_OK; - io_cb_t cb; - - info->opn_cnt++; - - if (info->opn_cnt > 1) { /* opened before */ - if (dir == info->direction) { /* direction is the same */ - return E_OK; - } else { /* open with different direction */ - return E_OPNED; - } - } - - if (io_gpio_open(ctx->dev_id)) { - return E_SYS; - } - - info->direction = dir; - info->method = 0; - ctx->int_bit_type = 0; - ctx->int_bit_polarity = 0; - ctx->int_bit_debounce = 0; - cb.cb = (IO_CB_FUNC)ctx->int_cb; - io_gpio_ioctl(ctx->dev_id, IO_SET_CB_RX, &cb); - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_INT_ENABLE, &info->method); - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_DIRECTION, &info->direction); - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_INT_POLARITY, &ctx->int_bit_polarity); - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_DEBOUNCE, &ctx->int_bit_debounce); - - int_enable(ctx->intno); - - return ret; -} - -int32_t ss_gpio_close(SS_GPIO_DEV_CONTEXT *ctx) -{ - DEV_GPIO_INFO *info = ctx->info; - - info->opn_cnt--; - - if (info->opn_cnt == 0) { - io_gpio_close(ctx->dev_id); - int_disable(ctx->intno); - } else { - return E_OPNED; - } - - return E_OK; -} - -int32_t ss_gpio_control(SS_GPIO_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param) -{ - int32_t ret = E_OK; - DEV_GPIO_INFO *info = ctx->info; - DEV_GPIO_INT_CFG *cfg = (DEV_GPIO_INT_CFG *)param; - DEV_GPIO_BIT_ISR *isr = (DEV_GPIO_BIT_ISR *)param; - uint32_t mask; - - switch (ctrl_cmd) { - case GPIO_CMD_SET_BIT_DIR_INPUT: - case GPIO_CMD_SET_BIT_DIR_OUTPUT: - if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_OUTPUT) { - info->direction |= ((uint32_t)param); - } else { - info->direction &= ~((uint32_t)param); - } - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_DIRECTION, &(info->direction)); - break; - case GPIO_CMD_GET_BIT_DIR: - *((uint32_t *) param) = info->direction; - break; - - case GPIO_CMD_ENA_BIT_INT: - case GPIO_CMD_DIS_BIT_INT: - if (ctrl_cmd == GPIO_CMD_ENA_BIT_INT) { - info->method |= ((uint32_t)param); - } else { - info->method &= ~((uint32_t)param); - } - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_INT_ENABLE, &(info->method)); - if (info->method) { - int_enable(ctx->intno); - } else { - int_disable(ctx->intno); - } - break; - - case GPIO_CMD_GET_BIT_MTHD: - io_gpio_ioctl(ctx->dev_id, IO_GPIO_GET_INT_ENABLE, &(info->method)); - *((uint32_t *) param) = info->method; - break; - case GPIO_CMD_SET_BIT_INT_CFG: - mask = cfg->int_bit_mask; - ctx->int_bit_type &= ~(mask); - ctx->int_bit_type |= cfg->int_bit_type; - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_INT_TYPE, &ctx->int_bit_type); - - ctx->int_bit_polarity &= ~(mask); - ctx->int_bit_polarity |= cfg->int_bit_polarity; - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_INT_POLARITY, &ctx->int_bit_polarity); - - cfg->int_bit_debounce &= mask; - ctx->int_bit_debounce &= ~(mask); - ctx->int_bit_debounce |= cfg->int_bit_debounce; - io_gpio_ioctl(ctx->dev_id, IO_GPIO_SET_DEBOUNCE, &ctx->int_bit_debounce); - break; - - case GPIO_CMD_GET_BIT_INT_CFG: - cfg->int_bit_type = ctx->int_bit_type & cfg->int_bit_mask; - cfg->int_bit_polarity = ctx->int_bit_polarity & cfg->int_bit_mask; - cfg->int_bit_debounce = ctx->int_bit_debounce & cfg->int_bit_mask; - break; - - case GPIO_CMD_SET_BIT_ISR: - if (isr->int_bit_ofs < ctx->width) { - ctx->handlers[isr->int_bit_ofs] = isr->int_bit_handler; - } else { - ret = E_PAR; - } - break; - - case GPIO_CMD_GET_BIT_ISR: - if (isr->int_bit_ofs < ctx->width) { - isr->int_bit_handler = ctx->handlers[isr->int_bit_ofs]; - } else { - ret = E_PAR; - } - break; - default: - ret = E_NOSPT; - break; - } - - return ret; -} - -int32_t ss_gpio_write(SS_GPIO_DEV_CONTEXT *ctx, uint32_t val, uint32_t mask) -{ - uint32_t temp_val; - - io_gpio_read(ctx->dev_id, &temp_val); - temp_val &= (~mask); - val &= mask; - io_gpio_write(ctx->dev_id, temp_val | val); - - return 0; -} - -int32_t ss_gpio_read(SS_GPIO_DEV_CONTEXT *ctx, uint32_t *val, uint32_t mask) -{ - uint32_t raw; - - io_gpio_read(ctx->dev_id, &raw); - *val = raw & mask; - - return 0; -} - -void ss_gpio_int_cb(SS_GPIO_DEV_CONTEXT *ctx, void *param) -{ - DEV_GPIO_INFO *info = ctx->info; - uint32_t i; - - for (i = 0; i < ctx->width; i++) { - if ((uint32_t)param & (1 << i) && ctx->handlers[i]) { - ctx->handlers[i](info); - } - } -} diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/i2s_rx_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/i2s_rx_master.c deleted file mode 100644 index 7d680f0b..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/i2s_rx_master.c +++ /dev/null @@ -1,522 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/i2s_rx_master.h" -#include "io_config.h" -#include "apexextensions.h" - -/* I2S Rx Master device registers */ -#define I2S_IER 0x000 -#define I2S_IRER 0x004 -#define I2S_CER 0x00c -#define I2S_CCR 0x010 -#define I2S_RXFFR 0x014 -#define I2S_LRBR0 0x020 -#define I2S_RRBR0 0x024 -#define I2S_RER0 0x028 -#define I2S_RCR0 0x030 // Receive configuration register -#define I2S_ISR0 0x038 // Interrupt status register -#define I2S_IMR0 0x03c // Interrupt mask register -#define I2S_ROR0 0x040 -#define I2S_RFCR0 0x048 -#define I2S_RFF0 0x050 -#define I2S_RXDMA 0x1c0 - -/* I2S Rx Master device specific macros */ -#define I2S_RX_MASTER_DMA_CTRL (0xa0000077) /* am=b10, i=b1, dw/inc=b011, dtt=b10, r=b1, op=b11 */ -#define I2S_RX_MASTER_DMA_CTRL_SIZE_POS (8) -#define I2S_RX_MASTER_DMA_CTRL_XFER_POS (21) - -#define DMA_NONE (0xff) - -typedef _Interrupt void (*ISR) (); - -typedef struct i2s_rx_master_info_struct { - /* I2S Rx master configuration settings */ - const uint32_t reg_base; // base address of device register set - const uint8_t instID; // module instance ID - const uint16_t fifo_size; // FIFO depth - const uint16_t dmachanid; // DMA channel ID - /* I2S data buffer related fields */ - uint32_t xfr_len; // number of samples transferred in current buffer - uint32_t xfr_started; // transfer started flag - uint32_t *buffer[2]; // two pointers to the user' buffers - uint32_t *bufsize[2]; // two sizes of user buffers - volatile uint32_t usr_cnt; // user' buffer access counter (incremented from read service) - volatile uint32_t sys_cnt; // system' buffer access counter (incremented from ISR) -#ifdef __Xdmac - _Uncached uint32_t *dmadescriptor; // pointer to the DMA descriptor location -#endif - /* User' callbacks */ - IO_CB_FUNC rx_cb; // user' RX completion callback - IO_CB_FUNC err_cb; // user' error callback - /* Interrupt numbers and handlers */ - const uint8_t rx_vector; // RX interrupt vector number - const uint8_t err_vector; // RX Error inetrrupt vector number - ISR rx_isr; // I2S data available interrupt handler - ISR err_isr; // I2S FIFO overrun interrupt handler -} i2s_rx_master_info_t, *i2s_rx_master_info_pt; - -#ifdef IO_I2S_RX_MST0_PRESENT -#define I2S_RX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_RX_MST1_PRESENT -#define I2S_RX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_RX_MST2_PRESENT -#define I2S_RX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_RX_MST3_PRESENT -#define I2S_RX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_RX_MST4_PRESENT -#define I2S_RX_MASTER_DEV_PRESENT -#endif - -#ifdef I2S_RX_MASTER_DEV_PRESENT - -#define I2S_RX_MASTER_MAX_CNT (4) - -static void i2s_rx_master_rx_ISR_proc(uint32_t dev_id); -static void i2s_rx_master_err_ISR_proc(uint32_t dev_id); - -#ifdef IO_I2S_RX_MST0_PRESENT -static _Interrupt void i2s_rx_master0_rx_ISR() -{ - i2s_rx_master_rx_ISR_proc(0); -} - -static _Interrupt void i2s_rx_master0_err_ISR() -{ - i2s_rx_master_err_ISR_proc(0); -} -#endif -#ifdef IO_I2S_RX_MST1_PRESENT -static _Interrupt void i2s_rx_master1_rx_ISR() -{ - i2s_rx_master_rx_ISR_proc(1); -} - -static _Interrupt void i2s_rx_master1_err_ISR() -{ - i2s_rx_master_err_ISR_proc(1); -} -#endif -#ifdef IO_I2S_RX_MST2_PRESENT -static _Interrupt void i2s_rx_master2_rx_ISR() -{ - i2s_rx_master_rx_ISR_proc(2); -} - -static _Interrupt void i2s_rx_master2_err_ISR() -{ - i2s_rx_master_err_ISR_proc(2); -} -#endif -#ifdef IO_I2S_RX_MST3_PRESENT - -static _Interrupt void i2s_rx_master3_rx_ISR() -{ - i2s_rx_master_rx_ISR_proc(3); -} - -static _Interrupt void i2s_rx_master3_err_ISR() -{ - i2s_rx_master_err_ISR_proc(3); -} -#endif - -/* I2S RX Master devices private data structures */ -static i2s_rx_master_info_pt i2s_rx_master_handles[I2S_RX_MASTER_MAX_CNT] = -{ 0 }; -#ifdef __Xdmac -static __attribute__ ((aligned(32))) -_Uncached uint32_t i2s_rx_master_dma_descriptors[8 * - I2S_RX_MASTER_MAX_CNT]; -#endif - -static i2s_rx_master_info_t i2s_rx_master_devs[] = { -#ifdef IO_I2S_RX_MST0_PRESENT - { .instID = 0, - .reg_base = AR_IO_I2S_RX_MST0_IER, - .rx_vector = IO_I2S_RX_MST0_INT_RX_AVAIL, - .err_vector = IO_I2S_RX_MST0_INT_ERR, - .rx_isr = i2s_rx_master0_rx_ISR, - .err_isr = i2s_rx_master0_err_ISR, -#ifdef IO_I2S_RX_MST0_DMA - .dmachanid = IO_I2S_RX_MST0_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_RX_MST0_FS }, -#endif -#ifdef IO_I2S_RX_MST1_PRESENT - { .instID = 1, - .reg_base = AR_IO_I2S_RX_MST1_IER, - .rx_vector = IO_I2S_RX_MST1_INT_RX_AVAIL, - .err_vector = IO_I2S_RX_MST1_INT_ERR, - .rx_isr = i2s_rx_master1_rx_ISR, - .err_isr = i2s_rx_master1_err_ISR, -#ifdef IO_I2S_RX_MST1_DMA - .dmachanid = IO_I2S_RX_MST1_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_RX_MST1_FS }, -#endif -#ifdef IO_I2S_RX_MST2_PRESENT - { .instID = 2, - .reg_base = AR_IO_I2S_RX_MST2_IER, - .rx_vector = IO_I2S_RX_MST2_INT_RX_AVAIL, - .err_vector = IO_I2S_RX_MST2_INT_ERR, - .rx_isr = i2s_rx_master2_rx_ISR, - .err_isr = i2s_rx_master2_err_ISR, -#ifdef IO_I2S_RX_MST2_DMA - .dmachanid = IO_I2S_RX_MST2_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_RX_MST2_FS }, -#endif -#ifdef IO_I2S_RX_MST3_PRESENT - { .instID = 3, - .reg_base = AR_IO_I2S_RX_MST3_IER, - .rx_vector = IO_I2S_RX_MST3_INT_RX_AVAIL, - .err_vector = IO_I2S_RX_MST3_INT_ERR, - .rx_isr = i2s_rx_master3_rx_ISR, - .err_isr = i2s_rx_master3_err_ISR, -#ifdef IO_I2S_RX_MST3_DMA - .dmachanid = IO_I2S_RX_MST3_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_RX_MST3_FS }, -#endif - { .instID = I2S_RX_MASTER_MAX_CNT } -}; - -#define REG_WRITE(reg, x) _sr((uint32_t)((x)), (uint32_t)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((uint32_t)(dev->reg_base + (reg))) - -/* API functions */ -uint32_t io_i2s_rx_master_open(uint32_t dev_id) -{ - i2s_rx_master_info_pt dev; - uint32_t h = 0; - - /* check device descriptor availability */ - while ((i2s_rx_master_devs[h].instID != dev_id) - && (i2s_rx_master_devs[h].instID != I2S_RX_MASTER_MAX_CNT)) { - h++; - } - if ((i2s_rx_master_devs[h].instID == I2S_RX_MASTER_MAX_CNT) || (0 != i2s_rx_master_handles[dev_id])) { /* dev_id not part of design, or still open */ - return 1; - } - i2s_rx_master_handles[dev_id] = &i2s_rx_master_devs[h]; - dev = i2s_rx_master_handles[dev_id]; - - /* initialize driver internal variables */ - dev->xfr_started = 0; // clear transfer started flag - dev->xfr_len = 0; // clear transfer length - dev->usr_cnt = dev->sys_cnt = 0; // reset buffer access counters - -#ifdef __Xdmac - /* initialize DMA descriptors */ - dev->dmadescriptor = &i2s_rx_master_dma_descriptors[8 * h]; - - if (dev->dmachanid != DMA_NONE) { - dev->dmadescriptor[0] = dev->dmadescriptor[4] = 0; - dev->dmadescriptor[1] = dev->dmadescriptor[5] = - dev->reg_base + I2S_RXDMA; - dev->dmadescriptor[2] = dev->dmadescriptor[6] = 0; - dev->dmadescriptor[3] = (uint32_t) &(dev->dmadescriptor[4]); - dev->dmadescriptor[7] = (uint32_t) &(dev->dmadescriptor[0]); - - /* assign DMA interrupt handlers */ - _setvecti(dev->err_vector, dev->err_isr); - - _setvecti(DMAC_INT_BASE + dev->dmachanid, dev->rx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmachanid, dev->err_isr); - } else { -#endif - /* assign non DMA interrupt handlers */ - _setvecti(dev->rx_vector, dev->rx_isr); - _setvecti(dev->err_vector, dev->err_isr); -#ifdef __Xdmac -} -#endif - - REG_WRITE(I2S_IER, 0x01); // I2S: enable device - - return (0); -} - -void io_i2s_rx_master_close(uint32_t dev_id) -{ - i2s_rx_master_info_pt dev = i2s_rx_master_handles[dev_id]; - - /* reset I2S hardware */ - REG_WRITE(I2S_IMR0, 0x03); // mask RX interrupts - REG_WRITE(I2S_RER0, 0x01); // reset channel enable to default (1) - REG_WRITE(I2S_CER, 0x00); // disable clk - REG_WRITE(I2S_IRER, 0x00); // disable receive block - REG_WRITE(I2S_RCR0, 0x02); // reset wlen to default (2) - REG_WRITE(I2S_RFCR0, 0x00); // reset threshold - REG_WRITE(I2S_IER, 0x00); // disable device and flushes fifo - -#ifdef __Xdmac - /* reset DMA channel */ - _dma_chan_enable((0x1 << dev->dmachanid), 0); // aux-DMA channel reset bug fix - _dma_chan_reset(0x1 << dev->dmachanid); - /* deinitialize DMA interrupt handlers */ - _setvecti(DMAC_INT_BASE + dev->dmachanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmachanid, NULL); -#endif - /* deinitialize non DMA interrupt handlers */ - _setvecti(dev->rx_vector, NULL); - _setvecti(dev->err_vector, NULL); - - /* reset driver internal variables */ - dev->rx_cb = NULL; - dev->err_cb = NULL; - dev->xfr_started = 0; - - /* reset device handler */ - i2s_rx_master_handles[dev_id] = 0; -} - -void io_i2s_rx_master_read(uint32_t dev_id, uint32_t *data, - uint32_t *size) -{ - i2s_rx_master_info_pt dev = i2s_rx_master_handles[dev_id]; - uint32_t idx = dev->usr_cnt; // copy user access counter to the temporary variable - - if (((idx - dev->sys_cnt) != 2) && (*size != 0)) { - idx = idx & 0x0001; // current index in dev->buffer[] & dev->bufsize[] -#ifdef __Xdmac - if (dev->dmachanid != DMA_NONE) { - - uint32_t burst_size = (REG_READ(I2S_RFCR0) + 1) << 1; // actual FIFO trigger level - uint32_t xfer_size = (*size) << 2; // transfer size in bytes (ToDo: limited by 8KB) - idx = idx << 2; // calculate available buffer' index - - /* DMA: update DMACTRL and DMADAR part of descriptor */ - dev->dmadescriptor[idx + 0] = - I2S_RX_MASTER_DMA_CTRL | - (burst_size << I2S_RX_MASTER_DMA_CTRL_XFER_POS) | - ((xfer_size - 1) << I2S_RX_MASTER_DMA_CTRL_SIZE_POS); - dev->dmadescriptor[idx + 2] = (uint32_t) data + xfer_size - 2; - - if (dev->xfr_started == 0) { /* I2S transfer not yet started -> init DMA and I2S Rx */ - dev->xfr_started = 1; - - REG_WRITE(I2S_RXFFR, 0x01); // I2S: reset RX FIFO - REG_WRITE(I2S_RFF0, 0x01); // I2S: flush RX FIFO - REG_WRITE(I2S_CER, 0x01); // I2S: start the clock - REG_WRITE(I2S_IRER, 0x01); // I2S: enable receive block - REG_WRITE(I2S_IMR0, ~0x02); // I2S: Unmask RX overrun interrupt - - if (dev->dmachanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmachanid, &(dev->dmadescriptor[0])); // dev->dmaidx must be 0 !!! - } else { - _dma_chan_desc_aux(dev->dmachanid, &(dev->dmadescriptor[0])); // dev->dmaidx must be 0 !!! - } - - /* Start DMA channel / renew descriptor */ - _dma_chan_enable((0x1 << dev->dmachanid), 1); - } - } else { -#endif /* __Xdmac */ - /* Update data buffer parameters */ - dev->buffer[idx] = data; - dev->bufsize[idx] = size; - - if (dev->xfr_started == 0) { /* I2S transfer not yet started -> init I2S Rx */ - dev->xfr_started = 1; - - /* Start I2S non DMA interrupt flow */ - REG_WRITE(I2S_RXFFR, 0x01); // I2S: reset RX FIFO - REG_WRITE(I2S_RFF0, 0x01); // I2S: flush RX FIFO - REG_WRITE(I2S_CER, 0x01); // I2S: start the clock - REG_WRITE(I2S_IRER, 0x01); // I2S: enable receive block - REG_WRITE(I2S_IMR0, ~0x03); // I2S: Unmask all RX interrupts - } -#ifdef __Xdmac - } -#endif /* __Xdmac */ - - dev->usr_cnt++; // update user' buffer access counter - } -} - -void io_i2s_rx_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - i2s_rx_master_info_pt dev = i2s_rx_master_handles[dev_id]; - - switch (cmd) { - case IO_SET_CB_RX: - dev->rx_cb = ((io_cb_t *) arg)->cb; - break; - - case IO_SET_CB_ERR: - dev->err_cb = ((io_cb_t *) arg)->cb; - break; - - case IO_I2S_RX_MASTER_SET_SAMPLE_WIDTH: - /* channel must be disabled before programming I2S_RCR0 */ - REG_WRITE(I2S_RCR0, (*(uint32_t *) arg)); - break; - - case IO_I2S_RX_MASTER_SET_FIFO_THRESHOLD: - /* channel must be disabled before programming I2S_RFCR0 */ - REG_WRITE(I2S_RFCR0, (*(uint32_t *) arg)); - break; - - case IO_I2S_RX_MASTER_SET_BITCLOCK: - REG_WRITE(I2S_CER, *((uint32_t *) arg)); - break; - - default: - break; - } -} - -static uint32_t i2s_rx_master_read_samples(uint32_t dev_id, - uint32_t *count) -{ - i2s_rx_master_info_pt dev = i2s_rx_master_handles[dev_id]; - uint32_t free_cnt = 0; - - if (dev->usr_cnt == dev->sys_cnt) { /* no more data buffer available (buffer underflow error) */ - /* if no buffer will be available until FIFO is full then error callback will be called from error ISR */ - return (1); - } else { - uint32_t idx = dev->sys_cnt & 0x0001; - uint32_t *buff = dev->buffer[idx]; - uint32_t *size = dev->bufsize[idx]; - - free_cnt = (*size - dev->xfr_len); - if (*count <= free_cnt) { /* enough space in buffer[0] */ - free_cnt = *count; - *count = 0; - } else { /* *count > free_cnt: there will be samples remaining for the next buffer */ - *count -= free_cnt; - } - /* fill current buffer */ - for (int32_t i = 0; i != free_cnt; i++) { - buff[dev->xfr_len + i] = REG_READ(I2S_LRBR0); - buff[dev->xfr_len + i] |= (REG_READ(I2S_RRBR0) << 16); - } - dev->xfr_len += free_cnt; - - /* if current buffer is full: rx callback, and increment system counter */ - if (dev->xfr_len == *size) { - dev->sys_cnt++; - dev->xfr_len = 0; - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - } - } - - return (0); -} - -/* I2S RX data available interrupt handler */ -static void i2s_rx_master_rx_ISR_proc(uint32_t dev_id) -{ - i2s_rx_master_info_pt dev = i2s_rx_master_handles[dev_id]; - uint32_t sample_cnt = 0; - uint32_t error = 0; - - /* Rx FIFO trigger level reached - data available interrupt */ -#ifdef __Xdmac - if (dev->dmachanid == DMA_NONE) { /* DMA either disabled or does not exist */ -#endif /* __Xdmac */ - - sample_cnt = REG_READ(I2S_RFCR0) + 1; // actual FIFO trigger level - - while (sample_cnt != 0) { - error = i2s_rx_master_read_samples(dev_id, &sample_cnt); - if (error != 0) { /* buffer underrun - no user' buffer left to receive data */ - REG_WRITE(I2S_IMR0, 0x0001); // I2S: mask RXDA interrupt - break; - } - } - -#ifdef __Xdmac -} else { /* DMA enabled for I2S peripheral */ - if (++dev->sys_cnt == dev->usr_cnt) { /* no data buffers left - disable dma channel and mask data available interrupt */ - _dma_chan_enable((0x1 << dev->dmachanid), 0); - } else { - // update channel descriptor - _dma_chan_enable((0x1 << dev->dmachanid), 1); - } - - if (NULL != dev->rx_cb) { /* call for Rx callback if any */ - dev->rx_cb(dev_id); - } - - _dma_int_clear((0x1 << dev->dmachanid)); // clear DMA interrupt flag -} -#endif /* __Xdmac */ -} - -/* I2S RX error (FIFO overflow) interrupt handler */ -static void i2s_rx_master_err_ISR_proc(uint32_t dev_id) -{ - i2s_rx_master_info_pt dev = i2s_rx_master_handles[dev_id]; - - /* Rx FIFO overrun case */ -#ifdef __Xdmac - if (dev->dmachanid != DMA_NONE) { - /* DMA: disable DMA channel */ - _dma_chan_enable((0x1 << dev->dmachanid), 0); - _dma_int_clear((0x1 << dev->dmachanid)); - } -#endif - - /* I2S: stop I2S device */ - REG_WRITE(I2S_IMR0, 0x03); // I2S: mask RX interrupts - REG_WRITE(I2S_CER, 0x00); // I2S: disable clk - REG_WRITE(I2S_IER, 0x00); // I2S: disable device - - /* call error callback if any */ - if (NULL != dev->err_cb) { - dev->err_cb(dev_id); - } -} - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/i2s_tx_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/i2s_tx_master.c deleted file mode 100644 index d25d82e9..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/i2s_tx_master.c +++ /dev/null @@ -1,531 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/i2s_tx_master.h" -#include "io_config.h" -#include "apexextensions.h" - -/* I2S Tx Master device registers */ -#define I2S_IER 0x000 -#define I2S_ITER 0x008 -#define I2S_CER 0x00c -#define I2S_CCR 0x010 -#define I2S_TXFFR 0x018 -#define I2S_LTHR 0x020 -#define I2S_RTHR 0x024 -#define I2S_TER 0x02C -#define I2S_TCR 0x034 // Transmit configuration register -#define I2S_ISR 0x038 // Interrupt status register -#define I2S_IMR 0x03c // Interrupt mask register -#define I2S_TOR 0x044 -#define I2S_TFCR 0x04c -#define I2S_TFF 0x054 -#define I2S_TXDMA 0x1c8 - -/* I2S Tx Master device specific macros */ -#define I2S_TX_MASTER_DMA_CTRL (0x6000006F) /* am=b01, i=b1, dw/inc=b011, dtt=b01, r=b1, op=b11 */ -#define I2S_TX_MASTER_DMA_CTRL_SIZE_POS (8) -#define I2S_TX_MASTER_DMA_CTRL_XFER_POS (21) - -#define DMA_NONE (0xff) - -typedef _Interrupt void (*ISR) (); - -typedef struct i2s_tx_master_info_struct { - /* I2S peripheral configuration values */ - const uint32_t reg_base; // base address of device register set - const uint8_t instID; // I2S module instance ID - const uint16_t fifo_size; // FIFO depth - const uint16_t dmachanid; // DMA channel ID - /* I2S data buffer related fields */ - uint32_t xfr_len; // number of transferred samples in current buffer - uint32_t xfr_started; // I2S transfer started flag (used for nonDMA xfer) - uint32_t *buffer[2]; // two pointers to the user data buffers - uint32_t *bufsize[2]; // two pointers to the user data buffer sizes - volatile uint32_t sys_cnt; // read access buffer counter (incremented by ISR) - volatile uint32_t usr_cnt; // write access buffer counter (incremented from write service) -#ifdef __Xdmac - _Uncached uint32_t *dmadescriptor; // pointer to DMA descriptors location -#endif - /* User callbacks */ - IO_CB_FUNC tx_cb; // user' TX completion callback - IO_CB_FUNC err_cb; // user' error callback - /* Interrupt numbers and handlers */ - const uint8_t tx_vector; // TX interrupt vector number - const uint8_t err_vector; // Error interrupt vector number - ISR tx_isr; // I2S data available ISRs - ISR err_isr; // I2S FIFO overrun ISRs -} i2s_tx_master_info_t, *i2s_tx_master_info_pt; - -#ifdef IO_I2S_TX_MST0_PRESENT -#define I2S_TX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_TX_MST1_PRESENT -#define I2S_TX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_TX_MST2_PRESENT -#define I2S_TX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_TX_MST3_PRESENT -#define I2S_TX_MASTER_DEV_PRESENT -#endif -#ifdef IO_I2S_TX_MST4_PRESENT -#define I2S_TX_MASTER_DEV_PRESENT -#endif - -#ifdef I2S_TX_MASTER_DEV_PRESENT - -#define I2S_TX_MASTER_MAX_CNT (4) - -static void i2s_tx_master_tx_ISR_proc(uint32_t dev_id); -static void i2s_tx_master_err_ISR_proc(uint32_t dev_id); - -#ifdef IO_I2S_TX_MST0_PRESENT -static _Interrupt void i2s_tx_master0_tx_ISR() -{ - i2s_tx_master_tx_ISR_proc(0); -} - -static _Interrupt void i2s_tx_master0_err_ISR() -{ - i2s_tx_master_err_ISR_proc(0); -} -#endif -#ifdef IO_I2S_TX_MST1_PRESENT -static _Interrupt void i2s_tx_master1_tx_ISR() -{ - i2s_tx_master_tx_ISR_proc(1); -} - -static _Interrupt void i2s_tx_master1_err_ISR() -{ - i2s_tx_master_err_ISR_proc(1); -} -#endif -#ifdef IO_I2S_TX_MST2_PRESENT -static _Interrupt void i2s_tx_master2_tx_ISR() -{ - i2s_tx_master_tx_ISR_proc(2); -} - -static _Interrupt void i2s_tx_master2_err_ISR() -{ - i2s_tx_master_err_ISR_proc(2); -} -#endif -#ifdef IO_I2S_TX_MST3_PRESENT - -static _Interrupt void i2s_tx_master3_tx_ISR() -{ - i2s_tx_master_tx_ISR_proc(3); -} - -static _Interrupt void i2s_tx_master3_err_ISR() -{ - i2s_tx_master_err_ISR_proc(3); -} -#endif - -/* I2S TX Master devices private data structures */ -static i2s_tx_master_info_pt i2s_tx_master_handles[I2S_TX_MASTER_MAX_CNT] = -{ 0 }; -#ifdef __Xdmac -static __attribute__ ((aligned(32))) -_Uncached uint32_t i2s_tx_master_dma_descriptors[8 * - I2S_TX_MASTER_MAX_CNT]; -#endif - -static i2s_tx_master_info_t i2s_tx_master_devs[] = { -#ifdef IO_I2S_TX_MST0_PRESENT - { .instID = 0, - .reg_base = AR_IO_I2S_TX_MST0_IER, - .tx_vector = IO_I2S_TX_MST0_INT_TX_REQ, - .err_vector = IO_I2S_TX_MST0_INT_ERR, - .tx_isr = i2s_tx_master0_tx_ISR, - .err_isr = i2s_tx_master0_err_ISR, -#ifdef IO_I2S_TX_MST0_DMA - .dmachanid = IO_I2S_TX_MST0_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_TX_MST0_FS }, -#endif -#ifdef IO_I2S_TX_MST1_PRESENT - { .instID = 1, - .reg_base = AR_IO_I2S_TX_MST1_IER, - .tx_vector = IO_I2S_TX_MST1_INT_TX_REQ, - .err_vector = IO_I2S_TX_MST1_INT_ERR, - .tx_isr = i2s_tx_master1_tx_ISR, - .err_isr = i2s_tx_master1_err_ISR, -#ifdef IO_I2S_TX_MST1_DMA - .dmachanid = IO_I2S_TX_MST1_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_TX_MST1_FS }, -#endif -#ifdef IO_I2S_TX_MST2_PRESENT - { .instID = 2, - .reg_base = AR_IO_I2S_TX_MST2_IER, - .tx_vector = IO_I2S_TX_MST2_INT_TX_REQ, - .err_vector = IO_I2S_TX_MST2_INT_ERR, - .tx_isr = i2s_tx_master2_tx_ISR, - .err_isr = i2s_tx_master2_err_ISR, -#ifdef IO_I2S_TX_MST2_DMA - .dmachanid = IO_I2S_TX_MST2_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_TX_MST2_FS }, -#endif -#ifdef IO_I2S_TX_MST3_PRESENT - { .instID = 3, - .reg_base = AR_IO_I2S_TX_MST3_IER, - .tx_vector = IO_I2S_TX_MST3_INT_TX_REQ, - .err_vector = IO_I2S_TX_MST3_INT_ERR, - .tx_isr = i2s_tx_master3_tx_ISR, - .err_isr = i2s_tx_master3_err_ISR, -#ifdef IO_I2S_TX_MST3_DMA - .dmachanid = IO_I2S_TX_MST3_DMA, -#else - .dmachanid = DMA_NONE, -#endif - .fifo_size = IO_I2S_TX_MST3_FS }, -#endif - { .instID = I2S_TX_MASTER_MAX_CNT } -}; - -#define REG_WRITE(reg, x) _sr((uint32_t)((x)), (uint32_t)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((uint32_t)(dev->reg_base + (reg))) - -/* API functions */ -uint32_t io_i2s_tx_master_open(uint32_t dev_id) -{ - i2s_tx_master_info_pt dev; - uint32_t h = 0; - - /* check device descriptor availability */ - while ((i2s_tx_master_devs[h].instID != dev_id) - && (i2s_tx_master_devs[h].instID != I2S_TX_MASTER_MAX_CNT)) { - h++; - } - if ((i2s_tx_master_devs[h].instID == I2S_TX_MASTER_MAX_CNT) || (0 != i2s_tx_master_handles[dev_id])) { /* dev_id not part of design, or still open */ - return 1; - } - i2s_tx_master_handles[dev_id] = &i2s_tx_master_devs[h]; - dev = i2s_tx_master_handles[dev_id]; - - dev->xfr_started = 0; // clear transfer started flag - dev->xfr_len = 0; // clear transfer lenght - dev->sys_cnt = dev->usr_cnt = 0; // reset buffer' access counters - -#ifdef __Xdmac - /* initialize DMA descriptors */ - dev->dmadescriptor = &i2s_tx_master_dma_descriptors[8 * h]; - - if (dev->dmachanid != DMA_NONE) { - dev->dmadescriptor[0] = dev->dmadescriptor[4] = 0; - dev->dmadescriptor[1] = dev->dmadescriptor[5] = 0; - dev->dmadescriptor[2] = dev->dmadescriptor[6] = - dev->reg_base + I2S_TXDMA; - dev->dmadescriptor[3] = (uint32_t) &(dev->dmadescriptor[4]); - dev->dmadescriptor[7] = (uint32_t) &(dev->dmadescriptor[0]); - - /* assign DMA interrupt vectors */ - _setvecti(dev->err_vector, dev->err_isr); - - _setvecti(DMAC_INT_BASE + dev->dmachanid, dev->tx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmachanid, dev->err_isr); - } else { -#endif - _setvecti(dev->tx_vector, dev->tx_isr); - _setvecti(dev->err_vector, dev->err_isr); -#ifdef __Xdmac -} -#endif - - REG_WRITE(I2S_IER, 0x01); // I2S: enable device - - return (0); -} - -void io_i2s_tx_master_close(uint32_t dev_id) -{ - i2s_tx_master_info_pt dev = i2s_tx_master_handles[dev_id]; - - /* put I2S registers into "after reset" state */ - REG_WRITE(I2S_IMR, 0x30); // mask TX interrupts - REG_WRITE(I2S_TER, 0x00); // disable channel - REG_WRITE(I2S_TFCR, 0x00); // reset threshold to default (0) - REG_WRITE(I2S_TCR, 0x02); // reset wlen to default (2) - REG_WRITE(I2S_TER, 0x01); // reset channel enable to default (1) - REG_WRITE(I2S_CER, 0x00); // disable clk - REG_WRITE(I2S_ITER, 0x00); // disable receive block - REG_WRITE(I2S_IER, 0x00); // disable device and flushes fifo - -#ifdef __Xdmac - /* reset DMA channel */ - _dma_chan_enable((0x1 << dev->dmachanid), 0); // aux-DMA channel reset bug fix - _dma_chan_reset(0x1 << dev->dmachanid); - /* deinitialize DMA interrupt handlers */ - _setvecti(DMAC_INT_BASE + dev->dmachanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmachanid, NULL); -#endif - /* deinitialize non DMA interrupt handlers */ - _setvecti(dev->tx_vector, NULL); - _setvecti(dev->err_vector, NULL); - - /* clear driver internal variables */ - dev->tx_cb = NULL; - dev->err_cb = NULL; - dev->xfr_started = 0; - - /* reset device handler */ - i2s_tx_master_handles[dev_id] = 0; -} - -void io_i2s_tx_master_write(uint32_t dev_id, uint32_t *data, - uint32_t *size) -{ - i2s_tx_master_info_pt dev = i2s_tx_master_handles[dev_id]; - uint32_t idx = dev->usr_cnt; - - if (((idx - dev->sys_cnt) != 2) && (*size != 0)) { - idx = idx & 0x0001; // current index in dev->buffer[] & dev->bufsize[] -#ifdef __Xdmac - if (dev->dmachanid != DMA_NONE) { - uint32_t burst_size = (dev->fifo_size - REG_READ(I2S_TFCR)) << 1; // actual FIFO trigger level - uint32_t xfer_size = (*size) << 2; // transfer size in bytes (ToDo: limited by 8KB) - idx = idx << 2; // now this is index in the array of DMA descriptors - - /* DMA: update DMACTRL and DMASAR part of descriptor */ - dev->dmadescriptor[idx + 0] = - I2S_TX_MASTER_DMA_CTRL | - (burst_size << I2S_TX_MASTER_DMA_CTRL_XFER_POS) | - ((xfer_size - 1) << I2S_TX_MASTER_DMA_CTRL_SIZE_POS); - dev->dmadescriptor[idx + 1] = (uint32_t) data + xfer_size - 2; - dev->usr_cnt++; // update user' buffer access counter; - - /* init DMA if required */ - if (dev->xfr_started == 0) { /* I2S transfer is not yet started -> init I2S Tx and DMA channel */ - dev->xfr_started = 1; - - REG_WRITE(I2S_TXFFR, 0x01); // I2S: reset TX FIFO - REG_WRITE(I2S_TFF, 0x01); // I2S: flush TX FIFO - REG_WRITE(I2S_CER, 0x01); // I2S: start the clock - REG_WRITE(I2S_ITER, 0x01); // I2S: enable transmitter block - REG_WRITE(I2S_IMR, ~0x20); // I2S: Unmask TX FIFO write overrun interrupts - - if (dev->dmachanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmachanid, - &(dev->dmadescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmachanid, - &(dev->dmadescriptor[0])); - } - - /* Start DMA channel */ - _dma_chan_enable((0x1 << dev->dmachanid), 1); - } - } else { -#endif /* __Xdmac */ - /* Store data buffer parameters */ - dev->buffer[idx] = data; - dev->bufsize[idx] = size; - dev->usr_cnt++; // update user' buffer access counter; - - if (dev->xfr_started == 0) { /* I2S transfer not yet started -> init I2S Rx */ - dev->xfr_started = 1; - - REG_WRITE(I2S_TXFFR, 0x01); // I2S: reset TX FIFO - REG_WRITE(I2S_TFF, 0x01); // I2S: flush TX FIFO - REG_WRITE(I2S_CER, 0x01); // I2S: start the clock - REG_WRITE(I2S_ITER, 0x01); // I2S: enable transmitter block - REG_WRITE(I2S_IMR, ~0x30); // I2S: Unmask TX interrupts - } -#ifdef __Xdmac - } -#endif /* __Xdmac */ - - } -} - -void io_i2s_tx_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - i2s_tx_master_info_pt dev = i2s_tx_master_handles[dev_id]; - - switch (cmd) { - case IO_SET_CB_TX: - dev->tx_cb = ((io_cb_t *) arg)->cb; - break; - - case IO_SET_CB_ERR: - dev->err_cb = ((io_cb_t *) arg)->cb; - break; - - case IO_I2S_TX_MASTER_SET_SAMPLE_WIDTH: - /* channel must be disabled before programming I2S_TCR */ - REG_WRITE(I2S_TCR, (*(uint32_t *) arg)); - break; - - case IO_I2S_TX_MASTER_SET_FIFO_THRESHOLD: - /* channel must be disabled before programming I2S_TFCR */ - REG_WRITE(I2S_TFCR, (*(uint32_t *) arg)); - break; - - case IO_I2S_TX_MASTER_SET_BITCLOCK: - REG_WRITE(I2S_CER, *((uint32_t *) arg)); - break; - - default: - break; - } -} - -static uint32_t i2s_tx_master_write_samples(uint32_t dev_id, - uint32_t *count) -{ - i2s_tx_master_info_pt dev = i2s_tx_master_handles[dev_id]; - uint32_t avail_cnt = 0; - - if (dev->sys_cnt == dev->usr_cnt) { /* no more data buffer available (buffer underflow error) */ - /* if no buffer will be available until FIFO is full then error callback will be called from error ISR */ - return (1); - } else { - uint32_t idx = dev->sys_cnt & 0x0001; - uint32_t *buff = dev->buffer[idx]; - uint32_t *size = dev->bufsize[idx]; - - avail_cnt = (*size - dev->xfr_len); - if (*count <= avail_cnt) { /* enough space in current buffer */ - avail_cnt = *count; - *count = 0; - } else { /* *count > avail_cnt: there will be samples remaining for the next buffer */ - *count -= avail_cnt; - } - - /* fill current buffer */ - for (int32_t i = 0; i != avail_cnt; i++) { - REG_WRITE(I2S_LTHR, buff[dev->xfr_len + i]); - REG_WRITE(I2S_RTHR, buff[dev->xfr_len + i] >> 16); - } - dev->xfr_len += avail_cnt; - - /* if current buffer is full: call user' callback, and increment read access counter */ - if (dev->xfr_len == *size) { - dev->sys_cnt++; - dev->xfr_len = 0; - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - } - } - - return (0); -} - -/* I2S TX data available interrupt handler */ -static void i2s_tx_master_tx_ISR_proc(uint32_t dev_id) -{ - i2s_tx_master_info_pt dev = i2s_tx_master_handles[dev_id]; - uint32_t sample_cnt = 0; - uint32_t error = 0; - - /* Tx FIFO trigger level reached - data available interrupt */ -#ifdef __Xdmac - if (dev->dmachanid == DMA_NONE) { /* DMA either disabled or does not exist */ -#endif /* __Xdmac */ - - sample_cnt = dev->fifo_size; - - if (dev->xfr_started == 0) { - dev->xfr_started = 1; - } else { - sample_cnt -= REG_READ(I2S_TFCR); // available data space in FIFO - } - - while (sample_cnt != 0) { - error = i2s_tx_master_write_samples(dev_id, &sample_cnt); - if (error != 0) { /* buffer underrun - no user' buffer left to receive data */ - REG_WRITE(I2S_IMR, 0x10); // I2S: mask TXFE interrupt - break; - } - } - -#ifdef __Xdmac -} else { /* DMA enabled for I2S peripheral */ - if (++dev->sys_cnt == dev->usr_cnt) { /* no data buffers left - disable dma channel and mask data available interrupt */ - _dma_chan_enable((0x1 << dev->dmachanid), 0); - } else { - // update buffer descriptor - _dma_chan_enable((0x1 << dev->dmachanid), 1); - } - - if (NULL != dev->tx_cb) { /* call for Tx callback if any */ - dev->tx_cb(dev_id); - } - - _dma_int_clear(0x1 << dev->dmachanid); // clear DMA interrupt flag - -} -#endif /* __Xdmac */ -} - -/* I2S TX error (FIFO overflow) interrupt handler */ -static void i2s_tx_master_err_ISR_proc(uint32_t dev_id) -{ - i2s_tx_master_info_pt dev = i2s_tx_master_handles[dev_id]; - - /* Tx FIFO overrun case */ -#ifdef __Xdmac - if (dev->dmachanid != DMA_NONE) { - /* DMA: disable DMA channel */ - _dma_chan_enable((0x1 << dev->dmachanid), 0); - _dma_int_clear((0x1 << dev->dmachanid)); - } -#endif - - /* I2S: stop I2S device */ - REG_WRITE(I2S_IMR, 0x30); // I2S: mask TX interrupts - REG_WRITE(I2S_CER, 0x00); // I2S: disable clk - REG_WRITE(I2S_IER, 0x00); // I2S: disable device - - /* call error callback if any */ - if (NULL != dev->err_cb) { - dev->err_cb(dev_id); - } -} - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/ss_i2s_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/ss_i2s_master.c deleted file mode 100644 index a7cb5b9e..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/i2s/ss_i2s_master.c +++ /dev/null @@ -1,345 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/* the wrapper of subsystem i2s master driver */ -#include "embARC_error.h" -#include "embARC_toolchain.h" - -#include "device/subsystem/i2s_rx_master.h" -#include "device/subsystem/i2s_tx_master.h" -#include "device/subsystem/ss_i2s_master.h" - -/** check expressions used in DFSS I2S driver implementation */ -#define SS_I2S_MASTER_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -/* I2S Master device registers */ -#define I2S_IER 0x000 /*!< (0x000) : Enable Register */ -#define I2S_IRER 0x004 /*!< (0x004) : I2S Receiver Block Enable Register */ -#define I2S_ITER 0x008 -#define I2S_CER 0x00c /*!< (0x00C) : Clock Enable Register */ -#define I2S_CCR 0x010 /*!< (0x010) : Clock Configuration Register */ -#define I2S_RXFFR 0x014 /*!< (0x014) : Receiver Block FIFO Register */ -#define I2S_TXFFR 0x018 -#define I2S_LTHR0 0x020 /*!< (0x020) : Left Transmit Holding Register 0 */ -#define I2S_RTHR0 0x024 /*!< (0x024) : Right Transmit Holding Register 0 */ -#define I2S_RER0 0x028 /*!< (0x028) : Receive Enable Register 0 */ -#define I2S_TER0 0x02C -#define I2S_RCR0 0x030 /*!< (0x030) : Receive Configuration Register 0 */ -#define I2S_TCR0 0x034 -#define I2S_ISR0 0x038 /*!< (0x038) : Interrupt Status Register 0 */ -#define I2S_IMR0 0x03c /*!< (0x03C) : Interrupt Mask Register 0 */ -#define I2S_ROR0 0x040 /*!< (0x040) : Receive Overrun Register 0 */ -#define I2S_TOR0 0x044 -#define I2S_RFCR0 0x048 /*!< (0x048) : Receive FIFO Configuration Register 0 */ -#define I2S_RFF0 0x050 /*!< (0x050) : Receive FIFO Flush 0 */ -#define I2S_TFF0 0x054 -#define I2S_RXDMA 0x1c0 /*!< (0x1C0) : Receiver Block DMA Register */ -#define I2S_TXDMA 0x1c8 - -#define REG_READ(x) arc_aux_read((ctx->reg_base + x)) -#define REG_WRITE(x, y) arc_aux_write((ctx->reg_base + x), y) - -static void ss_i2s_master_reset(SS_I2S_MST_DEV_CONTEXT *ctx) -{ - -} - -static void ss_i2s_master_flush_tx(SS_I2S_MST_DEV_CONTEXT *ctx) -{ - -} - -static void ss_i2s_master_flush_rx(SS_I2S_MST_DEV_CONTEXT *ctx) -{ - -} - -static void ss_i2s_master_enable(SS_I2S_MST_DEV_CONTEXT *ctx) -{ - // enable device - REG_WRITE(I2S_IER, 1); -} - -static void ss_i2s_master_disable(SS_I2S_MST_DEV_CONTEXT *ctx) -{ - // disable device - REG_WRITE(I2S_IER, 0); -} - -int32_t ss_i2s_mst_open(SS_I2S_MST_DEV_CONTEXT *ctx, uint32_t mode, uint32_t param) -{ - uint32_t dev_id = ctx->dev_id; - uint8_t io_mode = ctx->io_mode; - DEV_I2S_INFO_PTR info = ctx->info; - io_cb_t callback; - int32_t int_e = 0; - - if (mode != DEV_MASTER_MODE) { - return E_PAR; - } - - if (info->opn_cnt > 0) { - info->opn_cnt++; - return E_OPNED; - } - info->opn_cnt++; - - if (io_mode == SS_I2S_RX) { - if (io_i2s_rx_master_open(dev_id)) { - return E_SYS; - } - callback.cb = (IO_CB_FUNC)ctx->int_rx_cb; - int_e = int_e | int_enable(ctx->int_rx_avil); - int_e = int_e | int_enable(ctx->int_rx_err); - io_i2s_rx_master_ioctl(dev_id, IO_SET_CB_RX, &callback); - } else if (io_mode == SS_I2S_TX) { - if (io_i2s_tx_master_open(dev_id)) { - return E_SYS; - } - callback.cb = (IO_CB_FUNC)ctx->int_tx_cb; - io_i2s_tx_master_ioctl(dev_id, IO_SET_CB_TX, &callback); - int_e = int_e | int_enable(ctx->int_tx_req); - int_e = int_e | int_enable(ctx->int_tx_err); - } else { - return E_SYS; - } - - callback.cb = (IO_CB_FUNC)ctx->int_err_cb; - io_i2s_tx_master_ioctl(dev_id, IO_SET_CB_ERR, &callback); - - if (int_e != 0) { - return E_PAR; - } - return E_OK; -} - -int32_t ss_i2s_mst_close(SS_I2S_MST_DEV_CONTEXT *ctx) -{ - DEV_I2S_INFO_PTR info = ctx->info; - uint8_t io_mode = ctx->io_mode; - - info->opn_cnt--; - if (info->opn_cnt == 0) { - if (io_mode == SS_I2S_RX) { - int_disable(ctx->int_rx_avil); - int_disable(ctx->int_rx_err); - io_i2s_rx_master_close(ctx->dev_id); - } else if (io_mode == SS_I2S_TX) { - int_disable(ctx->int_tx_req); - int_disable(ctx->int_tx_err); - io_i2s_tx_master_close(ctx->dev_id); - } else { - return E_SYS; - } - info->opn_cnt = 0; - info->status = DEV_DISABLED; - ctx->flags = 0; - } else { - return E_OPNED; - } - return E_OK; -} - -int32_t ss_i2s_mst_read(SS_I2S_MST_DEV_CONTEXT *ctx, void *data, uint32_t len) -{ - uint32_t dev_id = ctx->dev_id; - uint8_t io_mode = ctx->io_mode; - uint32_t rd_len = len; - - if (ctx->flags) { - return E_NORES; - } - if (io_mode == SS_I2S_TX) { - return E_OBJ; - } - - if (arc_locked()) { - /* - * not allow to be called in isr or cpu is locked. - * because the bottom driver is simply interrupt driven - */ - return E_SYS; - } - ctx->flags = SS_I2S_MASTER_FLAG_RX; - io_i2s_rx_master_read(dev_id, data, &rd_len); - /* wait finished: i2s master int enable & no cpu lock */ - while (ctx->flags & SS_I2S_MASTER_FLAG_RX) { - ; - } - - if (ctx->flags & SS_I2S_MASTER_FLAG_RX_ERROR) { - ctx->flags = 0; - return E_SYS; - } - return rd_len; -} - -int32_t ss_i2s_mst_write(SS_I2S_MST_DEV_CONTEXT *ctx, void *data, uint32_t len) -{ - uint32_t dev_id = ctx->dev_id; - uint8_t io_mode = ctx->io_mode; - uint32_t wt_len = len; - - if (ctx->flags) { - return E_NORES; - } - if (io_mode == SS_I2S_RX) { - return E_OBJ; - } - - if (arc_locked()) { - /* - * not allow to be called in isr or cpu is locked. - * because the bottom driver is simply interrupt driven - */ - return E_SYS; - } - ctx->flags = SS_I2S_MASTER_FLAG_TX; - io_i2s_tx_master_write(dev_id, data, &wt_len); - /* wait finished: i2s master int enable & no cpu lock */ - while (ctx->flags & SS_I2S_MASTER_FLAG_TX) { - ; - } - - if (ctx->flags & SS_I2S_MASTER_FLAG_TX_ERROR) { - ctx->flags = 0; - return E_SYS; - } - return wt_len; -} - -int32_t ss_i2s_mst_control(SS_I2S_MST_DEV_CONTEXT *ctx, uint32_t cmd, void *param) -{ - uint32_t dev_id = ctx->dev_id; - uint8_t io_mode = ctx->io_mode; - DEV_I2S_INFO_PTR info = ctx->info; - int32_t ercd = E_OK; - - io_i2s_rx_master_ioctl(dev_id, cmd, param); - io_i2s_tx_master_ioctl(dev_id, cmd, param); - - switch (cmd) { - case I2S_CMD_GET_STATUS: - SS_I2S_MASTER_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = info->status; - break; - case I2S_CMD_SET_TXCB: - if (io_mode == SS_I2S_TX) { - SS_I2S_MASTER_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - io_i2s_tx_master_ioctl(dev_id, IO_SET_CB_TX, param); - } - break; - case I2S_CMD_SET_RXCB: - if (io_mode == SS_I2S_RX) { - SS_I2S_MASTER_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - io_i2s_rx_master_ioctl(dev_id, IO_SET_CB_RX, param); - } - break; - case I2S_CMD_SET_ERRCB: - if (io_mode == SS_I2S_RX) { - SS_I2S_MASTER_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - io_i2s_rx_master_ioctl(dev_id, IO_SET_CB_ERR, param); - } else if (io_mode == SS_I2S_TX) { - SS_I2S_MASTER_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - io_i2s_tx_master_ioctl(dev_id, IO_SET_CB_ERR, param); - } - break; - case I2S_CMD_SET_TXINT: break; - case I2S_CMD_SET_RXINT: break; - case I2S_CMD_RESET: - ss_i2s_master_reset(ctx); - break; - case I2S_CMD_FLUSH_TX: - ss_i2s_master_flush_tx(ctx); - break; - case I2S_CMD_FLUSH_RX: - ss_i2s_master_flush_rx(ctx); - break; - case I2S_CMD_ENA_DEV: - ss_i2s_master_enable(ctx); - break; - case I2S_CMD_DIS_DEV: - ss_i2s_master_disable(ctx); - break; - case I2S_CMD_SET_TXINT_BUF: break; - case I2S_CMD_SET_RXINT_BUF: break; - case I2S_CMD_SET_TXCHET_BUF: break; - case I2S_CMD_SET_RXCHDT_BUF: break; - case I2S_CMD_MST_SET_CLK: break; - case I2S_CMD_MST_SET_WSS: break; - case I2S_CMD_MST_SET_SCLKG: break; - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -void ss_i2s_mst_int_tx_cb(SS_I2S_MST_DEV_CONTEXT *ctx, void *param) -{ - DEV_I2S_INFO_PTR info = ctx->info; - - if (ctx->flags & SS_I2S_MASTER_FLAG_TX) { - ctx->flags &= ~SS_I2S_MASTER_FLAG_TX; - if (info->i2s_cbs.tx_cb) { - info->i2s_cbs.tx_cb(info); - } - } -} - -void ss_i2s_mst_int_rx_cb(SS_I2S_MST_DEV_CONTEXT *ctx, void *param) -{ - DEV_I2S_INFO_PTR info = ctx->info; - - if (ctx->flags & SS_I2S_MASTER_FLAG_RX) { - ctx->flags &= ~SS_I2S_MASTER_FLAG_RX; - if (info->i2s_cbs.rx_cb) { - info->i2s_cbs.rx_cb(info); - } - } -} - -void ss_i2s_mst_int_err_cb(SS_I2S_MST_DEV_CONTEXT *ctx, void *param) -{ - DEV_I2S_INFO_PTR info = ctx->info; - uint8_t io_mode = ctx->io_mode; - uint32_t flag; - - flag = (io_mode == SS_I2S_RX) ? SS_I2S_MASTER_FLAG_RX_ERROR : SS_I2S_MASTER_FLAG_TX_ERROR; - - if (ctx->flags & flag) { - ctx->flags &= ~flag; - if (info->i2s_cbs.err_cb) { - info->i2s_cbs.err_cb(info); - } - } -} diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/i2c_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/i2c_master.c deleted file mode 100644 index a4b0b7fc..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/i2c_master.c +++ /dev/null @@ -1,947 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/i2c_master.h" -#include "device/subsystem/i2c_priv.h" -#include "io_config.h" -#include "apexextensions.h" - -/* Notes: - * - */ - -#ifdef IO_I2C_MST0_PRESENT -#define I2C_DEV_PRESENT -#endif -#ifdef IO_I2C_MST1_PRESENT -#define I2C_DEV_PRESENT -#endif -#ifdef IO_I2C_MST2_PRESENT -#define I2C_DEV_PRESENT -#endif -#ifdef IO_I2C_MST3_PRESENT -#define I2C_DEV_PRESENT -#endif - -#ifdef I2C_DEV_PRESENT - -#define I2C_MAX_CNT (4) - -static void i2c_mst_err_ISR_proc(uint32_t dev_id); -static void i2c_mst_rx_avail_ISR_proc(uint32_t dev_id); -static void i2c_mst_tx_req_ISR_proc(uint32_t dev_id); -static void i2c_mst_stop_det_ISR_proc(uint32_t dev_id); - -#ifdef IO_I2C_MST0_PRESENT -static _Interrupt void i2c_mst0_err_ISR() -{ - i2c_mst_err_ISR_proc(0); -} - -static _Interrupt void i2c_mst0_rx_avail_ISR() -{ - i2c_mst_rx_avail_ISR_proc(0); -} - -static _Interrupt void i2c_mst0_tx_req_ISR() -{ - i2c_mst_tx_req_ISR_proc(0); -} - -static _Interrupt void i2c_mst0_stop_det_ISR() -{ - i2c_mst_stop_det_ISR_proc(0); -} -#endif -#ifdef IO_I2C_MST1_PRESENT -static _Interrupt void i2c_mst1_err_ISR() -{ - i2c_mst_err_ISR_proc(1); -} - -static _Interrupt void i2c_mst1_rx_avail_ISR() -{ - i2c_mst_rx_avail_ISR_proc(1); -} - -static _Interrupt void i2c_mst1_tx_req_ISR() -{ - i2c_mst_tx_req_ISR_proc(1); -} - -static _Interrupt void i2c_mst1_stop_det_ISR() -{ - i2c_mst_stop_det_ISR_proc(1); -} -#endif -#ifdef IO_I2C_MST2_PRESENT -static _Interrupt void i2c_mst2_err_ISR() -{ - i2c_mst_err_ISR_proc(2); -} - -static _Interrupt void i2c_mst2_rx_avail_ISR() -{ - i2c_mst_rx_avail_ISR_proc(2); -} - -static _Interrupt void i2c_mst2_tx_req_ISR() -{ - i2c_mst_tx_req_ISR_proc(2); -} - -static _Interrupt void i2c_mst2_stop_det_ISR() -{ - i2c_mst_stop_det_ISR_proc(2); -} -#endif -#ifdef IO_I2C_MST3_PRESENT -static _Interrupt void i2c_mst3_err_ISR() -{ - i2c_mst_err_ISR_proc(3); -} - -static _Interrupt void i2c_mst3_rx_avail_ISR() -{ - i2c_mst_rx_avail_ISR_proc(3); -} - -static _Interrupt void i2c_mst3_tx_req_ISR() -{ - i2c_mst_tx_req_ISR_proc(3); -} - -static _Interrupt void i2c_mst3_stop_det_ISR() -{ - i2c_mst_stop_det_ISR_proc(3); -} -#endif - -static void fill_txfifo(i2c_info_pt dev); -static void fill_txfifo_for_rx(i2c_info_pt dev); -static void retrieve_rxfifo(i2c_info_pt dev); - -#ifdef __Xdmac -static void create_dma_descriptors_rx(i2c_info_pt dev, uint8_t *dest, - uint32_t size, uint32_t burst); -static void create_dma_descriptors_tx(i2c_info_pt dev, uint8_t *src, - uint32_t size, uint32_t burst); -static void create_dma_descriptors_tx_for_rx(i2c_info_pt dev, - uint32_t size, - uint32_t burst); -#endif - -/* I2C master devices private data structures */ -static i2c_info_pt i2c_handles[I2C_MAX_CNT] = { 0 }; - -#ifdef __Xdmac -static _Uncached uint32_t i2c_dmarx_descriptors[4 * I2C_MAX_CNT]; -static _Uncached uint32_t i2c_dmatx_descriptors[8 * I2C_MAX_CNT]; -#endif - -static i2c_info_t i2c_master_devs[] = { -#ifdef IO_I2C_MST0_PRESENT - { .instID = 0, - .reg_base = AR_IO_I2C_MST0_CON, -#ifdef IO_I2C_MST0_DMA_RX - .dmarxchanid = IO_I2C_MST0_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_I2C_MST0_DMA_TX - .dmatxchanid = IO_I2C_MST0_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_I2C_MST0_FS, - .vector_err = IO_I2C_MST0_INT_ERR, - .isr_err = i2c_mst0_err_ISR, - .vector_rx_avail = IO_I2C_MST0_INT_RX_AVAIL, - .isr_rx_avail = i2c_mst0_rx_avail_ISR, - .vector_tx_req = IO_I2C_MST0_INT_TX_REQ, - .isr_tx_req = i2c_mst0_tx_req_ISR, - .vector_stop_det = IO_I2C_MST0_INT_STOP_DET, - .isr_stop_det = i2c_mst0_stop_det_ISR }, -#endif -#ifdef IO_I2C_MST1_PRESENT - { .instID = 1, - .reg_base = AR_IO_I2C_MST1_CON, -#ifdef IO_I2C_MST1_DMA_RX - .dmarxchanid = IO_I2C_MST1_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_I2C_MST1_DMA_TX - .dmatxchanid = IO_I2C_MST1_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_I2C_MST1_FS, - .vector_err = IO_I2C_MST1_INT_ERR, - .isr_err = i2c_mst1_err_ISR, - .vector_rx_avail = IO_I2C_MST1_INT_RX_AVAIL, - .isr_rx_avail = i2c_mst1_rx_avail_ISR, - .vector_tx_req = IO_I2C_MST1_INT_TX_REQ, - .isr_tx_req = i2c_mst1_tx_req_ISR, - .vector_stop_det = IO_I2C_MST1_INT_STOP_DET, - .isr_stop_det = i2c_mst1_stop_det_ISR }, -#endif -#ifdef IO_I2C_MST2_PRESENT - { .instID = 2, - .reg_base = AR_IO_I2C_MST2_CON, -#ifdef IO_I2C_MST2_DMA_RX - .dmarxchanid = IO_I2C_MST2_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_I2C_MST2_DMA_TX - .dmatxchanid = IO_I2C_MST2_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_I2C_MST2_FS, - .vector_err = IO_I2C_MST2_INT_ERR, - .isr_err = i2c_mst2_err_ISR, - .vector_rx_avail = IO_I2C_MST2_INT_RX_AVAIL, - .isr_rx_avail = i2c_mst2_rx_avail_ISR, - .vector_tx_req = IO_I2C_MST2_INT_TX_REQ, - .isr_tx_req = i2c_mst2_tx_req_ISR, - .vector_stop_det = IO_I2C_MST2_INT_STOP_DET, - .isr_stop_det = i2c_mst2_stop_det_ISR }, -#endif -#ifdef IO_I2C_MST3_PRESENT - { .instID = 3, - .reg_base = AR_IO_I2C_MST3_CON, -#ifdef IO_I2C_MST3_DMA_RX - .dmarxchanid = IO_I2C_MST3_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_I2C_MST3_DMA_TX - .dmatxchanid = IO_I2C_MST3_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_I2C_MST3_FS, - .vector_err = IO_I2C_MST3_INT_ERR, - .isr_err = i2c_mst3_err_ISR, - .vector_rx_avail = IO_I2C_MST3_INT_RX_AVAIL, - .isr_rx_avail = i2c_mst3_rx_avail_ISR, - .vector_tx_req = IO_I2C_MST3_INT_TX_REQ, - .isr_tx_req = i2c_mst3_tx_req_ISR, - .vector_stop_det = IO_I2C_MST3_INT_STOP_DET, - .isr_stop_det = i2c_mst3_stop_det_ISR }, -#endif - { .instID = I2C_MAX_CNT } -}; - -#define REG_WRITE(reg, x) _sr((unsigned)(x), (unsigned)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((unsigned)(dev->reg_base + reg)) -#define REG_WRITE_BITS(reg, x, y, len, pos) REG_WRITE(reg, ((((x) & ~((~(0xffffffff << len)) << pos)) \ - | (((y) << pos) & ((~(0xffffffff << len)) << pos))))) - -/* API functions */ -uint32_t io_i2c_master_open(uint32_t dev_id) -{ - uint32_t h = 0; - i2c_info_pt dev; - - h = 0; - while ((i2c_master_devs[h].instID != dev_id) - && (i2c_master_devs[h].instID != I2C_MAX_CNT)) { - h++; - } - if ((i2c_master_devs[h].instID == I2C_MAX_CNT) || (0 != i2c_handles[dev_id])) { /* dev_id not part of design, or still open */ - return 1; - } - i2c_handles[dev_id] = &i2c_master_devs[h]; - dev = i2c_handles[dev_id]; - - /* enable clock */ - REG_WRITE(I2C_CLKEN, 0x1); - - /* mask all interrupts */ - REG_WRITE(I2C_INTR_MASK, 0); - - /* initialize */ - dev->handling_tx = dev->handling_rx = 0; - dev->tx_data = dev->rx_data = NULL; - dev->next_cond = I2C_STOP_CMD; - - /* set interrupt vector */ - _setvecti(dev->vector_err, dev->isr_err); - _setvecti(dev->vector_rx_avail, dev->isr_rx_avail); - _setvecti(dev->vector_tx_req, dev->isr_tx_req); - _setvecti(dev->vector_stop_det, dev->isr_stop_det); - -#ifdef __Xdmac - dev->dmarxdescriptor = &i2c_dmarx_descriptors[4 * h]; - dev->dmatxdescriptor = &i2c_dmatx_descriptors[8 * h]; - - if (dev->dmarxchanid != DMA_NONE) { - dev->dmarxdescriptor[1] = dev->reg_base + I2C_DATA_CMD; - dev->dmarxdescriptor[3] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, dev->isr_rx_avail); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, dev->isr_err); - } - - if (dev->dmatxchanid != DMA_NONE) { - dev->dmatxdescriptor[2] = dev->dmatxdescriptor[6] = - dev->reg_base + I2C_DATA_CMD; - dev->dmatxdescriptor[3] = (uint32_t) &(dev->dmatxdescriptor[4]); - dev->dmatxdescriptor[7] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, dev->isr_tx_req); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, dev->isr_err); - } -#endif - - /* enable device */ - REG_WRITE(I2C_ENABLE, 0x1); - - /* unmask error interrupt: stop-detection, tx-abort, rx-over */ - REG_WRITE(I2C_INTR_MASK, R_TX_ABRT | R_RX_OVER); - - return 0; -} - -void io_i2c_master_close(uint32_t dev_id) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t enable = REG_READ(I2C_ENABLE); - - /* clear all interrupts */ - REG_WRITE(I2C_INTR_MASK, 0); - REG_READ(I2C_CLR_INTR); - - /* abort (and wait) */ - REG_WRITE(I2C_ENABLE, (enable | (0x1 << 1))); - while ((REG_READ(I2C_TX_ABRT_SOURCE) & (0x1 << 16)) == 0) { - ; - } - - /* disable */ - REG_WRITE(I2C_ENABLE, 0); - - /* reset regs */ - REG_WRITE(I2C_CON, 0x65); - REG_WRITE(I2C_TAR, 0x55); - REG_WRITE(I2C_SS_SCL_HCNT, 0x30); - REG_WRITE(I2C_SS_SCL_LCNT, 0x38); - REG_WRITE(I2C_FS_SCL_HCNT, 0); - REG_WRITE(I2C_FS_SCL_LCNT, 0); - REG_WRITE(I2C_RX_TL, 0); - REG_WRITE(I2C_TX_TL, 0); - REG_WRITE(I2C_SDA_HOLD, 0x1); - REG_WRITE(I2C_FS_SPKLEN, 0x1); - - /* gate the I2C clock */ - REG_WRITE(I2C_CLKEN, 0); - - _setvecti(dev->vector_err, NULL); - _setvecti(dev->vector_rx_avail, NULL); - _setvecti(dev->vector_tx_req, NULL); - _setvecti(dev->vector_stop_det, NULL); - -#ifdef __Xdmac - if (dev->dmarxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmarxchanid); - } - - if (dev->dmatxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmatxchanid); - } -#endif - - dev->rx_cb = NULL; - dev->tx_cb = NULL; - dev->err_cb = NULL; - - i2c_handles[dev_id] = 0; -} - -void io_i2c_master_read(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t val = 0; - - dev->rx_size = *size; - dev->rx_count = dev->rx_req_count = 0; - dev->rx_data = data; - - /* check whether a master-tx is in progress; if so, postpone until tx completion */ - if (dev->handling_tx == 0) { - dev->handling_rx = 1; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* write first requests to fifo, assuming size > 0 */ - fill_txfifo_for_rx(dev); - /* unmask interrupts: tx-threshold (tx-empty), rx-threshold (rx-full) */ - val = REG_READ(I2C_INTR_MASK) | R_TX_EMPTY | R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); -#ifdef __Xdmac - } else { - /* RX descriptor - to fetch data */ - if (*size != 0) { - /* rx data available; at least one */ - create_dma_descriptors_rx(dev, data, *size, - (1 + REG_READ(I2C_RX_TL))); - - /* init dma */ - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmarxchanid), 1); - } - /* TX descriptor - for read command and a closing read+stop command */ - if (*size != 0) { - /* tx data available; at least one, more is uncertain */ - create_dma_descriptors_tx_for_rx(dev, *size, - (dev->fifo_depth - - REG_READ(I2C_TX_TL))); - - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - } - } -#endif - } -} - -void io_i2c_master_write(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t val = 0; - - dev->tx_size = *size; - dev->tx_count = 0; - dev->tx_data = data; - - /* check whether a master-rx is in progress; if so, postpone until rx completion */ - if (dev->handling_rx == 0) { - dev->handling_tx = 1; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* write first bytes to fifo, assuming size > 0 */ - fill_txfifo(dev); - /* unmask interrupt: tx-threshold (tx-empty) */ - val = REG_READ(I2C_INTR_MASK) | R_TX_EMPTY; - REG_WRITE(I2C_INTR_MASK, val); -#ifdef __Xdmac - } else { - /* TX descriptor - data+write command and a closing data+write+stop command */ - if (*size != 0) { - /* tx data available; at least one, more is uncertain */ - create_dma_descriptors_tx(dev, data, *size, - (dev->fifo_depth - - REG_READ(I2C_TX_TL))); - - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - } - } -#endif - } -} - -void io_i2c_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - uint32_t data = 0, enable = 0; - i2c_info_pt dev = i2c_handles[dev_id]; - - switch (cmd) { - case IO_SET_CB_RX: - dev->rx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_TX: - dev->tx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_ERR: - dev->err_cb = ((io_cb_t *) arg)->cb; - break; - case IO_I2C_MASTER_SET_NEXT_COND: - dev->next_cond = (uint16_t)*((uint32_t *) arg); - break; - - default: - { - enable = REG_READ(I2C_ENABLE); - REG_WRITE(I2C_ENABLE, (enable & ~(0x1))); - - switch (cmd) { - case IO_I2C_MASTER_SET_HOLD_TIME_RX: - data = REG_READ(I2C_SDA_HOLD); - REG_WRITE_BITS(I2C_SDA_HOLD, data, *((uint32_t *) arg), 8, - 16); - break; - case IO_I2C_MASTER_SET_HOLD_TIME_TX: - data = REG_READ(I2C_SDA_HOLD); - REG_WRITE_BITS(I2C_SDA_HOLD, data, *((uint32_t *) arg), 16, - 0); - break; - case IO_I2C_MASTER_SET_SPEED: - data = REG_READ(I2C_CON); - REG_WRITE_BITS(I2C_CON, data, *((uint32_t *) arg), 2, 1); - break; - case IO_I2C_MASTER_SET_10BIT_ADDR: - data = REG_READ(I2C_CON); - REG_WRITE_BITS(I2C_CON, data, *((uint32_t *) arg), 1, 3); - break; - - case IO_I2C_MASTER_SET_SPKLEN: - REG_WRITE(I2C_FS_SPKLEN, *((uint32_t *) arg)); - break; - case IO_I2C_MASTER_SET_TARGET_ADDR: - REG_WRITE(I2C_TAR, *((uint32_t *) arg)); - break; - case IO_I2C_MASTER_SET_SS_SCL_HCNT: - REG_WRITE(I2C_SS_SCL_HCNT, *((uint32_t *) arg)); - break; - case IO_I2C_MASTER_SET_SS_SCL_LCNT: - REG_WRITE(I2C_SS_SCL_LCNT, *((uint32_t *) arg)); - break; - case IO_I2C_MASTER_SET_FS_SCL_HCNT: - REG_WRITE(I2C_FS_SCL_HCNT, *((uint32_t *) arg)); - break; - case IO_I2C_MASTER_SET_FS_SCL_LCNT: - REG_WRITE(I2C_FS_SCL_LCNT, *((uint32_t *) arg)); - break; - case IO_I2C_MASTER_SET_RX_THRESHOLD: - REG_WRITE(I2C_RX_TL, *((uint32_t *) arg)); - break; - case IO_I2C_MASTER_SET_TX_THRESHOLD: - REG_WRITE(I2C_TX_TL, *((uint32_t *) arg)); - break; - - default: - break; - } - - while ((0x1 & REG_READ(I2C_ENABLE_STATUS)) != 0) { - ; - } - enable = REG_READ(I2C_ENABLE); - REG_WRITE(I2C_ENABLE, (enable | 0x1)); - - break; - } - } - -} - -static void i2c_mst_err_ISR_proc(uint32_t dev_id) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - - if (REG_READ(I2C_CLR_TX_ABRT)) { - if (NULL != dev->err_cb) { - dev->err_cb(dev_id); - } - } - - if (REG_READ(I2C_CLR_RX_OVER)) { - if (NULL != dev->err_cb) { - dev->err_cb(dev_id); - } - } -} - -static void i2c_mst_rx_avail_ISR_proc(uint32_t dev_id) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t val = 0; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* read data from fifo */ - retrieve_rxfifo(dev); - if (dev->rx_size == dev->rx_count) { /* read buffer completely filled, mask rx-avail interrupt */ - val = REG_READ(I2C_INTR_MASK) & ~R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); - - dev->handling_rx = 0; - dev->rx_data = NULL; - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - } -#ifdef __Xdmac -} else { - /* DMA RX xfer done */ - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - _dma_int_clear((0x1 << dev->dmarxchanid)); -} -#endif -} - -static void i2c_mst_tx_req_ISR_proc(uint32_t dev_id) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t val = 0; - - if (dev->handling_tx == 1) { -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - if (dev->tx_size == dev->tx_count) { /* no data left to put into the fifo, mask tx-threshold (tx-empty) */ - val = REG_READ(I2C_INTR_MASK) & ~R_TX_EMPTY; - REG_WRITE(I2C_INTR_MASK, val); - /* tx done */ - dev->handling_tx = 0; - dev->tx_data = NULL; - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - } else { /* write data into fifo */ - fill_txfifo(dev); - } -#ifdef __Xdmac - } else { - /* DMA TX xfer done */ - _dma_chan_enable((0x1 << dev->dmatxchanid), 0); - _dma_int_clear((0x1 << dev->dmatxchanid)); - } -#endif - } - - if (dev->handling_rx == 1) { -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - if (dev->rx_size == dev->rx_req_count) { /* no data left to put into the fifo, mask tx-threshold (tx-empty) */ - val = REG_READ(I2C_INTR_MASK) & ~R_TX_EMPTY; - REG_WRITE(I2C_INTR_MASK, val); - } else { /* write data into fifo */ - fill_txfifo_for_rx(dev); - } -#ifdef __Xdmac - } else { - /* DMA TX xfer done */ - dev->rx_req_count = dev->rx_size; - - _dma_chan_enable((0x1 << dev->dmatxchanid), 0); - _dma_int_clear((0x1 << dev->dmatxchanid)); - } -#endif - } - -} - -static void i2c_mst_stop_det_ISR_proc(uint32_t dev_id) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t val = 0; - - if (dev->handling_tx == 1) { - /* tx done */ - dev->handling_tx = 0; - - dev->tx_data = NULL; - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - - /* handle pending rx, if any */ - if (dev->rx_data != NULL) { - dev->handling_rx = 1; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* write first requests to fifo, assuming size > 0 */ - fill_txfifo_for_rx(dev); - /* unmask interrupts: tx-threshold (tx-empty), rx-threshold (rx-full) */ - val = REG_READ(I2C_INTR_MASK) | R_TX_EMPTY | R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); -#ifdef __Xdmac - } else { - /* RX descriptor - to fetch data */ - if (dev->rx_size != 0) { - /* rx data available; at least one */ - create_dma_descriptors_rx(dev, dev->rx_data, - dev->rx_size, - (1 + REG_READ(I2C_RX_TL))); - - /* init dma */ - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmarxchanid), 1); - } - /* TX descriptor - for read command and a closing read+stop command */ - if (dev->rx_size != 0) { - /* tx data available; at least one, more is uncertain */ - create_dma_descriptors_tx_for_rx(dev, dev->rx_size, - (dev->fifo_depth - - REG_READ - (I2C_TX_TL))); - - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - } - } -#endif - } else { /* done, prevent threshold interrupts */ - val = REG_READ(I2C_INTR_MASK) & ~R_TX_EMPTY & ~R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); - } - } else if (dev->handling_rx == 1) { -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* read remaining data from fifo */ - retrieve_rxfifo(dev); -#ifdef __Xdmac - } -#endif - - /* rx done */ - dev->handling_rx = 0; - - dev->rx_data = NULL; - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - - /* handle pending tx, if any */ - if (dev->tx_data != NULL) { - dev->handling_tx = 1; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* write first bytes to fifo, assuming size > 0 */ - fill_txfifo(dev); - /* unmask interrupt: tx-threshold (tx-empty) */ - val = REG_READ(I2C_INTR_MASK) | R_TX_EMPTY; - REG_WRITE(I2C_INTR_MASK, val); -#ifdef __Xdmac - } else { - /* TX descriptor - data+write command and a closing data+write+stop command */ - if (dev->tx_size != 0) { - /* tx data available; at least one, more is uncertain */ - create_dma_descriptors_tx(dev, dev->tx_data, - dev->tx_size, - (dev->fifo_depth - - REG_READ(I2C_TX_TL))); - - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - } - } -#endif - } else { /* done, prevent threshold interrupts */ - val = REG_READ(I2C_INTR_MASK) & ~R_TX_EMPTY & ~R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); - } - } - - REG_READ(I2C_CLR_STOP_DET); -} - -static void fill_txfifo(i2c_info_pt dev) -{ - uint32_t h = 0, free = 0, cnt = 0; - - cnt = dev->tx_size - dev->tx_count; - free = dev->fifo_depth - REG_READ(I2C_TXFLR); - if (cnt > free) { - cnt = free; - } - for (h = 0; h != (cnt - 1); h++) { - REG_WRITE(I2C_DATA_CMD, (dev->tx_data[dev->tx_count++])); - } - if ((dev->tx_size - 1) == dev->tx_count) { /* end of message, insert stop condition */ - REG_WRITE(I2C_DATA_CMD, - (dev->tx_data[dev->tx_count++] | dev->next_cond)); - } else { /* continue */ - REG_WRITE(I2C_DATA_CMD, (dev->tx_data[dev->tx_count++])); - } -} - -static void fill_txfifo_for_rx(i2c_info_pt dev) -{ - uint32_t h = 0, free = 0, cnt = 0; - - cnt = dev->rx_size - dev->rx_req_count; - free = dev->fifo_depth - REG_READ(I2C_TXFLR); - if (cnt > free) { - cnt = free; - } - for (h = 0; h != (cnt - 1); h++) { - REG_WRITE(I2C_DATA_CMD, I2C_READ_CMD); - } - dev->rx_req_count += cnt; - if (dev->rx_size == dev->rx_req_count) { /* end of message, insert stop condition */ - REG_WRITE(I2C_DATA_CMD, (I2C_READ_CMD | dev->next_cond)); - } else { /* continue */ - REG_WRITE(I2C_DATA_CMD, I2C_READ_CMD); - } -} - -static void retrieve_rxfifo(i2c_info_pt dev) -{ - uint32_t h = 0, avail = 0, cnt = 0; - - cnt = dev->rx_size - dev->rx_count; - avail = REG_READ(I2C_RXFLR); - if (cnt > avail) { - cnt = avail; - } - for (h = 0; h != cnt; h++) { - dev->rx_data[dev->rx_count++] = REG_READ(I2C_DATA_CMD); - } -} - -#ifdef __Xdmac -#define I2C_MST_DMA_RX_CTRL (0xa0000015) /* am=b10, i=b1, dw/inc=b000, dtt=b10, r=b1, op=b01 */ -#define I2C_MST_DMA_TX_FOR_RX_CTRL (0x0000006f) /* am=b00, i=b0, dw/inc=b011, dtt=b01, r=b1, op=b11 */ -#define I2C_MST_DMA_TX_END_CTRL (0x2000006d) /* am=b00, i=b1, dw/inc=b011, dtt=b01, r=b1, op=b01 */ -#define I2C_MST_DMA_TX_CTRL (0x4000000f) /* am=b01, i=b0, dw/inc=b000, dtt=b01, r=b1, op=b11 */ -#define I2C_MST_DMA_CTRL_SIZE_POS (8) -#define I2C_MST_DMA_CTRL_XFER_POS (21) - -static uint16_t readCommand = I2C_READ_CMD; -static uint16_t readstopCommand = I2C_READ_CMD | I2C_STOP_CMD; - -static void create_dma_descriptors_rx(i2c_info_pt dev, uint8_t *dest, - uint32_t size, uint32_t burst) -{ - dev->dmarxdescriptor[0] = - I2C_MST_DMA_RX_CTRL | (burst << I2C_MST_DMA_CTRL_XFER_POS) | - ((size - 1) << I2C_MST_DMA_CTRL_SIZE_POS); - dev->dmarxdescriptor[2] = (uint32_t) dest + (size - 1); -} - -static void create_dma_descriptors_tx(i2c_info_pt dev, uint8_t *src, - uint32_t size, uint32_t burst) -{ - if (size > 1) { - dev->dmatxdescriptor[0] = - I2C_MST_DMA_TX_CTRL | (burst << I2C_MST_DMA_CTRL_XFER_POS) | - ((size - 2) << I2C_MST_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[1] = (uint32_t) src + (size - 2); - - dev->dmatx_last = src[size - 1] | I2C_STOP_CMD; - dev->dmatxdescriptor[4 + 0] = - I2C_MST_DMA_TX_END_CTRL | (burst << I2C_MST_DMA_CTRL_XFER_POS) - | (1 << I2C_MST_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[4 + 1] = (uint32_t) &(dev->dmatx_last); - } else { /* size == 1 */ - dev->dmatx_last = src[0] | I2C_STOP_CMD; - dev->dmatxdescriptor[0] = - I2C_MST_DMA_TX_END_CTRL | (burst << I2C_MST_DMA_CTRL_XFER_POS) - | (1 << I2C_MST_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[1] = (uint32_t) &(dev->dmatx_last); - } -} - -static void create_dma_descriptors_tx_for_rx(i2c_info_pt dev, - uint32_t size, uint32_t burst) -{ - if (size > 1) { - dev->dmatxdescriptor[0] = - I2C_MST_DMA_TX_FOR_RX_CTRL | (burst << - I2C_MST_DMA_CTRL_XFER_POS) | - (((size - 1) * 2 - 1) << I2C_MST_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[1] = (uint32_t) &readCommand; - - dev->dmatxdescriptor[4 + 0] = - I2C_MST_DMA_TX_END_CTRL | (burst << I2C_MST_DMA_CTRL_XFER_POS) - | (1 << I2C_MST_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[4 + 1] = (uint32_t) &readstopCommand; - } else { /* size == 1 */ - dev->dmatxdescriptor[0] = - I2C_MST_DMA_TX_END_CTRL | (burst << I2C_MST_DMA_CTRL_XFER_POS) - | (1 << I2C_MST_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[1] = (uint32_t) &readstopCommand; - } -} - -#endif - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/i2c_slave.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/i2c_slave.c deleted file mode 100644 index 075b75e5..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/i2c_slave.c +++ /dev/null @@ -1,690 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/i2c_slave.h" -#include "device/subsystem/i2c_priv.h" -#include "io_config.h" -#include "apexextensions.h" - -/* Notes: - * - */ -#ifdef IO_I2C_SLV0_PRESENT -#define I2C_DEV_PRESENT - -static _Interrupt void i2c_slv0_err_ISR(); -static _Interrupt void i2c_slv0_rx_avail_ISR(); -static _Interrupt void i2c_slv0_tx_req_ISR(); -static _Interrupt void i2c_slv0_stop_det_ISR(); -static _Interrupt void i2c_slv0_rd_req_ISR(); - -/* I2C slave devices private data structures; at most 1 instance */ -static i2c_info_pt i2c_handles[1] = { 0 }; - -#ifdef __Xdmac -static _Uncached uint32_t i2c_dmarx_descriptors[4 * 1]; -static _Uncached uint32_t i2c_dmatx_descriptors[8 * 1]; -#endif - -#define I2C_SLV_DMA_RX_CTRL (0xa0000015) /* am=b10, i=b1, dw/inc=b000, dtt=b10, r=b1, op=b01 */ -#define I2C_SLV_DMA_TX_CTRL (0x6000000d) /* am=b01, i=b1, dw/inc=b000, dtt=b01, r=b1, op=b01 */ -#define I2C_SLV_DMA_CTRL_SIZE_POS (8) -#define I2C_SLV_DMA_CTRL_XFER_POS (21) - -static i2c_info_t i2c_slave_devs[] = { - { .instID = 0, - .reg_base = AR_IO_I2C_SLV0_CON, -#ifdef IO_I2C_SLV0_DMA_RX - .dmarxchanid = IO_I2C_SLV0_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_I2C_SLV0_DMA_TX - .dmatxchanid = IO_I2C_SLV0_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_I2C_SLV0_FS, - .vector_err = IO_I2C_SLV0_INT_ERR, - .isr_err = i2c_slv0_err_ISR, - .vector_rx_avail = IO_I2C_SLV0_INT_RX_AVAIL, - .isr_rx_avail = i2c_slv0_rx_avail_ISR, - .vector_tx_req = IO_I2C_SLV0_INT_TX_REQ, - .isr_tx_req = i2c_slv0_tx_req_ISR, - .vector_stop_det = IO_I2C_SLV0_INT_STOP_DET, - .isr_stop_det = i2c_slv0_stop_det_ISR, - .vector_restart_det = IO_I2C_SLV0_INT_RESTART_DET, - .vector_rd_req = IO_I2C_SLV0_INT_RD_REQ, - .isr_rd_req = i2c_slv0_rd_req_ISR } -}; -#endif - -#ifdef I2C_DEV_PRESENT - -#define REG_WRITE(reg, x) _sr((unsigned)(x), (unsigned)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((unsigned)(dev->reg_base + reg)) -#define REG_WRITE_BITS(reg, x, y, len, pos) REG_WRITE(reg, ((((x) & ~((~(0xffffffff << len)) << pos)) \ - | (((y) << pos) & ((~(0xffffffff << len)) << pos))))) - -/* API functions */ -uint32_t io_i2c_slave_open(uint32_t dev_id) -{ - i2c_info_pt dev; - uint32_t h = 0; - - if ((0 != i2c_handles[0]) || (dev_id != 0)) { /* device still open or non-zero id */ - return 1; - } - i2c_handles[0] = &i2c_slave_devs[0]; - dev = i2c_handles[0]; - - /* enable clock; replicate code to make sure i2c enable is 255+ cycles later (see databook) */ - for (h = 0; h != 255; h++) { - REG_WRITE(I2C_CLKEN, 0x1); - } - - /* mask all interrupts */ - REG_WRITE(I2C_INTR_MASK, 0); - /* get stop detect interrupt only when addressed */ - REG_WRITE(I2C_CON, (REG_READ(I2C_CON) | (0x1 << 7))); - - /* initialize */ - dev->handling_tx = dev->handling_rx = 0; - dev->tx_data = dev->rx_data = NULL; - - /* set interrupt vector, mid/high priority */ - _setvecti(dev->vector_err, dev->isr_err); - _setvecti(dev->vector_rx_avail, dev->isr_rx_avail); - _setvecti(dev->vector_tx_req, dev->isr_tx_req); - _setvecti(dev->vector_stop_det, dev->isr_stop_det); - _setvecti(dev->vector_restart_det, dev->isr_stop_det); - _setvecti(dev->vector_rd_req, dev->isr_rd_req); - -#ifdef __Xdmac - dev->dmarxdescriptor = &i2c_dmarx_descriptors[4 * 0]; - dev->dmatxdescriptor = &i2c_dmatx_descriptors[8 * 0]; - - if (dev->dmarxchanid != DMA_NONE) { - dev->dmarxdescriptor[1] = dev->reg_base + I2C_DATA_CMD; - dev->dmarxdescriptor[3] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, dev->isr_rx_avail); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, dev->isr_err); - } - - if (dev->dmatxchanid != DMA_NONE) { /* one descriptor only */ - dev->dmatxdescriptor[2] = dev->reg_base + I2C_DATA_CMD; - dev->dmatxdescriptor[3] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, dev->isr_tx_req); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, dev->isr_err); - } -#endif - - /* enable device */ - REG_WRITE(I2C_ENABLE, 0x1); - - /* unmask interrupt: stop-detect, rd-req, rx-over, tx-abort */ - REG_WRITE(I2C_INTR_MASK, - R_STOP_DET | R_RD_REQ | R_RX_OVER | R_TX_ABRT); - - return 0; -} - -void io_i2c_slave_close(uint32_t dev_id) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - - /* clear all interrupts */ - REG_WRITE(I2C_INTR_MASK, 0); - REG_READ(I2C_CLR_INTR); - - /* disable */ - REG_WRITE(I2C_ENABLE, 0); - - /* reset regs */ - REG_WRITE(I2C_CON, 0x4); - REG_WRITE(I2C_SAR, 0); - REG_WRITE(I2C_RX_TL, 0); - REG_WRITE(I2C_TX_TL, 0); - REG_WRITE(I2C_SDA_HOLD, 0x1); - REG_WRITE(I2C_SDA_SETUP, 0x64); - REG_WRITE(I2C_FS_SPKLEN, 0x1); - - /* gate the I2C clock */ - REG_WRITE(I2C_CLKEN, 0); - - _setvecti(dev->vector_err, NULL); - _setvecti(dev->vector_rx_avail, NULL); - _setvecti(dev->vector_tx_req, NULL); - _setvecti(dev->vector_stop_det, NULL); - _setvecti(dev->vector_restart_det, NULL); - _setvecti(dev->vector_rd_req, NULL); - -#ifdef __Xdmac - if (dev->dmarxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmarxchanid); - } - - if (dev->dmatxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmatxchanid); - } -#endif - - dev->rx_cb = NULL; - dev->tx_cb = NULL; - dev->err_cb = NULL; - - i2c_handles[dev_id] = 0; -} - -void io_i2c_slave_read(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t cnt = 0, h = 0, val = 0, avail = 0; - - dev->rx_data = data; - dev->rx_size = *size; - dev->rx_count = 0; - dev->p_rxsize = size; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - - /* mask stop-condition interrupt (to prevent stop-det ISR from interrupting) */ - val = REG_READ(I2C_INTR_MASK); - REG_WRITE(I2C_INTR_MASK, (val & ~R_STOP_DET)); - - if (dev->handling_rx == 0) { - dev->handling_rx = 1; - dev->stop_detected = 0; - - /* unmask interrupt: rx threshold (rx-full) */ - val = REG_READ(I2C_INTR_MASK) | R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); - } else { - /* RX already in progress, due to earlier read() calls */ - if (dev->stop_detected == 0) { - /* unmask interrupts: rx threshold (rx-full) and stop-condition */ - val = REG_READ(I2C_INTR_MASK) | R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); - } else { - /* there is data in the rx-fifo remaining: read it */ - cnt = dev->rx_size - dev->rx_count; - avail = REG_READ(I2C_RXFLR); - - if (cnt >= avail) { /* after reading, all data processed, rx buffer not completely filled */ - cnt = avail; - dev->handling_rx = 0; - } - for (h = 0; h != cnt; h++) { - dev->rx_data[dev->rx_count++] = REG_READ(I2C_DATA_CMD); - } - if (dev->handling_rx == 0) { - if (dev->rx_size != dev->rx_count) { /* read buffer NOT completely filled */ - *(dev->p_rxsize) = dev->rx_count; - } - } - - /* slave rx done */ - dev->rx_data = NULL; - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - } - } - - /* unmask stop-condition interrupt again */ - val = REG_READ(I2C_INTR_MASK) | R_STOP_DET; - REG_WRITE(I2C_INTR_MASK, val); -#ifdef __Xdmac -} else { /* DMA: create descriptor */ - uint32_t threshold; - - dev->handling_rx = 1; - dev->stop_detected = 0; - - if (*size != 0) { - /* rx data available; at least one, more is uncertain */ - threshold = REG_READ(I2C_RX_TL); - dev->dmarxdescriptor[0] = - I2C_SLV_DMA_RX_CTRL | ((threshold + 1) << - I2C_SLV_DMA_CTRL_XFER_POS) | ((*size - - - 1) << - I2C_SLV_DMA_CTRL_SIZE_POS); - dev->dmarxdescriptor[2] = (uint32_t) data + (*size - 1); - - /* init dma */ - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmarxchanid), 1); - } -} -#endif - -} - -void io_i2c_slave_write(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t cnt = 0, h = 0, val = 0, free = 0; - - dev->tx_data = data; - dev->tx_size = *size; - dev->tx_count = 0; - dev->p_txsize = size; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* mask read request interrupt (to prevent read request ISR from interrupting) */ - val = REG_READ(I2C_INTR_MASK); - REG_WRITE(I2C_INTR_MASK, (val & ~R_RD_REQ)); - - if (dev->handling_tx == 0) { - dev->handling_tx = 1; - dev->rd_req_detected = 0; - } else { - /* TX already in progress, due to earlier write() calls */ - if (dev->rd_req_detected != 0) { - /* there is space in the tx-fifo remaining: fill it */ - cnt = dev->tx_size - dev->tx_count; - free = dev->fifo_depth - REG_READ(I2C_TXFLR); - if (cnt > free) { - cnt = free; - } - for (h = 0; h != cnt; h++) { - REG_WRITE(I2C_DATA_CMD, - (dev->tx_data[dev->tx_count++])); - } - - if (dev->tx_size == dev->tx_count) { /* write buffer completely emptied */ - dev->tx_data = NULL; - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - } - - /* unmask interrupt: tx-threshold (tx-empty) */ - val = REG_READ(I2C_INTR_MASK) | R_TX_EMPTY; - REG_WRITE(I2C_INTR_MASK, val); - } - } - - /* unmask rd-req interrupt again */ - val = REG_READ(I2C_INTR_MASK) | R_RD_REQ; - REG_WRITE(I2C_INTR_MASK, val); -#ifdef __Xdmac -} else { /* DMA: create descriptor */ - uint32_t threshold; - - dev->handling_tx = 1; - dev->rd_req_detected = 0; - - if (*size != 0) { - /* tx data available; at least one, more is uncertain */ - threshold = REG_READ(I2C_TX_TL); - dev->dmatxdescriptor[0] = - I2C_SLV_DMA_TX_CTRL | ((dev->fifo_depth - threshold) << - I2C_SLV_DMA_CTRL_XFER_POS) | ((*size - - - 1) << - I2C_SLV_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[1] = (uint32_t) data + (*size - 1); - - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - } -} -#endif - -} - -void io_i2c_slave_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t data = 0, enable = 0; - - switch (cmd) { - case IO_SET_CB_RX: - dev->rx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_TX: - dev->tx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_ERR: - dev->err_cb = ((io_cb_t *) arg)->cb; - break; - - default: - { - enable = REG_READ(I2C_ENABLE); - REG_WRITE(I2C_ENABLE, (enable & ~(0x1))); - - switch (cmd) { - case IO_I2C_SLAVE_SET_HOLD_TIME_RX: - data = REG_READ(I2C_SDA_HOLD); - REG_WRITE_BITS(I2C_SDA_HOLD, data, *((uint32_t *) arg), 8, - 16); - break; - case IO_I2C_SLAVE_SET_HOLD_TIME_TX: - data = REG_READ(I2C_SDA_HOLD); - REG_WRITE_BITS(I2C_SDA_HOLD, data, *((uint32_t *) arg), 16, - 0); - break; - case IO_I2C_SLAVE_SET_10BIT_ADDR: - data = REG_READ(I2C_CON); - REG_WRITE_BITS(I2C_CON, data, *((uint32_t *) arg), 1, 3); - break; - - case IO_I2C_SLAVE_SET_SETUP_TIME: - REG_WRITE(I2C_SDA_SETUP, *((uint32_t *) arg)); - break; - case IO_I2C_SLAVE_SET_SPKLEN: - REG_WRITE(I2C_FS_SPKLEN, *((uint32_t *) arg)); - break; - case IO_I2C_SLAVE_SET_ADDR: - REG_WRITE(I2C_SAR, *((uint32_t *) arg)); - break; - case IO_I2C_SLAVE_SET_RX_THRESHOLD: - REG_WRITE(I2C_RX_TL, *((uint32_t *) arg)); - break; - case IO_I2C_SLAVE_SET_TX_THRESHOLD: - REG_WRITE(I2C_TX_TL, *((uint32_t *) arg)); - break; - - default: - break; - } - - while ((0x1 & REG_READ(I2C_ENABLE_STATUS)) != 0) { - ; - } - enable = REG_READ(I2C_ENABLE); - REG_WRITE(I2C_ENABLE, (enable | 0x1)); - - break; - } - } -} - -static _Interrupt void i2c_slv0_err_ISR() -{ - uint32_t dev_id = 0; - i2c_info_pt dev = i2c_handles[dev_id]; - - if (REG_READ(I2C_CLR_RX_OVER)) { - if (NULL != dev->err_cb) { - dev->err_cb(0); - } - } - - if (REG_READ(I2C_CLR_TX_ABRT)) { - /* must be reception of read command (rd_req) while tx-fifo non-empty: results in flush of fifo */ - } -} - -static _Interrupt void i2c_slv0_rx_avail_ISR() -{ - uint32_t dev_id = 0; - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t cnt = 0, h = 0, val = 0, avail = 0; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* read data from fifo */ - cnt = dev->rx_size - dev->rx_count; - avail = REG_READ(I2C_RXFLR); - if (cnt > avail) { - cnt = avail; - } - for (h = 0; h != cnt; h++) { - dev->rx_data[dev->rx_count++] = REG_READ(I2C_DATA_CMD); - } - if (dev->rx_size == dev->rx_count) { /* read buffer completely filled */ - dev->rx_data = NULL; - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - - /* mask rx-avail interrupt */ - val = REG_READ(I2C_INTR_MASK) & ~R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); - } -#ifdef __Xdmac -} else { - /* DMA RX xfer done */ - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - _dma_int_clear((0x1 << dev->dmarxchanid)); - - /* call user callback function, if any */ - dev->rx_data = NULL; - if (dev->rx_cb != NULL) { - dev->rx_cb(dev_id); - } -} -#endif -} - -static _Interrupt void i2c_slv0_tx_req_ISR() -{ - uint32_t dev_id = 0; - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t cnt = 0, h = 0, val = 0, free = 0; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* write data into fifo */ - cnt = dev->tx_size - dev->tx_count; - free = dev->fifo_depth - REG_READ(I2C_TXFLR); - if (cnt > free) { - cnt = free; - } - for (h = 0; h != cnt; h++) { - REG_WRITE(I2C_DATA_CMD, (dev->tx_data[dev->tx_count++])); - } - if (dev->tx_size == dev->tx_count) { - /* write buffer completely emptied */ - dev->tx_data = NULL; - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - - /* mask tx-threshold (tx-empty) */ - val = REG_READ(I2C_INTR_MASK) & ~R_TX_EMPTY; - REG_WRITE(I2C_INTR_MASK, val); - } -#ifdef __Xdmac -} else { - /* DMA TX xfer done */ - _dma_chan_enable((0x1 << dev->dmatxchanid), 0); - _dma_int_clear((0x1 << dev->dmatxchanid)); - - /* call user callback function, if any */ - dev->tx_data = NULL; - if (dev->tx_cb != NULL) { - dev->tx_cb(dev_id); - } -} -#endif -} - -static _Interrupt void i2c_slv0_stop_det_ISR() -{ - uint32_t dev_id = 0; - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t cnt = 0, h = 0, val = 0, avail = 0; - - if (dev->handling_rx == 1) { - avail = REG_READ(I2C_RXFLR); - - if (dev->rx_data == NULL) { - if (avail == 0) { /* all data processed */ - dev->handling_rx = 0; - } else { /* still data in fifo to process, new data will not become available anymore */ - dev->stop_detected = 1; - } - } else { -#ifdef __Xdmac - if (dev->dmarxchanid != DMA_NONE) { /* disable DMA transfer and determine how much data has been transferred */ - uint32_t ctrl; - - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - _dma_chan_desc_get_ctrl(dev->dmarxchanid, &ctrl); - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc_get_ctrl(dev->dmarxchanid, &ctrl); - } else { - _dma_chan_desc_aux_get_ctrl(dev->dmarxchanid, &ctrl); - } - dev->rx_count = - ((dev->rx_size - 1) - - ((ctrl >> I2C_SLV_DMA_CTRL_SIZE_POS) & 0x1fff)); - } -#endif - /* read remaining data from fifo */ - cnt = dev->rx_size - dev->rx_count; - if (cnt < avail) { /* after reading, still data in fifo to process, new data will not become available anymore */ - dev->stop_detected = 1; - } else if (cnt == avail) { /* after reading, all data processed */ - dev->handling_rx = 0; - } else { /* after reading, all data processed, rx buffer not completely filled */ - cnt = avail; - dev->handling_rx = 0; - } - for (h = 0; h != cnt; h++) { - dev->rx_data[dev->rx_count++] = REG_READ(I2C_DATA_CMD); - } - if (dev->handling_rx == 0) { - if (dev->rx_size != dev->rx_count) { /* read buffer NOT completely filled */ - *(dev->p_rxsize) = dev->rx_count; - } - } - - /* slave rx done */ - dev->rx_data = NULL; - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - } - - /* mask rx-avail interrupt, if not done yet */ - val = REG_READ(I2C_INTR_MASK) & ~R_RX_FULL; - REG_WRITE(I2C_INTR_MASK, val); - } - - if (dev->handling_tx == 1) { - dev->handling_tx = 0; - - if (dev->tx_data != NULL) { - /* slave tx done */ - *(dev->p_txsize) = dev->tx_count - REG_READ(I2C_TXFLR); - - dev->tx_data = NULL; - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - } - - } - - REG_READ(I2C_CLR_STOP_DET); -} - -static _Interrupt void i2c_slv0_rd_req_ISR() -{ - uint32_t dev_id = 0; - i2c_info_pt dev = i2c_handles[dev_id]; - uint32_t cnt = 0, h = 0, val = 0; - - if (dev->tx_data != NULL) { - dev->rd_req_detected = 1; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* write data into (empty) fifo */ - cnt = dev->tx_size - dev->tx_count; - if (cnt > dev->fifo_depth) { - cnt = dev->fifo_depth; - } - - for (h = 0; h != cnt; h++) { - REG_WRITE(I2C_DATA_CMD, (dev->tx_data[dev->tx_count++])); - } - - if (dev->tx_size == dev->tx_count) { /* write buffer completely emptied */ - dev->tx_data = NULL; - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - } else { - /* unmask interrupts: tx-threshold (tx-empty) */ - val = REG_READ(I2C_INTR_MASK) | R_TX_EMPTY; - REG_WRITE(I2C_INTR_MASK, val); - } -#ifdef __Xdmac - } else { /* have DMAC fill the fifo */ - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - } -#endif - } else { - /* no data available for tx --> the only thing to do is returning any data */ - REG_WRITE(I2C_DATA_CMD, 0xff); - } - - REG_READ(I2C_CLR_RD_REQ); -} - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/ss_i2c_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/ss_i2c_master.c deleted file mode 100644 index bba8211e..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/iic/ss_i2c_master.c +++ /dev/null @@ -1,491 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include "embARC_error.h" -#include "embARC_toolchain.h" -#include "arc/arc_exception.h" - -#include "device/subsystem/i2c_master.h" -#include "device/subsystem/ss_i2c_master.h" -#include "device/subsystem/i2c_priv.h" - -#define REG_READ(x) arc_aux_read((ctx->reg_base + x)) -#define REG_WRITE(x, y) arc_aux_write((ctx->reg_base + x), y) - -/** - * @fn int32_t ss_iic_master_putready(SS_IIC_MASTER_DEV_CONTEXT *ctx) - * @brief Test whether iic is ready to write, 1 ready, 0 not ready - */ -Inline int32_t ss_iic_master_putready(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - uint32_t status = REG_READ(I2C_STATUS); - - return ((status & IC_STATUS_TFNF) != 0); -} - -/** - * @fn int32_t ss_iic_master_getready(SS_IIC_MASTER_DEV_CONTEXT *ctx) - * @brief test whether iic is ready to receive, 1 ready, 0 not ready - */ -Inline int32_t ss_iic_master_getready(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - uint32_t status = REG_READ(I2C_STATUS); - - return ((status & IC_STATUS_RFNE) != 0); -} - -/** - * @fn void ss_iic_mask_interrupt(SS_IIC_MASTER_DEV_CONTEXT *ctx, uint32_t mask) - * @brief Mask iic interrupt - */ -Inline void ss_iic_mask_interrupt(SS_IIC_MASTER_DEV_CONTEXT *ctx, uint32_t mask) -{ - uint32_t intr_mask = REG_READ(I2C_INTR_MASK); - - REG_WRITE(I2C_INTR_MASK, intr_mask & (~mask)); -} - -static void ss_iic_master_enable_device(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - DEV_IIC_INFO *info = ctx->info; - uint32_t enable = REG_READ(I2C_ENABLE); - - if (((enable & 0x1) & DEV_ENABLED) == 0) { - REG_WRITE(I2C_ENABLE, (enable | 0x1)); - info->status |= DEV_ENABLED; - } -} - -static void ss_iic_master_disable_device(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - uint32_t enable = REG_READ(I2C_ENABLE); - - REG_WRITE(I2C_ENABLE, (enable & (~(0x1)))); - - while ((0x1 & REG_READ(I2C_ENABLE_STATUS)) != 0) { - ; - } -} - -/* reset IIC master */ -static void ss_iic_master_reset_device(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - - DEV_IIC_INFO *info = ctx->info; - - io_i2c_master_close(ctx->dev_id); - info->next_cond = IIC_MODE_STOP; - info->cur_state = IIC_FREE; - info->err_state = IIC_ERR_NONE; - ctx->flags = 0; - - io_i2c_master_open(ctx->dev_id); -} - -/** disable iic master interrupt for transmit or receive */ -static void ss_iic_master_dis_cbr(SS_IIC_MASTER_DEV_CONTEXT *ctx, uint32_t cbrtn) -{ - switch (cbrtn) { - case SS_IIC_MASTER_RDY_SND: - ss_iic_mask_interrupt(ctx, R_TX_EMPTY); - break; - case SS_IIC_MASTER_RDY_RCV: - ss_iic_mask_interrupt(ctx, R_TX_EMPTY | R_RX_FULL); - break; - default: - break; - } -} - -/** - * @fn void ss_iic_master_flush_tx(SS_IIC_MASTER_DEV_CONTEXT *ctx) - * @brief flush TX FIFO - */ -Inline void ss_iic_master_flush_tx(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - -} - -/** - * @fn int32_t ss_iic_master_flush_rx(SS_IIC_MASTER_DEV_CONTEXT *ctx) - * @brief Flush RX FIFO - */ -Inline void ss_iic_master_flush_rx(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - -} - -/** - * @fn uint32_t ss_iic_master_get_txavail(SS_IIC_MASTER_DEV_CONTEXT *ctx) - * @brief Get available transmit FIFO count - */ -Inline uint32_t ss_iic_master_get_txavail(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - uint32_t flr = REG_READ(I2C_TXFLR); - - return (int32_t)(IC_TX_RX_FIFO_SIZE - flr); -} - -/** - * @fn ss_iic_master_get_rxavail(SS_IIC_MASTER_DEV_CONTEXT *ctx) - * @brief Get available receive FIFO count - */ -Inline uint32_t ss_iic_master_get_rxavail(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - uint32_t flr = REG_READ(I2C_RXFLR); - - return (int32_t)flr; -} - -int32_t ss_iic_master_close(SS_IIC_MASTER_DEV_CONTEXT *ctx) -{ - int32_t ret = E_OK; - - DEV_IIC_INFO *info = ctx->info; - - if (info->opn_cnt > 0) { - info->opn_cnt = 0; - io_i2c_master_close(ctx->dev_id); - int_disable(ctx->int_err); - int_disable(ctx->int_rx_avail); - int_disable(ctx->int_tx_req); - int_disable(ctx->int_stop_det); - } else { - ret = E_CLSED; - } - - return ret; -} - -int32_t ss_iic_master_control(SS_IIC_MASTER_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - uint32_t val32; - uint32_t arg; - uint32_t dev_id = ctx->dev_id; - DEV_IIC_INFO *iic_info_ptr = ctx->info; - io_cb_t callback; - - switch (ctrl_cmd) { - case IIC_CMD_GET_STATUS: - SS_IIC_MASTER_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = iic_info_ptr->status; - break; - case IIC_CMD_ENA_DEV: - ss_iic_master_enable_device(ctx); - break; - case IIC_CMD_DIS_DEV: - ss_iic_master_disable_device(ctx); - break; - case IIC_CMD_RESET: - ss_iic_master_reset_device(ctx); - break; - case IIC_CMD_FLUSH_TX: - ss_iic_master_flush_tx(ctx); - break; - case IIC_CMD_FLUSH_RX: - ss_iic_master_flush_rx(ctx); - break; - case IIC_CMD_SET_ADDR_MODE: - val32 = (uint32_t)param; - SS_IIC_MASTER_CHECK_EXP((val32 == IIC_7BIT_ADDRESS) || (val32 == IIC_10BIT_ADDRESS), E_PAR); - if (val32 == IIC_10BIT_ADDRESS) { - arg = 1; - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_10BIT_ADDR, &arg); - iic_info_ptr->addr_mode = IIC_10BIT_ADDRESS; - } else { - arg = 0; - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_10BIT_ADDR, &arg); - iic_info_ptr->addr_mode = IIC_7BIT_ADDRESS; - } - iic_info_ptr->addr_mode = val32; - break; - case IIC_CMD_GET_RXAVAIL: - SS_IIC_MASTER_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = ss_iic_master_get_rxavail(ctx); - break; - case IIC_CMD_GET_TXAVAIL: - SS_IIC_MASTER_CHECK_EXP((param != NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = ss_iic_master_get_txavail(ctx); - break; - case IIC_CMD_SET_TXCB: - SS_IIC_MASTER_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - callback.cb = param; - io_i2c_master_ioctl(dev_id, IO_SET_CB_TX, &callback); - break; - case IIC_CMD_SET_RXCB: - SS_IIC_MASTER_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - callback.cb = param; - io_i2c_master_ioctl(dev_id, IO_SET_CB_RX, &callback); - break; - case IIC_CMD_SET_ERRCB: - SS_IIC_MASTER_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - callback.cb = param; - io_i2c_master_ioctl(dev_id, IO_SET_CB_ERR, &callback); - break; - case IIC_CMD_ABORT_TX: - ercd = E_NOSPT; - break; - case IIC_CMD_ABORT_RX: - ercd = E_NOSPT; - break; - case IIC_CMD_SET_TXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - ss_iic_master_dis_cbr(ctx, SS_IIC_MASTER_RDY_SND); - } else { - ss_iic_master_dis_cbr(ctx, SS_IIC_MASTER_RDY_SND); - } - break; - case IIC_CMD_SET_RXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - ss_iic_master_dis_cbr(ctx, SS_IIC_MASTER_RDY_RCV); - } else { - ss_iic_master_dis_cbr(ctx, SS_IIC_MASTER_RDY_RCV); - } - break; - case IIC_CMD_SET_TXINT_BUF: - ercd = E_NOSPT; - break; - case IIC_CMD_SET_RXINT_BUF: - ercd = E_NOSPT; - break; - case IIC_CMD_MST_SET_SPEED_MODE: - val32 = (uint32_t)param; - SS_IIC_MASTER_CHECK_EXP((val32 >= IIC_SPEED_STANDARD) && (val32 <= IIC_SPEED_FAST), E_PAR); - if (val32 == IIC_SPEED_STANDARD) { - arg = 1; - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_SPEED, &arg); - iic_info_ptr->speed_mode = IIC_SPEED_STANDARD; - } else { - arg = 2; - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_SPEED, &arg); - iic_info_ptr->speed_mode = IIC_SPEED_FAST; - } - break; - case IIC_CMD_MST_SET_TAR_ADDR: - if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) { - val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK; - } else { - val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK; - } - if (val32 != iic_info_ptr->tar_addr) { - arg = val32; - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_TARGET_ADDR, &arg); - iic_info_ptr->tar_addr = val32; - } - break; - case IIC_CMD_MST_SET_NEXT_COND: - val32 = (uint32_t) param; - if (val32 == IIC_MODE_STOP) { - arg = I2C_STOP_CMD; - } else if (val32 == IIC_MODE_RESTART) { - arg = I2C_RESTART_CMD; - } else { - arg = 0; - } - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_NEXT_COND, &arg); - break; - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/* param: speed mode, 1-standard mode, 2-fast mode, 2 as default in hardware */ -int32_t ss_iic_master_open(SS_IIC_MASTER_DEV_CONTEXT *ctx, uint32_t param) -{ - int32_t ercd = E_OK; - uint32_t dev_id = ctx->dev_id; - DEV_IIC_INFO *info = ctx->info; - io_cb_t callback; - int32_t int_e = 0; - uint32_t arg; - - SS_IIC_MASTER_CHECK_EXP((param >= IIC_SPEED_STANDARD) && (param <= IIC_SPEED_FAST), E_PAR); - - if (info->opn_cnt == 0) { - SS_IIC_MASTER_CHECK_EXP(io_i2c_master_open(dev_id) == 0, E_SYS); - - if (param == IIC_SPEED_STANDARD) { - arg = 1; - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_SPEED, &arg); - info->speed_mode = IIC_SPEED_STANDARD; - } else { - arg = 2; - io_i2c_master_ioctl(dev_id, IO_I2C_MASTER_SET_SPEED, &arg); - info->speed_mode = IIC_SPEED_FAST; - } - - callback.cb = (IO_CB_FUNC)ctx->int_rx_cb; - io_i2c_master_ioctl(dev_id, IO_SET_CB_RX, &callback); - callback.cb = (IO_CB_FUNC)ctx->int_tx_cb; - io_i2c_master_ioctl(dev_id, IO_SET_CB_TX, &callback); - callback.cb = (IO_CB_FUNC)ctx->int_err_cb; - io_i2c_master_ioctl(dev_id, IO_SET_CB_ERR, &callback); - - info->opn_cnt++; - info->addr_mode = IIC_7BIT_ADDRESS; - info->mode = DEV_MASTER_MODE; - info->tar_addr &= IIC_7BIT_ADDRESS_MASK; - - ctx->flags = 0; - - /* enable interrupt */ - int_e = int_e | int_enable(ctx->int_err); - int_e = int_e | int_enable(ctx->int_rx_avail); - int_e = int_e | int_enable(ctx->int_tx_req); - int_e = int_e | int_enable(ctx->int_stop_det); - - if (int_e != 0) { - ercd = E_PAR; - } - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -int32_t ss_iic_master_write(SS_IIC_MASTER_DEV_CONTEXT *ctx, const void *data, uint32_t len) -{ - uint32_t xlen; - uint32_t dev_id = ctx->dev_id; - - if (ctx->flags) { - return E_NORES; - } - - if (arc_locked()) { - /* - * not allow to be called in isr or cpu is locked. - * because the bottom driver is simply interrupt driven - */ - return E_SYS; - } - - xlen = len; - - ctx->flags = SS_IIC_MASTER_FLAG_TX; - - io_i2c_master_write(dev_id, (uint8_t *)data, &xlen); - - /* wait finished: i2c master int enable & no cpu lock */ - while (ctx->flags & SS_IIC_MASTER_FLAG_TX) { - ; - } - - if (ctx->flags & SS_IIC_MASTER_FLAG_ERROR) { - ctx->flags = 0; - return E_SYS; - } - - ctx->flags = 0; - - return len; -} - -int32_t ss_iic_master_read(SS_IIC_MASTER_DEV_CONTEXT *ctx, const void *data, uint32_t len) -{ - uint32_t xlen; - uint32_t dev_id = ctx->dev_id; - - if (ctx->flags) { - return E_NORES; - } - - if (arc_locked()) { - /* - * not allow to be called in isr or cpu is locked. - * because the bottom driver is simply interrupt driven - */ - return E_SYS; - } - - xlen = len; - - ctx->flags = SS_IIC_MASTER_FLAG_RX; - - io_i2c_master_read(dev_id, (uint8_t *)data, &xlen); - - /* wait finished: i2c master int enable & no cpu lock */ - while (ctx->flags & SS_IIC_MASTER_FLAG_RX) { - ; - } - - if (ctx->flags & SS_IIC_MASTER_FLAG_ERROR) { - ctx->flags = 0; - return E_SYS; - } - - ctx->flags = 0; - - return len; -} - -void ss_iic_master_tx_cb(SS_IIC_MASTER_DEV_CONTEXT *ctx, void *param) -{ - DEV_IIC_INFO *info = ctx->info; - - if (ctx->flags & SS_IIC_MASTER_FLAG_TX) { - ctx->flags &= ~SS_IIC_MASTER_FLAG_TX; - if (info->iic_cbs.tx_cb) { - info->iic_cbs.tx_cb(info); - } - } -} - -void ss_iic_master_rx_cb(SS_IIC_MASTER_DEV_CONTEXT *ctx, void *param) -{ - DEV_IIC_INFO *info = ctx->info; - - if (ctx->flags & SS_IIC_MASTER_FLAG_RX) { - ctx->flags &= ~SS_IIC_MASTER_FLAG_RX; - if (info->iic_cbs.rx_cb) { - info->iic_cbs.rx_cb(info); - } - } -} - -void ss_iic_master_err_cb(SS_IIC_MASTER_DEV_CONTEXT *ctx, void *param) -{ - DEV_IIC_INFO *info = ctx->info; - - ctx->flags |= SS_IIC_MASTER_FLAG_ERROR; - - if (info->iic_cbs.err_cb) { - info->iic_cbs.err_cb(info); - } -} \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/spi_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/spi_master.c deleted file mode 100644 index ec0912b3..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/spi_master.c +++ /dev/null @@ -1,1034 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/spi_master.h" -#include "device/subsystem/spi_priv.h" -#include "io_config.h" -#include "apexextensions.h" - -#ifdef IO_SPI_MST0_PRESENT -#define SPI_DEV_PRESENT -#endif -#ifdef IO_SPI_MST1_PRESENT -#define SPI_DEV_PRESENT -#endif -#ifdef IO_SPI_MST2_PRESENT -#define SPI_DEV_PRESENT -#endif -#ifdef IO_SPI_MST3_PRESENT -#define SPI_DEV_PRESENT -#endif - -#ifdef SPI_DEV_PRESENT - -#define SPI_MAX_CNT (4) - -static void spi_mst_rx_ISR_proc(uint32_t dev_id); -static void spi_mst_tx_ISR_proc(uint32_t dev_id); -static void spi_mst_idle_ISR_proc(uint32_t dev_id); -static void spi_mst_err_ISR_proc(uint32_t dev_id); - -#ifdef IO_SPI_MST0_PRESENT -static _Interrupt void spi_mst0_rx_ISR() -{ - spi_mst_rx_ISR_proc(0); -} - -static _Interrupt void spi_mst0_tx_ISR() -{ - spi_mst_tx_ISR_proc(0); -} - -static _Interrupt void spi_mst0_idle_ISR() -{ - spi_mst_idle_ISR_proc(0); -} - -static _Interrupt void spi_mst0_err_ISR() -{ - spi_mst_err_ISR_proc(0); -} -#endif -#ifdef IO_SPI_MST1_PRESENT -static _Interrupt void spi_mst1_rx_ISR() -{ - spi_mst_rx_ISR_proc(1); -} - -static _Interrupt void spi_mst1_tx_ISR() -{ - spi_mst_tx_ISR_proc(1); -} - -static _Interrupt void spi_mst1_idle_ISR() -{ - spi_mst_idle_ISR_proc(1); -} - -static _Interrupt void spi_mst1_err_ISR() -{ - spi_mst_err_ISR_proc(1); -} -#endif -#ifdef IO_SPI_MST2_PRESENT -static _Interrupt void spi_mst2_rx_ISR() -{ - spi_mst_rx_ISR_proc(2); -} - -static _Interrupt void spi_mst2_tx_ISR() -{ - spi_mst_tx_ISR_proc(2); -} - -static _Interrupt void spi_mst2_idle_ISR() -{ - spi_mst_idle_ISR_proc(2); -} - -static _Interrupt void spi_mst2_err_ISR() -{ - spi_mst_err_ISR_proc(2); -} -#endif -#ifdef IO_SPI_MST3_PRESENT -static _Interrupt void spi_mst3_rx_ISR() -{ - spi_mst_rx_ISR_proc(3); -} - -static _Interrupt void spi_mst3_tx_ISR() -{ - spi_mst_tx_ISR_proc(3); -} - -static _Interrupt void spi_mst3_idle_ISR() -{ - spi_mst_idle_ISR_proc(3); -} - -static _Interrupt void spi_mst3_err_ISR() -{ - spi_mst_err_ISR_proc(3); -} -#endif - -static void fill_txfifo(spi_info_pt dev); -static void retrieve_rxfifo(spi_info_pt dev); - -#ifdef __Xdmac -static void create_dma_descriptors_rx(spi_info_pt dev, uint32_t burst, - uint8_t idx); -static void create_dma_descriptors_tx(spi_info_pt dev, uint32_t burst, - uint8_t idx); -#endif - -/* SPI master devices private data structures */ -static spi_info_pt spi_handles[SPI_MAX_CNT] = { 0 }; - -#ifdef __Xdmac -static _Uncached uint32_t spi_dmarx_descriptors[8 * SPI_MAX_CNT]; -static _Uncached uint32_t spi_dmatx_descriptors[8 * SPI_MAX_CNT]; -#endif - -static spi_info_t spi_master_devs[] = { -#ifdef IO_SPI_MST0_PRESENT - { .instID = 0, - .reg_base = AR_IO_SPI_MST0_CTRLR0, -#ifdef IO_SPI_MST0_DMA_RX - .dmarxchanid = IO_SPI_MST0_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_MST0_DMA_TX - .dmatxchanid = IO_SPI_MST0_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_MST0_INT_RX_AVAIL, - .tx_vector = IO_SPI_MST0_INT_TX_REQ, - .idle_vector = IO_SPI_MST0_INT_IDLE, - .err_vector = IO_SPI_MST0_INT_ERR, - .rx_isr = spi_mst0_rx_ISR, - .tx_isr = spi_mst0_tx_ISR, - .idle_isr = spi_mst0_idle_ISR, - .err_isr = spi_mst0_err_ISR, - .log_xfer_size = (IO_SPI_MST0_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_MST0_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_MST0_FS }, -#endif -#ifdef IO_SPI_MST1_PRESENT - { .instID = 1, - .reg_base = AR_IO_SPI_MST1_CTRLR0, -#ifdef IO_SPI_MST1_DMA_RX - .dmarxchanid = IO_SPI_MST1_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_MST1_DMA_TX - .dmatxchanid = IO_SPI_MST1_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_MST1_INT_RX_AVAIL, - .tx_vector = IO_SPI_MST1_INT_TX_REQ, - .idle_vector = IO_SPI_MST1_INT_IDLE, - .err_vector = IO_SPI_MST1_INT_ERR, - .rx_isr = spi_mst1_rx_ISR, - .tx_isr = spi_mst1_tx_ISR, - .idle_isr = spi_mst1_idle_ISR, - .err_isr = spi_mst1_err_ISR, - .log_xfer_size = (IO_SPI_MST1_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_MST1_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_MST1_FS }, -#endif -#ifdef IO_SPI_MST2_PRESENT - { .instID = 2, - .reg_base = AR_IO_SPI_MST2_CTRLR0, -#ifdef IO_SPI_MST2_DMA_RX - .dmarxchanid = IO_SPI_MST2_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_MST2_DMA_TX - .dmatxchanid = IO_SPI_MST2_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_MST2_INT_RX_AVAIL, - .tx_vector = IO_SPI_MST2_INT_TX_REQ, - .idle_vector = IO_SPI_MST2_INT_IDLE, - .err_vector = IO_SPI_MST2_INT_ERR, - .rx_isr = spi_mst2_rx_ISR, - .tx_isr = spi_mst2_tx_ISR, - .idle_isr = spi_mst2_idle_ISR, - .err_isr = spi_mst2_err_ISR, - .log_xfer_size = (IO_SPI_MST2_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_MST2_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_MST2_FS }, -#endif -#ifdef IO_SPI_MST3_PRESENT - { .instID = 3, - .reg_base = AR_IO_SPI_MST3_CTRLR0, -#ifdef IO_SPI_MST3_DMA_RX - .dmarxchanid = IO_SPI_MST3_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_MST3_DMA_TX - .dmatxchanid = IO_SPI_MST3_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_MST3_INT_RX_AVAIL, - .tx_vector = IO_SPI_MST3_INT_TX_REQ, - .idle_vector = IO_SPI_MST3_INT_IDLE, - .err_vector = IO_SPI_MST3_INT_ERR, - .rx_isr = spi_mst3_rx_ISR, - .tx_isr = spi_mst3_tx_ISR, - .idle_isr = spi_mst3_idle_ISR, - .err_isr = spi_mst3_err_ISR, - .log_xfer_size = (IO_SPI_MST3_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_MST3_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_MST3_FS }, -#endif - { .instID = SPI_MAX_CNT } -}; - -#define REG_WRITE(reg, x) _sr((unsigned)(x), (unsigned)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((unsigned)(dev->reg_base + reg)) -#define REG_WRITE_BITS(reg, x, y, len, pos) REG_WRITE(reg, ((((x) & ~((~(0xffffffff << len)) << pos)) \ - | (((y) << pos) & ((~(0xffffffff << len)) << pos))))) -#define REG_GET_BITS(reg, len, pos) ((REG_READ(reg) >> pos) & ~(0xffffffff << len)) - -uint32_t io_spi_master_open(uint32_t dev_id) -{ - uint32_t h = 0; - spi_info_pt dev; - - h = 0; - while ((spi_master_devs[h].instID != dev_id) - && (spi_master_devs[h].instID != SPI_MAX_CNT)) { - h++; - } - if ((spi_master_devs[h].instID == SPI_MAX_CNT) || (0 != spi_handles[dev_id])) { /* dev_id not part of design, or still open */ - return 1; - } - spi_handles[dev_id] = &spi_master_devs[h]; - dev = spi_handles[dev_id]; - - /* enable clock */ - REG_WRITE(CLK_ENA, 0x1); - - if (dev->log_xfer_size == 1) { - REG_WRITE_BITS(CTRL0, 0x0, 15, 4, 0); - } else { /* log_xfer_size == 2 */ - REG_WRITE_BITS(CTRL0, 0x0, 31, 5, 16); - } - - /* mask RX-available, TX-empty ,and Idle interrupts */ - REG_WRITE(IMR, ~(R_TX_EMPTY | R_RX_FULL | R_IDLE)); - - dev->handling_rx = dev->handling_tx = 0; - - _setvecti(dev->rx_vector, dev->rx_isr); - _setvecti(dev->tx_vector, dev->tx_isr); - _setvecti(dev->idle_vector, dev->idle_isr); - _setvecti(dev->err_vector, dev->err_isr); - -#ifdef __Xdmac - dev->dmarxdescriptor = &spi_dmarx_descriptors[8 * h]; - dev->dmatxdescriptor = &spi_dmatx_descriptors[8 * h]; - - if (dev->dmarxchanid != DMA_NONE) { - dev->dmarxdescriptor[1] = dev->dmarxdescriptor[5] = - dev->reg_base + DR; - dev->dmarxdescriptor[3] = (uint32_t) &(dev->dmarxdescriptor[4]); - dev->dmarxdescriptor[7] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, dev->rx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, dev->err_isr); - } - - if (dev->dmatxchanid != DMA_NONE) { - dev->dmatxdescriptor[2] = dev->dmatxdescriptor[6] = - dev->reg_base + DR; - dev->dmatxdescriptor[3] = (uint32_t) &(dev->dmatxdescriptor[4]); - dev->dmatxdescriptor[7] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, dev->tx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, dev->err_isr); - } -#endif - - REG_WRITE(SPIEN, 0x1); - - return 0; -} - -void io_spi_master_close(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - - REG_WRITE(IMR, 0); - REG_WRITE(SPIEN, 0); - - REG_WRITE(CTRL0, 0x7); - REG_WRITE(CTRL1, 0); - REG_WRITE(SER, 0); - REG_WRITE(BAUDR, 0); - REG_WRITE(TXFTLR, 0); - REG_WRITE(RXFTLR, 0); - REG_WRITE(RX_SAMPLE_DLY, 0); - REG_WRITE(IMR, 0xff); - - /* gate clock */ - REG_WRITE(CLK_ENA, 0); - - _setvecti(dev->rx_vector, NULL); - _setvecti(dev->tx_vector, NULL); - _setvecti(dev->idle_vector, NULL); - _setvecti(dev->err_vector, NULL); - -#ifdef __Xdmac - if (dev->dmarxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmarxchanid); - } - - if (dev->dmatxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmatxchanid); - } -#endif - - dev->rx_cb = NULL; - dev->tx_cb = NULL; - dev->err_cb = NULL; - - spi_handles[dev_id] = 0; -} - -void io_spi_master_read(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - - dev->rx_size = *size; - dev->p_rxsize = size; - dev->rx_count = 0; - - dev->rx_buff = (void *) data; - - dev->handling_rx = 1; - - /* Configure the Number of Data frames to be received */ - REG_WRITE(SPIEN, 0); - val = - (dev->rx_size + (dev->log_xfer_size << 1) - - 1) >> dev->log_xfer_size; - REG_WRITE(CTRL1, (val - 1)); - while (REG_READ(SPIEN) != 0) { - ; - } - REG_WRITE(SPIEN, 0x1); - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - if (REG_GET_BITS(CTRL0, 2, 8) == SPI_RECEIVE_ONLY_MODE) { - /* Write dummy to trigger the transfer */ - REG_WRITE(DR, 0xdeadbeef); - - /* Enable RX-available and Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_RX_FULL | R_IDLE)); - } -#ifdef __Xdmac -} else { /* RX descriptor - postpone for SPI_TRANSMIT_RECEIVE_MODE, since size depends on tx-size */ - if ((dev->rx_size != 0) - && (REG_GET_BITS(CTRL0, 2, 8) != SPI_TRANSMIT_RECEIVE_MODE)) { - /* rx data available; at least one */ - create_dma_descriptors_rx(dev, (1 + REG_READ(RXFTLR)), 0); - if (dev->rx_size > (dev->rx_count << dev->log_xfer_size)) { - create_dma_descriptors_rx(dev, (1 + REG_READ(RXFTLR)), 4); - } - - /* init dma */ - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmarxchanid), 1); - - if (REG_GET_BITS(CTRL0, 2, 8) == SPI_RECEIVE_ONLY_MODE) { - /* Write dummy to trigger the transfer */ - REG_WRITE(DR, 0xdeadbeef); - } - } -} -#endif -} - -void io_spi_master_write(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - - dev->tx_size = *size; - dev->tx_count = 0; - dev->tx_buff = (void *) data; - - /* modify rx_size when in TXRX mode */ - if (REG_GET_BITS(CTRL0, 2, 8) == SPI_TRANSMIT_RECEIVE_MODE) { - /* if receive buffer not completely filled yet, it contains tx-size of data */ - if (dev->rx_size > dev->tx_size) { - dev->rx_size = *(dev->p_rxsize) = dev->tx_size; - } -#ifdef __Xdmac - if ((dev->dmatxchanid != DMA_NONE) && (dev->rx_size != 0)) { - /* create RX DMA descriptors, now the size is known */ - create_dma_descriptors_rx(dev, (1 + REG_READ(RXFTLR)), 0); - if (dev->rx_size > (dev->rx_count << dev->log_xfer_size)) { - create_dma_descriptors_rx(dev, (1 + REG_READ(RXFTLR)), 4); - } - - /* init dma */ - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmarxchanid), 1); - - } -#endif - } - - dev->handling_tx = 1; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* write first bytes to fifo, assuming size > 0 */ - fill_txfifo(dev); - - /* Enable TX-empty, Idle interrupt, and (optional) RX-available */ - if (REG_GET_BITS(CTRL0, 2, 8) == SPI_TRANSMIT_ONLY_MODE) { - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_TX_EMPTY | R_IDLE)); - } else { /* TX-RX mode or EEPROM mode */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_TX_EMPTY | R_IDLE | R_RX_FULL)); - } -#ifdef __Xdmac -} else { /* TX descriptor */ - if (*size != 0) { - /* tx data available; at least one, more is uncertain */ - create_dma_descriptors_tx(dev, - (dev->fifo_depth - REG_READ(TXFTLR)), - 0); - if (dev->tx_size > (dev->tx_count << dev->log_xfer_size)) { - create_dma_descriptors_tx(dev, - (dev->fifo_depth - - REG_READ(TXFTLR)), 4); - } - - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - } -} -#endif -} - -void io_spi_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t regval; - - switch (cmd) { - case IO_SET_CB_RX: - dev->rx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_TX: - dev->tx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_ERR: - dev->err_cb = ((io_cb_t *) arg)->cb; - break; - - case IO_SPI_MASTER_SET_SE: - REG_WRITE(SER, *((uint32_t *) arg)); - break; - case IO_SPI_MASTER_SET_RX_THRESHOLD: - REG_WRITE(RXFTLR, *((uint32_t *) arg)); - break; - case IO_SPI_MASTER_SET_TX_THRESHOLD: - REG_WRITE(TXFTLR, *((uint32_t *) arg)); - break; - case IO_SPI_MASTER_GET_XFER_SIZE: - *((uint32_t *) arg) = (8 << dev->log_xfer_size); - break; - - case IO_SPI_MASTER_SET_PACKING: - { /* DFS must be set before applying this option */ - if (*((uint32_t *) arg) == 0) { /* reset packing */ - dev->log_xfer_size = dev->max_xfer_size >> 4; - } else { /* set packing */ - regval = REG_READ(CTRL0); - if (dev->max_xfer_size == 32) { /* 32-bits SPI */ - regval = (regval >> 16) & 0x01F; // Get DFS field from CTRL0 value - dev->log_xfer_size = - (regval == 15) ? 1 : (regval == 7) ? 0 : 2; - } else { /* 16-bits SPI */ - regval = regval & 0x00F; // Get DFS field from CTRL0 value - dev->log_xfer_size = (regval == 7) ? 0 : 1; - } - } - break; - } - - default: - { - /* ioctl calls that require disabling of the SPI first */ - REG_WRITE(SPIEN, 0); - - regval = REG_READ(CTRL0); - switch (cmd) { - case IO_SPI_MASTER_SET_BAUD: - REG_WRITE(BAUDR, *((uint32_t *) arg)); - break; - case IO_SPI_MASTER_SET_RX_DELAY: - REG_WRITE(RX_SAMPLE_DLY, *((uint32_t *) arg)); - break; - case IO_SPI_MASTER_SET_TRANSFER_MODE: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 2, 8); - break; - case IO_SPI_MASTER_SET_SCPH: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 1, 6); - break; - case IO_SPI_MASTER_SET_SCPL: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 1, 7); - break; - case IO_SPI_MASTER_SET_SRL_MODE: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 1, 11); - break; - - case IO_SPI_MASTER_SET_DFS: - REG_WRITE_BITS(CTRL0, regval, ((*((uint32_t *) arg)) - 1), - (3 + dev->log_xfer_size), - ((dev->log_xfer_size - 1) << 4)); - break; - - default: - break; - } - - while (REG_READ(SPIEN) != 0) { - ; - } - REG_WRITE(SPIEN, 0x1); - - break; - } - } -} - -static void spi_mst_rx_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* read remaining data from fifo */ - retrieve_rxfifo(dev); - - if (dev->rx_size <= (dev->rx_count << dev->log_xfer_size)) { /* read buffer completely filled, mask RX-avail interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_RX_FULL)); - } -#ifdef __Xdmac -} else { - uint32_t divisor = 0, remainder = 0; - - /* DMA RX xfer done */ - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - _dma_int_clear((0x1 << dev->dmarxchanid)); - - /* process final data, if it is a partial (half)word */ - divisor = dev->rx_size >> dev->log_xfer_size; - remainder = dev->rx_size - (divisor << dev->log_xfer_size); - if (remainder != 0) { - uint32_t mask = ~((~0x0) << (remainder * 8)); - - if (dev->log_xfer_size == 1) { - ((uint16_t *) (dev->rx_buff))[divisor] = - (((uint16_t *) (dev-> - rx_buff))[divisor] & ~mask) | (dev-> - dmarx_last16 - & mask); - } else if (dev->log_xfer_size == 2) { - ((uint32_t *) (dev->rx_buff))[divisor] = - (((uint32_t *) (dev-> - rx_buff))[divisor] & ~mask) | (dev-> - dmarx_last32 - & mask); - } - - } - - /* Enable Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_IDLE)); -} -#endif -} - -static void spi_mst_tx_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - if ((dev->tx_size <= (dev->tx_count << dev->log_xfer_size))) { - /* no data left to put into the fifo, mask TX-request */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_TX_EMPTY)); - } else { /* write data into the fifo */ - fill_txfifo(dev); - } -#ifdef __Xdmac -} else { - /* DMA TX xfer done */ - _dma_chan_enable((0x1 << dev->dmatxchanid), 0); - _dma_int_clear((0x1 << dev->dmatxchanid)); - - /* Enable Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_IDLE)); -} -#endif -} - -static void spi_mst_idle_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - - if (dev->handling_tx == 1) { - dev->handling_tx = 0; - - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - - /* mask TX-empty (if not done yet) and Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_TX_EMPTY & ~R_IDLE)); - - } - - if (dev->handling_rx == 1) { - dev->handling_rx = 0; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* read remaining data from fifo */ - retrieve_rxfifo(dev); -#ifdef __Xdmac - } -#endif - - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - - /* mask RX-available (if not done yet) and Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_RX_FULL & ~R_IDLE)); - } - -} - -static void spi_mst_err_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - - REG_WRITE(IMR, 0); - - if (NULL != dev->err_cb) { - dev->err_cb(dev_id); - } - - REG_WRITE(ICR, R_RX_OVER | R_RX_UNDER | R_TX_OVER); -} - -static void fill_txfifo(spi_info_pt dev) -{ - uint32_t cnt = 0, h = 0, free = 0; - - cnt = dev->tx_size - (dev->tx_count << dev->log_xfer_size); - free = (dev->fifo_depth - REG_READ(TXFLR)) << dev->log_xfer_size; - if (cnt > free) { - cnt = free; - } - - if (dev->log_xfer_size == 0) { /* 8-bits data */ - for (h = 0; h != cnt; h++) { - REG_WRITE(DR, ((uint8_t *) (dev->tx_buff))[dev->tx_count++]); - } - } else if (dev->log_xfer_size == 1) { /* 16-bits data */ - for (h = 0; h != cnt / 2; h++) { - REG_WRITE(DR, ((uint16_t *) (dev->tx_buff))[dev->tx_count++]); - } - /* if 2h != cnt: partial tx left at the end */ - if (2 * h != cnt) { - REG_WRITE(DR, - ((((uint16_t *) (dev->tx_buff))[dev-> - tx_count++]) & - 0x00ff)); - } - } else { /* log_xfer_size == 2; 32-bits data */ - for (h = 0; h != cnt / 4; h++) { - REG_WRITE(DR, ((uint32_t *) (dev->tx_buff))[dev->tx_count++]); - } - /* if 4h != cnt: partial tx left at the end */ - if (4 * h != cnt) { - uint32_t mask32 = ~((~0x0) << ((cnt - 4 * h) * 8)); - REG_WRITE(DR, - ((((uint32_t *) (dev->tx_buff))[dev-> - tx_count++]) & - mask32)); - } - } - -} - -static void retrieve_rxfifo(spi_info_pt dev) -{ - uint32_t cnt = 0, h = 0, avail = 0; - - cnt = dev->rx_size - (dev->rx_count << dev->log_xfer_size); - avail = REG_READ(RXFLR) << dev->log_xfer_size; - if (cnt > avail) { - cnt = avail; - } - - if (dev->log_xfer_size == 0) { /* 8-bits data */ - for (h = 0; h != cnt; h++) { - ((uint8_t *) (dev->rx_buff))[dev->rx_count++] = - (uint8_t) REG_READ(DR); - } - } else if (dev->log_xfer_size == 1) { /* 16-bits data */ - for (h = 0; h != cnt / 2; h++) { - ((uint16_t *) (dev->rx_buff))[dev->rx_count++] = - (uint16_t) REG_READ(DR); - } - /* if 2h != cnt: partial rx left at the end */ - if (2 * h != cnt) { - ((uint16_t *) (dev->rx_buff))[dev->rx_count] = - (((uint16_t *) (dev->rx_buff))[dev-> - rx_count] & ~0x00ff) | - (REG_READ(DR) & 0x00ff); - dev->rx_count++; - } - - } else { /* log_xfer_size == 2; 32-bits data */ - for (h = 0; h != cnt / 4; h++) { - ((uint32_t *) (dev->rx_buff))[dev->rx_count++] = REG_READ(DR); - } - /* if 4h != cnt: partial rx left at the end */ - if (4 * h != cnt) { - uint32_t mask32 = ~((~0x0) << ((cnt - 4 * h) * 8)); - ((uint32_t *) (dev->rx_buff))[dev->rx_count] = - (((uint32_t *) (dev->rx_buff))[dev-> - rx_count] & ~mask32) | - (REG_READ(DR) & mask32); - dev->rx_count++; - } - } - -} - -void io_spi_master_polling(uint32_t dev_id, DEV_SPI_TRANSFER *xfer) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint8_t tmp; - uint32_t tx_left, tx_free; - uint32_t rx_left, rx_avail; - - REG_WRITE(SPIEN, 0); - REG_WRITE(SPIEN, 1); /* disable then enable SPI to reset the TX and RX FIFO */ - - while (xfer->tx_idx < xfer->tot_len || xfer->rx_idx < xfer->tot_len) { - tx_left = (xfer->tot_len - xfer->tx_idx); - tx_free = dev->fifo_depth - REG_READ(TXFLR); - if (tx_free > tx_left) { - tx_free = tx_left; - } - while (tx_free) { - if (xfer->tx_idx >= xfer->tx_ofs && xfer->tx_idx < xfer->tx_totlen) { - REG_WRITE(DR, xfer->tx_buf[xfer->tx_idx]); - } else { - REG_WRITE(DR, 0xFF); - } - xfer->tx_idx++; - tx_free--; - } - rx_left = (xfer->tot_len - xfer->rx_idx); - rx_avail = REG_READ(RXFLR); - if (rx_avail > rx_left) { - rx_avail = rx_left; - } - while (rx_avail) { - if (xfer->rx_idx >= xfer->rx_ofs && xfer->rx_idx < xfer->rx_totlen) { - xfer->rx_buf[xfer->rx_idx - xfer->rx_ofs] = (uint8_t)REG_READ(DR); - } else { - tmp = (uint8_t)REG_READ(DR); - } - xfer->rx_idx++; - rx_avail--; - } - } -} - -#ifdef __Xdmac -#define SPI_MST_DMA_RX_CTRL (0x80000017) /* am=b10, i=b0, dw/inc=b..., dtt=b10, r=b1, op=b11 */ -#define SPI_MST_DMA_RX_END_CTRL (0xa0000015) /* am=b10, i=b1, dw/inc=b..., dtt=b10, r=b1, op=b01 */ -#define SPI_MST_DMA_RX_REM_CTRL (0xa0000015) /* am=b10, i=b1, dw/inc=b..., dtt=b10, r=b1, op=b01 */ -#define SPI_MST_DMA_TX_CTRL (0x4000000f) /* am=b01, i=b0, dw/inc=b..., dtt=b01, r=b1, op=b11 */ -#define SPI_MST_DMA_TX_END_CTRL (0x6000000d) /* am=b01, i=b1, dw/inc=b..., dtt=b01, r=b1, op=b01 */ -#define SPI_MST_DMA_TX_REM_CTRL (0x6000000d) /* am=b01, i=b1, dw/inc=b..., dtt=b01, r=b1, op=b01 */ -#define SPI_MST_DMA_CTRL_DWINC_POS (5) -#define SPI_MST_DMA_CTRL_SIZE_POS (8) -#define SPI_MST_DMA_CTRL_XFER_POS (21) -#define SPI_MST_DMA_FORCE_INT (0x1 << 29) - -static void create_dma_descriptors_rx(spi_info_pt dev, uint32_t burst, - uint8_t idx) -{ - uint32_t divisor = 0, remainder = 0; - uint32_t ctrl = 0; - - ctrl = burst << SPI_MST_DMA_CTRL_XFER_POS; - if (dev->log_xfer_size == 0) { - ctrl |= (0x0 << SPI_MST_DMA_CTRL_DWINC_POS); - } else if (dev->log_xfer_size == 1) { - ctrl |= (0x3 << SPI_MST_DMA_CTRL_DWINC_POS); - } else { /* dev->log_xfer_size == 2 */ - - ctrl |= (0x5 << SPI_MST_DMA_CTRL_DWINC_POS); - } - - if ((dev->rx_size - (dev->rx_count << dev->log_xfer_size)) <= 8 * 1024) { - divisor = (dev->rx_size >> dev->log_xfer_size) - dev->rx_count; - remainder = - dev->rx_size - - ((dev->rx_size >> dev->log_xfer_size) << dev->log_xfer_size); - - if ((divisor > 0) && (remainder == 0)) { - dev->dmarxdescriptor[idx + 0] = - SPI_MST_DMA_RX_END_CTRL | ctrl | - (((dev->rx_size - (dev->rx_count << dev->log_xfer_size)) - - 1) << SPI_MST_DMA_CTRL_SIZE_POS); - dev->rx_count += divisor; - dev->dmarxdescriptor[idx + 2] = - (uint32_t) dev->rx_buff + - ((dev->rx_count << dev->log_xfer_size) - 1); - } else if ((divisor > 0) && (remainder > 0)) { - dev->dmarxdescriptor[idx + 0] = - SPI_MST_DMA_RX_CTRL | ctrl | - (((dev->rx_size - (dev->rx_count << dev->log_xfer_size)) - - 1 - remainder) << SPI_MST_DMA_CTRL_SIZE_POS); - dev->rx_count += divisor; - dev->dmarxdescriptor[idx + 2] = - (uint32_t) dev->rx_buff + - ((dev->rx_count << dev->log_xfer_size) - 1); - } else { /* divisor == 0, remainder > 0 */ - - dev->dmarxdescriptor[idx + 0] = - SPI_MST_DMA_RX_REM_CTRL | ctrl | - ((2 * dev->log_xfer_size - - 1) << SPI_MST_DMA_CTRL_SIZE_POS); - dev->rx_count++; - if (dev->log_xfer_size == 1) { - dev->dmarxdescriptor[idx + 2] = - (uint32_t) &(dev->dmarx_last16) + 1; - } else { - dev->dmarxdescriptor[idx + 2] = - (uint32_t) &(dev->dmarx_last32) + 3; - } - } - } -} - -static void create_dma_descriptors_tx(spi_info_pt dev, uint32_t burst, - uint8_t idx) -{ - uint32_t divisor = 0, remainder = 0; - uint32_t ctrl = 0; - - ctrl = burst << SPI_MST_DMA_CTRL_XFER_POS; - if (dev->log_xfer_size == 0) { - ctrl |= (0x0 << SPI_MST_DMA_CTRL_DWINC_POS); - } else if (dev->log_xfer_size == 1) { - ctrl |= (0x3 << SPI_MST_DMA_CTRL_DWINC_POS); - } else { /* dev->log_xfer_size == 2 */ - - ctrl |= (0x5 << SPI_MST_DMA_CTRL_DWINC_POS); - } - - if ((dev->tx_size - (dev->tx_count << dev->log_xfer_size)) <= 8 * 1024) { - divisor = (dev->tx_size >> dev->log_xfer_size) - dev->tx_count; - remainder = - dev->tx_size - - ((dev->tx_size >> dev->log_xfer_size) << dev->log_xfer_size); - - if (dev->log_xfer_size == 1) { - dev->dmatx_last16 = - ((uint16_t *) (dev->tx_buff))[(dev->tx_size >> dev-> - log_xfer_size)] & ~((~0x0) - << - (remainder - * 8)); - } else if (dev->log_xfer_size == 2) { - dev->dmatx_last32 = - ((uint32_t *) (dev->tx_buff))[(dev->tx_size >> dev-> - log_xfer_size)] & ~((~0x0) - << - (remainder - * 8)); - } - - if ((divisor > 0) && (remainder == 0)) { - dev->dmatxdescriptor[idx + 0] = - SPI_MST_DMA_TX_END_CTRL | ctrl | - ((dev->tx_size - (dev->tx_count << dev->log_xfer_size) - - 1) << SPI_MST_DMA_CTRL_SIZE_POS); - dev->tx_count += divisor; - dev->dmatxdescriptor[idx + 1] = - (uint32_t) dev->tx_buff + - ((dev->tx_count << dev->log_xfer_size) - 1); - } else if ((divisor > 0) && (remainder > 0)) { - dev->dmatxdescriptor[idx + 0] = - SPI_MST_DMA_TX_CTRL | ctrl | - ((dev->tx_size - (dev->tx_count << dev->log_xfer_size) - - 1 - remainder) << SPI_MST_DMA_CTRL_SIZE_POS); - dev->tx_count += divisor; - dev->dmatxdescriptor[idx + 1] = - (uint32_t) dev->tx_buff + - ((dev->tx_count << dev->log_xfer_size) - 1); - } else { /* divisor == 0, remainder > 0 */ - - dev->dmatxdescriptor[idx + 0] = - SPI_MST_DMA_TX_REM_CTRL | ctrl | - ((2 * dev->log_xfer_size - - 1) << SPI_MST_DMA_CTRL_SIZE_POS); - dev->tx_count++; - if (dev->log_xfer_size == 1) { - dev->dmatxdescriptor[idx + 1] = - (uint32_t) &(dev->dmatx_last16) + 1; - } else { - dev->dmatxdescriptor[idx + 1] = - (uint32_t) &(dev->dmatx_last32) + 3; - } - } - } -} -#endif - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/spi_slave.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/spi_slave.c deleted file mode 100644 index 0de3af7b..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/spi_slave.c +++ /dev/null @@ -1,949 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/spi_slave.h" -#include "device/subsystem/spi_priv.h" -#include "io_config.h" -#include "apexextensions.h" - -/* local defines (!!) */ -#define SPI_TRANSMIT_RECEIVE_MODE (0) -#define SPI_TRANSMIT_ONLY_MODE (1) -#define SPI_RECEIVE_ONLY_MODE (2) - -#ifdef IO_SPI_SLV0_PRESENT -#define SPI_DEV_PRESENT -#endif -#ifdef IO_SPI_SLV1_PRESENT -#define SPI_DEV_PRESENT -#endif -#ifdef IO_SPI_SLV2_PRESENT -#define SPI_DEV_PRESENT -#endif -#ifdef IO_SPI_SLV3_PRESENT -#define SPI_DEV_PRESENT -#endif - -#ifdef SPI_DEV_PRESENT - -#define SPI_MAX_CNT (4) - -static void spi_slv_rx_ISR_proc(uint32_t dev_id); -static void spi_slv_tx_ISR_proc(uint32_t dev_id); -static void spi_slv_idle_ISR_proc(uint32_t dev_id); -static void spi_slv_err_ISR_proc(uint32_t dev_id); - -#ifdef IO_SPI_SLV0_PRESENT -static _Interrupt void spi_slv0_rx_ISR() -{ - spi_slv_rx_ISR_proc(0); -} - -static _Interrupt void spi_slv0_tx_ISR() -{ - spi_slv_tx_ISR_proc(0); -} - -static _Interrupt void spi_slv0_idle_ISR() -{ - spi_slv_idle_ISR_proc(0); -} - -static _Interrupt void spi_slv0_err_ISR() -{ - spi_slv_err_ISR_proc(0); -} -#endif -#ifdef IO_SPI_SLV1_PRESENT -static _Interrupt void spi_slv1_rx_ISR() -{ - spi_slv_rx_ISR_proc(1); -} - -static _Interrupt void spi_slv1_tx_ISR() -{ - spi_slv_tx_ISR_proc(1); -} - -static _Interrupt void spi_slv1_idle_ISR() -{ - spi_slv_idle_ISR_proc(1); -} - -static _Interrupt void spi_slv1_err_ISR() -{ - spi_slv_err_ISR_proc(1); -} -#endif -#ifdef IO_SPI_SLV2_PRESENT -static _Interrupt void spi_slv2_rx_ISR() -{ - spi_slv_rx_ISR_proc(2); -} - -static _Interrupt void spi_slv2_tx_ISR() -{ - spi_slv_tx_ISR_proc(2); -} - -static _Interrupt void spi_slv2_idle_ISR() -{ - spi_slv_idle_ISR_proc(2); -} - -static _Interrupt void spi_slv2_err_ISR() -{ - spi_slv_err_ISR_proc(2); -} -#endif -#ifdef IO_SPI_SLV3_PRESENT -static _Interrupt void spi_slv3_rx_ISR() -{ - spi_slv_rx_ISR_proc(3); -} - -static _Interrupt void spi_slv3_tx_ISR() -{ - spi_slv_tx_ISR_proc(3); -} - -static _Interrupt void spi_slv3_idle_ISR() -{ - spi_slv_idle_ISR_proc(3); -} - -static _Interrupt void spi_slv3_err_ISR() -{ - spi_slv_err_ISR_proc(3); -} -#endif - -static void fill_txfifo(spi_info_pt dev); -static void retrieve_rxfifo(spi_info_pt dev); - -#ifdef __Xdmac -static void create_dma_descriptors_rx(spi_info_pt dev, uint8_t *dest, - uint32_t size, uint32_t burst); -static void create_dma_descriptors_tx(spi_info_pt dev, uint8_t *src, - uint32_t size, uint32_t burst); -#endif - -/* SPI slave devices private data structures */ -static spi_info_pt spi_handles[SPI_MAX_CNT] = { 0 }; - -#ifdef __Xdmac -static _Uncached uint32_t spi_dmarx_descriptors[8 * SPI_MAX_CNT]; -static _Uncached uint32_t spi_dmatx_descriptors[8 * SPI_MAX_CNT]; -#endif - -static spi_info_t spi_slave_devs[] = { -#ifdef IO_SPI_SLV0_PRESENT - { .instID = 0, - .reg_base = AR_IO_SPI_SLV0_CTRLR0, -#ifdef IO_SPI_SLV0_DMA_RX - .dmarxchanid = IO_SPI_SLV0_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_SLV0_DMA_TX - .dmatxchanid = IO_SPI_SLV0_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_SLV0_INT_RX_AVAIL, - .tx_vector = IO_SPI_SLV0_INT_TX_REQ, - .idle_vector = IO_SPI_SLV0_INT_IDLE, - .err_vector = IO_SPI_SLV0_INT_ERR, - .rx_isr = spi_slv0_rx_ISR, - .tx_isr = spi_slv0_tx_ISR, - .idle_isr = spi_slv0_idle_ISR, - .err_isr = spi_slv0_err_ISR, - .log_xfer_size = (IO_SPI_SLV0_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_SLV0_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_SLV0_FS }, -#endif -#ifdef IO_SPI_SLV1_PRESENT - { .instID = 1, - .reg_base = AR_IO_SPI_SLV1_CTRLR0, -#ifdef IO_SPI_SLV1_DMA_RX - .dmarxchanid = IO_SPI_SLV1_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_SLV1_DMA_TX - .dmatxchanid = IO_SPI_SLV1_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_SLV1_INT_RX_AVAIL, - .tx_vector = IO_SPI_SLV1_INT_TX_REQ, - .idle_vector = IO_SPI_SLV1_INT_IDLE, - .err_vector = IO_SPI_SLV1_INT_ERR, - .rx_isr = spi_slv1_rx_ISR, - .tx_isr = spi_slv1_tx_ISR, - .idle_isr = spi_slv1_idle_ISR, - .err_isr = spi_slv1_err_ISR, - .log_xfer_size = (IO_SPI_SLV1_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_SLV1_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_SLV1_FS }, -#endif -#ifdef IO_SPI_SLV2_PRESENT - { .instID = 2, - .reg_base = AR_IO_SPI_SLV2_CTRLR0, -#ifdef IO_SPI_SLV2_DMA_RX - .dmarxchanid = IO_SPI_SLV2_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_SLV2_DMA_TX - .dmatxchanid = IO_SPI_SLV2_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_SLV2_INT_RX_AVAIL, - .tx_vector = IO_SPI_SLV2_INT_TX_REQ, - .idle_vector = IO_SPI_SLV2_INT_IDLE, - .err_vector = IO_SPI_SLV2_INT_ERR, - .rx_isr = spi_slv2_rx_ISR, - .tx_isr = spi_slv2_tx_ISR, - .idle_isr = spi_slv2_idle_ISR, - .err_isr = spi_slv2_err_ISR, - .log_xfer_size = (IO_SPI_SLV2_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_SLV2_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_SLV2_FS }, -#endif -#ifdef IO_SPI_SLV3_PRESENT - { .instID = 3, - .reg_base = AR_IO_SPI_SLV3_CTRLR0, -#ifdef IO_SPI_SLV3_DMA_RX - .dmarxchanid = IO_SPI_SLV3_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_SPI_SLV3_DMA_TX - .dmatxchanid = IO_SPI_SLV3_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .rx_vector = IO_SPI_SLV3_INT_RX_AVAIL, - .tx_vector = IO_SPI_SLV3_INT_TX_REQ, - .idle_vector = IO_SPI_SLV3_INT_IDLE, - .err_vector = IO_SPI_SLV3_INT_ERR, - .rx_isr = spi_slv3_rx_ISR, - .tx_isr = spi_slv3_tx_ISR, - .idle_isr = spi_slv3_idle_ISR, - .err_isr = spi_slv3_err_ISR, - .log_xfer_size = (IO_SPI_SLV3_MAX_XFER_SIZE >> 4), - .max_xfer_size = (IO_SPI_SLV3_MAX_XFER_SIZE), - .fifo_depth = IO_SPI_SLV3_FS }, -#endif - { .instID = SPI_MAX_CNT } -}; - -#define REG_WRITE(reg, x) _sr((unsigned)(x), (unsigned)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((unsigned)(dev->reg_base + reg)) -#define REG_WRITE_BITS(reg, x, y, len, pos) REG_WRITE(reg, ((((x) & ~((~(0xffffffff << len)) << pos)) \ - | (((y) << pos) & ((~(0xffffffff << len)) << pos))))) -#define REG_GET_BITS(reg, len, pos) ((REG_READ(reg) >> pos) & ~(0xffffffff << len)) - -uint32_t io_spi_slave_open(uint32_t dev_id) -{ - uint32_t h = 0; - spi_info_pt dev; - - h = 0; - while ((spi_slave_devs[h].instID != dev_id) - && (spi_slave_devs[h].instID != SPI_MAX_CNT)) { - h++; - } - if ((spi_slave_devs[h].instID == SPI_MAX_CNT) || (0 != spi_handles[dev_id])) { /* dev_id not part of design, or still open */ - return 1; - } - spi_handles[dev_id] = &spi_slave_devs[h]; - dev = spi_handles[dev_id]; - - /* enable clock */ - REG_WRITE(CLK_ENA, 0x1); - - if (dev->max_xfer_size == 16) { /* 16-bits SPI; log_xfer_size == 1 */ - dev->log_xfer_size = dev->max_xfer_size >> 4; - REG_WRITE_BITS(CTRL0, 0x0, 15, 4, 0); - } else { - /* 32-bits SPI; log_xfer_size == 2 */ - dev->log_xfer_size = dev->max_xfer_size >> 4; - REG_WRITE_BITS(CTRL0, 0x0, 31, 5, 16); - } - - /* mask RX-available and TX-empty interrupts, always mask TX-underflow */ - REG_WRITE(IMR, ~(R_TX_EMPTY | R_RX_FULL | R_TX_UNDER)); - - dev->handling_rx = dev->handling_tx = 0; - - _setvecti(dev->rx_vector, dev->rx_isr); - _setvecti(dev->tx_vector, dev->tx_isr); - _setvecti(dev->idle_vector, dev->idle_isr); - _setvecti(dev->err_vector, dev->err_isr); - -#ifdef __Xdmac - dev->dmarxdescriptor = &spi_dmarx_descriptors[8 * h]; - dev->dmatxdescriptor = &spi_dmatx_descriptors[8 * h]; - - if (dev->dmarxchanid != DMA_NONE) { - dev->dmarxdescriptor[1] = dev->dmarxdescriptor[5] = - dev->reg_base + DR; - dev->dmarxdescriptor[3] = (uint32_t) &(dev->dmarxdescriptor[4]); - dev->dmarxdescriptor[7] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, dev->rx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, dev->err_isr); - } - - if (dev->dmatxchanid != DMA_NONE) { - dev->dmatxdescriptor[2] = dev->dmatxdescriptor[6] = - dev->reg_base + DR; - dev->dmatxdescriptor[3] = (uint32_t) &(dev->dmatxdescriptor[4]); - dev->dmatxdescriptor[7] = 0; - - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, dev->tx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, dev->err_isr); - } -#endif - - REG_WRITE(SPIEN, 0x1); - - return 0; -} - -void io_spi_slave_close(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - - REG_WRITE(IMR, 0); - REG_WRITE(SPIEN, 0); - - REG_WRITE(CTRL0, 0x7); - REG_WRITE(TXFTLR, 0); - REG_WRITE(RXFTLR, 0); - REG_WRITE(IMR, 0xff); - - /* gate clock */ - REG_WRITE(CLK_ENA, 0); - - _setvecti(dev->rx_vector, NULL); - _setvecti(dev->tx_vector, NULL); - _setvecti(dev->idle_vector, NULL); - _setvecti(dev->err_vector, NULL); - -#ifdef __Xdmac - if (dev->dmarxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmarxchanid); - } - - if (dev->dmatxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmatxchanid); - } -#endif - - dev->rx_cb = NULL; - dev->tx_cb = NULL; - dev->err_cb = NULL; - - spi_handles[dev_id] = 0; -} - -void io_spi_slave_read(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - - dev->rx_size = *size; - dev->p_rxsize = size; - dev->rx_count = 0; - - dev->rx_buff = (void *) data; - - dev->handling_rx = 1; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* Enable RX-available and Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_RX_FULL | R_IDLE)); -#ifdef __Xdmac -} else { /* RX descriptor */ - if (*size != 0) { - /* rx data available; at least one */ - create_dma_descriptors_rx(dev, data, *size, - (1 + REG_READ(RXFTLR))); - - /* init dma */ - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmarxchanid), 1); - - /* enable the Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, val | R_IDLE); - } -} -#endif -} - -void io_spi_slave_write(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - - dev->tx_size = *size; - dev->tx_count = 0; - dev->tx_buff = (void *) data; - - dev->handling_tx = 1; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* write first bytes to fifo, assuming size > 0 */ - fill_txfifo(dev); - - /* Enable TX-empty, Idle interrupt, and (optional) RX-available */ - if (REG_GET_BITS(CTRL0, 2, 8) == SPI_TRANSMIT_ONLY_MODE) { - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_TX_EMPTY | R_IDLE)); - } else { /* TX-RX mode */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val | R_TX_EMPTY | R_IDLE | R_RX_FULL)); - } -#ifdef __Xdmac -} else { /* TX descriptor */ - if (*size != 0) { - /* tx data available; at least one, more is uncertain */ - create_dma_descriptors_tx(dev, data, *size, - (dev->fifo_depth - - REG_READ(TXFTLR))); - - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - - /* enable the Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, val | R_IDLE); - } -} -#endif -} - -void io_spi_slave_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t regval; - - switch (cmd) { - case IO_SET_CB_RX: - dev->rx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_TX: - dev->tx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_ERR: - dev->err_cb = ((io_cb_t *) arg)->cb; - break; - - case IO_SPI_SLAVE_SET_RX_THRESHOLD: - REG_WRITE(RXFTLR, *((uint32_t *) arg)); - break; - case IO_SPI_SLAVE_SET_TX_THRESHOLD: - REG_WRITE(TXFTLR, *((uint32_t *) arg)); - break; - - case IO_SPI_SLAVE_SET_PACKING: - { /* DFS must be set prior applying this option */ - regval = REG_READ(CTRL0); - if (*((uint32_t *) arg) == 0) { /* reset packing */ - dev->log_xfer_size = dev->max_xfer_size >> 4; - } else { /* set packing */ - if (dev->max_xfer_size == 32) { /* 32-bits SPI */ - regval = (regval >> 16) & 0x01F; // Get DFS field from CTRL0 value - dev->log_xfer_size = - (regval == 15) ? 1 : (regval == - 7) ? 0 : dev-> - max_xfer_size >> 4; - } else { /* 16-bits SPI */ - regval = regval & 0x00F; // Get DFS field from CTRL0 value - dev->log_xfer_size = - (regval == 7) ? 0 : dev->max_xfer_size >> 4; - } - } - break; - } - default: - { - /* ioctl calls that require disabling of the SPI first */ - REG_WRITE(SPIEN, 0); - - regval = REG_READ(CTRL0); - switch (cmd) { - case IO_SPI_SLAVE_SET_TRANSFER_MODE: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 2, 8); - break; - case IO_SPI_SLAVE_SET_SCPH: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 1, 6); - break; - case IO_SPI_SLAVE_SET_SCPL: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 1, 7); - break; - case IO_SPI_SLAVE_SET_SRL_MODE: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 1, 11); - break; - case IO_SPI_SLAVE_SET_OUTPUT_ENABLE: - REG_WRITE_BITS(CTRL0, regval, *((uint32_t *) arg), 1, 10); - break; - - case IO_SPI_SLAVE_SET_DFS: - REG_WRITE_BITS(CTRL0, regval, ((*((uint32_t *) arg)) - 1), - (3 + dev->log_xfer_size), - ((dev->log_xfer_size - 1) << 4)); - break; - - default: - break; - } - - REG_WRITE(SPIEN, 0x1); - - break; - } - } -} - -static void spi_slv_rx_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* read remaining data from fifo */ - retrieve_rxfifo(dev); - - if (dev->rx_size <= (dev->rx_count << dev->log_xfer_size)) { /* read buffer completely filled, mask RX-avail interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_RX_FULL)); - } -#ifdef __Xdmac -} else { - uint32_t divisor = 0, remainder = 0; - - /* DMA RX xfer done */ - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - _dma_int_clear((0x1 << dev->dmarxchanid)); - - /* process final data, if it is a partial (half)word */ - divisor = dev->rx_size >> dev->log_xfer_size; - remainder = dev->rx_size - (divisor << dev->log_xfer_size); - - if (remainder != 0) { - uint32_t mask = ~((~0x0) << (remainder * 8)); - - if (dev->log_xfer_size == 1) { - ((uint16_t *) (dev->rx_buff))[divisor] = - (((uint16_t *) (dev-> - rx_buff))[divisor] & ~mask) | (dev-> - dmarx_last16 - & mask); - } else if (dev->log_xfer_size == 2) { - ((uint32_t *) (dev->rx_buff))[divisor] = - (((uint32_t *) (dev-> - rx_buff))[divisor] & ~mask) | (dev-> - dmarx_last32 - & mask); - } - } -} -#endif -} - -static void spi_slv_tx_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - if (dev->tx_size <= (dev->tx_count << dev->log_xfer_size)) { - /* no data left to put into the fifo, mask TX-request */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_TX_EMPTY)); - } else { /* write data into the fifo */ - fill_txfifo(dev); - } -#ifdef __Xdmac -} else { - /* DMA TX xfer done */ - _dma_chan_enable((0x1 << dev->dmatxchanid), 0); - _dma_int_clear((0x1 << dev->dmatxchanid)); -} -#endif -} - -static void spi_slv_idle_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - uint32_t val = 0; - - if (dev->handling_tx == 1) { - if ((dev->tx_size <= (dev->tx_count << dev->log_xfer_size)) || (dev->dmatxchanid != DMA_NONE)) { /* buffer completely processed */ - - dev->handling_tx = 0; - - if (NULL != dev->tx_cb) { - dev->tx_cb(dev_id); - } - - /* mask TX-empty (if not done yet) and Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_TX_EMPTY & ~R_IDLE)); - } - } - - if (dev->handling_rx == 1) { -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - /* read remaining data from fifo */ - retrieve_rxfifo(dev); -#ifdef __Xdmac - } -#endif - - if ((dev->rx_size <= (dev->rx_count << dev->log_xfer_size)) || (dev->dmarxchanid != DMA_NONE)) { /* buffer completely processed */ - - dev->handling_rx = 0; - - if (NULL != dev->rx_cb) { - dev->rx_cb(dev_id); - } - - /* mask RX-available (if not done yet) and Idle interrupt */ - val = REG_READ(IMR); - REG_WRITE(IMR, (val & ~R_RX_FULL & ~R_IDLE)); - } - } - - /* clear idle interrupt */ - REG_WRITE(ICR, R_IDLE); -} - -static void spi_slv_err_ISR_proc(uint32_t dev_id) -{ - spi_info_pt dev = spi_handles[dev_id]; - - REG_WRITE(IMR, 0); - - if (NULL != dev->err_cb) { - dev->err_cb(dev_id); - } - - REG_WRITE(ICR, R_RX_OVER | R_RX_UNDER | R_TX_OVER | R_TX_UNDER); -} - -static void fill_txfifo(spi_info_pt dev) -{ - uint32_t cnt = 0, h = 0, free = 0; - - cnt = dev->tx_size - (dev->tx_count << dev->log_xfer_size); - free = (dev->fifo_depth - REG_READ(TXFLR)) << dev->log_xfer_size; - if (cnt > free) { - cnt = free; - } - - if (dev->log_xfer_size == 0) { /* 8-bits data */ - for (h = 0; h != cnt; h++) { - REG_WRITE(DR, ((uint8_t *) (dev->tx_buff))[dev->tx_count++]); - } - } else if (dev->log_xfer_size == 1) { /* 16-bits data */ - for (h = 0; h != cnt / 2; h++) { - REG_WRITE(DR, ((uint16_t *) (dev->tx_buff))[dev->tx_count++]); - } - /* if 2h != cnt: partial tx left at the end */ - if (2 * h != cnt) { - REG_WRITE(DR, - ((((uint16_t *) (dev->tx_buff))[dev-> - tx_count++]) & - 0x00ff)); - } - } else { /* log_xfer_size == 2; 32-bits data */ - for (h = 0; h != cnt / 4; h++) { - REG_WRITE(DR, ((uint32_t *) (dev->tx_buff))[dev->tx_count++]); - } - /* if 4h != cnt: partial tx left at the end */ - if (4 * h != cnt) { - uint32_t mask32 = ~((~0x0) << ((cnt - 4 * h) * 8)); - REG_WRITE(DR, - ((((uint32_t *) (dev->tx_buff))[dev-> - tx_count++]) & - mask32)); - } - } - -} - -static void retrieve_rxfifo(spi_info_pt dev) -{ - uint32_t cnt = 0, h = 0, avail = 0; - - cnt = dev->rx_size - (dev->rx_count << dev->log_xfer_size); - avail = REG_READ(RXFLR) << dev->log_xfer_size; - if (cnt > avail) { - cnt = avail; - } - - if (dev->log_xfer_size == 0) { /* 8-bits data */ - for (h = 0; h != cnt; h++) { - ((uint8_t *) (dev->rx_buff))[dev->rx_count++] = - (uint8_t) REG_READ(DR); - } - } else if (dev->log_xfer_size == 1) { /* 16-bits data */ - for (h = 0; h != cnt / 2; h++) { - ((uint16_t *) (dev->rx_buff))[dev->rx_count++] = - (uint16_t) REG_READ(DR); - } - /* if 2h != cnt: partial rx left at the end */ - if (2 * h != cnt) { - ((uint16_t *) (dev->rx_buff))[dev->rx_count] = - (((uint16_t *) (dev->rx_buff))[dev-> - rx_count] & ~0x00ff) | - (REG_READ(DR) & 0x00ff); - dev->rx_count++; - } - - } else { /* 32-bits data; log_xfer_size == 2 */ - for (h = 0; h != cnt / 4; h++) { - ((uint32_t *) (dev->rx_buff))[dev->rx_count++] = REG_READ(DR); - } - /* if 4h != cnt: partial rx left at the end */ - if (4 * h != cnt) { - uint32_t mask32 = ~((~0x0) << ((cnt - 4 * h) * 8)); - ((uint32_t *) (dev->rx_buff))[dev->rx_count] = - (((uint32_t *) (dev->rx_buff))[dev-> - rx_count] & ~mask32) | - (REG_READ(DR) & mask32); - dev->rx_count++; - } - } - -} - -#ifdef __Xdmac -#define SPI_SLV_DMA_RX_CTRL (0x80000017) /* am=b10, i=b0, dw/inc=b..., dtt=b10, r=b1, op=b11 */ -#define SPI_SLV_DMA_RX_END_CTRL (0xa0000015) /* am=b10, i=b1, dw/inc=b..., dtt=b10, r=b1, op=b01 */ -#define SPI_SLV_DMA_RX_REM_CTRL (0xa0000015) /* am=b10, i=b1, dw/inc=b..., dtt=b10, r=b1, op=b01 */ -#define SPI_SLV_DMA_TX_CTRL (0x4000000f) /* am=b01, i=b0, dw/inc=b..., dtt=b01, r=b1, op=b11 */ -#define SPI_SLV_DMA_TX_END_CTRL (0x6000000d) /* am=b01, i=b1, dw/inc=b..., dtt=b01, r=b1, op=b01 */ -#define SPI_SLV_DMA_TX_REM_CTRL (0x6000000d) /* am=b01, i=b1, dw/inc=b..., dtt=b01, r=b1, op=b01 */ -#define SPI_SLV_DMA_CTRL_DWINC_POS (5) -#define SPI_SLV_DMA_CTRL_SIZE_POS (8) -#define SPI_SLV_DMA_CTRL_XFER_POS (21) -#define SPI_SLV_DMA_FORCE_INT (0x1 << 29) - -static void create_dma_descriptors_rx(spi_info_pt dev, uint8_t *dest, - uint32_t size, uint32_t burst) -{ - uint32_t divisor = 0, remainder = 0; - - divisor = size >> dev->log_xfer_size; - remainder = size - (divisor << dev->log_xfer_size); - - if (dev->log_xfer_size == 0) { - dev->dmarxdescriptor[0] = - SPI_SLV_DMA_RX_END_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS); - dev->dmarxdescriptor[2] = (uint32_t) dest + (size - 1); - if (dev->dmarxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmarxdescriptor[3] = 0; - } - } else if ((divisor > 0) && (remainder == 0)) { - dev->dmarxdescriptor[0] = - SPI_SLV_DMA_RX_END_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - dev->dmarxdescriptor[2] = (uint32_t) dest + (size - 1); - if (dev->dmarxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmarxdescriptor[3] = 0; - } - } else if ((divisor > 0) && (remainder > 0)) { - dev->dmarxdescriptor[0] = - SPI_SLV_DMA_RX_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((size - 1 - remainder) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - dev->dmarxdescriptor[2] = (uint32_t) dest + (size - 1 - remainder); - if (dev->dmarxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmarxdescriptor[0] |= SPI_SLV_DMA_FORCE_INT; - dev->dmarxdescriptor[3] = - (uint32_t) &(dev->dmarxdescriptor[4]); - } - dev->dmarxdescriptor[4 + 0] = - SPI_SLV_DMA_RX_REM_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((2 * dev->log_xfer_size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - if (dev->log_xfer_size == 1) { - dev->dmarxdescriptor[4 + 2] = - (uint32_t) &(dev->dmarx_last16) + 1; - } else { - dev->dmarxdescriptor[4 + 2] = - (uint32_t) &(dev->dmarx_last32) + 3; - } - if (dev->dmarxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmarxdescriptor[4 + 3] = 0; - } - } else { /* divisor == 0, remainder > 0 */ - - dev->dmarxdescriptor[0] = - SPI_SLV_DMA_RX_REM_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((2 * dev->log_xfer_size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - if (dev->log_xfer_size == 1) { - dev->dmarxdescriptor[2] = (uint32_t) &(dev->dmarx_last16) + 1; - } else { - dev->dmarxdescriptor[2] = (uint32_t) &(dev->dmarx_last32) + 3; - } - if (dev->dmarxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmarxdescriptor[3] = 0; - } - } -} - -static void create_dma_descriptors_tx(spi_info_pt dev, uint8_t *src, - uint32_t size, uint32_t burst) -{ - uint32_t divisor = 0, remainder = 0; - - divisor = size >> dev->log_xfer_size; - remainder = size - (divisor << dev->log_xfer_size); - - if (dev->log_xfer_size == 1) { - dev->dmatx_last16 = - ((uint16_t *) (dev-> - tx_buff))[divisor] & ~((~0x0) << (remainder * - 8)); - } else { - dev->dmatx_last32 = - ((uint32_t *) (dev-> - tx_buff))[divisor] & ~((~0x0) << (remainder * - 8)); - } - - if (dev->log_xfer_size == 0) { - dev->dmatxdescriptor[0] = - SPI_SLV_DMA_TX_END_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS); - dev->dmatxdescriptor[1] = (uint32_t) src + (size - 1); - if (dev->dmatxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmatxdescriptor[3] = 0; - } - } else if ((divisor > 0) && (remainder == 0)) { - dev->dmatxdescriptor[0] = - SPI_SLV_DMA_TX_END_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - dev->dmatxdescriptor[1] = (uint32_t) src + (size - 1); - if (dev->dmatxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmatxdescriptor[3] = 0; - } - } else if ((divisor > 0) && (remainder > 0)) { - dev->dmatxdescriptor[0] = - SPI_SLV_DMA_TX_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((size - 1 - remainder) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - dev->dmatxdescriptor[1] = (uint32_t) src + (size - 1 - remainder); - if (dev->dmatxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmatxdescriptor[0] |= SPI_SLV_DMA_FORCE_INT; - dev->dmatxdescriptor[3] = - (uint32_t) &(dev->dmatxdescriptor[4]); - } - dev->dmatxdescriptor[4 + 0] = - SPI_SLV_DMA_TX_REM_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((2 * dev->log_xfer_size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - if (dev->log_xfer_size == 1) { - dev->dmatxdescriptor[4 + 1] = - (uint32_t) &(dev->dmatx_last16) + 1; - } else { - dev->dmatxdescriptor[4 + 1] = - (uint32_t) &(dev->dmatx_last32) + 3; - } - if (dev->dmatxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmatxdescriptor[4 + 3] = 0; - } - } else { /* divisor == 0, remainder > 0 */ - - dev->dmatxdescriptor[0] = - SPI_SLV_DMA_TX_REM_CTRL | (burst << SPI_SLV_DMA_CTRL_XFER_POS) - | ((2 * dev->log_xfer_size - 1) << SPI_SLV_DMA_CTRL_SIZE_POS) - | ((2 * dev->log_xfer_size + 1) << SPI_SLV_DMA_CTRL_DWINC_POS); - if (dev->log_xfer_size == 1) { - dev->dmatxdescriptor[1] = (uint32_t) &(dev->dmatx_last16) + 1; - } else { - dev->dmatxdescriptor[1] = (uint32_t) &(dev->dmatx_last32) + 3; - } - if (dev->dmatxchanid >= DMAC_MEM_CHAN_CNT) { - dev->dmatxdescriptor[3] = 0; - } - } -} -#endif - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/ss_spi_master.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/ss_spi_master.c deleted file mode 100644 index 9d3b7e68..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/ss_spi_master.c +++ /dev/null @@ -1,416 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - - * 1) Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include "embARC_error.h" -#include "embARC_toolchain.h" -#include "arc/arc_exception.h" - -#include "device/subsystem/spi_master.h" -#include "device/subsystem/ss_spi_master.h" - -int32_t ss_spi_master_open(SS_SPI_MASTER_DEV_CONTEXT *ctx, uint32_t mode, uint32_t param) -{ - uint32_t dev_id = ctx->dev_id; - DEV_SPI_INFO *info = ctx->info; - io_cb_t callback; - uint32_t val; - - if (mode != DEV_MASTER_MODE) { - return E_PAR; - } - - if (info->opn_cnt > 0) { - if (param != info->freq) { - return E_OPNED; - } else { - return E_OK; - } - } - - if (io_spi_master_open(dev_id)) { - return E_SYS; - } - - callback.cb = (IO_CB_FUNC)ctx->int_rx_cb; - io_spi_master_ioctl(dev_id, IO_SET_CB_RX, &callback); - callback.cb = (IO_CB_FUNC)ctx->int_tx_cb; - io_spi_master_ioctl(dev_id, IO_SET_CB_TX, &callback); - callback.cb = (IO_CB_FUNC)ctx->int_err_cb; - io_spi_master_ioctl(dev_id, IO_SET_CB_ERR, &callback); - - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_DFS, &info->dfs); - val = 1; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_PACKING, &val); - - info->freq = param; - param = ctx->bus_freq / param; - - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_BAUD, ¶m); - info->opn_cnt++; - ctx->flags = 0; - -/* cs pin will toggle when FIFO is empty, to avoid this, spi master operation - * should not be interruptted by others. so set int pri to INT_PRI_MIN - */ - int_enable(ctx->intno_rx); - int_pri_set(ctx->intno_rx, INT_PRI_MIN); - int_enable(ctx->intno_tx); - int_pri_set(ctx->intno_tx, INT_PRI_MIN); - int_enable(ctx->intno_idle); - int_pri_set(ctx->intno_idle, INT_PRI_MIN); - int_enable(ctx->intno_err); - int_pri_set(ctx->intno_err, INT_PRI_MIN); - - return E_OK; -} - -int32_t ss_spi_master_close(SS_SPI_MASTER_DEV_CONTEXT *ctx) -{ - DEV_SPI_INFO *info = ctx->info; - - info->opn_cnt--; - if (info->opn_cnt == 0) { - io_spi_master_close(ctx->dev_id); - int_disable(ctx->intno_rx); - int_disable(ctx->intno_tx); - int_disable(ctx->intno_idle); - int_disable(ctx->intno_err); - info->status = DEV_DISABLED; - ctx->flags = 0; - } else { - return E_OPNED; - } - return E_OK; -} - -int32_t ss_spi_master_control(SS_SPI_MASTER_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param) -{ - uint32_t dev_id = ctx->dev_id; - DEV_SPI_INFO *info = ctx->info; - uint32_t val32 = (uint32_t)param; - DEV_BUFFER *buf = (DEV_BUFFER *)param; - DEV_SPI_TRANSFER *spi_xfer = &(info->xfer); - - switch (ctrl_cmd) { - case SPI_CMD_SET_TXINT_BUF: - if (buf && !(ctx->flags & SS_SPI_MASTER_FLAG_BUSY)) { - DEV_SPI_XFER_SET_TXBUF(spi_xfer, buf->buf, buf->ofs, buf->len); - ctx->flags |= SS_SPI_MASTER_FLAG_TX_READY; - } else { - return E_NOSPT; - } - break; - case SPI_CMD_SET_TXINT: - if (val32 && (ctx->flags & SS_SPI_MASTER_FLAG_TX_READY) && !(ctx->flags & SS_SPI_MASTER_FLAG_BUSY)) { - ctx->flags |= SS_SPI_MASTER_FLAG_BUSY; - val32 = SPI_TRANSMIT_ONLY_MODE; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_write(dev_id, spi_xfer->tx_buf + spi_xfer->tx_ofs, - &spi_xfer->tx_len); - } else { - return E_SYS; - } - break; - - case SPI_CMD_SET_RXINT_BUF: - if (buf && !(ctx->flags & SS_SPI_MASTER_FLAG_BUSY)) { - DEV_SPI_XFER_SET_RXBUF(spi_xfer, buf->buf, buf->ofs, buf->len); - ctx->flags |= SS_SPI_MASTER_FLAG_RX_READY; - } else { - return E_NOSPT; - } - break; - - case SPI_CMD_SET_RXINT: - if (val32 && (ctx->flags & SS_SPI_MASTER_FLAG_RX_READY) && !(ctx->flags & SS_SPI_MASTER_FLAG_BUSY)) { - ctx->flags |= SS_SPI_MASTER_FLAG_BUSY; - val32 = SPI_RECEIVE_ONLY_MODE; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_read(dev_id, spi_xfer->rx_buf + spi_xfer->rx_ofs, - &spi_xfer->rx_len); - } else { - return E_SYS; - } - break; - - case SPI_CMD_TRANSFER_INT: - if (param != NULL && !(ctx->flags & SS_SPI_MASTER_FLAG_BUSY)) { - ctx->flags = SS_SPI_MASTER_FLAG_BUSY | SS_SPI_MASTER_FLAG_TX_RX; - *spi_xfer = *((DEV_SPI_TRANSFER *)param); - - if (spi_xfer->rx_len == 0) { - val32 = SPI_TRANSMIT_ONLY_MODE; - ctx->flags |= SS_SPI_MASTER_FLAG_TX_READY; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_write(dev_id, spi_xfer->tx_buf, &spi_xfer->tx_len); - } else if (spi_xfer->tx_len == 0) { - val32 = SPI_RECEIVE_ONLY_MODE; - ctx->flags |= SS_SPI_MASTER_FLAG_RX_READY; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_read(dev_id, spi_xfer->rx_buf, &spi_xfer->rx_len); - } else if (spi_xfer->rx_ofs == spi_xfer->tx_len && spi_xfer->tx_ofs == 0) { - ctx->flags |= (SS_SPI_MASTER_FLAG_RX_READY | SS_SPI_MASTER_FLAG_TX_READY); - val32 = SPI_RECEIVE_AFTER_TRANSMIT_MODE; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_read(dev_id, spi_xfer->rx_buf, &spi_xfer->rx_len); - io_spi_master_write(dev_id, spi_xfer->tx_buf, &spi_xfer->tx_len); - } else { - - if (spi_xfer->tx_ofs != 0 || spi_xfer->rx_ofs != 0) { - return E_NOSPT; - } - - ctx->flags |= (SS_SPI_MASTER_FLAG_RX_READY | SS_SPI_MASTER_FLAG_TX_READY); - DEV_SPI_XFER_INIT(spi_xfer); - - val32 = SPI_TRANSMIT_RECEIVE_MODE; - - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_read(dev_id, spi_xfer->rx_buf, &spi_xfer->tot_len); - io_spi_master_write(dev_id, spi_xfer->tx_buf, &spi_xfer->tot_len); - } - } else { - return E_NOSPT; - } - break; - - case SPI_CMD_TRANSFER_POLLING: - if (param != NULL && !(ctx->flags & SS_SPI_MASTER_FLAG_BUSY)) { - spi_xfer = (DEV_SPI_TRANSFER *)param; - while (spi_xfer != NULL) { - ctx->flags = SS_SPI_MASTER_FLAG_BUSY; - DEV_SPI_XFER_INIT(spi_xfer); - io_spi_master_polling(dev_id, spi_xfer); - ctx->flags &= ~SS_SPI_MASTER_FLAG_BUSY; - spi_xfer = spi_xfer->next; - } - } else { - return E_NOSPT; - } - break; - - case SPI_CMD_SET_TXCB: - info->spi_cbs.tx_cb = param; - break; - - case SPI_CMD_SET_RXCB: - info->spi_cbs.rx_cb = param; - break; - - case SPI_CMD_SET_XFERCB: - info->spi_cbs.xfer_cb = param; - break; - - case SPI_CMD_SET_ERRCB: - info->spi_cbs.err_cb = param; - break; - - case SPI_CMD_SET_CLK_MODE: - switch (val32) { - case SPI_CPOL_0_CPHA_0: - val32 = 0; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPL, &val32); - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPH, &val32); - break; - case SPI_CPOL_0_CPHA_1: - val32 = 0; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPL, &val32); - val32 = 1; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPH, &val32); - break; - case SPI_CPOL_1_CPHA_0: - val32 = 1; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPL, &val32); - val32 = 0; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPH, &val32); - break; - case SPI_CPOL_1_CPHA_1: - val32 = 1; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPL, &val32); - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SCPH, &val32); - break; - } - break; - - case SPI_CMD_SET_DFS: - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_DFS, &val32); - break; - - case SPI_CMD_MST_SET_FREQ: - info->freq = val32; - val32 = ctx->bus_freq / val32; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_BAUD, &val32); - break; - - case SPI_CMD_MST_SEL_DEV: - info->slave = val32; - val32 = (1 << val32); - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SE, &val32); - break; - - case SPI_CMD_MST_DSEL_DEV: - val32 = info->slave & (~(1 << val32)); - info->slave = SPI_SLAVE_NOT_SELECTED; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_SE, &val32); - break; - - default: - return E_NOSPT; - } - return E_OK; -} - -int32_t ss_spi_master_write(SS_SPI_MASTER_DEV_CONTEXT *ctx, const void *data, uint32_t len) -{ - uint32_t dev_id = ctx->dev_id; - uint32_t len_ = len; - uint32_t val32 = SPI_TRANSMIT_ONLY_MODE; - - /* spi busy */ - if (ctx->flags & SS_SPI_MASTER_FLAG_BUSY) { - return E_NORES; - } - - if (arc_locked()) { - /* - * not allow to be called in isr or cpu is locked. - * Beacue the bottom drvier is simply interrupt driven - */ - return E_SYS; - } - - ctx->flags = SS_SPI_MASTER_FLAG_BUSY; - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_write(dev_id, (uint8_t *) data, &len_); - - /* wait finished: spi int enable & no cpu lock */ - while (ctx->flags & SS_SPI_MASTER_FLAG_BUSY) { - ; - } - - if (ctx->flags & SS_SPI_MASTER_FLAG_ERROR) { - ctx->flags = 0; - return E_SYS; - } - - ctx->flags = 0; - return E_OK; -} - -int32_t ss_spi_master_read(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *data, uint32_t len) -{ - uint32_t dev_id = ctx->dev_id; - uint32_t len_ = len; - uint32_t val32 = SPI_RECEIVE_ONLY_MODE; - - if (ctx->flags & SS_SPI_MASTER_FLAG_BUSY) { - return E_NORES; - } - - if (arc_locked()) { - /* - * not allow to be called in isr or cpu is locked. - * Beacue the bottom drvier is simply interrupt driven - */ - return E_SYS; - } - - ctx->flags = SS_SPI_MASTER_FLAG_BUSY; - - io_spi_master_ioctl(dev_id, IO_SPI_MASTER_SET_TRANSFER_MODE, &val32); - io_spi_master_read(dev_id, (uint8_t *)data, &len_); - - while (ctx->flags & SS_SPI_MASTER_FLAG_BUSY) { - ; - } - - if (ctx->flags & SS_SPI_MASTER_FLAG_ERROR) { - ctx->flags = 0; - return E_SYS; - } - ctx->flags = 0; - return 0; -} - -void ss_spi_master_tx_cb(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *param) -{ - DEV_SPI_INFO *info = ctx->info; - DEV_SPI_TRANSFER *spi_xfer = &(info->xfer); - - if (ctx->flags & SS_SPI_MASTER_FLAG_TX_RX) { - if (spi_xfer->rx_len == 0) { - ctx->flags &= ~SS_SPI_MASTER_FLAG_TX_RX; - - if (ctx->flags & SS_SPI_MASTER_FLAG_TX_READY && info->spi_cbs.xfer_cb) { - info->spi_cbs.xfer_cb(info); - } - } - } else if (ctx->flags & SS_SPI_MASTER_FLAG_TX_READY && info->spi_cbs.tx_cb) { - info->spi_cbs.tx_cb(info); - } - - ctx->flags &= ~(SS_SPI_MASTER_FLAG_TX_READY | SS_SPI_MASTER_FLAG_BUSY); - -} - -void ss_spi_master_rx_cb(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *param) -{ - DEV_SPI_INFO *info = ctx->info; - - if (ctx->flags & SS_SPI_MASTER_FLAG_TX_RX) { - if (ctx->flags & SS_SPI_MASTER_FLAG_RX_READY && info->spi_cbs.xfer_cb) { - info->spi_cbs.xfer_cb(info); - } - ctx->flags &= ~(SS_SPI_MASTER_FLAG_RX_READY | SS_SPI_MASTER_FLAG_TX_READY | - SS_SPI_MASTER_FLAG_BUSY | SS_SPI_MASTER_FLAG_TX_RX); - - } else { - if (ctx->flags & SS_SPI_MASTER_FLAG_RX_READY && info->spi_cbs.rx_cb) { - info->spi_cbs.rx_cb(info); - } - - ctx->flags &= ~(SS_SPI_MASTER_FLAG_RX_READY | SS_SPI_MASTER_FLAG_BUSY); - } -} - -void ss_spi_master_err_cb(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *param) -{ - DEV_SPI_INFO *info = ctx->info; - - ctx->flags = SS_SPI_MASTER_FLAG_ERROR; - - if (info->spi_cbs.err_cb) { - info->spi_cbs.err_cb(info); - } -} \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/ss_spi_slave.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/ss_spi_slave.c deleted file mode 100644 index 3c7b0166..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/spi/ss_spi_slave.c +++ /dev/null @@ -1,33 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - - * 1) Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/uart/ss_uart.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/uart/ss_uart.c deleted file mode 100644 index eb9a2dff..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/uart/ss_uart.c +++ /dev/null @@ -1,440 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include "embARC_error.h" -#include "embARC_toolchain.h" -#include "arc/arc_exception.h" - -#include "device/subsystem/uart.h" -#include "device/subsystem/ss_uart.h" -#include "io_config.h" - -/* APEX UART device registers */ -#define UART_RBR (0x00) -#define UART_THR (0x00) -#define UART_DLL (0x00) -#define UART_IER (0x04) -#define UART_DLH (0x04) -#define UART_IIR (0x08) -#define UART_FCR (0x08) -#define UART_LCR (0x0c) -#define UART_MCR (0x10) -#define UART_LSR (0x14) // unused -#define UART_MSR (0x18) // unused -#define UART_USR (0x7c) // unused -#define UART_CLKEN (0xc0) - -#define REG_READ(x) arc_aux_read((ctx->reg_base + x)) -#define REG_WRITE(x, y) arc_aux_write((ctx->reg_base + x), y) - -/** convert uart baudrate to subsystem divisor */ -#define SS_UART_BAUD2DIV(perifreq, baud) ((perifreq) / ((baud) * 16) + 1) - -/** - * @fn int32_t set_hwfc(uint32_t dev_id, uint32_t control) - */ -Inline int32_t set_hwfc(uint32_t dev_id, uint32_t control) -{ - uint32_t param = 0; - - if (control == UART_FC_NONE) { - param = 0; - } else { - param = 1; - } - - io_uart_ioctl(dev_id, IO_UART_SET_FLOW_CONTROL, ¶m); - - return E_OK; -} - -/** - * @fn int32_t set_baud(SS_UART_DEV_CONTEXT *ctx, uint32_t baud) - */ -Inline int32_t set_baud(SS_UART_DEV_CONTEXT *ctx, uint32_t baud) -{ - uint32_t param; - DEV_UART_INFO *info = ctx->info; - - param = SS_UART_BAUD2DIV(ctx->bus_freq, baud); - io_uart_ioctl(ctx->dev_id, IO_UART_SET_DLx, ¶m); - info->baudrate = baud; - - return E_OK; -} - -static int32_t set_dps(uint32_t dev_id, const UART_DPS_FORMAT *format) -{ - uint32_t param = 0; - - switch (format->databits) { - case 6: - param |= 0x1; - break; - case 7: - param |= 0x2; - break; - case 8: - param |= 0x3; - break; - default: - return E_NOSPT; - } - - if (format->stopbits == UART_STPBITS_ONE) { - - } else if (format->stopbits == UART_STPBITS_ONEHALF && format->databits == 5) { - param |= 0x4; - } else { - return E_NOSPT; - } - - if (format->parity != UART_PARITY_NONE) { - param |= 0x8; // PEN - - if (format->parity == UART_PARITY_EVEN) { - param |= 0x10; // EPS - } else if (format->parity == UART_PARITY_MARK) { - // PEN & Stick parity = logic 1 - param |= (0x20); - } else if (format->parity == UART_PARITY_SPACE) { - // PEN & EPS & Stick parity = logic 0 - param |= (0x10 | 0x20); - } - } - - io_uart_ioctl(dev_id, IO_UART_SET_LCR, ¶m); - - return E_OK; -} - -static void io_uart_poll_write(SS_UART_DEV_CONTEXT *ctx, uint8_t *data, uint32_t *size) -{ - uint32_t old_val; - uint32_t i = 0; - uint32_t len; - - /* disbale uart interrupt */ - old_val = REG_READ(UART_IER); - REG_WRITE(UART_IER, 0x80); - - len = *size; - while (i < len) { - while ((REG_READ(UART_LSR) & 0x20)) { - ; // wait THR empty - } - REG_WRITE(UART_THR, data[i++]); - } - - REG_WRITE(UART_IER, old_val); -} - -static void io_uart_poll_read(SS_UART_DEV_CONTEXT *ctx, uint8_t *data, uint32_t *size) -{ - uint32_t i = 0; - uint32_t len; - uint32_t old_val; - - old_val = REG_READ(UART_IER); - REG_WRITE(UART_IER, 0x80); - - len = *size; - while (i < len) { - while (!(REG_READ(UART_LSR) & 0x1)) { - ; // wait data ready - } - data[i++] = REG_READ(UART_RBR); - } - - REG_WRITE(UART_IER, old_val); -} - -static void io_uart_rx_int(SS_UART_DEV_CONTEXT *ctx, uint32_t enable) -{ - uint32_t val; - - if (enable) { - /* enable ERBFI interrupt */ - val = REG_READ(UART_IER) | 0x1; - REG_WRITE(UART_IER, val); - } else { - val = REG_READ(UART_IER) & ~0x1; - REG_WRITE(UART_IER, val); - } -} - -static void io_uart_tx_int(SS_UART_DEV_CONTEXT *ctx, uint32_t enable) -{ - uint32_t val; - - if (enable) { - /* enable ETBEI interrupt and enable use of interrupt for TX threshold */ - val = REG_READ(UART_IER) | 0x82; - REG_WRITE(UART_IER, val); - } else { - val = REG_READ(UART_IER) & ~0x82; - REG_WRITE(UART_IER, val); - } -} - -int32_t ss_uart_open(SS_UART_DEV_CONTEXT *ctx, uint32_t baud) -{ - int32_t ret = E_OK; - DEV_UART_INFO *info = ctx->info; - io_cb_t callback; - int32_t dev_id = ctx->dev_id; - - info->opn_cnt++; - - if (info->opn_cnt > 1) { - if (baud == info->baudrate) { - return E_OK; - } else { - return E_OPNED; - } - } - - if (io_uart_open(dev_id)) { - return E_SYS; - } - - callback.cb = (IO_CB_FUNC)ctx->tx_cb; - io_uart_ioctl(dev_id, IO_SET_CB_TX, &callback); - - callback.cb = (IO_CB_FUNC)ctx->rx_cb; - io_uart_ioctl(dev_id, IO_SET_CB_RX, &callback); - - callback.cb = (IO_CB_FUNC)ctx->err_cb; - io_uart_ioctl(dev_id, IO_SET_CB_ERR, &callback); - - UART_DPS_FORMAT_DEFAULT(info->dps_format); - set_dps(dev_id, &info->dps_format); - - info->hwfc = UART_FC_DEFAULT; - set_hwfc(dev_id, info->hwfc); - - set_baud(ctx, baud); - - ctx->flags = 0; - - info->baudrate = baud; - - int_enable(ctx->intno); - - return ret; -} - -int32_t ss_uart_close(SS_UART_DEV_CONTEXT *ctx) -{ - DEV_UART_INFO *info = ctx->info; - - info->opn_cnt--; - if (info->opn_cnt == 0) { - info->baudrate = 0; - io_uart_close(ctx->dev_id); - int_disable(ctx->intno); - } - - return E_OK; -} - -int32_t ss_uart_control(SS_UART_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param) -{ - DEV_BUFFER *devbuf; - uint32_t int_val = (uint32_t)param; - int32_t dev_id = ctx->dev_id; - DEV_UART_INFO *info = ctx->info; - - switch (ctrl_cmd) { - case UART_CMD_SET_BAUD: - return set_baud(ctx, int_val); - case UART_CMD_SET_HWFC: - io_uart_ioctl(dev_id, IO_UART_SET_FLOW_CONTROL, param); - return E_OK; - case UART_CMD_SET_DPS_FORMAT: - return set_dps(dev_id, (UART_DPS_FORMAT *)param); - case UART_CMD_GET_RXAVAIL: - if (REG_READ(UART_LSR) & 0x1) { - /* at least one byte */ - *((uint32_t *)param) = 1; - } else { - *((uint32_t *)param) = 0; - } - return E_OK; - case UART_CMD_GET_TXAVAIL: - int_val = REG_READ(UART_LSR); - if (int_val & 0x40) { - *((uint32_t *)param) = IO_UART0_FS; - } else { - if (int_val & 0x20) { - /* FIFO full */ - *((uint32_t *)param) = 0; - } else { - *((uint32_t *)param) = 1; - } - } - return E_OK; - case UART_CMD_SET_RXCB: - info->uart_cbs.rx_cb = param; - return E_OK; - case UART_CMD_SET_TXCB: - info->uart_cbs.tx_cb = param; - return E_OK; - case UART_CMD_SET_ERRCB: - info->uart_cbs.err_cb = param; - return E_OK; - case UART_CMD_SET_TXINT: - io_uart_tx_int(ctx, int_val); - return E_OK; - case UART_CMD_SET_RXINT: - io_uart_rx_int(ctx, int_val); - return E_OK; - case UART_CMD_SET_TXINT_BUF: - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - info->tx_buf = *devbuf; - info->tx_buf.ofs = 0; - io_uart_write(dev_id, (uint8_t *)(devbuf->buf), - &(devbuf->len)); - } else { - info->tx_buf.buf = NULL; - info->tx_buf.len = 0; - info->tx_buf.ofs = 0; - io_uart_write(dev_id, NULL, &(info->tx_buf.len)); - } - break; - case UART_CMD_SET_RXINT_BUF: - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - info->rx_buf = *devbuf; - info->rx_buf.ofs = 0; - io_uart_read(dev_id, (uint8_t *)(devbuf->buf), - &(devbuf->len)); - } else { - info->rx_buf.buf = NULL; - info->rx_buf.len = 0; - info->rx_buf.ofs = 0; - io_uart_read(dev_id, NULL, &(info->rx_buf.len)); - } - break; - case UART_CMD_BREAK_SET: - case UART_CMD_BREAK_CLR: - return E_NOSPT; - default: - return E_NOSPT; - } - return E_OK; -} - -int32_t ss_uart_write(SS_UART_DEV_CONTEXT *ctx, const void *data, uint32_t len) -{ - uint32_t dev_id = ctx->dev_id; - - if (arc_locked() || arc_int_active()) { - io_uart_poll_write(ctx, (uint8_t *) data, &len); - } else { - ctx->flags = SS_UART_FLAG_TX; - io_uart_write(dev_id, (uint8_t *) data, &len); - - /* wait finished: uart int enable & no cpu lock */ - while (ctx->flags & SS_UART_FLAG_TX) { - ; - } - - if (ctx->flags & SS_UART_FLAG_ERROR) { - ctx->flags = 0; - return E_SYS; - } - - ctx->flags = 0; - } - - return len; -} - -int32_t ss_uart_read(SS_UART_DEV_CONTEXT *ctx, void *data, uint32_t len) -{ - int32_t dev_id = ctx->dev_id; - - if (arc_locked() || arc_int_active()) { - io_uart_poll_read(ctx, (uint8_t *) data, &len); - } else { - ctx->flags = SS_UART_FLAG_RX; - - io_uart_read(dev_id, (uint8_t *) data, &len); - - /* wait finished: uart int enable & no cpu lock */ - while (ctx->flags & SS_UART_FLAG_RX) { - ; - } - - if (ctx->flags & SS_UART_FLAG_ERROR) { - ctx->flags = 0; - return E_SYS; - } - - ctx->flags = 0; - } - - return len; -} - -void ss_uart_tx_cb(SS_UART_DEV_CONTEXT *ctx, void *param) -{ - DEV_UART_INFO *info = ctx->info; - - if (ctx->flags & SS_UART_FLAG_TX) { - ctx->flags &= ~SS_UART_FLAG_TX; - } else if (info->uart_cbs.tx_cb) { - info->uart_cbs.tx_cb(info); - } -} - -void ss_uart_rx_cb(SS_UART_DEV_CONTEXT *ctx, void *param) -{ - DEV_UART_INFO *info = ctx->info; - - if (ctx->flags & SS_UART_FLAG_RX) { - ctx->flags &= ~SS_UART_FLAG_RX; - } else if (info->uart_cbs.rx_cb) { - info->uart_cbs.rx_cb(info); - } -} - -void ss_uart_err_cb(SS_UART_DEV_CONTEXT *ctx, void *param) -{ - DEV_UART_INFO *info = ctx->info; - - ctx->flags = SS_UART_FLAG_ERROR; - - if (info->uart_cbs.err_cb) { - info->uart_cbs.err_cb(info); - } -} \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/uart/uart.c b/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/uart/uart.c deleted file mode 100644 index c870dbee..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/ip/subsystem/uart/uart.c +++ /dev/null @@ -1,950 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#include -#include -#include -#include "device/subsystem/uart.h" -#include "io_config.h" -#include "apexextensions.h" - -/* APEX UART device registers */ -#define UART_RBR (0x00) -#define UART_THR (0x00) -#define UART_DLL (0x00) -#define UART_IER (0x04) -#define UART_DLH (0x04) -#define UART_IIR (0x08) -#define UART_FCR (0x08) -#define UART_LCR (0x0c) -#define UART_MCR (0x10) -#define UART_LSR (0x14) // unused -#define UART_MSR (0x18) // unused -#define UART_USR (0x7c) // unused -#define UART_CLKEN (0xc0) - -#define DMA_NONE (0xff) - -#define FLOW_CONTROL_OFF 0 // Flow Control is OFF -#define FLOW_CONTROL_ON 1 // Using software implementation of CTS/RTS handling - -#define nCTS_LOW 0 -#define nCTS_HIGH 1 - -typedef _Interrupt void (*ISR) (); - -/* Private data structure maintained by the driver. */ -typedef struct uart_info_struct { - uint32_t reg_base; /* base address of device register set */ - /* TX & RX Buffer and lengths */ - uint8_t *tx_data; - uint32_t tx_size; - uint32_t tx_count; - uint8_t *rx_data; - uint32_t rx_size, *p_rxsize; - uint32_t rx_count; - - uint8_t instID; - uint16_t dmarxchanid, dmatxchanid; -#ifdef __Xdmac - _Uncached uint32_t *dmarxdescriptor, *dmatxdescriptor; - uint8_t dmarxidx; - uint8_t dmatxidx; -#endif - /* Callbacks */ - IO_CB_FUNC tx_cb; - IO_CB_FUNC rx_cb; - IO_CB_FUNC err_cb; - /* Interrupt numbers and handlers */ - uint8_t isr_vector; /* ISR vector */ - ISR uart_isr; /* UART device ISRs */ - ISR uart_dmatx_isr; /* UART DMA TX ISRs */ - ISR uart_dmarx_isr; /* UART DMA RX ISRs */ - - uint32_t fifo_depth, rx_threshold, tx_threshold; - uint8_t fcr_mirror; - uint8_t flow_control; - uint8_t nCTS_state; -} uart_info_t, *uart_info_pt; - -#ifdef IO_UART0_PRESENT -#define UART_DEV_PRESENT -#endif -#ifdef IO_UART1_PRESENT -#define UART_DEV_PRESENT -#endif -#ifdef IO_UART2_PRESENT -#define UART_DEV_PRESENT -#endif -#ifdef IO_UART3_PRESENT -#define UART_DEV_PRESENT -#endif - -#ifdef UART_DEV_PRESENT - -#define UART_MAX_CNT (4) - -static void uart_isr_proc(uint32_t dev_id); -static void uart_dmatx_isr_proc(uint32_t dev_id); -static void uart_dmarx_isr_proc(uint32_t dev_id); - -#ifdef IO_UART0_PRESENT -static _Interrupt void uart0_ISR() -{ - uart_isr_proc(0); -} - -static _Interrupt void uart0_dmatx_ISR() -{ - uart_dmatx_isr_proc(0); -} - -static _Interrupt void uart0_dmarx_ISR() -{ - uart_dmarx_isr_proc(0); -} -#endif -#ifdef IO_UART1_PRESENT -static _Interrupt void uart1_ISR() -{ - uart_isr_proc(1); -} - -static _Interrupt void uart1_dmatx_ISR() -{ - uart_dmatx_isr_proc(1); -} - -static _Interrupt void uart1_dmarx_ISR() -{ - uart_dmarx_isr_proc(1); -} -#endif -#ifdef IO_UART2_PRESENT -static _Interrupt void uart2_ISR() -{ - uart_isr_proc(2); -} - -static _Interrupt void uart2_dmatx_ISR() -{ - uart_dmatx_isr_proc(2); -} - -static _Interrupt void uart2_dmarx_ISR() -{ - uart_dmarx_isr_proc(2); -} -#endif -#ifdef IO_UART3_PRESENT -static _Interrupt void uart3_ISR() -{ - uart_isr_proc(3); -} - -static _Interrupt void uart3_dmatx_ISR() -{ - uart_dmatx_isr_proc(3); -} - -static _Interrupt void uart3_dmarx_ISR() -{ - uart_dmarx_isr_proc(3); -} -#endif - -#ifdef __Xdmac -static void create_dma_descriptor_rx(uart_info_pt dev, uint32_t burst, - uint8_t idx); -static void create_dma_descriptor_tx(uart_info_pt dev, uint32_t burst, - uint8_t idx); -#endif - -/* UART devices private data structures */ -static uart_info_pt uart_handles[UART_MAX_CNT] = { 0 }; - -#ifdef __Xdmac -static _Uncached uint32_t uart_dmarx_descriptors[8 * UART_MAX_CNT]; -static _Uncached uint32_t uart_dmatx_descriptors[8 * UART_MAX_CNT]; -#endif - -static uart_info_t uart_devs[] = { -#ifdef IO_UART0_PRESENT - { .instID = 0, - .reg_base = AR_IO_UART0_RBR_THR_DLL, - .isr_vector = IO_UART0_INTR, - .uart_isr = uart0_ISR, - .uart_dmatx_isr = uart0_dmatx_ISR, - .uart_dmarx_isr = uart0_dmarx_ISR, -#ifdef IO_UART0_DMA_RX - .dmarxchanid = IO_UART0_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_UART0_DMA_TX - .dmatxchanid = IO_UART0_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_UART0_FS }, -#endif -#ifdef IO_UART1_PRESENT - { .instID = 1, - .reg_base = AR_IO_UART1_RBR_THR_DLL, - .isr_vector = IO_UART1_INTR, - .uart_isr = uart1_ISR, - .uart_dmatx_isr = uart1_dmatx_ISR, - .uart_dmarx_isr = uart1_dmarx_ISR, -#ifdef IO_UART1_DMA_RX - .dmarxchanid = IO_UART1_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_UART1_DMA_TX - .dmatxchanid = IO_UART1_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_UART1_FS }, -#endif -#ifdef IO_UART2_PRESENT - { .instID = 2, - .reg_base = AR_IO_UART2_RBR_THR_DLL, - .isr_vector = IO_UART2_INTR, - .uart_isr = uart2_ISR, - .uart_dmatx_isr = uart2_dmatx_ISR, - .uart_dmarx_isr = uart2_dmarx_ISR, -#ifdef IO_UART2_DMA_RX - .dmarxchanid = IO_UART2_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_UART2_DMA_TX - .dmatxchanid = IO_UART2_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_UART2_FS }, -#endif -#ifdef IO_UART3_PRESENT - { .instID = 3, - .reg_base = AR_IO_UART3_RBR_THR_DLL, - .isr_vector = IO_UART3_INTR, - .uart_isr = uart3_ISR, - .uart_dmatx_isr = uart3_dmatx_ISR, - .uart_dmarx_isr = uart3_dmarx_ISR, -#ifdef IO_UART3_DMA_RX - .dmarxchanid = IO_UART3_DMA_RX, -#else - .dmarxchanid = DMA_NONE, -#endif -#ifdef IO_UART3_DMA_TX - .dmatxchanid = IO_UART3_DMA_TX, -#else - .dmatxchanid = DMA_NONE, -#endif - .fifo_depth = IO_UART3_FS }, -#endif - { .instID = UART_MAX_CNT } -}; - -#define REG_WRITE(reg, x) _sr((unsigned)(x), (unsigned)(dev->reg_base + reg)) -#define REG_READ(reg) _lr((unsigned)(dev->reg_base + reg)) - -uint32_t io_uart_open(uint32_t dev_id) -{ - uint32_t h = 0; - uint32_t val = 0; - uart_info_pt dev; - - h = 0; - while ((uart_devs[h].instID != dev_id) - && (uart_devs[h].instID != UART_MAX_CNT)) { - h++; - } - if ((uart_devs[h].instID == UART_MAX_CNT) || (0 != uart_handles[dev_id])) { /* dev_id not part of design, or still open */ - return 1; - } - uart_handles[dev_id] = &uart_devs[h]; - dev = uart_handles[dev_id]; - - REG_WRITE(UART_CLKEN, 0x1); - REG_WRITE(UART_IER, 0x0); - REG_READ(UART_RBR); - - /* when there are fifos available, always enable and reset these */ - if (dev->fifo_depth != 0) { - REG_WRITE(UART_FCR, 0x07); - dev->fcr_mirror = 0; - dev->rx_threshold = 1; - dev->tx_threshold = 0; - } - - /* save nCTS state */ - val = REG_READ(UART_MSR); - dev->nCTS_state = (val & 0x10) ? nCTS_LOW : nCTS_HIGH; - - _setvecti(dev->isr_vector, dev->uart_isr); - -#ifdef __Xdmac - dev->dmarxdescriptor = &uart_dmarx_descriptors[8 * h]; - dev->dmatxdescriptor = &uart_dmatx_descriptors[8 * h]; - - if (dev->dmarxchanid != DMA_NONE) { - dev->dmarxdescriptor[1] = dev->dmarxdescriptor[4 + 1] = - dev->reg_base + UART_RBR; - dev->dmarxdescriptor[3] = (uint32_t) &(dev->dmarxdescriptor[4]); - dev->dmarxdescriptor[4 + 3] = - (uint32_t) &(dev->dmarxdescriptor[0]); - - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, dev->uart_dmarx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, dev->uart_isr); - } - - if (dev->dmatxchanid != DMA_NONE) { - dev->dmatxdescriptor[2] = dev->dmatxdescriptor[4 + 2] = - dev->reg_base + UART_THR; - dev->dmatxdescriptor[3] = (uint32_t) &(dev->dmatxdescriptor[4]); - dev->dmatxdescriptor[4 + 3] = - (uint32_t) &(dev->dmatxdescriptor[0]); - - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, dev->uart_dmatx_isr); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, dev->uart_isr); - } -#endif - - return 0; -} - -void io_uart_close(uint32_t dev_id) -{ - uart_info_pt dev = uart_handles[dev_id]; - - // bring uart instance to reset state - if (dev->fifo_depth != 0) { - REG_WRITE(UART_FCR, 0x07); // reset FIFOs - } - REG_WRITE(UART_IER, 0x0); // clear interrupt enable register - - /* gate the UART clock */ - REG_WRITE(UART_CLKEN, 0x0); - - _setvecti(dev->isr_vector, NULL); - -#ifdef __Xdmac - if (dev->dmarxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmarxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmarxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmarxchanid); - } - - if (dev->dmatxchanid != DMA_NONE) { - _setvecti(DMAC_INT_BASE + dev->dmatxchanid, NULL); - _setvecti(DMAC_ERR_BASE + dev->dmatxchanid, NULL); - _dma_chan_reset(0x1 << dev->dmatxchanid); - } -#endif - - dev->rx_cb = NULL; - dev->tx_cb = NULL; - dev->err_cb = NULL; - - uart_handles[dev_id] = 0; -} - -void io_uart_read(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - uart_info_pt dev = uart_handles[dev_id]; - uint32_t val = 0; - - dev->rx_data = data; - dev->rx_size = *size; - dev->p_rxsize = size; - dev->rx_count = 0; - -#ifdef __Xdmac - if (dev->dmarxchanid == DMA_NONE) { -#endif - if (dev->rx_size > 0) { - if ((dev->fifo_depth != 0) && (dev->rx_size < dev->rx_threshold)) { - /* temporary reset the rx_threshold to 1 */ - REG_WRITE(UART_FCR, (((dev->fcr_mirror & ~0xC) << 4) | 0x01)); - } - /* enable ERBFI and ELSI interrupt */ - val = REG_READ(UART_IER) | 0x5; - REG_WRITE(UART_IER, val); - } -#ifdef __Xdmac -} else { /* DMA: create descriptor */ - if (dev->rx_size != 0) { - if (dev->fifo_depth == 0) { /* fifos are not available */ - val = 1; - } else { - val = dev->rx_threshold; - } - create_dma_descriptor_rx(dev, val, 0); - if (dev->rx_size != dev->rx_count) { - create_dma_descriptor_rx(dev, val, 4); - } - - /* init dma */ - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmarxchanid, - &(dev->dmarxdescriptor[0])); - } - - dev->dmarxidx = 0; - - _dma_chan_enable((0x1 << dev->dmarxchanid), 1); - - /* enable ELSI interrupt */ - val = REG_READ(UART_IER) | 0x4; - REG_WRITE(UART_IER, val); - } -} -/* - * De-assert nRTS line if flow control is enabled - * Note that UART controller inverts the MCR bit value - */ -if (dev->flow_control == FLOW_CONTROL_ON) { - val = REG_READ(UART_MCR) | 0x2; - REG_WRITE(UART_MCR, val); -} -#endif -} - -void io_uart_write(uint32_t dev_id, uint8_t *data, uint32_t *size) -{ - uart_info_pt dev = uart_handles[dev_id]; - uint32_t cnt = 0; - uint32_t h = 0; - uint32_t val = 0; - - dev->tx_data = data; - dev->tx_size = *size; - dev->tx_count = 0; - -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* If... - * - flow control is disabled or - * - flow control is enabled && nCTS is already LOW - * ...start data transmit immediately, wait for nCTS change IRQ otherwise */ - if ((dev->flow_control == FLOW_CONTROL_OFF) || - ((dev->flow_control == FLOW_CONTROL_ON) - && (dev->nCTS_state == nCTS_LOW))) { - /* write first bytes to fifo (if any) */ - cnt = dev->tx_size - dev->tx_count; - if (cnt > 0) { - if (dev->fifo_depth == 0) { /* fifos are not available */ - cnt = 1; - } else if (cnt > dev->fifo_depth) { /* fifos enabled (and by definition != FIFO_NONE) */ - cnt = dev->fifo_depth; - } - for (h = 0; h != cnt; h++) { - REG_WRITE(UART_THR, (dev->tx_data[dev->tx_count++])); - } - /* enable ETBEI interrupt and enable use of interrupt for TX threshold */ - val = REG_READ(UART_IER) | 0x82; - REG_WRITE(UART_IER, val); - } - } -#ifdef __Xdmac -} else { - /* DMA: create descriptor */ - if (dev->fifo_depth == 0) { /* fifos are not available */ - cnt = 1; - } else { - cnt = dev->fifo_depth - dev->tx_threshold; - } - create_dma_descriptor_tx(dev, cnt, 0); - if (dev->tx_size != dev->tx_count) { - create_dma_descriptor_tx(dev, cnt, 4); - } - /* init dma */ - if (dev->dmatxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc(dev->dmatxchanid, &(dev->dmatxdescriptor[0])); - } else { - _dma_chan_desc_aux(dev->dmatxchanid, - &(dev->dmatxdescriptor[0])); - } - - dev->dmatxidx = 0; - - /* If nCTS is already LOW and flow control is enabled - start data transmit immediately, - * wait for nCTS change IRQ otherwise */ - if (! - ((dev->flow_control == FLOW_CONTROL_ON) - && (dev->nCTS_state == nCTS_HIGH))) { - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); - } -} -#endif -} - -void io_uart_ioctl(uint32_t dev_id, uint32_t cmd, void *arg) -{ - uart_info_pt dev = uart_handles[dev_id]; - uint32_t val = 0; - - switch (cmd) { - case IO_SET_CB_RX: - dev->rx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_TX: - dev->tx_cb = ((io_cb_t *) arg)->cb; - break; - case IO_SET_CB_ERR: - dev->err_cb = ((io_cb_t *) arg)->cb; - break; -#if 0 - case IO_UART_SET_MCR: // not part of public API (yet) - REG_WRITE(UART_MCR, *((uint32_t *) arg)); - break; - case IO_UART_GET_MCR: // not part of public API (yet) - *((uint32_t *) arg) = REG_READ(UART_MCR); - break; -#endif - case IO_UART_SET_LCR: - /* leave the LDAB bit cleared */ - REG_WRITE(UART_LCR, (*((uint32_t *) arg) & 0x7f)); - break; - case IO_UART_GET_LCR: - *((uint32_t *) arg) = REG_READ(UART_LCR); - break; - case IO_UART_SET_DLx: - /* 16 bit divisor --> DLL (lower 8) and DLH (upper 8) registers */ - /* set LDAB bit for DLx register access, first */ - val = REG_READ(UART_LCR); - REG_WRITE(UART_LCR, (val | (0x1 << 7))); - REG_WRITE(UART_DLL, (*((uint32_t *) arg) & 0x00ff)); - REG_WRITE(UART_DLH, ((*((uint32_t *) arg) & 0xff00) >> 8)); - REG_WRITE(UART_LCR, val); - break; - case IO_UART_GET_DLx: - /* set LDAB bit for DLx register access, first */ - val = REG_READ(UART_LCR); - REG_WRITE(UART_LCR, (val | (0x1 << 7))); - *((uint32_t *) arg) = - (REG_READ(UART_DLL) | (REG_READ(UART_DLH) << 8)); - REG_WRITE(UART_LCR, val); - break; - case IO_UART_SET_RX_THRESHOLD: - /* precondition: can only be called for dev->fifo_depth != 0 */ - val = *((uint32_t *) arg); - dev->fcr_mirror = (dev->fcr_mirror & ~0xC) | (val << 2); - REG_WRITE(UART_FCR, ((dev->fcr_mirror << 4) | 0x01)); - if (val == 0) { - dev->rx_threshold = 1; - } else if (val == 1) { - dev->rx_threshold = dev->fifo_depth >> 2; - } else if (val == 2) { - dev->rx_threshold = dev->fifo_depth >> 1; - } else if (val == 3) { - dev->rx_threshold = dev->fifo_depth - 2; - } - break; - case IO_UART_SET_TX_THRESHOLD: - /* precondition: can only be called for dev->fifo_depth != 0 */ - val = *((uint32_t *) arg); - dev->fcr_mirror = (dev->fcr_mirror & ~0x3) | val; - REG_WRITE(UART_FCR, ((dev->fcr_mirror << 4) | 0x01)); - if (val == 0) { - dev->tx_threshold = 0; - } else if (val == 1) { - dev->tx_threshold = 2; - } else if (val == 2) { - dev->tx_threshold = dev->fifo_depth >> 2; - } else if (val == 3) { - dev->tx_threshold = dev->fifo_depth >> 1; - } - break; - case IO_UART_SET_FLOW_CONTROL: - if ((uint32_t) (*((uint32_t *) arg)) == 1) { - // Enable Flow Control - dev->flow_control = FLOW_CONTROL_ON; // Use software implementation of CTS/RTS control - val = REG_READ(UART_IER) | 0x08; - REG_WRITE(UART_IER, val); // Enable modem status interrupt - - val = REG_READ(UART_MSR); - if (val & 0x10) { - dev->nCTS_state = nCTS_LOW; - } else { - dev->nCTS_state = nCTS_HIGH; - } - } else { - // Diable Flow Control - dev->flow_control = FLOW_CONTROL_OFF; - val = REG_READ(UART_IER) & ~0x08; - REG_WRITE(UART_IER, val); // Disable modem status interrupt - } - break; - default: - break; - } -} - -static void uart_isr_proc(uint32_t dev_id) -{ - uart_info_pt dev = uart_handles[dev_id]; - uint32_t intid = 0; - uint32_t cnt = 0; - uint32_t h = 0; - volatile uint32_t val = 0; - - intid = REG_READ(UART_IIR) & 0x0f; - - /* workaround for break detect: break interrupt may have been cleared by DMAC reading from rxfifo... */ - if (intid == 0x1) { /* break detect + dma: copy source from while loop */ - /* line break detected; complete read immediately */ -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - *(dev->p_rxsize) = dev->rx_count; - REG_READ(UART_RBR); -#ifdef __Xdmac - } else { - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc_get_ctrl(dev->dmarxchanid, &val); - } else { - _dma_chan_desc_aux_get_ctrl(dev->dmarxchanid, &val); - } - *(dev->p_rxsize) = dev->rx_count - 1 - ((val >> 8) & 0x1fff); - *(dev->p_rxsize) -= 1; - } -#endif - /* disable (ERBFI and) ELSI interrupt */ - val = REG_READ(UART_IER) & ~0x5; - REG_WRITE(UART_IER, val); - if (dev->fifo_depth != 0) { /* restore threshold to user defined value */ - REG_WRITE(UART_FCR, ((dev->fcr_mirror << 4) | 0x01)); - } - /* call user callback function, if any */ - if (dev->rx_cb != 0) { - dev->rx_cb(dev_id); - } - } - - while (intid != 0x1) { - switch (intid) { - case 0x2: - { /* tx empty */ - if (dev->tx_data == NULL) { - if (dev->tx_cb != 0) { - dev->tx_cb(dev_id); - } else { - val = REG_READ(UART_IER) & ~0x82; - REG_WRITE(UART_IER, val); - } - } else { - if (dev->tx_count == dev->tx_size) { /* disable ETBEI interrupt (and disable threshold interrupt IER[7]) */ - val = REG_READ(UART_IER) & ~0x82; - REG_WRITE(UART_IER, val); - /* call user callback function, if any */ - if (dev->tx_cb != 0) { - dev->tx_cb(dev_id); - } - dev->tx_size = 0; // indicates no TX pending - } else { - /* write next bytes to fifo (if any) */ - cnt = dev->tx_size - dev->tx_count; - if (dev->fifo_depth == 0) { /* fifos are not available */ - cnt = 1; - } else if (cnt > dev->fifo_depth) { /* fifos enabled (and by definition != FIFO_NONE) */ - cnt = dev->fifo_depth; - } - if (REG_READ(UART_IER) & 0x80) { /* if IER[7] is set, threshold shall be taken into account */ - if (cnt > (dev->fifo_depth - dev->tx_threshold)) { - cnt = dev->fifo_depth - dev->tx_threshold; - } - } - for (h = 0; h != cnt; h++) { - REG_WRITE(UART_THR, - (dev->tx_data[dev->tx_count++])); - } - } - } - break; - } - case 0x4: - { /* rx data available; at least one, more is uncertain */ - if (dev->rx_data == NULL) { - if (dev->rx_cb != 0) { - dev->rx_cb(dev_id); - } else { - REG_READ(UART_RBR); - } - } else { - if (dev->fifo_depth == 0) { - dev->rx_data[dev->rx_count++] = REG_READ(UART_RBR); - } else { - cnt = dev->rx_size - dev->rx_count; - if (cnt < dev->rx_threshold) { - dev->rx_data[dev->rx_count++] = REG_READ(UART_RBR); - } else { - for (h = 0; h != dev->rx_threshold; h++) { - dev->rx_data[dev->rx_count++] = - REG_READ(UART_RBR); - } - cnt -= dev->rx_threshold; - if (cnt < dev->rx_threshold) { - /* temporary reset the rx_threshold to 1 */ - REG_WRITE(UART_FCR, - (((dev-> - fcr_mirror & ~0xC) << 4) | 0x01)); - } - } - } - if (dev->rx_count == dev->rx_size) { /* disable ERBFI and ELSI interrupt */ - val = REG_READ(UART_IER) & ~0x5; - REG_WRITE(UART_IER, val); - if (dev->fifo_depth != 0) { /* restore threshold to user defined value */ - REG_WRITE(UART_FCR, - ((dev->fcr_mirror << 4) | 0x01)); - } - /* call user callback function, if any */ - if (dev->rx_cb != 0) { - dev->rx_cb(dev_id); - } - } - } - break; - } - case 0x0: // Modem control status - { - val = REG_READ(UART_MSR); - if ((val & 0x10) != 0) { - dev->nCTS_state = nCTS_LOW; - // If there is a data buffer, it is time to start sending - nCTS turns low - if (dev->tx_size > 0) { -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - /* enable ETBEI interrupt - starting TX */ - val = REG_READ(UART_IER) | 0x2; - REG_WRITE(UART_IER, val); -#ifdef __Xdmac - } else { - _dma_chan_enable((0x1 << dev->dmatxchanid), 1); // !!!!! - } -#endif - } - } else { - // nCTS was switched high back - dev->nCTS_state = nCTS_HIGH; - } - - break; - } - case 0x6: - { - val = REG_READ(UART_LSR); - if (val & (0x1 << 4)) { - /* line break detected; complete read immediately */ -#ifdef __Xdmac - if (dev->dmatxchanid == DMA_NONE) { -#endif - *(dev->p_rxsize) = dev->rx_count; - REG_READ(UART_RBR); -#ifdef __Xdmac - } else { - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - if (dev->dmarxchanid < DMAC_MEM_CHAN_CNT) { - _dma_chan_desc_get_ctrl(dev->dmarxchanid, - &val); - } else { - _dma_chan_desc_aux_get_ctrl(dev->dmarxchanid, - &val); - } - *(dev->p_rxsize) = - dev->rx_count - 1 - ((val >> 8) & 0x1fff); - *(dev->p_rxsize) -= 1; - } -#endif - /* disable (ERBFI and) ELSI interrupt */ - val = REG_READ(UART_IER) & ~0x5; - REG_WRITE(UART_IER, val); - if (dev->fifo_depth != 0) { /* restore threshold to user defined value */ - REG_WRITE(UART_FCR, - ((dev->fcr_mirror << 4) | 0x01)); - } - /* call user callback function, if any */ - if (dev->rx_cb != 0) { - dev->rx_cb(dev_id); - } - } - - break; - } - case 0x7: - { - val = REG_READ(UART_USR);// update IIR busy status by read Uart Status Register - break; - } - default: - { /* something wrong; at least, disable interrupts */ - REG_WRITE(UART_IER, 0x0); - if (dev->err_cb != 0) { - dev->err_cb(dev_id); - } - break; - } - } - intid = REG_READ(UART_IIR) & 0x0f; - } - -} - -static void uart_dmatx_isr_proc(uint32_t dev_id) -{ -#ifdef __Xdmac - uart_info_pt dev = uart_handles[dev_id]; - uint32_t cnt = 0; - volatile uint32_t val = 0; - - if (dev->tx_count == dev->tx_size) { - /* DMA TX xfer done */ - _dma_chan_enable((0x1 << dev->dmatxchanid), 0); - _dma_int_clear((0x1 << dev->dmatxchanid)); - - /* enable ETBEI interrupt, to detect FIFO empty for end of tx */ - val = REG_READ(UART_IER) | 0x2; - REG_WRITE(UART_IER, val); - } else { - /* clear DMA interrupt */ - _dma_int_clear((0x1 << dev->dmatxchanid)); - - if (dev->fifo_depth == 0) { /* fifos are not available */ - cnt = 1; - } else { - cnt = dev->fifo_depth - dev->tx_threshold; - } - create_dma_descriptor_tx(dev, cnt, dev->dmatxidx); - - dev->dmatxidx = 4 - dev->dmatxidx; - } -#endif -} - -static void uart_dmarx_isr_proc(uint32_t dev_id) -{ -#ifdef __Xdmac - uart_info_pt dev = uart_handles[dev_id]; - uint32_t val = 0; - - if (dev->rx_count == dev->rx_size) { - /* Buffer transfer completed. Assert RTS line back if flow control is enabled */ - if (dev->flow_control == FLOW_CONTROL_ON) { - val = REG_READ(UART_MCR) & ~0x2; - REG_WRITE(UART_MCR, val); - } - /* DMA RX xfer done */ - _dma_chan_enable((0x1 << dev->dmarxchanid), 0); - _dma_int_clear((0x1 << dev->dmarxchanid)); - - /* call user callback function, if any */ - if (dev->rx_cb != NULL) { - dev->rx_cb(dev_id); - } - } else { - /* clear DMA interrupt */ - _dma_int_clear((0x1 << dev->dmarxchanid)); - - if (dev->fifo_depth == 0) { /* fifos are not available */ - val = 1; - } else { - val = dev->rx_threshold; - } - create_dma_descriptor_rx(dev, val, dev->dmarxidx); - - dev->dmarxidx = 4 - dev->dmarxidx; - } -#endif -} - -#ifdef __Xdmac -#define UART_DMA_RX_END_CTRL (0xa0000015) /* am=b10, i=b1, dw/inc=b000, dtt=b10, r=b1, op=b01 */ -#define UART_DMA_RX_CTRL (0x801fff17) /* am=b10, i=b0, size=h1fff, dw/inc=b000, dtt=b10, r=b1, op=b11 */ -#define UART_DMA_RX_INT_CTRL (0xa01fff17) /* am=b10, i=b1, size=h1fff, dw/inc=b000, dtt=b10, r=b1, op=b11 */ -#define UART_DMA_TX_END_CTRL (0x6000000d) /* am=b01, i=b1, dw/inc=b000, dtt=b01, r=b1, op=b01 */ -#define UART_DMA_TX_CTRL (0x401fff0f) /* am=b01, i=b0, size=h1fff, dw/inc=b000, dtt=b01, r=b1, op=b11 */ -#define UART_DMA_TX_INT_CTRL (0x601fff0f) /* am=b01, i=b1, size=h1fff, dw/inc=b000, dtt=b01, r=b1, op=b11 */ -#define UART_DMA_CTRL_SIZE_POS (8) -#define UART_DMA_CTRL_XFER_POS (21) - -/* use maximum block size of 4kB per DMA transfer */ - -static void create_dma_descriptor_rx(uart_info_pt dev, uint32_t burst, - uint8_t idx) -{ - dev->dmarxdescriptor[idx + 0] = (burst << UART_DMA_CTRL_XFER_POS); - if ((dev->rx_size - dev->rx_count) <= 8 * 1024) { - dev->dmarxdescriptor[idx + 0] |= - UART_DMA_RX_END_CTRL | (((dev->rx_size - dev->rx_count) - 1) << - UART_DMA_CTRL_SIZE_POS); - dev->rx_count = dev->rx_size; - } else { - dev->dmarxdescriptor[idx + 0] |= - ((dev->rx_size - dev->rx_count) <= - 2 * 8 * 1024 ? UART_DMA_RX_CTRL : UART_DMA_RX_INT_CTRL); - dev->rx_count += 8 * 1024; - } - dev->dmarxdescriptor[idx + 2] = - (uint32_t) dev->rx_data + (dev->rx_count - 1); -} - -static void create_dma_descriptor_tx(uart_info_pt dev, uint32_t burst, - uint8_t idx) -{ - dev->dmatxdescriptor[idx + 0] = (burst << UART_DMA_CTRL_XFER_POS); - if ((dev->tx_size - dev->tx_count) <= 8 * 1024) { - dev->dmatxdescriptor[idx + 0] |= - UART_DMA_TX_END_CTRL | (((dev->tx_size - dev->tx_count) - 1) << - UART_DMA_CTRL_SIZE_POS); - dev->tx_count = dev->tx_size; - } else { - dev->dmatxdescriptor[idx + 0] |= - ((dev->tx_size - dev->tx_count) <= - 2 * 8 * 1024 ? UART_DMA_TX_CTRL : UART_DMA_TX_INT_CTRL); - dev->tx_count += 8 * 1024; - } - dev->dmatxdescriptor[idx + 1] = - (uint32_t) dev->tx_data + (dev->tx_count - 1); -} -#endif - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.c deleted file mode 100644 index b41cb7ac..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.c +++ /dev/null @@ -1,119 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -// ADC088S022 is ADC on EMSDP board -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "board.h" - -// #define DBG_MORE -#include "embARC_debug.h" - -#include "adc088s022.h" - -#define ADC_CHECK_EXP_NORTN(EXPR) CHECK_EXP_NOERCD(EXPR, error_exit) - -/** - * @brief Initialize adc088s022 - * @param[in] obj adc088s022 object - * @retval E_OK Initialize adc088s022 successfully - * @retval !E_OK Initialize adc088s022 failed - */ -int32_t adc088s022_adc_init(ADC088S022_DEF_PTR obj) -{ - int32_t ercd = E_OK; - DEV_SPI_PTR spi_obj = spi_get_dev(obj->dev_id); - - dbg_printf(DBG_MORE_INFO, "[%s]%d: spi_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, spi_obj, *spi_obj); - ADC_CHECK_EXP_NORTN(spi_obj != NULL); - - ercd = spi_obj->spi_open(DEV_MASTER_MODE, BOARD_ADC_SPI_HZ); - if ((ercd == E_OPNED) || (ercd == E_OK)) { - ercd = spi_obj->spi_control(SPI_CMD_SET_CLK_MODE, CONV2VOID(SPI_CLK_MODE_0)); - } - -error_exit: - return ercd; -} - -/** - * @brief Deinitialize adc088s022 - * @param[in] obj adc088s022 object - * @retval E_OK Deinitialize adc088s022 successfully - * @retval !E_OK Deinitialize adc088s022 failed - */ -int32_t adc088s022_adc_deinit(ADC088S022_DEF_PTR obj) -{ - int32_t ercd = E_OK; - DEV_SPI_PTR spi_obj = spi_get_dev(obj->dev_id); - - ercd = spi_obj->spi_close(); - return ercd; -} - -/** - * @brief Read adc088s022 channel - * @param[in] obj adc088s022 object - * @param[out] val Pointer to the return value (Unit is mV) - * @param[in] channel ADC channel - * @retval E_OK Read adc088s022 channel successfully - * @retval !E_OK Read adc088s022 channel failed - */ -int32_t adc088s022_adc_read(ADC088S022_DEF_PTR obj, float *val, int8_t channel) -{ - int32_t ercd = E_OK; - DEV_SPI_PTR spi_obj = spi_get_dev(obj->dev_id); - - dbg_printf(DBG_MORE_INFO, "[%s]%d: spi_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, spi_obj, *spi_obj); - ADC_CHECK_EXP_NORTN(spi_obj != NULL); - - uint8_t adc_value = 0; - uint8_t spi_buffer_rx[2]; - uint8_t spi_buffer_tx[2]; - DEV_SPI_TRANSFER spi_xfer; - /* Master and Slave transmit */ - DEV_SPI_XFER_SET_TXBUF(&spi_xfer, spi_buffer_tx, 0, 2); - DEV_SPI_XFER_SET_RXBUF(&spi_xfer, spi_buffer_rx, 0, 2); - DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL); - - spi_buffer_tx[1] = ((channel & 0x07) << 3); // Select channel - ercd = spi_obj->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(0)); - ercd = spi_obj->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&spi_xfer)); - // Read it again to have valid number (otherwise you might get value from previous channel) - ercd = spi_obj->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&spi_xfer)); - ercd = spi_obj->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(0)); - - adc_value = (spi_buffer_rx[1] << 4) | (spi_buffer_rx[0] >> 4); - dbg_printf(DBG_MORE_INFO, "ADC-Channel(%d) = %d (0x%x)\r\n", channel, adc_value, adc_value); - *val = adc_value * ADC_REF_VDD / 256.0; // adc088s022 is an 8-bit ADC - -error_exit: - return ercd; -} diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.h deleted file mode 100644 index fe020abc..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.h +++ /dev/null @@ -1,68 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_ADC088S022 -#define H_ADC088S022 -// ADC088S022 (a low-power, eight-channel. 23• Eight Input Channels. CMOS 8-bit analog-to-digital converter) is on EMSDP board - -#define ADC_REF_VDD 3300 /*< power supply voltage is 3300mV, used as V_ref*/ -#define ADC_FCLK_MIN 800000 // 0.8MHz -#define ADC_FLCK_MAX 3200000 // 3.2MHz - -#define EMSDP_ADC_SPI_ID DFSS_SPI_2_ID -#define BOARD_ADC_SPI_HZ 1000000 // 1.0MHz -#if BOARD_ADC_SPI_HZ < ADC_FCLK_MIN || BOARD_ADC_SPI_HZ > ADC_FLCK_MAX -#error "BOARD_ADC_SPI_HZ should be within range of [ADC_FCLK_MIN, ADC_FLCK_MAX]" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** ADC088S022 object type */ -typedef struct { - uint32_t dev_id; -} ADC088S022_DEF, *ADC088S022_DEF_PTR; - -#define ADC088S022_DEFINE(NAME, DEVICE_ID) \ - ADC088S022_DEF __ ## NAME = { \ - .dev_id = DEVICE_ID, \ - }; \ - ADC088S022_DEF_PTR NAME = &__ ## NAME - -extern int32_t adc088s022_adc_init(ADC088S022_DEF_PTR obj); -extern int32_t adc088s022_adc_deinit(ADC088S022_DEF_PTR obj); -extern int32_t adc088s022_adc_read(ADC088S022_DEF_PTR obj, float *val, int8_t channel); - -#ifdef __cplusplus -} -#endif - -#endif /* H_ADC088S022 */ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.mk b/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.mk deleted file mode 100644 index aa8b7a4f..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/adc/adc088s022/adc088s022.mk +++ /dev/null @@ -1,2 +0,0 @@ -DEV_CSRCDIR += $(EMBARC_ROOT)/device/peripheral/adc/adc088s022 -DEV_INCDIR += $(EMBARC_ROOT)/device/peripheral/adc/adc088s022 \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.c deleted file mode 100644 index ad47e098..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.c +++ /dev/null @@ -1,728 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "embARC.h" -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "board.h" -#include "max9880a.h" - -#define DBG_LESS -#include "embARC_debug.h" - -#define MAX9880A_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -// Register names -typedef enum { - MAX9880A_STATUS = 0x00, // RO 0x00 - MAX9880A_JACKSTATUS, // RO 0x01 - MAX9880A_AUXHIGH, // RO 0x02 - MAX9880A_AUXLOW, // RO 0x03 - MAX9880A_INTERRUPT_ENABLE, // RW 0x04 - MAX9880A_SYSTEM_CLOCK, // RW 0x05 - // DAI1-Clock Control - MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, // RW 0x06 - MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, // RW 0x07 - // DAI1-Configuration - MAX9880A_DAI1_INTERFACE_MODE_A, // RW 0x08 - MAX9880A_DAI1_INTERFACE_MODE_B, // RW 0x09 - MAX9880A_DAI1_TIME_DIVISION_MUL, // RW 0x0A - // DAI2-Clock Control - MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, // RW 0x0B - MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, // RW 0x0C - // DAI2-Configuration - MAX9880A_DAI2_INTERFACE_MODE_A, // RW 0x0D - MAX9880A_DAI2_INTERFACE_MODE_B, // RW 0x0E - MAX9880A_DAI2_TIME_DIVISION_MUL, // RW 0x0F - // Digital Mixers - MAX9880A_DAC_LR_MIXER, // RW 0x10 - // Digital Filtering - MAX9880A_CODEC_FILTERS, // RW 0x11 - // SPDM Outputs - MAX9880A_SPDM_CONFIGURATIONS, // RW 0x12 - MAX9880A_SPDM_INPUT, // RW 0x13 - MAX9880A_REV_ID, // RO 0x14 - // LEVEL control - MAX9880A_SIDETONE, // RW 0x15 - MAX9880A_STEREO_DAC_LEVEL, // RW 0x16 - MAX9880A_VOICE_DAC_LEVEL, // RW 0x17 - MAX9880A_LEFT_ADC_LEVEL, // RW 0x18 - MAX9880A_RIGHT_ADC_LEVEL, // RW 0x19 - MAX9880A_LEFT_LINE_INPUT_LEVEL, // RW 0x1A - MAX9880A_RIGHT_LINE_INPUT_LEVEL, // RW 0x1B - MAX9880A_LEFT_VOLUME_CTRL, // RW 0x1C - MAX9880A_RIGHT_VOLUME_CTRL, // RW 0x1D - MAX9880A_LEFT_LINE_OUTPUT_LEVEL, // RW 0x1E - MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, // RW 0x1F - MAX9880A_LEFT_MIC_GAIN, // RW 0x20 - MAX9880A_RIGHT_MIC_GAIN, // RW 0x21 - // Configuration - MAX9880A_INPUT, // RW 0x22 - MAX9880A_MICROPHONE, // RW 0x23 - MAX9880A_MODE, // RW 0x24 - MAX9880A_JACK_DETECT, // RW 0x25 - // Power Management - MAX9880A_ENABLE, // RW 0x26 - MAX9880A_SYSTEM_SHUTDOWN, // RW 0x27 - MAX9880A_REVISION_ID = 0xFF, // RO 0xFF -} max9880a_reg_t; - -typedef struct max9880a_settings { - max9880a_reg_t reg; - uint8_t val; -} max9880a_settings_t; - -/******************************************************************************/ -/*********** MAX9880A Configs **************************************/ -/******************************************************************************/ - -/** - * MAX9880A_I2SIN_LINEOUT_13MHZ - * - * Playback: I2S In -> LineOut, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * - * Measured with scope: - * => I2S clk from FPGA-HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from FPGA-HSDK to MAX: 16 KHz. - * => I2S data from FPGA-HSDK to MAX: 16 bit - * - * => MCLK on MAX9880 board is not from FPGA-HSDK but a on board Chrystal of 13.00 MHz. - */ -const max9880a_settings_t settings_i2sin_lineout_13mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27, - { MAX9880A_SYSTEM_CLOCK, 0x10 }, // 0x05, MCLK between 10-20 Mhz (PCLK=MCLK) - - // For recording (S1 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0x9E }, // 0x06, PLL=enabled, Ni=0x1E3F, DAI1 for LineIn -> I2S out, See table 6 datasheet (LRCLK=16 KHz PCLK=13 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x3F }, // 0x07 - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x30 }, // 0x09, SEL1 = 0, Map S1 to DAI1 - // For playback (S2 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0x9E }, // 0x0B, PLL=enabled, Ni=0x1E3F, DAI2 for I2S in -> LineOut, See table 6 datasheet (LRCLK=16 KHz PCLK=13 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x3F }, // 0x0C - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x50 }, // 0x0E, SEL2 = 1, Map S2 to DAI2 - - { MAX9880A_DAC_LR_MIXER, 0x21 }, // 0x10, DAi2 left channel, DAi2 right channel (audio out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1E, unmuted, Gain 0dB - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1F, unmuted, Gain 0dB - - { MAX9880A_INPUT, 0x00 }, // 0x22, No input selected - { MAX9880A_ENABLE, 0x3C }, // 0x26, LineOut-Enable, LineIn-Disable, Left/Right DAC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x80 }, // 0x27, Power On, Mclk to clk prescaler, disable internal clk osc -}; - -#define SETTINGS_I2SIN_LINEOUT_13MHZ_LENGTH (sizeof(settings_i2sin_lineout_13mhz) / sizeof(settings_i2sin_lineout_13mhz[0])) - -/** - * MAX9880A_LINEIN_I2SOUT_13MHZ - * - * Recording: LineIn -> I2S out, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * - * Measured with scope: - * => I2S clk from HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from HSDK to MAX: 16 KHz. - * - * => MCLK on MAX9880 board is not from FPGA-HSDK but a on board Chrystal of 13.00 MHz. - */ -const max9880a_settings_t settings_linein_i2sout_13mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27 - { MAX9880A_SYSTEM_CLOCK, 0x10 }, // 0x05, MCLK between 10-20 Mhz (PCLK=MCLK) - - // For recording (S1 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0x9E }, // 0x06, PLL=enabled, Ni=0x1E3F, DAI1 for LineIn -> I2S out, See table 6 datasheet (LRCLK=16 KHz PCLK=13 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x3F }, // 0x07 - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x30 }, // 0x09, SEL1 = 0, Map S1 to DAI1 - // For playback (S2 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0x9E }, // 0x0B, PLL=enabled, Ni=0x1E3F, DAI2 for I2S in -> LineOut, See table 6 datasheet (LRCLK=16 KHz PCLK=13 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x3F }, // 0x0C - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x50 }, // 0x0E, SEL2 = 1, Map S2 to DAI2 - - { MAX9880A_DAC_LR_MIXER, 0x21 }, // 0x10, DAi2 left channel, DAi2 right channel (audio out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, Select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1E, muted - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1F, muted - - { MAX9880A_INPUT, 0xA0 }, // 0x22, Left & Right Line input - { MAX9880A_ENABLE, 0xC3 }, // 0x26, LineIn-Enable, LineOut-Disable, Left/Right ADC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x80 }, // 0x27, Power On, Mclk to clk prescaler, disable internal clk osc -}; - -#define SETTINGS_LINEIN_I2SOUT_13MHZ_LENGTH (sizeof(settings_linein_i2sout_13mhz) / sizeof(settings_linein_i2sout_13mhz[0])) - -/** - * MAX9880A_I2SIN_LINEOUT_12DOT288MHZ - * - * Playback: I2S In -> LineOut, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * - * Measured with scope: - * => I2S clk from FPGA-HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from FPGA-HSDK to MAX: 16 KHz. - * => I2S data from FPGA-HSDK to MAX: 16 bit - * - * => MCLK disconnected, route 12.288 XTAL to clk-prescaler (JU12 on max9880a board) - * - * Difference with 13 Mhz settings above is "*" regs - */ -const max9880a_settings_t settings_i2sin_lineout_12_288mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27, - { MAX9880A_SYSTEM_CLOCK, 0x10 }, // 0x05, MCLK between 10-20 Mhz (PCLK=MCLK) - - // For recording (S1 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x06*, PLL=enabled, Ni=0x2000, DAI1 for LineIn -> I2S out, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x07* - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x30 }, // 0x09, SEL1 = 0, Map S1 to DAI1 - // For playback (S2 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x0B*, PLL=enabled, Ni=0x2000, DAI2 for I2S in -> LineOut, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x0C* - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x50 }, // 0x0E, SEL2 = 1, Map S2 to DAI2 - - { MAX9880A_DAC_LR_MIXER, 0x21 }, // 0x10, DAi2 left channel, DAi2 right channel (audio out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1E, unmuted, Gain 0dB - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1F, unmuted, Gain 0dB - - { MAX9880A_INPUT, 0x00 }, // 0x22, No input selected - { MAX9880A_ENABLE, 0x3C }, // 0x26, LineOut-Enable, LineIn-Disable, Left/Right DAC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x88 }, // 0x27*, Power On, Xtal to clk-prescaler -}; - -#define SETTINGS_I2SIN_LINEOUT_12_288MHZ_LENGTH (sizeof(settings_i2sin_lineout_12_288mhz) / sizeof(settings_i2sin_lineout_12_288mhz[0])) - -/** - * MAX9880A_LINEIN_I2SOUT_12DOT288MHZ - * - * Recording: LineIn -> I2S out, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * - * Measured with scope: - * => I2S clk from FPGA-HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from FPGA-HSDK to MAX: 16 KHz. - * - * => MCLK disconnected, route 12.288 XTAL to clk-prescaler - * - * Difference with 13 Mhz settings above is "*" regs - */ -const max9880a_settings_t settings_linein_i2sout_12_288mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27 - { MAX9880A_SYSTEM_CLOCK, 0x10 }, // 0x05, MCLK between 10-20 Mhz (PCLK=MCLK) - - // For recording (S1 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x06*, PLL=enabled, Ni=0x2000, DAI1 for LineIn -> I2S out, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x07* - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x30 }, // 0x09, SEL1 = 0, Map S1 to DAI1 - // For playback (S2 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x0B*, PLL=enabled, Ni=0x2000, DAI2 for I2S in -> LineOut, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x0C* - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x50 }, // 0x0E, SEL2 = 1, Map S2 to DAI2 - - { MAX9880A_DAC_LR_MIXER, 0x21 }, // 0x10, DAi2 left channel, DAi2 right channel (audio out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, Select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1E, muted - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1F, muted - - { MAX9880A_INPUT, 0xA0 }, // 0x22, Left & Right Line input - { MAX9880A_ENABLE, 0xC3 }, // 0x26, LineIn-Enable, LineOut-Disable, Left/Right ADC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x88 }, // 0x27*, Power On, Xtal to clk-prescaler -}; - -#define SETTINGS_LINEIN_I2SOUT_12_288MHZ_LENGTH (sizeof(settings_linein_i2sout_12_288mhz) / sizeof(settings_linein_i2sout_12_288mhz[0])) - -/** - * MAX9880A_I2SIN_LINEOUT_24DOT567MHZ - * - * Playback: I2S In -> LineOut, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * - * Measured with scope: - * => I2S clk from FPGA-HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from FPGA-HSDK to MAX: 16 KHz. - * => I2S data from FPGA-HSDK to MAX: 16 bit - * - * => MCLK from FPGA-HSDK of 24.567 MHz - * - * Difference with 13 Mhz settings above is "*" regs - */ -const max9880a_settings_t settings_i2sin_lineout_24_567mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27, - { MAX9880A_SYSTEM_CLOCK, 0x20 }, // 0x05*, MCLK between 20-40 Mhz (PCLK=MCLK/2) - - // For recording (S1 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x06*, PLL=enabled, Ni=0x2000, DAI1 for LineIn -> I2S out, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x07* - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x30 }, // 0x09, SEL1 = 0, Map S1 to DAI1 - // For playback (S2 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x0B*, PLL=enabled, Ni=0x2000, DAI2 for I2S in -> LineOut, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x0C* - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x50 }, // 0x0E, SEL2 = 1, Map S2 to DAI2 - - { MAX9880A_DAC_LR_MIXER, 0x21 }, // 0x10, DAi2 left channel, DAi2 right channel (audio out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1E, unmuted, Gain 0dB - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1F, unmuted, Gain 0dB - - { MAX9880A_INPUT, 0x00 }, // 0x22, No input selected - { MAX9880A_ENABLE, 0x3C }, // 0x26, LineOut-Enable, LineIn-Disable, Left/Right DAC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x80 }, // 0x27, Power On, Mclk to clk-prescaler -}; - -#define SETTINGS_I2SIN_LINEOUT_24_567MHZ_LENGTH (sizeof(settings_i2sin_lineout_24_567mhz) / sizeof(settings_i2sin_lineout_24_567mhz[0])) - -/** - * MAX9880A_LINEIN_I2SOUT_24DOT567MHZ - * - * Recording: LineIn -> I2S out, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * - * Measured with scope: - * => I2S clk from FPGA-HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from FPGA-HSDK to MAX: 16 KHz. - * - * => MCLK from HSDK of 24.567 MHz - * - * Difference with 13 Mhz settings above is "*" regs - */ -const max9880a_settings_t settings_linein_i2sout_24_567mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27 - { MAX9880A_SYSTEM_CLOCK, 0x20 }, // 0x05*, MCLK between 20-40 Mhz (PCLK=MCLK/2) - - // For recording (S1 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x06*, PLL=enabled, Ni=0x2000, DAI1 for LineIn -> I2S out, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x07* - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x30 }, // 0x09, SEL1 = 0, Map S1 to DAI1 - // For playback (S2 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x0B*, PLL=enabled, Ni=0x2000, DAI2 for I2S in -> LineOut, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x0C* - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x50 }, // 0x0E, SEL2 = 1, Map S2 to DAI2 - - { MAX9880A_DAC_LR_MIXER, 0x21 }, // 0x10, DAi2 left channel, DAi2 right channel (audio out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, Select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1E, muted - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1F, muted - - { MAX9880A_INPUT, 0xA0 }, // 0x22, Left & Right Line input - { MAX9880A_ENABLE, 0xC3 }, // 0x26, LineIn-Enable, LineOut-Disable, Left/Right ADC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x80 }, // 0x27, Power On, Mclk to clk-prescaler -}; - -#define SETTINGS_LINEIN_I2SOUT_24_567MHZ_LENGTH (sizeof(settings_linein_i2sout_24_567mhz) / sizeof(settings_linein_i2sout_24_567mhz[0])) - -/** - * MAX9880A_DAI2_I2SIN_LINEOUT_24DOT567MHZ - * - * Playback: I2S In -> LineOut, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * But now we have PLAYBACK on DAI2 (input I2S on S1 BCLKS1, LRCLKS1, SDINS1 from I2S-TX) - * - * Measured with scope: - * => I2S clk from IC-HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from IC-HSDK to MAX: 16 KHz. - * => I2S data from IC-HSDK to MAX: 16 bit - * - * => MCLK from HSDK of 24.567 MHz - * - */ -const max9880a_settings_t settings_dai2_i2sin_lineout_24_567mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27, - { MAX9880A_SYSTEM_CLOCK, 0x20 }, // 0x05, MCLK between 20-40 Mhz (PCLK=MCLK/2) - - // For recording (S2 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x06, PLL=enabled, Ni=0x2000, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x07 - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x50 }, // 0x09, SEL1 = 1, Map S1 to DAI2, SDIEN1=1, SDOEN1=0 - // For playback (S1 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x0B, PLL=enabled, Ni=0x2000, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x0C - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x30 }, // 0x0E, SEL2 = 0, Map S2 to DAI1, SDIEN2=1, SDOEN2=1 - - { MAX9880A_DAC_LR_MIXER, 0x21 }, // 0x10, DAi2 left channel, DAi2 right channel (i2s in) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1E, unmuted, Gain 0dB - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1F, unmuted, Gain 0dB - - { MAX9880A_INPUT, 0x00 }, // 0x22, No input selected - { MAX9880A_ENABLE, 0x3C }, // 0x26, LineOut-Enable, LineIn-Disable, Left/Right DAC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x80 }, // 0x27, Power On, Mclk to clk-prescaler -}; - -#define SETTINGS_DAI2_I2SIN_LINEOUT_24_567MHZ_LENGTH (sizeof(settings_dai2_i2sin_lineout_24_567mhz) / sizeof(settings_dai2_i2sin_lineout_24_567mhz[0])) - -/** - * MAX9880A_LINEIN_DAI1_I2SOUT_24DOT567MHZ - * - * Recording: LineIn -> I2S out, Stereo 16Bit I2S, Fs=16 Khz (LRclk=32Khz) - * But now we have RECORDING on DAI1 (output I2S on S2 BCLKS2, LRCLKS2, SDOUTS2 to I2S-RX) - * - * Measured with scope: - * => I2S clk from IC-HSDK to MAX: 512 KHz, divider is 48. (24.567 / 48 = 512 KHz). - * => I2S ws from IC-HSDK to MAX: 16 KHz. - * - * => MCLK from IC-HSDK of 24.567 MHz - */ -const max9880a_settings_t settings_linein_dai1_i2sout_24_567mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27 - { MAX9880A_SYSTEM_CLOCK, 0x20 }, // 0x05, MCLK between 20-40 Mhz (PCLK=MCLK/2) - - // For recording (S2 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x06, PLL=enabled, Ni=0x2000, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x07 - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x50 }, // 0x09, SEL1 = 1, Map S1 to DAI2, SDIEN1=1, SDOEN1=0 - // For playback (S1 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x0B, PLL=enabled, Ni=0x2000, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x0C - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x30 }, // 0x0E, SEL2 = 0, Map S2 to DAI1, SDIEN2=1, SDOEN2=1 - - { MAX9880A_DAC_LR_MIXER, 0x84 }, // 0x10, DAi1 left channel, DAi1 right channel (i2s out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, Select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1E, muted - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x40 }, // 0x1F, muted - - { MAX9880A_INPUT, 0xA0 }, // 0x22, Left & Right Line input - { MAX9880A_ENABLE, 0xC3 }, // 0x26, LineIn-Enable, LineOut-Disable, Left/Right ADC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x80 }, // 0x27, Power On, Mclk to clk-prescaler -}; - -#define SETTINGS_LINEIN_DAI1_I2SOUT_24_567MHZ_LENGTH (sizeof(settings_linein_dai1_i2sout_24_567mhz) / sizeof(settings_linein_dai1_i2sout_24_567mhz[0])) - -/** - * MAX9880A_24DOT567MHZ - * - * Playback & Recording (both tables mixed) - */ -const max9880a_settings_t settings_24_567mhz[] = -{ - { MAX9880A_SYSTEM_SHUTDOWN, 0x04 }, // 0x27, - { MAX9880A_SYSTEM_CLOCK, 0x20 }, // 0x05, MCLK between 20-40 Mhz (PCLK=MCLK/2) - - // For recording (S2 pins are mapped on DAI1) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x06, PLL=enabled, Ni=0x2000, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x07 - { MAX9880A_DAI1_INTERFACE_MODE_A, 0x10 }, // 0x08, Slave mode, Delay Mode - { MAX9880A_DAI1_INTERFACE_MODE_B, 0x50 }, // 0x09, SEL1 = 1, Map S1 to DAI2, SDIEN1=1, SDOEN1=0 - // For playback (S1 pins are mapped on DAI2) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH, 0xA0 }, // 0x0B, PLL=enabled, Ni=0x2000, See table 6 datasheet (LRCLK=16 KHz PCLK=12.288 MHz) - { MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW, 0x00 }, // 0x0C - { MAX9880A_DAI2_INTERFACE_MODE_A, 0x10 }, // 0x0D, Slave mode, Delay Mode, 16BitI2S - { MAX9880A_DAI2_INTERFACE_MODE_B, 0x30 }, // 0x0E, SEL2 = 0, Map S2 to DAI1, SDIEN2=1, SDOEN2=1 - - { MAX9880A_DAC_LR_MIXER, 0xA5 }, // 0x10, DAi2 left channel, DAi2 right channel (i2s in/out) - { MAX9880A_CODEC_FILTERS, 0x80 }, // 0x11, select music filters - - { MAX9880A_LEFT_ADC_LEVEL, 0x0D }, // 0x18, Gain 0dB, Gain -10dB - { MAX9880A_RIGHT_ADC_LEVEL, 0x0D }, // 0x19, Gain 0dB, Gain -10dB - { MAX9880A_LEFT_LINE_INPUT_LEVEL, 0x0C }, // 0x1A, Gain 0dB - { MAX9880A_RIGHT_LINE_INPUT_LEVEL, 0x0C }, // 0x1B, Gain 0dB - - { MAX9880A_LEFT_VOLUME_CTRL, 0x0C }, // 0x1C, Gain 0dB - { MAX9880A_RIGHT_VOLUME_CTRL, 0x0C }, // 0x1D, Gain 0dB - { MAX9880A_LEFT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1E, unmuted, Gain 0dB - { MAX9880A_RIGHT_LINE_OUTPUT_LEVEL, 0x00 }, // 0x1F, unmuted, Gain 0dB - - { MAX9880A_INPUT, 0xA0 }, // 0x22, Left & Right Line input - { MAX9880A_ENABLE, 0xFF }, // 0x26, LineOut-Enable, LineIn-Enable, Left/Right ADC/DAC enabled - { MAX9880A_SYSTEM_SHUTDOWN, 0x80 }, // 0x27, Power On, Mclk to clk-prescaler -}; - -#define SETTINGS_24_567MHZ_LENGTH (sizeof(settings_24_567mhz) / sizeof(settings_24_567mhz[0])) - -/******************************************************************************/ -/*********** END of MAX9880A Configs ********************************/ -/******************************************************************************/ - -// Max9880a register name list -typedef struct max9880a_reg_table { - char str[10]; - max9880a_reg_t reg; -} max9880a_reg_table_t; - -const max9880a_reg_table_t max9880a_reg_table[] = -{ - { "STS ", MAX9880A_STATUS }, - { "JACK STS ", MAX9880A_JACKSTATUS }, - { "AUX HIGH ", MAX9880A_AUXHIGH }, - { "AUX LOW ", MAX9880A_AUXLOW }, - { "INT ENA ", MAX9880A_INTERRUPT_ENABLE }, - { "SYS CLK ", MAX9880A_SYSTEM_CLOCK }, - // DAI1-Clock Control - { "DAI1 CLKH", MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_HIGH }, - { "DAI1 CLKL", MAX9880A_DAI1_STEREO_AUDIO_CLK_CTRL_LOW }, - // DAI1-Configuration - { "INTMODE A", MAX9880A_DAI1_INTERFACE_MODE_A }, - { "INTMODE B", MAX9880A_DAI1_INTERFACE_MODE_B }, - { "TIME DIV ", MAX9880A_DAI1_TIME_DIVISION_MUL }, - // DAI2-Clock Control - { "DAI2 CLKH", MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_HIGH }, - { "DAI2 CLKL", MAX9880A_DAI2_STEREO_AUDIO_CLK_CTRL_LOW }, - // DAI2-Configuration - { "INTMODE A", MAX9880A_DAI2_INTERFACE_MODE_A }, - { "INTMODE B", MAX9880A_DAI2_INTERFACE_MODE_B }, - { "TIME DIV ", MAX9880A_DAI2_TIME_DIVISION_MUL }, - // Digital Mixers - { "DAC-LRMIX", MAX9880A_DAC_LR_MIXER }, - // Digital Filtering - { "CODEC ", MAX9880A_CODEC_FILTERS }, - // SPDM Outputs - { "SPDM CONF", MAX9880A_SPDM_CONFIGURATIONS }, - { "SPDM INP ", MAX9880A_SPDM_INPUT }, - { "REV ID ", MAX9880A_REV_ID }, - // LEVEL control - { "SIDE TONE", MAX9880A_SIDETONE }, - { "STDAC LVL", MAX9880A_STEREO_DAC_LEVEL }, - { "V-DAC LVL", MAX9880A_VOICE_DAC_LEVEL }, - { "ADC LVL L", MAX9880A_LEFT_ADC_LEVEL }, - { "ADC LVL R", MAX9880A_RIGHT_ADC_LEVEL }, - { "LIINLVL L", MAX9880A_LEFT_LINE_INPUT_LEVEL }, - { "LIINLVL R", MAX9880A_RIGHT_LINE_INPUT_LEVEL }, - { "VOLCTRL L", MAX9880A_LEFT_VOLUME_CTRL }, - { "VOLCTRL R", MAX9880A_RIGHT_VOLUME_CTRL }, - { "LIOULVL L", MAX9880A_LEFT_LINE_OUTPUT_LEVEL }, - { "LIOULVL R", MAX9880A_RIGHT_LINE_OUTPUT_LEVEL }, - { "MICGAIN L", MAX9880A_LEFT_MIC_GAIN }, - { "MICGAIN R", MAX9880A_RIGHT_MIC_GAIN }, - // Configuration - { "INPUT ", MAX9880A_INPUT }, - { "MIC ", MAX9880A_MICROPHONE }, - { "MODE ", MAX9880A_MODE }, - { "JACK DET ", MAX9880A_JACK_DETECT }, - // Power Management - { "ENABLE ", MAX9880A_ENABLE }, - { "SHUTDOWN ", MAX9880A_SYSTEM_SHUTDOWN }, - { "REV ID ", MAX9880A_REVISION_ID }, -}; - -#define MAX9880A_REG_LENGTH (sizeof(max9880a_reg_table) / sizeof(max9880a_reg_table[0])) - -uint32_t max9880a_dump_reg(MAX9880A_DEF_PTR obj) -{ - int32_t ercd; - uint8_t buffer_rx[MAX9880A_REG_LENGTH - 1];// ignore last register (rev id) - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - MAX9880A_CHECK_EXP(iic_obj != NULL, E_OBJ); - - ercd = iic_obj->iic_read((void *)buffer_rx, MAX9880A_REG_LENGTH - 1); - for (int i = 0; i < MAX9880A_REG_LENGTH - 1; i++) { - dbg_printf(DBG_LESS_INFO, " %s (0x%x) = 0x%x\n\r", max9880a_reg_table[i].str, max9880a_reg_table[i].reg, buffer_rx[i]); - } - -error_exit: - return ercd; -} - -uint32_t max9880a_config(MAX9880A_DEF_PTR obj, max9880a_config_t config) -{ - int32_t ercd; - max9880a_settings_t *ptr; - uint32_t length; - uint8_t value[2]; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - MAX9880A_CHECK_EXP(iic_obj != NULL, E_OBJ); - - switch (config) { - case MAX9880A_I2SIN_LINEOUT_13MHZ: - ptr = (max9880a_settings_t *)settings_i2sin_lineout_13mhz; - length = SETTINGS_I2SIN_LINEOUT_13MHZ_LENGTH; - break; - break; - case MAX9880A_LINEIN_I2SOUT_13MHZ: - ptr = (max9880a_settings_t *)settings_linein_i2sout_13mhz; - length = SETTINGS_LINEIN_I2SOUT_13MHZ_LENGTH; - break; - break; - case MAX9880A_I2SIN_LINEOUT_12DOT288MHZ: - ptr = (max9880a_settings_t *)settings_i2sin_lineout_12_288mhz; - length = SETTINGS_I2SIN_LINEOUT_12_288MHZ_LENGTH; - break; - break; - case MAX9880A_LINEIN_I2SOUT_12DOT288MHZ: - ptr = (max9880a_settings_t *)settings_linein_i2sout_12_288mhz; - length = SETTINGS_LINEIN_I2SOUT_12_288MHZ_LENGTH; - break; - break; - case MAX9880A_I2SIN_LINEOUT_24DOT567MHZ: - ptr = (max9880a_settings_t *)settings_i2sin_lineout_24_567mhz; - length = SETTINGS_I2SIN_LINEOUT_24_567MHZ_LENGTH; - break; - break; - case MAX9880A_LINEIN_I2SOUT_24DOT567MHZ: - ptr = (max9880a_settings_t *)settings_linein_i2sout_24_567mhz; - length = SETTINGS_LINEIN_I2SOUT_24_567MHZ_LENGTH; - break; - break; - case MAX9880A_DAI2_I2SIN_LINEOUT_24DOT567MHZ: - ptr = (max9880a_settings_t *)settings_dai2_i2sin_lineout_24_567mhz; - length = SETTINGS_DAI2_I2SIN_LINEOUT_24_567MHZ_LENGTH; - break; - break; - case MAX9880A_LINEIN_DAI1_I2SOUT_24DOT567MHZ: - ptr = (max9880a_settings_t *)settings_linein_dai1_i2sout_24_567mhz; - length = SETTINGS_LINEIN_DAI1_I2SOUT_24_567MHZ_LENGTH; - break; - break; - case MAX9880A_24DOT567MHZ: - ptr = (max9880a_settings_t *)settings_24_567mhz; - length = SETTINGS_24_567MHZ_LENGTH; - break; - default: - ptr = NULL; - length = 0; - break; - } - - for (int i = 0; i < length; i++) { - value[0] = (uint8_t)(ptr[i].reg); - value[1] = (uint8_t)(ptr[i].val); - ercd = iic_obj->iic_write(value, 2); - dbg_printf(DBG_MORE_INFO, "[%d]iic_write 0x%x 0x%x ret %d\r\n", i, value[0], value[1], ercd); - MAX9880A_CHECK_EXP(ercd == 2, E_SYS); - } - ercd = E_OK; -error_exit: - return ercd; -} - -uint32_t max9880a_init(MAX9880A_DEF_PTR obj) -{ - int32_t ercd; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - MAX9880A_CHECK_EXP(iic_obj != NULL, E_OBJ); - ercd = iic_obj->iic_open(DEV_MASTER_MODE, IIC_SPEED_STANDARD); - dbg_printf(DBG_MORE_INFO, "[%s]iic_open ret %d\r\n", __FUNCTION__, ercd);// should return E_OK - MAX9880A_CHECK_EXP(ercd == E_OK, E_SYS); - ercd = iic_obj->iic_control(IIC_CMD_ENA_DEV, (void *)obj->slvaddr); - dbg_printf(DBG_MORE_INFO, "[%s]iic_control IIC_CMD_ENA_DEV ret %d\r\n", __FUNCTION__, ercd);// should return E_OK - MAX9880A_CHECK_EXP(ercd == E_OK, E_SYS); - ercd = iic_obj->iic_control(IIC_CMD_SET_ADDR_MODE, IIC_7BIT_ADDRESS); - dbg_printf(DBG_MORE_INFO, "[%s]iic_control IIC_CMD_SET_ADDR_MODE ret %d\r\n", __FUNCTION__, ercd);// should return E_OK - MAX9880A_CHECK_EXP(ercd == E_OK, E_SYS); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_TAR_ADDR, (void *)obj->slvaddr); - dbg_printf(DBG_MORE_INFO, "[%s]iic_control IIC_CMD_MST_SET_TAR_ADDR ret %d\r\n", __FUNCTION__, ercd);// should return E_OK - MAX9880A_CHECK_EXP(ercd == E_OK, E_SYS); - - // dbg_printf(DBG_LESS_INFO, "max9880a_init\n\r"); -error_exit: - return ercd; -} - -uint32_t max9880a_deinit(MAX9880A_DEF_PTR obj) -{ - int32_t ercd; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - MAX9880A_CHECK_EXP(iic_obj != NULL, E_OBJ); - ercd = iic_obj->iic_close(); - -error_exit: - return ercd; -} diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.h deleted file mode 100644 index 437681fc..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.h +++ /dev/null @@ -1,94 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_MAX9880A -#define H_MAX9880A -// MAX9800A (Low-Power, High-Performance, Dual I²S, Stereo Audio Codec) is on EMSDP board -#define I2C_DEVICE_ADDRESS_MAX9880A (0x10) - -typedef enum { - /** - * Use external MCLK of 13 MHz - * S1 pins are mapped on DAI1 - * S2 pins are mapped on DAI2 - */ - MAX9880A_I2SIN_LINEOUT_13MHZ = 0, // Playback - MAX9880A_LINEIN_I2SOUT_13MHZ, // Recording - - /** - * Use no external MCLK, but route Xtal to clk-prescaler - * S1 pins are mapped on DAI1 - * S2 pins are mapped on DAI2 - */ - MAX9880A_I2SIN_LINEOUT_12DOT288MHZ, // Playback - MAX9880A_LINEIN_I2SOUT_24DOT567MHZ, // Recording - - /** - * Use external MCLK of 24.567 MHz - * S1 pins are mapped on DAI1 - * S2 pins are mapped on DAI2 - */ - MAX9880A_I2SIN_LINEOUT_24DOT567MHZ, // Playback - MAX9880A_LINEIN_I2SOUT_24DOT567MHZ, // Recording - - /** - * !!!! Use these settings for HSDK-IC on BOARD !!!! - * - * Mapping is now different - * S1 pins are mapped on DAI2 - * S2 pins are mapped on DAI1 - * - * Use external MCLK of 24.567 MHz - * Use DAI2 (S1) for playback (I2S-TX), Use DAI1 (S2) for recording (I2S-RX) - */ - MAX9880A_DAI2_I2SIN_LINEOUT_24DOT567MHZ, // Playback - MAX9880A_LINEIN_DAI1_I2SOUT_24DOT567MHZ, // Recording - MAX9880A_24DOT567MHZ, // PlayBack and Recording (Regression) - -} max9880a_config_t; - -/* temperature sensor object type*/ -typedef struct { - uint32_t i2c_id; - uint32_t slvaddr; -} MAX9880A_DEF, *MAX9880A_DEF_PTR; - -#define MAX9880A_DEFINE(NAME, I2C_ID, SLAVE_ADDRESS) \ - MAX9880A_DEF __ ## NAME = { \ - .i2c_id = I2C_ID, \ - .slvaddr = SLAVE_ADDRESS, \ - }; \ - MAX9880A_DEF_PTR NAME = &__ ## NAME - -extern uint32_t max9880a_dump_reg(MAX9880A_DEF_PTR obj); -extern uint32_t max9880a_config(MAX9880A_DEF_PTR obj, max9880a_config_t config); -extern uint32_t max9880a_init(MAX9880A_DEF_PTR obj); -extern uint32_t max9880a_deinit(MAX9880A_DEF_PTR obj); - -#endif /* H_MAX9880A */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.mk b/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.mk deleted file mode 100644 index 58f816c9..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/audio/max9880a/max9880a.mk +++ /dev/null @@ -1,2 +0,0 @@ -DEV_CSRCDIR += $(EMBARC_ROOT)/device/peripheral/audio/max9880a -DEV_INCDIR += $(EMBARC_ROOT)/device/peripheral/audio/max9880a diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/fl256s.mk b/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/fl256s.mk deleted file mode 100644 index 22539880..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/fl256s.mk +++ /dev/null @@ -1,2 +0,0 @@ -DEV_CSRCDIR += $(EMBARC_ROOT)/device/peripheral/flash/fl256s -DEV_INCDIR += $(EMBARC_ROOT)/device/peripheral/flash/fl256s \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/spi_flash_fl256s.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/spi_flash_fl256s.c deleted file mode 100644 index b54859c3..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/spi_flash_fl256s.c +++ /dev/null @@ -1,507 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "embARC.h" -#include "spi_flash_fl256s.h" - -// #define DBG_MORE -#include "embARC_debug.h" - -#define RDID 0x9F /*!spi_master); - - // cpu_status = cpu_lock_save(); - - /* select device */ - spi_flash->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID((uint32_t)dev->cs)); - spi_flash->spi_control(SPI_CMD_MST_SET_FREQ, CONV2VOID(dev->spi_freq)); - spi_flash->spi_control(SPI_CMD_SET_CLK_MODE, CONV2VOID(SPI_CLK_MODE_0)); - ercd = spi_flash->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(xfer)); - /* deselect device */ - spi_flash->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID((uint32_t)dev->cs)); - - // cpu_unlock_restore(cpu_status); - return ercd; -} - -/** - * @fn int32_t _spi_send_cmd_quad(FL256S_DEF_PTR dev, DEV_SPI_PAK_PTR pak_ptr) - */ -Inline int32_t _spi_send_cmd_quad(FL256S_DEF_PTR dev, DEV_SPI_PAK_PTR pak_ptr) -{ - uint32_t cpu_status; - DEV_SPI_PTR spi_flash; - int32_t ercd = 0; - - spi_flash = spi_get_dev(dev->spi_master); - - // cpu_status = cpu_lock_save(); - - /* select device */ - spi_flash->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID((uint32_t)dev->cs)); - spi_flash->spi_control(SPI_CMD_MST_SET_FREQ, CONV2VOID(dev->spi_freq)); - spi_flash->spi_control(SPI_CMD_SET_CLK_MODE, CONV2VOID(SPI_CLK_MODE_0)); - - ercd = spi_flash->spi_control(SPI_CMD_QUAD_READ, CONV2VOID(pak_ptr)); - /* deselect device */ - spi_flash->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID((uint32_t)dev->cs)); - - // cpu_unlock_restore(cpu_status); - return ercd; -} - -uint32_t fl256s_read_reg(FL256S_DEF_PTR dev, uint8_t reg, uint8_t *data, uint32_t len) -{ - - DEV_SPI_TRANSFER cmd_xfer = { 0 }; - DEV_SPI_TRANSFER data_xfer = { 0 }; - - DEV_SPI_XFER_SET_TXBUF(&data_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_RXBUF(&data_xfer, data, 0, len); - DEV_SPI_XFER_SET_NEXT(&data_xfer, NULL); - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, ®, 0, 1); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, &data_xfer); - - if (_spi_send_cmd(dev, &cmd_xfer) == 0) { - return len; - } else { - return FL256S_NOT_VALID; - } -} - -uint32_t fl256s_write_reg(FL256S_DEF_PTR dev, uint8_t reg, uint8_t *data, uint32_t len) -{ - - DEV_SPI_TRANSFER cmd_xfer = { 0 }; - DEV_SPI_TRANSFER data_xfer = { 0 }; - - DEV_SPI_XFER_SET_TXBUF(&data_xfer, data, 0, len); - DEV_SPI_XFER_SET_RXBUF(&data_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&data_xfer, NULL); - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, ®, 0, 1); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, &data_xfer); - - if (_spi_send_cmd(dev, &cmd_xfer) == 0) { - return len; - } else { - return FL256S_NOT_VALID; - } -} - -int32_t fl256s_quad_enable(FL256S_DEF_PTR dev) -{ - uint32_t status = 0; - uint8_t w_data[2] = { 0 }; - uint8_t r_data = 0; - - status = fl256s_read_reg(dev, RDCR, &r_data, 1); - if (status == FL256S_NOT_VALID) { - return -1; - } - if (!(r_data & 0x02)) { - w_data[1] = r_data | 0x02; - status = fl256s_read_reg(dev, RDSR1, &r_data, 1); - if (status == FL256S_NOT_VALID) { - return -1; - } - w_data[0] = r_data; - if (fl256s_write_enable(dev) != 0) { - return -1; - } - status = fl256s_write_reg(dev, WRSR1, w_data, 2); - if (status == FL256S_NOT_VALID) { - return -1; - } - dev->quad_en = 1; - } else { - dev->quad_en = 1; - } - return 0; -} - -int32_t fl256s_quad_disable(FL256S_DEF_PTR dev) -{ - uint32_t status = 0; - uint8_t w_data[2] = { 0 }; - uint8_t r_data = 0; - - status = fl256s_read_reg(dev, RDCR, &r_data, 1); - if (status == FL256S_NOT_VALID) { - return -1; - } - if (r_data & 0x02) { - w_data[1] = r_data & 0xFD; - status = fl256s_read_reg(dev, RDSR1, &r_data, 1); - if (status == FL256S_NOT_VALID) { - return -1; - } - w_data[0] = r_data; - if (fl256s_write_enable(dev) != 0) { - return -1; - } - status = fl256s_write_reg(dev, WRSR1, w_data, 2); - if (status == FL256S_NOT_VALID) { - return -1; - } - dev->quad_en = 0; - } else { - dev->quad_en = 0; - } - return 0; -} - -uint32_t fl256s_read_id(FL256S_DEF_PTR dev) -{ - uint32_t id = 0; - uint8_t local_buf[5]; - DEV_SPI_TRANSFER cmd_xfer; - - local_buf[0] = RDID; - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 1); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, local_buf, 0, 5); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (_spi_send_cmd(dev, &cmd_xfer) == 0) { - id = (local_buf[1] << 24) | (local_buf[2] << 16) | (local_buf[3] << 8) | local_buf[4]; - } else { - id = FL256S_NOT_VALID; - } - dbg_printf(DBG_MORE_INFO, "fl256s_read_id buf: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\r\n", local_buf[0], local_buf[1], local_buf[2], local_buf[3], local_buf[4]); - - return id; -} - -int32_t fl256s_wait_ready(FL256S_DEF_PTR dev) -{ - uint32_t status = 0x01; - uint8_t r_data = 0; - - do { - status = fl256s_read_reg(dev, RDSR1, &r_data, 1); - if (status == FL256S_NOT_VALID) { - return -1; - } - } while (r_data & 0x01);// Status Register 1 Bit 0 - - return 0; -} - -int32_t fl256s_init(FL256S_DEF_PTR dev, uint32_t freq) -{ - DEV_SPI_PTR spi_flash; - int32_t ercd = 0; - - dev->spi_freq = freq; - spi_flash = spi_get_dev(dev->spi_master); - - ercd = spi_flash->spi_open(DEV_MASTER_MODE, freq); - - if (ercd != E_OK && ercd != E_OPNED) { - return ercd; - } - - // spi_flash->spi_control(SPI_CMD_SET_DUMMY_DATA, CONV2VOID(0xFF)); - ercd = fl256s_wait_ready(dev); - dbg_printf(DBG_MORE_INFO, "fl256s_wait_ready ret %d\r\n", ercd); - return E_OK; -} - -int32_t fl256s_write_enable(FL256S_DEF_PTR dev) -{ - uint32_t status = 0; - uint8_t w_data, r_data = 0; - - do { - status = fl256s_write_reg(dev, WREN, &w_data, 0); - if (status == FL256S_NOT_VALID) { - return -1; - } - - status = fl256s_read_reg(dev, RDSR1, &r_data, 1); - - if (status == FL256S_NOT_VALID) { - return -1; - } - // clear protection bits - // Write Protect. and Write Enable. - if ((r_data & 0xfc) && (r_data & 0x02)) { - w_data = 0; - - status = fl256s_write_reg(dev, WRSR1, &w_data, 1); - if (status == FL256S_NOT_VALID) { - return -1; - } - r_data = 0; - } - } while (r_data != 0x02); - - return 0; -} - -int32_t fl256s_write_disable(FL256S_DEF_PTR dev) -{ - uint32_t status = 0; - uint8_t w_data, r_data = 0; - - do { - status = fl256s_write_reg(dev, WRDI, &w_data, 0); - if (status == FL256S_NOT_VALID) { - return -1; - } - - status = fl256s_read_reg(dev, RDSR1, &r_data, 1); - if (status == FL256S_NOT_VALID) { - return -1; - } - - dbg_printf(DBG_MORE_INFO, "fl256s_write_disable status = 0x%x\r\n", r_data); - if (status == FL256S_NOT_VALID) { - return -1; - } - } while (r_data & 0x02);// Status Register 1 Bit 1 - - return 0; - -} - -int32_t fl256s_erase(FL256S_DEF_PTR dev, uint32_t address, uint32_t size) -{ - uint32_t last_address; - uint32_t count = 0; - uint8_t local_buf[4]; - DEV_SPI_TRANSFER cmd_xfer; - - // start address of last sector - last_address = (address + size) & (~(dev->sector_sz - 1)); - - // start address of first sector - address &= ~(dev->sector_sz - 1); - - do { - if (fl256s_write_enable(dev) != 0) { - return -1; - } - - if (fl256s_wait_ready(dev) != 0) { - return -1; - } - - local_buf[0] = SE; - local_buf[1] = (address >> 16) & 0xff; - local_buf[2] = (address >> 8) & 0xff; - local_buf[3] = address & 0xff; - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 4); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (_spi_send_cmd(dev, &cmd_xfer) != 0) { - return -1; - } - - address += dev->sector_sz; - count++; - } while (address <= last_address); - - if (fl256s_wait_ready(dev) != 0) { - return -1; - } - if (fl256s_write_disable(dev) != 0) { - return -1; - } - - return (int32_t)count; -} - -int32_t fl256s_write(FL256S_DEF_PTR dev, uint32_t address, uint32_t size, const void *data) -{ - - uint8_t local_buf[4]; - DEV_SPI_TRANSFER cmd_xfer; - DEV_SPI_TRANSFER data_xfer; - - uint32_t first = 0; - uint32_t size_orig = size; - - if (fl256s_wait_ready(dev) != 0) { - return -1; - } - - first = FLASH_PAGE_SIZE - (address & (FLASH_PAGE_SIZE - 1)); - - do { - // send write enable command to flash - if (fl256s_write_enable(dev) != 0) { - return -1; - } - if (fl256s_wait_ready(dev) != 0) { - return -1; - } - - first = first < size ? first : size; - - local_buf[0] = PP; - local_buf[1] = (address >> 16) & 0xff; - local_buf[2] = (address >> 8) & 0xff; - local_buf[3] = address & 0xff; - - DEV_SPI_XFER_SET_TXBUF(&data_xfer, data, 0, first); - DEV_SPI_XFER_SET_RXBUF(&data_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&data_xfer, NULL); - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 4); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, &data_xfer); - - if (_spi_send_cmd(dev, &cmd_xfer) != 0) { - return -1; - } - - size -= first; - address += first; - data += first; - first = FLASH_PAGE_SIZE; - - } while (size); - - if (fl256s_wait_ready(dev) != 0) { - return -1; - } - if (fl256s_write_disable(dev) != 0) { - return -1; - } - - return (int32_t)(size_orig); -} - -int32_t fl256s_read(FL256S_DEF_PTR dev, uint32_t address, uint32_t size, void *data) -{ - uint8_t local_buf[4]; - DEV_SPI_TRANSFER cmd_xfer; - DEV_SPI_TRANSFER data_xfer; - uint32_t first = 0; - uint32_t size_orig = size; - - first = FLASH_PAGE_SIZE - (address & (FLASH_PAGE_SIZE - 1)); - - do { - if (fl256s_wait_ready(dev) != 0) { - return -1; - } - - first = first < size ? first : size; - - local_buf[0] = READ; - local_buf[1] = (address >> 16) & 0xff; - local_buf[2] = (address >> 8) & 0xff; - local_buf[3] = address & 0xff; - - DEV_SPI_XFER_SET_TXBUF(&data_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_RXBUF(&data_xfer, data, 0, first); - DEV_SPI_XFER_SET_NEXT(&data_xfer, NULL); - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 4); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, &data_xfer); - - if (_spi_send_cmd(dev, &cmd_xfer) != 0) { - return -1; - } - size -= first; - address += first; - data += first; - first = FLASH_PAGE_SIZE; - - } while (size); - - return (int32_t)(size_orig); -} - -int32_t fl256s_quad_read(FL256S_DEF_PTR dev, uint32_t address, uint32_t size, void *data) -{ - DEV_SPI_PAK spi_pak; - uint32_t first = 0; - uint32_t size_orig = size; - - uint32_t per_read_size = 32; - - first = per_read_size - (address & (per_read_size - 1)); - - do { - if (fl256s_wait_ready(dev) != 0) { - return -1; - } - - first = first < size ? first : size; - - spi_pak.cmd = QORD; - spi_pak.addr32 = address; - spi_pak.data_len = first; - spi_pak.data_ptr = data; - - if (_spi_send_cmd_quad(dev, &spi_pak) != 0) { - return -1; - } - size -= first; - address += first; - data += first; - first = per_read_size; - - } while (size); - - return (int32_t)(size_orig); -} \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/spi_flash_fl256s.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/spi_flash_fl256s.h deleted file mode 100644 index ed3cfa7f..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/fl256s/spi_flash_fl256s.h +++ /dev/null @@ -1,93 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SPI_FLASH_FL256S -#define H_SPI_FLASH_FL256S - -// Manufacturer: 0x01, DeviceId: 0x0219, ID-CFI: 0x4D -#define FLASH_ID 0x0102194D -#define FLASH_SECTOR_SIZE 0x00001000 -#define FLASH_PAGE_SIZE 0x00000100 - -#include "embARC_toolchain.h" -#include "embARC_error.h" - -/** flash data type */ -typedef struct { - uint32_t head; /*!< 0x68656164 ='head' */ - uint32_t cpu_type; /*!< = 0 - all images, reserved for future */ - uint32_t start; /*!< start address of application image in spi flash */ - uint32_t size; /*!< size of image in bytes */ - uint32_t ramaddr; /*!< address of ram for loading image */ - uint32_t ramstart; /*!< start address of application in RAM !!!! */ - uint32_t checksum; /*!< checksum of all bytes in image */ -} image_t; - -/** fl256s object type */ -typedef struct { - uint8_t spi_master; - uint8_t cs; - uint8_t quad_en; - uint32_t spi_freq; - - uint32_t page_sz; - uint32_t sector_sz; -} FL256S_DEF, *FL256S_DEF_PTR; - -#define FL256S_DEF(name, spi_master_id, cs_line, page, sector) \ - FL256S_DEF __ ## name = { \ - .spi_master = spi_master_id, \ - .cs = cs_line, \ - .page_sz = page, \ - .sector_sz = sector \ - }; \ - FL256S_DEF_PTR name = &__ ## name \ - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t fl256s_read_status(FL256S_DEF_PTR dev); -extern uint32_t fl256s_read_id(FL256S_DEF_PTR dev); -extern int32_t fl256s_read(FL256S_DEF_PTR dev, uint32_t address, uint32_t size, void *data); -extern int32_t fl256s_quad_read(FL256S_DEF_PTR dev, uint32_t address, uint32_t size, void *data); -extern int32_t fl256s_write_enable(FL256S_DEF_PTR dev); -extern int32_t fl256s_write_disable(FL256S_DEF_PTR dev); -extern int32_t fl256s_erase(FL256S_DEF_PTR dev, uint32_t address, uint32_t size); -extern int32_t fl256s_write(FL256S_DEF_PTR dev, uint32_t address, uint32_t size, const void *data); -extern int32_t fl256s_wait_ready(FL256S_DEF_PTR dev); -extern int32_t fl256s_init(FL256S_DEF_PTR dev, uint32_t freq); -extern int32_t fl256s_quad_enable(FL256S_DEF_PTR dev); -extern int32_t fl256s_quad_disable(FL256S_DEF_PTR dev); - -#ifdef __cplusplus -} -#endif - -#endif /* H_SPI_FLASH_FL256S */ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/spi_flash_w25qxx.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/spi_flash_w25qxx.c deleted file mode 100644 index cc825415..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/spi_flash_w25qxx.c +++ /dev/null @@ -1,371 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "spi_flash_w25qxx.h" - -#include "embARC_error.h" -#include "board.h" -#include "device/ip_hal/dev_spi.h" -#include "arc/arc_exception.h" -#include "string.h" - -/** - * @name W25QXX SPI Flash Commands - * @{ - */ -#define RDID 0x9F /*!spi_master); - - /* select device */ - spi_flash->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID((uint32_t)dev->cs)); - spi_flash->spi_control(SPI_CMD_MST_SET_FREQ, CONV2VOID(dev->spi_freq)); - spi_flash->spi_control(SPI_CMD_SET_CLK_MODE, CONV2VOID(SPI_CLK_MODE_0)); - ercd = spi_flash->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(xfer)); - /* deselect device */ - spi_flash->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID((uint32_t)dev->cs)); - - return ercd; -} - -/** - * @brief Read the status of spi flash - * @return Current status of spi flash - */ -uint32_t w25qxx_read_status(W25QXX_DEF_PTR dev) -{ - - uint8_t local_buf[2]; - DEV_SPI_TRANSFER cmd_xfer; - - local_buf[0] = RDSR; - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 1); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, local_buf, 1, 1); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (spi_send_cmd(dev, &cmd_xfer) == 0) { - return (uint32_t)local_buf[0]; - } else { - return W25QXX_NOT_VALID; - } -} - -/** - * @brief Enable to write flash - * @retval 0 Enable operation successfully - * @retval -1 Enable operation failed - */ -int32_t w25qxx_write_enable(W25QXX_DEF_PTR dev) -{ - uint8_t local_buf[3]; - DEV_SPI_TRANSFER cmd_xfer; - - uint32_t status = 0; - - do { - local_buf[0] = WREN; - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 1); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (spi_send_cmd(dev, &cmd_xfer) != 0) { - return -1; - } - - status = w25qxx_read_status(dev); - - if (status == W25QXX_NOT_VALID) { - return -1; - } - // clear protection bits - // Write Protect. and Write Enable. - if ((status & 0xfc) && (status & 0x02)) { - local_buf[0] = WRSR; // write status - local_buf[1] = 0x00; // write status - local_buf[2] = 0x00; // write status - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 3); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (spi_send_cmd(dev, &cmd_xfer) != 0) { - return -1; - } - status = 0; - } - } while (status != 0x02); - - return 0; -} - -/** - * @brief Initialize spi flash interface - * @retval 0 Initialize successfully - * @retval -1 Initialize failed - */ -int32_t w25qxx_init(W25QXX_DEF_PTR dev, uint32_t freq) -{ - DEV_SPI_PTR spi_flash; - int32_t ercd = 0; - - dev->spi_freq = freq; - spi_flash = spi_get_dev(dev->spi_master); - - ercd = spi_flash->spi_open(DEV_MASTER_MODE, freq); - - if (ercd != E_OK && ercd != E_OPNED) { - return ercd; - } - - spi_flash->spi_control(SPI_CMD_SET_DUMMY_DATA, CONV2VOID(0xFF)); - - return E_OK; -} - -/** - * @brief Read spi flash identification ID - * @return The id of the spi flash - */ -uint32_t w25qxx_read_id(W25QXX_DEF_PTR dev) -{ - uint32_t id = 0; - uint8_t local_buf[4]; - DEV_SPI_TRANSFER cmd_xfer; - - local_buf[0] = RDID; - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 1); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, local_buf, 1, 3); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (spi_send_cmd(dev, &cmd_xfer) == 0) { - id = (local_buf[0] << 16) | (local_buf[1] << 8) | local_buf[2]; - } else { - id = W25QXX_NOT_VALID; - } - - return id; -} - -/** - * @brief Read status and wait while busy flag is set - * @retval 0 Success - * @retval -1 Fail - */ -int32_t w25qxx_wait_ready(W25QXX_DEF_PTR dev) -{ - uint32_t status = 0x01; - - do { - status = w25qxx_read_status(dev); - - if (status == W25QXX_NOT_VALID) { - return -1; - } - } while (status & 0x01); - - return 0; -} - -/** - * @brief Read data from flash - * @param[in] address Start address - * @param[in] size Data size - * @param[out] data Pointer to the return data - * - * @retval -1 Read failed - * @retval >= 0 Data size - */ -int32_t w25qxx_read(W25QXX_DEF_PTR dev, uint32_t address, uint32_t size, void *data) -{ - - uint8_t local_buf[4]; - DEV_SPI_TRANSFER cmd_xfer; - - local_buf[0] = READ; - local_buf[1] = (address >> 16) & 0xff; - local_buf[2] = (address >> 8) & 0xff; - local_buf[3] = address & 0xff; - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 4); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, data, 4, size); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (spi_send_cmd(dev, &cmd_xfer) == 0) { - return size; - } else { - return -1; - } -} - -/** - * @brief Flash erase in sectors - * - * @param[in] address Erase start address of spi flash - * @param[in] size Erase size - * - * @retval -1 Erase failed - * @retval >= 0 Sector count erased - */ -int32_t w25qxx_erase(W25QXX_DEF_PTR dev, uint32_t address, uint32_t size) -{ - uint32_t last_address; - uint32_t count = 0; - uint8_t local_buf[4]; - DEV_SPI_TRANSFER cmd_xfer; - - // start address of last sector - last_address = (address + size) & (~(dev->sector_sz - 1)); - - // start address of first sector - address &= ~(dev->sector_sz - 1); - - do { - if (w25qxx_write_enable(dev) != 0) { - return -1; - } - - if (w25qxx_wait_ready(dev) != 0) { - return -1; - } - - local_buf[0] = SE; - local_buf[1] = (address >> 16) & 0xff; - local_buf[2] = (address >> 8) & 0xff; - local_buf[3] = address & 0xff; - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, local_buf, 0, 4); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (spi_send_cmd(dev, &cmd_xfer) != 0) { - return -1; - } - - address += dev->sector_sz; - count++; - } while (address <= last_address); - - if (w25qxx_wait_ready(dev) != 0) { - return -1; - } - - return (int32_t)count; -} - -/** - * @brief Write data to spi flash - * - * @param[in] address Start address - * @param[in] size Data size - * @param[in] data Pointer to data - * - * @retval >= 0 Written bytes number - * @retval < 0 Write data failed - */ -int32_t w25qxx_write(W25QXX_DEF_PTR dev, uint32_t address, uint32_t size, const void *data) -{ - DEV_SPI_TRANSFER cmd_xfer; - - uint32_t first = 0; - uint32_t size_orig = size; - - if (w25qxx_wait_ready(dev) != 0) { - return -1; - } - - first = FLASH_PAGE_SIZE - (address & (FLASH_PAGE_SIZE - 1)); - - do { - // send write enable command to flash - if (w25qxx_write_enable(dev) != 0) { - return -1; - } - if (w25qxx_wait_ready(dev) != 0) { - return -1; - } - - first = first < size ? first : size; - - dev->write_buf[0] = PP; - dev->write_buf[1] = (address >> 16) & 0xff; - dev->write_buf[2] = (address >> 8) & 0xff; - dev->write_buf[3] = address & 0xff; - - memcpy(&(dev->write_buf[4]), data, first); - - // DEV_SPI_XFER_SET_TXBUF(&data_xfer, data, 0, first); - // DEV_SPI_XFER_SET_RXBUF(&data_xfer, NULL, 0, 0); - // DEV_SPI_XFER_SET_NEXT(&data_xfer, NULL); - - DEV_SPI_XFER_SET_TXBUF(&cmd_xfer, dev->write_buf, 0, 4 + first); - DEV_SPI_XFER_SET_RXBUF(&cmd_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(&cmd_xfer, NULL); - - if (spi_send_cmd(dev, &cmd_xfer) != 0) { - return -1; - } - - size -= first; - address += first; - data += first; - first = FLASH_PAGE_SIZE; - - } while (size); - - if (w25qxx_wait_ready(dev) != 0) { - return -1; - } - - return (int32_t)(size_orig); -} diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/spi_flash_w25qxx.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/spi_flash_w25qxx.h deleted file mode 100644 index 4e0821f7..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/spi_flash_w25qxx.h +++ /dev/null @@ -1,87 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SPI_FLASH_W25QXX -#define H_SPI_FLASH_W25QXX - -#define FLASH_PAGE_SIZE 0x100 -#define FLASH_SECTOR_SIZE 0x1000 - -#include "embARC_toolchain.h" -#include "embARC_error.h" - -/** flash data type */ -typedef struct { - uint32_t head; /*!< 0x68656164 ='head' */ - uint32_t cpu_type; /*!< = 0 - all images, reserved for future */ - uint32_t start; /*!< start address of application image in spi flash */ - uint32_t size; /*!< size of image in bytes */ - uint32_t ramaddr; /*!< address of ram for loading image */ - uint32_t ramstart; /*!< start address of application in RAM !!!! */ - uint32_t checksum; /*!< checksum of all bytes in image */ -} image_t; - -/** w25qxx object type */ -typedef struct { - uint8_t spi_master; - uint8_t cs; - uint32_t spi_freq; - - uint32_t page_sz; - uint32_t sector_sz; - uint8_t write_buf[4 + FLASH_PAGE_SIZE]; -} W25QXX_DEF, *W25QXX_DEF_PTR; - -#define W25QXX_DEF(name, spi_master_id, cs_line, page, sector) \ - W25QXX_DEF __ ## name = { \ - .spi_master = spi_master_id, \ - .cs = cs_line, \ - .page_sz = page, \ - .sector_sz = sector \ - }; \ - W25QXX_DEF_PTR name = &__ ## name \ - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t w25qxx_read_status(W25QXX_DEF_PTR dev); -extern uint32_t w25qxx_read_id(W25QXX_DEF_PTR dev); -extern int32_t w25qxx_read(W25QXX_DEF_PTR dev, uint32_t address, uint32_t size, void *data); -extern int32_t w25qxx_write_enable(W25QXX_DEF_PTR dev); -extern int32_t w25qxx_erase(W25QXX_DEF_PTR dev, uint32_t address, uint32_t size); -extern int32_t w25qxx_write(W25QXX_DEF_PTR dev, uint32_t address, uint32_t size, const void *data); -extern int32_t w25qxx_wait_ready(W25QXX_DEF_PTR dev); -extern int32_t w25qxx_init(W25QXX_DEF_PTR dev, uint32_t freq); - -#ifdef __cplusplus -} -#endif - -#endif /* H_SPI_FLASH_W25QXX */ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/w25qxx.mk b/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/w25qxx.mk deleted file mode 100644 index 7f947a51..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/flash/w25qxx/w25qxx.mk +++ /dev/null @@ -1,2 +0,0 @@ -DEV_CSRCDIR += $(EMBARC_ROOT)/device/peripheral/flash/w25qxx -DEV_INCDIR += $(EMBARC_ROOT)/device/peripheral/flash/w25qxx \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.c deleted file mode 100644 index fc665a0d..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.c +++ /dev/null @@ -1,138 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#include -#include "embARC_error.h" -#include "embARC_debug.h" -#include "board.h" -#include "cy8c95xx.h" - -#define CY8C95XX_CHECK_EXP_NORTN(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -int32_t cy8c95xx_reg_write(CY8C95XX_DEF_PTR obj, uint8_t dev, uint8_t regaddr, uint8_t *val, uint8_t len) -{ - int32_t ercd = E_OK; - uint8_t data[1]; - uint32_t slvaddr; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - dbg_printf(DBG_LESS_INFO, "[%s]%d: obj 0x%x, regaddr 0x%x, val 0x%x\r\n", __FUNCTION__, __LINE__, obj, regaddr, *val); - dbg_printf(DBG_MORE_INFO, "[%s]%d: iic_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, iic_obj, *iic_obj); - CY8C95XX_CHECK_EXP_NORTN(iic_obj != NULL, E_PAR); - CY8C95XX_CHECK_EXP_NORTN((dev == 0) || (dev == 1), E_PAR); - - if (dev == 0) { - slvaddr = obj->slvaddr_io; - } else { - slvaddr = obj->slvaddr_eep; - } - - data[0] = (uint8_t)(regaddr & 0xff); - /** make sure set the temp sensor's slave address */ - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_TAR_ADDR, CONV2VOID(slvaddr)); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_RESTART)); - ercd = iic_obj->iic_write(data, 1); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_STOP)); - ercd = iic_obj->iic_write(val, len); - -error_exit: - return ercd; -} - -int32_t cy8c95xx_reg_read(CY8C95XX_DEF_PTR obj, uint8_t dev, uint8_t regaddr, uint8_t *val, uint8_t len) -{ - int32_t ercd = E_OK; - uint8_t data[1]; - uint32_t slvaddr; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - dbg_printf(DBG_MORE_INFO, "[%s]%d: iic_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, iic_obj, *iic_obj); - CY8C95XX_CHECK_EXP_NORTN(iic_obj != NULL, E_PAR); - CY8C95XX_CHECK_EXP_NORTN((dev == 0) || (dev == 1), E_PAR); - - if (dev == 0) { - slvaddr = obj->slvaddr_io; - } else { - slvaddr = obj->slvaddr_eep; - } - - data[0] = (uint8_t)(regaddr & 0xff); - /** make sure set the temp sensor's slave address */ - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_TAR_ADDR, CONV2VOID(slvaddr)); - /** write register address then read register value */ - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_RESTART)); - ercd = iic_obj->iic_write(data, 1); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_STOP)); - ercd = iic_obj->iic_read(val, len); - -error_exit: - return ercd; -} - -int32_t cy8c95xx_readid(CY8C95XX_DEF_PTR obj, uint8_t *value) -{ - int32_t ercd = E_OK; - uint8_t buffer_rx[1]; - - CY8C95XX_CHECK_EXP_NORTN(value != NULL, E_PAR); - CY8C95XX_CHECK_EXP_NORTN(cy8c95xx_reg_read(obj, CY8C95XX_DEV_IO, CY8C95XX_DEVICE_ID_REG, buffer_rx, 1) == E_OK, E_SYS); - *value = buffer_rx[0]; - -error_exit: - return ercd; -} - -int32_t cy8c95xx_writeport(CY8C95XX_DEF_PTR obj, uint8_t port, uint8_t value) -{ - int32_t ercd = E_OK; - uint8_t buffer_tx[1]; - uint8_t val = 0; - - CY8C95XX_CHECK_EXP_NORTN(port < CY8C95XX_PORT_NONE, E_PAR); - // Set port [0..7] - buffer_tx[0] = value; - CY8C95XX_CHECK_EXP_NORTN(cy8c95xx_reg_write(obj, CY8C95XX_DEV_IO, CY8C95XX_OUTPUT_PORT0_REG + port, buffer_tx, 1) == E_OK, E_SYS); - CY8C95XX_CHECK_EXP_NORTN(cy8c95xx_reg_read(obj, CY8C95XX_DEV_IO, CY8C95XX_OUTPUT_PORT0_REG + port, &val, 1) == E_OK, E_SYS); - CY8C95XX_CHECK_EXP_NORTN(val == value, E_OBJ); - -error_exit: - return ercd; -} - -int32_t cy8c95xx_readport(CY8C95XX_DEF_PTR obj, uint8_t port, uint8_t *value) -{ - int32_t ercd = E_OK; - - CY8C95XX_CHECK_EXP_NORTN(port < CY8C95XX_PORT_NONE, E_PAR); - CY8C95XX_CHECK_EXP_NORTN(cy8c95xx_reg_read(obj, CY8C95XX_DEV_IO, CY8C95XX_INPUT_PORT0_REG + port, value, 1) == E_OK, E_SYS); - -error_exit: - return ercd; -} diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.h deleted file mode 100644 index 7582e2c0..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.h +++ /dev/null @@ -1,149 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_CY8C95XX -#define H_CY8C95XX - -#define CY8C95XX_I2C_TIMEOUT (5000000) - -// CY8C95xx Series Interface is a multi-port IO expander using I2C bus, on HSDK board -typedef enum { - CY8C95XX_DEV_IO = 0, - CY8C95XX_DEV_EEP -} CY8C95XX_DEV_T; - -typedef enum { - CY8C95XX_PORT_0 = 0, - CY8C95XX_PORT_1, - CY8C95XX_PORT_2, - CY8C95XX_PORT_NONE -} CY8C95XX_PORT_T; - -typedef enum { - CY8C95XX_PIN_0 = 0, - CY8C95XX_PIN_1, - CY8C95XX_PIN_2, - CY8C95XX_PIN_3, - CY8C95XX_PIN_4, - CY8C95XX_PIN_5, - CY8C95XX_PIN_6, - CY8C95XX_PIN_7, - CY8C95XX_PIN_NONE -} CY8C95XX_PIN_T; - -typedef enum { - CY8C95XX_PWM_0 = 0, - CY8C95XX_PWM_1, - CY8C95XX_PWM_2, - CY8C95XX_PWM_3, - CY8C95XX_PWM_NONE -} CY8C95XX_PWM_T; - -typedef enum { - CY8C95XX_PWMFREQ_100HZ = 0, - CY8C95XX_PWMFREQ_300HZ, - CY8C95XX_PWMFREQ_500HZ, - CY8C95XX_PWMFREQ_700HZ, - CY8C95XX_PWMFREQ_900HZ, - CY8C95XX_PWMFREQ_NONE -} CY8C95XX_PWMFREQ_T; - -typedef enum { - CY8C95XX_ENABLE_WDE = 0, - CY8C95XX_ENABLE_EEE, - CY8C95XX_ENABLE_EERO, - CY8C95XX_ENABLE_NONE -} CY8C95XX_ENABLE_T; - -typedef struct { - uint32_t i2c_id; - uint32_t slvaddr_io; - uint32_t slvaddr_eep; -} CY8C95XX_DEF, *CY8C95XX_DEF_PTR; - -#define CY8C95XX_INPUT_PORT0_REG 0x00 -#define CY8C95XX_INPUT_PORT1_REG 0x01 -#define CY8C95XX_INPUT_PORT2_REG 0x02 -#define CY8C95XX_INPUT_PORT3_REG 0x03 -#define CY8C95XX_INPUT_PORT4_REG 0x04 -#define CY8C95XX_INPUT_PORT5_REG 0x05 -#define CY8C95XX_INPUT_PORT6_REG 0x06 -#define CY8C95XX_INPUT_PORT7_REG 0x07 - -#define CY8C95XX_OUTPUT_PORT0_REG 0x08 -#define CY8C95XX_OUTPUT_PORT1_REG 0x09 -#define CY8C95XX_OUTPUT_PORT2_REG 0x0A -#define CY8C95XX_OUTPUT_PORT3_REG 0x0B -#define CY8C95XX_OUTPUT_PORT4_REG 0x0C -#define CY8C95XX_OUTPUT_PORT5_REG 0x0D -#define CY8C95XX_OUTPUT_PORT6_REG 0x0E -#define CY8C95XX_OUTPUT_PORT7_REG 0x0F - -#define CY8C95XX_INTSTS_PORT0_REG 0x10 -#define CY8C95XX_INTSTS_PORT1_REG 0x11 -#define CY8C95XX_INTSTS_PORT2_REG 0x12 -#define CY8C95XX_INTSTS_PORT3_REG 0x13 -#define CY8C95XX_INTSTS_PORT4_REG 0x14 -#define CY8C95XX_INTSTS_PORT5_REG 0x15 -#define CY8C95XX_INTSTS_PORT6_REG 0x16 -#define CY8C95XX_INTSTS_PORT7_REG 0x17 - -#define CY8C95XX_PORT_SELECT_REG 0x18 -#define CY8C95XX_INTMSK_REG 0x19 -#define CY8C95XX_PORT_SELECT_PWM 0x1A -#define CY8C95XX_PIN_DIRECTION_REG 0x1C -#define CY8C95XX_DRIVE_MODE_PU_REG 0x1D -#define CY8C95XX_DRIVE_MODE_PD_REG 0x1E -#define CY8C95XX_DRIVE_MODE_ODH_REG 0x1F -#define CY8C95XX_DRIVE_MODE_ODL_REG 0x20 -#define CY8C95XX_DRIVE_MODE_S_REG 0x21 -#define CY8C95XX_DRIVE_MODE_SS_REG 0x22 -#define CY8C95XX_DRIVE_MODE_HZ_REG 0x23 - -#define CY8C95XX_PWM_SELECT 0x28 -#define CY8C95XX_PWM_CONFIG 0x29 -#define CY8C95XX_PWM_PERIOD 0x2A -#define CY8C95XX_PWM_PULSEWIDTH 0x2B -#define CY8C95XX_PWM_DIVIDER 0x2C - -#define CY8C95XX_ENABLE_REG 0x2D -#define CY8C95XX_DEVICE_ID_REG 0x2E -#define CY8C95XX_COMMAND_REG 0x30 - -extern int32_t cy8c95xx_readid(CY8C95XX_DEF_PTR obj, uint8_t *value); - -extern int32_t cy8c95xx_writeport(CY8C95XX_DEF_PTR obj, uint8_t port, uint8_t value); - -extern int32_t cy8c95xx_readport(CY8C95XX_DEF_PTR obj, uint8_t port, uint8_t *value); - -extern int32_t cy8c95xx_reg_write(CY8C95XX_DEF_PTR obj, uint8_t dev, uint8_t regaddr, uint8_t *val, uint8_t len); - -extern int32_t cy8c95xx_reg_read(CY8C95XX_DEF_PTR obj, uint8_t dev, uint8_t regaddr, uint8_t *val, uint8_t len); - -#endif /* H_CY8C95XX */ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.mk b/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.mk deleted file mode 100644 index f5b456eb..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/io/cy8c95xx/cy8c95xx.mk +++ /dev/null @@ -1,2 +0,0 @@ -DEV_CSRCDIR += $(EMBARC_ROOT)/device/peripheral/io/cy8c95xx -DEV_INCDIR += $(EMBARC_ROOT)/device/peripheral/io/cy8c95xx diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/dmpKey.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/dmpKey.h deleted file mode 100644 index 23706b2c..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/dmpKey.h +++ /dev/null @@ -1,519 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/* - $License: - Copyright (C) 2011 InvenSense Corporation, All Rights Reserved. - $ - */ -#ifndef DMPKEY_H__ -#define DMPKEY_H__ - -#define KEY_CFG_25 (0) -#define KEY_CFG_24 (KEY_CFG_25 + 1) -#define KEY_CFG_26 (KEY_CFG_24 + 1) -#define KEY_CFG_27 (KEY_CFG_26 + 1) -#define KEY_CFG_21 (KEY_CFG_27 + 1) -#define KEY_CFG_20 (KEY_CFG_21 + 1) -#define KEY_CFG_TAP4 (KEY_CFG_20 + 1) -#define KEY_CFG_TAP5 (KEY_CFG_TAP4 + 1) -#define KEY_CFG_TAP6 (KEY_CFG_TAP5 + 1) -#define KEY_CFG_TAP7 (KEY_CFG_TAP6 + 1) -#define KEY_CFG_TAP0 (KEY_CFG_TAP7 + 1) -#define KEY_CFG_TAP1 (KEY_CFG_TAP0 + 1) -#define KEY_CFG_TAP2 (KEY_CFG_TAP1 + 1) -#define KEY_CFG_TAP3 (KEY_CFG_TAP2 + 1) -#define KEY_CFG_TAP_QUANTIZE (KEY_CFG_TAP3 + 1) -#define KEY_CFG_TAP_JERK (KEY_CFG_TAP_QUANTIZE + 1) -#define KEY_CFG_DR_INT (KEY_CFG_TAP_JERK + 1) -#define KEY_CFG_AUTH (KEY_CFG_DR_INT + 1) -#define KEY_CFG_TAP_SAVE_ACCB (KEY_CFG_AUTH + 1) -#define KEY_CFG_TAP_CLEAR_STICKY (KEY_CFG_TAP_SAVE_ACCB + 1) -#define KEY_CFG_FIFO_ON_EVENT (KEY_CFG_TAP_CLEAR_STICKY + 1) -#define KEY_FCFG_ACCEL_INPUT (KEY_CFG_FIFO_ON_EVENT + 1) -#define KEY_FCFG_ACCEL_INIT (KEY_FCFG_ACCEL_INPUT + 1) -#define KEY_CFG_23 (KEY_FCFG_ACCEL_INIT + 1) -#define KEY_FCFG_1 (KEY_CFG_23 + 1) -#define KEY_FCFG_3 (KEY_FCFG_1 + 1) -#define KEY_FCFG_2 (KEY_FCFG_3 + 1) -#define KEY_CFG_3D (KEY_FCFG_2 + 1) -#define KEY_CFG_3B (KEY_CFG_3D + 1) -#define KEY_CFG_3C (KEY_CFG_3B + 1) -#define KEY_FCFG_5 (KEY_CFG_3C + 1) -#define KEY_FCFG_4 (KEY_FCFG_5 + 1) -#define KEY_FCFG_7 (KEY_FCFG_4 + 1) -#define KEY_FCFG_FSCALE (KEY_FCFG_7 + 1) -#define KEY_FCFG_AZ (KEY_FCFG_FSCALE + 1) -#define KEY_FCFG_6 (KEY_FCFG_AZ + 1) -#define KEY_FCFG_LSB4 (KEY_FCFG_6 + 1) -#define KEY_CFG_12 (KEY_FCFG_LSB4 + 1) -#define KEY_CFG_14 (KEY_CFG_12 + 1) -#define KEY_CFG_15 (KEY_CFG_14 + 1) -#define KEY_CFG_16 (KEY_CFG_15 + 1) -#define KEY_CFG_18 (KEY_CFG_16 + 1) -#define KEY_CFG_6 (KEY_CFG_18 + 1) -#define KEY_CFG_7 (KEY_CFG_6 + 1) -#define KEY_CFG_4 (KEY_CFG_7 + 1) -#define KEY_CFG_5 (KEY_CFG_4 + 1) -#define KEY_CFG_2 (KEY_CFG_5 + 1) -#define KEY_CFG_3 (KEY_CFG_2 + 1) -#define KEY_CFG_1 (KEY_CFG_3 + 1) -#define KEY_CFG_EXTERNAL (KEY_CFG_1 + 1) -#define KEY_CFG_8 (KEY_CFG_EXTERNAL + 1) -#define KEY_CFG_9 (KEY_CFG_8 + 1) -#define KEY_CFG_ORIENT_3 (KEY_CFG_9 + 1) -#define KEY_CFG_ORIENT_2 (KEY_CFG_ORIENT_3 + 1) -#define KEY_CFG_ORIENT_1 (KEY_CFG_ORIENT_2 + 1) -#define KEY_CFG_GYRO_SOURCE (KEY_CFG_ORIENT_1 + 1) -#define KEY_CFG_ORIENT_IRQ_1 (KEY_CFG_GYRO_SOURCE + 1) -#define KEY_CFG_ORIENT_IRQ_2 (KEY_CFG_ORIENT_IRQ_1 + 1) -#define KEY_CFG_ORIENT_IRQ_3 (KEY_CFG_ORIENT_IRQ_2 + 1) -#define KEY_FCFG_MAG_VAL (KEY_CFG_ORIENT_IRQ_3 + 1) -#define KEY_FCFG_MAG_MOV (KEY_FCFG_MAG_VAL + 1) -#define KEY_CFG_LP_QUAT (KEY_FCFG_MAG_MOV + 1) - -/* MPU6050 keys */ -#define KEY_CFG_ACCEL_FILTER (KEY_CFG_LP_QUAT + 1) -#define KEY_CFG_MOTION_BIAS (KEY_CFG_ACCEL_FILTER + 1) -#define KEY_TEMPLABEL (KEY_CFG_MOTION_BIAS + 1) - -#define KEY_D_0_22 (KEY_TEMPLABEL + 1) -#define KEY_D_0_24 (KEY_D_0_22 + 1) -#define KEY_D_0_36 (KEY_D_0_24 + 1) -#define KEY_D_0_52 (KEY_D_0_36 + 1) -#define KEY_D_0_96 (KEY_D_0_52 + 1) -#define KEY_D_0_104 (KEY_D_0_96 + 1) -#define KEY_D_0_108 (KEY_D_0_104 + 1) -#define KEY_D_0_163 (KEY_D_0_108 + 1) -#define KEY_D_0_188 (KEY_D_0_163 + 1) -#define KEY_D_0_192 (KEY_D_0_188 + 1) -#define KEY_D_0_224 (KEY_D_0_192 + 1) -#define KEY_D_0_228 (KEY_D_0_224 + 1) -#define KEY_D_0_232 (KEY_D_0_228 + 1) -#define KEY_D_0_236 (KEY_D_0_232 + 1) - -#define KEY_DMP_PREVPTAT (KEY_D_0_236 + 1) -#define KEY_D_1_2 (KEY_DMP_PREVPTAT + 1) -#define KEY_D_1_4 (KEY_D_1_2 + 1) -#define KEY_D_1_8 (KEY_D_1_4 + 1) -#define KEY_D_1_10 (KEY_D_1_8 + 1) -#define KEY_D_1_24 (KEY_D_1_10 + 1) -#define KEY_D_1_28 (KEY_D_1_24 + 1) -#define KEY_D_1_36 (KEY_D_1_28 + 1) -#define KEY_D_1_40 (KEY_D_1_36 + 1) -#define KEY_D_1_44 (KEY_D_1_40 + 1) -#define KEY_D_1_72 (KEY_D_1_44 + 1) -#define KEY_D_1_74 (KEY_D_1_72 + 1) -#define KEY_D_1_79 (KEY_D_1_74 + 1) -#define KEY_D_1_88 (KEY_D_1_79 + 1) -#define KEY_D_1_90 (KEY_D_1_88 + 1) -#define KEY_D_1_92 (KEY_D_1_90 + 1) -#define KEY_D_1_96 (KEY_D_1_92 + 1) -#define KEY_D_1_98 (KEY_D_1_96 + 1) -#define KEY_D_1_100 (KEY_D_1_98 + 1) -#define KEY_D_1_106 (KEY_D_1_100 + 1) -#define KEY_D_1_108 (KEY_D_1_106 + 1) -#define KEY_D_1_112 (KEY_D_1_108 + 1) -#define KEY_D_1_128 (KEY_D_1_112 + 1) -#define KEY_D_1_152 (KEY_D_1_128 + 1) -#define KEY_D_1_160 (KEY_D_1_152 + 1) -#define KEY_D_1_168 (KEY_D_1_160 + 1) -#define KEY_D_1_175 (KEY_D_1_168 + 1) -#define KEY_D_1_176 (KEY_D_1_175 + 1) -#define KEY_D_1_178 (KEY_D_1_176 + 1) -#define KEY_D_1_179 (KEY_D_1_178 + 1) -#define KEY_D_1_218 (KEY_D_1_179 + 1) -#define KEY_D_1_232 (KEY_D_1_218 + 1) -#define KEY_D_1_236 (KEY_D_1_232 + 1) -#define KEY_D_1_240 (KEY_D_1_236 + 1) -#define KEY_D_1_244 (KEY_D_1_240 + 1) -#define KEY_D_1_250 (KEY_D_1_244 + 1) -#define KEY_D_1_252 (KEY_D_1_250 + 1) -#define KEY_D_2_12 (KEY_D_1_252 + 1) -#define KEY_D_2_96 (KEY_D_2_12 + 1) -#define KEY_D_2_108 (KEY_D_2_96 + 1) -#define KEY_D_2_208 (KEY_D_2_108 + 1) -#define KEY_FLICK_MSG (KEY_D_2_208 + 1) -#define KEY_FLICK_COUNTER (KEY_FLICK_MSG + 1) -#define KEY_FLICK_LOWER (KEY_FLICK_COUNTER + 1) -#define KEY_CFG_FLICK_IN (KEY_FLICK_LOWER + 1) -#define KEY_FLICK_UPPER (KEY_CFG_FLICK_IN + 1) -#define KEY_CGNOTICE_INTR (KEY_FLICK_UPPER + 1) -#define KEY_D_2_224 (KEY_CGNOTICE_INTR + 1) -#define KEY_D_2_244 (KEY_D_2_224 + 1) -#define KEY_D_2_248 (KEY_D_2_244 + 1) -#define KEY_D_2_252 (KEY_D_2_248 + 1) - -#define KEY_D_GYRO_BIAS_X (KEY_D_2_252 + 1) -#define KEY_D_GYRO_BIAS_Y (KEY_D_GYRO_BIAS_X + 1) -#define KEY_D_GYRO_BIAS_Z (KEY_D_GYRO_BIAS_Y + 1) -#define KEY_D_ACC_BIAS_X (KEY_D_GYRO_BIAS_Z + 1) -#define KEY_D_ACC_BIAS_Y (KEY_D_ACC_BIAS_X + 1) -#define KEY_D_ACC_BIAS_Z (KEY_D_ACC_BIAS_Y + 1) -#define KEY_D_GYRO_ENABLE (KEY_D_ACC_BIAS_Z + 1) -#define KEY_D_ACCEL_ENABLE (KEY_D_GYRO_ENABLE + 1) -#define KEY_D_QUAT_ENABLE (KEY_D_ACCEL_ENABLE + 1) -#define KEY_D_OUTPUT_ENABLE (KEY_D_QUAT_ENABLE + 1) -#define KEY_D_CR_TIME_G (KEY_D_OUTPUT_ENABLE + 1) -#define KEY_D_CR_TIME_A (KEY_D_CR_TIME_G + 1) -#define KEY_D_CR_TIME_Q (KEY_D_CR_TIME_A + 1) -#define KEY_D_CS_TAX (KEY_D_CR_TIME_Q + 1) -#define KEY_D_CS_TAY (KEY_D_CS_TAX + 1) -#define KEY_D_CS_TAZ (KEY_D_CS_TAY + 1) -#define KEY_D_CS_TGX (KEY_D_CS_TAZ + 1) -#define KEY_D_CS_TGY (KEY_D_CS_TGX + 1) -#define KEY_D_CS_TGZ (KEY_D_CS_TGY + 1) -#define KEY_D_CS_TQ0 (KEY_D_CS_TGZ + 1) -#define KEY_D_CS_TQ1 (KEY_D_CS_TQ0 + 1) -#define KEY_D_CS_TQ2 (KEY_D_CS_TQ1 + 1) -#define KEY_D_CS_TQ3 (KEY_D_CS_TQ2 + 1) - -/* Compass keys */ -#define KEY_CPASS_BIAS_X (KEY_D_CS_TQ3 + 1) -#define KEY_CPASS_BIAS_Y (KEY_CPASS_BIAS_X + 1) -#define KEY_CPASS_BIAS_Z (KEY_CPASS_BIAS_Y + 1) -#define KEY_CPASS_MTX_00 (KEY_CPASS_BIAS_Z + 1) -#define KEY_CPASS_MTX_01 (KEY_CPASS_MTX_00 + 1) -#define KEY_CPASS_MTX_02 (KEY_CPASS_MTX_01 + 1) -#define KEY_CPASS_MTX_10 (KEY_CPASS_MTX_02 + 1) -#define KEY_CPASS_MTX_11 (KEY_CPASS_MTX_10 + 1) -#define KEY_CPASS_MTX_12 (KEY_CPASS_MTX_11 + 1) -#define KEY_CPASS_MTX_20 (KEY_CPASS_MTX_12 + 1) -#define KEY_CPASS_MTX_21 (KEY_CPASS_MTX_20 + 1) -#define KEY_CPASS_MTX_22 (KEY_CPASS_MTX_21 + 1) - -/* Gesture Keys */ -#define KEY_DMP_TAPW_MIN (KEY_CPASS_MTX_22 + 1) -#define KEY_DMP_TAP_THR_X (KEY_DMP_TAPW_MIN + 1) -#define KEY_DMP_TAP_THR_Y (KEY_DMP_TAP_THR_X + 1) -#define KEY_DMP_TAP_THR_Z (KEY_DMP_TAP_THR_Y + 1) -#define KEY_DMP_SH_TH_Y (KEY_DMP_TAP_THR_Z + 1) -#define KEY_DMP_SH_TH_X (KEY_DMP_SH_TH_Y + 1) -#define KEY_DMP_SH_TH_Z (KEY_DMP_SH_TH_X + 1) -#define KEY_DMP_ORIENT (KEY_DMP_SH_TH_Z + 1) -#define KEY_D_ACT0 (KEY_DMP_ORIENT + 1) -#define KEY_D_ACSX (KEY_D_ACT0 + 1) -#define KEY_D_ACSY (KEY_D_ACSX + 1) -#define KEY_D_ACSZ (KEY_D_ACSY + 1) - -#define KEY_X_GRT_Y_TMP (KEY_D_ACSZ + 1) -#define KEY_SKIP_X_GRT_Y_TMP (KEY_X_GRT_Y_TMP + 1) -#define KEY_SKIP_END_COMPARE (KEY_SKIP_X_GRT_Y_TMP + 1) -#define KEY_END_COMPARE_Y_X_TMP2 (KEY_SKIP_END_COMPARE + 1) -#define KEY_CFG_ANDROID_ORIENT_INT (KEY_END_COMPARE_Y_X_TMP2 + 1) -#define KEY_NO_ORIENT_INTERRUPT (KEY_CFG_ANDROID_ORIENT_INT + 1) -#define KEY_END_COMPARE_Y_X_TMP (KEY_NO_ORIENT_INTERRUPT + 1) -#define KEY_END_ORIENT_1 (KEY_END_COMPARE_Y_X_TMP + 1) -#define KEY_END_COMPARE_Y_X (KEY_END_ORIENT_1 + 1) -#define KEY_END_ORIENT (KEY_END_COMPARE_Y_X + 1) -#define KEY_X_GRT_Y (KEY_END_ORIENT + 1) -#define KEY_NOT_TIME_MINUS_1 (KEY_X_GRT_Y + 1) -#define KEY_END_COMPARE_Y_X_TMP3 (KEY_NOT_TIME_MINUS_1 + 1) -#define KEY_X_GRT_Y_TMP2 (KEY_END_COMPARE_Y_X_TMP3 + 1) - -/* Authenticate Keys */ -#define KEY_D_AUTH_OUT (KEY_X_GRT_Y_TMP2 + 1) -#define KEY_D_AUTH_IN (KEY_D_AUTH_OUT + 1) -#define KEY_D_AUTH_A (KEY_D_AUTH_IN + 1) -#define KEY_D_AUTH_B (KEY_D_AUTH_A + 1) - -/* Pedometer standalone only keys */ -#define KEY_D_PEDSTD_BP_B (KEY_D_AUTH_B + 1) -#define KEY_D_PEDSTD_HP_A (KEY_D_PEDSTD_BP_B + 1) -#define KEY_D_PEDSTD_HP_B (KEY_D_PEDSTD_HP_A + 1) -#define KEY_D_PEDSTD_BP_A4 (KEY_D_PEDSTD_HP_B + 1) -#define KEY_D_PEDSTD_BP_A3 (KEY_D_PEDSTD_BP_A4 + 1) -#define KEY_D_PEDSTD_BP_A2 (KEY_D_PEDSTD_BP_A3 + 1) -#define KEY_D_PEDSTD_BP_A1 (KEY_D_PEDSTD_BP_A2 + 1) -#define KEY_D_PEDSTD_INT_THRSH (KEY_D_PEDSTD_BP_A1 + 1) -#define KEY_D_PEDSTD_CLIP (KEY_D_PEDSTD_INT_THRSH + 1) -#define KEY_D_PEDSTD_SB (KEY_D_PEDSTD_CLIP + 1) -#define KEY_D_PEDSTD_SB_TIME (KEY_D_PEDSTD_SB + 1) -#define KEY_D_PEDSTD_PEAKTHRSH (KEY_D_PEDSTD_SB_TIME + 1) -#define KEY_D_PEDSTD_TIML (KEY_D_PEDSTD_PEAKTHRSH + 1) -#define KEY_D_PEDSTD_TIMH (KEY_D_PEDSTD_TIML + 1) -#define KEY_D_PEDSTD_PEAK (KEY_D_PEDSTD_TIMH + 1) -#define KEY_D_PEDSTD_TIMECTR (KEY_D_PEDSTD_PEAK + 1) -#define KEY_D_PEDSTD_STEPCTR (KEY_D_PEDSTD_TIMECTR + 1) -#define KEY_D_PEDSTD_WALKTIME (KEY_D_PEDSTD_STEPCTR + 1) -#define KEY_D_PEDSTD_DECI (KEY_D_PEDSTD_WALKTIME + 1) - -/*Host Based No Motion*/ -#define KEY_D_HOST_NO_MOT (KEY_D_PEDSTD_DECI + 1) - -/* EIS keys */ -#define KEY_P_EIS_FIFO_FOOTER (KEY_D_HOST_NO_MOT + 1) -#define KEY_P_EIS_FIFO_YSHIFT (KEY_P_EIS_FIFO_FOOTER + 1) -#define KEY_P_EIS_DATA_RATE (KEY_P_EIS_FIFO_YSHIFT + 1) -#define KEY_P_EIS_FIFO_XSHIFT (KEY_P_EIS_DATA_RATE + 1) -#define KEY_P_EIS_FIFO_SYNC (KEY_P_EIS_FIFO_XSHIFT + 1) -#define KEY_P_EIS_FIFO_ZSHIFT (KEY_P_EIS_FIFO_SYNC + 1) -#define KEY_P_EIS_FIFO_READY (KEY_P_EIS_FIFO_ZSHIFT + 1) -#define KEY_DMP_FOOTER (KEY_P_EIS_FIFO_READY + 1) -#define KEY_DMP_INTX_HC (KEY_DMP_FOOTER + 1) -#define KEY_DMP_INTX_PH (KEY_DMP_INTX_HC + 1) -#define KEY_DMP_INTX_SH (KEY_DMP_INTX_PH + 1) -#define KEY_DMP_AINV_SH (KEY_DMP_INTX_SH + 1) -#define KEY_DMP_A_INV_XH (KEY_DMP_AINV_SH + 1) -#define KEY_DMP_AINV_PH (KEY_DMP_A_INV_XH + 1) -#define KEY_DMP_CTHX_H (KEY_DMP_AINV_PH + 1) -#define KEY_DMP_CTHY_H (KEY_DMP_CTHX_H + 1) -#define KEY_DMP_CTHZ_H (KEY_DMP_CTHY_H + 1) -#define KEY_DMP_NCTHX_H (KEY_DMP_CTHZ_H + 1) -#define KEY_DMP_NCTHY_H (KEY_DMP_NCTHX_H + 1) -#define KEY_DMP_NCTHZ_H (KEY_DMP_NCTHY_H + 1) -#define KEY_DMP_CTSQ_XH (KEY_DMP_NCTHZ_H + 1) -#define KEY_DMP_CTSQ_YH (KEY_DMP_CTSQ_XH + 1) -#define KEY_DMP_CTSQ_ZH (KEY_DMP_CTSQ_YH + 1) -#define KEY_DMP_INTX_H (KEY_DMP_CTSQ_ZH + 1) -#define KEY_DMP_INTY_H (KEY_DMP_INTX_H + 1) -#define KEY_DMP_INTZ_H (KEY_DMP_INTY_H + 1) -// #define KEY_DMP_HPX_H (KEY_DMP_INTZ_H + 1) -// #define KEY_DMP_HPY_H (KEY_DMP_HPX_H + 1) -// #define KEY_DMP_HPZ_H (KEY_DMP_HPY_H + 1) - -/* Stream keys */ -#define KEY_STREAM_P_GYRO_Z (KEY_DMP_INTZ_H + 1) -#define KEY_STREAM_P_GYRO_Y (KEY_STREAM_P_GYRO_Z + 1) -#define KEY_STREAM_P_GYRO_X (KEY_STREAM_P_GYRO_Y + 1) -#define KEY_STREAM_P_TEMP (KEY_STREAM_P_GYRO_X + 1) -#define KEY_STREAM_P_AUX_Y (KEY_STREAM_P_TEMP + 1) -#define KEY_STREAM_P_AUX_X (KEY_STREAM_P_AUX_Y + 1) -#define KEY_STREAM_P_AUX_Z (KEY_STREAM_P_AUX_X + 1) -#define KEY_STREAM_P_ACCEL_Y (KEY_STREAM_P_AUX_Z + 1) -#define KEY_STREAM_P_ACCEL_X (KEY_STREAM_P_ACCEL_Y + 1) -#define KEY_STREAM_P_FOOTER (KEY_STREAM_P_ACCEL_X + 1) -#define KEY_STREAM_P_ACCEL_Z (KEY_STREAM_P_FOOTER + 1) - -#define NUM_KEYS (KEY_STREAM_P_ACCEL_Z + 1) - -typedef struct { - unsigned short key; - unsigned short addr; -} tKeyLabel; - -#define DINA0A 0x0a -#define DINA22 0x22 -#define DINA42 0x42 -#define DINA5A 0x5a - -#define DINA06 0x06 -#define DINA0E 0x0e -#define DINA16 0x16 -#define DINA1E 0x1e -#define DINA26 0x26 -#define DINA2E 0x2e -#define DINA36 0x36 -#define DINA3E 0x3e -#define DINA46 0x46 -#define DINA4E 0x4e -#define DINA56 0x56 -#define DINA5E 0x5e -#define DINA66 0x66 -#define DINA6E 0x6e -#define DINA76 0x76 -#define DINA7E 0x7e - -#define DINA00 0x00 -#define DINA08 0x08 -#define DINA10 0x10 -#define DINA18 0x18 -#define DINA20 0x20 -#define DINA28 0x28 -#define DINA30 0x30 -#define DINA38 0x38 -#define DINA40 0x40 -#define DINA48 0x48 -#define DINA50 0x50 -#define DINA58 0x58 -#define DINA60 0x60 -#define DINA68 0x68 -#define DINA70 0x70 -#define DINA78 0x78 - -#define DINA04 0x04 -#define DINA0C 0x0c -#define DINA14 0x14 -#define DINA1C 0x1C -#define DINA24 0x24 -#define DINA2C 0x2c -#define DINA34 0x34 -#define DINA3C 0x3c -#define DINA44 0x44 -#define DINA4C 0x4c -#define DINA54 0x54 -#define DINA5C 0x5c -#define DINA64 0x64 -#define DINA6C 0x6c -#define DINA74 0x74 -#define DINA7C 0x7c - -#define DINA01 0x01 -#define DINA09 0x09 -#define DINA11 0x11 -#define DINA19 0x19 -#define DINA21 0x21 -#define DINA29 0x29 -#define DINA31 0x31 -#define DINA39 0x39 -#define DINA41 0x41 -#define DINA49 0x49 -#define DINA51 0x51 -#define DINA59 0x59 -#define DINA61 0x61 -#define DINA69 0x69 -#define DINA71 0x71 -#define DINA79 0x79 - -#define DINA25 0x25 -#define DINA2D 0x2d -#define DINA35 0x35 -#define DINA3D 0x3d -#define DINA4D 0x4d -#define DINA55 0x55 -#define DINA5D 0x5D -#define DINA6D 0x6d -#define DINA75 0x75 -#define DINA7D 0x7d - -#define DINADC 0xdc -#define DINAF2 0xf2 -#define DINAAB 0xab -#define DINAAA 0xaa -#define DINAF1 0xf1 -#define DINADF 0xdf -#define DINADA 0xda -#define DINAB1 0xb1 -#define DINAB9 0xb9 -#define DINAF3 0xf3 -#define DINA8B 0x8b -#define DINAA3 0xa3 -#define DINA91 0x91 -#define DINAB6 0xb6 -#define DINAB4 0xb4 - -#define DINC00 0x00 -#define DINC01 0x01 -#define DINC02 0x02 -#define DINC03 0x03 -#define DINC08 0x08 -#define DINC09 0x09 -#define DINC0A 0x0a -#define DINC0B 0x0b -#define DINC10 0x10 -#define DINC11 0x11 -#define DINC12 0x12 -#define DINC13 0x13 -#define DINC18 0x18 -#define DINC19 0x19 -#define DINC1A 0x1a -#define DINC1B 0x1b - -#define DINC20 0x20 -#define DINC21 0x21 -#define DINC22 0x22 -#define DINC23 0x23 -#define DINC28 0x28 -#define DINC29 0x29 -#define DINC2A 0x2a -#define DINC2B 0x2b -#define DINC30 0x30 -#define DINC31 0x31 -#define DINC32 0x32 -#define DINC33 0x33 -#define DINC38 0x38 -#define DINC39 0x39 -#define DINC3A 0x3a -#define DINC3B 0x3b - -#define DINC40 0x40 -#define DINC41 0x41 -#define DINC42 0x42 -#define DINC43 0x43 -#define DINC48 0x48 -#define DINC49 0x49 -#define DINC4A 0x4a -#define DINC4B 0x4b -#define DINC50 0x50 -#define DINC51 0x51 -#define DINC52 0x52 -#define DINC53 0x53 -#define DINC58 0x58 -#define DINC59 0x59 -#define DINC5A 0x5a -#define DINC5B 0x5b - -#define DINC60 0x60 -#define DINC61 0x61 -#define DINC62 0x62 -#define DINC63 0x63 -#define DINC68 0x68 -#define DINC69 0x69 -#define DINC6A 0x6a -#define DINC6B 0x6b -#define DINC70 0x70 -#define DINC71 0x71 -#define DINC72 0x72 -#define DINC73 0x73 -#define DINC78 0x78 -#define DINC79 0x79 -#define DINC7A 0x7a -#define DINC7B 0x7b - -#define DIND40 0x40 - -#define DINA80 0x80 -#define DINA90 0x90 -#define DINAA0 0xa0 -#define DINAC9 0xc9 -#define DINACB 0xcb -#define DINACD 0xcd -#define DINACF 0xcf -#define DINAC8 0xc8 -#define DINACA 0xca -#define DINACC 0xcc -#define DINACE 0xce -#define DINAD8 0xd8 -#define DINADD 0xdd -#define DINAF8 0xf0 -#define DINAFE 0xfe - -#define DINBF8 0xf8 -#define DINAC0 0xb0 -#define DINAC1 0xb1 -#define DINAC2 0xb4 -#define DINAC3 0xb5 -#define DINAC4 0xb8 -#define DINAC5 0xb9 -#define DINBC0 0xc0 -#define DINBC2 0xc2 -#define DINBC4 0xc4 -#define DINBC6 0xc6 - -#endif // DMPKEY_H__ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/dmpmap.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/dmpmap.h deleted file mode 100644 index d8564fc2..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/dmpmap.h +++ /dev/null @@ -1,293 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/* - $License: - Copyright (C) 2011 InvenSense Corporation, All Rights Reserved. - $ - */ -#ifndef DMPMAP_H -#define DMPMAP_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#define DMP_PTAT 0 -#define DMP_XGYR 2 -#define DMP_YGYR 4 -#define DMP_ZGYR 6 -#define DMP_XACC 8 -#define DMP_YACC 10 -#define DMP_ZACC 12 -#define DMP_ADC1 14 -#define DMP_ADC2 16 -#define DMP_ADC3 18 -#define DMP_BIASUNC 20 -#define DMP_FIFORT 22 -#define DMP_INVGSFH 24 -#define DMP_INVGSFL 26 -#define DMP_1H 28 -#define DMP_1L 30 -#define DMP_BLPFSTCH 32 -#define DMP_BLPFSTCL 34 -#define DMP_BLPFSXH 36 -#define DMP_BLPFSXL 38 -#define DMP_BLPFSYH 40 -#define DMP_BLPFSYL 42 -#define DMP_BLPFSZH 44 -#define DMP_BLPFSZL 46 -#define DMP_BLPFMTC 48 -#define DMP_SMC 50 -#define DMP_BLPFMXH 52 -#define DMP_BLPFMXL 54 -#define DMP_BLPFMYH 56 -#define DMP_BLPFMYL 58 -#define DMP_BLPFMZH 60 -#define DMP_BLPFMZL 62 -#define DMP_BLPFC 64 -#define DMP_SMCTH 66 -#define DMP_0H2 68 -#define DMP_0L2 70 -#define DMP_BERR2H 72 -#define DMP_BERR2L 74 -#define DMP_BERR2NH 76 -#define DMP_SMCINC 78 -#define DMP_ANGVBXH 80 -#define DMP_ANGVBXL 82 -#define DMP_ANGVBYH 84 -#define DMP_ANGVBYL 86 -#define DMP_ANGVBZH 88 -#define DMP_ANGVBZL 90 -#define DMP_BERR1H 92 -#define DMP_BERR1L 94 -#define DMP_ATCH 96 -#define DMP_BIASUNCSF 98 -#define DMP_ACT2H 100 -#define DMP_ACT2L 102 -#define DMP_GSFH 104 -#define DMP_GSFL 106 -#define DMP_GH 108 -#define DMP_GL 110 -#define DMP_0_5H 112 -#define DMP_0_5L 114 -#define DMP_0_0H 116 -#define DMP_0_0L 118 -#define DMP_1_0H 120 -#define DMP_1_0L 122 -#define DMP_1_5H 124 -#define DMP_1_5L 126 -#define DMP_TMP1AH 128 -#define DMP_TMP1AL 130 -#define DMP_TMP2AH 132 -#define DMP_TMP2AL 134 -#define DMP_TMP3AH 136 -#define DMP_TMP3AL 138 -#define DMP_TMP4AH 140 -#define DMP_TMP4AL 142 -#define DMP_XACCW 144 -#define DMP_TMP5 146 -#define DMP_XACCB 148 -#define DMP_TMP8 150 -#define DMP_YACCB 152 -#define DMP_TMP9 154 -#define DMP_ZACCB 156 -#define DMP_TMP10 158 -#define DMP_DZH 160 -#define DMP_DZL 162 -#define DMP_XGCH 164 -#define DMP_XGCL 166 -#define DMP_YGCH 168 -#define DMP_YGCL 170 -#define DMP_ZGCH 172 -#define DMP_ZGCL 174 -#define DMP_YACCW 176 -#define DMP_TMP7 178 -#define DMP_AFB1H 180 -#define DMP_AFB1L 182 -#define DMP_AFB2H 184 -#define DMP_AFB2L 186 -#define DMP_MAGFBH 188 -#define DMP_MAGFBL 190 -#define DMP_QT1H 192 -#define DMP_QT1L 194 -#define DMP_QT2H 196 -#define DMP_QT2L 198 -#define DMP_QT3H 200 -#define DMP_QT3L 202 -#define DMP_QT4H 204 -#define DMP_QT4L 206 -#define DMP_CTRL1H 208 -#define DMP_CTRL1L 210 -#define DMP_CTRL2H 212 -#define DMP_CTRL2L 214 -#define DMP_CTRL3H 216 -#define DMP_CTRL3L 218 -#define DMP_CTRL4H 220 -#define DMP_CTRL4L 222 -#define DMP_CTRLS1 224 -#define DMP_CTRLSF1 226 -#define DMP_CTRLS2 228 -#define DMP_CTRLSF2 230 -#define DMP_CTRLS3 232 -#define DMP_CTRLSFNLL 234 -#define DMP_CTRLS4 236 -#define DMP_CTRLSFNL2 238 -#define DMP_CTRLSFNL 240 -#define DMP_TMP30 242 -#define DMP_CTRLSFJT 244 -#define DMP_TMP31 246 -#define DMP_TMP11 248 -#define DMP_CTRLSF2_2 250 -#define DMP_TMP12 252 -#define DMP_CTRLSF1_2 254 -#define DMP_PREVPTAT 256 -#define DMP_ACCZB 258 -#define DMP_ACCXB 264 -#define DMP_ACCYB 266 -#define DMP_1HB 272 -#define DMP_1LB 274 -#define DMP_0H 276 -#define DMP_0L 278 -#define DMP_ASR22H 280 -#define DMP_ASR22L 282 -#define DMP_ASR6H 284 -#define DMP_ASR6L 286 -#define DMP_TMP13 288 -#define DMP_TMP14 290 -#define DMP_FINTXH 292 -#define DMP_FINTXL 294 -#define DMP_FINTYH 296 -#define DMP_FINTYL 298 -#define DMP_FINTZH 300 -#define DMP_FINTZL 302 -#define DMP_TMP1BH 304 -#define DMP_TMP1BL 306 -#define DMP_TMP2BH 308 -#define DMP_TMP2BL 310 -#define DMP_TMP3BH 312 -#define DMP_TMP3BL 314 -#define DMP_TMP4BH 316 -#define DMP_TMP4BL 318 -#define DMP_STXG 320 -#define DMP_ZCTXG 322 -#define DMP_STYG 324 -#define DMP_ZCTYG 326 -#define DMP_STZG 328 -#define DMP_ZCTZG 330 -#define DMP_CTRLSFJT2 332 -#define DMP_CTRLSFJTCNT 334 -#define DMP_PVXG 336 -#define DMP_TMP15 338 -#define DMP_PVYG 340 -#define DMP_TMP16 342 -#define DMP_PVZG 344 -#define DMP_TMP17 346 -#define DMP_MNMFLAGH 352 -#define DMP_MNMFLAGL 354 -#define DMP_MNMTMH 356 -#define DMP_MNMTML 358 -#define DMP_MNMTMTHRH 360 -#define DMP_MNMTMTHRL 362 -#define DMP_MNMTHRH 364 -#define DMP_MNMTHRL 366 -#define DMP_ACCQD4H 368 -#define DMP_ACCQD4L 370 -#define DMP_ACCQD5H 372 -#define DMP_ACCQD5L 374 -#define DMP_ACCQD6H 376 -#define DMP_ACCQD6L 378 -#define DMP_ACCQD7H 380 -#define DMP_ACCQD7L 382 -#define DMP_ACCQD0H 384 -#define DMP_ACCQD0L 386 -#define DMP_ACCQD1H 388 -#define DMP_ACCQD1L 390 -#define DMP_ACCQD2H 392 -#define DMP_ACCQD2L 394 -#define DMP_ACCQD3H 396 -#define DMP_ACCQD3L 398 -#define DMP_XN2H 400 -#define DMP_XN2L 402 -#define DMP_XN1H 404 -#define DMP_XN1L 406 -#define DMP_YN2H 408 -#define DMP_YN2L 410 -#define DMP_YN1H 412 -#define DMP_YN1L 414 -#define DMP_YH 416 -#define DMP_YL 418 -#define DMP_B0H 420 -#define DMP_B0L 422 -#define DMP_A1H 424 -#define DMP_A1L 426 -#define DMP_A2H 428 -#define DMP_A2L 430 -#define DMP_SEM1 432 -#define DMP_FIFOCNT 434 -#define DMP_SH_TH_X 436 -#define DMP_PACKET 438 -#define DMP_SH_TH_Y 440 -#define DMP_FOOTER 442 -#define DMP_SH_TH_Z 444 -#define DMP_TEMP29 448 -#define DMP_TEMP30 450 -#define DMP_XACCB_PRE 452 -#define DMP_XACCB_PREL 454 -#define DMP_YACCB_PRE 456 -#define DMP_YACCB_PREL 458 -#define DMP_ZACCB_PRE 460 -#define DMP_ZACCB_PREL 462 -#define DMP_TMP22 464 -#define DMP_TAP_TIMER 466 -#define DMP_TAP_THX 468 -#define DMP_TAP_THY 472 -#define DMP_TAP_THZ 476 -#define DMP_TAPW_MIN 478 -#define DMP_TMP25 480 -#define DMP_TMP26 482 -#define DMP_TMP27 484 -#define DMP_TMP28 486 -#define DMP_ORIENT 488 -#define DMP_THRSH 490 -#define DMP_ENDIANH 492 -#define DMP_ENDIANL 494 -#define DMP_BLPFNMTCH 496 -#define DMP_BLPFNMTCL 498 -#define DMP_BLPFNMXH 500 -#define DMP_BLPFNMXL 502 -#define DMP_BLPFNMYH 504 -#define DMP_BLPFNMYL 506 -#define DMP_BLPFNMZH 508 -#define DMP_BLPFNMZL 510 -#ifdef __cplusplus -} -#endif -#endif // DMPMAP_H diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu.c deleted file mode 100644 index 3469adf2..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu.c +++ /dev/null @@ -1,3664 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/* - $License: - Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. - See included License.txt for License information. - $ - */ -/** - * @addtogroup DRIVERS Sensor Driver Layer - * @brief Hardware drivers to communicate with sensors via I2C. - * - * @{ - * @file inv_mpu.c - * @brief An I2C-based driver for Invensense gyroscopes. - * @details This driver currently works for the following devices: - * MPU6050 - * MPU6500 - * MPU9150 (or MPU6050 w/ AK8975 on the auxiliary bus) - * MPU9250 (or MPU6500 w/ AK8963 on the auxiliary bus) - */ -#include -#include -#include -#include -#include -#include "inv_mpu.h" - -/* The following functions must be defined for this platform: - * i2c_write(unsigned char slave_addr, unsigned char reg_addr, - * unsigned char length, unsigned char const *data) - * i2c_read(unsigned char slave_addr, unsigned char reg_addr, - * unsigned char length, unsigned char *data) - * delay_ms(unsigned long num_ms) - * get_ms(unsigned long *count) - * reg_int_cb(void (*cb)(void), unsigned char port, unsigned char pin) - * labs(long x) - * fabsf(float x) - * min(int a, int b) - */ -#define MOTION_DRIVER_TARGET_IOTDK -#define MPU9250 -#if defined MOTION_DRIVER_TARGET_MSP430 -#include "msp430.h" -#include "msp430_i2c.h" -#include "msp430_clock.h" -#include "msp430_interrupt.h" -#define i2c_write msp430_i2c_write -#define i2c_read msp430_i2c_read -#define delay_ms msp430_delay_ms -#define get_ms msp430_get_clock_ms -static inline int reg_int_cb(struct int_param_s *int_param) -{ - return msp430_reg_int_cb(int_param->cb, int_param->pin, int_param->lp_exit, - int_param->active_low); -} -#define log_i(...) do {} while (0) -#define log_e(...) do {} while (0) -/* labs is already defined by TI's toolchain. */ -/* fabs is for doubles. fabsf is for floats. */ -#define fabs fabsf -#define min(a, b) ((a < b) ? a : b) -#elif defined EMPL_TARGET_MSP430 -#include "msp430.h" -#include "msp430_i2c.h" -#include "msp430_clock.h" -#include "msp430_interrupt.h" -#include "log.h" -#define i2c_write msp430_i2c_write -#define i2c_read msp430_i2c_read -#define delay_ms msp430_delay_ms -#define get_ms msp430_get_clock_ms -static inline int reg_int_cb(struct int_param_s *int_param) -{ - return msp430_reg_int_cb(int_param->cb, int_param->pin, int_param->lp_exit, - int_param->active_low); -} -#define log_i MPL_LOGI -#define log_e MPL_LOGE -/* labs is already defined by TI's toolchain. */ -/* fabs is for doubles. fabsf is for floats. */ -#define fabs fabsf -#define min(a, b) ((a < b) ? a : b) -#elif defined EMPL_TARGET_UC3L0 -/* Instead of using the standard TWI driver from the ASF library, we're using - * a TWI driver that follows the slave address + register address convention. - */ -#include "twi.h" -#include "delay.h" -#include "sysclk.h" -#include "log.h" -#include "sensors_xplained.h" -#include "uc3l0_clock.h" -#define i2c_write(a, b, c, d) twi_write(a, b, d, c) -#define i2c_read(a, b, c, d) twi_read(a, b, d, c) -/* delay_ms is a function already defined in ASF. */ -#define get_ms uc3l0_get_clock_ms -static inline int reg_int_cb(struct int_param_s *int_param) -{ - sensor_board_irq_connect(int_param->pin, int_param->cb, int_param->arg); - return 0; -} -#define log_i MPL_LOGI -#define log_e MPL_LOGE -/* UC3 is a 32-bit processor, so abs and labs are equivalent. */ -#define labs abs -#define fabs(x) (((x) > 0) ? (x) : -(x)) -#elif defined MOTION_DRIVER_TARGET_IOTDK -#include -#include "embARC.h" -#include "embARC_debug.h" -#include "mpu9250.h" - -#define i2c_write mpu_iic_write -#define i2c_read mpu_iic_read -#define delay_ms mpu_delay_ms -#define get_ms mpu_get_ms - -#define log_i EMBARC_PRINTF // (...) do {} while (0) -#define log_e EMBARC_PRINTF // (...) do {} while (0) -#define labs abs -#define fabs fabsf -#define min(a, b) ((a < b) ? a : b) - -#else -#error Gyro driver is missing the system layer implementations. -#endif - -#if !defined MPU6050 && !defined MPU9150 && !defined MPU6500 && !defined MPU9250 -#error Which gyro are you using? Define MPUxxxx in your compiler options. -#endif - -/* Time for some messy macro work. =] - * #define MPU9150 - * is equivalent to.. - * #define MPU6050 - * #define AK8975_SECONDARY - * - * #define MPU9250 - * is equivalent to.. - * #define MPU6500 - * #define AK8963_SECONDARY - */ -#if defined MPU9150 -#ifndef MPU6050 -#define MPU6050 -#endif /* #ifndef MPU6050 */ -#if defined AK8963_SECONDARY -#error "MPU9150 and AK8963_SECONDARY cannot both be defined." -#elif !defined AK8975_SECONDARY /* #if defined AK8963_SECONDARY */ -#define AK8975_SECONDARY -#endif /* #if defined AK8963_SECONDARY */ -#elif defined MPU9250 /* #if defined MPU9150 */ -#ifndef MPU6500 -#define MPU6500 -#endif /* #ifndef MPU6500 */ -#if defined AK8975_SECONDARY -#error "MPU9250 and AK8975_SECONDARY cannot both be defined." -#elif !defined AK8963_SECONDARY /* #if defined AK8975_SECONDARY */ -#define AK8963_SECONDARY -#endif /* #if defined AK8975_SECONDARY */ -#endif /* #if defined MPU9150 */ - -#if defined AK8975_SECONDARY || defined AK8963_SECONDARY -#define AK89xx_SECONDARY -#else -/* #warning "No compass = less profit for Invensense. Lame." */ -#endif - -static int set_int_enable(unsigned char enable); - -/* Hardware registers needed by driver. */ -struct gyro_reg_s { - unsigned char who_am_i; - unsigned char rate_div; - unsigned char lpf; - unsigned char prod_id; - unsigned char user_ctrl; - unsigned char fifo_en; - unsigned char gyro_cfg; - unsigned char accel_cfg; - unsigned char accel_cfg2; - unsigned char lp_accel_odr; - unsigned char motion_thr; - unsigned char motion_dur; - unsigned char fifo_count_h; - unsigned char fifo_r_w; - unsigned char raw_gyro; - unsigned char raw_accel; - unsigned char temp; - unsigned char int_enable; - unsigned char dmp_int_status; - unsigned char int_status; - unsigned char accel_intel; - unsigned char pwr_mgmt_1; - unsigned char pwr_mgmt_2; - unsigned char int_pin_cfg; - unsigned char mem_r_w; - unsigned char accel_offs; - unsigned char i2c_mst; - unsigned char bank_sel; - unsigned char mem_start_addr; - unsigned char prgm_start_h; -#if defined AK89xx_SECONDARY - unsigned char s0_addr; - unsigned char s0_reg; - unsigned char s0_ctrl; - unsigned char s1_addr; - unsigned char s1_reg; - unsigned char s1_ctrl; - unsigned char s4_ctrl; - unsigned char s0_do; - unsigned char s1_do; - unsigned char i2c_delay_ctrl; - unsigned char raw_compass; - /* The I2C_MST_VDDIO bit is in this register. */ - unsigned char yg_offs_tc; -#endif -}; - -/* Information specific to a particular device. */ -struct hw_s { - unsigned char addr; - unsigned short max_fifo; - unsigned char num_reg; - unsigned short temp_sens; - short temp_offset; - unsigned short bank_size; -#if defined AK89xx_SECONDARY - unsigned short compass_fsr; -#endif -}; - -/* When entering motion interrupt mode, the driver keeps track of the - * previous state so that it can be restored at a later time. - * TODO: This is tacky. Fix it. - */ -struct motion_int_cache_s { - unsigned short gyro_fsr; - unsigned char accel_fsr; - unsigned short lpf; - unsigned short sample_rate; - unsigned char sensors_on; - unsigned char fifo_sensors; - unsigned char dmp_on; -}; - -/* Cached chip configuration data. - * TODO: A lot of these can be handled with a bitmask. - */ -struct chip_cfg_s { - /* Matches gyro_cfg >> 3 & 0x03 */ - unsigned char gyro_fsr; - /* Matches accel_cfg >> 3 & 0x03 */ - unsigned char accel_fsr; - /* Enabled sensors. Uses same masks as fifo_en, NOT pwr_mgmt_2. */ - unsigned char sensors; - /* Matches config register. */ - unsigned char lpf; - unsigned char clk_src; - /* Sample rate, NOT rate divider. */ - unsigned short sample_rate; - /* Matches fifo_en register. */ - unsigned char fifo_enable; - /* Matches int enable register. */ - unsigned char int_enable; - /* 1 if devices on auxiliary I2C bus appear on the primary. */ - unsigned char bypass_mode; - /* 1 if half-sensitivity. - * NOTE: This doesn't belong here, but everything else in hw_s is const, - * and this allows us to save some precious RAM. - */ - unsigned char accel_half; - /* 1 if device in low-power accel-only mode. */ - unsigned char lp_accel_mode; - /* 1 if interrupts are only triggered on motion events. */ - unsigned char int_motion_only; - struct motion_int_cache_s cache; - /* 1 for active low interrupts. */ - unsigned char active_low_int; - /* 1 for latched interrupts. */ - unsigned char latched_int; - /* 1 if DMP is enabled. */ - unsigned char dmp_on; - /* Ensures that DMP will only be loaded once. */ - unsigned char dmp_loaded; - /* Sampling rate used when DMP is enabled. */ - unsigned short dmp_sample_rate; -#ifdef AK89xx_SECONDARY - /* Compass sample rate. */ - unsigned short compass_sample_rate; - unsigned char compass_addr; - short mag_sens_adj[3]; -#endif -}; - -/* Information for self-test. */ -struct test_s { - unsigned long gyro_sens; - unsigned long accel_sens; - unsigned char reg_rate_div; - unsigned char reg_lpf; - unsigned char reg_gyro_fsr; - unsigned char reg_accel_fsr; - unsigned short wait_ms; - unsigned char packet_thresh; - float min_dps; - float max_dps; - float max_gyro_var; - float min_g; - float max_g; - float max_accel_var; -#ifdef MPU6500 - float max_g_offset; - unsigned short sample_wait_ms; -#endif -}; - -/* Gyro driver state variables. */ -struct gyro_state_s { - const struct gyro_reg_s *reg; - const struct hw_s *hw; - struct chip_cfg_s chip_cfg; - const struct test_s *test; -}; - -/* Filter configurations. */ -enum lpf_e { - INV_FILTER_256HZ_NOLPF2 = 0, - INV_FILTER_188HZ, - INV_FILTER_98HZ, - INV_FILTER_42HZ, - INV_FILTER_20HZ, - INV_FILTER_10HZ, - INV_FILTER_5HZ, - INV_FILTER_2100HZ_NOLPF, - NUM_FILTER -}; - -/* Full scale ranges. */ -enum gyro_fsr_e { - INV_FSR_250DPS = 0, - INV_FSR_500DPS, - INV_FSR_1000DPS, - INV_FSR_2000DPS, - NUM_GYRO_FSR -}; - -/* Full scale ranges. */ -enum accel_fsr_e { - INV_FSR_2G = 0, - INV_FSR_4G, - INV_FSR_8G, - INV_FSR_16G, - NUM_ACCEL_FSR -}; - -/* Clock sources. */ -enum clock_sel_e { - INV_CLK_INTERNAL = 0, - INV_CLK_PLL, - NUM_CLK -}; - -/* Low-power accel wakeup rates. */ -enum lp_accel_rate_e { -#if defined MPU6050 - INV_LPA_1_25HZ, - INV_LPA_5HZ, - INV_LPA_20HZ, - INV_LPA_40HZ -#elif defined MPU6500 - INV_LPA_0_24HZ, - INV_LPA_0_49HZ, - INV_LPA_0_98HZ, - INV_LPA_1_95HZ, - INV_LPA_3_91HZ, - INV_LPA_7_81HZ, - INV_LPA_15_63HZ, - INV_LPA_31_25HZ, - INV_LPA_62_50HZ, - INV_LPA_125HZ, - INV_LPA_250HZ, - INV_LPA_500HZ -#endif -}; - -#define BIT_I2C_MST_VDDIO (0x80) -#define BIT_FIFO_EN (0x40) -#define BIT_DMP_EN (0x80) -#define BIT_FIFO_RST (0x04) -#define BIT_DMP_RST (0x08) -#define BIT_FIFO_OVERFLOW (0x10) -#define BIT_DATA_RDY_EN (0x01) -#define BIT_DMP_INT_EN (0x02) -#define BIT_MOT_INT_EN (0x40) -#define BITS_FSR (0x18) -#define BITS_LPF (0x07) -#define BITS_HPF (0x07) -#define BITS_CLK (0x07) -#define BIT_FIFO_SIZE_1024 (0x40) -#define BIT_FIFO_SIZE_2048 (0x80) -#define BIT_FIFO_SIZE_4096 (0xC0) -#define BIT_RESET (0x80) -#define BIT_SLEEP (0x40) -#define BIT_S0_DELAY_EN (0x01) -#define BIT_S2_DELAY_EN (0x04) -#define BITS_SLAVE_LENGTH (0x0F) -#define BIT_SLAVE_BYTE_SW (0x40) -#define BIT_SLAVE_GROUP (0x10) -#define BIT_SLAVE_EN (0x80) -#define BIT_I2C_READ (0x80) -#define BITS_I2C_MASTER_DLY (0x1F) -#define BIT_AUX_IF_EN (0x20) -#define BIT_ACTL (0x80) -#define BIT_LATCH_EN (0x20) -#define BIT_ANY_RD_CLR (0x10) -#define BIT_BYPASS_EN (0x02) -#define BITS_WOM_EN (0xC0) -#define BIT_LPA_CYCLE (0x20) -#define BIT_STBY_XA (0x20) -#define BIT_STBY_YA (0x10) -#define BIT_STBY_ZA (0x08) -#define BIT_STBY_XG (0x04) -#define BIT_STBY_YG (0x02) -#define BIT_STBY_ZG (0x01) -#define BIT_STBY_XYZA (BIT_STBY_XA | BIT_STBY_YA | BIT_STBY_ZA) -#define BIT_STBY_XYZG (BIT_STBY_XG | BIT_STBY_YG | BIT_STBY_ZG) -#define BIT_ACCL_FC_B (0x08) - -#if defined AK8975_SECONDARY -#define SUPPORTS_AK89xx_HIGH_SENS (0x00) -#define AK89xx_FSR (9830) -#elif defined AK8963_SECONDARY -#define SUPPORTS_AK89xx_HIGH_SENS (0x10) -#define AK89xx_FSR (4915) -#endif - -#ifdef AK89xx_SECONDARY -#define AKM_REG_WHOAMI (0x00) - -#define AKM_REG_ST1 (0x02) -#define AKM_REG_HXL (0x03) -#define AKM_REG_ST2 (0x09) - -#define AKM_REG_CNTL (0x0A) -#define AKM_REG_ASTC (0x0C) -#define AKM_REG_ASAX (0x10) -#define AKM_REG_ASAY (0x11) -#define AKM_REG_ASAZ (0x12) - -#define AKM_DATA_READY (0x01) -#define AKM_DATA_OVERRUN (0x02) -#define AKM_OVERFLOW (0x80) -#define AKM_DATA_ERROR (0x40) - -#define AKM_BIT_SELF_TEST (0x40) - -#define AKM_POWER_DOWN (0x00 | SUPPORTS_AK89xx_HIGH_SENS) -#define AKM_SINGLE_MEASUREMENT (0x01 | SUPPORTS_AK89xx_HIGH_SENS) -#define AKM_FUSE_ROM_ACCESS (0x0F | SUPPORTS_AK89xx_HIGH_SENS) -#define AKM_MODE_SELF_TEST (0x08 | SUPPORTS_AK89xx_HIGH_SENS) - -#define AKM_WHOAMI (0x48) -#endif - -#if defined MPU6050 -const struct gyro_reg_s reg = { - .who_am_i = 0x75, - .rate_div = 0x19, - .lpf = 0x1A, - .prod_id = 0x0C, - .user_ctrl = 0x6A, - .fifo_en = 0x23, - .gyro_cfg = 0x1B, - .accel_cfg = 0x1C, - .motion_thr = 0x1F, - .motion_dur = 0x20, - .fifo_count_h = 0x72, - .fifo_r_w = 0x74, - .raw_gyro = 0x43, - .raw_accel = 0x3B, - .temp = 0x41, - .int_enable = 0x38, - .dmp_int_status = 0x39, - .int_status = 0x3A, - .pwr_mgmt_1 = 0x6B, - .pwr_mgmt_2 = 0x6C, - .int_pin_cfg = 0x37, - .mem_r_w = 0x6F, - .accel_offs = 0x06, - .i2c_mst = 0x24, - .bank_sel = 0x6D, - .mem_start_addr = 0x6E, - .prgm_start_h = 0x70 -#ifdef AK89xx_SECONDARY - , .raw_compass = 0x49, - .yg_offs_tc = 0x01, - .s0_addr = 0x25, - .s0_reg = 0x26, - .s0_ctrl = 0x27, - .s1_addr = 0x28, - .s1_reg = 0x29, - .s1_ctrl = 0x2A, - .s4_ctrl = 0x34, - .s0_do = 0x63, - .s1_do = 0x64, - .i2c_delay_ctrl = 0x67 -#endif -}; -const struct hw_s hw = { - .addr = 0x68, - .max_fifo = 1024, - .num_reg = 118, - .temp_sens = 340, - .temp_offset = -521, - .bank_size = 256 -#if defined AK89xx_SECONDARY - , .compass_fsr = AK89xx_FSR -#endif -}; - -const struct test_s test = { - .gyro_sens = 32768 / 250, - .accel_sens = 32768 / 16, - .reg_rate_div = 0, /* 1kHz. */ - .reg_lpf = 1, /* 188Hz. */ - .reg_gyro_fsr = 0, /* 250dps. */ - .reg_accel_fsr = 0x18, /* 16g. */ - .wait_ms = 50, - .packet_thresh = 5, /* 5% */ - .min_dps = 10.f, - .max_dps = 105.f, - .max_gyro_var = 0.14f, - .min_g = 0.3f, - .max_g = 0.95f, - .max_accel_var = 0.14f -}; - -static struct gyro_state_s st = { - .reg = ®, - .hw = &hw, - .test = &test -}; -#elif defined MPU6500 -const struct gyro_reg_s reg = { - .who_am_i = 0x75, - .rate_div = 0x19, - .lpf = 0x1A, - .prod_id = 0x0C, - .user_ctrl = 0x6A, - .fifo_en = 0x23, - .gyro_cfg = 0x1B, - .accel_cfg = 0x1C, - .accel_cfg2 = 0x1D, - .lp_accel_odr = 0x1E, - .motion_thr = 0x1F, - .motion_dur = 0x20, - .fifo_count_h = 0x72, - .fifo_r_w = 0x74, - .raw_gyro = 0x43, - .raw_accel = 0x3B, - .temp = 0x41, - .int_enable = 0x38, - .dmp_int_status = 0x39, - .int_status = 0x3A, - .accel_intel = 0x69, - .pwr_mgmt_1 = 0x6B, - .pwr_mgmt_2 = 0x6C, - .int_pin_cfg = 0x37, - .mem_r_w = 0x6F, - .accel_offs = 0x77, - .i2c_mst = 0x24, - .bank_sel = 0x6D, - .mem_start_addr = 0x6E, - .prgm_start_h = 0x70 -#ifdef AK89xx_SECONDARY - , .raw_compass = 0x49, - .s0_addr = 0x25, - .s0_reg = 0x26, - .s0_ctrl = 0x27, - .s1_addr = 0x28, - .s1_reg = 0x29, - .s1_ctrl = 0x2A, - .s4_ctrl = 0x34, - .s0_do = 0x63, - .s1_do = 0x64, - .i2c_delay_ctrl = 0x67 -#endif -}; -const struct hw_s hw = { - .addr = 0x68, - .max_fifo = 1024, - .num_reg = 128, - .temp_sens = 321, - .temp_offset = 0, - .bank_size = 256 -#if defined AK89xx_SECONDARY - , .compass_fsr = AK89xx_FSR -#endif -}; - -const struct test_s test = { - .gyro_sens = 32768 / 250, - .accel_sens = 32768 / 2, // FSR = +-2G = 16384 LSB/G - .reg_rate_div = 0, /* 1kHz. */ - .reg_lpf = 2, /* 92Hz low pass filter*/ - .reg_gyro_fsr = 0, /* 250dps. */ - .reg_accel_fsr = 0x0, /* Accel FSR setting = 2g. */ - .wait_ms = 200, // 200ms stabilization time - .packet_thresh = 200, /* 200 samples */ - .min_dps = 20.f, // 20 dps for Gyro Criteria C - .max_dps = 60.f, // Must exceed 60 dps threshold for Gyro Criteria B - .max_gyro_var = .5f, // Must exceed +50% variation for Gyro Criteria A - .min_g = .225f, // Accel must exceed Min 225 mg for Criteria B - .max_g = .675f, // Accel cannot exceed Max 675 mg for Criteria B - .max_accel_var = .5f, // Accel must be within 50% variation for Criteria A - .max_g_offset = .5f, // 500 mg for Accel Criteria C - .sample_wait_ms = 10 // 10ms sample time wait -}; - -static struct gyro_state_s st = { - .reg = ®, - .hw = &hw, - .test = &test -}; -#endif - -#define MAX_PACKET_LENGTH (12) -#ifdef MPU6500 -#define HWST_MAX_PACKET_LENGTH (512) -#endif - -#ifdef AK89xx_SECONDARY -static int setup_compass(void); -#define MAX_COMPASS_SAMPLE_RATE (100) -#endif - -/** - * @brief Enable/disable data ready interrupt. - * If the DMP is on, the DMP interrupt is enabled. Otherwise, the data ready - * interrupt is used. - * @param[in] enable 1 to enable interrupt. - * @return 0 if successful. - */ -static int set_int_enable(unsigned char enable) -{ - unsigned char tmp; - - if (st.chip_cfg.dmp_on) { - if (enable) { - tmp = BIT_DMP_INT_EN; - } else { - tmp = 0x00; - } - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &tmp)) { - return -1; - } - st.chip_cfg.int_enable = tmp; - } else { - if (!st.chip_cfg.sensors) { - return -1; - } - if (enable && st.chip_cfg.int_enable) { - return 0; - } - if (enable) { - tmp = BIT_DATA_RDY_EN; - } else { - tmp = 0x00; - } - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &tmp)) { - return -1; - } - st.chip_cfg.int_enable = tmp; - } - return 0; -} - -/** - * @brief Register dump for testing. - * @return 0 if successful. - */ -int mpu_reg_dump(void) -{ - unsigned char ii; - unsigned char data; - - for (ii = 0; ii < st.hw->num_reg; ii++) { - if (ii == st.reg->fifo_r_w || ii == st.reg->mem_r_w) { - continue; - } - if (i2c_read(st.hw->addr, ii, 1, &data)) { - return -1; - } - log_i("%#5x: %#5x\r\n", ii, data); - } - return 0; -} - -/** - * @brief Read from a single register. - * NOTE: The memory and FIFO read/write registers cannot be accessed. - * @param[in] reg Register address. - * @param[out] data Register data. - * @return 0 if successful. - */ -int mpu_read_reg(unsigned char reg, unsigned char *data) -{ - if (reg == st.reg->fifo_r_w || reg == st.reg->mem_r_w) { - return -1; - } - if (reg >= st.hw->num_reg) { - return -1; - } - return i2c_read(st.hw->addr, reg, 1, data); -} - -/** - * @brief Initialize hardware. - * Initial configuration:\n - * Gyro FSR: +/- 2000DPS\n - * Accel FSR +/- 2G\n - * DLPF: 42Hz\n - * FIFO rate: 50Hz\n - * Clock source: Gyro PLL\n - * FIFO: Disabled.\n - * Data ready interrupt: Disabled, active low, unlatched. - * @param[in] int_param Platform-specific parameters to interrupt API. - * @return 0 if successful. - */ -// int mpu_init(struct int_param_s *int_param) -int mpu_init() -{ - unsigned char data[6]; - - /* Reset device. */ - data[0] = BIT_RESET; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) { - return -1; - } - delay_ms(100); - - /* Wake up chip. */ - data[0] = 0x00; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) { - return -1; - } - - st.chip_cfg.accel_half = 0; - -#ifdef MPU6500 - /* MPU6500 shares 4kB of memory between the DMP and the FIFO. Since the - * first 3kB are needed by the DMP, we'll use the last 1kB for the FIFO. - */ - data[0] = BIT_FIFO_SIZE_1024; - if (i2c_write(st.hw->addr, st.reg->accel_cfg2, 1, data)) { - return -1; - } -#endif - - /* Set to invalid values to ensure no I2C writes are skipped. */ - st.chip_cfg.sensors = 0xFF; - st.chip_cfg.gyro_fsr = 0xFF; - st.chip_cfg.accel_fsr = 0xFF; - st.chip_cfg.lpf = 0xFF; - st.chip_cfg.sample_rate = 0xFFFF; - st.chip_cfg.fifo_enable = 0xFF; - st.chip_cfg.bypass_mode = 0xFF; -#ifdef AK89xx_SECONDARY - st.chip_cfg.compass_sample_rate = 0xFFFF; -#endif - /* mpu_set_sensors always preserves this setting. */ - st.chip_cfg.clk_src = INV_CLK_PLL; - /* Handled in next call to mpu_set_bypass. */ - st.chip_cfg.active_low_int = 1; - st.chip_cfg.latched_int = 0; - st.chip_cfg.int_motion_only = 0; - st.chip_cfg.lp_accel_mode = 0; - memset(&st.chip_cfg.cache, 0, sizeof(st.chip_cfg.cache)); - st.chip_cfg.dmp_on = 0; - st.chip_cfg.dmp_loaded = 0; - st.chip_cfg.dmp_sample_rate = 0; - - if (mpu_set_gyro_fsr(2000)) { - return -1; - } - if (mpu_set_accel_fsr(2)) { - return -1; - } - if (mpu_set_lpf(42)) { - return -1; - } - if (mpu_set_sample_rate(50)) { - return -1; - } - if (mpu_configure_fifo(0)) { - return -1; - } - - // if (int_param) - // reg_int_cb(int_param); - -#ifdef AK89xx_SECONDARY - setup_compass(); - if (mpu_set_compass_sample_rate(10)) { - return -1; - } -#else - /* Already disabled by setup_compass. */ - if (mpu_set_bypass(0)) { - return -1; - } -#endif - - mpu_set_sensors(0); - return 0; -} - -/** - * @brief Enter low-power accel-only mode. - * In low-power accel mode, the chip goes to sleep and only wakes up to sample - * the accelerometer at one of the following frequencies: - * \n MPU6050: 1.25Hz, 5Hz, 20Hz, 40Hz - * \n MPU6500: 0.24Hz, 0.49Hz, 0.98Hz, 1.95Hz, 3.91Hz, 7.81Hz, 15.63Hz, 31.25Hz, 62.5Hz, 125Hz, 250Hz, 500Hz - * \n If the requested rate is not one listed above, the device will be set to - * the next highest rate. Requesting a rate above the maximum supported - * frequency will result in an error. - * \n To select a fractional wake-up frequency, round down the value passed to - * @e rate. - * @param[in] rate Minimum sampling rate, or zero to disable LP - * accel mode. - * @return 0 if successful. - */ -int mpu_lp_accel_mode(unsigned short rate) -{ - unsigned char tmp[2]; - -#if defined MPU6500 - unsigned char data; -#endif - - if (!rate) { - mpu_set_int_latched(0); - tmp[0] = 0; - tmp[1] = BIT_STBY_XYZG; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, tmp)) { - return -1; - } - st.chip_cfg.lp_accel_mode = 0; - return 0; - } - /* For LP accel, we automatically configure the hardware to produce latched - * interrupts. In LP accel mode, the hardware cycles into sleep mode before - * it gets a chance to deassert the interrupt pin; therefore, we shift this - * responsibility over to the MCU. - * - * Any register read will clear the interrupt. - */ - mpu_set_int_latched(1); -#if defined MPU6050 - tmp[0] = BIT_LPA_CYCLE; - if (rate == 1) { - tmp[1] = INV_LPA_1_25HZ; - mpu_set_lpf(5); - } else if (rate <= 5) { - tmp[1] = INV_LPA_5HZ; - mpu_set_lpf(5); - } else if (rate <= 20) { - tmp[1] = INV_LPA_20HZ; - mpu_set_lpf(10); - } else { - tmp[1] = INV_LPA_40HZ; - mpu_set_lpf(20); - } - tmp[1] = (tmp[1] << 6) | BIT_STBY_XYZG; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, tmp)) { - return -1; - } -#elif defined MPU6500 - /* Set wake frequency. */ - if (rate == 1) { - data = INV_LPA_0_98HZ; - } else if (rate == 2) { - data = INV_LPA_1_95HZ; - } else if (rate <= 5) { - data = INV_LPA_3_91HZ; - } else if (rate <= 10) { - data = INV_LPA_7_81HZ; - } else if (rate <= 20) { - data = INV_LPA_15_63HZ; - } else if (rate <= 40) { - data = INV_LPA_31_25HZ; - } else if (rate <= 70) { - data = INV_LPA_62_50HZ; - } else if (rate <= 125) { - data = INV_LPA_125HZ; - } else if (rate <= 250) { - data = INV_LPA_250HZ; - } else { - data = INV_LPA_500HZ; - } - - if (i2c_write(st.hw->addr, st.reg->lp_accel_odr, 1, &data)) { - return -1; - } - - if (i2c_read(st.hw->addr, st.reg->accel_cfg2, 1, &data)) { - return -1; - } - - data = data | BIT_ACCL_FC_B; - if (i2c_write(st.hw->addr, st.reg->accel_cfg2, 1, &data)) { - return -1; - } - - data = BIT_LPA_CYCLE; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, &data)) { - return -1; - } -#endif - st.chip_cfg.sensors = INV_XYZ_ACCEL; - st.chip_cfg.clk_src = 0; - st.chip_cfg.lp_accel_mode = 1; - mpu_configure_fifo(0); - - return 0; -} - -/** - * @brief Read raw gyro data directly from the registers. - * @param[out] data Raw data in hardware units. - * @param[out] timestamp Timestamp in milliseconds. Null if not needed. - * @return 0 if successful. - */ -int mpu_get_gyro_reg(short *data, unsigned long *timestamp) -{ - unsigned char tmp[6]; - - if (!(st.chip_cfg.sensors & INV_XYZ_GYRO)) { - return -1; - } - - if (i2c_read(st.hw->addr, st.reg->raw_gyro, 6, tmp)) { - return -1; - } - data[0] = (tmp[0] << 8) | tmp[1]; - data[1] = (tmp[2] << 8) | tmp[3]; - data[2] = (tmp[4] << 8) | tmp[5]; - if (timestamp) { - get_ms(timestamp); - } - return 0; -} - -/** - * @brief Read raw accel data directly from the registers. - * @param[out] data Raw data in hardware units. - * @param[out] timestamp Timestamp in milliseconds. Null if not needed. - * @return 0 if successful. - */ -int mpu_get_accel_reg(short *data, unsigned long *timestamp) -{ - unsigned char tmp[6]; - - if (!(st.chip_cfg.sensors & INV_XYZ_ACCEL)) { - return -1; - } - - if (i2c_read(st.hw->addr, st.reg->raw_accel, 6, tmp)) { - return -1; - } - data[0] = (tmp[0] << 8) | tmp[1]; - data[1] = (tmp[2] << 8) | tmp[3]; - data[2] = (tmp[4] << 8) | tmp[5]; - if (timestamp) { - get_ms(timestamp); - } - return 0; -} - -/** - * @brief Read temperature data directly from the registers. - * @param[out] data Data in q16 format. - * @param[out] timestamp Timestamp in milliseconds. Null if not needed. - * @return 0 if successful. - */ -int mpu_get_temperature(long *data, unsigned long *timestamp) -{ - unsigned char tmp[2]; - short raw; - - if (!(st.chip_cfg.sensors)) { - return -1; - } - - if (i2c_read(st.hw->addr, st.reg->temp, 2, tmp)) { - return -1; - } - raw = (tmp[0] << 8) | tmp[1]; - if (timestamp) { - get_ms(timestamp); - } - - data[0] = (long)((35 + ((raw - (float)st.hw->temp_offset) / st.hw->temp_sens)) * 65536L); - return 0; -} - -/** - * @brief Read biases to the accel bias 6500 registers. - * This function reads from the MPU6500 accel offset cancellations registers. - * The format are G in +-8G format. The register is initialized with OTP - * factory trim values. - * @param[in] accel_bias returned structure with the accel bias - * @return 0 if successful. - */ -int mpu_read_6500_accel_bias(long *accel_bias) -{ - unsigned char data[6]; - - if (i2c_read(st.hw->addr, 0x77, 2, &data[0])) { - return -1; - } - if (i2c_read(st.hw->addr, 0x7A, 2, &data[2])) { - return -1; - } - if (i2c_read(st.hw->addr, 0x7D, 2, &data[4])) { - return -1; - } - accel_bias[0] = ((long)data[0] << 8) | data[1]; - accel_bias[1] = ((long)data[2] << 8) | data[3]; - accel_bias[2] = ((long)data[4] << 8) | data[5]; - return 0; -} - -/** - * @brief Read biases to the accel bias 6050 registers. - * This function reads from the MPU6050 accel offset cancellations registers. - * The format are G in +-8G format. The register is initialized with OTP - * factory trim values. - * @param[in] accel_bias returned structure with the accel bias - * @return 0 if successful. - */ -int mpu_read_6050_accel_bias(long *accel_bias) -{ - unsigned char data[6]; - - if (i2c_read(st.hw->addr, 0x06, 2, &data[0])) { - return -1; - } - if (i2c_read(st.hw->addr, 0x08, 2, &data[2])) { - return -1; - } - if (i2c_read(st.hw->addr, 0x0A, 2, &data[4])) { - return -1; - } - accel_bias[0] = ((long)data[0] << 8) | data[1]; - accel_bias[1] = ((long)data[2] << 8) | data[3]; - accel_bias[2] = ((long)data[4] << 8) | data[5]; - return 0; -} - -int mpu_read_6500_gyro_bias(long *gyro_bias) -{ - unsigned char data[6]; - - if (i2c_read(st.hw->addr, 0x13, 2, &data[0])) { - return -1; - } - if (i2c_read(st.hw->addr, 0x15, 2, &data[2])) { - return -1; - } - if (i2c_read(st.hw->addr, 0x17, 2, &data[4])) { - return -1; - } - gyro_bias[0] = ((long)data[0] << 8) | data[1]; - gyro_bias[1] = ((long)data[2] << 8) | data[3]; - gyro_bias[2] = ((long)data[4] << 8) | data[5]; - return 0; -} - -/** - * @brief Push biases to the gyro bias 6500/6050 registers. - * This function expects biases relative to the current sensor output, and - * these biases will be added to the factory-supplied values. Bias inputs are LSB - * in +-1000dps format. - * @param[in] gyro_bias New biases. - * @return 0 if successful. - */ -int mpu_set_gyro_bias_reg(long *gyro_bias) -{ - unsigned char data[6] = { 0, 0, 0, 0, 0, 0 }; - long gyro_reg_bias[3] = { 0, 0, 0 }; - int i = 0; - - if (mpu_read_6500_gyro_bias(gyro_reg_bias)) { - return -1; - } - - for (i = 0; i < 3; i++) { - gyro_reg_bias[i] -= gyro_bias[i]; - } - - data[0] = (gyro_reg_bias[0] >> 8) & 0xff; - data[1] = (gyro_reg_bias[0]) & 0xff; - data[2] = (gyro_reg_bias[1] >> 8) & 0xff; - data[3] = (gyro_reg_bias[1]) & 0xff; - data[4] = (gyro_reg_bias[2] >> 8) & 0xff; - data[5] = (gyro_reg_bias[2]) & 0xff; - - if (i2c_write(st.hw->addr, 0x13, 2, &data[0])) { - return -1; - } - if (i2c_write(st.hw->addr, 0x15, 2, &data[2])) { - return -1; - } - if (i2c_write(st.hw->addr, 0x17, 2, &data[4])) { - return -1; - } - return 0; -} - -/** - * @brief Push biases to the accel bias 6050 registers. - * This function expects biases relative to the current sensor output, and - * these biases will be added to the factory-supplied values. Bias inputs are LSB - * in +-8G format. - * @param[in] accel_bias New biases. - * @return 0 if successful. - */ -int mpu_set_accel_bias_6050_reg(const long *accel_bias) -{ - unsigned char data[6] = { 0, 0, 0, 0, 0, 0 }; - long accel_reg_bias[3] = { 0, 0, 0 }; - - if (mpu_read_6050_accel_bias(accel_reg_bias)) { - return -1; - } - - accel_reg_bias[0] -= (accel_bias[0] & ~1); - accel_reg_bias[1] -= (accel_bias[1] & ~1); - accel_reg_bias[2] -= (accel_bias[2] & ~1); - - data[0] = (accel_reg_bias[0] >> 8) & 0xff; - data[1] = (accel_reg_bias[0]) & 0xff; - data[2] = (accel_reg_bias[1] >> 8) & 0xff; - data[3] = (accel_reg_bias[1]) & 0xff; - data[4] = (accel_reg_bias[2] >> 8) & 0xff; - data[5] = (accel_reg_bias[2]) & 0xff; - - if (i2c_write(st.hw->addr, 0x06, 2, &data[0])) { - return -1; - } - if (i2c_write(st.hw->addr, 0x08, 2, &data[2])) { - return -1; - } - if (i2c_write(st.hw->addr, 0x0A, 2, &data[4])) { - return -1; - } - - return 0; -} - -/** - * @brief Push biases to the accel bias 6500 registers. - * This function expects biases relative to the current sensor output, and - * these biases will be added to the factory-supplied values. Bias inputs are LSB - * in +-8G format. - * @param[in] accel_bias New biases. - * @return 0 if successful. - */ -int mpu_set_accel_bias_6500_reg(const long *accel_bias) -{ - unsigned char data[6] = { 0, 0, 0, 0, 0, 0 }; - long accel_reg_bias[3] = { 0, 0, 0 }; - - if (mpu_read_6500_accel_bias(accel_reg_bias)) { - return -1; - } - - // Preserve bit 0 of factory value (for temperature compensation) - accel_reg_bias[0] -= (accel_bias[0] & ~1); - accel_reg_bias[1] -= (accel_bias[1] & ~1); - accel_reg_bias[2] -= (accel_bias[2] & ~1); - - data[0] = (accel_reg_bias[0] >> 8) & 0xff; - data[1] = (accel_reg_bias[0]) & 0xff; - data[2] = (accel_reg_bias[1] >> 8) & 0xff; - data[3] = (accel_reg_bias[1]) & 0xff; - data[4] = (accel_reg_bias[2] >> 8) & 0xff; - data[5] = (accel_reg_bias[2]) & 0xff; - - if (i2c_write(st.hw->addr, 0x77, 2, &data[0])) { - return -1; - } - if (i2c_write(st.hw->addr, 0x7A, 2, &data[2])) { - return -1; - } - if (i2c_write(st.hw->addr, 0x7D, 2, &data[4])) { - return -1; - } - - return 0; -} - -/** - * @brief Reset FIFO read/write pointers. - * @return 0 if successful. - */ -int mpu_reset_fifo(void) -{ - unsigned char data; - - if (!(st.chip_cfg.sensors)) { - return -1; - } - - data = 0; - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, &data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) { - return -1; - } - - if (st.chip_cfg.dmp_on) { - data = BIT_FIFO_RST | BIT_DMP_RST; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) { - return -1; - } - delay_ms(50); - data = BIT_DMP_EN | BIT_FIFO_EN; - if (st.chip_cfg.sensors & INV_XYZ_COMPASS) { - data |= BIT_AUX_IF_EN; - } - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) { - return -1; - } - if (st.chip_cfg.int_enable) { - data = BIT_DMP_INT_EN; - } else { - data = 0; - } - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &data)) { - return -1; - } - data = 0; - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, &data)) { - return -1; - } - } else { - data = BIT_FIFO_RST; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) { - return -1; - } - if (st.chip_cfg.bypass_mode || !(st.chip_cfg.sensors & INV_XYZ_COMPASS)) { - data = BIT_FIFO_EN; - } else { - data = BIT_FIFO_EN | BIT_AUX_IF_EN; - } - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) { - return -1; - } - delay_ms(50); - if (st.chip_cfg.int_enable) { - data = BIT_DATA_RDY_EN; - } else { - data = 0; - } - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, &st.chip_cfg.fifo_enable)) { - return -1; - } - } - return 0; -} - -/** - * @brief Get the gyro full-scale range. - * @param[out] fsr Current full-scale range. - * @return 0 if successful. - */ -int mpu_get_gyro_fsr(unsigned short *fsr) -{ - switch (st.chip_cfg.gyro_fsr) { - case INV_FSR_250DPS: - fsr[0] = 250; - break; - case INV_FSR_500DPS: - fsr[0] = 500; - break; - case INV_FSR_1000DPS: - fsr[0] = 1000; - break; - case INV_FSR_2000DPS: - fsr[0] = 2000; - break; - default: - fsr[0] = 0; - break; - } - return 0; -} - -/** - * @brief Set the gyro full-scale range. - * @param[in] fsr Desired full-scale range. - * @return 0 if successful. - */ -int mpu_set_gyro_fsr(unsigned short fsr) -{ - unsigned char data; - - if (!(st.chip_cfg.sensors)) { - return -1; - } - - switch (fsr) { - case 250: - data = INV_FSR_250DPS << 3; - break; - case 500: - data = INV_FSR_500DPS << 3; - break; - case 1000: - data = INV_FSR_1000DPS << 3; - break; - case 2000: - data = INV_FSR_2000DPS << 3; - break; - default: - return -1; - } - - if (st.chip_cfg.gyro_fsr == (data >> 3)) { - return 0; - } - if (i2c_write(st.hw->addr, st.reg->gyro_cfg, 1, &data)) { - return -1; - } - st.chip_cfg.gyro_fsr = data >> 3; - return 0; -} - -/** - * @brief Get the accel full-scale range. - * @param[out] fsr Current full-scale range. - * @return 0 if successful. - */ -int mpu_get_accel_fsr(unsigned char *fsr) -{ - switch (st.chip_cfg.accel_fsr) { - case INV_FSR_2G: - fsr[0] = 2; - break; - case INV_FSR_4G: - fsr[0] = 4; - break; - case INV_FSR_8G: - fsr[0] = 8; - break; - case INV_FSR_16G: - fsr[0] = 16; - break; - default: - return -1; - } - if (st.chip_cfg.accel_half) { - fsr[0] <<= 1; - } - return 0; -} - -/** - * @brief Set the accel full-scale range. - * @param[in] fsr Desired full-scale range. - * @return 0 if successful. - */ -int mpu_set_accel_fsr(unsigned char fsr) -{ - unsigned char data; - - if (!(st.chip_cfg.sensors)) { - return -1; - } - - switch (fsr) { - case 2: - data = INV_FSR_2G << 3; - break; - case 4: - data = INV_FSR_4G << 3; - break; - case 8: - data = INV_FSR_8G << 3; - break; - case 16: - data = INV_FSR_16G << 3; - break; - default: - return -1; - } - - if (st.chip_cfg.accel_fsr == (data >> 3)) { - return 0; - } - if (i2c_write(st.hw->addr, st.reg->accel_cfg, 1, &data)) { - return -1; - } - st.chip_cfg.accel_fsr = data >> 3; - return 0; -} - -/** - * @brief Get the current DLPF setting. - * @param[out] lpf Current LPF setting. - * 0 if successful. - */ -int mpu_get_lpf(unsigned short *lpf) -{ - switch (st.chip_cfg.lpf) { - case INV_FILTER_188HZ: - lpf[0] = 188; - break; - case INV_FILTER_98HZ: - lpf[0] = 98; - break; - case INV_FILTER_42HZ: - lpf[0] = 42; - break; - case INV_FILTER_20HZ: - lpf[0] = 20; - break; - case INV_FILTER_10HZ: - lpf[0] = 10; - break; - case INV_FILTER_5HZ: - lpf[0] = 5; - break; - case INV_FILTER_256HZ_NOLPF2: - case INV_FILTER_2100HZ_NOLPF: - default: - lpf[0] = 0; - break; - } - return 0; -} - -/** - * @brief Set digital low pass filter. - * The following LPF settings are supported: 188, 98, 42, 20, 10, 5. - * @param[in] lpf Desired LPF setting. - * @return 0 if successful. - */ -int mpu_set_lpf(unsigned short lpf) -{ - unsigned char data; - - if (!(st.chip_cfg.sensors)) { - return -1; - } - - if (lpf >= 188) { - data = INV_FILTER_188HZ; - } else if (lpf >= 98) { - data = INV_FILTER_98HZ; - } else if (lpf >= 42) { - data = INV_FILTER_42HZ; - } else if (lpf >= 20) { - data = INV_FILTER_20HZ; - } else if (lpf >= 10) { - data = INV_FILTER_10HZ; - } else { - data = INV_FILTER_5HZ; - } - - if (st.chip_cfg.lpf == data) { - return 0; - } - - if (i2c_write(st.hw->addr, st.reg->lpf, 1, &data)) { - return -1; - } - -#ifdef MPU6500 // MPU6500 accel/gyro dlpf separately - data = BIT_FIFO_SIZE_1024 | data; - if (i2c_write(st.hw->addr, st.reg->accel_cfg2, 1, &data)) { - return -1; - } -#endif - - st.chip_cfg.lpf = data; - return 0; -} - -/** - * @brief Get sampling rate. - * @param[out] rate Current sampling rate (Hz). - * @return 0 if successful. - */ -int mpu_get_sample_rate(unsigned short *rate) -{ - if (st.chip_cfg.dmp_on) { - return -1; - } else { - rate[0] = st.chip_cfg.sample_rate; - } - return 0; -} - -/** - * @brief Set sampling rate. - * Sampling rate must be between 4Hz and 1kHz. - * @param[in] rate Desired sampling rate (Hz). - * @return 0 if successful. - */ -int mpu_set_sample_rate(unsigned short rate) -{ - unsigned char data; - - if (!(st.chip_cfg.sensors)) { - return -1; - } - - if (st.chip_cfg.dmp_on) { - return -1; - } else { - if (st.chip_cfg.lp_accel_mode) { - if (rate && (rate <= 40)) { - /* Just stay in low-power accel mode. */ - mpu_lp_accel_mode(rate); - return 0; - } - /* Requested rate exceeds the allowed frequencies in LP accel mode, - * switch back to full-power mode. - */ - mpu_lp_accel_mode(0); - } - if (rate < 4) { - rate = 4; - } else if (rate > 1000) { - rate = 1000; - } - - data = 1000 / rate - 1; - if (i2c_write(st.hw->addr, st.reg->rate_div, 1, &data)) { - return -1; - } - - st.chip_cfg.sample_rate = 1000 / (1 + data); - -#ifdef AK89xx_SECONDARY - mpu_set_compass_sample_rate(min(st.chip_cfg.compass_sample_rate, MAX_COMPASS_SAMPLE_RATE)); -#endif - - /* Automatically set LPF to 1/2 sampling rate. */ - mpu_set_lpf(st.chip_cfg.sample_rate >> 1); - return 0; - } -} - -/** - * @brief Get compass sampling rate. - * @param[out] rate Current compass sampling rate (Hz). - * @return 0 if successful. - */ -int mpu_get_compass_sample_rate(unsigned short *rate) -{ -#ifdef AK89xx_SECONDARY - rate[0] = st.chip_cfg.compass_sample_rate; - return 0; -#else - rate[0] = 0; - return -1; -#endif -} - -/** - * @brief Set compass sampling rate. - * The compass on the auxiliary I2C bus is read by the MPU hardware at a - * maximum of 100Hz. The actual rate can be set to a fraction of the gyro - * sampling rate. - * - * \n WARNING: The new rate may be different than what was requested. Call - * mpu_get_compass_sample_rate to check the actual setting. - * @param[in] rate Desired compass sampling rate (Hz). - * @return 0 if successful. - */ -int mpu_set_compass_sample_rate(unsigned short rate) -{ -#ifdef AK89xx_SECONDARY - unsigned char div; - if (!rate || rate > st.chip_cfg.sample_rate || rate > MAX_COMPASS_SAMPLE_RATE) { - return -1; - } - - div = st.chip_cfg.sample_rate / rate - 1; - if (i2c_write(st.hw->addr, st.reg->s4_ctrl, 1, &div)) { - return -1; - } - st.chip_cfg.compass_sample_rate = st.chip_cfg.sample_rate / (div + 1); - return 0; -#else - return -1; -#endif -} - -/** - * @brief Get gyro sensitivity scale factor. - * @param[out] sens Conversion from hardware units to dps. - * @return 0 if successful. - */ -int mpu_get_gyro_sens(float *sens) -{ - switch (st.chip_cfg.gyro_fsr) { - case INV_FSR_250DPS: - sens[0] = 131.f; - break; - case INV_FSR_500DPS: - sens[0] = 65.5f; - break; - case INV_FSR_1000DPS: - sens[0] = 32.8f; - break; - case INV_FSR_2000DPS: - sens[0] = 16.4f; - break; - default: - return -1; - } - return 0; -} - -/** - * @brief Get accel sensitivity scale factor. - * @param[out] sens Conversion from hardware units to g's. - * @return 0 if successful. - */ -int mpu_get_accel_sens(unsigned short *sens) -{ - switch (st.chip_cfg.accel_fsr) { - case INV_FSR_2G: - sens[0] = 16384; - break; - case INV_FSR_4G: - sens[0] = 8092; - break; - case INV_FSR_8G: - sens[0] = 4096; - break; - case INV_FSR_16G: - sens[0] = 2048; - break; - default: - return -1; - } - if (st.chip_cfg.accel_half) { - sens[0] >>= 1; - } - return 0; -} - -/** - * @brief Get current FIFO configuration. - * @e sensors can contain a combination of the following flags: - * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO - * \n INV_XYZ_GYRO - * \n INV_XYZ_ACCEL - * @param[out] sensors Mask of sensors in FIFO. - * @return 0 if successful. - */ -int mpu_get_fifo_config(unsigned char *sensors) -{ - sensors[0] = st.chip_cfg.fifo_enable; - return 0; -} - -/** - * @brief Select which sensors are pushed to FIFO. - * @e sensors can contain a combination of the following flags: - * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO - * \n INV_XYZ_GYRO - * \n INV_XYZ_ACCEL - * @param[in] sensors Mask of sensors to push to FIFO. - * @return 0 if successful. - */ -int mpu_configure_fifo(unsigned char sensors) -{ - unsigned char prev; - int result = 0; - - /* Compass data isn't going into the FIFO. Stop trying. */ - sensors &= ~INV_XYZ_COMPASS; - - if (st.chip_cfg.dmp_on) { - return 0; - } else { - if (!(st.chip_cfg.sensors)) { - return -1; - } - prev = st.chip_cfg.fifo_enable; - st.chip_cfg.fifo_enable = sensors & st.chip_cfg.sensors; - if (st.chip_cfg.fifo_enable != sensors) { - /* You're not getting what you asked for. Some sensors are - * asleep. - */ - result = -1; - } else { - result = 0; - } - if (sensors || st.chip_cfg.lp_accel_mode) { - set_int_enable(1); - } else { - set_int_enable(0); - } - if (sensors) { - if (mpu_reset_fifo()) { - st.chip_cfg.fifo_enable = prev; - return -1; - } - } - } - - return result; -} - -/** - * @brief Get current power state. - * @param[in] power_on 1 if turned on, 0 if suspended. - * @return 0 if successful. - */ -int mpu_get_power_state(unsigned char *power_on) -{ - if (st.chip_cfg.sensors) { - power_on[0] = 1; - } else { - power_on[0] = 0; - } - return 0; -} - -/** - * @brief Turn specific sensors on/off. - * @e sensors can contain a combination of the following flags: - * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO - * \n INV_XYZ_GYRO - * \n INV_XYZ_ACCEL - * \n INV_XYZ_COMPASS - * @param[in] sensors Mask of sensors to wake. - * @return 0 if successful. - */ -int mpu_set_sensors(unsigned char sensors) -{ - unsigned char data; - -#ifdef AK89xx_SECONDARY - unsigned char user_ctrl; -#endif - - if (sensors & INV_XYZ_GYRO) { - data = INV_CLK_PLL; - } else if (sensors) { - data = 0; - } else { - data = BIT_SLEEP; - } - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, &data)) { - st.chip_cfg.sensors = 0; - return -1; - } - st.chip_cfg.clk_src = data & ~BIT_SLEEP; - - data = 0; - if (!(sensors & INV_X_GYRO)) { - data |= BIT_STBY_XG; - } - if (!(sensors & INV_Y_GYRO)) { - data |= BIT_STBY_YG; - } - if (!(sensors & INV_Z_GYRO)) { - data |= BIT_STBY_ZG; - } - if (!(sensors & INV_XYZ_ACCEL)) { - data |= BIT_STBY_XYZA; - } - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_2, 1, &data)) { - st.chip_cfg.sensors = 0; - return -1; - } - - if (sensors && (sensors != INV_XYZ_ACCEL)) { - /* Latched interrupts only used in LP accel mode. */ - mpu_set_int_latched(0); - } - -#ifdef AK89xx_SECONDARY -#ifdef AK89xx_BYPASS - if (sensors & INV_XYZ_COMPASS) { - mpu_set_bypass(1); - } else { - mpu_set_bypass(0); - } -#else - if (i2c_read(st.hw->addr, st.reg->user_ctrl, 1, &user_ctrl)) { - return -1; - } - /* Handle AKM power management. */ - if (sensors & INV_XYZ_COMPASS) { - data = AKM_SINGLE_MEASUREMENT; - user_ctrl |= BIT_AUX_IF_EN; - } else { - data = AKM_POWER_DOWN; - user_ctrl &= ~BIT_AUX_IF_EN; - } - if (st.chip_cfg.dmp_on) { - user_ctrl |= BIT_DMP_EN; - } else { - user_ctrl &= ~BIT_DMP_EN; - } - if (i2c_write(st.hw->addr, st.reg->s1_do, 1, &data)) { - return -1; - } - /* Enable/disable I2C master mode. */ - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &user_ctrl)) { - return -1; - } -#endif -#endif - - st.chip_cfg.sensors = sensors; - st.chip_cfg.lp_accel_mode = 0; - delay_ms(50); - return 0; -} - -/** - * @brief Read the MPU interrupt status registers. - * @param[out] status Mask of interrupt bits. - * @return 0 if successful. - */ -int mpu_get_int_status(short *status) -{ - unsigned char tmp[2]; - - if (!st.chip_cfg.sensors) { - return -1; - } - if (i2c_read(st.hw->addr, st.reg->dmp_int_status, 2, tmp)) { - return -1; - } - status[0] = (tmp[0] << 8) | tmp[1]; - return 0; -} - -/** - * @brief Get one packet from the FIFO. - * If @e sensors does not contain a particular sensor, disregard the data - * returned to that pointer. - * \n @e sensors can contain a combination of the following flags: - * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO - * \n INV_XYZ_GYRO - * \n INV_XYZ_ACCEL - * \n If the FIFO has no new data, @e sensors will be zero. - * \n If the FIFO is disabled, @e sensors will be zero and this function will - * return a non-zero error code. - * @param[out] gyro Gyro data in hardware units. - * @param[out] accel Accel data in hardware units. - * @param[out] timestamp Timestamp in milliseconds. - * @param[out] sensors Mask of sensors read from FIFO. - * @param[out] more Number of remaining packets. - * @return 0 if successful. - */ -int mpu_read_fifo(short *gyro, short *accel, unsigned long *timestamp, - unsigned char *sensors, unsigned char *more) -{ - /* Assumes maximum packet size is gyro (6) + accel (6). */ - unsigned char data[MAX_PACKET_LENGTH]; - unsigned char packet_size = 0; - unsigned short fifo_count, index = 0; - - if (st.chip_cfg.dmp_on) { - return -1; - } - - sensors[0] = 0; - if (!st.chip_cfg.sensors) { - return -1; - } - if (!st.chip_cfg.fifo_enable) { - return -1; - } - - if (st.chip_cfg.fifo_enable & INV_X_GYRO) { - packet_size += 2; - } - if (st.chip_cfg.fifo_enable & INV_Y_GYRO) { - packet_size += 2; - } - if (st.chip_cfg.fifo_enable & INV_Z_GYRO) { - packet_size += 2; - } - if (st.chip_cfg.fifo_enable & INV_XYZ_ACCEL) { - packet_size += 6; - } - - if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, data)) { - return -1; - } - fifo_count = (data[0] << 8) | data[1]; - if (fifo_count < packet_size) { - return 0; - } -// log_i("FIFO count: %hd\n", fifo_count); - if (fifo_count > (st.hw->max_fifo >> 1)) { - /* FIFO is 50% full, better check overflow bit. */ - if (i2c_read(st.hw->addr, st.reg->int_status, 1, data)) { - return -1; - } - if (data[0] & BIT_FIFO_OVERFLOW) { - mpu_reset_fifo(); - return -2; - } - } - get_ms((unsigned long *)timestamp); - - if (i2c_read(st.hw->addr, st.reg->fifo_r_w, packet_size, data)) { - return -1; - } - more[0] = fifo_count / packet_size - 1; - sensors[0] = 0; - - if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_XYZ_ACCEL) { - accel[0] = (data[index + 0] << 8) | data[index + 1]; - accel[1] = (data[index + 2] << 8) | data[index + 3]; - accel[2] = (data[index + 4] << 8) | data[index + 5]; - sensors[0] |= INV_XYZ_ACCEL; - index += 6; - } - if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_X_GYRO) { - gyro[0] = (data[index + 0] << 8) | data[index + 1]; - sensors[0] |= INV_X_GYRO; - index += 2; - } - if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_Y_GYRO) { - gyro[1] = (data[index + 0] << 8) | data[index + 1]; - sensors[0] |= INV_Y_GYRO; - index += 2; - } - if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_Z_GYRO) { - gyro[2] = (data[index + 0] << 8) | data[index + 1]; - sensors[0] |= INV_Z_GYRO; - index += 2; - } - - return 0; -} - -/** - * @brief Get one unparsed packet from the FIFO. - * This function should be used if the packet is to be parsed elsewhere. - * @param[in] length Length of one FIFO packet. - * @param[in] data FIFO packet. - * @param[in] more Number of remaining packets. - */ -int mpu_read_fifo_stream(unsigned short length, unsigned char *data, - unsigned char *more) -{ - unsigned char tmp[2]; - unsigned short fifo_count; - - if (!st.chip_cfg.dmp_on) { - return -1; - } - if (!st.chip_cfg.sensors) { - return -1; - } - - if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, tmp)) { - return -1; - } - fifo_count = (tmp[0] << 8) | tmp[1]; - if (fifo_count < length) { - more[0] = 0; - return -1; - } - if (fifo_count > (st.hw->max_fifo >> 1)) { - /* FIFO is 50% full, better check overflow bit. */ - if (i2c_read(st.hw->addr, st.reg->int_status, 1, tmp)) { - return -1; - } - if (tmp[0] & BIT_FIFO_OVERFLOW) { - mpu_reset_fifo(); - return -2; - } - } - - if (i2c_read(st.hw->addr, st.reg->fifo_r_w, length, data)) { - return -1; - } - more[0] = fifo_count / length - 1; - return 0; -} - -/** - * @brief Set device to bypass mode. - * @param[in] bypass_on 1 to enable bypass mode. - * @return 0 if successful. - */ -int mpu_set_bypass(unsigned char bypass_on) -{ - unsigned char tmp; - - if (st.chip_cfg.bypass_mode == bypass_on) { - return 0; - } - - if (bypass_on) { - if (i2c_read(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) { - return -1; - } - tmp &= ~BIT_AUX_IF_EN; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) { - return -1; - } - delay_ms(3); - tmp = BIT_BYPASS_EN; - if (st.chip_cfg.active_low_int) { - tmp |= BIT_ACTL; - } - if (st.chip_cfg.latched_int) { - tmp |= BIT_LATCH_EN | BIT_ANY_RD_CLR; - } - if (i2c_write(st.hw->addr, st.reg->int_pin_cfg, 1, &tmp)) { - return -1; - } - } else { - /* Enable I2C master mode if compass is being used. */ - if (i2c_read(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) { - return -1; - } - if (st.chip_cfg.sensors & INV_XYZ_COMPASS) { - tmp |= BIT_AUX_IF_EN; - } else { - tmp &= ~BIT_AUX_IF_EN; - } - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) { - return -1; - } - delay_ms(3); - if (st.chip_cfg.active_low_int) { - tmp = BIT_ACTL; - } else { - tmp = 0; - } - if (st.chip_cfg.latched_int) { - tmp |= BIT_LATCH_EN | BIT_ANY_RD_CLR; - } - if (i2c_write(st.hw->addr, st.reg->int_pin_cfg, 1, &tmp)) { - return -1; - } - } - st.chip_cfg.bypass_mode = bypass_on; - return 0; -} - -/** - * @brief Set interrupt level. - * @param[in] active_low 1 for active low, 0 for active high. - * @return 0 if successful. - */ -int mpu_set_int_level(unsigned char active_low) -{ - st.chip_cfg.active_low_int = active_low; - return 0; -} - -/** - * @brief Enable latched interrupts. - * Any MPU register will clear the interrupt. - * @param[in] enable 1 to enable, 0 to disable. - * @return 0 if successful. - */ -int mpu_set_int_latched(unsigned char enable) -{ - unsigned char tmp; - - if (st.chip_cfg.latched_int == enable) { - return 0; - } - - if (enable) { - tmp = BIT_LATCH_EN | BIT_ANY_RD_CLR; - } else { - tmp = 0; - } - if (st.chip_cfg.bypass_mode) { - tmp |= BIT_BYPASS_EN; - } - if (st.chip_cfg.active_low_int) { - tmp |= BIT_ACTL; - } - if (i2c_write(st.hw->addr, st.reg->int_pin_cfg, 1, &tmp)) { - return -1; - } - st.chip_cfg.latched_int = enable; - return 0; -} - -#ifdef MPU6050 -static int get_accel_prod_shift(float *st_shift) -{ - unsigned char tmp[4], shift_code[3], ii; - - if (i2c_read(st.hw->addr, 0x0D, 4, tmp)) { - return 0x07; - } - - shift_code[0] = ((tmp[0] & 0xE0) >> 3) | ((tmp[3] & 0x30) >> 4); - shift_code[1] = ((tmp[1] & 0xE0) >> 3) | ((tmp[3] & 0x0C) >> 2); - shift_code[2] = ((tmp[2] & 0xE0) >> 3) | (tmp[3] & 0x03); - for (ii = 0; ii < 3; ii++) { - if (!shift_code[ii]) { - st_shift[ii] = 0.f; - continue; - } - /* Equivalent to.. - * st_shift[ii] = 0.34f * powf(0.92f/0.34f, (shift_code[ii]-1) / 30.f) - */ - st_shift[ii] = 0.34f; - while (--shift_code[ii]) { - st_shift[ii] *= 1.034f; - } - } - return 0; -} - -static int accel_self_test(long *bias_regular, long *bias_st) -{ - int jj, result = 0; - float st_shift[3], st_shift_cust, st_shift_var; - - get_accel_prod_shift(st_shift); - for (jj = 0; jj < 3; jj++) { - st_shift_cust = labs(bias_regular[jj] - bias_st[jj]) / 65536.f; - if (st_shift[jj]) { - st_shift_var = st_shift_cust / st_shift[jj] - 1.f; - if (fabs(st_shift_var) > test.max_accel_var) { - result |= 1 << jj; - } - } else if ((st_shift_cust < test.min_g) || - (st_shift_cust > test.max_g)) { - result |= 1 << jj; - } - } - - return result; -} - -static int gyro_self_test(long *bias_regular, long *bias_st) -{ - int jj, result = 0; - unsigned char tmp[3]; - float st_shift, st_shift_cust, st_shift_var; - - if (i2c_read(st.hw->addr, 0x0D, 3, tmp)) { - return 0x07; - } - - tmp[0] &= 0x1F; - tmp[1] &= 0x1F; - tmp[2] &= 0x1F; - - for (jj = 0; jj < 3; jj++) { - st_shift_cust = labs(bias_regular[jj] - bias_st[jj]) / 65536.f; - if (tmp[jj]) { - st_shift = 3275.f / test.gyro_sens; - while (--tmp[jj]) { - st_shift *= 1.046f; - } - st_shift_var = st_shift_cust / st_shift - 1.f; - if (fabs(st_shift_var) > test.max_gyro_var) { - result |= 1 << jj; - } - } else if ((st_shift_cust < test.min_dps) || - (st_shift_cust > test.max_dps)) { - result |= 1 << jj; - } - } - return result; -} - -#endif -#ifdef AK89xx_SECONDARY -static int compass_self_test(void) -{ - unsigned char tmp[6]; - unsigned char tries = 10; - int result = 0x07; - short data; - - mpu_set_bypass(1); - - tmp[0] = AKM_POWER_DOWN; - if (i2c_write(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp)) { - return 0x07; - } - tmp[0] = AKM_BIT_SELF_TEST; - if (i2c_write(st.chip_cfg.compass_addr, AKM_REG_ASTC, 1, tmp)) { - goto AKM_restore; - } - tmp[0] = AKM_MODE_SELF_TEST; - if (i2c_write(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp)) { - goto AKM_restore; - } - - do { - delay_ms(10); - if (i2c_read(st.chip_cfg.compass_addr, AKM_REG_ST1, 1, tmp)) { - goto AKM_restore; - } - if (tmp[0] & AKM_DATA_READY) { - break; - } - } while (tries--); - if (!(tmp[0] & AKM_DATA_READY)) { - goto AKM_restore; - } - - if (i2c_read(st.chip_cfg.compass_addr, AKM_REG_HXL, 6, tmp)) { - goto AKM_restore; - } - - result = 0; -#if defined MPU9150 - data = (short)(tmp[1] << 8) | tmp[0]; - if ((data > 100) || (data < -100)) { - result |= 0x01; - } - data = (short)(tmp[3] << 8) | tmp[2]; - if ((data > 100) || (data < -100)) { - result |= 0x02; - } - data = (short)(tmp[5] << 8) | tmp[4]; - if ((data > -300) || (data < -1000)) { - result |= 0x04; - } -#elif defined MPU9250 - data = (short)(tmp[1] << 8) | tmp[0]; - if ((data > 200) || (data < -200)) { - result |= 0x01; - } - data = (short)(tmp[3] << 8) | tmp[2]; - if ((data > 200) || (data < -200)) { - result |= 0x02; - } - data = (short)(tmp[5] << 8) | tmp[4]; - if ((data > -800) || (data < -3200)) { - result |= 0x04; - } -#endif -AKM_restore: - tmp[0] = 0 | SUPPORTS_AK89xx_HIGH_SENS; - i2c_write(st.chip_cfg.compass_addr, AKM_REG_ASTC, 1, tmp); - tmp[0] = SUPPORTS_AK89xx_HIGH_SENS; - i2c_write(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp); - mpu_set_bypass(0); - return result; -} -#endif - -static int get_st_biases(long *gyro, long *accel, unsigned char hw_test) -{ - unsigned char data[MAX_PACKET_LENGTH]; - unsigned char packet_count, ii; - unsigned short fifo_count; - - data[0] = 0x01; - data[1] = 0; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, data)) { - return -1; - } - delay_ms(200); - data[0] = 0; - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->i2c_mst, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) { - return -1; - } - data[0] = BIT_FIFO_RST | BIT_DMP_RST; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) { - return -1; - } - delay_ms(15); - data[0] = st.test->reg_lpf; - if (i2c_write(st.hw->addr, st.reg->lpf, 1, data)) { - return -1; - } - data[0] = st.test->reg_rate_div; - if (i2c_write(st.hw->addr, st.reg->rate_div, 1, data)) { - return -1; - } - if (hw_test) { - data[0] = st.test->reg_gyro_fsr | 0xE0; - } else { - data[0] = st.test->reg_gyro_fsr; - } - if (i2c_write(st.hw->addr, st.reg->gyro_cfg, 1, data)) { - return -1; - } - - if (hw_test) { - data[0] = st.test->reg_accel_fsr | 0xE0; - } else { - data[0] = test.reg_accel_fsr; - } - if (i2c_write(st.hw->addr, st.reg->accel_cfg, 1, data)) { - return -1; - } - if (hw_test) { - delay_ms(200); - } - - /* Fill FIFO for test.wait_ms milliseconds. */ - data[0] = BIT_FIFO_EN; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) { - return -1; - } - - data[0] = INV_XYZ_GYRO | INV_XYZ_ACCEL; - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) { - return -1; - } - delay_ms(test.wait_ms); - data[0] = 0; - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) { - return -1; - } - - if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, data)) { - return -1; - } - - fifo_count = (data[0] << 8) | data[1]; - packet_count = fifo_count / MAX_PACKET_LENGTH; - gyro[0] = gyro[1] = gyro[2] = 0; - accel[0] = accel[1] = accel[2] = 0; - - for (ii = 0; ii < packet_count; ii++) { - short accel_cur[3], gyro_cur[3]; - if (i2c_read(st.hw->addr, st.reg->fifo_r_w, MAX_PACKET_LENGTH, data)) { - return -1; - } - accel_cur[0] = ((short)data[0] << 8) | data[1]; - accel_cur[1] = ((short)data[2] << 8) | data[3]; - accel_cur[2] = ((short)data[4] << 8) | data[5]; - accel[0] += (long)accel_cur[0]; - accel[1] += (long)accel_cur[1]; - accel[2] += (long)accel_cur[2]; - gyro_cur[0] = (((short)data[6] << 8) | data[7]); - gyro_cur[1] = (((short)data[8] << 8) | data[9]); - gyro_cur[2] = (((short)data[10] << 8) | data[11]); - gyro[0] += (long)gyro_cur[0]; - gyro[1] += (long)gyro_cur[1]; - gyro[2] += (long)gyro_cur[2]; - } -#ifdef EMPL_NO_64BIT - gyro[0] = (long)(((float)gyro[0] * 65536.f) / test.gyro_sens / packet_count); - gyro[1] = (long)(((float)gyro[1] * 65536.f) / test.gyro_sens / packet_count); - gyro[2] = (long)(((float)gyro[2] * 65536.f) / test.gyro_sens / packet_count); - if (has_accel) { - accel[0] = (long)(((float)accel[0] * 65536.f) / test.accel_sens / - packet_count); - accel[1] = (long)(((float)accel[1] * 65536.f) / test.accel_sens / - packet_count); - accel[2] = (long)(((float)accel[2] * 65536.f) / test.accel_sens / - packet_count); - /* Don't remove gravity! */ - accel[2] -= 65536L; - } -#else - gyro[0] = (long)(((long long)gyro[0] << 16) / test.gyro_sens / packet_count); - gyro[1] = (long)(((long long)gyro[1] << 16) / test.gyro_sens / packet_count); - gyro[2] = (long)(((long long)gyro[2] << 16) / test.gyro_sens / packet_count); - accel[0] = (long)(((long long)accel[0] << 16) / test.accel_sens / - packet_count); - accel[1] = (long)(((long long)accel[1] << 16) / test.accel_sens / - packet_count); - accel[2] = (long)(((long long)accel[2] << 16) / test.accel_sens / - packet_count); - /* Don't remove gravity! */ - if (accel[2] > 0L) { - accel[2] -= 65536L; - } else { - accel[2] += 65536L; - } -#endif - - return 0; -} - -#ifdef MPU6500 -#define REG_6500_XG_ST_DATA 0x0 -#define REG_6500_XA_ST_DATA 0xD -static const unsigned short mpu_6500_st_tb[256] = { - 2620, 2646, 2672, 2699, 2726, 2753, 2781, 2808, // 7 - 2837, 2865, 2894, 2923, 2952, 2981, 3011, 3041, // 15 - 3072, 3102, 3133, 3165, 3196, 3228, 3261, 3293, // 23 - 3326, 3359, 3393, 3427, 3461, 3496, 3531, 3566, // 31 - 3602, 3638, 3674, 3711, 3748, 3786, 3823, 3862, // 39 - 3900, 3939, 3979, 4019, 4059, 4099, 4140, 4182, // 47 - 4224, 4266, 4308, 4352, 4395, 4439, 4483, 4528, // 55 - 4574, 4619, 4665, 4712, 4759, 4807, 4855, 4903, // 63 - 4953, 5002, 5052, 5103, 5154, 5205, 5257, 5310, // 71 - 5363, 5417, 5471, 5525, 5581, 5636, 5693, 5750, // 79 - 5807, 5865, 5924, 5983, 6043, 6104, 6165, 6226, // 87 - 6289, 6351, 6415, 6479, 6544, 6609, 6675, 6742, // 95 - 6810, 6878, 6946, 7016, 7086, 7157, 7229, 7301, // 103 - 7374, 7448, 7522, 7597, 7673, 7750, 7828, 7906, // 111 - 7985, 8065, 8145, 8227, 8309, 8392, 8476, 8561, // 119 - 8647, 8733, 8820, 8909, 8998, 9088, 9178, 9270, - 9363, 9457, 9551, 9647, 9743, 9841, 9939, 10038, - 10139, 10240, 10343, 10446, 10550, 10656, 10763, 10870, - 10979, 11089, 11200, 11312, 11425, 11539, 11654, 11771, - 11889, 12008, 12128, 12249, 12371, 12495, 12620, 12746, - 12874, 13002, 13132, 13264, 13396, 13530, 13666, 13802, - 13940, 14080, 14221, 14363, 14506, 14652, 14798, 14946, - 15096, 15247, 15399, 15553, 15709, 15866, 16024, 16184, - 16346, 16510, 16675, 16842, 17010, 17180, 17352, 17526, - 17701, 17878, 18057, 18237, 18420, 18604, 18790, 18978, - 19167, 19359, 19553, 19748, 19946, 20145, 20347, 20550, - 20756, 20963, 21173, 21385, 21598, 21814, 22033, 22253, - 22475, 22700, 22927, 23156, 23388, 23622, 23858, 24097, - 24338, 24581, 24827, 25075, 25326, 25579, 25835, 26093, - 26354, 26618, 26884, 27153, 27424, 27699, 27976, 28255, - 28538, 28823, 29112, 29403, 29697, 29994, 30294, 30597, - 30903, 31212, 31524, 31839, 32157, 32479, 32804, 33132 -}; -static int accel_6500_self_test(long *bias_regular, long *bias_st, int debug) -{ - int i, result = 0, otp_value_zero = 0; - float accel_st_al_min, accel_st_al_max; - float st_shift_cust[3], st_shift_ratio[3], ct_shift_prod[3], accel_offset_max; - unsigned char regs[3]; - - if (i2c_read(st.hw->addr, REG_6500_XA_ST_DATA, 3, regs)) { - if (debug) { - log_i("Reading OTP Register Error.\n"); - } - return 0x07; - } - if (debug) { - log_i("Accel OTP:%d, %d, %d\n", regs[0], regs[1], regs[2]); - } - for (i = 0; i < 3; i++) { - if (regs[i] != 0) { - ct_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1]; - ct_shift_prod[i] *= 65536.f; - ct_shift_prod[i] /= test.accel_sens; - } else { - ct_shift_prod[i] = 0; - otp_value_zero = 1; - } - } - if (otp_value_zero == 0) { - if (debug) { - log_i("ACCEL:CRITERIA A\n"); - } - for (i = 0; i < 3; i++) { - st_shift_cust[i] = bias_st[i] - bias_regular[i]; - if (debug) { - log_i("Bias_Shift=%7.4f, Bias_Reg=%7.4f, Bias_HWST=%7.4f\r\n", - st_shift_cust[i] / 1.f, bias_regular[i] / 1.f, - bias_st[i] / 1.f); - log_i("OTP value: %7.4f\r\n", ct_shift_prod[i] / 1.f); - } - - st_shift_ratio[i] = st_shift_cust[i] / ct_shift_prod[i] - 1.f; - - if (debug) { - log_i("ratio=%7.4f, threshold=%7.4f\r\n", st_shift_ratio[i] / 1.f, - test.max_accel_var / 1.f); - } - - if (fabs(st_shift_ratio[i]) > test.max_accel_var) { - if (debug) { - log_i("ACCEL Fail Axis = %d\n", i); - } - result |= 1 << i; // Error condition - } - } - } else { - /* Self Test Pass/Fail Criteria B */ - accel_st_al_min = test.min_g * 65536.f; - accel_st_al_max = test.max_g * 65536.f; - - if (debug) { - log_i("ACCEL:CRITERIA B\r\n"); - log_i("Min MG: %7.4f\r\n", accel_st_al_min / 1.f); - log_i("Max MG: %7.4f\r\n", accel_st_al_max / 1.f); - } - - for (i = 0; i < 3; i++) { - st_shift_cust[i] = bias_st[i] - bias_regular[i]; - - if (debug) { - log_i("Bias_shift=%7.4f, st=%7.4f, reg=%7.4f\n", st_shift_cust[i] / 1.f, bias_st[i] / 1.f, bias_regular[i] / 1.f); - } - if (st_shift_cust[i] < accel_st_al_min || st_shift_cust[i] > accel_st_al_max) { - if (debug) { - log_i("Accel FAIL axis:%d <= 225mg or >= 675mg\n", i); - } - result |= 1 << i; // Error condition - } - } - } - - if (result == 0) { - /* Self Test Pass/Fail Criteria C */ - accel_offset_max = test.max_g_offset * 65536.f; - if (debug) { - log_i("Accel:CRITERIA C: bias less than %7.4f\n", accel_offset_max / 1.f); - } - for (i = 0; i < 3; i++) { - if (labs(bias_regular[i]) > accel_offset_max) { - if (debug) { - log_i("FAILED: Accel axis:%d = %d > 500mg\n", i, bias_regular[i]); - } - result |= 1 << i; // Error condition - } - } - } - - return result; -} - -static int gyro_6500_self_test(long *bias_regular, long *bias_st, int debug) -{ - int i, result = 0, otp_value_zero = 0; - float gyro_st_al_max; - float st_shift_cust[3], st_shift_ratio[3], ct_shift_prod[3], gyro_offset_max; - unsigned char regs[3]; - - if (i2c_read(st.hw->addr, REG_6500_XG_ST_DATA, 3, regs)) { - if (debug) { - log_i("Reading OTP Register Error.\n"); - } - return 0x07; - } - - if (debug) { - log_i("Gyro OTP:%d, %d, %d\r\n", regs[0], regs[1], regs[2]); - } - - for (i = 0; i < 3; i++) { - if (regs[i] != 0) { - ct_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1]; - ct_shift_prod[i] *= 65536.f; - ct_shift_prod[i] /= test.gyro_sens; - } else { - ct_shift_prod[i] = 0; - otp_value_zero = 1; - } - } - - if (otp_value_zero == 0) { - if (debug) { - log_i("GYRO:CRITERIA A\n"); - } - /* Self Test Pass/Fail Criteria A */ - for (i = 0; i < 3; i++) { - st_shift_cust[i] = bias_st[i] - bias_regular[i]; - - if (debug) { - log_i("Bias_Shift=%7.4f, Bias_Reg=%7.4f, Bias_HWST=%7.4f\r\n", - st_shift_cust[i] / 1.f, bias_regular[i] / 1.f, - bias_st[i] / 1.f); - log_i("OTP value: %7.4f\r\n", ct_shift_prod[i] / 1.f); - } - - st_shift_ratio[i] = st_shift_cust[i] / ct_shift_prod[i]; - - if (debug) { - log_i("ratio=%7.4f, threshold=%7.4f\r\n", st_shift_ratio[i] / 1.f, - test.max_gyro_var / 1.f); - } - - if (fabs(st_shift_ratio[i]) < test.max_gyro_var) { - if (debug) { - log_i("Gyro Fail Axis = %d\n", i); - } - result |= 1 << i; // Error condition - } - } - } else { - /* Self Test Pass/Fail Criteria B */ - gyro_st_al_max = test.max_dps * 65536.f; - - if (debug) { - log_i("GYRO:CRITERIA B\r\n"); - log_i("Max DPS: %7.4f\r\n", gyro_st_al_max / 1.f); - } - - for (i = 0; i < 3; i++) { - st_shift_cust[i] = bias_st[i] - bias_regular[i]; - - if (debug) { - log_i("Bias_shift=%7.4f, st=%7.4f, reg=%7.4f\n", st_shift_cust[i] / 1.f, bias_st[i] / 1.f, bias_regular[i] / 1.f); - } - if (st_shift_cust[i] < gyro_st_al_max) { - if (debug) { - log_i("GYRO FAIL axis:%d greater than 60dps\n", i); - } - result |= 1 << i; // Error condition - } - } - } - - if (result == 0) { - /* Self Test Pass/Fail Criteria C */ - gyro_offset_max = test.min_dps * 65536.f; - if (debug) { - log_i("Gyro:CRITERIA C: bias less than %7.4f\n", gyro_offset_max / 1.f); - } - for (i = 0; i < 3; i++) { - if (labs(bias_regular[i]) > gyro_offset_max) { - if (debug) { - log_i("FAILED: Gyro axis:%d = %d > 20dps\n", i, bias_regular[i]); - } - result |= 1 << i; // Error condition - } - } - } - return result; -} - -static int get_st_6500_biases(long *gyro, long *accel, unsigned char hw_test, int debug) -{ - unsigned char data[HWST_MAX_PACKET_LENGTH]; - unsigned char packet_count, ii; - unsigned short fifo_count; - int s = 0, read_size = 0, ind; - - data[0] = 0x01; - data[1] = 0; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, data)) { - return -1; - } - delay_ms(200); - data[0] = 0; - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->i2c_mst, 1, data)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) { - return -1; - } - data[0] = BIT_FIFO_RST | BIT_DMP_RST; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) { - return -1; - } - delay_ms(15); - data[0] = st.test->reg_lpf; - if (i2c_write(st.hw->addr, st.reg->lpf, 1, data)) { - return -1; - } - data[0] = st.test->reg_rate_div; - if (i2c_write(st.hw->addr, st.reg->rate_div, 1, data)) { - return -1; - } - if (hw_test) { - data[0] = st.test->reg_gyro_fsr | 0xE0; - } else { - data[0] = st.test->reg_gyro_fsr; - } - if (i2c_write(st.hw->addr, st.reg->gyro_cfg, 1, data)) { - return -1; - } - - if (hw_test) { - data[0] = st.test->reg_accel_fsr | 0xE0; - } else { - data[0] = test.reg_accel_fsr; - } - if (i2c_write(st.hw->addr, st.reg->accel_cfg, 1, data)) { - return -1; - } - - delay_ms(test.wait_ms); // wait 200ms for sensors to stabilize - - /* Enable FIFO */ - data[0] = BIT_FIFO_EN; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) { - return -1; - } - data[0] = INV_XYZ_GYRO | INV_XYZ_ACCEL; - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) { - return -1; - } - - // initialize the bias return values - gyro[0] = gyro[1] = gyro[2] = 0; - accel[0] = accel[1] = accel[2] = 0; - - if (debug) { - log_i("Starting Bias Loop Reads\n"); - } - - // start reading samples - while (s < test.packet_thresh) { - delay_ms(test.sample_wait_ms); // wait 10ms to fill FIFO - if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, data)) { - return -1; - } - fifo_count = (data[0] << 8) | data[1]; - packet_count = fifo_count / MAX_PACKET_LENGTH; - if ((test.packet_thresh - s) < packet_count) { - packet_count = test.packet_thresh - s; - } - read_size = packet_count * MAX_PACKET_LENGTH; - - // burst read from FIFO - if (i2c_read(st.hw->addr, st.reg->fifo_r_w, read_size, data)) { - return -1; - } - ind = 0; - for (ii = 0; ii < packet_count; ii++) { - short accel_cur[3], gyro_cur[3]; - accel_cur[0] = ((short)data[ind + 0] << 8) | data[ind + 1]; - accel_cur[1] = ((short)data[ind + 2] << 8) | data[ind + 3]; - accel_cur[2] = ((short)data[ind + 4] << 8) | data[ind + 5]; - accel[0] += (long)accel_cur[0]; - accel[1] += (long)accel_cur[1]; - accel[2] += (long)accel_cur[2]; - gyro_cur[0] = (((short)data[ind + 6] << 8) | data[ind + 7]); - gyro_cur[1] = (((short)data[ind + 8] << 8) | data[ind + 9]); - gyro_cur[2] = (((short)data[ind + 10] << 8) | data[ind + 11]); - gyro[0] += (long)gyro_cur[0]; - gyro[1] += (long)gyro_cur[1]; - gyro[2] += (long)gyro_cur[2]; - ind += MAX_PACKET_LENGTH; - } - s += packet_count; - } - - if (debug) { - log_i("Samples: %d\n", s); - } - - // stop FIFO - data[0] = 0; - if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) { - return -1; - } - gyro[0] = (long)(((long long)gyro[0] << 16) / test.gyro_sens / s); - gyro[1] = (long)(((long long)gyro[1] << 16) / test.gyro_sens / s); - gyro[2] = (long)(((long long)gyro[2] << 16) / test.gyro_sens / s); - accel[0] = (long)(((long long)accel[0] << 16) / test.accel_sens / s); - accel[1] = (long)(((long long)accel[1] << 16) / test.accel_sens / s); - accel[2] = (long)(((long long)accel[2] << 16) / test.accel_sens / s); - /* remove gravity from bias calculation */ - if (accel[2] > 0L) { - accel[2] -= 65536L; - } else { - accel[2] += 65536L; - } - - if (debug) { - log_i("Accel offset data HWST bit=%d: %7.4f %7.4f %7.4f\r\n", hw_test, accel[0] / 65536.f, accel[1] / 65536.f, accel[2] / 65536.f); - log_i("Gyro offset data HWST bit=%d: %7.4f %7.4f %7.4f\r\n", hw_test, gyro[0] / 65536.f, gyro[1] / 65536.f, gyro[2] / 65536.f); - } - - return 0; -} -/** - * @brief Trigger gyro/accel/compass self-test for MPU6500/MPU9250 - * On success/error, the self-test returns a mask representing the sensor(s) - * that failed. For each bit, a one (1) represents a "pass" case; conversely, - * a zero (0) indicates a failure. - * - * \n The mask is defined as follows: - * \n Bit 0: Gyro. - * \n Bit 1: Accel. - * \n Bit 2: Compass. - * - * @param[out] gyro Gyro biases in q16 format. - * @param[out] accel Accel biases (if applicable) in q16 format. - * @param[in] debug Debug flag used to print out more detailed logs. Must first set up logging in Motion Driver. - * @return Result mask (see above). - */ -int mpu_run_6500_self_test(long *gyro, long *accel, unsigned char debug) -{ - const unsigned char tries = 2; - long gyro_st[3], accel_st[3]; - unsigned char accel_result, gyro_result; - -#ifdef AK89xx_SECONDARY - unsigned char compass_result; -#endif - int ii; - - int result; - unsigned char accel_fsr, fifo_sensors, sensors_on; - unsigned short gyro_fsr, sample_rate, lpf; - unsigned char dmp_was_on; - - if (debug) { - log_i("Starting MPU6500 HWST!\r\n"); - } - - if (st.chip_cfg.dmp_on) { - mpu_set_dmp_state(0); - dmp_was_on = 1; - } else { - dmp_was_on = 0; - } - - /* Get initial settings. */ - mpu_get_gyro_fsr(&gyro_fsr); - mpu_get_accel_fsr(&accel_fsr); - mpu_get_lpf(&lpf); - mpu_get_sample_rate(&sample_rate); - sensors_on = st.chip_cfg.sensors; - mpu_get_fifo_config(&fifo_sensors); - - if (debug) { - log_i("Retrieving Biases\r\n"); - } - - for (ii = 0; ii < tries; ii++) { - if (!get_st_6500_biases(gyro, accel, 0, debug)) { - break; - } - } - if (ii == tries) { - /* If we reach this point, we most likely encountered an I2C error. - * We'll just report an error for all three sensors. - */ - if (debug) { - log_i("Retrieving Biases Error - possible I2C error\n"); - } - - result = 0; - goto restore; - } - - if (debug) { - log_i("Retrieving ST Biases\n"); - } - - for (ii = 0; ii < tries; ii++) { - if (!get_st_6500_biases(gyro_st, accel_st, 1, debug)) { - break; - } - } - if (ii == tries) { - - if (debug) { - log_i("Retrieving ST Biases Error - possible I2C error\n"); - } - - /* Again, probably an I2C error. */ - result = 0; - goto restore; - } - - accel_result = accel_6500_self_test(accel, accel_st, debug); - if (debug) { - log_i("Accel Self Test Results: %d\n", accel_result); - } - - gyro_result = gyro_6500_self_test(gyro, gyro_st, debug); - if (debug) { - log_i("Gyro Self Test Results: %d\n", gyro_result); - } - - result = 0; - if (!gyro_result) { - result |= 0x01; - } - if (!accel_result) { - result |= 0x02; - } - -#ifdef AK89xx_SECONDARY - compass_result = compass_self_test(); - if (debug) { - log_i("Compass Self Test Results: %d\n", compass_result); - } - if (!compass_result) { - result |= 0x04; - } -#else - result |= 0x04; -#endif -restore: - if (debug) { - log_i("Exiting HWST\n"); - } - /* Set to invalid values to ensure no I2C writes are skipped. */ - st.chip_cfg.gyro_fsr = 0xFF; - st.chip_cfg.accel_fsr = 0xFF; - st.chip_cfg.lpf = 0xFF; - st.chip_cfg.sample_rate = 0xFFFF; - st.chip_cfg.sensors = 0xFF; - st.chip_cfg.fifo_enable = 0xFF; - st.chip_cfg.clk_src = INV_CLK_PLL; - mpu_set_gyro_fsr(gyro_fsr); - mpu_set_accel_fsr(accel_fsr); - mpu_set_lpf(lpf); - mpu_set_sample_rate(sample_rate); - mpu_set_sensors(sensors_on); - mpu_configure_fifo(fifo_sensors); - - if (dmp_was_on) { - mpu_set_dmp_state(1); - } - - return result; -} -#endif -/* - * \n This function must be called with the device either face-up or face-down - * (z-axis is parallel to gravity). - * @param[out] gyro Gyro biases in q16 format. - * @param[out] accel Accel biases (if applicable) in q16 format. - * @return Result mask (see above). - */ -int mpu_run_self_test(long *gyro, long *accel) -{ -#ifdef MPU6050 - const unsigned char tries = 2; - long gyro_st[3], accel_st[3]; - unsigned char accel_result, gyro_result; -#ifdef AK89xx_SECONDARY - unsigned char compass_result; -#endif - int ii; -#endif - int result; - unsigned char accel_fsr, fifo_sensors, sensors_on; - unsigned short gyro_fsr, sample_rate, lpf; - unsigned char dmp_was_on; - - if (st.chip_cfg.dmp_on) { - mpu_set_dmp_state(0); - dmp_was_on = 1; - } else { - dmp_was_on = 0; - } - - /* Get initial settings. */ - mpu_get_gyro_fsr(&gyro_fsr); - mpu_get_accel_fsr(&accel_fsr); - mpu_get_lpf(&lpf); - mpu_get_sample_rate(&sample_rate); - sensors_on = st.chip_cfg.sensors; - mpu_get_fifo_config(&fifo_sensors); - - /* For older chips, the self-test will be different. */ -#if defined MPU6050 - for (ii = 0; ii < tries; ii++) { - if (!get_st_biases(gyro, accel, 0)) { - break; - } - } - if (ii == tries) { - /* If we reach this point, we most likely encountered an I2C error. - * We'll just report an error for all three sensors. - */ - result = 0; - goto restore; - } - for (ii = 0; ii < tries; ii++) { - if (!get_st_biases(gyro_st, accel_st, 1)) { - break; - } - } - if (ii == tries) { - /* Again, probably an I2C error. */ - result = 0; - goto restore; - } - accel_result = accel_self_test(accel, accel_st); - gyro_result = gyro_self_test(gyro, gyro_st); - - result = 0; - if (!gyro_result) { - result |= 0x01; - } - if (!accel_result) { - result |= 0x02; - } - -#ifdef AK89xx_SECONDARY - compass_result = compass_self_test(); - if (!compass_result) { - result |= 0x04; - } -#else - result |= 0x04; -#endif -restore: -#elif defined MPU6500 - /* For now, this function will return a "pass" result for all three sensors - * for compatibility with current test applications. - */ - get_st_biases(gyro, accel, 0); - result = 0x7; -#endif - /* Set to invalid values to ensure no I2C writes are skipped. */ - st.chip_cfg.gyro_fsr = 0xFF; - st.chip_cfg.accel_fsr = 0xFF; - st.chip_cfg.lpf = 0xFF; - st.chip_cfg.sample_rate = 0xFFFF; - st.chip_cfg.sensors = 0xFF; - st.chip_cfg.fifo_enable = 0xFF; - st.chip_cfg.clk_src = INV_CLK_PLL; - mpu_set_gyro_fsr(gyro_fsr); - mpu_set_accel_fsr(accel_fsr); - mpu_set_lpf(lpf); - mpu_set_sample_rate(sample_rate); - mpu_set_sensors(sensors_on); - mpu_configure_fifo(fifo_sensors); - - if (dmp_was_on) { - mpu_set_dmp_state(1); - } - - return result; -} - -/** - * @brief Write to the DMP memory. - * This function prevents I2C writes past the bank boundaries. The DMP memory - * is only accessible when the chip is awake. - * @param[in] mem_addr Memory location (bank << 8 | start address) - * @param[in] length Number of bytes to write. - * @param[in] data Bytes to write to memory. - * @return 0 if successful. - */ -int mpu_write_mem(unsigned short mem_addr, unsigned short length, - unsigned char *data) -{ - unsigned char tmp[2]; - - if (!data) { - return -1; - } - if (!st.chip_cfg.sensors) { - return -1; - } - - tmp[0] = (unsigned char)(mem_addr >> 8); - tmp[1] = (unsigned char)(mem_addr & 0xFF); - - /* Check bank boundaries. */ - if (tmp[1] + length > st.hw->bank_size) { - return -1; - } - - if (i2c_write(st.hw->addr, st.reg->bank_sel, 2, tmp)) { - return -1; - } - if (i2c_write(st.hw->addr, st.reg->mem_r_w, length, data)) { - return -1; - } - return 0; -} - -/** - * @brief Read from the DMP memory. - * This function prevents I2C reads past the bank boundaries. The DMP memory - * is only accessible when the chip is awake. - * @param[in] mem_addr Memory location (bank << 8 | start address) - * @param[in] length Number of bytes to read. - * @param[out] data Bytes read from memory. - * @return 0 if successful. - */ -int mpu_read_mem(unsigned short mem_addr, unsigned short length, - unsigned char *data) -{ - unsigned char tmp[2]; - - if (!data) { - return -1; - } - if (!st.chip_cfg.sensors) { - return -1; - } - - tmp[0] = (unsigned char)(mem_addr >> 8); - tmp[1] = (unsigned char)(mem_addr & 0xFF); - - /* Check bank boundaries. */ - if (tmp[1] + length > st.hw->bank_size) { - return -1; - } - - if (i2c_write(st.hw->addr, st.reg->bank_sel, 2, tmp)) { - return -1; - } - if (i2c_read(st.hw->addr, st.reg->mem_r_w, length, data)) { - return -1; - } - return 0; -} - -/** - * @brief Load and verify DMP image. - * @param[in] length Length of DMP image. - * @param[in] firmware DMP code. - * @param[in] start_addr Starting address of DMP code memory. - * @param[in] sample_rate Fixed sampling rate used when DMP is enabled. - * @return 0 if successful. - */ -int mpu_load_firmware(unsigned short length, const unsigned char *firmware, - unsigned short start_addr, unsigned short sample_rate) -{ - unsigned short ii; - unsigned short this_write; - - /* Must divide evenly into st.hw->bank_size to avoid bank crossings. */ -#define LOAD_CHUNK (16) - unsigned char cur[LOAD_CHUNK], tmp[2]; - - if (st.chip_cfg.dmp_loaded) { - /* DMP should only be loaded once. */ - return -1; - } - - if (!firmware) { - return -1; - } - for (ii = 0; ii < length; ii += this_write) { - this_write = min(LOAD_CHUNK, length - ii); - if (mpu_write_mem(ii, this_write, (unsigned char *)&firmware[ii])) { - return -1; - } - if (mpu_read_mem(ii, this_write, cur)) { - return -1; - } - if (memcmp(firmware + ii, cur, this_write)) { - return -2; - } - } - - /* Set program start address. */ - tmp[0] = start_addr >> 8; - tmp[1] = start_addr & 0xFF; - if (i2c_write(st.hw->addr, st.reg->prgm_start_h, 2, tmp)) { - return -1; - } - - st.chip_cfg.dmp_loaded = 1; - st.chip_cfg.dmp_sample_rate = sample_rate; - return 0; -} - -/** - * @brief Enable/disable DMP support. - * @param[in] enable 1 to turn on the DMP. - * @return 0 if successful. - */ -int mpu_set_dmp_state(unsigned char enable) -{ - unsigned char tmp; - - if (st.chip_cfg.dmp_on == enable) { - return 0; - } - - if (enable) { - if (!st.chip_cfg.dmp_loaded) { - return -1; - } - /* Disable data ready interrupt. */ - set_int_enable(0); - /* Disable bypass mode. */ - mpu_set_bypass(0); - /* Keep constant sample rate, FIFO rate controlled by DMP. */ - mpu_set_sample_rate(st.chip_cfg.dmp_sample_rate); - /* Remove FIFO elements. */ - tmp = 0; - i2c_write(st.hw->addr, 0x23, 1, &tmp); - st.chip_cfg.dmp_on = 1; - /* Enable DMP interrupt. */ - set_int_enable(1); - mpu_reset_fifo(); - } else { - /* Disable DMP interrupt. */ - set_int_enable(0); - /* Restore FIFO settings. */ - tmp = st.chip_cfg.fifo_enable; - i2c_write(st.hw->addr, 0x23, 1, &tmp); - st.chip_cfg.dmp_on = 0; - mpu_reset_fifo(); - } - return 0; -} - -/** - * @brief Get DMP state. - * @param[out] enabled 1 if enabled. - * @return 0 if successful. - */ -int mpu_get_dmp_state(unsigned char *enabled) -{ - enabled[0] = st.chip_cfg.dmp_on; - return 0; -} - -#ifdef AK89xx_SECONDARY -/* This initialization is similar to the one in ak8975.c. */ -static int setup_compass(void) -{ - unsigned char data[4], akm_addr; - - mpu_set_bypass(1); - - /* Find compass. Possible addresses range from 0x0C to 0x0F. */ - for (akm_addr = 0x0C; akm_addr <= 0x0F; akm_addr++) { - int result; - result = i2c_read(akm_addr, AKM_REG_WHOAMI, 1, data); - if (!result && (data[0] == AKM_WHOAMI)) { - break; - } - } - - if (akm_addr > 0x0F) { - /* TODO: Handle this case in all compass-related functions. */ - log_e("Compass not found.\n"); - return -1; - } - - st.chip_cfg.compass_addr = akm_addr; - - data[0] = AKM_POWER_DOWN; - if (i2c_write(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, data)) { - return -1; - } - delay_ms(1); - - data[0] = AKM_FUSE_ROM_ACCESS; - if (i2c_write(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, data)) { - return -1; - } - delay_ms(1); - - /* Get sensitivity adjustment data from fuse ROM. */ - if (i2c_read(st.chip_cfg.compass_addr, AKM_REG_ASAX, 3, data)) { - return -1; - } - st.chip_cfg.mag_sens_adj[0] = (long)data[0] + 128; - st.chip_cfg.mag_sens_adj[1] = (long)data[1] + 128; - st.chip_cfg.mag_sens_adj[2] = (long)data[2] + 128; - - data[0] = AKM_POWER_DOWN; - if (i2c_write(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, data)) { - return -1; - } - delay_ms(1); - - mpu_set_bypass(0); - - /* Set up master mode, master clock, and ES bit. */ - data[0] = 0x40; - if (i2c_write(st.hw->addr, st.reg->i2c_mst, 1, data)) { - return -1; - } - - /* Slave 0 reads from AKM data registers. */ - data[0] = BIT_I2C_READ | st.chip_cfg.compass_addr; - if (i2c_write(st.hw->addr, st.reg->s0_addr, 1, data)) { - return -1; - } - - /* Compass reads start at this register. */ - data[0] = AKM_REG_ST1; - if (i2c_write(st.hw->addr, st.reg->s0_reg, 1, data)) { - return -1; - } - - /* Enable slave 0, 8-byte reads. */ - data[0] = BIT_SLAVE_EN | 8; - if (i2c_write(st.hw->addr, st.reg->s0_ctrl, 1, data)) { - return -1; - } - - /* Slave 1 changes AKM measurement mode. */ - data[0] = st.chip_cfg.compass_addr; - if (i2c_write(st.hw->addr, st.reg->s1_addr, 1, data)) { - return -1; - } - - /* AKM measurement mode register. */ - data[0] = AKM_REG_CNTL; - if (i2c_write(st.hw->addr, st.reg->s1_reg, 1, data)) { - return -1; - } - - /* Enable slave 1, 1-byte writes. */ - data[0] = BIT_SLAVE_EN | 1; - if (i2c_write(st.hw->addr, st.reg->s1_ctrl, 1, data)) { - return -1; - } - - /* Set slave 1 data. */ - data[0] = AKM_SINGLE_MEASUREMENT; - if (i2c_write(st.hw->addr, st.reg->s1_do, 1, data)) { - return -1; - } - - /* Trigger slave 0 and slave 1 actions at each sample. */ - data[0] = 0x03; - if (i2c_write(st.hw->addr, st.reg->i2c_delay_ctrl, 1, data)) { - return -1; - } - -#ifdef MPU9150 - /* For the MPU9150, the auxiliary I2C bus needs to be set to VDD. */ - data[0] = BIT_I2C_MST_VDDIO; - if (i2c_write(st.hw->addr, st.reg->yg_offs_tc, 1, data)) { - return -1; - } -#endif - - return 0; -} -#endif - -/** - * @brief Read raw compass data. - * @param[out] data Raw data in hardware units. - * @param[out] timestamp Timestamp in milliseconds. Null if not needed. - * @return 0 if successful. - */ -int mpu_get_compass_reg(short *data, unsigned long *timestamp) -{ -#ifdef AK89xx_SECONDARY - unsigned char tmp[9]; - - if (!(st.chip_cfg.sensors & INV_XYZ_COMPASS)) { - return -1; - } - -#ifdef AK89xx_BYPASS - if (i2c_read(st.chip_cfg.compass_addr, AKM_REG_ST1, 8, tmp)) { - return -1; - } - tmp[8] = AKM_SINGLE_MEASUREMENT; - if (i2c_write(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp + 8)) { - return -1; - } -#else - if (i2c_read(st.hw->addr, st.reg->raw_compass, 8, tmp)) { - return -1; - } -#endif - -#if defined AK8975_SECONDARY - /* AK8975 doesn't have the overrun error bit. */ - if (!(tmp[0] & AKM_DATA_READY)) { - return -2; - } - if ((tmp[7] & AKM_OVERFLOW) || (tmp[7] & AKM_DATA_ERROR)) { - return -3; - } -#elif defined AK8963_SECONDARY - /* AK8963 doesn't have the data read error bit. */ - if (!(tmp[0] & AKM_DATA_READY) || (tmp[0] & AKM_DATA_OVERRUN)) { - return -2; - } - if (tmp[7] & AKM_OVERFLOW) { - return -3; - } -#endif - data[0] = (tmp[2] << 8) | tmp[1]; - data[1] = (tmp[4] << 8) | tmp[3]; - data[2] = (tmp[6] << 8) | tmp[5]; - - data[0] = ((long)data[0] * st.chip_cfg.mag_sens_adj[0]) >> 8; - data[1] = ((long)data[1] * st.chip_cfg.mag_sens_adj[1]) >> 8; - data[2] = ((long)data[2] * st.chip_cfg.mag_sens_adj[2]) >> 8; - - if (timestamp) { - get_ms(timestamp); - } - return 0; -#else - return -1; -#endif -} - -/** - * @brief Get the compass full-scale range. - * @param[out] fsr Current full-scale range. - * @return 0 if successful. - */ -int mpu_get_compass_fsr(unsigned short *fsr) -{ -#ifdef AK89xx_SECONDARY - fsr[0] = st.hw->compass_fsr; - return 0; -#else - return -1; -#endif -} - -/** - * @brief Enters LP accel motion interrupt mode. - * The behaviour of this feature is very different between the MPU6050 and the - * MPU6500. Each chip's version of this feature is explained below. - * - * \n The hardware motion threshold can be between 32mg and 8160mg in 32mg - * increments. - * - * \n Low-power accel mode supports the following frequencies: - * \n 1.25Hz, 5Hz, 20Hz, 40Hz - * - * \n MPU6500: - * \n Unlike the MPU6050 version, the hardware does not "lock in" a reference - * sample. The hardware monitors the accel data and detects any large change - * over a short period of time. - * - * \n The hardware motion threshold can be between 4mg and 1020mg in 4mg - * increments. - * - * \n MPU6500 Low-power accel mode supports the following frequencies: - * \n 0.24Hz, 0.49Hz, 0.98Hz, 1.95Hz, 3.91Hz, 7.81Hz, 15.63Hz, 31.25Hz, 62.5Hz, 125Hz, 250Hz, 500Hz - * - * \n\n NOTES: - * \n The driver will round down @e thresh to the nearest supported value if - * an unsupported threshold is selected. - * \n To select a fractional wake-up frequency, round down the value passed to - * @e lpa_freq. - * \n The MPU6500 does not support a delay parameter. If this function is used - * for the MPU6500, the value passed to @e time will be ignored. - * \n To disable this mode, set @e lpa_freq to zero. The driver will restore - * the previous configuration. - * - * @param[in] thresh Motion threshold in mg. - * @param[in] time Duration in milliseconds that the accel data must - * exceed @e thresh before motion is reported. - * @param[in] lpa_freq Minimum sampling rate, or zero to disable. - * @return 0 if successful. - */ -int mpu_lp_motion_interrupt(unsigned short thresh, unsigned char time, - unsigned char lpa_freq) -{ - -#if defined MPU6500 - unsigned char data[3]; -#endif - if (lpa_freq) { -#if defined MPU6500 - unsigned char thresh_hw; - - /* 1LSb = 4mg. */ - if (thresh > 1020) { - thresh_hw = 255; - } else if (thresh < 4) { - thresh_hw = 1; - } else { - thresh_hw = thresh >> 2; - } -#endif - - if (!time) { - /* Minimum duration must be 1ms. */ - time = 1; - } - -#if defined MPU6500 - // if (lpa_freq > 500) - /* At this point, the chip has not been re-configured, so the - * function can safely exit. - */ - // return -1; -#endif - - if (!st.chip_cfg.int_motion_only) { - /* Store current settings for later. */ - if (st.chip_cfg.dmp_on) { - mpu_set_dmp_state(0); - st.chip_cfg.cache.dmp_on = 1; - } else { - st.chip_cfg.cache.dmp_on = 0; - } - mpu_get_gyro_fsr(&st.chip_cfg.cache.gyro_fsr); - mpu_get_accel_fsr(&st.chip_cfg.cache.accel_fsr); - mpu_get_lpf(&st.chip_cfg.cache.lpf); - mpu_get_sample_rate(&st.chip_cfg.cache.sample_rate); - st.chip_cfg.cache.sensors_on = st.chip_cfg.sensors; - mpu_get_fifo_config(&st.chip_cfg.cache.fifo_sensors); - } - -#if defined MPU6500 - /* Disable hardware interrupts. */ - set_int_enable(0); - - /* Enter full-power accel-only mode, no FIFO/DMP. */ - data[0] = 0; - data[1] = 0; - data[2] = BIT_STBY_XYZG; - if (i2c_write(st.hw->addr, st.reg->user_ctrl, 3, data)) { - goto lp_int_restore; - } - - /* Set motion threshold. */ - data[0] = thresh_hw; - if (i2c_write(st.hw->addr, st.reg->motion_thr, 1, data)) { - goto lp_int_restore; - } - - /* Set wake frequency. */ - if (lpa_freq == 1) { - data[0] = INV_LPA_0_98HZ; - } else if (lpa_freq == 2) { - data[0] = INV_LPA_1_95HZ; - } else if (lpa_freq <= 5) { - data[0] = INV_LPA_3_91HZ; - } else if (lpa_freq <= 10) { - data[0] = INV_LPA_7_81HZ; - } else if (lpa_freq <= 20) { - data[0] = INV_LPA_15_63HZ; - } else if (lpa_freq <= 40) { - data[0] = INV_LPA_31_25HZ; - } else if (lpa_freq <= 70) { - data[0] = INV_LPA_62_50HZ; - } else if (lpa_freq <= 125) { - data[0] = INV_LPA_125HZ; - } else if (lpa_freq <= 250) { - data[0] = INV_LPA_250HZ; - } else { - data[0] = INV_LPA_500HZ; - } - if (i2c_write(st.hw->addr, st.reg->lp_accel_odr, 1, data)) { - goto lp_int_restore; - } - - /* Enable motion interrupt (MPU6500 version). */ - data[0] = BITS_WOM_EN; - if (i2c_write(st.hw->addr, st.reg->accel_intel, 1, data)) { - goto lp_int_restore; - } - - /* Bypass DLPF ACCEL_FCHOICE_B=1*/ - data[0] = BIT_ACCL_FC_B | 0x01; - if (i2c_write(st.hw->addr, st.reg->accel_cfg2, 1, data)) { - goto lp_int_restore; - } - - /* Enable interrupt. */ - data[0] = BIT_MOT_INT_EN; - if (i2c_write(st.hw->addr, st.reg->int_enable, 1, data)) { - goto lp_int_restore; - } - - /* Enable cycle mode. */ - data[0] = BIT_LPA_CYCLE; - if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) { - goto lp_int_restore; - } - - st.chip_cfg.int_motion_only = 1; - return 0; -#endif - } else { - /* Don't "restore" the previous state if no state has been saved. */ - int ii; - char *cache_ptr = (char *)&st.chip_cfg.cache; - for (ii = 0; ii < sizeof(st.chip_cfg.cache); ii++) { - if (cache_ptr[ii] != 0) { - goto lp_int_restore; - } - } - /* If we reach this point, motion interrupt mode hasn't been used yet. */ - return -1; - } -lp_int_restore: - /* Set to invalid values to ensure no I2C writes are skipped. */ - st.chip_cfg.gyro_fsr = 0xFF; - st.chip_cfg.accel_fsr = 0xFF; - st.chip_cfg.lpf = 0xFF; - st.chip_cfg.sample_rate = 0xFFFF; - st.chip_cfg.sensors = 0xFF; - st.chip_cfg.fifo_enable = 0xFF; - st.chip_cfg.clk_src = INV_CLK_PLL; - mpu_set_sensors(st.chip_cfg.cache.sensors_on); - mpu_set_gyro_fsr(st.chip_cfg.cache.gyro_fsr); - mpu_set_accel_fsr(st.chip_cfg.cache.accel_fsr); - mpu_set_lpf(st.chip_cfg.cache.lpf); - mpu_set_sample_rate(st.chip_cfg.cache.sample_rate); - mpu_configure_fifo(st.chip_cfg.cache.fifo_sensors); - - if (st.chip_cfg.cache.dmp_on) { - mpu_set_dmp_state(1); - } - -#ifdef MPU6500 - /* Disable motion interrupt (MPU6500 version). */ - data[0] = 0; - if (i2c_write(st.hw->addr, st.reg->accel_intel, 1, data)) { - goto lp_int_restore; - } -#endif - - st.chip_cfg.int_motion_only = 0; - return 0; -} - -/** - * @} - */ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu.h deleted file mode 100644 index b4ccaf6f..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu.h +++ /dev/null @@ -1,161 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/* - $License: - Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. - See included License.txt for License information. - $ - */ -/** - * @addtogroup DRIVERS Sensor Driver Layer - * @brief Hardware drivers to communicate with sensors via I2C. - * - * @{ - * @file inv_mpu.h - * @brief An I2C-based driver for Invensense gyroscopes. - * @details This driver currently works for the following devices: - * MPU6050 - * MPU6500 - * MPU9150 (or MPU6050 w/ AK8975 on the auxiliary bus) - * MPU9250 (or MPU6500 w/ AK8963 on the auxiliary bus) - */ - -#ifndef _INV_MPU_H_ -#define _INV_MPU_H_ - -#define INV_X_GYRO (0x40) -#define INV_Y_GYRO (0x20) -#define INV_Z_GYRO (0x10) -#define INV_XYZ_GYRO (INV_X_GYRO | INV_Y_GYRO | INV_Z_GYRO) -#define INV_XYZ_ACCEL (0x08) -#define INV_XYZ_COMPASS (0x01) - -struct int_param_s { -#if defined EMPL_TARGET_MSP430 || defined MOTION_DRIVER_TARGET_MSP430 - void (*cb)(void); - unsigned short pin; - unsigned char lp_exit; - unsigned char active_low; -#elif defined EMPL_TARGET_UC3L0 - unsigned long pin; - void (*cb)(volatile void *); - void *arg; -#endif -}; - -#define MPU_INT_STATUS_DATA_READY (0x0001) -#define MPU_INT_STATUS_DMP (0x0002) -#define MPU_INT_STATUS_PLL_READY (0x0004) -#define MPU_INT_STATUS_I2C_MST (0x0008) -#define MPU_INT_STATUS_FIFO_OVERFLOW (0x0010) -#define MPU_INT_STATUS_ZMOT (0x0020) -#define MPU_INT_STATUS_MOT (0x0040) -#define MPU_INT_STATUS_FREE_FALL (0x0080) -#define MPU_INT_STATUS_DMP_0 (0x0100) -#define MPU_INT_STATUS_DMP_1 (0x0200) -#define MPU_INT_STATUS_DMP_2 (0x0400) -#define MPU_INT_STATUS_DMP_3 (0x0800) -#define MPU_INT_STATUS_DMP_4 (0x1000) -#define MPU_INT_STATUS_DMP_5 (0x2000) - -/* Set up APIs */ -// int mpu_init(struct int_param_s *int_param); -int mpu_init();// struct int_param_s *int_param); -int mpu_init_slave(void); -int mpu_set_bypass(unsigned char bypass_on); - -/* Configuration APIs */ -int mpu_lp_accel_mode(unsigned short rate); -int mpu_lp_motion_interrupt(unsigned short thresh, unsigned char time, - unsigned char lpa_freq); -int mpu_set_int_level(unsigned char active_low); -int mpu_set_int_latched(unsigned char enable); - -int mpu_set_dmp_state(unsigned char enable); -int mpu_get_dmp_state(unsigned char *enabled); - -int mpu_get_lpf(unsigned short *lpf); -int mpu_set_lpf(unsigned short lpf); - -int mpu_get_gyro_fsr(unsigned short *fsr); -int mpu_set_gyro_fsr(unsigned short fsr); - -int mpu_get_accel_fsr(unsigned char *fsr); -int mpu_set_accel_fsr(unsigned char fsr); - -int mpu_get_compass_fsr(unsigned short *fsr); - -int mpu_get_gyro_sens(float *sens); -int mpu_get_accel_sens(unsigned short *sens); - -int mpu_get_sample_rate(unsigned short *rate); -int mpu_set_sample_rate(unsigned short rate); -int mpu_get_compass_sample_rate(unsigned short *rate); -int mpu_set_compass_sample_rate(unsigned short rate); - -int mpu_get_fifo_config(unsigned char *sensors); -int mpu_configure_fifo(unsigned char sensors); - -int mpu_get_power_state(unsigned char *power_on); -int mpu_set_sensors(unsigned char sensors); - -int mpu_read_6500_accel_bias(long *accel_bias); -int mpu_set_gyro_bias_reg(long *gyro_bias); -int mpu_set_accel_bias_6500_reg(const long *accel_bias); -int mpu_read_6050_accel_bias(long *accel_bias); -int mpu_set_accel_bias_6050_reg(const long *accel_bias); - -/* Data getter/setter APIs */ -int mpu_get_gyro_reg(short *data, unsigned long *timestamp); -int mpu_get_accel_reg(short *data, unsigned long *timestamp); -int mpu_get_compass_reg(short *data, unsigned long *timestamp); -int mpu_get_temperature(long *data, unsigned long *timestamp); - -int mpu_get_int_status(short *status); -int mpu_read_fifo(short *gyro, short *accel, unsigned long *timestamp, - unsigned char *sensors, unsigned char *more); -int mpu_read_fifo_stream(unsigned short length, unsigned char *data, - unsigned char *more); -int mpu_reset_fifo(void); - -int mpu_write_mem(unsigned short mem_addr, unsigned short length, - unsigned char *data); -int mpu_read_mem(unsigned short mem_addr, unsigned short length, - unsigned char *data); -int mpu_load_firmware(unsigned short length, const unsigned char *firmware, - unsigned short start_addr, unsigned short sample_rate); - -int mpu_reg_dump(void); -int mpu_read_reg(unsigned char reg, unsigned char *data); -int mpu_run_self_test(long *gyro, long *accel); -int mpu_run_6500_self_test(long *gyro, long *accel, unsigned char debug); -int mpu_register_tap_cb(void (*func)(unsigned char, unsigned char)); - -#endif /* #ifndef _INV_MPU_H_ */ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu_dmp_motion_driver.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu_dmp_motion_driver.c deleted file mode 100644 index 46ba4c92..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu_dmp_motion_driver.c +++ /dev/null @@ -1,1452 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/* - $License: - Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. - See included License.txt for License information. - $ - */ -/** - * @addtogroup DRIVERS Sensor Driver Layer - * @brief Hardware drivers to communicate with sensors via I2C. - * - * @{ - * @file inv_mpu_dmp_motion_driver.c - * @brief DMP image and interface functions. - * @details All functions are preceded by the dmp_ prefix to - * differentiate among MPL and general driver function calls. - */ -#include -#include -#include -#include -#include -#include "inv_mpu.h" -#include "inv_mpu_dmp_motion_driver.h" -#include "dmpKey.h" -#include "dmpmap.h" -#define MOTION_DRIVER_TARGET_IOTDK -/* The following functions must be defined for this platform: - * i2c_write(unsigned char slave_addr, unsigned char reg_addr, - * unsigned char length, unsigned char const *data) - * i2c_read(unsigned char slave_addr, unsigned char reg_addr, - * unsigned char length, unsigned char *data) - * delay_ms(unsigned long num_ms) - * get_ms(unsigned long *count) - */ -#if defined MOTION_DRIVER_TARGET_MSP430 -#include "msp430.h" -#include "msp430_clock.h" -#define delay_ms msp430_delay_ms -#define get_ms msp430_get_clock_ms -#define log_i(...) do {} while (0) -#define log_e(...) do {} while (0) - -#elif defined EMPL_TARGET_MSP430 -#include "msp430.h" -#include "msp430_clock.h" -#include "log.h" -#define delay_ms msp430_delay_ms -#define get_ms msp430_get_clock_ms -#define log_i MPL_LOGI -#define log_e MPL_LOGE - -#elif defined EMPL_TARGET_UC3L0 -/* Instead of using the standard TWI driver from the ASF library, we're using - * a TWI driver that follows the slave address + register address convention. - */ -#include "delay.h" -#include "sysclk.h" -#include "log.h" -#include "uc3l0_clock.h" -/* delay_ms is a function already defined in ASF. */ -#define get_ms uc3l0_get_clock_ms -#define log_i MPL_LOGI -#define log_e MPL_LOGE - -#elif defined MOTION_DRIVER_TARGET_IOTDK -#include "embARC.h" -#include "embARC_debug.h" -#include "mpu9250.h" -#define get_ms mpu_get_ms -#else -#error Gyro driver is missing the system layer implementations. -#endif - -/* These defines are copied from dmpDefaultMPU6050.c in the general MPL - * releases. These defines may change for each DMP image, so be sure to modify - * these values when switching to a new image. - */ -#define CFG_LP_QUAT (2712) -#define END_ORIENT_TEMP (1866) -#define CFG_27 (2742) -#define CFG_20 (2224) -#define CFG_23 (2745) -#define CFG_FIFO_ON_EVENT (2690) -#define END_PREDICTION_UPDATE (1761) -#define CGNOTICE_INTR (2620) -#define X_GRT_Y_TMP (1358) -#define CFG_DR_INT (1029) -#define CFG_AUTH (1035) -#define UPDATE_PROP_ROT (1835) -#define END_COMPARE_Y_X_TMP2 (1455) -#define SKIP_X_GRT_Y_TMP (1359) -#define SKIP_END_COMPARE (1435) -#define FCFG_3 (1088) -#define FCFG_2 (1066) -#define FCFG_1 (1062) -#define END_COMPARE_Y_X_TMP3 (1434) -#define FCFG_7 (1073) -#define FCFG_6 (1106) -#define FLAT_STATE_END (1713) -#define SWING_END_4 (1616) -#define SWING_END_2 (1565) -#define SWING_END_3 (1587) -#define SWING_END_1 (1550) -#define CFG_8 (2718) -#define CFG_15 (2727) -#define CFG_16 (2746) -#define CFG_EXT_GYRO_BIAS (1189) -#define END_COMPARE_Y_X_TMP (1407) -#define DO_NOT_UPDATE_PROP_ROT (1839) -#define CFG_7 (1205) -#define FLAT_STATE_END_TEMP (1683) -#define END_COMPARE_Y_X (1484) -#define SKIP_SWING_END_1 (1551) -#define SKIP_SWING_END_3 (1588) -#define SKIP_SWING_END_2 (1566) -#define TILTG75_START (1672) -#define CFG_6 (2753) -#define TILTL75_END (1669) -#define END_ORIENT (1884) -#define CFG_FLICK_IN (2573) -#define TILTL75_START (1643) -#define CFG_MOTION_BIAS (1208) -#define X_GRT_Y (1408) -#define TEMPLABEL (2324) -#define CFG_ANDROID_ORIENT_INT (1853) -#define CFG_GYRO_RAW_DATA (2722) -#define X_GRT_Y_TMP2 (1379) - -#define D_0_22 (22 + 512) -#define D_0_24 (24 + 512) - -#define D_0_36 (36) -#define D_0_52 (52) -#define D_0_96 (96) -#define D_0_104 (104) -#define D_0_108 (108) -#define D_0_163 (163) -#define D_0_188 (188) -#define D_0_192 (192) -#define D_0_224 (224) -#define D_0_228 (228) -#define D_0_232 (232) -#define D_0_236 (236) - -#define D_1_2 (256 + 2) -#define D_1_4 (256 + 4) -#define D_1_8 (256 + 8) -#define D_1_10 (256 + 10) -#define D_1_24 (256 + 24) -#define D_1_28 (256 + 28) -#define D_1_36 (256 + 36) -#define D_1_40 (256 + 40) -#define D_1_44 (256 + 44) -#define D_1_72 (256 + 72) -#define D_1_74 (256 + 74) -#define D_1_79 (256 + 79) -#define D_1_88 (256 + 88) -#define D_1_90 (256 + 90) -#define D_1_92 (256 + 92) -#define D_1_96 (256 + 96) -#define D_1_98 (256 + 98) -#define D_1_106 (256 + 106) -#define D_1_108 (256 + 108) -#define D_1_112 (256 + 112) -#define D_1_128 (256 + 144) -#define D_1_152 (256 + 12) -#define D_1_160 (256 + 160) -#define D_1_176 (256 + 176) -#define D_1_178 (256 + 178) -#define D_1_218 (256 + 218) -#define D_1_232 (256 + 232) -#define D_1_236 (256 + 236) -#define D_1_240 (256 + 240) -#define D_1_244 (256 + 244) -#define D_1_250 (256 + 250) -#define D_1_252 (256 + 252) -#define D_2_12 (512 + 12) -#define D_2_96 (512 + 96) -#define D_2_108 (512 + 108) -#define D_2_208 (512 + 208) -#define D_2_224 (512 + 224) -#define D_2_236 (512 + 236) -#define D_2_244 (512 + 244) -#define D_2_248 (512 + 248) -#define D_2_252 (512 + 252) - -#define CPASS_BIAS_X (35 * 16 + 4) -#define CPASS_BIAS_Y (35 * 16 + 8) -#define CPASS_BIAS_Z (35 * 16 + 12) -#define CPASS_MTX_00 (36 * 16) -#define CPASS_MTX_01 (36 * 16 + 4) -#define CPASS_MTX_02 (36 * 16 + 8) -#define CPASS_MTX_10 (36 * 16 + 12) -#define CPASS_MTX_11 (37 * 16) -#define CPASS_MTX_12 (37 * 16 + 4) -#define CPASS_MTX_20 (37 * 16 + 8) -#define CPASS_MTX_21 (37 * 16 + 12) -#define CPASS_MTX_22 (43 * 16 + 12) -#define D_EXT_GYRO_BIAS_X (61 * 16) -#define D_EXT_GYRO_BIAS_Y (61 * 16) + 4 -#define D_EXT_GYRO_BIAS_Z (61 * 16) + 8 -#define D_ACT0 (40 * 16) -#define D_ACSX (40 * 16 + 4) -#define D_ACSY (40 * 16 + 8) -#define D_ACSZ (40 * 16 + 12) - -#define FLICK_MSG (45 * 16 + 4) -#define FLICK_COUNTER (45 * 16 + 8) -#define FLICK_LOWER (45 * 16 + 12) -#define FLICK_UPPER (46 * 16 + 12) - -#define D_AUTH_OUT (992) -#define D_AUTH_IN (996) -#define D_AUTH_A (1000) -#define D_AUTH_B (1004) - -#define D_PEDSTD_BP_B (768 + 0x1C) -#define D_PEDSTD_HP_A (768 + 0x78) -#define D_PEDSTD_HP_B (768 + 0x7C) -#define D_PEDSTD_BP_A4 (768 + 0x40) -#define D_PEDSTD_BP_A3 (768 + 0x44) -#define D_PEDSTD_BP_A2 (768 + 0x48) -#define D_PEDSTD_BP_A1 (768 + 0x4C) -#define D_PEDSTD_INT_THRSH (768 + 0x68) -#define D_PEDSTD_CLIP (768 + 0x6C) -#define D_PEDSTD_SB (768 + 0x28) -#define D_PEDSTD_SB_TIME (768 + 0x2C) -#define D_PEDSTD_PEAKTHRSH (768 + 0x98) -#define D_PEDSTD_TIML (768 + 0x2A) -#define D_PEDSTD_TIMH (768 + 0x2E) -#define D_PEDSTD_PEAK (768 + 0X94) -#define D_PEDSTD_STEPCTR (768 + 0x60) -#define D_PEDSTD_TIMECTR (964) -#define D_PEDSTD_DECI (768 + 0xA0) - -#define D_HOST_NO_MOT (976) -#define D_ACCEL_BIAS (660) - -#define D_ORIENT_GAP (76) - -#define D_TILT0_H (48) -#define D_TILT0_L (50) -#define D_TILT1_H (52) -#define D_TILT1_L (54) -#define D_TILT2_H (56) -#define D_TILT2_L (58) -#define D_TILT3_H (60) -#define D_TILT3_L (62) - -#define DMP_CODE_SIZE (3062) - -static const unsigned char dmp_memory[DMP_CODE_SIZE] = { - /* bank # 0 */ - 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, - 0x00, 0x65, 0x00, 0x54, 0xff, 0xef, 0x00, 0x00, 0xfa, 0x80, 0x00, 0x0b, 0x12, 0x82, 0x00, 0x01, - 0x03, 0x0c, 0x30, 0xc3, 0x0e, 0x8c, 0x8c, 0xe9, 0x14, 0xd5, 0x40, 0x02, 0x13, 0x71, 0x0f, 0x8e, - 0x38, 0x83, 0xf8, 0x83, 0x30, 0x00, 0xf8, 0x83, 0x25, 0x8e, 0xf8, 0x83, 0x30, 0x00, 0xf8, 0x83, - 0xff, 0xff, 0xff, 0xff, 0x0f, 0xfe, 0xa9, 0xd6, 0x24, 0x00, 0x04, 0x00, 0x1a, 0x82, 0x79, 0xa1, - 0x00, 0x00, 0x00, 0x3c, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x38, 0x83, 0x6f, 0xa2, - 0x00, 0x3e, 0x03, 0x30, 0x40, 0x00, 0x00, 0x00, 0x02, 0xca, 0xe3, 0x09, 0x3e, 0x80, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, - 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0x18, 0x6e, 0x00, 0x00, 0x06, 0x92, 0x0a, 0x16, 0xc0, 0xdf, - 0xff, 0xff, 0x02, 0x56, 0xfd, 0x8c, 0xd3, 0x77, 0xff, 0xe1, 0xc4, 0x96, 0xe0, 0xc5, 0xbe, 0xaa, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x0b, 0x2b, 0x00, 0x00, 0x16, 0x57, 0x00, 0x00, 0x03, 0x59, - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0xfa, 0x00, 0x02, 0x6c, 0x1d, 0x00, 0x00, 0x00, 0x00, - 0x3f, 0xff, 0xdf, 0xeb, 0x00, 0x3e, 0xb3, 0xb6, 0x00, 0x0d, 0x22, 0x78, 0x00, 0x00, 0x2f, 0x3c, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x42, 0xb5, 0x00, 0x00, 0x39, 0xa2, 0x00, 0x00, 0xb3, 0x65, - 0xd9, 0x0e, 0x9f, 0xc9, 0x1d, 0xcf, 0x4c, 0x34, 0x30, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, - 0x3b, 0xb6, 0x7a, 0xe8, 0x00, 0x64, 0x00, 0x00, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* bank # 1 */ - 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0xfa, 0x92, 0x10, 0x00, 0x22, 0x5e, 0x00, 0x0d, 0x22, 0x9f, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0xff, 0x46, 0x00, 0x00, 0x63, 0xd4, 0x00, 0x00, - 0x10, 0x00, 0x00, 0x00, 0x04, 0xd6, 0x00, 0x00, 0x04, 0xcc, 0x00, 0x00, 0x04, 0xcc, 0x00, 0x00, - 0x00, 0x00, 0x10, 0x72, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x06, 0x00, 0x02, 0x00, 0x05, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, 0x64, 0x00, 0x20, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x32, 0xf8, 0x98, 0x00, 0x00, 0xff, 0x65, 0x00, 0x00, 0x83, 0x0f, 0x00, 0x00, - 0xff, 0x9b, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0xb2, 0x6a, 0x00, 0x02, 0x00, 0x00, - 0x00, 0x01, 0xfb, 0x83, 0x00, 0x68, 0x00, 0x00, 0x00, 0xd9, 0xfc, 0x00, 0x7c, 0xf1, 0xff, 0x83, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x64, 0x03, 0xe8, 0x00, 0x64, 0x00, 0x28, - 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x00, 0x16, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, - 0x00, 0x00, 0x10, 0x00, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf4, 0x00, 0x00, 0x10, 0x00, - /* bank # 2 */ - 0x00, 0x28, 0x00, 0x00, 0xff, 0xff, 0x45, 0x81, 0xff, 0xff, 0xfa, 0x72, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x05, 0x00, 0x05, 0xba, 0xc6, 0x00, 0x47, 0x78, 0xa2, - 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x14, - 0x00, 0x00, 0x25, 0x4d, 0x00, 0x2f, 0x70, 0x6d, 0x00, 0x00, 0x05, 0xae, 0x00, 0x0c, 0x02, 0xd0, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x64, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x0e, - 0x00, 0x00, 0x0a, 0xc7, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x32, 0xff, 0xff, 0xff, 0x9c, - 0x00, 0x00, 0x0b, 0x2b, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x64, - 0xff, 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* bank # 3 */ - 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x24, 0x26, 0xd3, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x10, 0x00, 0x96, 0x00, 0x3c, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0c, 0x0a, 0x4e, 0x68, 0xcd, 0xcf, 0x77, 0x09, 0x50, 0x16, 0x67, 0x59, 0xc6, 0x19, 0xce, 0x82, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0xd7, 0x84, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc7, 0x93, 0x8f, 0x9d, 0x1e, 0x1b, 0x1c, 0x19, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x18, 0x85, 0x00, 0x00, 0x40, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x67, 0x7d, 0xdf, 0x7e, 0x72, 0x90, 0x2e, 0x55, 0x4c, 0xf6, 0xe6, 0x88, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - /* bank # 4 */ - 0xd8, 0xdc, 0xb4, 0xb8, 0xb0, 0xd8, 0xb9, 0xab, 0xf3, 0xf8, 0xfa, 0xb3, 0xb7, 0xbb, 0x8e, 0x9e, - 0xae, 0xf1, 0x32, 0xf5, 0x1b, 0xf1, 0xb4, 0xb8, 0xb0, 0x80, 0x97, 0xf1, 0xa9, 0xdf, 0xdf, 0xdf, - 0xaa, 0xdf, 0xdf, 0xdf, 0xf2, 0xaa, 0xc5, 0xcd, 0xc7, 0xa9, 0x0c, 0xc9, 0x2c, 0x97, 0xf1, 0xa9, - 0x89, 0x26, 0x46, 0x66, 0xb2, 0x89, 0x99, 0xa9, 0x2d, 0x55, 0x7d, 0xb0, 0xb0, 0x8a, 0xa8, 0x96, - 0x36, 0x56, 0x76, 0xf1, 0xba, 0xa3, 0xb4, 0xb2, 0x80, 0xc0, 0xb8, 0xa8, 0x97, 0x11, 0xb2, 0x83, - 0x98, 0xba, 0xa3, 0xf0, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xb2, 0xb9, 0xb4, 0x98, 0x83, 0xf1, - 0xa3, 0x29, 0x55, 0x7d, 0xba, 0xb5, 0xb1, 0xa3, 0x83, 0x93, 0xf0, 0x00, 0x28, 0x50, 0xf5, 0xb2, - 0xb6, 0xaa, 0x83, 0x93, 0x28, 0x54, 0x7c, 0xf1, 0xb9, 0xa3, 0x82, 0x93, 0x61, 0xba, 0xa2, 0xda, - 0xde, 0xdf, 0xdb, 0x81, 0x9a, 0xb9, 0xae, 0xf5, 0x60, 0x68, 0x70, 0xf1, 0xda, 0xba, 0xa2, 0xdf, - 0xd9, 0xba, 0xa2, 0xfa, 0xb9, 0xa3, 0x82, 0x92, 0xdb, 0x31, 0xba, 0xa2, 0xd9, 0xba, 0xa2, 0xf8, - 0xdf, 0x85, 0xa4, 0xd0, 0xc1, 0xbb, 0xad, 0x83, 0xc2, 0xc5, 0xc7, 0xb8, 0xa2, 0xdf, 0xdf, 0xdf, - 0xba, 0xa0, 0xdf, 0xdf, 0xdf, 0xd8, 0xd8, 0xf1, 0xb8, 0xaa, 0xb3, 0x8d, 0xb4, 0x98, 0x0d, 0x35, - 0x5d, 0xb2, 0xb6, 0xba, 0xaf, 0x8c, 0x96, 0x19, 0x8f, 0x9f, 0xa7, 0x0e, 0x16, 0x1e, 0xb4, 0x9a, - 0xb8, 0xaa, 0x87, 0x2c, 0x54, 0x7c, 0xba, 0xa4, 0xb0, 0x8a, 0xb6, 0x91, 0x32, 0x56, 0x76, 0xb2, - 0x84, 0x94, 0xa4, 0xc8, 0x08, 0xcd, 0xd8, 0xb8, 0xb4, 0xb0, 0xf1, 0x99, 0x82, 0xa8, 0x2d, 0x55, - 0x7d, 0x98, 0xa8, 0x0e, 0x16, 0x1e, 0xa2, 0x2c, 0x54, 0x7c, 0x92, 0xa4, 0xf0, 0x2c, 0x50, 0x78, - /* bank # 5 */ - 0xf1, 0x84, 0xa8, 0x98, 0xc4, 0xcd, 0xfc, 0xd8, 0x0d, 0xdb, 0xa8, 0xfc, 0x2d, 0xf3, 0xd9, 0xba, - 0xa6, 0xf8, 0xda, 0xba, 0xa6, 0xde, 0xd8, 0xba, 0xb2, 0xb6, 0x86, 0x96, 0xa6, 0xd0, 0xf3, 0xc8, - 0x41, 0xda, 0xa6, 0xc8, 0xf8, 0xd8, 0xb0, 0xb4, 0xb8, 0x82, 0xa8, 0x92, 0xf5, 0x2c, 0x54, 0x88, - 0x98, 0xf1, 0x35, 0xd9, 0xf4, 0x18, 0xd8, 0xf1, 0xa2, 0xd0, 0xf8, 0xf9, 0xa8, 0x84, 0xd9, 0xc7, - 0xdf, 0xf8, 0xf8, 0x83, 0xc5, 0xda, 0xdf, 0x69, 0xdf, 0x83, 0xc1, 0xd8, 0xf4, 0x01, 0x14, 0xf1, - 0xa8, 0x82, 0x4e, 0xa8, 0x84, 0xf3, 0x11, 0xd1, 0x82, 0xf5, 0xd9, 0x92, 0x28, 0x97, 0x88, 0xf1, - 0x09, 0xf4, 0x1c, 0x1c, 0xd8, 0x84, 0xa8, 0xf3, 0xc0, 0xf9, 0xd1, 0xd9, 0x97, 0x82, 0xf1, 0x29, - 0xf4, 0x0d, 0xd8, 0xf3, 0xf9, 0xf9, 0xd1, 0xd9, 0x82, 0xf4, 0xc2, 0x03, 0xd8, 0xde, 0xdf, 0x1a, - 0xd8, 0xf1, 0xa2, 0xfa, 0xf9, 0xa8, 0x84, 0x98, 0xd9, 0xc7, 0xdf, 0xf8, 0xf8, 0xf8, 0x83, 0xc7, - 0xda, 0xdf, 0x69, 0xdf, 0xf8, 0x83, 0xc3, 0xd8, 0xf4, 0x01, 0x14, 0xf1, 0x98, 0xa8, 0x82, 0x2e, - 0xa8, 0x84, 0xf3, 0x11, 0xd1, 0x82, 0xf5, 0xd9, 0x92, 0x50, 0x97, 0x88, 0xf1, 0x09, 0xf4, 0x1c, - 0xd8, 0x84, 0xa8, 0xf3, 0xc0, 0xf8, 0xf9, 0xd1, 0xd9, 0x97, 0x82, 0xf1, 0x49, 0xf4, 0x0d, 0xd8, - 0xf3, 0xf9, 0xf9, 0xd1, 0xd9, 0x82, 0xf4, 0xc4, 0x03, 0xd8, 0xde, 0xdf, 0xd8, 0xf1, 0xad, 0x88, - 0x98, 0xcc, 0xa8, 0x09, 0xf9, 0xd9, 0x82, 0x92, 0xa8, 0xf5, 0x7c, 0xf1, 0x88, 0x3a, 0xcf, 0x94, - 0x4a, 0x6e, 0x98, 0xdb, 0x69, 0x31, 0xda, 0xad, 0xf2, 0xde, 0xf9, 0xd8, 0x87, 0x95, 0xa8, 0xf2, - 0x21, 0xd1, 0xda, 0xa5, 0xf9, 0xf4, 0x17, 0xd9, 0xf1, 0xae, 0x8e, 0xd0, 0xc0, 0xc3, 0xae, 0x82, - /* bank # 6 */ - 0xc6, 0x84, 0xc3, 0xa8, 0x85, 0x95, 0xc8, 0xa5, 0x88, 0xf2, 0xc0, 0xf1, 0xf4, 0x01, 0x0e, 0xf1, - 0x8e, 0x9e, 0xa8, 0xc6, 0x3e, 0x56, 0xf5, 0x54, 0xf1, 0x88, 0x72, 0xf4, 0x01, 0x15, 0xf1, 0x98, - 0x45, 0x85, 0x6e, 0xf5, 0x8e, 0x9e, 0x04, 0x88, 0xf1, 0x42, 0x98, 0x5a, 0x8e, 0x9e, 0x06, 0x88, - 0x69, 0xf4, 0x01, 0x1c, 0xf1, 0x98, 0x1e, 0x11, 0x08, 0xd0, 0xf5, 0x04, 0xf1, 0x1e, 0x97, 0x02, - 0x02, 0x98, 0x36, 0x25, 0xdb, 0xf9, 0xd9, 0x85, 0xa5, 0xf3, 0xc1, 0xda, 0x85, 0xa5, 0xf3, 0xdf, - 0xd8, 0x85, 0x95, 0xa8, 0xf3, 0x09, 0xda, 0xa5, 0xfa, 0xd8, 0x82, 0x92, 0xa8, 0xf5, 0x78, 0xf1, - 0x88, 0x1a, 0x84, 0x9f, 0x26, 0x88, 0x98, 0x21, 0xda, 0xf4, 0x1d, 0xf3, 0xd8, 0x87, 0x9f, 0x39, - 0xd1, 0xaf, 0xd9, 0xdf, 0xdf, 0xfb, 0xf9, 0xf4, 0x0c, 0xf3, 0xd8, 0xfa, 0xd0, 0xf8, 0xda, 0xf9, - 0xf9, 0xd0, 0xdf, 0xd9, 0xf9, 0xd8, 0xf4, 0x0b, 0xd8, 0xf3, 0x87, 0x9f, 0x39, 0xd1, 0xaf, 0xd9, - 0xdf, 0xdf, 0xf4, 0x1d, 0xf3, 0xd8, 0xfa, 0xfc, 0xa8, 0x69, 0xf9, 0xf9, 0xaf, 0xd0, 0xda, 0xde, - 0xfa, 0xd9, 0xf8, 0x8f, 0x9f, 0xa8, 0xf1, 0xcc, 0xf3, 0x98, 0xdb, 0x45, 0xd9, 0xaf, 0xdf, 0xd0, - 0xf8, 0xd8, 0xf1, 0x8f, 0x9f, 0xa8, 0xca, 0xf3, 0x88, 0x09, 0xda, 0xaf, 0x8f, 0xcb, 0xf8, 0xd8, - 0xf2, 0xad, 0x97, 0x8d, 0x0c, 0xd9, 0xa5, 0xdf, 0xf9, 0xba, 0xa6, 0xf3, 0xfa, 0xf4, 0x12, 0xf2, - 0xd8, 0x95, 0x0d, 0xd1, 0xd9, 0xba, 0xa6, 0xf3, 0xfa, 0xda, 0xa5, 0xf2, 0xc1, 0xba, 0xa6, 0xf3, - 0xdf, 0xd8, 0xf1, 0xba, 0xb2, 0xb6, 0x86, 0x96, 0xa6, 0xd0, 0xca, 0xf3, 0x49, 0xda, 0xa6, 0xcb, - 0xf8, 0xd8, 0xb0, 0xb4, 0xb8, 0xd8, 0xad, 0x84, 0xf2, 0xc0, 0xdf, 0xf1, 0x8f, 0xcb, 0xc3, 0xa8, - /* bank # 7 */ - 0xb2, 0xb6, 0x86, 0x96, 0xc8, 0xc1, 0xcb, 0xc3, 0xf3, 0xb0, 0xb4, 0x88, 0x98, 0xa8, 0x21, 0xdb, - 0x71, 0x8d, 0x9d, 0x71, 0x85, 0x95, 0x21, 0xd9, 0xad, 0xf2, 0xfa, 0xd8, 0x85, 0x97, 0xa8, 0x28, - 0xd9, 0xf4, 0x08, 0xd8, 0xf2, 0x8d, 0x29, 0xda, 0xf4, 0x05, 0xd9, 0xf2, 0x85, 0xa4, 0xc2, 0xf2, - 0xd8, 0xa8, 0x8d, 0x94, 0x01, 0xd1, 0xd9, 0xf4, 0x11, 0xf2, 0xd8, 0x87, 0x21, 0xd8, 0xf4, 0x0a, - 0xd8, 0xf2, 0x84, 0x98, 0xa8, 0xc8, 0x01, 0xd1, 0xd9, 0xf4, 0x11, 0xd8, 0xf3, 0xa4, 0xc8, 0xbb, - 0xaf, 0xd0, 0xf2, 0xde, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xd8, 0xf1, 0xb8, 0xf6, - 0xb5, 0xb9, 0xb0, 0x8a, 0x95, 0xa3, 0xde, 0x3c, 0xa3, 0xd9, 0xf8, 0xd8, 0x5c, 0xa3, 0xd9, 0xf8, - 0xd8, 0x7c, 0xa3, 0xd9, 0xf8, 0xd8, 0xf8, 0xf9, 0xd1, 0xa5, 0xd9, 0xdf, 0xda, 0xfa, 0xd8, 0xb1, - 0x85, 0x30, 0xf7, 0xd9, 0xde, 0xd8, 0xf8, 0x30, 0xad, 0xda, 0xde, 0xd8, 0xf2, 0xb4, 0x8c, 0x99, - 0xa3, 0x2d, 0x55, 0x7d, 0xa0, 0x83, 0xdf, 0xdf, 0xdf, 0xb5, 0x91, 0xa0, 0xf6, 0x29, 0xd9, 0xfb, - 0xd8, 0xa0, 0xfc, 0x29, 0xd9, 0xfa, 0xd8, 0xa0, 0xd0, 0x51, 0xd9, 0xf8, 0xd8, 0xfc, 0x51, 0xd9, - 0xf9, 0xd8, 0x79, 0xd9, 0xfb, 0xd8, 0xa0, 0xd0, 0xfc, 0x79, 0xd9, 0xfa, 0xd8, 0xa1, 0xf9, 0xf9, - 0xf9, 0xf9, 0xf9, 0xa0, 0xda, 0xdf, 0xdf, 0xdf, 0xd8, 0xa1, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xac, - 0xde, 0xf8, 0xad, 0xde, 0x83, 0x93, 0xac, 0x2c, 0x54, 0x7c, 0xf1, 0xa8, 0xdf, 0xdf, 0xdf, 0xf6, - 0x9d, 0x2c, 0xda, 0xa0, 0xdf, 0xd9, 0xfa, 0xdb, 0x2d, 0xf8, 0xd8, 0xa8, 0x50, 0xda, 0xa0, 0xd0, - 0xde, 0xd9, 0xd0, 0xf8, 0xf8, 0xf8, 0xdb, 0x55, 0xf8, 0xd8, 0xa8, 0x78, 0xda, 0xa0, 0xd0, 0xdf, - /* bank # 8 */ - 0xd9, 0xd0, 0xfa, 0xf8, 0xf8, 0xf8, 0xf8, 0xdb, 0x7d, 0xf8, 0xd8, 0x9c, 0xa8, 0x8c, 0xf5, 0x30, - 0xdb, 0x38, 0xd9, 0xd0, 0xde, 0xdf, 0xa0, 0xd0, 0xde, 0xdf, 0xd8, 0xa8, 0x48, 0xdb, 0x58, 0xd9, - 0xdf, 0xd0, 0xde, 0xa0, 0xdf, 0xd0, 0xde, 0xd8, 0xa8, 0x68, 0xdb, 0x70, 0xd9, 0xdf, 0xdf, 0xa0, - 0xdf, 0xdf, 0xd8, 0xf1, 0xa8, 0x88, 0x90, 0x2c, 0x54, 0x7c, 0x98, 0xa8, 0xd0, 0x5c, 0x38, 0xd1, - 0xda, 0xf2, 0xae, 0x8c, 0xdf, 0xf9, 0xd8, 0xb0, 0x87, 0xa8, 0xc1, 0xc1, 0xb1, 0x88, 0xa8, 0xc6, - 0xf9, 0xf9, 0xda, 0x36, 0xd8, 0xa8, 0xf9, 0xda, 0x36, 0xd8, 0xa8, 0xf9, 0xda, 0x36, 0xd8, 0xa8, - 0xf9, 0xda, 0x36, 0xd8, 0xa8, 0xf9, 0xda, 0x36, 0xd8, 0xf7, 0x8d, 0x9d, 0xad, 0xf8, 0x18, 0xda, - 0xf2, 0xae, 0xdf, 0xd8, 0xf7, 0xad, 0xfa, 0x30, 0xd9, 0xa4, 0xde, 0xf9, 0xd8, 0xf2, 0xae, 0xde, - 0xfa, 0xf9, 0x83, 0xa7, 0xd9, 0xc3, 0xc5, 0xc7, 0xf1, 0x88, 0x9b, 0xa7, 0x7a, 0xad, 0xf7, 0xde, - 0xdf, 0xa4, 0xf8, 0x84, 0x94, 0x08, 0xa7, 0x97, 0xf3, 0x00, 0xae, 0xf2, 0x98, 0x19, 0xa4, 0x88, - 0xc6, 0xa3, 0x94, 0x88, 0xf6, 0x32, 0xdf, 0xf2, 0x83, 0x93, 0xdb, 0x09, 0xd9, 0xf2, 0xaa, 0xdf, - 0xd8, 0xd8, 0xae, 0xf8, 0xf9, 0xd1, 0xda, 0xf3, 0xa4, 0xde, 0xa7, 0xf1, 0x88, 0x9b, 0x7a, 0xd8, - 0xf3, 0x84, 0x94, 0xae, 0x19, 0xf9, 0xda, 0xaa, 0xf1, 0xdf, 0xd8, 0xa8, 0x81, 0xc0, 0xc3, 0xc5, - 0xc7, 0xa3, 0x92, 0x83, 0xf6, 0x28, 0xad, 0xde, 0xd9, 0xf8, 0xd8, 0xa3, 0x50, 0xad, 0xd9, 0xf8, - 0xd8, 0xa3, 0x78, 0xad, 0xd9, 0xf8, 0xd8, 0xf8, 0xf9, 0xd1, 0xa1, 0xda, 0xde, 0xc3, 0xc5, 0xc7, - 0xd8, 0xa1, 0x81, 0x94, 0xf8, 0x18, 0xf2, 0xb0, 0x89, 0xac, 0xc3, 0xc5, 0xc7, 0xf1, 0xd8, 0xb8, - /* bank # 9 */ - 0xb4, 0xb0, 0x97, 0x86, 0xa8, 0x31, 0x9b, 0x06, 0x99, 0x07, 0xab, 0x97, 0x28, 0x88, 0x9b, 0xf0, - 0x0c, 0x20, 0x14, 0x40, 0xb0, 0xb4, 0xb8, 0xf0, 0xa8, 0x8a, 0x9a, 0x28, 0x50, 0x78, 0xb7, 0x9b, - 0xa8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38, 0x64, 0x48, 0x31, 0xf1, 0xbb, 0xab, - 0x88, 0x00, 0x2c, 0x54, 0x7c, 0xf0, 0xb3, 0x8b, 0xb8, 0xa8, 0x04, 0x28, 0x50, 0x78, 0xf1, 0xb0, - 0x88, 0xb4, 0x97, 0x26, 0xa8, 0x59, 0x98, 0xbb, 0xab, 0xb3, 0x8b, 0x02, 0x26, 0x46, 0x66, 0xb0, - 0xb8, 0xf0, 0x8a, 0x9c, 0xa8, 0x29, 0x51, 0x79, 0x8b, 0x29, 0x51, 0x79, 0x8a, 0x24, 0x70, 0x59, - 0x8b, 0x20, 0x58, 0x71, 0x8a, 0x44, 0x69, 0x38, 0x8b, 0x39, 0x40, 0x68, 0x8a, 0x64, 0x48, 0x31, - 0x8b, 0x30, 0x49, 0x60, 0x88, 0xf1, 0xac, 0x00, 0x2c, 0x54, 0x7c, 0xf0, 0x8c, 0xa8, 0x04, 0x28, - 0x50, 0x78, 0xf1, 0x88, 0x97, 0x26, 0xa8, 0x59, 0x98, 0xac, 0x8c, 0x02, 0x26, 0x46, 0x66, 0xf0, - 0x89, 0x9c, 0xa8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38, 0x64, 0x48, 0x31, 0xa9, - 0x88, 0x09, 0x20, 0x59, 0x70, 0xab, 0x11, 0x38, 0x40, 0x69, 0xa8, 0x19, 0x31, 0x48, 0x60, 0x8c, - 0xa8, 0x3c, 0x41, 0x5c, 0x20, 0x7c, 0x00, 0xf1, 0x87, 0x98, 0x19, 0x86, 0xa8, 0x6e, 0x76, 0x7e, - 0xa9, 0x99, 0x88, 0x2d, 0x55, 0x7d, 0xd8, 0xb1, 0xb5, 0xb9, 0xa3, 0xdf, 0xdf, 0xdf, 0xae, 0xd0, - 0xdf, 0xaa, 0xd0, 0xde, 0xf2, 0xab, 0xf8, 0xf9, 0xd9, 0xb0, 0x87, 0xc4, 0xaa, 0xf1, 0xdf, 0xdf, - 0xbb, 0xaf, 0xdf, 0xdf, 0xb9, 0xd8, 0xb1, 0xf1, 0xa3, 0x97, 0x8e, 0x60, 0xdf, 0xb0, 0x84, 0xf2, - 0xc8, 0xf8, 0xf9, 0xd9, 0xde, 0xd8, 0x93, 0x85, 0xf1, 0x4a, 0xb1, 0x83, 0xa3, 0x08, 0xb5, 0x83, - /* bank # 10 */ - 0x9a, 0x08, 0x10, 0xb7, 0x9f, 0x10, 0xd8, 0xf1, 0xb0, 0xba, 0xae, 0xb0, 0x8a, 0xc2, 0xb2, 0xb6, - 0x8e, 0x9e, 0xf1, 0xfb, 0xd9, 0xf4, 0x1d, 0xd8, 0xf9, 0xd9, 0x0c, 0xf1, 0xd8, 0xf8, 0xf8, 0xad, - 0x61, 0xd9, 0xae, 0xfb, 0xd8, 0xf4, 0x0c, 0xf1, 0xd8, 0xf8, 0xf8, 0xad, 0x19, 0xd9, 0xae, 0xfb, - 0xdf, 0xd8, 0xf4, 0x16, 0xf1, 0xd8, 0xf8, 0xad, 0x8d, 0x61, 0xd9, 0xf4, 0xf4, 0xac, 0xf5, 0x9c, - 0x9c, 0x8d, 0xdf, 0x2b, 0xba, 0xb6, 0xae, 0xfa, 0xf8, 0xf4, 0x0b, 0xd8, 0xf1, 0xae, 0xd0, 0xf8, - 0xad, 0x51, 0xda, 0xae, 0xfa, 0xf8, 0xf1, 0xd8, 0xb9, 0xb1, 0xb6, 0xa3, 0x83, 0x9c, 0x08, 0xb9, - 0xb1, 0x83, 0x9a, 0xb5, 0xaa, 0xc0, 0xfd, 0x30, 0x83, 0xb7, 0x9f, 0x10, 0xb5, 0x8b, 0x93, 0xf2, - 0x02, 0x02, 0xd1, 0xab, 0xda, 0xde, 0xd8, 0xf1, 0xb0, 0x80, 0xba, 0xab, 0xc0, 0xc3, 0xb2, 0x84, - 0xc1, 0xc3, 0xd8, 0xb1, 0xb9, 0xf3, 0x8b, 0xa3, 0x91, 0xb6, 0x09, 0xb4, 0xd9, 0xab, 0xde, 0xb0, - 0x87, 0x9c, 0xb9, 0xa3, 0xdd, 0xf1, 0xb3, 0x8b, 0x8b, 0x8b, 0x8b, 0x8b, 0xb0, 0x87, 0xa3, 0xa3, - 0xa3, 0xa3, 0xb2, 0x8b, 0xb6, 0x9b, 0xf2, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, - 0xa3, 0xf1, 0xb0, 0x87, 0xb5, 0x9a, 0xa3, 0xf3, 0x9b, 0xa3, 0xa3, 0xdc, 0xba, 0xac, 0xdf, 0xb9, - 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, - 0xd8, 0xd8, 0xd8, 0xbb, 0xb3, 0xb7, 0xf1, 0xaa, 0xf9, 0xda, 0xff, 0xd9, 0x80, 0x9a, 0xaa, 0x28, - 0xb4, 0x80, 0x98, 0xa7, 0x20, 0xb7, 0x97, 0x87, 0xa8, 0x66, 0x88, 0xf0, 0x79, 0x51, 0xf1, 0x90, - 0x2c, 0x87, 0x0c, 0xa7, 0x81, 0x97, 0x62, 0x93, 0xf0, 0x71, 0x71, 0x60, 0x85, 0x94, 0x01, 0x29, - /* bank # 11 */ - 0x51, 0x79, 0x90, 0xa5, 0xf1, 0x28, 0x4c, 0x6c, 0x87, 0x0c, 0x95, 0x18, 0x85, 0x78, 0xa3, 0x83, - 0x90, 0x28, 0x4c, 0x6c, 0x88, 0x6c, 0xd8, 0xf3, 0xa2, 0x82, 0x00, 0xf2, 0x10, 0xa8, 0x92, 0x19, - 0x80, 0xa2, 0xf2, 0xd9, 0x26, 0xd8, 0xf1, 0x88, 0xa8, 0x4d, 0xd9, 0x48, 0xd8, 0x96, 0xa8, 0x39, - 0x80, 0xd9, 0x3c, 0xd8, 0x95, 0x80, 0xa8, 0x39, 0xa6, 0x86, 0x98, 0xd9, 0x2c, 0xda, 0x87, 0xa7, - 0x2c, 0xd8, 0xa8, 0x89, 0x95, 0x19, 0xa9, 0x80, 0xd9, 0x38, 0xd8, 0xa8, 0x89, 0x39, 0xa9, 0x80, - 0xda, 0x3c, 0xd8, 0xa8, 0x2e, 0xa8, 0x39, 0x90, 0xd9, 0x0c, 0xd8, 0xa8, 0x95, 0x31, 0x98, 0xd9, - 0x0c, 0xd8, 0xa8, 0x09, 0xd9, 0xff, 0xd8, 0x01, 0xda, 0xff, 0xd8, 0x95, 0x39, 0xa9, 0xda, 0x26, - 0xff, 0xd8, 0x90, 0xa8, 0x0d, 0x89, 0x99, 0xa8, 0x10, 0x80, 0x98, 0x21, 0xda, 0x2e, 0xd8, 0x89, - 0x99, 0xa8, 0x31, 0x80, 0xda, 0x2e, 0xd8, 0xa8, 0x86, 0x96, 0x31, 0x80, 0xda, 0x2e, 0xd8, 0xa8, - 0x87, 0x31, 0x80, 0xda, 0x2e, 0xd8, 0xa8, 0x82, 0x92, 0xf3, 0x41, 0x80, 0xf1, 0xd9, 0x2e, 0xd8, - 0xa8, 0x82, 0xf3, 0x19, 0x80, 0xf1, 0xd9, 0x2e, 0xd8, 0x82, 0xac, 0xf3, 0xc0, 0xa2, 0x80, 0x22, - 0xf1, 0xa6, 0x2e, 0xa7, 0x2e, 0xa9, 0x22, 0x98, 0xa8, 0x29, 0xda, 0xac, 0xde, 0xff, 0xd8, 0xa2, - 0xf2, 0x2a, 0xf1, 0xa9, 0x2e, 0x82, 0x92, 0xa8, 0xf2, 0x31, 0x80, 0xa6, 0x96, 0xf1, 0xd9, 0x00, - 0xac, 0x8c, 0x9c, 0x0c, 0x30, 0xac, 0xde, 0xd0, 0xde, 0xff, 0xd8, 0x8c, 0x9c, 0xac, 0xd0, 0x10, - 0xac, 0xde, 0x80, 0x92, 0xa2, 0xf2, 0x4c, 0x82, 0xa8, 0xf1, 0xca, 0xf2, 0x35, 0xf1, 0x96, 0x88, - 0xa6, 0xd9, 0x00, 0xd8, 0xf1, 0xff -}; - -static const unsigned short sStartAddress = 0x0400; - -/* END OF SECTION COPIED FROM dmpDefaultMPU6050.c */ - -#define INT_SRC_TAP (0x01) -#define INT_SRC_ANDROID_ORIENT (0x08) - -#define DMP_FEATURE_SEND_ANY_GYRO (DMP_FEATURE_SEND_RAW_GYRO | \ - DMP_FEATURE_SEND_CAL_GYRO) - -#define MAX_PACKET_LENGTH (32) - -#define DMP_SAMPLE_RATE (200) -#define GYRO_SF (46850825LL * 200 / DMP_SAMPLE_RATE) - -#define FIFO_CORRUPTION_CHECK -#ifdef FIFO_CORRUPTION_CHECK -#define QUAT_ERROR_THRESH (1L << 24) -#define QUAT_MAG_SQ_NORMALIZED (1L << 28) -#define QUAT_MAG_SQ_MIN (QUAT_MAG_SQ_NORMALIZED - QUAT_ERROR_THRESH) -#define QUAT_MAG_SQ_MAX (QUAT_MAG_SQ_NORMALIZED + QUAT_ERROR_THRESH) -#endif - -struct dmp_s { - void (*tap_cb)(unsigned char count, unsigned char direction); - void (*android_orient_cb)(unsigned char orientation); - unsigned short orient; - unsigned short feature_mask; - unsigned short fifo_rate; - unsigned char packet_length; -}; - -static struct dmp_s dmp = { - .tap_cb = NULL, - .android_orient_cb = NULL, - .orient = 0, - .feature_mask = 0, - .fifo_rate = 0, - .packet_length = 0 -}; - -/** - * @brief Load the DMP with this image. - * @return 0 if successful. - */ -int dmp_load_motion_driver_firmware(void) -{ - return mpu_load_firmware(DMP_CODE_SIZE, dmp_memory, sStartAddress, - DMP_SAMPLE_RATE); -} - -/** - * @brief Push gyro and accel orientation to the DMP. - * The orientation is represented here as the output of - * @e inv_orientation_matrix_to_scalar. - * @param[in] orient Gyro and accel orientation in body frame. - * @return 0 if successful. - */ -int dmp_set_orientation(unsigned short orient) -{ - unsigned char gyro_regs[3], accel_regs[3]; - const unsigned char gyro_axes[3] = { DINA4C, DINACD, DINA6C }; - const unsigned char accel_axes[3] = { DINA0C, DINAC9, DINA2C }; - const unsigned char gyro_sign[3] = { DINA36, DINA56, DINA76 }; - const unsigned char accel_sign[3] = { DINA26, DINA46, DINA66 }; - - gyro_regs[0] = gyro_axes[orient & 3]; - gyro_regs[1] = gyro_axes[(orient >> 3) & 3]; - gyro_regs[2] = gyro_axes[(orient >> 6) & 3]; - accel_regs[0] = accel_axes[orient & 3]; - accel_regs[1] = accel_axes[(orient >> 3) & 3]; - accel_regs[2] = accel_axes[(orient >> 6) & 3]; - - /* Chip-to-body, axes only. */ - if (mpu_write_mem(FCFG_1, 3, gyro_regs)) { - return -1; - } - if (mpu_write_mem(FCFG_2, 3, accel_regs)) { - return -1; - } - - memcpy(gyro_regs, gyro_sign, 3); - memcpy(accel_regs, accel_sign, 3); - if (orient & 4) { - gyro_regs[0] |= 1; - accel_regs[0] |= 1; - } - if (orient & 0x20) { - gyro_regs[1] |= 1; - accel_regs[1] |= 1; - } - if (orient & 0x100) { - gyro_regs[2] |= 1; - accel_regs[2] |= 1; - } - - /* Chip-to-body, sign only. */ - if (mpu_write_mem(FCFG_3, 3, gyro_regs)) { - return -1; - } - if (mpu_write_mem(FCFG_7, 3, accel_regs)) { - return -1; - } - dmp.orient = orient; - return 0; -} - -/** - * @brief Push gyro biases to the DMP. - * Because the gyro integration is handled in the DMP, any gyro biases - * calculated by the MPL should be pushed down to DMP memory to remove - * 3-axis quaternion drift. - * @note If the DMP-based gyro calibration is enabled, the DMP will - * overwrite the biases written to this location once a new one is computed. - * @param[in] bias Gyro biases in q16. - * @return 0 if successful. - */ -int dmp_set_gyro_bias(long *bias) -{ - long gyro_bias_body[3]; - unsigned char regs[4]; - - gyro_bias_body[0] = bias[dmp.orient & 3]; - if (dmp.orient & 4) { - gyro_bias_body[0] *= -1; - } - gyro_bias_body[1] = bias[(dmp.orient >> 3) & 3]; - if (dmp.orient & 0x20) { - gyro_bias_body[1] *= -1; - } - gyro_bias_body[2] = bias[(dmp.orient >> 6) & 3]; - if (dmp.orient & 0x100) { - gyro_bias_body[2] *= -1; - } - -#ifdef EMPL_NO_64BIT - gyro_bias_body[0] = (long)(((float)gyro_bias_body[0] * GYRO_SF) / 1073741824.f); - gyro_bias_body[1] = (long)(((float)gyro_bias_body[1] * GYRO_SF) / 1073741824.f); - gyro_bias_body[2] = (long)(((float)gyro_bias_body[2] * GYRO_SF) / 1073741824.f); -#else - gyro_bias_body[0] = (long)(((long long)gyro_bias_body[0] * GYRO_SF) >> 30); - gyro_bias_body[1] = (long)(((long long)gyro_bias_body[1] * GYRO_SF) >> 30); - gyro_bias_body[2] = (long)(((long long)gyro_bias_body[2] * GYRO_SF) >> 30); -#endif - - regs[0] = (unsigned char)((gyro_bias_body[0] >> 24) & 0xFF); - regs[1] = (unsigned char)((gyro_bias_body[0] >> 16) & 0xFF); - regs[2] = (unsigned char)((gyro_bias_body[0] >> 8) & 0xFF); - regs[3] = (unsigned char)(gyro_bias_body[0] & 0xFF); - if (mpu_write_mem(D_EXT_GYRO_BIAS_X, 4, regs)) { - return -1; - } - - regs[0] = (unsigned char)((gyro_bias_body[1] >> 24) & 0xFF); - regs[1] = (unsigned char)((gyro_bias_body[1] >> 16) & 0xFF); - regs[2] = (unsigned char)((gyro_bias_body[1] >> 8) & 0xFF); - regs[3] = (unsigned char)(gyro_bias_body[1] & 0xFF); - if (mpu_write_mem(D_EXT_GYRO_BIAS_Y, 4, regs)) { - return -1; - } - - regs[0] = (unsigned char)((gyro_bias_body[2] >> 24) & 0xFF); - regs[1] = (unsigned char)((gyro_bias_body[2] >> 16) & 0xFF); - regs[2] = (unsigned char)((gyro_bias_body[2] >> 8) & 0xFF); - regs[3] = (unsigned char)(gyro_bias_body[2] & 0xFF); - return mpu_write_mem(D_EXT_GYRO_BIAS_Z, 4, regs); -} - -/** - * @brief Push accel biases to the DMP. - * These biases will be removed from the DMP 6-axis quaternion. - * @param[in] bias Accel biases in q16. - * @return 0 if successful. - */ -int dmp_set_accel_bias(long *bias) -{ - long accel_bias_body[3]; - unsigned char regs[12]; - long long accel_sf; - unsigned short accel_sens; - - mpu_get_accel_sens(&accel_sens); - accel_sf = (long long)accel_sens << 15; - Asm("nop_s");// __no_operation(); - - accel_bias_body[0] = bias[dmp.orient & 3]; - if (dmp.orient & 4) { - accel_bias_body[0] *= -1; - } - accel_bias_body[1] = bias[(dmp.orient >> 3) & 3]; - if (dmp.orient & 0x20) { - accel_bias_body[1] *= -1; - } - accel_bias_body[2] = bias[(dmp.orient >> 6) & 3]; - if (dmp.orient & 0x100) { - accel_bias_body[2] *= -1; - } - -#ifdef EMPL_NO_64BIT - accel_bias_body[0] = (long)(((float)accel_bias_body[0] * accel_sf) / 1073741824.f); - accel_bias_body[1] = (long)(((float)accel_bias_body[1] * accel_sf) / 1073741824.f); - accel_bias_body[2] = (long)(((float)accel_bias_body[2] * accel_sf) / 1073741824.f); -#else - accel_bias_body[0] = (long)(((long long)accel_bias_body[0] * accel_sf) >> 30); - accel_bias_body[1] = (long)(((long long)accel_bias_body[1] * accel_sf) >> 30); - accel_bias_body[2] = (long)(((long long)accel_bias_body[2] * accel_sf) >> 30); -#endif - - regs[0] = (unsigned char)((accel_bias_body[0] >> 24) & 0xFF); - regs[1] = (unsigned char)((accel_bias_body[0] >> 16) & 0xFF); - regs[2] = (unsigned char)((accel_bias_body[0] >> 8) & 0xFF); - regs[3] = (unsigned char)(accel_bias_body[0] & 0xFF); - regs[4] = (unsigned char)((accel_bias_body[1] >> 24) & 0xFF); - regs[5] = (unsigned char)((accel_bias_body[1] >> 16) & 0xFF); - regs[6] = (unsigned char)((accel_bias_body[1] >> 8) & 0xFF); - regs[7] = (unsigned char)(accel_bias_body[1] & 0xFF); - regs[8] = (unsigned char)((accel_bias_body[2] >> 24) & 0xFF); - regs[9] = (unsigned char)((accel_bias_body[2] >> 16) & 0xFF); - regs[10] = (unsigned char)((accel_bias_body[2] >> 8) & 0xFF); - regs[11] = (unsigned char)(accel_bias_body[2] & 0xFF); - return mpu_write_mem(D_ACCEL_BIAS, 12, regs); -} - -/** - * @brief Set DMP output rate. - * Only used when DMP is on. - * @param[in] rate Desired fifo rate (Hz). - * @return 0 if successful. - */ -int dmp_set_fifo_rate(unsigned short rate) -{ - const unsigned char regs_end[12] = { DINAFE, DINAF2, DINAAB, - 0xc4, DINAAA, DINAF1, DINADF, DINADF, 0xBB, 0xAF, DINADF, DINADF }; - unsigned short div; - unsigned char tmp[8]; - - if (rate > DMP_SAMPLE_RATE) { - return -1; - } - div = DMP_SAMPLE_RATE / rate - 1; - tmp[0] = (unsigned char)((div >> 8) & 0xFF); - tmp[1] = (unsigned char)(div & 0xFF); - if (mpu_write_mem(D_0_22, 2, tmp)) { - return -1; - } - if (mpu_write_mem(CFG_6, 12, (unsigned char *)regs_end)) { - return -1; - } - - dmp.fifo_rate = rate; - return 0; -} - -/** - * @brief Get DMP output rate. - * @param[out] rate Current fifo rate (Hz). - * @return 0 if successful. - */ -int dmp_get_fifo_rate(unsigned short *rate) -{ - rate[0] = dmp.fifo_rate; - return 0; -} - -/** - * @brief Set tap threshold for a specific axis. - * @param[in] axis 1, 2, and 4 for XYZ accel, respectively. - * @param[in] thresh Tap threshold, in mg/ms. - * @return 0 if successful. - */ -int dmp_set_tap_thresh(unsigned char axis, unsigned short thresh) -{ - unsigned char tmp[4], accel_fsr; - float scaled_thresh; - unsigned short dmp_thresh, dmp_thresh_2; - - if (!(axis & TAP_XYZ) || thresh > 1600) { - return -1; - } - - scaled_thresh = (float)thresh / DMP_SAMPLE_RATE; - - mpu_get_accel_fsr(&accel_fsr); - switch (accel_fsr) { - case 2: - dmp_thresh = (unsigned short)(scaled_thresh * 16384); - /* dmp_thresh * 0.75 */ - dmp_thresh_2 = (unsigned short)(scaled_thresh * 12288); - break; - case 4: - dmp_thresh = (unsigned short)(scaled_thresh * 8192); - /* dmp_thresh * 0.75 */ - dmp_thresh_2 = (unsigned short)(scaled_thresh * 6144); - break; - case 8: - dmp_thresh = (unsigned short)(scaled_thresh * 4096); - /* dmp_thresh * 0.75 */ - dmp_thresh_2 = (unsigned short)(scaled_thresh * 3072); - break; - case 16: - dmp_thresh = (unsigned short)(scaled_thresh * 2048); - /* dmp_thresh * 0.75 */ - dmp_thresh_2 = (unsigned short)(scaled_thresh * 1536); - break; - default: - return -1; - } - tmp[0] = (unsigned char)(dmp_thresh >> 8); - tmp[1] = (unsigned char)(dmp_thresh & 0xFF); - tmp[2] = (unsigned char)(dmp_thresh_2 >> 8); - tmp[3] = (unsigned char)(dmp_thresh_2 & 0xFF); - - if (axis & TAP_X) { - if (mpu_write_mem(DMP_TAP_THX, 2, tmp)) { - return -1; - } - if (mpu_write_mem(D_1_36, 2, tmp + 2)) { - return -1; - } - } - if (axis & TAP_Y) { - if (mpu_write_mem(DMP_TAP_THY, 2, tmp)) { - return -1; - } - if (mpu_write_mem(D_1_40, 2, tmp + 2)) { - return -1; - } - } - if (axis & TAP_Z) { - if (mpu_write_mem(DMP_TAP_THZ, 2, tmp)) { - return -1; - } - if (mpu_write_mem(D_1_44, 2, tmp + 2)) { - return -1; - } - } - return 0; -} - -/** - * @brief Set which axes will register a tap. - * @param[in] axis 1, 2, and 4 for XYZ, respectively. - * @return 0 if successful. - */ -int dmp_set_tap_axes(unsigned char axis) -{ - unsigned char tmp = 0; - - if (axis & TAP_X) { - tmp |= 0x30; - } - if (axis & TAP_Y) { - tmp |= 0x0C; - } - if (axis & TAP_Z) { - tmp |= 0x03; - } - return mpu_write_mem(D_1_72, 1, &tmp); -} - -/** - * @brief Set minimum number of taps needed for an interrupt. - * @param[in] min_taps Minimum consecutive taps (1-4). - * @return 0 if successful. - */ -int dmp_set_tap_count(unsigned char min_taps) -{ - unsigned char tmp; - - if (min_taps < 1) { - min_taps = 1; - } else if (min_taps > 4) { - min_taps = 4; - } - - tmp = min_taps - 1; - return mpu_write_mem(D_1_79, 1, &tmp); -} - -/** - * @brief Set length between valid taps. - * @param[in] time Milliseconds between taps. - * @return 0 if successful. - */ -int dmp_set_tap_time(unsigned short time) -{ - unsigned short dmp_time; - unsigned char tmp[2]; - - dmp_time = time / (1000 / DMP_SAMPLE_RATE); - tmp[0] = (unsigned char)(dmp_time >> 8); - tmp[1] = (unsigned char)(dmp_time & 0xFF); - return mpu_write_mem(DMP_TAPW_MIN, 2, tmp); -} - -/** - * @brief Set max time between taps to register as a multi-tap. - * @param[in] time Max milliseconds between taps. - * @return 0 if successful. - */ -int dmp_set_tap_time_multi(unsigned short time) -{ - unsigned short dmp_time; - unsigned char tmp[2]; - - dmp_time = time / (1000 / DMP_SAMPLE_RATE); - tmp[0] = (unsigned char)(dmp_time >> 8); - tmp[1] = (unsigned char)(dmp_time & 0xFF); - return mpu_write_mem(D_1_218, 2, tmp); -} - -/** - * @brief Set shake rejection threshold. - * If the DMP detects a gyro sample larger than @e thresh, taps are rejected. - * @param[in] sf Gyro scale factor. - * @param[in] thresh Gyro threshold in dps. - * @return 0 if successful. - */ -int dmp_set_shake_reject_thresh(long sf, unsigned short thresh) -{ - unsigned char tmp[4]; - long thresh_scaled = sf / 1000 * thresh; - - tmp[0] = (unsigned char)(((long)thresh_scaled >> 24) & 0xFF); - tmp[1] = (unsigned char)(((long)thresh_scaled >> 16) & 0xFF); - tmp[2] = (unsigned char)(((long)thresh_scaled >> 8) & 0xFF); - tmp[3] = (unsigned char)((long)thresh_scaled & 0xFF); - return mpu_write_mem(D_1_92, 4, tmp); -} - -/** - * @brief Set shake rejection time. - * Sets the length of time that the gyro must be outside of the threshold set - * by @e gyro_set_shake_reject_thresh before taps are rejected. A mandatory - * 60 ms is added to this parameter. - * @param[in] time Time in milliseconds. - * @return 0 if successful. - */ -int dmp_set_shake_reject_time(unsigned short time) -{ - unsigned char tmp[2]; - - time /= (1000 / DMP_SAMPLE_RATE); - tmp[0] = time >> 8; - tmp[1] = time & 0xFF; - return mpu_write_mem(D_1_90, 2, tmp); -} - -/** - * @brief Set shake rejection timeout. - * Sets the length of time after a shake rejection that the gyro must stay - * inside of the threshold before taps can be detected again. A mandatory - * 60 ms is added to this parameter. - * @param[in] time Time in milliseconds. - * @return 0 if successful. - */ -int dmp_set_shake_reject_timeout(unsigned short time) -{ - unsigned char tmp[2]; - - time /= (1000 / DMP_SAMPLE_RATE); - tmp[0] = time >> 8; - tmp[1] = time & 0xFF; - return mpu_write_mem(D_1_88, 2, tmp); -} - -/** - * @brief Get current step count. - * @param[out] count Number of steps detected. - * @return 0 if successful. - */ -int dmp_get_pedometer_step_count(unsigned long *count) -{ - unsigned char tmp[4]; - - if (!count) { - return -1; - } - - if (mpu_read_mem(D_PEDSTD_STEPCTR, 4, tmp)) { - return -1; - } - - count[0] = ((unsigned long)tmp[0] << 24) | ((unsigned long)tmp[1] << 16) | - ((unsigned long)tmp[2] << 8) | tmp[3]; - return 0; -} - -/** - * @brief Overwrite current step count. - * WARNING: This function writes to DMP memory and could potentially encounter - * a race condition if called while the pedometer is enabled. - * @param[in] count New step count. - * @return 0 if successful. - */ -int dmp_set_pedometer_step_count(unsigned long count) -{ - unsigned char tmp[4]; - - tmp[0] = (unsigned char)((count >> 24) & 0xFF); - tmp[1] = (unsigned char)((count >> 16) & 0xFF); - tmp[2] = (unsigned char)((count >> 8) & 0xFF); - tmp[3] = (unsigned char)(count & 0xFF); - return mpu_write_mem(D_PEDSTD_STEPCTR, 4, tmp); -} - -/** - * @brief Get duration of walking time. - * @param[in] time Walk time in milliseconds. - * @return 0 if successful. - */ -int dmp_get_pedometer_walk_time(unsigned long *time) -{ - unsigned char tmp[4]; - - if (!time) { - return -1; - } - - if (mpu_read_mem(D_PEDSTD_TIMECTR, 4, tmp)) { - return -1; - } - - time[0] = (((unsigned long)tmp[0] << 24) | ((unsigned long)tmp[1] << 16) | - ((unsigned long)tmp[2] << 8) | tmp[3]) * 20; - return 0; -} - -/** - * @brief Overwrite current walk time. - * WARNING: This function writes to DMP memory and could potentially encounter - * a race condition if called while the pedometer is enabled. - * @param[in] time New walk time in milliseconds. - */ -int dmp_set_pedometer_walk_time(unsigned long time) -{ - unsigned char tmp[4]; - - time /= 20; - - tmp[0] = (unsigned char)((time >> 24) & 0xFF); - tmp[1] = (unsigned char)((time >> 16) & 0xFF); - tmp[2] = (unsigned char)((time >> 8) & 0xFF); - tmp[3] = (unsigned char)(time & 0xFF); - return mpu_write_mem(D_PEDSTD_TIMECTR, 4, tmp); -} - -/** - * @brief Enable DMP features. - * The following \#define's are used in the input mask: - * @n DMP_FEATURE_TAP - * @n DMP_FEATURE_ANDROID_ORIENT - * @n DMP_FEATURE_LP_QUAT - * @n DMP_FEATURE_6X_LP_QUAT - * @n DMP_FEATURE_GYRO_CAL - * @n DMP_FEATURE_SEND_RAW_ACCEL - * @n DMP_FEATURE_SEND_RAW_GYRO - * @note DMP_FEATURE_LP_QUAT and DMP_FEATURE_6X_LP_QUAT are mutually - * exclusive. - * @note DMP_FEATURE_SEND_RAW_GYRO and DMP_FEATURE_SEND_CAL_GYRO are also - * mutually exclusive. - * @param[in] mask Mask of features to enable. - * @return 0 if successful. - */ -int dmp_enable_feature(unsigned short mask) -{ - unsigned char tmp[10]; - - /* TODO: All of these settings can probably be integrated into the default - * DMP image. - */ - /* Set integration scale factor. */ - tmp[0] = (unsigned char)((GYRO_SF >> 24) & 0xFF); - tmp[1] = (unsigned char)((GYRO_SF >> 16) & 0xFF); - tmp[2] = (unsigned char)((GYRO_SF >> 8) & 0xFF); - tmp[3] = (unsigned char)(GYRO_SF & 0xFF); - mpu_write_mem(D_0_104, 4, tmp); - - /* Send sensor data to the FIFO. */ - tmp[0] = 0xA3; - if (mask & DMP_FEATURE_SEND_RAW_ACCEL) { - tmp[1] = 0xC0; - tmp[2] = 0xC8; - tmp[3] = 0xC2; - } else { - tmp[1] = 0xA3; - tmp[2] = 0xA3; - tmp[3] = 0xA3; - } - if (mask & DMP_FEATURE_SEND_ANY_GYRO) { - tmp[4] = 0xC4; - tmp[5] = 0xCC; - tmp[6] = 0xC6; - } else { - tmp[4] = 0xA3; - tmp[5] = 0xA3; - tmp[6] = 0xA3; - } - tmp[7] = 0xA3; - tmp[8] = 0xA3; - tmp[9] = 0xA3; - mpu_write_mem(CFG_15, 10, tmp); - - /* Send gesture data to the FIFO. */ - if (mask & (DMP_FEATURE_TAP | DMP_FEATURE_ANDROID_ORIENT)) { - tmp[0] = DINA20; - } else { - tmp[0] = 0xD8; - } - mpu_write_mem(CFG_27, 1, tmp); - - if (mask & DMP_FEATURE_GYRO_CAL) { - dmp_enable_gyro_cal(1); - } else { - dmp_enable_gyro_cal(0); - } - - if (mask & DMP_FEATURE_SEND_ANY_GYRO) { - if (mask & DMP_FEATURE_SEND_CAL_GYRO) { - tmp[0] = 0xB2; - tmp[1] = 0x8B; - tmp[2] = 0xB6; - tmp[3] = 0x9B; - } else { - tmp[0] = DINAC0; - tmp[1] = DINA80; - tmp[2] = DINAC2; - tmp[3] = DINA90; - } - mpu_write_mem(CFG_GYRO_RAW_DATA, 4, tmp); - } - - if (mask & DMP_FEATURE_TAP) { - /* Enable tap. */ - tmp[0] = 0xF8; - mpu_write_mem(CFG_20, 1, tmp); - dmp_set_tap_thresh(TAP_XYZ, 250); - dmp_set_tap_axes(TAP_XYZ); - dmp_set_tap_count(1); - dmp_set_tap_time(100); - dmp_set_tap_time_multi(500); - - dmp_set_shake_reject_thresh(GYRO_SF, 200); - dmp_set_shake_reject_time(40); - dmp_set_shake_reject_timeout(10); - } else { - tmp[0] = 0xD8; - mpu_write_mem(CFG_20, 1, tmp); - } - - if (mask & DMP_FEATURE_ANDROID_ORIENT) { - tmp[0] = 0xD9; - } else { - tmp[0] = 0xD8; - } - mpu_write_mem(CFG_ANDROID_ORIENT_INT, 1, tmp); - - if (mask & DMP_FEATURE_LP_QUAT) { - dmp_enable_lp_quat(1); - } else { - dmp_enable_lp_quat(0); - } - - if (mask & DMP_FEATURE_6X_LP_QUAT) { - dmp_enable_6x_lp_quat(1); - } else { - dmp_enable_6x_lp_quat(0); - } - - /* Pedometer is always enabled. */ - dmp.feature_mask = mask | DMP_FEATURE_PEDOMETER; - mpu_reset_fifo(); - - dmp.packet_length = 0; - if (mask & DMP_FEATURE_SEND_RAW_ACCEL) { - dmp.packet_length += 6; - } - if (mask & DMP_FEATURE_SEND_ANY_GYRO) { - dmp.packet_length += 6; - } - if (mask & (DMP_FEATURE_LP_QUAT | DMP_FEATURE_6X_LP_QUAT)) { - dmp.packet_length += 16; - } - if (mask & (DMP_FEATURE_TAP | DMP_FEATURE_ANDROID_ORIENT)) { - dmp.packet_length += 4; - } - - return 0; -} - -/** - * @brief Get list of currently enabled DMP features. - * @param[out] Mask of enabled features. - * @return 0 if successful. - */ -int dmp_get_enabled_features(unsigned short *mask) -{ - mask[0] = dmp.feature_mask; - return 0; -} - -/** - * @brief Calibrate the gyro data in the DMP. - * After eight seconds of no motion, the DMP will compute gyro biases and - * subtract them from the quaternion output. If @e dmp_enable_feature is - * called with @e DMP_FEATURE_SEND_CAL_GYRO, the biases will also be - * subtracted from the gyro output. - * @param[in] enable 1 to enable gyro calibration. - * @return 0 if successful. - */ -int dmp_enable_gyro_cal(unsigned char enable) -{ - if (enable) { - unsigned char regs[9] = { 0xb8, 0xaa, 0xb3, 0x8d, 0xb4, 0x98, 0x0d, 0x35, 0x5d }; - return mpu_write_mem(CFG_MOTION_BIAS, 9, regs); - } else { - unsigned char regs[9] = { 0xb8, 0xaa, 0xaa, 0xaa, 0xb0, 0x88, 0xc3, 0xc5, 0xc7 }; - return mpu_write_mem(CFG_MOTION_BIAS, 9, regs); - } -} - -/** - * @brief Generate 3-axis quaternions from the DMP. - * In this driver, the 3-axis and 6-axis DMP quaternion features are mutually - * exclusive. - * @param[in] enable 1 to enable 3-axis quaternion. - * @return 0 if successful. - */ -int dmp_enable_lp_quat(unsigned char enable) -{ - unsigned char regs[4]; - - if (enable) { - regs[0] = DINBC0; - regs[1] = DINBC2; - regs[2] = DINBC4; - regs[3] = DINBC6; - } else { - memset(regs, 0x8B, 4); - } - - mpu_write_mem(CFG_LP_QUAT, 4, regs); - - return mpu_reset_fifo(); -} - -/** - * @brief Generate 6-axis quaternions from the DMP. - * In this driver, the 3-axis and 6-axis DMP quaternion features are mutually - * exclusive. - * @param[in] enable 1 to enable 6-axis quaternion. - * @return 0 if successful. - */ -int dmp_enable_6x_lp_quat(unsigned char enable) -{ - unsigned char regs[4]; - - if (enable) { - regs[0] = DINA20; - regs[1] = DINA28; - regs[2] = DINA30; - regs[3] = DINA38; - } else { - memset(regs, 0xA3, 4); - } - - mpu_write_mem(CFG_8, 4, regs); - - return mpu_reset_fifo(); -} - -/** - * @brief Decode the four-byte gesture data and execute any callbacks. - * @param[in] gesture Gesture data from DMP packet. - * @return 0 if successful. - */ -static int decode_gesture(unsigned char *gesture) -{ - unsigned char tap, android_orient; - - android_orient = gesture[3] & 0xC0; - tap = 0x3F & gesture[3]; - - if (gesture[1] & INT_SRC_TAP) { - unsigned char direction, count; - direction = tap >> 3; - count = (tap % 8) + 1; - if (dmp.tap_cb) { - dmp.tap_cb(direction, count); - } - } - - if (gesture[1] & INT_SRC_ANDROID_ORIENT) { - if (dmp.android_orient_cb) { - dmp.android_orient_cb(android_orient >> 6); - } - } - - return 0; -} - -/** - * @brief Specify when a DMP interrupt should occur. - * A DMP interrupt can be configured to trigger on either of the two - * conditions below: - * @n a. One FIFO period has elapsed (set by @e mpu_set_sample_rate). - * @n b. A tap event has been detected. - * @param[in] mode DMP_INT_GESTURE or DMP_INT_CONTINUOUS. - * @return 0 if successful. - */ -int dmp_set_interrupt_mode(unsigned char mode) -{ - const unsigned char regs_continuous[11] = - { 0xd8, 0xb1, 0xb9, 0xf3, 0x8b, 0xa3, 0x91, 0xb6, 0x09, 0xb4, 0xd9 }; - const unsigned char regs_gesture[11] = - { 0xda, 0xb1, 0xb9, 0xf3, 0x8b, 0xa3, 0x91, 0xb6, 0xda, 0xb4, 0xda }; - - switch (mode) { - case DMP_INT_CONTINUOUS: - return mpu_write_mem(CFG_FIFO_ON_EVENT, 11, - (unsigned char *)regs_continuous); - case DMP_INT_GESTURE: - return mpu_write_mem(CFG_FIFO_ON_EVENT, 11, - (unsigned char *)regs_gesture); - default: - return -1; - } -} - -/** - * @brief Get one packet from the FIFO. - * If @e sensors does not contain a particular sensor, disregard the data - * returned to that pointer. - * @n @e sensors can contain a combination of the following flags: - * @n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO - * @n INV_XYZ_GYRO - * @n INV_XYZ_ACCEL - * @n INV_WXYZ_QUAT - * @n If the FIFO has no new data, @e sensors will be zero. - * @n If the FIFO is disabled, @e sensors will be zero and this function will - * return a non-zero error code. - * @param[out] gyro Gyro data in hardware units. - * @param[out] accel Accel data in hardware units. - * @param[out] quat 3-axis quaternion data in hardware units. - * @param[out] timestamp Timestamp in milliseconds. - * @param[out] sensors Mask of sensors read from FIFO. - * @param[out] more Number of remaining packets. - * @return 0 if successful. - */ -int dmp_read_fifo(short *gyro, short *accel, long *quat, - unsigned long *timestamp, short *sensors, unsigned char *more) -{ - unsigned char fifo_data[MAX_PACKET_LENGTH]; - unsigned char ii = 0; - - /* TODO: sensors[0] only changes when dmp_enable_feature is called. We can - * cache this value and save some cycles. - */ - sensors[0] = 0; - - /* Get a packet. */ - if (mpu_read_fifo_stream(dmp.packet_length, fifo_data, more)) { - return -1; - } - - /* Parse DMP packet. */ - if (dmp.feature_mask & (DMP_FEATURE_LP_QUAT | DMP_FEATURE_6X_LP_QUAT)) { -#ifdef FIFO_CORRUPTION_CHECK - long quat_q14[4], quat_mag_sq; -#endif - quat[0] = ((long)fifo_data[0] << 24) | ((long)fifo_data[1] << 16) | - ((long)fifo_data[2] << 8) | fifo_data[3]; - quat[1] = ((long)fifo_data[4] << 24) | ((long)fifo_data[5] << 16) | - ((long)fifo_data[6] << 8) | fifo_data[7]; - quat[2] = ((long)fifo_data[8] << 24) | ((long)fifo_data[9] << 16) | - ((long)fifo_data[10] << 8) | fifo_data[11]; - quat[3] = ((long)fifo_data[12] << 24) | ((long)fifo_data[13] << 16) | - ((long)fifo_data[14] << 8) | fifo_data[15]; - ii += 16; -#ifdef FIFO_CORRUPTION_CHECK - /* We can detect a corrupted FIFO by monitoring the quaternion data and - * ensuring that the magnitude is always normalized to one. This - * shouldn't happen in normal operation, but if an I2C error occurs, - * the FIFO reads might become misaligned. - * - * Let's start by scaling down the quaternion data to avoid long long - * math. - */ - quat_q14[0] = quat[0] >> 16; - quat_q14[1] = quat[1] >> 16; - quat_q14[2] = quat[2] >> 16; - quat_q14[3] = quat[3] >> 16; - quat_mag_sq = quat_q14[0] * quat_q14[0] + quat_q14[1] * quat_q14[1] + - quat_q14[2] * quat_q14[2] + quat_q14[3] * quat_q14[3]; - if ((quat_mag_sq < QUAT_MAG_SQ_MIN) || - (quat_mag_sq > QUAT_MAG_SQ_MAX)) { - /* Quaternion is outside of the acceptable threshold. */ - mpu_reset_fifo(); - sensors[0] = 0; - return -1; - } - sensors[0] |= INV_WXYZ_QUAT; -#endif - } - - if (dmp.feature_mask & DMP_FEATURE_SEND_RAW_ACCEL) { - accel[0] = ((short)fifo_data[ii + 0] << 8) | fifo_data[ii + 1]; - accel[1] = ((short)fifo_data[ii + 2] << 8) | fifo_data[ii + 3]; - accel[2] = ((short)fifo_data[ii + 4] << 8) | fifo_data[ii + 5]; - ii += 6; - sensors[0] |= INV_XYZ_ACCEL; - } - - if (dmp.feature_mask & DMP_FEATURE_SEND_ANY_GYRO) { - gyro[0] = ((short)fifo_data[ii + 0] << 8) | fifo_data[ii + 1]; - gyro[1] = ((short)fifo_data[ii + 2] << 8) | fifo_data[ii + 3]; - gyro[2] = ((short)fifo_data[ii + 4] << 8) | fifo_data[ii + 5]; - ii += 6; - sensors[0] |= INV_XYZ_GYRO; - } - - /* Gesture data is at the end of the DMP packet. Parse it and call - * the gesture callbacks (if registered). - */ - if (dmp.feature_mask & (DMP_FEATURE_TAP | DMP_FEATURE_ANDROID_ORIENT)) { - decode_gesture(fifo_data + ii); - } - - get_ms(timestamp); - return 0; -} - -/** - * @brief Register a function to be executed on a tap event. - * The tap direction is represented by one of the following: - * @n TAP_X_UP - * @n TAP_X_DOWN - * @n TAP_Y_UP - * @n TAP_Y_DOWN - * @n TAP_Z_UP - * @n TAP_Z_DOWN - * @param[in] func Callback function. - * @return 0 if successful. - */ -int dmp_register_tap_cb(void (*func)(unsigned char, unsigned char)) -{ - dmp.tap_cb = func; - return 0; -} - -/** - * @brief Register a function to be executed on a android orientation event. - * @param[in] func Callback function. - * @return 0 if successful. - */ -int dmp_register_android_orient_cb(void (*func)(unsigned char)) -{ - dmp.android_orient_cb = func; - return 0; -} - -/** - * @} - */ diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu_dmp_motion_driver.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu_dmp_motion_driver.h deleted file mode 100644 index 189d3eb3..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/inv_mpu_dmp_motion_driver.h +++ /dev/null @@ -1,126 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/* - $License: - Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. - See included License.txt for License information. - $ - */ -/** - * @addtogroup DRIVERS Sensor Driver Layer - * @brief Hardware drivers to communicate with sensors via I2C. - * - * @{ - * @file inv_mpu_dmp_motion_driver.h - * @brief DMP image and interface functions. - * @details All functions are preceded by the dmp_ prefix to - * differentiate among MPL and general driver function calls. - */ -#ifndef _INV_MPU_DMP_MOTION_DRIVER_H_ -#define _INV_MPU_DMP_MOTION_DRIVER_H_ - -#define TAP_X (0x01) -#define TAP_Y (0x02) -#define TAP_Z (0x04) -#define TAP_XYZ (0x07) - -#define TAP_X_UP (0x01) -#define TAP_X_DOWN (0x02) -#define TAP_Y_UP (0x03) -#define TAP_Y_DOWN (0x04) -#define TAP_Z_UP (0x05) -#define TAP_Z_DOWN (0x06) - -#define ANDROID_ORIENT_PORTRAIT (0x00) -#define ANDROID_ORIENT_LANDSCAPE (0x01) -#define ANDROID_ORIENT_REVERSE_PORTRAIT (0x02) -#define ANDROID_ORIENT_REVERSE_LANDSCAPE (0x03) - -#define DMP_INT_GESTURE (0x01) -#define DMP_INT_CONTINUOUS (0x02) - -#define DMP_FEATURE_TAP (0x001) -#define DMP_FEATURE_ANDROID_ORIENT (0x002) -#define DMP_FEATURE_LP_QUAT (0x004) -#define DMP_FEATURE_PEDOMETER (0x008) -#define DMP_FEATURE_6X_LP_QUAT (0x010) -#define DMP_FEATURE_GYRO_CAL (0x020) -#define DMP_FEATURE_SEND_RAW_ACCEL (0x040) -#define DMP_FEATURE_SEND_RAW_GYRO (0x080) -#define DMP_FEATURE_SEND_CAL_GYRO (0x100) - -#define INV_WXYZ_QUAT (0x100) - -/* Set up functions. */ -int dmp_load_motion_driver_firmware(void); -int dmp_set_fifo_rate(unsigned short rate); -int dmp_get_fifo_rate(unsigned short *rate); -int dmp_enable_feature(unsigned short mask); -int dmp_get_enabled_features(unsigned short *mask); -int dmp_set_interrupt_mode(unsigned char mode); -int dmp_set_orientation(unsigned short orient); -int dmp_set_gyro_bias(long *bias); -int dmp_set_accel_bias(long *bias); - -/* Tap functions. */ -int dmp_register_tap_cb(void (*func)(unsigned char, unsigned char)); -int dmp_set_tap_thresh(unsigned char axis, unsigned short thresh); -int dmp_set_tap_axes(unsigned char axis); -int dmp_set_tap_count(unsigned char min_taps); -int dmp_set_tap_time(unsigned short time); -int dmp_set_tap_time_multi(unsigned short time); -int dmp_set_shake_reject_thresh(long sf, unsigned short thresh); -int dmp_set_shake_reject_time(unsigned short time); -int dmp_set_shake_reject_timeout(unsigned short time); - -/* Android orientation functions. */ -int dmp_register_android_orient_cb(void (*func)(unsigned char)); - -/* LP quaternion functions. */ -int dmp_enable_lp_quat(unsigned char enable); -int dmp_enable_6x_lp_quat(unsigned char enable); - -/* Pedometer functions. */ -int dmp_get_pedometer_step_count(unsigned long *count); -int dmp_set_pedometer_step_count(unsigned long count); -int dmp_get_pedometer_walk_time(unsigned long *time); -int dmp_set_pedometer_walk_time(unsigned long time); - -/* DMP gyro calibration functions. */ -int dmp_enable_gyro_cal(unsigned char enable); - -/* Read function. This function should be called whenever the MPU interrupt is - * detected. - */ -int dmp_read_fifo(short *gyro, short *accel, long *quat, - unsigned long *timestamp, short *sensors, unsigned char *more); - -#endif /* #ifndef _INV_MPU_DMP_MOTION_DRIVER_H_ */ - diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.c b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.c deleted file mode 100644 index 3f72902a..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.c +++ /dev/null @@ -1,473 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include "arc/arc.h" -#include "arc/arc_builtin.h" -#include "embARC_toolchain.h" -#include "embARC_error.h" -#include "embARC_debug.h" - -#include "device/ip_hal/dev_iic.h" -#include "mpu9250.h" -#include "board.h" - -#include "inv_mpu.h" -#include "inv_mpu_dmp_motion_driver.h" -#include -#define DEFAULT_MPU_HZ 200 -// **************************************** -#define SMPLRT_DIV 0x19 -#define CONFIG 0x1A -#define GYRO_CONFIG 0x1B -#define ACCEL_CONFIG 0x1C -#define ACCEL_CONFIG_2 0x1D -#define INT_PIN_CFG 0x37 -#define INT_ENABLE 0x38 -#define USER_CTRL 0x6A -#define PWR_MGMT_1 0x6B -#define PWR_MGMT_2 0x6C -#define MAG_CTRL 0x0A - -#define MPU_WIM 0x75 -#define MPU_ID 0x71 - -#define MAG_WIM 0x00 -#define MAG_ID 0x48 - -#define ACCEL_XOUT_H 0x3B -#define GYRO_XOUT_H 0x43 -#define MAG_XOUT_L 0x03 - -#ifdef MPU9250_USE_DMP -MPU9250_DEF_PTR mpu9250_ptr; -static signed char gyro_orientation[9] = { 1, 0, 0, - 0, 1, 0, - 0, 0, 1 }; -static inline unsigned short inv_row_2_scale(const signed char *row) -{ - unsigned short b; - - if (row[0] > 0) { - b = 0; - } else if (row[0] < 0) { - b = 4; - } else if (row[1] > 0) { - b = 1; - } else if (row[1] < 0) { - b = 5; - } else if (row[2] > 0) { - b = 2; - } else if (row[2] < 0) { - b = 6; - } else { - b = 7; // error - } - - return b; -} - -static inline unsigned short inv_orientation_matrix_to_scalar(const signed char *mtx) -{ - unsigned short scalar; - - /* - XYZ 010_001_000 Identity Matrix - XZY 001_010_000 - YXZ 010_000_001 - YZX 000_010_001 - ZXY 001_000_010 - ZYX 000_001_010 - */ - scalar = inv_row_2_scale(mtx); - scalar |= inv_row_2_scale(mtx + 3) << 3; - scalar |= inv_row_2_scale(mtx + 6) << 6; - - return scalar; -} -static inline void run_self_test(void) -{ - int result; - long gyro[3], accel[3]; - unsigned char i = 0; - - result = mpu_run_6500_self_test(gyro, accel, 1); - EMBARC_PRINTF("mpu run self test, result = %d\r\n"); - - if (result == 0x7) { - for (i = 0; i < 3; i++) { - gyro[i] = (long)(gyro[i] * 32.8f); // convert to +-1000dps - accel[i] *= 2048.f; // convert to +-16G - accel[i] = accel[i] >> 16; - gyro[i] = (long)(gyro[i] >> 16); - } - - mpu_set_gyro_bias_reg(gyro); - mpu_set_accel_bias_6500_reg(accel); - } -} -#endif - -#define MPU9250_CHECK_EXP_NORTN(EXPR) CHECK_EXP_NOERCD(EXPR, error_exit) - -static int32_t _mpu_reg_write(MPU9250_DEF_PTR obj, uint32_t slaveaddr, uint8_t regaddr, uint8_t *val, uint8_t len) -{ - int32_t ercd = E_PAR; - uint8_t data[1]; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - dbg_printf(DBG_LESS_INFO, "[%s]%d: obj 0x%x, regaddr 0x%x, val 0x%x\r\n", __FUNCTION__, __LINE__, obj, regaddr, *val); - dbg_printf(DBG_MORE_INFO, "[%s]%d: iic_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, iic_obj, *iic_obj); - MPU9250_CHECK_EXP_NORTN(iic_obj != NULL); - - data[0] = (uint8_t)(regaddr & 0xff); - - iic_obj->iic_control(IIC_CMD_MST_SET_TAR_ADDR, CONV2VOID(slaveaddr)); - - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_RESTART)); - ercd = iic_obj->iic_write(data, 1); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_STOP)); - ercd = iic_obj->iic_write(val, len); - -error_exit: - return ercd; -} - -static int32_t _mpu_reg_read(MPU9250_DEF_PTR obj, uint32_t slaveaddr, uint8_t regaddr, uint8_t *val, uint8_t len) -{ - int32_t ercd = E_PAR; - uint8_t data[1]; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - dbg_printf(DBG_MORE_INFO, "[%s]%d: iic_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, iic_obj, *iic_obj); - MPU9250_CHECK_EXP_NORTN(iic_obj != NULL); - - data[0] = (uint8_t)(regaddr & 0xff); - - iic_obj->iic_control(IIC_CMD_MST_SET_TAR_ADDR, CONV2VOID(slaveaddr)); - - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_RESTART)); - ercd = iic_obj->iic_write(data, 1); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_STOP)); - ercd = iic_obj->iic_read(val, len); - -error_exit: - return ercd; -} - -int32_t mpu9250_sensor_init(MPU9250_DEF_PTR obj) -{ - int32_t ercd = E_OK; - - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - dbg_printf(DBG_MORE_INFO, "[%s]%d: iic_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, iic_obj, *iic_obj); - MPU9250_CHECK_EXP_NORTN(iic_obj != NULL); - - ercd = iic_obj->iic_open(DEV_MASTER_MODE, IIC_SPEED_STANDARD); - - if ((ercd == E_OK) || (ercd == E_OPNED)) { -#ifndef MPU9250_USE_DMP - uint8_t config; - uint8_t data[0]; - config = 0x80; - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, PWR_MGMT_1, &config, 1);// 0x6B - board_delay_ms(100); - - /* - * get stable time source; Auto select clock source to be PLL gyroscope reference if ready - * else use the internal oscillator - */ - config = 0x01; - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, PWR_MGMT_1, &config, 1); - config = 0x00; - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, PWR_MGMT_2, &config, 1); - /* no i2c master */ - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, USER_CTRL, &config, 1); - board_delay_ms(200); - - ercd = _mpu_reg_read(obj, obj->mpu_slvaddr, MPU_WIM, data, 1); - - if (data[0] != MPU_ID) { - dbg_printf(DBG_MORE_INFO, "mpu init failed\r\n"); - return E_SYS; - } - - config = 0x07; // SAMPLE_RATE=Internal_Sample_Rate(1khz) / (1 + SMPLRT_DIV) - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, SMPLRT_DIV, &config, 1); // Sample Rate Divider - - config = 0x06; - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, CONFIG, &config, 1);// DLPF config: 5Hz - - config = 0x18; - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, GYRO_CONFIG, &config, 1);// +2000dps - - config = 0x00; - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, ACCEL_CONFIG, &config, 1);// +-2g - - config = 0x08; - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, ACCEL_CONFIG_2, &config, 1); // 1.13kHz - - config = 0x2; // set passby - ercd = _mpu_reg_write(obj, obj->mpu_slvaddr, INT_PIN_CFG, &config, 1); - board_delay_ms(100); - - ercd = _mpu_reg_read(obj, obj->mag_slvaddr, MAG_WIM, data, 1);// read mag who i am; - - if (data[0] != MAG_ID) { - dbg_printf(DBG_MORE_INFO, "mpu init failed\r\n"); - return E_SYS; - } - - config = 0x01; - ercd = _mpu_reg_write(obj, obj->mag_slvaddr, MAG_CTRL, &config, 1);// mag single measurement mode -#else - mpu9250_ptr = obj; - - if (!mpu_init()) { - if (!mpu_set_sensors(INV_XYZ_GYRO | INV_XYZ_ACCEL)) { - EMBARC_PRINTF("mpu_set_sensor complete ......\r\n"); - } - - mpu_delay_ms(50); - - if (!mpu_configure_fifo(INV_XYZ_GYRO | INV_XYZ_ACCEL)) { - EMBARC_PRINTF("mpu_configure_fifo complete ......\r\n"); - } - - mpu_delay_ms(50); - - if (!mpu_set_sample_rate(DEFAULT_MPU_HZ)) { - EMBARC_PRINTF("mpu_set_sample_rate complete ......\r\n"); - } - - mpu_delay_ms(50); - // if(!mpu_set_gyro_bias_reg(gyroZero)) - // EMBARC_PRINTF("mpu_set_gyro_bias_reg complete ......\r\n"); - mpu_delay_ms(50); - - if (!dmp_load_motion_driver_firmware()) { - EMBARC_PRINTF("dmp_load_motion_driver_firmware complete ......\r\n"); - } - - mpu_delay_ms(50); - - if (!dmp_set_orientation(inv_orientation_matrix_to_scalar(gyro_orientation))) { - EMBARC_PRINTF("dmp_set_orientation complete ......\r\n"); - } - - mpu_delay_ms(50); - - if (!dmp_enable_feature(DMP_FEATURE_6X_LP_QUAT | DMP_FEATURE_SEND_RAW_ACCEL | - DMP_FEATURE_SEND_RAW_GYRO)) { - // DMP_FEATURE_SEND_CAL_GYRO | DMP_FEATURE_GYRO_CAL)) - EMBARC_PRINTF("dmp_enable_feature complete ......\r\n"); - } - - mpu_delay_ms(50); - - if (!dmp_set_fifo_rate(DEFAULT_MPU_HZ)) { - EMBARC_PRINTF("dmp_set_fifo_rate complete ......\r\n"); - } - - mpu_delay_ms(50); - // run_self_test(); - mpu_delay_ms(50); - - if (!mpu_set_dmp_state(1)) { - EMBARC_PRINTF("mpu_set_dmp_state complete ......\r\n"); - } - - mpu_delay_ms(50); - } - -#endif - } - -error_exit: - return ercd; -} - -int32_t mpu9250_sensor_deinit(MPU9250_DEF_PTR obj) -{ - int32_t ercd = E_OK; - DEV_IIC_PTR iic_obj = iic_get_dev(obj->i2c_id); - - ercd = iic_obj->iic_close(); - MPU9250_CHECK_EXP_NORTN(ercd == E_OK); - -error_exit: - return ercd; -} - -int32_t mpu9250_sensor_read(MPU9250_DEF_PTR obj, MPU9250_DATA_PTR mp_data) -{ - int32_t ercd = E_OK; - - MPU9250_CHECK_EXP_NORTN(mp_data != NULL); -#ifndef MPU9250_USE_DMP - uint8_t data[6]; - uint8_t config; - ercd = _mpu_reg_read(obj, obj->mpu_slvaddr, GYRO_XOUT_H, data, 6); - - if (ercd != 6) { - ercd = E_OBJ; - goto error_exit; - } else { - ercd = E_OK; - - mp_data->gyro_x = ((int16_t)data[0] << 8) + ((int16_t)data[1]); - mp_data->gyro_y = ((int16_t)data[2] << 8) + ((int16_t)data[3]); - mp_data->gyro_z = ((int16_t)data[4] << 8) + ((int16_t)data[5]); - } - - ercd = _mpu_reg_read(obj, obj->mpu_slvaddr, ACCEL_XOUT_H, data, 6); - - if (ercd != 6) { - ercd = E_OBJ; - goto error_exit; - } else { - ercd = E_OK; - - mp_data->accel_x = ((int16_t)data[0] << 8) + ((int16_t)data[1]); - mp_data->accel_y = ((int16_t)data[2] << 8) + ((int16_t)data[3]); - mp_data->accel_z = ((int16_t)data[4] << 8) + ((int16_t)data[5]); - } - - ercd = _mpu_reg_read(obj, obj->mag_slvaddr, MAG_XOUT_L, data, 6); - - if (ercd != 6) { - ercd = E_OBJ; - } else { - ercd = E_OK; - - mp_data->mag_x = ((int16_t)data[1] << 8) + ((int16_t)data[0]); - mp_data->mag_y = ((int16_t)data[3] << 8) + ((int16_t)data[2]); - mp_data->mag_z = ((int16_t)data[5] << 8) + ((int16_t)data[4]); - } - - config = 0x01; - ercd = _mpu_reg_write(obj, obj->mag_slvaddr, MAG_CTRL, &config, 1);// mag single measurement mode -#else - short gyro[3], accel[3], sensors; - float q0 = 1.0f, q1 = 0.0f, q2 = 0.0f, q3 = 0.0f; - unsigned long sensor_timestamp; - unsigned char more; - long quat[4]; - float q30 = (float)(1 << 30); - - if (dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors, &more) == 0) { - mp_data->gyro_x = gyro[0]; - mp_data->gyro_y = gyro[1]; - mp_data->gyro_z = gyro[2]; - mp_data->accel_x = accel[0]; - mp_data->accel_y = accel[1]; - mp_data->accel_z = accel[2]; - - if (sensors & INV_WXYZ_QUAT) { - q0 = quat[0] / q30; - q1 = quat[1] / q30; - q2 = quat[2] / q30; - q3 = quat[3] / q30; - mp_data->pitch = (float)asin(-2 * q1 * q3 + 2 * q0 * q2) * 57.3f; - mp_data->roll = (float)atan2(2 * q2 * q3 + 2 * q0 * q1, -2 * q1 * q1 - 2 * q2 * q2 + 1) * 57.3f; - mp_data->yaw = (float)atan2(2 * (q1 * q2 + q0 * q3), q0 * q0 + q1 * q1 - q2 * q2 - q3 * q3) * 57.3f; - return 0; - } - } - -#endif -error_exit: - return ercd; -} - -#ifdef MPU9250_USE_DMP -int32_t mpu_iic_write(uint32_t slaveaddr, uint8_t regaddr, uint8_t len, uint8_t *val) -{ - int32_t ercd = E_PAR; - uint8_t data[1]; - DEV_IIC_PTR iic_obj = iic_get_dev(mpu9250_ptr->i2c_id); - - dbg_printf(DBG_LESS_INFO, "[%s]%d: obj 0x%x, regaddr 0x%x, val 0x%x\r\n", __FUNCTION__, __LINE__, obj, regaddr, *val); - dbg_printf(DBG_MORE_INFO, "[%s]%d: iic_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, iic_obj, *iic_obj); - MPU9250_CHECK_EXP_NORTN(iic_obj != NULL); - - data[0] = (uint8_t)(regaddr & 0xff); - - iic_obj->iic_control(IIC_CMD_MST_SET_TAR_ADDR, CONV2VOID(slaveaddr)); - - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_RESTART)); - ercd = iic_obj->iic_write(data, 1); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_STOP)); - ercd = iic_obj->iic_write(val, len); - - if (ercd == len) { - ercd = E_OK; - } - -error_exit: - return ercd; -} - -int32_t mpu_iic_read(uint32_t slaveaddr, uint8_t regaddr, uint8_t len, uint8_t *val) -{ - int32_t ercd = E_PAR; - uint8_t data[1]; - DEV_IIC_PTR iic_obj = iic_get_dev(mpu9250_ptr->i2c_id); - - dbg_printf(DBG_MORE_INFO, "[%s]%d: iic_obj 0x%x -> 0x%x\r\n", __FUNCTION__, __LINE__, iic_obj, *iic_obj); - MPU9250_CHECK_EXP_NORTN(iic_obj != NULL); - - data[0] = (uint8_t)(regaddr & 0xff); - - iic_obj->iic_control(IIC_CMD_MST_SET_TAR_ADDR, CONV2VOID(slaveaddr)); - - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_RESTART)); - ercd = iic_obj->iic_write(data, 1); - ercd = iic_obj->iic_control(IIC_CMD_MST_SET_NEXT_COND, CONV2VOID(IIC_MODE_STOP)); - ercd = iic_obj->iic_read(val, len); - - if (ercd == len) { - ercd = E_OK; - } - -error_exit: - return ercd; -} - -int mpu_get_ms(unsigned long *count) -{ - *count = (unsigned long)OSP_GET_CUR_MS(); - return 0; -} -void mpu_delay_ms(uint32_t ms) -{ - board_delay_ms(ms); -} - -#endif diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.h b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.h deleted file mode 100644 index 9b841228..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.h +++ /dev/null @@ -1,87 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_MPU9250 -#define H_MPU9250 -// MPU9250 (Nine-Axis (Gyro + Accelerometer + Compass) sensor using I2C bus) is on IOTDK board -#include "device/ip_hal/dev_iic.h" - -#define MPU9250_USE_DMP - -#define MPU9250_AD0_PIN 0 /*!< I2C Serial Bus Address Selection Pin */ -#define MPU9250_IIC_ADDRESS (0x68 + (MPU9250_AD0_PIN << 1)) - -#define MAG_IIC_ADDRESS 0x0C -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - int16_t accel_x; - int16_t accel_y; - int16_t accel_z; - int16_t gyro_x; - int16_t gyro_y; - int16_t gyro_z; - int16_t mag_x; - int16_t mag_y; - int16_t mag_z; - float pitch; - float roll; - float yaw; -} MPU9250_DATA, *MPU9250_DATA_PTR; - -typedef struct { - uint32_t i2c_id; - uint32_t mpu_slvaddr; - uint32_t mag_slvaddr; - -} MPU9250_DEF, *MPU9250_DEF_PTR; - -#define MPU9250_DEFINE(NAME, I2C_ID, SLAVE_ADDRESS) \ - MPU9250_DEF __ ## NAME = { \ - .i2c_id = I2C_ID, \ - .mpu_slvaddr = SLAVE_ADDRESS, \ - .mag_slvaddr = MAG_IIC_ADDRESS \ - }; \ - - MPU9250_DEF_PTR NAME = &__ ## NAME - -extern int32_t mpu9250_sensor_init(MPU9250_DEF_PTR obj); -extern int32_t mpu9250_sensor_deinit(MPU9250_DEF_PTR obj); -extern int32_t mpu9250_sensor_read(MPU9250_DEF_PTR obj, MPU9250_DATA_PTR mp_data); -extern int32_t mpu_iic_read(uint32_t slaveaddr, uint8_t regaddr, uint8_t len, uint8_t *val); -extern int32_t mpu_iic_write(uint32_t slaveaddr, uint8_t regaddr, uint8_t len, uint8_t *val); -int mpu_get_ms(unsigned long *count); -void mpu_delay_ms(uint32_t ms); -#ifdef __cplusplus -} -#endif - -#endif /* H_MPU9250 */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.mk b/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.mk deleted file mode 100644 index 10301d40..00000000 --- a/platform/vendor_bsp/embarc_bsp/device/peripheral/sensor/imu/mpu9250/mpu9250.mk +++ /dev/null @@ -1,2 +0,0 @@ -DEV_CSRCDIR += $(EMBARC_ROOT)/device/peripheral/sensor/imu/mpu9250 -DEV_INCDIR += $(EMBARC_ROOT)/device/peripheral/sensor/imu/mpu9250 \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc.h deleted file mode 100644 index 3c4e07e8..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc.h +++ /dev/null @@ -1,490 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_CORE_COMM - * @brief Header file for common core definitions - */ - -/** - * @addtogroup ARC_HAL_CORE_COMM - * @{ - */ - -#ifndef H_ARC_CORE -#define H_ARC_CORE - -#include "arc/arc_feature_config.h" - -/** - * @name exception number definitions - * @{ - */ - -/* ARC exception number */ -#define EXC_NO_RESET (0) /*!< reset vector, the entry of power up and reset */ -#define EXC_NO_MEM_ERR (1) /*!< external memory bus error */ -#define EXC_NO_INS_ERR (2) /*!< illegal instruction or illegal instruction sequence */ -#define EXC_NO_MAC_CHK (3) /*!< machine check error */ -#define EXC_NO_TLB_MISS_I (4) /*!< instruction TLB missing exception, useless without MMU */ -#define EXC_NO_TLB_MISS_D (5) /*!< data TLB missing exception, useless without MMU */ -#define EXC_NO_PRO_VIO (6) /*!< protection violation */ -#define EXC_NO_PRI_VIO (7) /*!< privilege violation */ -#define EXC_NO_SWI (8) /*!< software interrupt */ -#define EXC_NO_TRAP (9) /*!< trap */ -#define EXC_NO_EXT (10) /*!< extension exception */ -#define EXC_NO_DIV_ZER0 (11) /*!< divide by zero */ -#define EXC_NO_DC_ERR (12) /*!< data cache consistency error */ -#define EXC_NO_MAL_ALIGN (13) /*!< misaligned data access */ -#define EXC_NO_VEC_UNIT (14) /*!< vector unit exception (Vector stack pointer check violation is detected in the vector unit.) */ -#define EXC_NO_RESERVE0 (15) /*!< reserved */ - -/* extension interrupts */ -#define EXC_NO_16 (16) /*!< interrupt vector 16 */ -#define EXC_NO_17 (17) /*!< interrupt vector 17 */ -#define EXC_NO_18 (18) /*!< interrupt vector 18 */ -#define EXC_NO_19 (19) /*!< interrupt vector 19 */ -#define EXC_NO_20 (20) /*!< interrupt vector 20 */ -#define EXC_NO_21 (21) /*!< interrupt vector 21 */ -#define EXC_NO_22 (22) /*!< interrupt vector 22 */ -#define EXC_NO_23 (23) /*!< interrupt vector 23 */ -#define EXC_NO_24 (24) /*!< interrupt vector 24 */ -#define EXC_NO_25 (25) /*!< interrupt vector 25 */ -#define EXC_NO_26 (26) /*!< interrupt vector 26 */ -#define EXC_NO_27 (27) /*!< interrupt vector 27 */ -#define EXC_NO_28 (28) /*!< interrupt vector 28 */ -#define EXC_NO_29 (29) /*!< interrupt vector 29 */ -#define EXC_NO_30 (30) /*!< interrupt vector 30 */ -#define EXC_NO_31 (31) /*!< interrupt vector 31 */ -/* ... ARC supports 255 interrupt vectors at most */ -#define EXC_NO_255 (255 /*!< interrupt vector 255 */ - -/** @} */ - -/** - * @name exception vector offset - * @{ - */ -#define EXC_NO_TO_OFFSET(no) (no << 2) - -/* ARC exception vector offset */ -#define EXC_VECTOR_RESET (0x00) /*!< EXC_NO_RESET offset */ -#define EXC_VECTOR_MEM_ERR (0x04) /*!< EXC_NO_MEM_ERR offset */ -#define EXC_VECTOR_INS_ERR (0x08) /*!< EXC_NO_INS_ERR offset */ -#define EXC_VECTOR_MAC_CHK (0x0c) /*!< EXC_NO_MAC_CHK offset */ -#define EXC_VECTOR_TLB_MISS_I (0x10) /*!< EXC_NO_TLB_MISS_I offset */ -#define EXC_VECTOR_TLB_MISS_D (0x14) /*!< EXC_NO_TLB_MISS_D offset */ -#define EXC_VECTOR_PRO_VIO (0x18) /*!< EXC_NO_PRO_VIO offset */ -#define EXC_VECTOR_PRI_VIO (0x1c) /*!< EXC_NO_PRI_VIO offset */ -#define EXC_VECTOR_SWI (0x20) /*!< EXC_NO_SWI offset */ -#define EXC_VECTOR_TRAP (0x24) /*!< EXC_NO_TRAP offset */ -#define EXC_VECTOR_EXT (0x28) /*!< EXC_NO_EXT offset */ -#define EXC_VECTOR_DIV_ZER0 (0x2c) /*!< EXC_NO_DIV_ZER0 offset */ -#define EXC_VECTOR_DC_ERR (0x30) /*!< EXC_NO_DC_ERR offset */ -#define EXC_VECTOR_MAL_ALIGN (0x34) /*!< EXC_NO_MAL_ALIGN offset */ -#define EXC_VECTOR_VEC_UNIT (0x38) /*!< EXC_NO_VEC_UNIT offset */ -#define EXC_VECTOR_RESERVE0 (0x3c) /*!< EXC_NO_RESERVE0 offset */ -/** @} */ - -/** - * @name build configuration register - * @{ - */ -#define AUX_BCR_VER (0x60) /*!< build configuration register version */ -#define AUX_BCR_BTA (0x63) /*!< build configuration for BTA LINK */ -#define AUX_BCR_VECBASE (0x68) /*!< build configuration for interrupt vector base */ -#define AUX_BCR_MPU (0x6d) /*!< build configuration for memory protection unit */ -#define AUX_BCR_RF (0x6e) /*!< build configuration for core registers */ -#define AUX_BCR_D_CACHE (0x72) /*!< build configuration for data cache */ -#define AUX_BCR_DCCM (0x74) /*!< build configuration for DCCM */ -#define AUX_BCR_TIMERS (0x75) /*!< build configuration for processor timers */ -#define AUX_BCR_AP (0x76) /*!< build configuration for actionpoints */ -#define AUX_BCR_I_CACHE (0x77) /*!< build configuration for instruction cache */ -#define AUX_BCR_ICCM (0x78) /*!< build configuration for ICCM */ -#define AUX_BCR_DSP (0x7a) /*!< build configuration for DSP */ -#define AUX_BCR_MUL (0x7b) /*!< build configuration for multiply */ -#define AUX_BCR_SWAP (0x7c) /*!< build configuration for swap */ -#define AUX_BCR_NORM (0x7d) /*!< build configuration for normalize */ -#define AUX_BCR_MIXMAX (0x7e) /*!< build configuration for MIN/MAX */ -#define AUX_BCR_BARREL (0x7f) /*!< build configuration for barrel shift */ -#define AUX_BCR_ISA (0xc1) /*!< build configuration for ISA configuration */ -#define AUX_BCR_STACK (0xc5) /*!< build configuration for stack region */ -#define AUX_BCR_ERP (0xc7) /*!< build configuration for error protection */ -#define AUX_BCR_FPU (0xc8) /*!< build configuration for floating-point unit */ -#define AUX_BCR_CPORT (0xc9) /*!< build configuration for code protection */ -#define AUX_BCR_BS (0xcb) /*!< build configuration for bitstream */ -#define AUX_BCR_AGU (0xcc) /*!< build configuration for address generate unit */ -#define AUX_BCR_DMAC (0xcd) /*!< build configuration for DMA */ -#define AUX_BCR_CONNECT_SYSTEM (0xd0) /*!< build configuration for arc connect */ -#define AUX_BCR_CONNECT_SEMA (0xd1) /*!< build configuration for inter-core semaphore */ -#define AUX_BCR_CONNECT_MESSAGE (0xd2) /*!< build configuration for inter-code message */ -#define AUX_BCR_CONNECT_PMU (0xd3) /*!< build configuration for power management unit */ -#define AUX_BCR_CONNECT_GFRC (0xd6) /*!< build configuration for global free running counter */ -#define AUX_BCR_CAL_STORE (0xd9) /*!< build configuration for calibration parameter storage */ -#define AUX_BCR_CONNECT_ICI (0xe0) /*!< build configuration for inter-core interrupt unit */ -#define AUX_BCR_CONNECT_ICD (0xe1) /*!< build configuration for inter-core debug unit */ -#define AUX_BCR_CONNECT_PDM (0xe3) /*!< build configuration for power domain management unit*/ -#define AUX_BCR_RTT (0xf2) /*!< build configuration for real-time trace */ -#define AUX_BCR_IRQ (0xf3) /*!< build configuration for interrupt */ -#define AUX_BCR_PCT (0xf5) /*!< build configuration for performance counters */ -#define AUX_BCR_CC (0xf6) /*!< build configuration for performance counters */ -#define AUX_BCR_PDM_DVFS (0xf7) /*!< build configuration for PDM and DVFS */ - -#define AUX_BCR_SEC_BUILD (0xdb) - -/* from 0xF5 and 0xF6 */ - -#define AUX_BCR_IFQUEUE (0xfe) /*!< build configuration for instruction fetch queue */ -#define AUX_BCR_SMART (0xff) /*!< build configuration for SmaRT debug feature */ -/** @} */ - -#define AUX_SEC_STAT (0x9) -#define AUX_SEC_STAT_BIT_SSC (0) -#define AUX_SEC_STAT_BIT_NSRT (1) -#define AUX_SEC_STAT_BIT_NSRU (2) -#define AUX_SEC_STAT_BIT_IRM (3) -#define AUX_SEC_STAT_BIT_SUE (4) -#define AUX_SEC_STAT_BIT_NIC (5) -#define AUX_SEC_STAT_BIT_ERM (31) - -/** - * @name status register STATUS32 - * @{ - */ -#define AUX_STATUS32 (0xa) -#define AUX_STATUS32_P0 (0xb) - -/* STATUS32 bit-field definition */ -#define AUX_STATUS_BIT_AE (5) /*!< processor is in an exception */ -#define AUX_STATUS_BIT_DE (6) /*!< delayed branch is pending */ -#define AUX_STATUS_BIT_U (7) /*!< user mode */ -#define AUX_STATUS_BIT_L (12) /*!< zero-overhead loop enable */ -#define AUX_STATUS_BIT_IE (31) /*!< interrupt enable */ -#define AUX_STATUS_BIT_HALT (0) /*!< halt bit */ -#define AUX_STATUS_BIT_SC (14) /*!< stack check bit */ -#define AUX_STATUS_BIT_AD (19) /*!< alignment check bit */ -#define AUX_STATUS_BIT_US (20) /*!< user sleep mode enable bit */ -#define AUX_STATUS_RB(x) ((x) << 16) /*!< register bank */ - -/* masks correspond to STATUS32 bit-field */ -#define AUX_STATUS_MASK_AE (1 << AUX_STATUS_BIT_AE) /*!< mask of AUX_STATUS_BIT_AE */ -#define AUX_STATUS_MASK_DE (1 << AUX_STATUS_BIT_DE) /*!< mask of AUX_STATUS_BIT_DE */ -#define AUX_STATUS_MASK_U (1 << AUX_STATUS_BIT_U) /*!< mask of AUX_STATUS_BIT_U */ -#define AUX_STATUS_MASK_L (1 << AUX_STATUS_BIT_L) /*!< mask of AUX_STATUS_BIT_L */ -#define AUX_STATUS_MASK_IE (1 << AUX_STATUS_BIT_IE) /*!< mask of AUX_STATUS_BIT_IE */ -#define AUX_STATUS_MASK_HALT (1 << AUX_STATUS_BIT_HALT) /*!< mask of AUX_STATUS_BIT_HALT */ -#define AUX_STATUS_MASK_SC (1 << AUX_STATUS_BIT_SC) /*!< mask of AUX_STATUS_BIT_SC */ -#define AUX_STATUS_MASK_AD (1 << AUX_STATUS_BIT_AD) /*!< mask of AUX_STATUS_BIT_AD */ -#define AUX_STATUS_MASK_US (1 << AUX_STATUS_BIT_US) /*!< mask of AUX_STATUS_BIT_US */ - -#ifdef ARC_FEATURE_UNALIGNED -#define STATUS32_RESET_VALUE (AUX_STATUS_MASK_AD | AUX_STATUS_MASK_US) -#else -#define STATUS32_RESET_VALUE (AUX_STATUS_MASK_US) -#endif - -/** @} */ - -/** - * @name zero overhead loop auxiliary register - * @{ - */ -#define AUX_LP_START (0x2) /*!< loop start address (32-bit) */ -#define AUX_LP_END (0x3) /*!< loop end address (32-bit) */ -/** @} */ - -#define AUX_USER_SP (0xd) /*!< user-mode stack pointer */ -/* added in secure mode */ -#define AUX_KERNEL_SP (0x38) /*!< kernel-mode stack pointer */ -#define AUX_SEC_U_SP (0x39) /*!< secure user-mode stack pointer */ -#define AUX_SEC_K_SP (0x3a) /*!< secure kernel-mode stack pointer */ - -/* additional stack checking registers for secure mode */ -#define AUX_S_USTACK_BASE (0x263) -#define AUX_S_USTACK_TOP (0x262) - -#define AUX_S_KSTACK_BASE (0x267) -#define AUX_S_KSTACK_TOP (0x266) - -#define AUX_KSTACK_TOP (0x264) -#define AUX_KSTACK_BASE (0x265) -#define AUX_USTACK_TOP (0x260) -#define AUX_USTACK_BASE (0x261) - -/** - * @name auxiliary register for hardware counter 0 and 1 - * @{ - */ -#define AUX_TIMER0_LIMIT (0x23) /*!< timer 0 limit value */ -#define AUX_TIMER0_CTRL (0x22) /*!< timer 0 control value */ -#define AUX_TIMER0_CNT (0x21) /*!< timer 0 count value */ -#define AUX_TIMER1_LIMIT (0x102) /*!< timer 1 limit value */ -#define AUX_TIMER1_CTRL (0x101) /*!< timer 1 control value */ -#define AUX_TIMER1_CNT (0x100) /*!< timer 1 count value */ -/** @} */ - -#define AUX_SECURE_TIMER0_CNT (0x106) /*!< secure timer 0 count value */ -#define AUX_SECURE_TIMER0_CTRL (0x107) /*!< secure timer 0 control value */ -#define AUX_SECURE_TIMER0_LIMIT (0x108) /*!< secure timer 0 limit value */ -#define AUX_SECURE_TIMER1_CNT (0x109) /*!< secure timer 1 count value */ -#define AUX_SECURE_TIMER1_CTRL (0x10a) /*!< secure timer 1 control value */ -#define AUX_SECURE_TIMER1_LIMIT (0x10b) /*!< secure timer 1 limit value */ - -/** - * @name auxiliary register for real-time counter - * @{ - */ -#define AUX_RTC_CTRL (0x103) /*!< real-time counter control register */ -#define AUX_RTC_LOW (0x104) /*!< real-time counter count low register */ -#define AUX_RTC_HIGH (0x105) /*!< real-time counter count high register */ -/** @} */ - -/** - * @name indexed table auxiliary register - * @{ - */ -#define AUX_JLI_BASE (0x290) /*!< jump and link indexed base address */ -#define AUX_LDI_BASE (0x291) /*!< load indexed base address */ -#define AUX_EI_BASE (0x292) /*!< execute indexed base address */ -/** @} */ - -/** - * @name baseline auxiliary register set - * @{ - */ -/* exception related aux regs */ -#define AUX_ERRET (0x400) /*!< exception return address */ -#define AUX_ERBTA (0x401) /*!< BTA saved on exception entry */ -#define AUX_ERSTATUS (0x402) /*!< STATUS32 saved on exception */ -#define AUX_ECR (0x403) /*!< exception cause register */ -#define AUX_EFA (0x404) /*!< exception fault address */ -#define AUX_BTA (0x412) /*!< branch target address */ -/** @} */ - -/* New register to control which exceptions can be handled in NS mode */ -#define AUX_ERSEC_STAT (0x406) -#define AUX_ERSEC_STAT_BIT_ERM (31) -#define AUX_SEC_EXCEPT (0x407) - -/** - * @name MPU register set - * @{ - */ -#define AUX_MPU_EN (0x409) /*!< MPU enable register */ -#define AUX_MPU_ECR (0x420) /*!< MPU exception cause */ -#define AUX_MPU_RDB0 (0x422) /*!< MPU region descriptor base 0 */ -#define AUX_MPU_RDP0 (0x423) /*!< MPU region descriptor permission 0 */ - -/* MPU register set in silverstone */ -#define AUX_MPU_INDEX (0x448) -#define AUX_MPU_INDEX_BIT_D (31) -#define AUX_MPU_RSTART (0x449) -#define AUX_MPU_REND (0x44a) -#define AUX_MPU_RPER (0x44b) -#define AUX_MPU_RPER_BIT_S (15) -#define AUX_MPU_PROBE (0x44c) - -#define AUX_NSC_TABLE_BASE (0x269) -#define AUX_NSC_TABLE_TOP (0x268) - -/** @} */ - -/** - * @name exception cause register (ECR) bit-field definition - * @{ - */ -#define AUX_ECR_VEC_MASK (0xff0000) /*!< [23:16] = exception vector */ -#define AUX_ECR_CODE_MASK (0x00ff00) /*!< [15: 8] = exception cause code */ -#define AUX_ECR_PARAM_MASK (0x0000ff) /*!< [ 7: 0] = exception parameters */ -/** @} */ - -/** - * @name exception vector number and cause code - * @{ - */ -#define AUX_ECR_V_INSN_ERR (0x02) /*!< vector number of illegal instruction */ -#define AUX_ECR_V_MACH_CHK (0x03) /*!< vector number of machine check */ -#define AUX_ECR_V_ITLB_MISS (0x04) /*!< vector number of instruction TLB missing exception */ -#define AUX_ECR_V_DTLB_MISS (0x05) /*!< vector number of data TLB missing exception */ -#define AUX_ECR_V_PROTV (0x06) /*!< vector number of protection violation */ -#define AUX_ECR_V_PRIV (0x07) /*!< vector number of privilege violation */ -#define AUX_ECR_V_SWI (0x08) /*!< vector number of software interrupt */ -#define AUX_ECR_V_TRAP (0x09) /*!< vector number of trap */ -#define AUX_ECR_V_EXT (0x0a) /*!< vector number of extension */ -#define AUX_ECR_V_DIV_ZERO (0x0b) /*!< vector number of divide by zero*/ -#define AUX_ECR_V_DC_ERR (0x0c) /*!< vector number of data cache consistency error */ -#define AUX_ECR_V_MISALIG_DATA (0x0d) /*!< vector number of misaligned data access */ - -#define AUX_ECR_C_PROTV_INST_FETCH (0x00) /*!< cause code of instruction fetch (protection violation) */ -#define AUX_ECR_C_PROTV_LOAD (0x01) /*!< cause code of memory read related (protection violation) */ -#define AUX_ECR_C_PROTV_STORE (0x02) /*!< cause code of memory write related (protection violation) */ -#define AUX_ECR_C_PROTV_XCHG (0x03) /*!< cause code of read-modify-write related (protection violation) */ -#define AUX_ECR_C_PROTV_NS_VECT_IN_S (0x10) /*!< cause code of NS vector table in S memory (protection violation) */ -#define AUX_ECR_C_PROTV_NS_HANDLER_IN_S (0x11) /*!< cause code of NS handler in S memory (protection violation) */ -#define AUX_ECR_C_PROTV_NSC_RANGE (0x12) /*!< cause code of NSC table range violation (protection violation) */ - -#define AUX_ECR_C_PRIV_PRIV (0x00) /*!< cause code of privilege violation (privilege violation) */ -#define AUX_ECR_C_PRIV_DIS_EXT (0x01) /*!< cause code of disabled extension (privilege violation) */ -#define AUX_ECR_C_PRIV_ACT_HIT (0x02) /*!< cause code of action point hit (privilege violation) */ -#define AUX_ECR_C_PRIV_ACT_SECURE (0x10) /*!< cause code of secure related operation (privilege violation) */ - -#define AUX_ECR_C_MCHK_DUP_TLB (0x01) /*!< @todo definition is to be added. */ - -#define AUX_ECR_C_BIT_DTLB_LD_MISS (8) /*!< @todo definition is to be added. */ -#define AUX_ECR_C_BIT_DTLB_ST_MISS (9) /*!< @todo definition is to be added. */ -/** @} */ - -/** - * @name interrupt related auxiliary register - * @{ - */ -#define AUX_IRQ_CTRL (0xe) /*!< interrupt context saving control register */ -#define AUX_INT_VECT_BASE (0x25) /*!< interrupt vector base register */ -#define AUX_INT_VECT_BASE_S (0x26) /*!< secure interrupt vector based register */ -#define AUX_IRQ_ACT (0x43) /*!< active interrupts register */ -#define AUX_IRQ_CAUSE (0x40a) /*!< interrupt cause register */ -#define AUX_IRQ_SELECT (0x40b) /*!< interrupt select register */ -#define AUX_IRQ_PRIORITY (0x206) /*!< interrupt priority register */ -#define AUX_IRQ_PRIORITY_BIT_S (0x8) /*!< S bit offset in interrupt priority register */ -#define AUX_IRQ_ENABLE (0x40c) /*!< interrupt enable register */ -#define AUX_IRQ_TRIGGER (0x40d) /*!< interrupt trigger: level or pulse */ -#define AUX_IRQ_PENDING (0x416) /*!< interrupt pending register */ -#define AUX_IRQ_PLUSE_CLR (0x415) /*!< interrupt pulse cancel register */ -#define AUX_IRQ_STATUS (0x40f) /*!< interrupt status register */ -#define AUX_IRQ_PRI_PENDING (0x200) /*!< interrupt priority pending register */ -#define AUX_IRQ_HINT (0x201) /*!< software interrupt trigger */ -/** @} */ - -/** - * @name cache related auxiliary register - * @{ - */ -#define AUX_IC_IVIC (0x10) /*!< invalidate instruction cache */ -#define AUX_IC_CTRL (0x11) /*!< instruction cache control register */ -#define AUX_IC_LIL (0x13) /*!< lock instruction cache line */ -#define AUX_IC_IVIL (0x19) /*!< invalidate instruction cache line */ -#define AUX_IC_RAM_ADDR (0x1a) /*!< instruction cache external access address */ -#define AUX_IC_TAG (0x1b) /*!< instruction cache tag access */ -#define AUX_IC_XTAG (0x1c) /*!< instruction cache secure bit tag */ -#define AUX_IC_DATA (0x1d) /*!< instruction cache data access */ -#define AUX_DC_IVDC (0x47) /*!< invalidate data cache */ -#define AUX_DC_CTRL (0x48) /*!< data cache control register */ -#define AUX_DC_LDL (0x49) /*!< lock data cache line */ -#define AUX_DC_IVDL (0x4a) /*!< invalidate data cache line */ -#define AUX_DC_FLSH (0x4b) /*!< flush data cache */ -#define AUX_DC_FLDL (0x4c) /*!< flush data line */ -#define AUX_DC_RAM_ADDR (0x58) /*!< data cache external access address */ -#define AUX_DC_TAG (0x59) /*!< data cache tag access */ -#define AUX_DC_XTAG (0x5a) /*!< data cache secure bit tag */ -#define AUX_DC_DATA (0x5b) /*!< data cache data access */ -/** @} */ - -/** - * @name dmac related auxiliary register - * @{ - */ -#define AUX_DMACTRL (0x680) /*!< DMA control register */ -#define AUX_DMACENB (0x681) /*!< DMA channel enable register */ -#define AUX_DMACDSB (0x682) /*!< DMA channel disable register */ -#define AUX_DMACHPRI (0x683) /*!< DMA channel high priority level register */ -#define AUX_DMACNPRI (0x684) /*!< DMA channel normal priority level register */ -#define AUX_DMACREQ (0x685) /*!< DMA channel transfer request register */ -#define AUX_DMACSTAT0 (0x686) /*!< DMA channel status register 0 */ -#define AUX_DMACSTAT1 (0x687) /*!< DMA channel status register 1 */ -#define AUX_DMACIRQ (0x688) /*!< DMA channel interrupt request status/clear register */ -#define AUX_DMACBASE (0x689) /*!< DMA channel structure register base address */ -#define AUX_DMACRST (0x68A) /*!< DMA channel reset register base address */ - -#define AUX_DMACTRL0 (0x690) /*!< DMA channel 0 control register when mapped in aux */ -#define AUX_DMASAR0 (0x691) /*!< DMA channel 0 source address register when mapped in aux */ -#define AUX_DMADAR0 (0x692) /*!< DMA channel 0 destination register when mapped in aux */ -#define AUX_DMACTRLx (AUX_DMACTRL0) /*!< DMA channel 0 control register when mapped in aux */ -#define AUX_DMASARx (AUX_DMASAR0) /*!< DMA channel 0 source address register when mapped in aux */ -#define AUX_DMADARx (AUX_DMADAR0) /*!< DMA channel 0 destination register when mapped in aux */ -/** @} */ - -/** - * @name fpu related auxiliary register - * @{ - */ -#define AUX_FPU_CTRL (0x300) /*!< FPU ctrl register */ -#define AUX_FPU_STATUS (0x301) /*!< FPU status register */ -#define AUX_FPU_DPFP1L (0x302) /*!< double float D1 register low */ -#define AUX_FPU_DPFP1H (0x303) /*!< double float D1 register high */ -#define AUX_FPU_DPFP2L (0x304) /*!< double float D2 register low */ -#define AUX_FPU_DPFP2H (0x305) /*!< double float D2 register high */ -/** @} */ - -/** - * @name dsp related auxiliary register - * @{ - */ - -#define AUX_ACC0_LO (0x580) -#define AUX_ACC0_GLO (0x581) -#define AUX_ACC0_HI (0x582) -#define AUX_ACC0_GHI (0x583) -#define AUX_DSP_BFLY0 (0x598) -#define AUX_DSP_FFT_CTRL (0x59e) -#define AUX_DSP_CTRL (0x59f) - -/** @} */ - -/** - * @name other auxiliary register - * @{ - */ -#define AUX_IDENTITY (0x4) /*!< identity register */ -#define AUX_DMP_PERIPHERAL (0x20a) /*!< peripheral memory region */ -#define AUX_XFLAGS (0x44f) /*!< user extension flags register */ - -#define AUX_CONNECT_CMD (0x600) /*!< ARConnect Command Register, CONNECT_CMD */ -#define AUX_CONNECT_WDATA (0x601) /*!< ARConnect Write Data Register, CONNECT_WDATA */ -#define AUX_CONNECT_READBACK (0x602) /*!< ARConnect Read Data Register, CONNECT_READBACK */ - -#define AUX_SMART_CONTROL (0x700) /*!< SmaRT Control Register, SMART_CONTROL */ -#define AUX_SMART_DATA (0x701) /*!< SmaRT Data Register, SMART_DATA */ - -/** @} */ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_CORE */ - -/** @} */ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_asm_common.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_asm_common.h deleted file mode 100644 index 2ec90a37..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_asm_common.h +++ /dev/null @@ -1,705 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC - * @brief common macro definitions for assembly file - */ -/** @cond ARC_HAL_ASM_COMMON */ - -#ifndef H_ARC_ASM_COMMON -#define H_ARC_ASM_COMMON - -#include "arc/arc.h" - -#ifdef __ASSEMBLY__ -/* the assembly macro definitions in ARC GNU and MWDT are - * different, so need different processing - */ -#if defined(__GNU__) -#define MACRO_ARG(x) \ x -#define ASM_MACRO1(name, arg1) name arg1 -#define ASM_MACRO2(name, arg1, arg2) name arg1 arg2 -#define ASM_MACRO3(name, arg1, arg2, arg3) name arg1 arg, agr3 -#define ASM_MACRO4(name, arg1, arg2, arg3, arg4) name arg1 arg2 arg3 arg4 -#else -#define MACRO_ARG(x) x -#define ASM_MACRO1(name, arg1) name, arg1 -#define ASM_MACRO2(name, arg1, arg2) name, arg1, arg2 -#define ASM_MACRO3(name, arg1, arg2, arg3) name, arg1, arg2, agr3 -#define ASM_MACRO4(name, arg1, arg2, arg3, arg4) name, arg1, arg2, arg3, arg4 -#endif -/* Note on the LD/ST addr modes with addr reg wback - * - * LD.a same as LD.aw - * - * LD.a reg1, [reg2, x] => Pre Incr - * Eff Addr for load = [reg2 + x] - * - * LD.ab reg1, [reg2, x] => Post Incr - * Eff Addr for load = [reg2] - */ -.macro ASM_MACRO1(PUSH, reg) -st.a MACRO_ARG(reg), [sp, -4] -.endm - -.macro ASM_MACRO1(PUSHAX, aux) -lr r10, [MACRO_ARG(aux)] -PUSH r10 -.endm - -.macro ASM_MACRO1(POP, reg) -ld.ab MACRO_ARG(reg), [sp, 4] -.endm - -.macro ASM_MACRO1(POPAX, aux) -POP r10 -sr r10, [MACRO_ARG(aux)] -.endm - -/* macro to get the cpu id */ -.macro ASM_MACRO1(GET_CORE_ID, reg) -lr MACRO_ARG(reg), [AUX_IDENTITY] -xbfu MACRO_ARG(reg), MACRO_ARG(reg), 0xe8 -.endm - -/* macro to save accl regs */ -.macro SAVE_R58_R59 -#if ARC_FEATURE_FPU || ARC_FEATURE_DSP || ARC_FEATURE_MPU_OPTION_NUM > 6 -PUSH r58 -PUSH r59 -#endif -.endm - -/* macro to restore accl regs */ -.macro RESTORE_R58_R59 -#if ARC_FEATURE_FPU || ARC_FEATURE_DSP || ARC_FEATURE_MPU_OPTION_NUM > 6 -POP r59 -POP r58 -#endif -.endm - -/* macro to save fpu related regs */ -.macro SAVE_FPU_REGS -#if ARC_FEATURE_FPU -PUSHAX AUX_FPU_CTRL -PUSHAX AUX_FPU_STATUS - -#if ARC_FEATURE_FPU_DA -PUSHAX AUX_FPU_DPFP1L -PUSHAX AUX_FPU_DPFP1H -PUSHAX AUX_FPU_DPFP2L -PUSHAX AUX_FPU_DPFP2H -#endif - -#endif -.endm - -/* macro to restore fpu related regs */ -.macro RESTORE_FPU_REGS -#if ARC_FEATURE_FPU - -#if ARC_FEATURE_FPU_DA -POPAX AUX_FPU_DPFP2H -POPAX AUX_FPU_DPFP2L -POPAX AUX_FPU_DPFP1H -POPAX AUX_FPU_DPFP1L -#endif -POPAX AUX_FPU_STATUS -POPAX AUX_FPU_CTRL -#endif - -.endm - -/* macro to save dsp related regs */ -.macro SAVE_DSP_REGS -#if ARC_FEATURE_DSP -PUSHAX AUX_DSP_CTRL -PUSHAX AUX_ACC0_LO -PUSHAX AUX_ACC0_GLO -PUSHAX AUX_ACC0_HI -PUSHAX AUX_ACC0_GHI - -#if ARC_FEATURE_DSP_COMPLEX -PUSHAX AUX_DSP_BFLY0 -PUSHAX AUX_DSP_FFT_CTRL -#endif - -#endif -.endm - -/* macro to restore dsp related regs */ -.macro RESTORE_DSP_REGS -#if ARC_FEATURE_DSP - -#if ARC_FEATURE_DSP_COMPLEX -POPAX AUX_DSP_FFT_CTRL -POPAX AUX_DSP_BFLY0 -#endif -POPAX AUX_ACC0_GHI -POPAX AUX_ACC0_HI -POPAX AUX_ACC0_GLO -POPAX AUX_ACC0_LO -POPAX AUX_DSP_CTRL -#endif -.endm - -/*-------------------------------------------------------------- -* Helpers to save/restore callee-saved regs: -* used by several macros below -*-------------------------------------------------------------*/ -.macro SAVE_CALLEE_REGS -PUSH r13 -PUSH r14 -PUSH r15 -#ifndef ARC_FEATURE_RF16 -PUSH r16 -PUSH r17 -PUSH r18 -PUSH r19 -PUSH r20 -PUSH r21 -PUSH r22 -PUSH r23 -PUSH r24 -PUSH r25 -#endif - -#if defined(ARC_ENABLE_EXTRA_CALLEE) -#if ARC_FEATURE_SEC_PRESENT -PUSHAX AUX_KERNEL_SP -PUSHAX AUX_SEC_K_SP -#else -PUSHAX AUX_USER_SP -#endif -#endif - -#if ARC_FEATURE_FPU_DSP_CONTEXT -SAVE_FPU_REGS -SAVE_DSP_REGS -#endif - -.endm - -.macro RESTORE_CALLEE_REGS - -#if ARC_FEATURE_FPU_DSP_CONTEXT -RESTORE_DSP_REGS -RESTORE_FPU_REGS -#endif - -#if defined(ARC_ENABLE_EXTRA_CALLEE) -#if ARC_FEATURE_SEC_PRESENT -POPAX AUX_SEC_K_SP -POPAX AUX_KERNEL_SP -#else -POPAX AUX_USER_SP -#endif -#endif - -#ifndef ARC_FEATURE_RF16 -POP r25 -POP r24 -POP r23 -POP r22 -POP r21 -POP r20 -POP r19 -POP r18 -POP r17 -POP r16 -#endif -POP r15 -POP r14 -POP r13 -.endm - -/* macro to clear callee regs */ -.macro CLEAR_CALLEE_REGS -#ifndef ARC_FEATURE_RF16 -mov r25, 0 -mov r24, 0 -mov r23, 0 -mov r22, 0 -mov r21, 0 -mov r20, 0 -mov r19, 0 -mov r18, 0 -mov r17, 0 -mov r16, 0 -#endif -mov r15, 0 -mov r14, 0 -mov r13, 0 -#if ARC_FEATURE_FPU_DSP_CONTEXT - -#if ARC_FEATURE_FPU - -#if ARC_FEATURE_FPU_DA -sr 0, [AUX_FPU_DPFP2H] -sr 0, [AUX_FPU_DPFP2L] -sr 0, [AUX_FPU_DPFP1H] -sr 0, [AUX_FPU_DPFP1L] -#endif -sr 0, [AUX_FPU_STATUS] -sr 0, [AUX_FPU_CTRL] -#endif /* ARC_FEATURE_FPU */ - -#if ARC_FEATURE_DSP - -#if ARC_FEATURE_DSP_COMPLEX -sr 0, [AUX_DSP_FFT_CTRL] -sr 0, [AUX_DSP_BFLY0] -#endif -sr 0, [AUX_ACC0_GHI] -sr 0, [AUX_ACC0_HI] -sr 0, [AUX_ACC0_GLO] -sr 0, [AUX_ACC0_LO] -sr 0, [AUX_DSP_CTRL] -#endif /* ARC_FEATURE_DSP */ - -#endif /* ARC_FEATURE_FPU_DSP_CONTEXT */ -.endm - -/* macro to clear scratch regs */ -.macro CLEAR_SCRATCH_REGS -mov r1, 0 -mov r2, 0 -mov r3, 0 -mov r4, 0 -mov r5, 0 -mov r6, 0 -mov r7, 0 -mov r8, 0 -mov r9, 0 -mov r10, 0 -mov r11, 0 -mov r12, 0 - -#if ARC_FEATURE_FPU || ARC_FEATURE_DSP || ARC_FEATURE_MPU_OPTION_NUM > 6 -mov r59, 0 -mov r58, 0 -#endif -mov fp, 0 -mov r29, 0 -mov r30, 0 -.endm - -.macro SAVE_LP_REGS -PUSH r60 -PUSHAX AUX_LP_START -PUSHAX AUX_LP_END -.endm - -.macro RESTORE_LP_REGS -POPAX AUX_LP_END -POPAX AUX_LP_START -POP r10 -/* must not use the LP_COUNT register(r60) as the destination of multi-cycle instruction */ -mov r60, r10 -.endm - -/* macro to save r0 to r12 */ -.macro SAVE_R0_TO_R12 -PUSH r0 -PUSH r1 -PUSH r2 -PUSH r3 -#ifndef ARC_FEATURE_RF16 -PUSH r4 -PUSH r5 -PUSH r6 -PUSH r7 -PUSH r8 -PUSH r9 -#endif -PUSH r10 -PUSH r11 -PUSH r12 -.endm - -/* macro to restore r0 to r12 */ -.macro RESTORE_R0_TO_R12 -POP r12 -POP r11 -POP r10 -#ifndef ARC_FEATURE_RF16 -POP r9 -POP r8 -POP r7 -POP r6 -POP r5 -POP r4 -#endif -POP r3 -POP r2 -POP r1 -POP r0 -.endm - -/* macro to save code density regs */ -.macro SAVE_CODE_DENSITY -PUSHAX AUX_JLI_BASE -PUSHAX AUX_LDI_BASE -PUSHAX AUX_EI_BASE -.endm - -/* macro to restore code density regs */ -.macro RESTORE_CODE_DENSITY -POPAX AUX_EI_BASE -POPAX AUX_LDI_BASE -POPAX AUX_JLI_BASE -.endm - -/* macro to save all non-caller saved regs */ -.macro SAVE_NONSCRATCH_REGS -/* caller saved regs are saved by caller function */ -PUSH gp -PUSH fp -PUSH blink -SAVE_CALLEE_REGS -.endm - -/* macro to restore all non-caller saved regs */ -.macro RESTORE_NONSCRATCH_REGS -RESTORE_CALLEE_REGS -POP blink -POP fp -POP gp -.endm - -/* macro to save regs in firq */ -.macro SAVE_FIQ_EXC_REGS -#ifndef ARC_FEATURE_RGF_BANKED_REGS -SAVE_R0_TO_R12 - -SAVE_R58_R59 - -PUSH gp -PUSH fp -PUSH r30 /* general purpose */ -PUSH blink - -#else -#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \ - ARC_FEATURE_RGF_BANKED_REGS != 16 && ARC_FEATURE_RGF_BANKED_REGS != 32 -#error "unsupported ARC_FEATURE_RGF_BANKED_REGS" -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_RGF_BANKED_REGS == 8 || \ - ARC_FEATURE_RGF_BANKED_REGS == 16 -#ifndef ARC_FEATURE_RF16 -PUSH r4 -PUSH r5 -PUSH r6 -PUSH r7 -PUSH r8 -PUSH r9 -#endif -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_RGF_BANKED_REGS == 8 -PUSH r10 -PUSH r11 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 -PUSH r12 -#endif - -SAVE_R58_R59 - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_RGF_BANKED_REGS == 8 -PUSH gp -PUSH fp -PUSH r30 /* general purpose */ -PUSH blink -#endif - -#endif /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */ - -#if ARC_FEATURE_CODE_DENSITY -SAVE_CODE_DENSITY -#endif -SAVE_LP_REGS -.endm - -/* macro to restore reg in firq */ -.macro RESTORE_FIQ_EXC_REGS -RESTORE_LP_REGS -#if ARC_FEATURE_CODE_DENSITY -RESTORE_CODE_DENSITY -#endif - -#ifndef ARC_FEATURE_RGF_BANKED_REGS -POP blink -POP r30 -POP fp -POP gp - -RESTORE_R58_R59 - -RESTORE_R0_TO_R12 -#else - -#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \ - ARC_FEATURE_RGF_BANKED_REGS != 16 && ARC_FEATURE_RGF_BANKED_REGS != 32 -#error "unsupported ARC_FEATURE_RGF_BANKED_REGS" -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_RGF_BANKED_REGS == 8 -POP blink -POP r30 -POP fp -POP gp -#endif - -RESTORE_R58_R59 - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 -POP r12 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_RGF_BANKED_REGS == 8 -POP r11 -POP r10 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_RGF_BANKED_REGS == 8 || \ - ARC_FEATURE_RGF_BANKED_REGS == 16 -#ifndef ARC_FEATURE_RF16 -POP r9 -POP r8 -POP r7 -POP r6 -POP r5 -POP r4 -#endif -#endif - -#endif /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */ -.endm - -/* normal interrupt prologue, pc, status and r0-r11 are saved by hardware */ -.macro INTERRUPT_PROLOGUE -PUSH r12 -SAVE_R58_R59 -PUSH gp -PUSH fp -PUSH ilink -PUSH r30 - -sub sp, sp, 4 /* skip bta */ -.endm - -/* normal interrupt epilogue, pc, status and r0-r11 are restored by hardware */ -.macro INTERRUPT_EPILOGUE -add sp, sp, 4 /* skip bta */ - -POP r30 -POP ilink -POP fp -POP gp -RESTORE_R58_R59 -POP r12 -.endm - -#if ARC_FEATURE_SEC_PRESENT -/* exception prologue, create the same frame of interrupt manually */ -.macro EXCEPTION_PROLOGUE -st.as r10, [sp, -6] /* save r10 first, free up a register*/ - -PUSHAX AUX_ERSTATUS -sub sp, sp, 4 /* slot for SEC_STAT */ -PUSHAX AUX_ERRET - -PUSH blink - -PUSH r11 -sub sp, sp, 4 /* r10 is pushed before */ -#ifndef ARC_FEATURE_RF16 -PUSH r9 -PUSH r8 -PUSH r7 -PUSH r6 -PUSH r5 -PUSH r4 -#endif -PUSH r3 -PUSH r2 -PUSH r1 -PUSH r0 - -#if ARC_FEATURE_CODE_DENSITY -SAVE_CODE_DENSITY -#endif -SAVE_LP_REGS - -PUSH r12 -SAVE_R58_R59 -PUSH gp -PUSH fp -PUSH ilink -PUSH r30 - -PUSHAX AUX_ERBTA -.endm - -/* exception epilogue, restore the same frame of interrupt manually */ -.macro EXCEPTION_EPILOGUE -POPAX AUX_ERBTA - -POP r30 -POP ilink -POP fp -POP gp -RESTORE_R58_R59 -POP r12 - -RESTORE_LP_REGS - -#if ARC_FEATURE_CODE_DENSITY -RESTORE_CODE_DENSITY -#endif -POP r0 -POP r1 -POP r2 -POP r3 -#ifndef ARC_FEATURE_RF16 -POP r4 -POP r5 -POP r6 -POP r7 -POP r8 -POP r9 -#endif -add sp, sp, 4 /* r10 will be popped finally */ -POP r11 - -POP blink - -POPAX AUX_ERRET -add sp, sp, 4 /* slot for SEC_STAT */ -POPAX AUX_ERSTATUS - -ld.as r10, [sp, -6] /* restore r10 */ -.endm -#else /* normal version */ -/* exception prologue, create the same frame of interrupt manually */ -.macro EXCEPTION_PROLOGUE -#if ARC_FEATURE_CODE_DENSITY -st.as r10, [sp, -11] /* save r10 first, free up a register*/ -#else -st.as r10, [sp, -8] -#endif -PUSHAX AUX_ERSTATUS -PUSHAX AUX_ERRET - -#if ARC_FEATURE_CODE_DENSITY -SAVE_CODE_DENSITY -#endif -SAVE_LP_REGS - -PUSH blink - -PUSH r11 -sub sp, sp, 4 /* r10 is pushed before */ -#ifndef ARC_FEATURE_RF16 -PUSH r9 -PUSH r8 -PUSH r7 -PUSH r6 -PUSH r5 -PUSH r4 -#endif -PUSH r3 -PUSH r2 -PUSH r1 -PUSH r0 - -PUSH r12 -SAVE_R58_R59 -PUSH gp -PUSH fp -PUSH ilink -PUSH r30 - -PUSHAX AUX_ERBTA -.endm - -/* exception epilogue, restore the same frame of interrupt manually */ -.macro EXCEPTION_EPILOGUE -POPAX AUX_ERBTA - -POP r30 -POP ilink -POP fp -POP gp -RESTORE_R58_R59 -POP r12 - -POP r0 -POP r1 -POP r2 -POP r3 -#ifndef ARC_FEATURE_RF16 -POP r4 -POP r5 -POP r6 -POP r7 -POP r8 -POP r9 -#endif -add sp, sp, 4 /* r10 will be popped finally */ -POP r11 - -POP blink - -RESTORE_LP_REGS - -#if ARC_FEATURE_CODE_DENSITY -RESTORE_CODE_DENSITY -#endif - -POPAX AUX_ERRET -POPAX AUX_ERSTATUS - -#if ARC_FEATURE_CODE_DENSITY -ld.as r10, [sp, -11] /* restore r10 */ -#else -ld.as r10, [sp, -8] -#endif -.endm - -#endif /* ARC_FEATURE_SEC_PRESENT */ -#endif /* __ASSEMBLY__ */ -#endif /* H_ARC_ASM_COMMON */ -/** @endcond */ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_builtin.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_builtin.h deleted file mode 100644 index 34437598..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_builtin.h +++ /dev/null @@ -1,498 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_BUILTIN - * @brief Header file of builtin and helper functions - * - * The Metaware toolchain and the GNU toolchain are supported. The details please go to see the file. - */ - -/** - * @addtogroup ARC_HAL_BUILTIN - * @{ - */ - -#ifndef H_ARC_BUILTIN -#define H_ARC_BUILTIN - -#include "embARC_toolchain.h" -#include "arc/arc.h" - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__MW__) /* Metaware toolchain */ - -#elif defined (__GNU__) /* GNU toolchain */ - -#endif - -/** - * @brief arc_compiler_usually(expr) evaluates expression expr and - * informs the compiler that the value is usually true. - */ -#define arc_compiler_usually(a) __builtin_expect(!!(a), 1) - -/** - * @brief arc_compiler_rarely(expr) evaluates expression expr and - * informs the compiler that the value is rarely true. - */ -#define arc_compiler_rarely(a) __builtin_expect(!!(a), 0) - -/** - * @fn void arc_mb(void) - * @brief Do memory barrier - * - */ -Inline void arc_mb(void) -{ - Asm("dmb 3\n" : : : "memory"); -} - -/** - * @fn void arc_rmb(void) - * @brief Read memory barrier - * - */ -Inline void arc_rmb(void) -{ - Asm("dmb 1\n" : : : "memory"); -} - -/** - * @fn void arc_wmb(void) - * @brief Write memory barrier - * - */ -Inline void arc_wmb(void) -{ - Asm("dmb 2\n" : : : "memory"); -} - -/** - * @fn uint32_t arc_aux_read(uint32_t aux) - * @brief Read auxiliary register - * - * @param aux auxiliary register address - * @return value of auxiliary register - */ -Inline uint32_t arc_aux_read(uint32_t aux) -{ - uint32_t ret; - - Asm("lr %0, [%1]" - : "=r" (ret) - : "r" (aux)); - - return ret; -} - -/** - * @fn void arc_aux_write(uint32_t aux, uint32_t val) - * @brief Write auxiliary register - * - * @param aux auxiliary register address - * @param val Value to write - */ -Inline void arc_aux_write(uint32_t aux, uint32_t val) -{ - Asm( - "sr %0, [%1] \n" - : - : "ir" (val), "r" (aux)); -} - -/** - * @fn void arc_brk(void) - * @brief Call brk instruction - * stop the core through a brk instruction - */ -Inline void arc_brk(void) -{ - Asm("brk"); -} - -/** - * @fn void arc_sync(void) - * @brief Call sync instruction - * - */ -Inline void arc_sync(void) -{ - Asm("sync"); -} - -/** - * @fn void arc_kflag(uint32_t flag) - * @brief Call kflag instruction to change status32 - * - * @param flag Flag to set in status32 - */ -Inline void arc_kflag(uint32_t flag) -{ - /*sr cannot write AUX_STATUS32 */ - Asm("kflag %0" ::"ir" (flag)); -} - -/** - * @fn void arc_nop(void) - * @brief Call nop_s function - * flush the pipeline by nop_s instruction - */ -Inline void arc_nop(void) -{ - Asm("nop_s"); -} - -/** - * @fn uint32_t arc_clri(void) - * @brief Call clri instruction - * call a clri instruction to disable interrupt - * @return interrupt related bits in status32 - */ -Inline uint32_t arc_clri(void) -{ - uint32_t v; - - Asm("clri %0" : "=r" (v):: "memory"); - return v; -} - -/** - * @fn void arc_seti(uint32_t key) - * @brief Call seti instruction - * call a set instruction to change interrupt status - * @param key interrupt status - */ -Inline void arc_seti(uint32_t key) -{ - Asm("seti %0" : : "ir" (key) : "memory"); -} - -/** - * @fn uint32_t arc_swap32(uint32_t val) - * @brief Swap bytes order of a 32-bits value - * - * @param val Target value - * @return Swapped value - */ -Inline uint32_t arc_swap32(uint32_t val) -{ - uint32_t v; - - Asm("swape %0, %1" : "=r" (v) : "r" (val)); - return v; -} - -/** - * @fn uint16_t arc_swap16(uint32_t val) - * @brief Swap bytes order of a 32-bits value and return high 16-bits - * - * @param val Target value - * @return High 16 bits of the swapped value - */ -Inline uint16_t arc_swap16(uint32_t val) -{ - uint32_t temp; - uint32_t v; - - Asm("swape %0, %1" : "=r" (temp) : "r" (val)); - Asm("lsr16 %0, %1" : "=r" (v) : "r" (temp)); - return (uint16_t)v; -} - -/** - * @name cache related helper function - * @{ - */ - -/** - * @fn arc_read_uncached_32(void *ptr) - * @brief Read memory and bypass the cache - * @param ptr Memory address - * @return data in the memory - */ -Inline uint32_t arc_read_uncached_32(void *ptr) -{ - uint32_t ret; - - Asm("ld.di %0, [%1]" : "=r" (ret) : "r" (ptr)); - return ret; -} - -/** - * @fn arc_write_uncached_32(void *ptr, uint32_t data) - * @brief Write memory and bypass the cache - * @param ptr memory address - * @param data value to be written - */ -Inline void arc_write_uncached_32(void *ptr, uint32_t data) -{ - Asm("st.di %0, [%1]" :: "r" (data), "r" (ptr)); -} - -/** - * @fn arc_read_cached_32(void *ptr) - * @brief Read memory with cache - * @param ptr Memory address - * @returns data in the memory - */ -Inline uint32_t arc_read_cached_32(void *ptr) -{ - uint32_t ret; - - Asm("ld %0, [%1]" : "=r" (ret) : "r" (ptr)); - return ret; -} - -/** - * @fn void arc_write_cached_32(void *ptr, uint32_t data) - * @brief Read memory with cache - * @param ptr Memory address - * @param data Data to be written - */ -Inline void arc_write_cached_32(void *ptr, uint32_t data) -{ - Asm("st %0, [%1]" :: "r" (data), "r" (ptr)); -} - -/** - * @fn int32_t arc_goto_main(int32_t argc, char **argv) - * @brief Go to main function with proper arguments - * @param argc Argument count - * @param argv Argument content array - * @retval Return value of main function - */ -Inline int32_t arc_goto_main(int32_t argc, char **argv) -{ - int32_t ret; - - Asm( - "mov %%r0, %1\n" - "mov %%r1, %2\n" - "push_s %%blink\n" - "jl main\n" - "pop_s %%blink\n" - "mov %0, %%r0" - : "=r" (ret) : "r" (argc), "r" (argv)); - return (int32_t)ret; -} - -/** - * @fn uint32_t arc_find_msb(uint32_t val) - * @brief Find most significant bit set in a 32-bit word - * - * This routine finds the first bit set starting from the most significant bit - * in the argument passed in and returns the index of that bit. Bits are - * numbered starting at 1 from the least significant bit. A return value of - * zero indicates that the value passed is zero. - * - * @return Most significant bit set, 0 if @a val is 0 - */ -Inline uint32_t arc_find_msb(uint32_t val) -{ - uint32_t bit; - - Asm( - /* BITSCAN_OPTION is required */ - "fls.f %0, %1;\n" - "add.nz %0, %0, 1;\n" - : "=r" (bit) - : "r" (val)); - - return bit; -} - -/** - * @fn uint32_t arc_find_lsb(uint32_t val) - * @brief Find least significant bit set in a 32-bit word - * - * This routine finds the first bit set starting from the least significant bit - * in the argument passed in and returns the index of that bit. Bits are - * numbered starting at 1 from the least significant bit. A return value of - * zero indicates that the value passed is zero. - * - * @return Least significant bit set, 0 if @a val is 0 - */ -Inline uint32_t arc_find_lsb(uint32_t val) -{ - uint32_t bit; - - Asm( - /* BITSCAN_OPTION is required */ - "ffs.f %0, %1;\n" - "add.nz %0, %0, 1;\n" - "mov.z %0, 0;\n" - : "=&r" (bit) - : "r" (val)); - - return bit; -} - -/** - * @fn uint32_t arc_core_id(void) - * @brief Read core id - * - * @return Core id - */ -Inline uint32_t arc_core_id(void) -{ - uint32_t ret; - - Asm( - "lr %0, [%1]\n" - "xbfu %0, %0, 0xe8\n" - : "=r" (ret) - : "i" (AUX_IDENTITY)); - - return ret; -} - -/** - * @fn void arc_stack_check_enable(void) - * @brief Enable hardware stack checking - */ -Inline void arc_stack_check_enable(void) -{ - -#if ARC_FEATURE_SEC_PRESENT - Asm( - "bset %0, %0, %1\n" - "sflag r0\n" - : - : "r" (arc_aux_read(AUX_SEC_STAT)), "i" (AUX_SEC_STAT_BIT_SSC)); -#else - Asm( - "bset %0, %0, %1\n" - "kflag r0\n" - : - : "r" (arc_aux_read(AUX_STATUS32)), "i" (AUX_STATUS_BIT_SC)); -#endif -} - -/** - * @fn void arc_stack_check_disable(void) - * @brief Disable hardware stack checking - */ -Inline void arc_stack_check_disable(void) -{ -#if ARC_FEATURE_SEC_PRESENT - Asm( - "bclr %0, %0, %1\n" - "sflag r0\n" - : - : "r" (arc_aux_read(AUX_SEC_STAT)), "i" (AUX_SEC_STAT_BIT_SSC)); -#else - Asm( - "bclr %0, %0, %1\n" - "kflag r0\n" - : - : "r" (arc_aux_read(AUX_STATUS32)), "i" (AUX_STATUS_BIT_SC)); -#endif -} - -/** - * @fn void arc_kernel_stack_check_configure(uint32_t top, uint32_t base) - * @brief Configure stack checking in kernel mode - * - * @param top Top of stack - * @param base Base of stack - */ -Inline void arc_kernel_stack_check_configure(uint32_t top, uint32_t base) -{ -#if ARC_FEATURE_SEC_PRESENT - arc_aux_write(AUX_S_KSTACK_TOP, top); - arc_aux_write(AUX_S_KSTACK_BASE, base); -#else - arc_aux_write(AUX_KSTACK_TOP, top); - arc_aux_write(AUX_KSTACK_BASE, base); -#endif -} - -/** - * @fn uint32_t arc_is_user_mode(void) - * @brief Check whether processor is in user mode - * this function relies on AUX_STATUS_BIT_US set in privileged mode first - * @return 1 user mode, 0 privileged mode - */ -Inline uint32_t arc_is_user_mode(void) -{ - uint32_t status; - - Asm( - "lr %0, [%1]\n" - : "=r" (status) - : "i" (AUX_STATUS32) - : "memory"); - - return !(status & AUX_STATUS_MASK_US) ? 1 : 0; -} - -/** - * @brief Go to user mode - * It's suggested to disable interrupt before call this function especially - * when using current stack, i.e., sp == 0. Because interrupt handling requires - * kernel mode stack which is different with user mode stack. - * @param target Target address to run in user mode, 0 means next - * line of code - * @param sp Stack where the target address runs, 0 means using - * current stack - */ -extern void arc_goto_usermode(void *target, uint32_t *sp); - -/** - * @brief Go to kernel mode - * this function uses trap exception to do switch from user mode to kernel mode, - * please install exc_entry_arc_goto_kernelmode for trap exception before call this - * function - * @param target Target address to run in kernel mode, 0 means next line of code - * @param sp Stack where the target address runs, 0 means using current stack - */ -extern void arc_goto_kernelmode(void *target, uint32_t *sp); - -/** - * @brief Trap exception entry used for arc_goto_kernelmode - * - * install this entry for trap exception before call arc_goto_kernelmode - */ -extern void exc_entry_arc_goto_kernelmode(void); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -/** @} */ -#endif /* H_ARC_BUILTIN */ -/** @} */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_cache.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_cache.h deleted file mode 100644 index a31fe727..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_cache.h +++ /dev/null @@ -1,331 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC_CACHE - * @brief Header file of cache module - */ - -#ifndef H_ARC_CACHE -#define H_ARC_CACHE - -#include "arc/arc_builtin.h" -#include "arc/arc_exception.h" - -/** - * @addtogroup ARC_HAL_MISC_CACHE - * @{ - */ -/** - * @name Marco definitions for cache control - * @todo These definitions will be reviewed. - * @{ - */ -#define IC_CTRL_IC_ENABLE (0x0) /*!< enable instruction cache */ -#define IC_CTRL_IC_DISABLE (0x1) /*!< disable instruction cache */ -#define IC_CTRL_DIRECT_ACCESS (0x0) /*!< direct access mode */ -#define IC_CTRL_INDIRECT_ACCESS (0x20) /*!< indirect access mode */ -#define IC_CTRL_OP_SUCCEEDED (0x8) /*!< instruction cache operation succeeded */ -/** @} */ - -/** - * @name Marco definitions for data cache control - * @todo These definition will be reviewed. - * @{ - */ -#define IC_CTRL_I -#define DC_CTRL_DC_ENABLE (0x0) /*!< enable data cache */ -#define DC_CTRL_DC_DISABLE (0x1) /*!< disable data cache */ -#define DC_CTRL_INVALID_ONLY (0x0) /*!< invalid data cache only */ -#define DC_CTRL_INVALID_FLUSH (0x40) /*!< invalid and flush data cache */ -#define DC_CTRL_ENABLE_FLUSH_LOCKED (0x80) /*!< the locked data cache can be flushed */ -#define DC_CTRL_DISABLE_FLUSH_LOCKED (0x0) /*!< the locked data cache cannot be flushed */ -#define DC_CTRL_FLUSH_STATUS (0x100) /*!< flush status */ -#define DC_CTRL_DIRECT_ACCESS (0x0) /*!< direct access mode */ -#define DC_CTRL_INDIRECT_ACCESS (0x20) /*!< indirect access mode */ -#define DC_CTRL_OP_SUCCEEDED (0x4) /*!< data cache operation succeeded */ -/** @} */ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name instruction cache related inline function - * @{ - */ - -/** - * @fn uint32_t icache_available(void) - * @brief Check whether instruction cache is available, - * @return 0 for not available, >0 for available - */ -Inline uint32_t icache_available(void) -{ - return (arc_aux_read(AUX_BCR_I_CACHE) & 0xF); -} - -/** - * @fn void icache_enable(uint32_t icache_en_mask) - * @brief Enable instruction cache - * @param icache_en_mask operation mask - */ -Inline void icache_enable(uint32_t icache_en_mask) -{ - if (!icache_available()) { - return; - } - arc_aux_write(AUX_IC_CTRL, icache_en_mask); -} - -/** - * @fn void icache_disable(void) - * @brief Disable instruction cache - */ -Inline void icache_disable(void) -{ - arc_aux_write(AUX_IC_CTRL, IC_CTRL_IC_DISABLE); -} - -/** - * @fn void icache_invalidate(void) - * @brief Invalidate the entire instruction cache - */ -Inline void icache_invalidate(void) -{ - /* invalidate the entire icache */ - arc_aux_write(AUX_IC_IVIC, 0); - arc_nop(); - arc_nop(); - arc_nop(); -} - -/** - * @fn void icache_invalidate_line(uint32_t address) - * @brief Invalidate specific cache line - * @param address Memory address - */ -Inline void icache_invalidate_line(uint32_t address) -{ - arc_aux_write(AUX_IC_IVIL, address); - /* the 3 nops are required by ARCv2 ISA */ - arc_nop(); - arc_nop(); - arc_nop(); -} - -/** - * @fn int32_t icache_lock_line(uint32_t address) - * @brief Lock specific cache line - * @param address Memory address - * @return 0, succeeded, -1, failed - */ -Inline int32_t icache_lock_line(uint32_t address) -{ - arc_aux_write(AUX_IC_LIL, address); - if (arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) { - return 0; - } else { - return -1; - } -} - -/** - * @fn void icache_access_mode(uint32_t mode) - * @brief Set icache access mode - * @param mode access mode, 1: indirect access 0:direct access - */ -Inline void icache_access_mode(uint32_t mode) -{ - if (mode) { - arc_aux_write(AUX_IC_CTRL, arc_aux_read(AUX_IC_CTRL) | IC_CTRL_INDIRECT_ACCESS); - } else { - arc_aux_write(AUX_IC_CTRL, arc_aux_read(AUX_IC_CTRL) & (~IC_CTRL_INDIRECT_ACCESS)); - } -} -/** @} */ - -/** - * @name data cache related inline functions - * @{ - */ - -/** - * @fn uint32_t dcache_available(void) - * @brief Check whether data cache is available, - * 0 for not available, >0 for available - */ -Inline uint32_t dcache_available(void) -{ - return (arc_aux_read(AUX_BCR_D_CACHE) & 0xF); -} - -/** - * @fn void dcache_invalidate(void) - * @brief Invalidate the entire data cache - */ -Inline void dcache_invalidate(void) -{ - uint32_t status; - - status = cpu_lock_save(); - arc_aux_write(AUX_DC_IVDC, 1); - /* wait for flush completion */ - while (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { - ; - } - cpu_unlock_restore(status); -} - -/** - * @fn void dcache_invalidate_line(uint32_t address) - * @brief Invalidate the specific cache line - * @param address Memory address - */ -Inline void dcache_invalidate_line(uint32_t address) -{ - arc_aux_write(AUX_DC_IVDL, address); - arc_nop(); - arc_nop(); - arc_nop(); -} - -/** - * @fn void dcache_enable(uint32_t dcache_en_mask) - * @brief Enable data cache - * @param dcache_en_mask Operation mask - */ -Inline void dcache_enable(uint32_t dcache_en_mask) -{ - arc_aux_write(AUX_DC_CTRL, dcache_en_mask); -} - -/** - * @fn void dcache_disable(void) - * @brief Disable data cache - */ -Inline void dcache_disable(void) -{ - arc_aux_write(AUX_DC_CTRL, DC_CTRL_DC_DISABLE); -} - -/** - * @fn void dcache_flush(void) - * @brief Flush data cache - */ -Inline void dcache_flush(void) -{ - uint32_t status; - - status = cpu_lock_save(); - arc_aux_write(AUX_DC_FLSH, 1); - /* wait for flush completion */ - while (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { - ; - } - cpu_unlock_restore(status); -} - -/** - * @fn void dcache_flush_line(uint32_t address) - * @brief Flush the specific data cache line - * @param address Memory address - */ -Inline void dcache_flush_line(uint32_t address) -{ - uint32_t status; - - status = cpu_lock_save(); - arc_aux_write(AUX_DC_FLDL, address); - while (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { - ; - } - cpu_unlock_restore(status); -} - -/** - * @fn int32_t dcache_lock_line(uint32_t address) - * @brief Lock the specific data cache line - * @param address Memory address - * @return 0, succeeded, -1, failed - */ -Inline int32_t dcache_lock_line(uint32_t address) -{ - arc_aux_write(AUX_DC_LDL, address); - if (arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) { - return 0; - } else { - return -1; - } -} - -/** - * @fn void dcache_access_mode(uint32_t mode) - * @brief Set dcache access mode - * @param mode Access mode, 1: indirect access 0:direct access - */ -Inline void dcache_access_mode(uint32_t mode) -{ - if (mode) { - arc_aux_write(AUX_DC_CTRL, arc_aux_read(AUX_DC_CTRL) | DC_CTRL_INDIRECT_ACCESS); - } else { - arc_aux_write(AUX_DC_CTRL, arc_aux_read(AUX_DC_CTRL) & (~DC_CTRL_INDIRECT_ACCESS)); - } -} - -/** @} */ - -/** - * @name declarations of cache related functions - * @{ - */ -extern int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size); -extern int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size); -extern int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data); -extern int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data); -extern int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data); -extern int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size); -extern int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size); -extern int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size); -extern int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data); -extern int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data); -extern int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data); -extern void arc_cache_init(void); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -/** @} */ -#endif /* H_ARC_CACHE */ -/** @} end of group ARC_HAL_MISC_CACHE */ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_connect.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_connect.h deleted file mode 100644 index eadedc35..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_connect.h +++ /dev/null @@ -1,250 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_ARC_CONNECT ARC_HAL - * @brief Header file of arc connect module - */ - -#ifndef H_ARC_CONNECT -#define H_ARC_CONNECT - -#include "arc/arc_builtin.h" - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ARC_CONNECT_CMD_CHECK_CORE_ID = 0x0, - - ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ = 0x1, - ARC_CONNECT_CMD_INTRPT_GENERATE_ACK = 0x2, - ARC_CONNECT_CMD_INTRPT_READ_STATUS = 0x3, - ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE = 0x4, - - ARC_CONNECT_CMD_SEMA_CLAIM_AND_READ = 0x11, - ARC_CONNECT_CMD_SEMA_RELEASE = 0x12, - ARC_CONNECT_CMD_SEMA_FORCE_RELEASE = 0x13, - - ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR = 0x21, - ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR = 0x22, - ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR_OFFSET = 0x23, - ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR_OFFSET = 0x24, - ARC_CONNECT_CMD_MSG_SRAM_WRITE = 0x25, - ARC_CONNECT_CMD_MSG_SRAM_WRITE_INC = 0x26, - ARC_CONNECT_CMD_MSG_SRAM_WRITE_IMM = 0x27, - ARC_CONNECT_CMD_MSG_SRAM_READ = 0x28, - ARC_CONNECT_CMD_MSG_SRAM_READ_INC = 0x29, - ARC_CONNECT_CMD_MSG_SRAM_READ_IMM = 0x2a, - ARC_CONNECT_CMD_MSG_SRAM_SET_ECC_CTRL = 0x2b, - ARC_CONNECT_CMD_MSG_SRAM_READ_ECC_CTRL = 0x2c, - - ARC_CONNECT_CMD_DEBUG_RESET = 0x31, - ARC_CONNECT_CMD_DEBUG_HALT = 0x32, - ARC_CONNECT_CMD_DEBUG_RUN = 0x33, - ARC_CONNECT_CMD_DEBUG_SET_MASK = 0x34, - ARC_CONNECT_CMD_DEBUG_READ_MASK = 0x35, - ARC_CONNECT_CMD_DEBUG_SET_SELECT = 0x36, - ARC_CONNECT_CMD_DEBUG_READ_SELECT = 0x37, - ARC_CONNECT_CMD_DEBUG_READ_EN = 0x38, - ARC_CONNECT_CMD_DEBUG_READ_CMD = 0x39, - ARC_CONNECT_CMD_DEBUG_READ_CORE = 0x3a, - - ARC_CONNECT_CMD_GFRC_CLEAR = 0x41, - ARC_CONNECT_CMD_GFRC_READ_LO = 0x42, - ARC_CONNECT_CMD_GFRC_READ_HI = 0x43, - ARC_CONNECT_CMD_GFRC_ENABLE = 0x44, - ARC_CONNECT_CMD_GFRC_DISABLE = 0x45, - ARC_CONNECT_CMD_GFRC_READ_DISABLE = 0x46, - ARC_CONNECT_CMD_GFRC_SET_CORE = 0x47, - ARC_CONNECT_CMD_GFRC_READ_CORE = 0x48, - ARC_CONNECT_CMD_GFRC_READ_HALT = 0x49, - - ARC_CONNECT_CMD_PDM_SET_PM = 0x81, - ARC_CONNECT_CMD_PDM_READ_PSTATUS = 0x82, - - ARC_CONNECT_CMD_PMU_SET_PUCNT = 0x51, - ARC_CONNECT_CMD_PMU_READ_PUCNT = 0x52, - ARC_CONNECT_CMD_PMU_SET_RSTCNT = 0x53, - ARC_CONNECT_CMD_PMU_READ_RSTCNT = 0x54, - ARC_CONNECT_CMD_PMU_SET_PDCNT = 0x55, - ARC_CONNECT_CMD_PMU_READ_PDCNT = 0x56, - - ARC_CONNECT_CMD_IDU_ENABLE = 0x71, - ARC_CONNECT_CMD_IDU_DISABLE = 0x72, - ARC_CONNECT_CMD_IDU_READ_ENABLE = 0x73, - ARC_CONNECT_CMD_IDU_SET_MODE = 0x74, - ARC_CONNECT_CMD_IDU_READ_MODE = 0x75, - ARC_CONNECT_CMD_IDU_SET_DEST = 0x76, - ARC_CONNECT_CMD_IDU_READ_DEST = 0x77, - ARC_CONNECT_CMD_IDU_GEN_CIRQ = 0x78, - ARC_CONNECT_CMD_IDU_ACK_CIRQ = 0x79, - ARC_CONNECT_CMD_IDU_CHECK_STATUS = 0x7a, - ARC_CONNECT_CMD_IDU_CHECK_SOURCE = 0x7b, - ARC_CONNECT_CMD_IDU_SET_MASK = 0x7c, - ARC_CONNECT_CMD_IDU_READ_MASK = 0x7d, - ARC_CONNECT_CMD_IDU_CHECK_FIRST = 0x7e -} ARC_CONNECT_CMD_T; - -typedef enum { - ARC_CONNECT_CMD_TYPE_CMD_ONLY = 0x0, - ARC_CONNECT_CMD_TYPE_CMD_RETURN = 0x1, - ARC_CONNECT_CMD_TYPE_CMD_WDATA = 0x2, - ARC_CONNECT_CMD_TYPE_CMD_WDATA_RETURN = 0x3 -} ARC_CONNECT_CMD_TYPE_T; - -typedef struct { - ARC_CONNECT_CMD_T cmd; - ARC_CONNECT_CMD_TYPE_T type; - uint32_t param; - uint32_t wdata; -} ARC_CONNECT_OP_T; - -#define ARC_CONNECT_INTRPT_TRIGGER_LEVEL 0 -#define ARC_CONNECT_INTRPT_TRIGGER_EDGE 1 - -#define ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN 0 -#define ARC_CONNECT_DISTRI_MODE_FIRST_ACK 1 -#define ARC_CONNECT_DISTRI_ALL_DEST 2 - -#define ARC_CONNECT_CORE_0 1 -#define ARC_CONNECT_CORE_1 2 -#define ARC_CONNECT_CORE_2 4 -#define ARC_CONNECT_CORE_3 8 - -#define ARC_CONNECT_OP_SET(op, cmd_v, type_v, param_v, wdata_v) { \ - (op)->cmd = (ARC_CONNECT_CMD_T)(cmd_v); \ - (op)->type = (ARC_CONNECT_CMD_TYPE_T)(type_v); \ - (op)->param = (uint32_t)(param_v); \ - (op)->wdata = (uint32_t)(wdata_v); } - -#define ARC_CONNECT_CMD_ONLY_OP_SET(op, cmd_v, param_v) { \ - (op)->cmd = (ARC_CONNECT_CMD_T)(cmd_v); \ - (op)->param = (uint32_t)(param_v); \ - (op)->type = ARC_CONNECT_CMD_TYPE_CMD_ONLY; } - -#define ARC_CONNECT_CMD_RETURN_OP_SET(op, cmd_v, param_v) { \ - (op)->cmd = (ARC_CONNECT_CMD_T)(cmd_v); \ - (op)->param = (uint32_t)(param_v); \ - (op)->type = ARC_CONNECT_CMD_TYPE_CMD_RETURN; } - -#define ARC_CONNECT_CMD_WDATA_OP_SET(op, cmd_v, param_v, wdata_v) \ - ARC_CONNECT_OP_SET(op, cmd_v, ARC_CONNECT_CMD_TYPE_CMD_WDATA, param_v, wdata_v) - -#define ARC_CONNECT_CMD_WDATA_RETURN_OP_SET(op, cmd_v, param_v, wdata_v) \ - ARC_CONNECT_OP_SET(op, cmd_v, ARC_CONNECT_CMD_TYPE_CMD_WDATA_RETURN, param_v, wdata_v) - -extern uint32_t arc_connect_check_core_id(void); - -/* inter-core interrupt related functions */ -extern void arc_connect_ici_generate(uint32_t core_id); -extern void arc_connect_ici_ack(uint32_t core_id); -extern uint32_t arc_connect_ici_read_status(uint32_t core_id); -extern uint32_t arc_connect_ici_check_src(void); - -/* inter-core semaphore related functions */ -extern uint32_t arc_connect_ics_take(uint32_t sem_id); -extern void arc_connect_ics_release(uint32_t sem_id); -extern void arc_connect_ics_force_release(uint32_t sem_id); - -/* inter-core message related functions */ -extern void arc_connect_icm_addr_set(uint32_t addr); -extern uint32_t arc_connect_icm_addr_read(void); -extern void arc_connect_icm_addr_offset_set(uint32_t offset); -extern uint32_t arc_connect_icm_addr_offset_read(void); -extern void arc_connect_icm_msg_write(uint32_t data); -extern void arc_connect_icm_msg_inc_write(uint32_t data); -extern void arc_connect_icm_msg_imm_write(uint32_t addr, uint32_t data); -extern uint32_t arc_connect_icm_msg_read(void); -extern uint32_t arc_connect_icm_msg_inc_read(void); -extern uint32_t arc_connect_icm_msg_imm_read(uint32_t addr); -extern void arc_connect_icm_ecc_ctrl_set(uint32_t val); -extern uint32_t arc_connect_icm_ecc_ctrl_read(void); - -/* inter-core debug related functions */ -extern void arc_connect_debug_reset(uint32_t cores); -extern void arc_connect_debug_halt(uint32_t cores); -extern void arc_connect_debug_run(uint32_t cores); -extern void arc_connect_debug_mask_set(uint32_t cores, uint32_t mask); -extern uint32_t arc_connect_debug_mask_read(uint32_t cores); -extern void arc_connect_debug_select_set(uint32_t cores); -extern uint32_t arc_connect_debug_select_read(void); -extern uint32_t arc_connect_debug_en_read(void); -extern uint32_t arc_connect_debug_cmd_read(void); -extern uint32_t arc_connect_debug_core_read(void); - -/* global free-running counter(gfrc) related functions */ -extern void arc_connect_gfrc_clear(void); -extern uint32_t arc_connect_gfrc_lo_read(void); -extern uint32_t arc_connect_gfrc_hi_read(void); -extern void arc_connect_gfrc_enable(void); -extern void arc_connect_gfrc_disable(void); -extern void arc_connect_gfrc_core_set(uint32_t cores); -extern uint32_t arc_connect_gfrc_halt_read(void); -extern uint32_t arc_connect_gfrc_core_read(void); - -/* power domain management related functions */ -extern void arc_connect_pdm_pm_set(uint32_t group, uint32_t cmd); -extern uint32_t arc_connect_pdm_pdstatus_read(uint32_t group); - -/* power management unit related functions */ -extern void arc_connect_pmu_pucnt_set(uint32_t cnt); -extern uint32_t arc_connect_pmu_pucnt_read(void); -extern void arc_connect_pmu_rstcnt_set(uint32_t cnt); -extern uint32_t arc_connect_pmu_rstcnt_read(void); -extern void arc_connect_pmu_pdccnt_set(uint32_t cnt); -extern uint32_t arc_connect_pmu_pdccnt_read(void); - -/* interrupt distribute unit related functions */ -extern void arc_connect_idu_enable(void); -extern void arc_connect_idu_disable(void); -extern uint32_t arc_connect_idu_read_enable(void); -extern void arc_connect_idu_set_mode(uint32_t irq_num, uint16_t trigger_mode, uint16_t distri_mode); -extern uint32_t arc_connect_idu_read_mode(uint32_t irq_num); -extern void arc_connect_idu_set_dest(uint32_t irq_num, uint32_t target_core); -extern uint32_t arc_connect_idu_read_dest(uint32_t irq_num); -extern void arc_connect_idu_gen_cirq(uint32_t irq_num); -extern void arc_connect_idu_ack_cirq(uint32_t irq_num); -extern uint32_t arc_connect_idu_check_status(uint32_t irq_num); -extern uint32_t arc_connect_idu_check_source(uint32_t irq_num); -extern void arc_connect_idu_set_mask(uint32_t irq_num, uint32_t mask); -extern uint32_t arc_connect_idu_read_mask(uint32_t irq_num); -extern uint32_t arc_connect_idu_check_first(uint32_t irq_num); -extern void arc_connect_idu_config_irq(uint32_t core, uint32_t irq_num, uint16_t trigger_mode, uint16_t distri_mode); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_CONNECT*/ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_em.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_em.h deleted file mode 100644 index b7f04c70..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_em.h +++ /dev/null @@ -1,127 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_CORE_EM - * @brief Header file of EM series - */ - -/** - * @addtogroup ARC_HAL_CORE_EM - * @{ - */ - -#ifndef H_ARC_EM -#define H_ARC_EM - -#include "arc/arc.h" - -/** - * @name Address Generation Unit (AGU) related auxiliary register - * @{ - */ -#define AUX_AGU_AP0 (0x5c0) -#define AUX_AGU_AP1 (0x5c1) -#define AUX_AGU_AP2 (0x5c2) -#define AUX_AGU_AP3 (0x5c3) -#define AUX_AGU_AP4 (0x5c4) -#define AUX_AGU_AP5 (0x5c5) -#define AUX_AGU_AP6 (0x5c6) -#define AUX_AGU_AP7 (0x5c7) -#define AUX_AGU_AP8 (0x5c8) -#define AUX_AGU_AP9 (0x5c9) -#define AUX_AGU_AP10 (0x5ca) -#define AUX_AGU_AP11 (0x5cb) -#define AUX_AGU_AP12 (0x5cc) -#define AUX_AGU_AP13 (0x5cd) -#define AUX_AGU_AP14 (0x5ce) -#define AUX_AGU_AP15 (0x5cf) - -#define AUX_AGU_OS0 (0x5d0) -#define AUX_AGU_OS1 (0x5d1) -#define AUX_AGU_OS2 (0x5d2) -#define AUX_AGU_OS3 (0x5d3) -#define AUX_AGU_OS4 (0x5d4) -#define AUX_AGU_OS5 (0x5d5) -#define AUX_AGU_OS6 (0x5d6) -#define AUX_AGU_OS7 (0x5d7) -#define AUX_AGU_OS8 (0x5d8) -#define AUX_AGU_OS9 (0x5d9) -#define AUX_AGU_OS10 (0x5da) -#define AUX_AGU_OS11 (0x5db) -#define AUX_AGU_OS12 (0x5dc) -#define AUX_AGU_OS13 (0x5dd) -#define AUX_AGU_OS14 (0x5de) -#define AUX_AGU_OS15 (0x5df) - -#define AUX_AGU_MOD0 (0x5e0) -#define AUX_AGU_MOD1 (0x5e1) -#define AUX_AGU_MOD2 (0x5e2) -#define AUX_AGU_MOD3 (0x5e3) -#define AUX_AGU_MOD4 (0x5e4) -#define AUX_AGU_MOD5 (0x5e5) -#define AUX_AGU_MOD6 (0x5e6) -#define AUX_AGU_MOD7 (0x5e7) -#define AUX_AGU_MOD8 (0x5e8) -#define AUX_AGU_MOD9 (0x5e9) -#define AUX_AGU_MOD10 (0x5ea) -#define AUX_AGU_MOD11 (0x5eb) -#define AUX_AGU_MOD12 (0x5ec) -#define AUX_AGU_MOD13 (0x5ed) -#define AUX_AGU_MOD14 (0x5ee) -#define AUX_AGU_MOD15 (0x5ef) -#define AUX_AGU_MOD16 (0x5f0) -#define AUX_AGU_MOD17 (0x5f1) -#define AUX_AGU_MOD18 (0x5f2) -#define AUX_AGU_MOD19 (0x5f3) -#define AUX_AGU_MOD20 (0x5f4) -#define AUX_AGU_MOD21 (0x5f5) -#define AUX_AGU_MOD22 (0x5f6) -#define AUX_AGU_MOD23 (0x5f7) -/** @} */ - -#define AUX_XCCM_BASE (0x5f8) -#define AUX_YCCM_BASE (0x5f9) - -/** @todo Add em series specific definitions here */ -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_EM */ - -/** @} */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_exception.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_exception.h deleted file mode 100644 index 6ffd521c..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_exception.h +++ /dev/null @@ -1,558 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT - * @brief Public interface for configuring interrupts and exceptions - */ - -#ifndef H_ARC_EXCEPTION -#define H_ARC_EXCEPTION - -#include "arc/arc_builtin.h" - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - */ -#ifndef NUM_EXC_CPU -/*!< number of CPU exceptions */ -#define NUM_EXC_CPU 16 -#endif - -#ifndef NUM_EXC_INT -/*!< number of interrupt exceptions, defined in arc_feature_config.h */ -#define NUM_EXC_INT 9 -#endif - -/*!< total number of exceptions */ -#define NUM_EXC_ALL (NUM_EXC_CPU + NUM_EXC_INT) - -#ifdef ARC_FEATURE_SEC_PRESENT -typedef struct { - uint32_t erbta; - - uint32_t r30; /* r30 is useless, skipped? */ - uint32_t ilink; /* r29 is useless, skipped?*/ - /* r28 is sp, saved other place */ - uint32_t fp; /* r27 */ - uint32_t gp; /* r26 */ - -#if ARC_FEATURE_DSP || ARC_FEATURE_FPU || ARC_FEATURE_MPU_OPTION_NUM > 6 - /* accl and acch, common for mpy_option >6 and fpu_fma option */ - uint32_t r59; - uint32_t r58; -#endif - - uint32_t r12; - - uint32_t lp_end, lp_start, lp_count; - -#if ARC_FEATURE_CODE_DENSITY - uint32_t ei, ldi, jli; -#endif - - uint32_t r0, r1, r2, r3; -#ifndef ARC_FEATURE_RF16 - uint32_t r4, r5, r6, r7, r8, r9; -#endif - uint32_t r10, r11; - - uint32_t blink; /* r31 */ - uint32_t ret; - uint32_t sec_stat; - uint32_t status32; -} EMBARC_PACKED INT_EXC_FRAME_T; -#else -typedef struct { - uint32_t erbta; - - uint32_t r30; /* r30 is useless, skipped? */ - uint32_t ilink; /* r29 is useless, skipped?*/ - /* r28 is sp, saved other place */ - uint32_t fp; /* r27 */ - uint32_t gp; /* r26 */ - -#if ARC_FEATURE_DSP || ARC_FEATURE_FPU || ARC_FEATURE_MPU_OPTION_NUM > 6 - /* accl and acch, common for mpy_option >6 and fpu_fma option */ - uint32_t r59; - uint32_t r58; -#endif - uint32_t r12; - - uint32_t r0, r1, r2, r3; -#ifndef ARC_FEATURE_RF16 - uint32_t r4, r5, r6, r7, r8, r9; -#endif - uint32_t r10, r11; - - uint32_t blink; /* r31 */ - - uint32_t lp_end, lp_start, lp_count; - -#if ARC_FEATURE_CODE_DENSITY - uint32_t ei, ldi, jli; -#endif - - uint32_t ret; - uint32_t status32; -} EMBARC_PACKED INT_EXC_FRAME_T; -#endif - -typedef struct { - /* todo xy memory support */ -#if ARC_FEATURE_DSP_COMPLEX - uint32_t dsp_fft_ctrl; - uint32_t dsp_bfly0; -#endif - uint32_t acc0_ghi; - uint32_t acc0_hi; - uint32_t acc0_glo; - uint32_t acc0_lo; - uint32_t dsp_ctrl; - -} EMBARC_PACKED DSP_EXT_FRAME_T; - -typedef struct { -#if ARC_FEATURE_FPU_DA - uint32_t dpfp2h; - uint32_t dpfp2l; - uint32_t dpfp1h; - uint32_t dpfp1l; -#endif - - uint32_t fpu_status; - uint32_t fpu_ctrl; - -} EMBARC_PACKED FPU_EXT_FRAME_T; - -typedef struct { - -#if ARC_FEATURE_FPU_DSP_CONTEXT - -#if ARC_FEATURE_DSP - DSP_EXT_FRAME_T dsp_regs; -#endif - -#if ARC_FEATURE_FPU - FPU_EXT_FRAME_T fpu_ext_regs; -#endif - -#endif /* ARC_FEATURE_FPU_DSP_CONTEXT */ - -#if defined(ARC_ENABLE_EXTRA_CALLEE) -#if ARC_FEATURE_SEC_PRESENT - uint32_t secure_kernel_sp; - uint32_t kernel_sp; -#else - uint32_t user_sp; -#endif -#endif - -#ifndef ARC_FEATURE_RF16 - uint32_t r25; - uint32_t r24; - uint32_t r23; - uint32_t r22; - uint32_t r21; - uint32_t r20; - uint32_t r19; - uint32_t r18; - uint32_t r17; - uint32_t r16; -#endif - uint32_t r15; - uint32_t r14; - uint32_t r13; -} EMBARC_PACKED CALLEE_FRAME_T; - -typedef struct { - CALLEE_FRAME_T callee_regs; - INT_EXC_FRAME_T exc_frame; -} EMBARC_PACKED PROCESSOR_FRAME_T; - -#define ARC_PROCESSOR_FRAME_T_SIZE (sizeof(PROCESSOR_FRAME_T) / sizeof(uint32_t)) -#define ARC_INT_EXC_FRAME_T_SIZE (sizeof(INT_EXC_FRAME_T) / sizeof(uint32_t)) -#define ARC_CALLEE_FRAME_T_SIZE (sizeof(CALLEE_FRAME_T) / sizeof(uint32_t)) - -/** - * @fn void arc_vector_base_write(uint32_t vec_base) - * @brief Write exception vector base - * - * @param vec_base Target vector base - */ -Inline void arc_vector_base_write(uint32_t vec_base) -{ - arc_aux_write(AUX_INT_VECT_BASE, vec_base); -} - -/** - * @fn uint32_t arc_vector_base_read(void) - * @brief Read current exception vector base - * - * @return Exception vector base (uint32_t) - */ -Inline uint32_t arc_vector_base_read(void) -{ - return arc_aux_read(AUX_INT_VECT_BASE); -} -/** @}*/ - -/** - * @addtogroup ARC_HAL_EXCEPTION_INTERRUPT - * @{ - */ -#ifndef INT_PRI_MIN -#define INT_PRI_MIN (-2) /*!< the minimum interrupt priority */ -#endif - -#define INT_PRI_MAX (-1) /*!< the maximum interrupt priority */ -/** - * @fn void arc_int_disable(const uint32_t intno) - * @brief Disable interrupt - * - * @param intno Interrupt number - */ -Inline void arc_int_disable(const uint32_t intno) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - arc_aux_write(AUX_IRQ_ENABLE, 0); -} - -/** - * @fn void arc_int_enable(const uint32_t intno) - * @brief Enable interrupt - * - * @param intno Interrupt number - */ -Inline void arc_int_enable(const uint32_t intno) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - arc_aux_write(AUX_IRQ_ENABLE, 1); -} - -/** - * @fn uint32_t arc_int_enabled(const uint32_t intno) - * @brief Check whether the specific interrupt is enabled - * - * @param intno Interrupt number - * @return 0 disabled, 1 enabled - */ -Inline uint32_t arc_int_enabled(const uint32_t intno) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - return arc_aux_read(AUX_IRQ_ENABLE); -} - -/** - * @fn uint32_t arc_int_ipm_get(void) - * @brief Get interrupt priority masking threshold - * - * @return Interrupt priority masking threshold, negative num - */ -Inline uint32_t arc_int_ipm_get(void) -{ - return ((arc_aux_read(AUX_STATUS32) >> 1) & 0x0f); -} - -/** - * @fn void arc_int_ipm_set(uint32_t intpri) - * @brief Set interrupt priority masking threshold - * - * @param intpri Interrupt priority masking threshold, negative num - */ -Inline void arc_int_ipm_set(uint32_t intpri) -{ - volatile uint32_t status; - - status = arc_aux_read(AUX_STATUS32) & ~0x1e; - - status = status | ((intpri << 1) & 0x1e); - arc_kflag(status); -} - -/** - * @fn uint32_t arc_int_pri_get(const uint32_t intno) - * @brief Get current interrupt priority masking threshold - * - * @param intno Interrupt number - */ -Inline uint32_t arc_int_pri_get(const uint32_t intno) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - return arc_aux_read(AUX_IRQ_PRIORITY) & 0xf; -} - -/** - * @fn void arc_int_pri_set(const uint32_t intno, uint32_t intpri) - * @brief Set interrupt priority - * - * @param intno Interrupt number - * @param intpri Interrupt priority - */ -Inline void arc_int_pri_set(const uint32_t intno, uint32_t intpri) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - arc_aux_write(AUX_IRQ_PRIORITY, intpri | (arc_aux_read(AUX_IRQ_PRIORITY) & 0xfffffff0)); -} - -/** - * @fn void arc_int_secure_set(const uint32_t intno, uint32_t secure) - * @brief Set interrupt secure or not secure - * @param intno Interrupt number - * @param secure 0 for normal, > 0 for secure - */ -Inline void arc_int_secure_set(const uint32_t intno, uint32_t secure) -{ - - arc_aux_write(AUX_IRQ_SELECT, intno); - - if (secure) { - arc_aux_write(AUX_IRQ_PRIORITY, arc_aux_read(AUX_IRQ_PRIORITY) | - (1 << AUX_IRQ_PRIORITY_BIT_S)); - } else { - arc_aux_write(AUX_IRQ_PRIORITY, arc_aux_read(AUX_IRQ_PRIORITY) & 0xf); - } - -} - -/** - * @fn uint32_t arc_int_probe(const uint32_t intno) - * @brief Probe interrupt pending state - * - * @param intno Interrupt number - * @returns 1 pending, 0 no pending, -1 error - */ -Inline uint32_t arc_int_probe(const uint32_t intno) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - return arc_aux_read(AUX_IRQ_PENDING); -} - -/** - * @fn void arc_int_sw_trigger(const uint32_t intno) - * @brief Trigger software interrupt - * - * @param intno Interrupt number - */ -Inline void arc_int_sw_trigger(const uint32_t intno) -{ - arc_aux_write(AUX_IRQ_HINT, intno); -} - -/** - * @fn void arc_int_level_config(const uint32_t intno, const uint32_t level) - * @brief Configure interrupt request mode. - * - * @param intno Interrupt number - * @param level 0-level triggered, 1-pluse triggered - */ -Inline void arc_int_level_config(const uint32_t intno, const uint32_t level) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - arc_aux_write(AUX_IRQ_TRIGGER, level); -} - -/** - * @fn uint32_t arc_int_level_get(const uint32_t intno) - * @brief Get interrupt request mode - * - * @param intno Interrupt number - * @return 0-level triggered, 1-pluse triggered - */ -Inline uint32_t arc_int_level_get(const uint32_t intno) -{ - arc_aux_write(AUX_IRQ_SELECT, intno); - return arc_aux_read(AUX_IRQ_TRIGGER) & 0x1; -} - -/** - * @fn void arc_lock(void) - * @brief Lock cpu to disable interrupts - */ -Inline void arc_lock(void) -{ - arc_clri(); -} - -/** - * @fn void arc_unlock(void) - * @brief Unlock cpu to enable interrupts - */ -Inline void arc_unlock(void) -{ - arc_seti(0); -} - -/** - * @fn uint32_t arc_locked(void) - * @brief Check if cpu is locked - * - * @return 1 locked, 0 unlocked - */ -Inline uint32_t arc_locked(void) -{ - if (arc_aux_read(AUX_STATUS32) & AUX_STATUS_MASK_IE) { - return 0; - } else { - return 1; - } -} - -/** - * @fn uint32_t arc_lock_save(void) - * @brief Lock cpu and return status - * - * @return CPU status - */ -Inline uint32_t arc_lock_save(void) -{ - return arc_clri(); -} - -/** - * @fn void arc_unlock_restore(const uint32_t status) - * @brief Unlock cpu with the specific status - * - * @param status CPU status saved by cpu_lock_save - */ -Inline void arc_unlock_restore(const uint32_t status) -{ - arc_seti(status); -} - -/** - * @fn uint32_t arc_int_active(void) - * @brief Check if interrupt is active - * - * @return 1 active, 0 inactive - */ -Inline uint32_t arc_int_active(void) -{ - if (arc_aux_read(AUX_IRQ_ACT) == 0) { - return 0; - } else { - return 1; - } -} -/** @}*/ - -/** - * @addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - */ -/** - * @typedef EXC_ENTRY_T - * @brief Data type for exception entry - */ -typedef void (*EXC_ENTRY_T) (void); -/** - * @typedef EXC_HANDLER_T - * @brief Data type for exception handler - */ -typedef void (*EXC_HANDLER_T) (void *exc_frame); -/** @}*/ - -/** - * @ingroup ARC_HAL_EXCEPTION_INTERRUPT - * @typedef INT_HANDLER_T - * @brief Data type for interrupt handler - */ -typedef void (*INT_HANDLER_T) (void *ptr); - -extern EXC_ENTRY_T exc_entry_table[NUM_EXC_ALL]; -extern EXC_HANDLER_T exc_int_handler_table[NUM_EXC_ALL]; - -/** @ingroup ARC_HAL_EXCEPTION_CPU - * @{ - */ -/** - * @fn exc_entry_reset - * @brief Reset entry - */ -extern void exc_entry_reset(void); -/** - * @fn exc_entry_cpu - * @brief Default CPU exception entry - */ -extern void exc_entry_cpu(void); - -/** - * @fn exc_entry_firq - * @brief Fast interrupt exception entry - */ -extern void exc_entry_firq(void); -/** - * @fn exc_entry_int - * @brief Interrupt exception entry - */ -extern void exc_entry_int(void); -/** @}*/ - -/* exception related apis */ -extern void exc_int_init(void); -extern int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY_T entry); -extern EXC_ENTRY_T exc_entry_get(const uint32_t excno); -extern int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER_T handler); -extern EXC_HANDLER_T exc_handler_get(const uint32_t excno); - -/* interrupt related apis */ -extern int32_t int_disable(const uint32_t intno); -extern int32_t int_enable(const uint32_t intno); -extern int32_t int_enabled(const uint32_t intno); -extern int32_t int_ipm_get(void); -extern int32_t int_ipm_set(int32_t intpri); -extern int32_t int_pri_get(const uint32_t intno); -extern int32_t int_pri_set(const uint32_t intno, int32_t intpri); -extern int32_t int_probe(const uint32_t intno); -extern int32_t int_sw_trigger(const uint32_t intno); -extern int32_t int_level_config(const uint32_t intno, const uint32_t level); -extern int32_t int_level_get(const uint32_t intno); -extern void cpu_lock(void); -extern void cpu_unlock(void); -extern uint32_t cpu_lock_save(void); -extern void cpu_unlock_restore(const uint32_t status); -extern int32_t int_handler_install(const uint32_t intno, INT_HANDLER_T handler); -extern INT_HANDLER_T int_handler_get(const uint32_t intno); -extern int32_t int_secure_set(const uint32_t intno, uint32_t secure); -extern void arc_firq_stack_set(uint8_t *firq_sp); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_EXCEPTION*/ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_feature_config.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_feature_config.h deleted file mode 100644 index f3271814..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_feature_config.h +++ /dev/null @@ -1,470 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC - * @brief Header file for arc feature configuration - */ - -/** - * @addtogroup ARC_HAL_MISC - * @{ - */ - -#ifndef H_ARC_FEATURE_CONFIG -#define H_ARC_FEATURE_CONFIG - -#ifdef EMBARC_TCF_GENERATED -#include "core_config.h" -#endif - -/** ARC baseline instruction set version number */ -#if !defined(ARC_FEATURE_ISA_VER) -#if defined(core_config_cir_identity_arcver) -#define ARC_FEATURE_ISA_VER core_config_cir_identity_arcver -#else -#define ARC_FEATURE_ISA_VER 0x42 -#endif -#endif - -#define ARC_FEATURE_ARC_EM 0x4 -#define ARC_FEATURE_ARC_HS 0x5 - -#if !defined(ARC_FEATURE_ARC_FAMILY) -#if defined(core_config_cir_identity_family) -#define ARC_FEATURE_ARC_FAMILY core_config_cir_identity_family -#else -#define ARC_FEATURE_ARC_FAMILY ARC_FEATURE_ARC_EM -#endif -#endif - -#if !defined(ARC_FEATURE_ARC_CORE_VER) -#if defined(core_config_cir_identity_corever) -#define ARC_FEATURE_ARC_CORE_VER core_config_cir_identity_corever -#else -#define ARC_FEATURE_ARC_CORE_VER 2 -#endif -#endif - -/** ARC CPU Clock Frequency in Hz unit */ -#if !defined(ARC_FEATURE_CPU_CLOCK_FREQ) -#if defined(core_config_clock_speed) -#define ARC_FEATURE_CPU_CLOCK_FREQ (core_config_clock_speed * 1000000) -#endif -#endif - -/** ARC PC size */ -#if !defined(ARC_FEATURE_PC_SIZE) -#if defined(core_config_pc_size) -#define ARC_FEATURE_PC_SIZE core_config_pc_size -#else -#define ARC_FEATURE_PC_SIZE 32 -#endif -#endif - -/** ARC LPC size */ -#if !defined(ARC_FEATURE_LPC_SIZE) -#if defined(core_config_lpc_size) -#define ARC_FEATURE_LPC_SIZE core_config_lpc_size -#else -#define ARC_FEATURE_LPC_SIZE 32 -#endif -#endif - -/** ARC Addr size */ -#if !defined(ARC_FEATURE_ADDR_SIZE) -#if defined(core_config_addr_size) -#define ARC_FEATURE_ADDR_SIZE core_config_addr_size -#else -#define ARC_FEATURE_ADDR_SIZE 32 -#endif -#endif - -/** ARC Endian/Byte Order */ -#define ARC_FEATURE_LITTLE_ENDIAN 1234 -#define ARC_FEATURE_BIG_ENDIAN 4321 - -#if !defined(ARC_FEATURE_BYTE_ORDER) -#if defined(core_config_bcr_isa_config_b) -#if core_config_bcr_isa_config_b == 0 -#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_LITTLE_ENDIAN -#else -#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_BIG_ENDIAN -#endif -#else -#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_LITTLE_ENDIAN -#endif -#endif - -/** Reduced register option, if enabled, ARC_FEATURE_RF16 will be defined */ -#if !defined(ARC_FEATURE_RF16) -#if defined(core_config_bcr_rf_build_e) && core_config_bcr_rf_build_e == 1 -#define ARC_FEATURE_RF16 -#endif -#endif - -/** Unaligned access option, if enabled, ARC_FEATURE_UNALIGNED will be defined */ -#if !defined(ARC_FEATURE_UNALIGNED) -#if defined(core_config_unaligned) && core_config_unaligned == 1 -#define ARC_FEATURE_UNALIGNED -#endif -#endif - -/** Code density option, if enabled, ARC_FEATURE_CODE_DENSITY will be defined */ -#if !defined(ARC_FEATURE_CODE_DENSITY) -#if defined(core_config_code_density) && core_config_code_density == 1 -#define ARC_FEATURE_CODE_DENSITY 1 -#else -#define ARC_FEATURE_CODE_DENSITY 0 -#endif -#endif - -/** The number of register file banks */ -#if !defined(ARC_FEATURE_RGF_NUM_BANKS) -#if defined(core_config_rgf_num_banks) -#define ARC_FEATURE_RGF_NUM_BANKS core_config_rgf_num_banks -#else -#define ARC_FEATURE_RGF_NUM_BANKS 1 -#endif -#endif - -/** The number of registers replicated per register bank */ -#if !defined(ARC_FEATURE_RGF_BANKED_REGS) -#if defined(core_config_rgf_banked_regs) -#define ARC_FEATURE_RGF_BANKED_REGS core_config_rgf_banked_regs -#endif -#endif - -/** Interrupt unit presence */ -#if !defined(ARC_FEATURE_INTERRUPTS_PRESENT) -#if defined(core_config_interrupts_present) -#define ARC_FEATURE_INTERRUPTS_PRESENT core_config_interrupts_present -#endif -#endif - -/** FIRQ_OPTION configuration option, 1 for enabled, 0 for disabled */ -#if !defined(ARC_FEATURE_FIRQ) -#if defined(core_config_bcr_irq_build_f) -#define ARC_FEATURE_FIRQ core_config_bcr_irq_build_f -#else -#define ARC_FEATURE_FIRQ 0 -#endif -#endif - -/** The number of interrupts */ -#if !defined(NUM_EXC_INT) -#if defined(core_config_interrupts_number) -#define NUM_EXC_INT core_config_interrupts_number -#endif -#endif - -/** The number of external interrupts */ -#if !defined(NUM_EXC_EXT_INT) -#if defined(core_config_interrupts_externals) -#define NUM_EXC_EXT_INT core_config_interrupts_externals -#endif -#endif - -/** The interrupt priority levels */ -#if !defined(INT_PRI_MIN) -#if defined(core_config_interrupts_priorities) -#define INT_PRI_MIN (-core_config_interrupts_priorities) -#endif -#endif - -/** Timer0 present or not */ -#if !defined(ARC_FEATURE_TIMER0_PRESENT) -#if defined(core_config_timer0) -#define ARC_FEATURE_TIMER0_PRESENT core_config_timer0 -#define ARC_FEATURE_TIMER0_LEVEL (core_config_timer0_level - core_config_interrupts_priorities) -#define ARC_FEATURE_TIMER0_VECTOR core_config_timer0_vector -#endif -#endif - -/** Timer1 present or not */ -#if !defined(ARC_FEATURE_TIMER1_PRESENT) -#if defined(core_config_timer1) -#define ARC_FEATURE_TIMER1_PRESENT core_config_timer1 -#define ARC_FEATURE_TIMER1_LEVEL (core_config_timer1_level - core_config_interrupts_priorities) -#define ARC_FEATURE_TIMER1_VECTOR core_config_timer1_vector -#endif -#endif - -/** Secure Timer0 present or not */ -#if !defined(ARC_FEATURE_SEC_TIMER0_PRESENT) -#if defined(core_config_sec_timer0) -#define ARC_FEATURE_SEC_TIMER0_PRESENT core_config_sec_timer0 -#define ARC_FEATURE_SEC_TIMER0_LEVEL (core_config_sec_timer0_level - core_config_interrupts_priorities) -#define ARC_FEATURE_SEC_TIMER0_VECTOR 20 -#endif -#endif - -/** Secure Timer1 present or not */ -#if !defined(ARC_FEATURE_SEC_TIMER1_PRESENT) -#if defined(core_config_sec_timer1) -#define ARC_FEATURE_SEC_TIMER1_PRESENT core_config_sec_timer1 -#define ARC_FEATURE_SEC_TIMER1_LEVEL (core_config_sec_timer1_level - core_config_interrupts_priorities) -#define ARC_FEATURE_SEC_TIMER1_VECTOR 21 -#endif -#endif - -/** 64bit RTC present or not */ -#if !defined(ARC_FEATURE_RTC_PRESENT) -#if defined(core_config_rtc) -#define ARC_FEATURE_RTC_PRESENT core_config_rtc -#endif -#endif - -/** ICCM Presence, base address and size */ -#if !defined(ARC_FEATURE_ICCM_PRESENT) -#if defined(core_config_iccm_present) && core_config_iccm_present == 1 -#define ARC_FEATURE_ICCM_PRESENT 1 -#define ARC_FEATURE_ICCM_BASE core_config_iccm_base -#define ARC_FEATURE_ICCM_SIZE core_config_iccm_size -#endif -#endif - -/** ICCM0 Presence, base address and size */ -#if !defined(ARC_FEATURE_ICCM0_PRESENT) -#if defined(core_config_iccm0_present) && core_config_iccm0_present == 1 -#define ARC_FEATURE_ICCM0_PRESENT 1 -#define ARC_FEATURE_ICCM0_BASE core_config_iccm0_base -#define ARC_FEATURE_ICCM0_SIZE core_config_iccm0_size -#endif -#endif - -/** ICCM1 Presence, base address and size */ -#if !defined(ARC_FEATURE_ICCM1_PRESENT) -#if defined(core_config_iccm1_present) && core_config_iccm1_present == 1 -#define ARC_FEATURE_ICCM1_PRESENT 1 -#define ARC_FEATURE_ICCM1_BASE core_config_iccm1_base -#define ARC_FEATURE_ICCM1_SIZE core_config_iccm1_size -#endif -#endif - -/** DCCM Presence, base address and size */ -#if !defined(ARC_FEATURE_DCCM_PRESENT) -#if defined(core_config_dccm_present) && core_config_dccm_present == 1 -#define ARC_FEATURE_DCCM_PRESENT 1 -#define ARC_FEATURE_DCCM_BASE core_config_dccm_base -#define ARC_FEATURE_DCCM_SIZE core_config_dccm_size -#ifdef core_config_dccm_interleave -#define ARC_FEATURE_DCCM_INTERLEAVE core_config_dccm_interleave -#endif -#endif -#endif - -/** ARC XY memory options */ -#if !defined(ARC_FEATURE_XY_MEM) -#if defined(core_config_xy) && core_config_xy == 1 -#define ARC_FEATURE_XY_MEM core_config_xy -#if defined(core_config_xy_x_base) -#define ARC_FEATURE_XCCM_PRESENT 1 -#define ARC_FEATURE_XCCM_BASE core_config_xy_x_base -#define ARC_FEATURE_YCCM_SIZE core_config_xy_size -#endif -#if defined(core_config_xy_y_base) -#define ARC_FEATURE_YCCM_PRESENT 1 -#define ARC_FEATURE_YCCM_BASE core_config_xy_y_base -#define ARC_FEATURE_YCCM_SIZE core_config_xy_size -#endif -#endif -#endif - -/** Peripheral memory region(DMP) base address, if dmp configured, this macro will be defined as base address */ -#if !defined(ARC_FEATURE_DMP_PERIPHERAL) -#if defined(core_config_cir_dmp_peripheral) -#define ARC_FEATURE_DMP_PERIPHERAL core_config_cir_dmp_peripheral -#endif -#endif - -/** MPU options */ -#if !defined(ARC_FEATURE_MPU_PRESENT) -#if defined(core_config_mpu_present) && core_config_mpu_present == 1 -#define ARC_FEATURE_MPU_PRESENT 1 -#define ARC_FEATURE_MPU_VERSION core_config_bcr_mpu_build_version -#define ARC_FEATURE_MPU_REGIONS core_config_mpu_regions -#ifdef core_config_bcr_mpu_build_i -#define ARC_FEATURE_MPU_BUILD_I core_config_bcr_mpu_build_i -#endif -#ifdef core_config_bcr_mpu_build_s -#define ARC_FEATURE_MPU_BUILD_S core_config_bcr_mpu_build_s -#endif -#endif -#endif - -/** Secure BCR SEC_BUILD BCR */ -#if !defined(ARC_FEATURE_SEC_PRESENT) -#if defined(core_config_bcr_sec_build) -#define ARC_FEATURE_SEC_PRESENT 1 -#define ARC_FEATURE_SEC_VERSION core_config_bcr_sec_build_version -#define ARC_FEATURE_SEC_BUILD_DSM core_config_bcr_sec_build_dsm -#define ARC_FEATURE_SEC_BUILD_NSM core_config_bcr_sec_build_nsm -#define ARC_FEATURE_SEC_BUILD_I1SM core_config_bcr_sec_build_i1sm -#define ARC_FEATURE_SEC_BUILD_I0SM core_config_bcr_sec_build_i0sm -#define ARC_FEATURE_SEC_BUILD_S core_config_bcr_sec_build_s -#define ARC_FEATURE_SEC_BUILD_EI core_config_bcr_sec_build_ei -#define ARC_FEATURE_SEC_BUILD_ED core_config_bcr_sec_build_ed -#endif -#endif - -#if !defined(ARC_FEATURE_SEC_MODES) -#if defined(core_config_sec_modes) -#define ARC_FEATURE_SEC_MODES core_config_sec_modes -#endif -#endif - -/** Data Cache options */ -#if !defined(ARC_FEATURE_DCACHE_PRESENT) -#if defined(core_config_dcache_present) && core_config_dcache_present == 1 -#define ARC_FEATURE_DCACHE_PRESENT 1 -#define ARC_FEATURE_DCACHE_BUILD core_config_bcr_d_cache_build -#define ARC_FEATURE_DCACHE_BUILD_VERSION core_config_bcr_d_cache_build_version -#define ARC_FEATURE_DCACHE_BUILD_ASSOC core_config_bcr_d_cache_build_assoc -#define ARC_FEATURE_DCACHE_BUILD_CAPACITY core_config_bcr_d_cache_build_capacity -#define ARC_FEATURE_DCACHE_BUILD_BSIZE core_config_bcr_d_cache_build_bsize -#define ARC_FEATURE_DCACHE_BUILD_FL core_config_bcr_d_cache_build_fl -#define ARC_FEATURE_DCACHE_BUILD_U core_config_bcr_d_cache_build_u -#define ARC_FEATURE_DCACHE_SIZE core_config_dcache_size -#define ARC_FEATURE_DCACHE_LINE_SIZE core_config_dcache_line_size -#define ARC_FEATURE_DCACHE_WAYS core_config_dcache_ways -#define ARC_FEATURE_DCACHE_FEATURE core_config_dcache_feature -#endif -#endif - -/** Instruction Cache options */ -#if !defined(ARC_FEATURE_ICACHE_PRESENT) -#if defined(core_config_icache_present) && core_config_icache_present == 1 -#define ARC_FEATURE_ICACHE_PRESENT 1 -#define ARC_FEATURE_ICACHE_BUILD core_config_bcr_i_cache_build -#define ARC_FEATURE_ICACHE_BUILD_VERSION core_config_bcr_i_cache_build_version -#define ARC_FEATURE_ICACHE_BUILD_ASSOC core_config_bcr_i_cache_build_assoc -#define ARC_FEATURE_ICACHE_BUILD_CAPACITY core_config_bcr_i_cache_build_capacity -#define ARC_FEATURE_ICACHE_BUILD_BSIZE core_config_bcr_i_cache_build_bsize -#define ARC_FEATURE_ICACHE_BUILD_FL core_config_bcr_i_cache_build_fl -#define ARC_FEATURE_ICACHE_BUILD_D core_config_bcr_i_cache_build_d -#define ARC_FEATURE_ICACHE_SIZE core_config_icache_size -#define ARC_FEATURE_ICACHE_LINE_SIZE core_config_icache_line_size -#define ARC_FEATURE_ICACHE_WAYS core_config_icache_ways -#define ARC_FEATURE_ICACHE_FEATURE core_config_icache_feature -#endif -#endif - -/** ARC uDMA options */ -#if !defined(ARC_FEATURE_DMAC) -#if defined(core_config_dmac) -#define ARC_FEATURE_DMAC core_config_dmac -#define CORE_DMAC_CHANNELS core_config_dmac_channels -#define CORE_DMAC_REGISTERS core_config_dmac_registers -#if core_config_bcr_dmac_build_int_cfg == 2 || core_config_bcr_dmac_build_int_cfg == 4 -#define DMA_MULTI_IRQ 1 -#else -#define DMA_MULTI_IRQ 0 -#endif -#define ARC_FEATURE_DMAC_PRESENT core_config_dmac -#define ARC_FEATURE_DMAC_VERSION core_config_bcr_dmac_build_version -#define ARC_FEATURE_DMAC_CHANNELS core_config_dmac_channels -#define ARC_FEATURE_DMAC_REGISTERS core_config_dmac_registers -#define ARC_FEATURE_DMAC_INT_CFG core_config_bcr_dmac_build_int_cfg -#define ARC_FEATURE_DMAC_FIFO_DEPTH core_config_dmac_fifo_depth - -#ifndef CORE_DMAC_INTERNAL_VERSION -#define CORE_DMAC_INTERNAL_VERSION ARC_FEATURE_DMAC_VERSION -#endif - -#ifdef ARC_FEATURE_SEC_TIMER0_PRESENT -#define DMA_IRQ_NUM_START 22 -#define ARC_FEATURE_DMAC_VECTOR_START 22 -#else -#define DMA_IRQ_NUM_START 20 -#define ARC_FEATURE_DMAC_VECTOR_START 20 -#endif -#endif -#endif - -/** ARC mpy option */ -#if !defined(ARC_FEATURE_MPU_OPTION_NUM) -#define ARC_FEATURE_MPU_OPTION_NUM core_config_mpy_option_num -#endif - -#if !defined(ARC_FEATURE_FPU_DSP_CONTEXT) -#define ARC_FEATURE_FPU_DSP_CONTEXT 1 /* whether to put FPU and DSP regs into the context */ -#endif - -/** ARC FPU options */ -#if !defined(ARC_FEATURE_FPU) -#if core_config_bcr_fpu_build_sp || core_config_bcr_fpu_build_dp -#define ARC_FEATURE_FPU 1 -#if core_config_bcr_fpu_build_da -#define ARC_FEATURE_FPU_DA 1 -#endif -#endif -#endif - -/** ARC DSP options */ -#if !defined(ARC_FEATURE_DSP) -#if core_config_dsp1 || core_config_dsp2 -#define ARC_FEATURE_DSP 1 -#if core_config_dsp_complex -#define ARC_FEATURE_DSP_COMPLEX 1 -#endif -#endif -#endif - -/** ARC Stack check options */ -#if !defined(ARC_FEATURE_STACK_CHECK) -#if core_config_stack_check -#define ARC_FEATURE_STACK_CHECK 1 -#endif -#endif - -/* ARC multi processors/cores related features */ -#if !defined(ARC_FEATURE_MP_NUM_CPUS) -#define ARC_FEATURE_MP_NUM_CPUS 1 -#endif - -#if !defined(ARC_FEATURE_CONNECT_PRESENT) -#if defined(core_config_connect_idu) && core_config_connect_idu > 1 -#define ARC_FEATURE_CONNECT_PRESENT 1 -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* H_ARC_FEATURE_CONFIG */ - -/** @} */ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_hs.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_hs.h deleted file mode 100644 index 99ad3196..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_hs.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_CORE_HS - * @brief header file of HS series - */ - -/** - * @addtogroup ARC_HAL_CORE_HS - * @{ - */ - -#ifndef H_ARC_HS -#define H_ARC_HS - -#include "arc/arc.h" - -#define AUX_TLBPD0 (0x460) -#define AUX_TLBPD1 (0x461) -#define AUX_TLBPD1_HL (0x463) -#define AUX_TLBINDEX (0x464) -#define AUX_TLBCOMMAND (0x465) -#define AUX_PID (0x468) -#define AUX_SASID0 (0x46a) -#define AUX_SASID1 (0x46b) -#define AUX_SCRATCH_DATA0 (0x46c) -#define AUX_BPU_FLUSH (0x480) -#define AUX_BPU_CTRL (0x481) -#define AUX_IO_COH_ENABLE (0x500) -#define AUX_IO_COH_PARTIAL (0x501) -#define AUX_IO_COH_AP0_BASE (0x508) -#define AUX_IO_COH_AP0_SIZE (0x509) -#define AUX_IO_CACHE_ENABLE (0x520) -#define AUX_IO_CACHE_AP0_BASE (0x528) -#define AUX_IO_CACHE_AP0_SIZE (0x529) - -#define AUX_SLC_AUX_CACHE_CONFIG (0x901) -#define AUX_SLC_AUX_CACHE_CTRL (0x903) -#define AUX_SLC_AUX_CACHE_FLUSH (0x904) -#define AUX_SLC_AUX_CACHE_INV (0x905) - -#define AUX_SLC_AUX_CACHE_LOCK0 (0x906) -#define AUX_SLC_AUX_CACHE_LOCK1 (0x907) -#define AUX_SLC_AUX_CACHE_LOCK2 (0x908) -#define AUX_SLC_AUX_CACHE_LOCK3 (0x909) -#define AUX_SLC_AUX_CACHE_LOCK4 (0x90a) -#define AUX_SLC_AUX_CACHE_LOCK5 (0x90b) -#define AUX_SLC_AUX_CACHE_LOCK6 (0x90c) -#define AUX_SLC_AUX_CACHE_LOCK7 (0x90d) - -#define AUX_SLC_AUX_LINE_LOCK (0x90e) -#define AUX_SLC_AUX_LINE_LOCK1 (0x90f) -#define AUX_SLC_AUX_LINE_INV (0x910) -#define AUX_SLC_AUX_LINE_INV1 (0x911) -#define AUX_SLC_AUX_LINE_FLUSH (0x912) -#define AUX_SLC_AUX_LINE_FLUSH1 (0x913) -#define AUX_SLC_AUX_RGN_START (0x914) -#define AUX_SLC_AUX_RGN_START1 (0x915) -#define AUX_SLC_AUX_RGN_END (0x916) -#define AUX_SLC_AUX_RGN_END1 (0x917) -#define AUX_SLC_AUX_LINE_ADDR (0x918) -#define AUX_SLC_AUX_LINE_ADDR1 (0x919) -#define AUX_SLC_AUX_DIRECT_IDX (0x91a) -#define AUX_SLC_AUX_TAG_DATA (0x91b) -#define AUX_SLC_AUX_TAG_DATA1 (0x91c) -#define AUX_SLC_AUX_STATUS_DATA (0x91d) -#define AUX_SLC_AUX_DATA0 (0x91f) -#define AUX_SLC_AUX_DATA1 (0x920) -#define AUX_SLC_AUX_DATA2 (0x921) -#define AUX_SLC_AUX_DATA3 (0x922) -#define AUX_SLC_AUX_FAULT_ADDR (0x923) -#define AUX_SLC_AUX_FAULT_ADDR1 (0x924) -#define AUX_SLC_AUX_FAULT_STAT (0x925) -#define AUX_SLC_AUX_PM_CMD (0x926) -#define AUX_SLC_AUX_PM_EVENT (0x927) -#define AUX_SLC_AUX_PM_OVF (0x928) -#define AUX_SLC_AUX_PM_CNT0 (0x929) -#define AUX_SLC_AUX_PM_CNT1 (0x92a) - -/** @todo add hs series specific definitions here */ -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_HS */ -/** @}*/ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_mp.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_mp.h deleted file mode 100644 index 3fc82e79..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_mp.h +++ /dev/null @@ -1,154 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2019, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_ARC_MP -#define H_ARC_MP - -/* ARC multi processors/cores related functions */ -#include "arc/arc_builtin.h" - -#ifndef INTNO_ICI -#define INTNO_ICI 19 /* inter-core interrupt intno */ -#endif - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -/* smp barrier */ -#define arc_smp_mb() arc_mb() - -typedef struct { - volatile uint32_t slock; -} ARC_SPINLOCK_T; - -#define ARC_SPIN_LOCK_LOCKED 1 -#define ARC_SPIN_LOCK_UNLOCKED 0 - -/** - * @fn void arc_spinlock_get(ARC_SPINLOCK_T *lock) - * @brief Get a spin lock - * - * @param lock Spin lock to get - */ -Inline void arc_spinlock_get(ARC_SPINLOCK_T *lock) -{ -#if ARC_FEATURE_ARC_FAMILY == ARC_FEATURE_ARC_HS - uint32_t val; - - arc_smp_mb(); - - Asm( - "1: llock %[val], [%[slock]] \n" - " breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */ - " scond %[LOCKED], [%[slock]] \n" /* acquire */ - " bnz 1b \n" - " \n" - :[val] "=&r" (val) - :[slock] "r" (&(lock->slock)), - [LOCKED] "r" (ARC_SPIN_LOCK_LOCKED) - : "memory", "cc"); - - arc_smp_mb(); -#else - lock->slock = arc_clri(); -#endif -} - -/** - * @fn int32_t arc_spinlock_try(ARC_SPINLOCK_T *lock) - * @brief Try to get a spinlock - * - * @param lock Spin lock to get - * @return 0 failed, 1 success - */ -Inline int32_t arc_spinlock_try(ARC_SPINLOCK_T *lock) -{ - -#if ARC_FEATURE_ARC_FAMILY == ARC_FEATURE_ARC_HS - uint32_t val, got_it = 0; - - arc_smp_mb(); - - Asm( - "1: llock %[val], [%[slock]] \n" - " breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */ - " scond %[LOCKED], [%[slock]] \n" /* acquire */ - " bnz 1b \n" - " mov %[got_it], 1 \n" - "4: \n" - " \n" - :[val] "=&r" (val), [got_it] "+&r" (got_it) - :[slock] "r" (&(lock->slock)), - [LOCKED] "r" (ARC_SPIN_LOCK_LOCKED) - : "memory", "cc"); - arc_smp_mb(); - - return got_it; -#else - lock->slock = arc_clri(); - - return 1; -#endif -} - -/** - * @fn void arc_spinlock_release(ARC_SPINLOCK_T *lock) - * @brief release a spin lock - * - * @param lock Spin lock to release - */ -Inline void arc_spinlock_release(ARC_SPINLOCK_T *lock) -{ -#if ARC_FEATURE_ARC_FAMILY == ARC_FEATURE_ARC_HS - arc_smp_mb(); - - lock->slock = ARC_SPIN_LOCK_UNLOCKED; - - arc_smp_mb(); -#else - arc_seti(lock->slock); -#endif -} - -/* variables required by start up of multi-core */ -extern volatile uint32_t arc_cpu_wake_flag; -extern volatile uint8_t *arc_cpu_sp; - -extern void arc_start_slave_cpu(uint32_t cpu_num, uint8_t *stack, uint32_t sz, - void (*fn)(uint32_t, void *), void *arg); -extern void arc_slave_start(uint32_t cpu_num); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_MP */ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_mpu.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_mpu.h deleted file mode 100644 index 978a7f38..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_mpu.h +++ /dev/null @@ -1,172 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MPU - * @brief Header file of mpu module - */ - -#ifndef H_ARC_MPU -#define H_ARC_MPU - -#include "arc/arc_builtin.h" - -/** - * @addtogroup ARC_HAL_MISC_MPU - * @{ - */ -#ifndef ARC_FEATURE_MPU_VERSION -#define ARC_FEATURE_MPU_VERSION 2 -#endif - -#ifndef ARC_FEATURE_MPU_REGIONS -#define ARC_FEATURE_MPU_REGIONS arc_mpu_regions() -#endif - -#define AUX_MPU_VALID_MASK (0x1) -#define AUX_MPU_EN_ENABLE (0x40000000) -#define AUX_MPU_EN_DISABLE (0xBFFFFFFF) - -#define AUX_MPU_RDP_REGION_SIZE(bits) \ - (((bits - 1) & 0x3) | (((bits - 1) & 0x1C) << 7)) - -#if ARC_FEATURE_MPU_VERSION == 2 -#define AUX_MPU_ATTR_MASK (0xFFB) -#elif ARC_FEATURE_MPU_VERSION == 4 -#define AUX_MPU_ATTR_MASK (0xFF81F9) -#else -#define AUX_MPU_ATTR_MASK (0xFFFFFFFF) -#endif - -#define AUX_MPU_ATTR_UE 0x008 /* allow user execution */ -#define AUX_MPU_ATTR_UW 0x010 /* allow user write */ -#define AUX_MPU_ATTR_UR 0x020 /* allow user read */ -#define AUX_MPU_ATTR_KE 0x040 /* only allow kernel execution */ -#define AUX_MPU_ATTR_KW 0x080 /* only allow kernel write */ -#define AUX_MPU_ATTR_KR 0x100 /* only allow kernel read */ -#define AUX_MPU_ATTR_S 0x8000 /* secure */ -#define AUX_MPU_ATTR_N 0x0000 /* normal */ - -#define AUX_MPU_ATTR_SID_OFFSET 16 -#define AUX_MPU_ATTR_SID_MASK (0xFF << AUX_MPU_ATTR_SID_OFFSET) -#define AUX_MPU_ATTR_SID(x) (x << AUX_MPU_ATTR_SID_OFFSET) - -#define AUX_MPU_INDEX_DEFAULT 0x80000000 -#define AUX_MPU_INDEX_MULT 0x40000000 - -#if ARC_FEATURE_MPU_VERSION == 2 -#define ARC_FEATURE_MPU_ALIGNMENT_BITS 11 -#elif ARC_FEATURE_MPU_VERSION == 4 -#define ARC_FEATURE_MPU_ALIGNMENT_BITS 5 -#endif - -/* derived region alignment settings */ -#define ARC_FEATURE_MPU_ALIGNMENT (1UL << ARC_FEATURE_MPU_ALIGNMENT_BITS) -#define ARC_FEATURE_MPU_ALIGNMENT_MASK (ARC_FEATURE_MPU_ALIGNMENT - 1) - -/* Some helper defines for common regions */ -#define ARC_MPU_REGION_RAM_ATTR \ - (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \ - AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR) - -#define ARC_MPU_REGION_FLASH_ATTR \ - (AUX_MPU_ATTR_UE | AUX_MPU_ATTR_UR | \ - AUX_MPU_ATTR_KE | AUX_MPU_ATTR_KR) - -#define ARC_MPU_REGION_IO_ATTR \ - (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \ - AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR) - -#define ARC_MPU_REGION_ALL_ATTR \ - (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \ - AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \ - AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE) - -#define REGION_32B (0x200) -#define REGION_64B (0x201) -#define REGION_128B (0x202) -#define REGION_256B (0x203) -#define REGION_512B (0x400) -#define REGION_1K (0x401) -#define REGION_2K (0x402) -#define REGION_4K (0x403) -#define REGION_8K (0x600) -#define REGION_16K (0x601) -#define REGION_32K (0x602) -#define REGION_64K (0x603) -#define REGION_128K (0x800) -#define REGION_256K (0x801) -#define REGION_512K (0x802) -#define REGION_1M (0x803) -#define REGION_2M (0xA00) -#define REGION_4M (0xA01) -#define REGION_8M (0xA02) -#define REGION_16M (0xA03) -#define REGION_32M (0xC00) -#define REGION_64M (0xC01) -#define REGION_128M (0xC02) -#define REGION_256M (0xC03) -#define REGION_512M (0xE00) -#define REGION_1G (0xE01) -#define REGION_2G (0xE02) -#define REGION_4G (0xE03) - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @fn uint8_t arc_mpu_regions(void) - */ -Inline uint8_t arc_mpu_regions(void) -{ - uint32_t num = arc_aux_read(AUX_BCR_MPU); - - num = (num & 0xFF00) >> 8; - - return (uint8_t)num; -} - -extern void arc_mpu_enable(void); -extern void arc_mpu_disable(void); -extern void arc_mpu_region_config(uint32_t index, uint32_t base, uint32_t size, uint32_t region_attr); -extern void arc_mpu_default(uint32_t region_attr); -extern int32_t arc_mpu_in_region(uint32_t index, uint32_t start, uint32_t size); -extern int32_t arc_mpu_probe(uint32_t addr); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_MPU */ -/** @} end of group ARC_HAL_MISC_MPU */ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_timer.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_timer.h deleted file mode 100644 index c865edfd..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_timer.h +++ /dev/null @@ -1,125 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC_TIMER - * @brief header file of ARC internal timer - */ - -/** - * @addtogroup ARC_HAL_MISC_TIMER - * @{ - */ - -#ifndef H_ARC_TIMER -#define H_ARC_TIMER - -#include "arc/arc_builtin.h" - -/** - * @name arc internal timers names - * @{ - */ -#define TIMER_0 0 /*!< macro name for arc internal timer 0 */ -#define TIMER_1 1 /*!< macro name for arc internal timer 1 */ -#define TIMER_RTC 2 /*!< macro name for arc internal RTC */ -#define SECURE_TIMER_0 0 /*!< macro name for arc internal secure timer 0 */ -#define SECURE_TIMER_1 1 /*!< macro name for arc internal secure timer 1 */ - -/** @} */ -#ifdef ARC_FEATURE_TIMER0_VECTOR -#define INTNO_TIMER0 ARC_FEATURE_TIMER0_VECTOR /*!< ARC Timer0 */ -#else -#define INTNO_TIMER0 16 -#endif -#ifdef ARC_FEATURE_TIMER1_VECTOR -#define INTNO_TIMER1 ARC_FEATURE_TIMER1_VECTOR /*!< ARC Timer1 */ -#else -#define INTNO_TIMER1 17 -#endif -#ifdef ARC_FEATURE_SEC_TIMER0_VECTOR -#define INTNO_SECURE_TIMER0 ARC_FEATURE_SEC_TIMER0_VECTOR /*!< Core Secure Timer 0 */ -#else -#define INTNO_SECURE_TIMER0 20 -#endif -#ifdef ARC_FEATURE_SEC_TIMER1_VECTOR -#define INTNO_SECURE_TIMER1 ARC_FEATURE_SEC_TIMER1_VECTOR /*!< Core Secure Timer 1 */ -#else -#define INTNO_SECURE_TIMER1 21 -#endif -/** - * @name bit definition of RTC CTRL reg - * @{ - */ - -#define TIMER_RTC_ENABLE (0x01) /*!< enable RTC */ -#define TIMER_RTC_CLEAR (0x02) /* clears the AUX_RTC_LOW and AUX_RTC_HIGH */ -#define TIMER_RTC_STATUS_A0 (0x40000000) /*!< track bit of atomicity of reads of RTC */ -#define TIMER_RTC_STATUS_A1 (0x80000000) /*!< track bit of atomicity of reads of RTC */ -/** @} */ - -/** - * @name bit definition of timer CTRL reg - * @{ - */ -#define TIMER_CTRL_IE (1 << 0) /*!< Interrupt when count reaches limit */ -#define TIMER_CTRL_NH (1 << 1) /*!< Count only when CPU NOT halted */ -#define TIMER_CTRL_W (1 << 2) /*!< watchdog enable */ -#define TIMER_CTRL_IP (1 << 3) /*!< interrupt pending */ - -/** @} */ -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -extern int32_t timer_present(const uint32_t no); -extern int32_t timer_start(const uint32_t no, const uint32_t mode, const uint32_t val); -extern int32_t timer_stop(const uint32_t no); -extern int32_t timer_current(const uint32_t no, void *val); -extern int32_t timer_int_clear(const uint32_t no); -extern void arc_timer_init(void); -extern void arc_delay_us(uint32_t usecs); -extern uint64_t timer_calibrate_delay(uint32_t cpu_clock); -extern int32_t secure_timer_present(const uint32_t no); -extern int32_t secure_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val); -extern int32_t secure_timer_stop(const uint32_t no); -extern int32_t secure_timer_current(const uint32_t no, void *val); -extern int32_t secure_timer_int_clear(const uint32_t no); -extern void secure_timer_init(void); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_TIMER */ -/** @}*/ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_udma.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_udma.h deleted file mode 100644 index 4bd3ff1a..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_udma.h +++ /dev/null @@ -1,330 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup ARC_HAL_MISC_UDMA - * @brief header file for ARC uDMA Controller - */ - -/** - * @addtogroup ARC_HAL_MISC_UDMA - * @{ - */ -#ifndef H_ARC_UDMA -#define H_ARC_UDMA - -#include -#include -#include -#include "arc/arc_builtin.h" -#include "arc/arc_cache.h" - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef CORE_DMAC_INTERNAL_VERSION -/** Version of the DMA controller */ -#define CORE_DMAC_INTERNAL_VERSION 2 -#endif - -#ifndef DMA_MULTI_IRQ -/** Multiple interrupts for DMA */ -#define DMA_MULTI_IRQ 0 -#endif - -#ifndef DMA_IRQ_PRIO -/** DMA IRQ priority */ -#define DMA_IRQ_PRIO (INT_PRI_MIN) -#endif - -#ifndef DMA_IRQ_NUM_START -/** DMA IRQ start vector */ -#define DMA_IRQ_NUM_START 20 -#endif - -#ifndef DMA_ALL_CHANNEL_NUM -/*!< Number of all DMA channels */ -#ifdef CORE_DMAC_CHANNELS -#define DMA_ALL_CHANNEL_NUM CORE_DMAC_CHANNELS -#else -#define DMA_ALL_CHANNEL_NUM 2 -#endif -#endif - -#ifndef DMA_REGISTER_CHANNEL_NUM -/*!< Number of all aux-register based DMA channels */ -#ifdef CORE_DMAC_REGISTERS -#define DMA_REGISTER_CHANNEL_NUM CORE_DMAC_REGISTERS -#else -#define DMA_REGISTER_CHANNEL_NUM 0 -#endif -#endif - -/*!< Mask of all DMA channels at the most */ -#define DMA_ALL_CHANNEL_MASK 0xFFFF - -#define DMACTRLx_OP_OFS (0) /*!< bit field offset: bit 0,1 */ -#define DMACTRLx_R_OFS (2) /*!< bit field offset: bit 2 */ -#define DMACTRLx_DTT_OFS (3) /*!< bit field offset: bit 3,4 */ -#define DMACTRLx_DWINC_OFS (5) /*!< bit field offset: bit 5,6,7 */ -#define DMACTRLx_SIZE_OFS (8) /*!< bit field offset: bit 8..20 */ -#define DMACTRLx_ARB_OFS (21) /*!< bit field offset: bit 21..28 */ -#define DMACTRLx_INT_OFS (29) /*!< bit field offset: bit 29 */ -#define DMACTRLx_AM_OFS (30) /*!< bit field offset: bit 30,31 */ - -#define DMACTRLx_OP(x) ((x) << DMACTRLx_OP_OFS) /*!< bit field value: bit 0,1 */ -#define DMACTRLx_R(x) ((x) << DMACTRLx_R_OFS) /*!< bit field value: bit 2 */ -#define DMACTRLx_DTT(x) ((x) << DMACTRLx_DTT_OFS) /*!< bit field value: bit 3,4 */ -#define DMACTRLx_DWINC(x) ((x) << DMACTRLx_DWINC_OFS) /*!< bit field value: bit 5,6,7 */ -#define DMACTRLx_SIZE(x) ((x) << DMACTRLx_SIZE_OFS) /*!< bit field value: bit 8..20 */ -#define DMACTRLx_ARB(x) ((x) << DMACTRLx_ARB_OFS) /*!< bit field value: bit 21..28 */ -#define DMACTRLx_INT(x) ((x) << DMACTRLx_INT_OFS) /*!< bit field value: bit 29 */ -#define DMACTRLx_AM(x) ((x) << DMACTRLx_AM_OFS) /*!< bit field value: bit 30,31 */ - -#define DMACTRLx_OP_MASK DMACTRLx_OP(0x3) /*!< bit field mask: bit 0,1 */ -#define DMACTRLx_R_MASK DMACTRLx_R(0x1) /*!< bit field mask: bit 2 */ -#define DMACTRLx_DTT_MASK DMACTRLx_DTT(0x3) /*!< bit field mask: bit 3,4 */ -#define DMACTRLx_DWINC_MASK DMACTRLx_DWINC(0x7) /*!< bit field mask: bit 5,6,7 */ -#define DMACTRLx_SIZE_MASK DMACTRLx_SIZE(0x1FFF) /*!< bit field mask: bit 8..20 */ -#define DMACTRLx_ARB_MASK DMACTRLx_ARB(0xFF) /*!< bit field mask: bit 21..28 */ -#define DMACTRLx_INT_MASK DMACTRLx_INT(0x1) /*!< bit field mask: bit 29 */ -#define DMACTRLx_AM_MASK DMACTRLx_AM(0x3) /*!< bit field mask: bit 30,31 */ - -#define DMACHANNEL(x) ((0x1 << (x)) & 0xFFFF) /*!< Channel number to Bit */ - -/** Handler function for uDAM callback, param should be current dma channel transfer structure DMA_CHANNEL_T */ -typedef void (*DMA_CALLBACK_T) (void *param); - -typedef struct { - uint32_t op : 2; /*!< operation field */ - uint32_t rt : 1; /*!< request type field */ - uint32_t dtt : 2; /*!< source and destination target types field */ - uint32_t dwinc : 3; /*!< data width and address increment field */ - uint32_t blksz : 13; /*!< data transfer in bytes field */ - uint32_t arb : 8; /*!< arbitration size */ - uint32_t intm : 1; /*!< interrupt mode bit */ - uint32_t am : 2; /*!< address mode field */ -} DMA_CTRL_FIELD_T; - -/** DMA channel control register union */ -typedef union { - DMA_CTRL_FIELD_T bits; /*!< control register in bits format */ - uint32_t value; /*!< control register in word format */ -} DMA_CTRL_T; - -/** DMA working status enumeration */ -#define DMA_IDLE 0 /*!< Current DMA status is IDLE */ -#define DMA_BUSY 1 /*!< Current DMA status is busy, in transfer */ -#define DMA_ERROR 2 /*!< Current DMA status is error, in transfer error */ -#define DMA_STOP 3 /*!< Current DMA is stop by user */ - -#define DMA_CHN_ANY -1 /*!< Any channel, request one */ -#define DMA_CHN_INVALID -2 /*!< Invalid channel */ - -/** DMA channel request or trigger source enumeration */ -#define DMA_REQ_SOFT 0 /*!< Software trigger */ -#define DMA_REQ_PERIPHERAL 1 /*!< Peripheral trigger */ - -/** DMA descriptor (DMA channel registers) */ -typedef struct { - uint32_t DMACTRLx; /*!< DMA channel control register */ - uint32_t DMASARx; /*!< DMA channel end source address register */ - uint32_t DMADARx; /*!< DMA channel end destination address register */ - uint32_t DMALLPx; /*!< DMA channel link-list pointer (for chaining/linking separate DMA transfers only) */ -} DMA_DESC_T; - -/** DMA Channel transfer structure */ -typedef struct { - int32_t channel; /*!< Channel ID binded to this transfer */ - int16_t priority; /*!< Transfer priority */ - int16_t int_en; /*!< Interrupt enable status */ - uint32_t source; /*!< DMA request or trigger source for this transfer */ - DMA_DESC_T *desc; /*!< DMA transfer descriptor for this transfer */ - volatile uint32_t status; /*!< DMA transfer status of this transfer */ - DMA_CALLBACK_T callback; /*!< DMA transfer callback */ -} DMA_CHANNEL_T; - -/** DMA channel control bit field enumeration - DMA Operation (OP) */ -#define DMA_INVALID_TRANSFER 0 /*!< Invalid channel */ -#define DMA_SINGLE_TRANSFER 1 /*!< Single Block */ -#define DMA_AUTO_LINKED_TRANSFER 2 /*!< Link-List (Auto-Request) */ -#define DMA_MANUAL_LINKED_TRANSFER 3 /*!< Link-List (Manual-Request) */ - -/** DMA channel control bit field enumeration - Request Type (RT) */ -#define DMA_AUTO_REQUEST 0 /*!< Auto-request following channel arbitration */ -#define DMA_MANUAL_REQUEST 1 /*!< Manual-request following channel arbitration */ - -/** DMA channel control bit field enumeration - Data Transfer Type (DTT) */ - -#define DMA_MEM2MEM 0 /*!< Memory to Memory */ -#define DMA_MEM2AUX 1 /*!< Memory to Auxiliary */ -#define DMA_AUX2MEM 2 /*!< Auxiliary to Memory */ -#define DMA_AUX2AUX 3 /*!< Auxiliary to Auxiliary */ - -/** DMA channel control bit field enumeration - Data Width/Increment (DW/INC) */ - -#define DMA_DW1INC1 0 /*!< dw=byte, inc=byte */ -#define DMA_DW1INC2 1 /*!< dw=byte, inc=half-word */ -#define DMA_DW1INC4 2 /*!< dw=byte, inc=word */ -#define DMA_DW2INC2 3 /*!< dw=half-word, inc=half-word */ -#define DMA_DW2INC4 4 /*!< dw=half-word, inc=word */ -#define DMA_DW4INC4 5 /*!< dw=word, inc=word */ -#define DMA_DWINC_CLR 6 /*!< clear mode (dw=word, inc=word) */ -#define DMA_DW8INC8 7 /*!< dw=double-word, inc=double-word(Only supported in HS) */ - -/** DMA channel control bit field enumeration - Internal/External Interrupt enable (INT) */ - -#define DMA_INT_DISABLE 0 /*!< Interrupt disabled, no interrupt raised is on completion of a data transfer */ -#define DMA_INT_ENABLE 1 /*!< Interrupt enabled, a level interrupt raised on completion of a data transfer */ - -/** DMA channel control bit field enumeration - Address update Mode (AM) */ - -#define DMA_AM_SRCNOT_DSTNOT 0 /*!< No Source or Destination Address increment */ -#define DMA_AM_SRCINC_DSTNOT 1 /*!< Source Address incremented, Destination Address not incremented */ -#define DMA_AM_SRCNOT_DSTINC 2 /*!< Source Address not incremented, Destination Address incremented */ -#define DMA_AM_SRCINC_DSTINC 3 /*!< Source Address and Destination Address incremented */ - -/** DMA channel priority enumeration */ - -#define DMA_CHN_NORM_PRIO 0 /*!< Normal priority */ -#define DMA_CHN_HIGH_PRIO 1 /*!< High priority */ - -/** Number of Memory based DMA Channel */ -#define DMA_MEMORY_CHANNEL_NUM ((DMA_ALL_CHANNEL_NUM) -(DMA_REGISTER_CHANNEL_NUM)) - -#if CORE_DMAC_INTERNAL_VERSION == 1 -#if DMA_MEMORY_CHANNEL_NUM > 0 -/** Memory based DMA channels existed */ -#define DMA_MEMORY_HEADER -#endif -#endif - -/** Check whether channel have register interface */ -#define DMA_CHECK_REGISTER(channel) (channel >= (DMA_MEMORY_CHANNEL_NUM)) - -/** DMA state to maintain uDMA resources */ -typedef struct { -#ifdef DMA_MEMORY_HEADER - /*!< Memory based DMA descriptors */ - EMBARC_ALIGNED(256) volatile DMA_DESC_T mem_dma_descs[DMA_MEMORY_CHANNEL_NUM]; -#endif -#if CORE_DMAC_INTERNAL_VERSION > 1 - EMBARC_ALIGNED(32) volatile uint32_t mem_dma_ptrs[DMA_ALL_CHANNEL_NUM]; -#endif - /*!< All uDMA channel resources */ - volatile DMA_CHANNEL_T *dma_chns[DMA_ALL_CHANNEL_NUM]; -} DMA_STATE_T; - -/** Set DMA_CTRL_T structure ctrl bit field - OP - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_OP(ctrl, val) (ctrl)->bits.op = val; -/** Set DMA_CTRL_T structure ctrl bit field - RT - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_RT(ctrl, val) (ctrl)->bits.rt = val; -/** Set DMA_CTRL_T structure ctrl bit field - DTT - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_DTT(ctrl, val) (ctrl)->bits.dtt = val; -/** Set DMA_CTRL_T structure ctrl bit field - DW/INC - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_DWINC(ctrl, val) (ctrl)->bits.dwinc = val; -/** Calculate right size - * - * @param x transfer size - * @retval (x-1) value after calculation - */ -#define DMA_CTRL_BLKSZ(x) (x - 1) -/** Set DMA_CTRL_T structure ctrl bit field - BLOCKSIZE - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_BLKSZ(ctrl, val) (ctrl)->bits.blksz = val; -/** Set DMA_CTRL_T structure ctrl bit field - ARB - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_ARB(ctrl, val) (ctrl)->bits.arb = val; -/** Set DMA_CTRL_T structure ctrl bit field - I - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_INT(ctrl, val) (ctrl)->bits.intm = val; -/** Set DMA_CTRL_T structure ctrl bit field - AM - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_AM(ctrl, val) (ctrl)->bits.am = val; - -/** Set DMA_CTRL_T structure ctrl value - * - * @param ctrl This should be DMA_CTRL_T structure, and not NULL - * @param val Target value - */ -#define DMA_CTRL_SET_VALUE(ctrl, val) (ctrl)->value = val; - -extern int32_t dmac_init(DMA_STATE_T *state); -extern void dmac_close(void); -extern int32_t dmac_config_desc(DMA_DESC_T *desc, void *src, void *dst, uint32_t size, DMA_CTRL_T *ctrl); -extern int32_t dmac_desc_add_linked(DMA_DESC_T *head, DMA_DESC_T *next); -extern int32_t dmac_init_channel(DMA_CHANNEL_T *dma_chn); -extern int32_t dmac_config_channel(DMA_CHANNEL_T *dma_chn, DMA_DESC_T *desc); -extern int32_t dmac_reserve_channel(int32_t channel, DMA_CHANNEL_T *dma_chn, uint32_t source); -extern int32_t dmac_start_channel(DMA_CHANNEL_T *dma_chn, DMA_CALLBACK_T callback, uint32_t priority); -extern int32_t dmac_stop_channel(DMA_CHANNEL_T *dma_chn); -extern int32_t dmac_release_channel(DMA_CHANNEL_T *dma_chn); -extern int32_t dmac_wait_channel(DMA_CHANNEL_T *dma_chn); -extern int32_t dmac_check_channel(DMA_CHANNEL_T *dma_chn); -extern int32_t dmac_clear_channel(DMA_CHANNEL_T *dma_chn); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_UDMA */ -/** @}*/ diff --git a/platform/vendor_bsp/embarc_bsp/include/arc/arc_xy_agu.h b/platform/vendor_bsp/embarc_bsp/include/arc/arc_xy_agu.h deleted file mode 100644 index 48774451..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/arc/arc_xy_agu.h +++ /dev/null @@ -1,308 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_ARC_XY_AGU -#define H_ARC_XY_AGU - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#define U0 % r32 -#define U1 % r33 -#define U2 % r34 - -#ifdef ARC_FEATURE_XCCM_PRESENT -#define ARC_X_CCM __attribute__ ((section(".x_ccm"))) -#else -#define ARC_X_CCM -#endif - -#ifdef ARC_FEATURE_YCCM_PRESENT -#define ARC_Y_CCM __attribute__ ((section(".y_ccm"))) -#else -#define ARC_Y_CCM -#endif - -#define US_EXPAND_MOD_NAME(reg_id) AUX_AGU_MOD ## reg_id -#define US_EXPAND_OS_NAME(reg_id) AUX_AGU_OS ## reg_id -#define US_EXPAND_AP_NAME(reg_id) AUX_AGU_AP ## reg_id - -#define ARC_AGU_MOD_SET(agu_mod, ptr_id, data_type, addressing) \ - arc_aux_write(US_EXPAND_MOD_NAME(agu_mod), (uint32_t)(ptr_id | data_type | addressing)) -#define ARC_AGU_OS_SET(os_id, offset) \ - arc_aux_write(US_EXPAND_OS_NAME(os_id), (uint32_t)offset) -#define ARC_AGU_AP_SET(ap_id, addr) \ - arc_aux_write(US_EXPAND_AP_NAME(ap_id), (uint32_t)addr) -#define ARC_AGU_MOD_GET(mod_id) arc_aux_read(US_EXPAND_MOD_NAME(mod_id)) -#define ARC_AGU_OS_GET(os_id) arc_aux_read(US_EXPAND_MOD_NAME(os_id)) -#define ARC_AGU_AP_GET(ap_id) arc_aux_read(US_EXPAND_AP_NAME(ap_id)) - -#define ARC_AGU_MOD_VW(x) ((x) << 4) -#define ARC_AGU_MOD_FX(x) ((x) << 6) -#define ARC_AGU_MOD_DIR(x) ((x) << 11) -#define ARC_AGU_MOD_REV (1 << 12) -#define ARC_AGU_MOD_REP (1 << 13) - -#define ARC_AGU_MOD_SC(x) ((x) << 14) -#define ARC_AGU_MOD_OFFSET_REG(x) ((x) << 25) -#define ARC_AGU_MOD_OFFSET_IMM(x) ((x) << 18) - -#define ARC_AGU_MOD_WRAP_REG(x) ((x) << 14) -#define ARC_AGU_MOD_WRAP_IMM(x) ((x) << 14) - -#define ARC_AGU_MOD_OPC(x) ((x) << 29) - -#define ARC_AGU_DT_I32 (ARC_AGU_MOD_FX(11) | ARC_AGU_MOD_VW(2)) -#define ARC_AGU_DT_I32_CAST_I16 (ARC_AGU_MOD_FX(8) | ARC_AGU_MOD_VW(2)) -#define ARC_AGU_DT_I32_CAST_I8 (ARC_AGU_MOD_FX(4) | ARC_AGU_MOD_VW(2)) - -#define ARC_AGU_DT_I16 (ARC_AGU_MOD_FX(3) | ARC_AGU_MOD_VW(1)) -#define ARC_AGU_DT_I16_CAST_I8 (ARC_AGU_MOD_FX(0) | ARC_AGU_MOD_VW(1)) - -#define ARC_AGU_DT_I8 (ARC_AGU_MOD_FX(7) | ARC_AGU_MOD_VW(0)) - -#define ARC_AGU_DT_V2I16 (ARC_AGU_MOD_FX(3) | ARC_AGU_MOD_VW(2)) -#define ARC_AGU_DT_V2I16_REPLIC_I16 (ARC_AGU_MOD_FX(3) | ARC_AGU_MOD_VW(2) | ARC_AGU_MOD_REP) -#define ARC_AGU_DT_V2I16_CAST_V2I8 (ARC_AGU_MOD_FX(0) | ARC_AGU_MOD_VW(2)) - -#define ARC_AGU_DT_V2I8 (ARC_AGU_MOD_FX(7) | ARC_AGU_MOD_VW(1)) -#define ARC_AGU_DT_V2I8_REPLIC_I8 (ARC_AGU_MOD_FX(7) | ARC_AGU_MOD_VW(1) | ARC_AGU_MOD_REP) - -#define ARC_AGU_DT_V4I8 (ARC_AGU_MOD_FX(7) | ARC_AGU_MOD_VW(2)) -#define ARC_AGU_DT_V4I8_REPLIC_I8 (ARC_AGU_MOD_FX(7) | ARC_AGU_MOD_VW(2) | ARC_AGU_MOD_REP) - -/* AGU addressing modes with scling factor macroses */ - -#define ARC_AGU_AD_INC_I32(offset) (ARC_AGU_MOD_OPC(1) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(2)) -#define ARC_AGU_AD_DEC_I32(offset) (ARC_AGU_MOD_OPC(1) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(2) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_INC_I32_REG(reg_id) (ARC_AGU_MOD_OPC(0) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(2)) -#define ARC_AGU_AD_DEC_I32_REG(reg_id) (ARC_AGU_MOD_OPC(0) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(2) | ARC_AGU_MOD_DIR(1)) - -#define ARC_AGU_AD_BITREV_INC_I32(offset) (ARC_AGU_MOD_OPC(3) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(2)) -#define ARC_AGU_AD_BITREV_DEC_I32(offset) (ARC_AGU_MOD_OPC(3) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(2) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_BITREV_INC_I32_REG(reg_id) (ARC_AGU_MOD_OPC(2) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(2)) -#define ARC_AGU_AD_BITREV_DEC_I32_REG(reg_id) (ARC_AGU_MOD_OPC(2) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(2) | ARC_AGU_MOD_DIR(1)) - -#define ARC_AGU_AD_INC_I16(offset) (ARC_AGU_MOD_OPC(1) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(1)) -#define ARC_AGU_AD_DEC_I16(offset) (ARC_AGU_MOD_OPC(1) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(1) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_INC_I16_REG(reg_id) (ARC_AGU_MOD_OPC(0) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(1)) -#define ARC_AGU_AD_DEC_I16_REG(reg_id) (ARC_AGU_MOD_OPC(0) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(1) | ARC_AGU_MOD_DIR(1)) - -#define ARC_AGU_AD_BITREV_INC_I16(offset) (ARC_AGU_MOD_OPC(3) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(1)) -#define ARC_AGU_AD_BITREV_DEC_I16(offset) (ARC_AGU_MOD_OPC(3) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(1) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_BITREV_INC_I16_REG(reg_id) (ARC_AGU_MOD_OPC(2) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(1)) -#define ARC_AGU_AD_BITREV_DEC_I16_REG(reg_id) (ARC_AGU_MOD_OPC(2) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(1) | ARC_AGU_MOD_DIR(1)) - -#define ARC_AGU_AD_INC_I8(offset) (ARC_AGU_MOD_OPC(1) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(0)) -#define ARC_AGU_AD_DEC_I8(offset) (ARC_AGU_MOD_OPC(1) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(0) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_INC_I8_REG(reg_id) (ARC_AGU_MOD_OPC(0) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(0)) -#define ARC_AGU_AD_DEC_I8_REG(reg_id) (ARC_AGU_MOD_OPC(0) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(0) | ARC_AGU_MOD_DIR(1)) - -#define ARC_AGU_AD_BITREV_INC_I8(offset) (ARC_AGU_MOD_OPC(3) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(0)) -#define ARC_AGU_AD_BITREV_DEC_I8(offset) (ARC_AGU_MOD_OPC(3) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_SC(0) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_BITREV_INC_I8_REG(reg_id) (ARC_AGU_MOD_OPC(2) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(0)) -#define ARC_AGU_AD_BITREV_DEC_I8_REG(reg_id) (ARC_AGU_MOD_OPC(2) | ARC_AGU_MOD_OFFSET_REG(reg_id) | ARC_AGU_MOD_SC(0) | ARC_AGU_MOD_DIR(1)) - -/****************************************************************************** -* -* AGU data types with type casting macroses for unsigned int data types -* unsigned int data type assumes lsb aligned data conversion without sign extension -* -******************************************************************************/ - -#define ARC_AGU_DT_UI32 ARC_AGU_DT_I32 -#define ARC_AGU_DT_UI32_CAST_UI16 (ARC_AGU_MOD_FX(9) | ARC_AGU_MOD_VW(2)) -#define ARC_AGU_DT_UI32_CAST_UI8 (ARC_AGU_MOD_FX(5) | ARC_AGU_MOD_VW(2)) - -#define ARC_AGU_DT_UI16 ARC_AGU_DT_I16 -#define ARC_AGU_DT_UI16_CAST_UI8 (ARC_AGU_MOD_FX(1) | ARC_AGU_MOD_VW(1)) - -#define ARC_AGU_DT_UI8 ARC_AGU_DT_I8 - -#define ARC_AGU_DT_V2UI16 ARC_AGU_DT_V2I16 -#define ARC_AGU_DT_V2UI16_REPLIC_UI16 ARC_AGU_DT_V2I16_REPLIC_I16 -#define ARC_AGU_DT_V2UI16_CAST_V2UI8 (ARC_AGU_MOD_FX(1) | ARC_AGU_MOD_VW(2)) - -#define ARC_AGU_DT_V2UI8 ARC_AGU_DT_V2I8 -#define ARC_AGU_DT_V2UI8_REPLIC_UI8 ARC_AGU_DT_V2I8_REPLIC_I8 - -#define ARC_AGU_DT_V4UI8 ARC_AGU_DT_V4I8 -#define ARC_AGU_DT_V4UI8_REPLIC_UI8 ARC_AGU_DT_V4I8_REPLIC_I8 - -/* AGU addressing modes with scling factor macroses */ - -#define ARC_AGU_AD_INC_UI32(offset) ARC_AGU_AD_INC_I32(offset) -#define ARC_AGU_AD_DEC_UI32(offset) ARC_AGU_AD_DEC_I32(offset) -#define ARC_AGU_AD_INC_UI32_REG(reg_id) ARC_AGU_AD_INC_I32_REG(reg_id) -#define ARC_AGU_AD_DEC_UI32_REG(reg_id) ARC_AGU_AD_DEC_I32_REG(reg_id) - -#define ARC_AGU_AD_BITREV_INC_UI32(offset) ARC_AGU_AD_BITREV_INC_I32(offset) -#define ARC_AGU_AD_BITREV_DEC_UI32(offset) ARC_AGU_AD_BITREV_DEC_I32(offset) -#define ARC_AGU_AD_BITREV_INC_UI32_REG(reg_id) ARC_AGU_AD_BITREV_INC_I32_REG(reg_id) -#define ARC_AGU_AD_BITREV_DEC_UI32_REG(reg_id) ARC_AGU_AD_BITREV_DEC_I32_REG(reg_id) - -#define ARC_AGU_AD_INC_UI16(offset) ARC_AGU_AD_INC_I16(offset) -#define ARC_AGU_AD_DEC_UI16(offset) ARC_AGU_AD_DEC_I16(offset) -#define ARC_AGU_AD_INC_UI16_REG(reg_id) ARC_AGU_AD_INC_I16_REG(reg_id) -#define ARC_AGU_AD_DEC_UI16_REG(reg_id) ARC_AGU_AD_DEC_I16_REG(reg_id) - -#define ARC_AGU_AD_BITREV_INC_UI16(offset) ARC_AGU_AD_BITREV_INC_I16(offset) -#define ARC_AGU_AD_BITREV_DEC_UI16(offset) ARC_AGU_AD_BITREV_DEC_I16(offset) -#define ARC_AGU_AD_BITREV_INC_UI16_REG(reg_id) ARC_AGU_AD_BITREV_INC_I16_REG(reg_id) -#define ARC_AGU_AD_BITREV_DEC_UI16_REG(reg_id) ARC_AGU_AD_BITREV_DEC_I16_REG(reg_id) - -#define ARC_AGU_AD_INC_UI8(offset) ARC_AGU_AD_INC_I8(offset) -#define ARC_AGU_AD_DEC_UI8(offset) ARC_AGU_AD_DEC_I8(offset) -#define ARC_AGU_AD_INC_UI8_REG(reg_id) ARC_AGU_AD_INC_I8_REG(reg_id) -#define ARC_AGU_AD_DEC_UI8_REG(reg_id) ARC_AGU_AD_DEC_I8_REG(reg_id) - -#define ARC_AGU_AD_BITREV_INC_UI8(offset) ARC_AGU_AD_BITREV_INC_I8(offset) -#define ARC_AGU_AD_BITREV_DEC_UI8(offset) ARC_AGU_AD_BITREV_DEC_I8(offset) -#define ARC_AGU_AD_BITREV_INC_UI8_REG(reg_id) ARC_AGU_AD_BITREV_INC_I8_REG(reg_id) -#define ARC_AGU_AD_BITREV_DEC_UI8_REG(reg_id) ARC_AGU_AD_BITREV_DEC_I8_REG(reg_id) - -/****************************************************************************** -* -* AGU data types with type casting macroses for q.xx data types -* q.xx data type assumes msb aligned data conversion -* -******************************************************************************/ - -#define ARC_AGU_DT_Q31 ARC_AGU_DT_I32 -#define ARC_AGU_DT_Q31_CAST_Q15 (ARC_AGU_MOD_FX(10) | ARC_AGU_MOD_VW(2)) -#define ARC_AGU_DT_Q31_CAST_Q7 (ARC_AGU_MOD_FX(6) | ARC_AGU_MOD_VW(2)) - -#define ARC_AGU_DT_Q15 ARC_AGU_DT_I16 -#define ARC_AGU_DT_Q15_CAST_Q7 (ARC_AGU_MOD_FX(2) | ARC_AGU_MOD_VW(1)) - -#define ARC_AGU_DT_Q7 ARC_AGU_DT_I8 -#define ARC_AGU_DT_Q7_CAST_Q15 (ARC_AGU_MOD_FX(2) | ARC_AGU_MOD_VW(1)) // packing - -#define ARC_AGU_DT_V2Q15 ARC_AGU_DT_V2I16 -#define ARC_AGU_DT_V2Q15_REPLIC_Q15 ARC_AGU_DT_V2I16_REPLIC_I16 -#define ARC_AGU_DT_V2Q15_CAST_V2Q7 (ARC_AGU_MOD_FX(2) | ARC_AGU_MOD_VW(2)) - -#define ARC_AGU_DT_V2Q7 ARC_AGU_DT_V2I8 -#define ARC_AGU_DT_V2Q7_REPLIC_Q7 ARC_AGU_DT_V2I8_REPLIC_I8 -#define ARC_AGU_DT_V2Q7_CAST_V2Q15 (ARC_AGU_MOD_FX(2) | ARC_AGU_MOD_VW(2)) // packing - -#define ARC_AGU_DT_V4Q7 ARC_AGU_DT_V4I8 -#define ARC_AGU_DT_V4Q7_REPLIC_Q7 ARC_AGU_DT_V4I8_REPLIC_I8 - -/* AGU addressing modes with scling factor macroses for q.xx data types */ - -#define ARC_AGU_AD_INC_Q31(offset) ARC_AGU_AD_INC_I32(offset) -#define ARC_AGU_AD_DEC_Q31(offset) ARC_AGU_AD_DEC_I32(offset) -#define ARC_AGU_AD_INC_Q31_REG(reg_id) ARC_AGU_AD_INC_I32_REG(reg_id) -#define ARC_AGU_AD_DEC_Q31_REG(reg_id) ARC_AGU_AD_DEC_I32_REG(reg_id) - -#define ARC_AGU_AD_BITREV_INC_Q31(offset) ARC_AGU_AD_BITREV_INC_I32(offset) -#define ARC_AGU_AD_BITREV_DEC_Q31(offset) ARC_AGU_AD_BITREV_DEC_I32(offset) -#define ARC_AGU_AD_BITREV_INC_Q31_REG(reg_id) ARC_AGU_AD_BITREV_INC_I32_REG(reg_id) -#define ARC_AGU_AD_BITREV_DEC_Q31_REG(reg_id) ARC_AGU_AD_BITREV_DEC_I32_REG(reg_id) - -#define ARC_AGU_AD_INC_Q15(offset) ARC_AGU_AD_INC_I16(offset) -#define ARC_AGU_AD_DEC_Q15(offset) ARC_AGU_AD_DEC_I16(offset) -#define ARC_AGU_AD_INC_Q15_REG(reg_id) ARC_AGU_AD_INC_I16_REG(reg_id) -#define ARC_AGU_AD_DEC_Q15_REG(reg_id) ARC_AGU_AD_DEC_I16_REG(reg_id) - -#define ARC_AGU_AD_BITREV_INC_Q15(offset) ARC_AGU_AD_BITREV_INC_I16(offset) -#define ARC_AGU_AD_BITREV_DEC_Q15(offset) ARC_AGU_AD_BITREV_DEC_I16(offset) -#define ARC_AGU_AD_BITREV_INC_Q15_REG(reg_id) ARC_AGU_AD_BITREV_INC_I16_REG(reg_id) -#define ARC_AGU_AD_BITREV_DEC_Q15_REG(reg_id) ARC_AGU_AD_BITREV_DEC_I16_REG(reg_id) - -#define ARC_AGU_AD_INC_Q7(offset) ARC_AGU_AD_INC_I8(offset) -#define ARC_AGU_AD_DEC_Q7(offset) ARC_AGU_AD_DEC_I8(offset) -#define ARC_AGU_AD_INC_Q7_REG(reg_id) ARC_AGU_AD_INC_I8_REG(reg_id) -#define ARC_AGU_AD_DEC_Q7_REG(reg_id) ARC_AGU_AD_DEC_I8_REG(reg_id) - -#define ARC_AGU_AD_BITREV_INC_Q7(offset) ARC_AGU_AD_BITREV_INC_I8(offset) -#define ARC_AGU_AD_BITREV_DEC_Q7(offset) ARC_AGU_AD_BITREV_DEC_I8(offset) -#define ARC_AGU_AD_BITREV_INC_Q7_REG(reg_id) ARC_AGU_AD_BITREV_INC_I8_REG(reg_id) -#define ARC_AGU_AD_BITREV_DEC_Q7_REG(reg_id) ARC_AGU_AD_BITREV_DEC_I8_REG(reg_id) - -/* AGU modificator for reverse vector elements (can be useful for Endian conversions) */ - -#define ARC_AGU_DT_VECTOR_REVERSE ARC_AGU_MOD_REV - -/* AGU wrapping modifiers */ - -#define ARC_AGU_AD_WRAP_INC_RR(inc_os_id, modulo_os_id) (ARC_AGU_MOD_OPC(4) | ARC_AGU_MOD_OFFSET_REG(inc_os_id) | ARC_AGU_MOD_WRAP_REG(modulo_os_id)) -#define ARC_AGU_AD_WRAP_DEC_RR(dec_os_id, modulo_os_id) (ARC_AGU_MOD_OPC(4) | ARC_AGU_MOD_OFFSET_REG(dec_os_id) | ARC_AGU_MOD_WRAP_REG(modulo_os_id) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_WRAP_INC_II(offset, modulo) (ARC_AGU_MOD_OPC(5) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_WRAP_IMM(modulo)) -#define ARC_AGU_AD_WRAP_DEC_II(offset, modulo) (ARC_AGU_MOD_OPC(5) | ARC_AGU_MOD_OFFSET_IMM(offset) | ARC_AGU_MOD_WRAP_IMM(modulo) | ARC_AGU_MOD_DIR(1)) -#define ARC_AGU_AD_WRAP_INC_RI(dec_os_id, modulo) (ARC_AGU_MOD_OPC(6) | ARC_AGU_MOD_OFFSET_REG(dec_os_id) | ARC_AGU_MOD_WRAP_IMM(modulo)) -#define ARC_AGU_AD_WRAP_DEC_RI(dec_os_id, modulo) (ARC_AGU_MOD_OPC(6) | ARC_AGU_MOD_OFFSET_REG(dec_os_id) | ARC_AGU_MOD_WRAP_IMM(modulo) | ARC_AGU_MOD_DIR(1)) - -/* Immediate Wrapping constants */ - -#define AGU_WRAP_IMM_2 0 -#define AGU_WRAP_IMM_4 1 -#define AGU_WRAP_IMM_8 2 -#define AGU_WRAP_IMM_16 3 -#define AGU_WRAP_IMM_32 4 -#define AGU_WRAP_IMM_64 5 -#define AGU_WRAP_IMM_128 6 -#define AGU_WRAP_IMM_256 7 -#define AGU_WRAP_IMM_512 8 -#define AGU_WRAP_IMM_1024 9 -#define AGU_WRAP_IMM_2048 10 -#define AGU_WRAP_IMM_4096 11 -#define AGU_WRAP_IMM_8192 12 -#define AGU_WRAP_IMM_16384 13 -#define AGU_WRAP_IMM_32768 14 -#define AGU_WRAP_IMM_65536 15 - -/* push pop macros to follow calling conventions */ - -#define ARC_AGU_STORE_REGS(ap_num, mod_num, os_num) \ - int32_t agu_temp_idx; \ - uint32_t agu_temp_ap[ap_num]; \ - uint32_t agu_temp_mod[mod_num]; \ - uint32_t agu_temp_os[os_num]; \ - int32_t agu_temp_ap_num = ap_num; \ - int32_t agu_temp_mod_num = mod_num; \ - int32_t agu_temp_os_num = os_num; \ - for (agu_temp_idx = 0; agu_temp_idx < ap_num; agu_temp_idx++) agu_temp_ap[agu_temp_idx] = _lr(AGU_AUX_AP0 + agu_temp_idx); \ - for (agu_temp_idx = 0; agu_temp_idx < mod_num; agu_temp_idx++) agu_temp_mod[agu_temp_idx] = _lr(AGU_AUX_MOD0 + agu_temp_idx); \ - for (agu_temp_idx = 0; agu_temp_idx < os_num; agu_temp_idx++) agu_temp_os[agu_temp_idx] = _lr(AGU_AUX_OS0 + agu_temp_idx); {} - -#define ARC_AGU_RESTORE_REGS() \ - for (agu_temp_idx = 0; agu_temp_idx < agu_temp_ap_num; agu_temp_idx++) _sr (agu_temp_ap[agu_temp_idx], AGU_AUX_AP0 + agu_temp_idx); \ - for (agu_temp_idx = 0; agu_temp_idx < agu_temp_mod_num; agu_temp_idx++) _sr (agu_temp_mod[agu_temp_idx], AGU_AUX_MOD0 + agu_temp_idx); \ - for (agu_temp_idx = 0; agu_temp_idx < agu_temp_os_num; agu_temp_idx++) _sr (agu_temp_os[agu_temp_idx], AGU_AUX_OS0 + agu_temp_idx); {} - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_ARC_XY_AGU */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_gpio.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_gpio.h deleted file mode 100644 index 29599061..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_gpio.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_GPIO -#define H_DW_GPIO - -#include "device/ip_hal/dev_gpio.h" -#include "arc/arc_exception.h" - -#define DW_GPIO_PORT_A (0) -#define DW_GPIO_PORT_B (1) -#define DW_GPIO_PORT_C (2) -#define DW_GPIO_PORT_D (3) - -#define DW_GPIO_INT_ACT_LOW GPIO_INT_ACTIVE_LOW -#define DW_GPIO_INT_ACT_HIGH GPIO_INT_ACTIVE_HIGH - -#define DW_GPIO_INT_LEVEL_TRIG GPIO_INT_LEVEL_TRIG -#define DW_GPIO_INT_EDGE_TRIG GPIO_INT_EDGE_TRIG - -#define DW_GPIO_INT_NO_DEBOUNCE GPIO_INT_NO_DEBOUNCE -#define DW_GPIO_INT_DEBOUNCE GPIO_INT_DEBOUNCE - -#define DW_GPIO_ALL_ZERO (0x0) -#define DW_GPIO_ALL_ONE (0xffffffff) -#define DW_GPIO_MASK_ALL (0xffffffff) -#define DW_GPIO_INPUT_ALL (0x0) -#define DW_GPIO_OUTPUT_ALL (0xffffffff) - -#define DW_GPIO_INVALID_INTNO (DEV_INTNO_INVALID) - -/** - * @name DesignWare GPIO Register Structure - * @brief DesignWare GPIO register structure for gpio port - * @{ - */ -typedef struct { - uint32_t DR; - uint32_t DDR; - uint32_t CTRL; -} PORT_CTRL; - -/* DW GPIO PORTS Registers */ -typedef volatile struct { - PORT_CTRL SWPORTS[4]; - uint32_t INTEN; /*!< (0x30) */ - uint32_t INTMASK; /*!< (0x34) */ - uint32_t INTTYPE_LEVEL; /*!< (0x38) */ - uint32_t INT_POLARITY; /*!< (0x3c) */ - uint32_t INTSTATUS; /*!< (0x40) */ - uint32_t RAW_INTSTATUS; /*!< (0x44) */ - uint32_t DEBOUNCE; /*!< (0x48) */ - uint32_t PORTA_EOI; /*!< (0x4c) */ - uint32_t EXT_PORTS[4]; /*!< (0x50) -A - (0x54) -B - (0x58) -C - (0x5c) -D */ - uint32_t LS_SYNC; /*!< (0x60) */ - uint32_t ID_CODE; /*!< (0x64) */ - uint32_t RESERVED_3; /*!< (0x68) */ - uint32_t VER_ID_CODE; /*!< (0x6c) */ - uint32_t CONFIG_REG2; /*!< (0x70) */ - uint32_t CONFIG_REG1; /*!< (0x74) */ -} DW_GPIO_REG, *DW_GPIO_REG_PTR; -/** @} */ - -/** interrupt handler for each port bit */ -typedef struct { - uint32_t int_bit_max_cnt; /*!< max bit count for each port */ - DEV_GPIO_HANDLER *int_bit_handler_ptr; /*!< interrupt handler pointer */ -} DW_GPIO_BIT_ISR, *DW_GPIO_BIT_ISR_PTR; - -/** - * @brief DesignWare GPIO control structure - * @details Structure type for gpio implementation - */ -typedef struct { - uint32_t no; /*!< gpio port number */ - DW_GPIO_REG_PTR regs; /*!< gpio port register */ - uint32_t intno; /*!< gpio interrupt vector number */ - uint32_t valid_bit_mask; /*!< valid bit mask of gpio port */ - INT_HANDLER_T int_handler; /*!< gpio interrupt handler */ - DW_GPIO_BIT_ISR_PTR gpio_bit_isr; /*!< gpio bit handler struct */ -} DW_GPIO_PORT, *DW_GPIO_PORT_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name DesignWare GPIO Function Declaration - * @brief Contains declarations of designware gpio functions - * @details These are only used in gpio object implementation source file - * @{ - */ -extern int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir); -extern int32_t dw_gpio_close(DEV_GPIO *gpio_obj); -extern int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask); -extern int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask); -extern int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* H_DW_GPIO */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s.h deleted file mode 100644 index 7002e8d5..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s.h +++ /dev/null @@ -1,345 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_I2S -#define H_DW_I2S - -#include "device/ip_hal/dev_i2s.h" -#include "stdio.h" -/* embARC HAL */ -#include "embARC.h" -#include "embARC_debug.h" - -/** - * If this header file is included, will indicate that this designware I2S device is used. - * - * sclk - serial clock - * ws - word select - * sd - serial data - * Transmitter - device that places data on the sd line and is clocked by sclk and ws - * Receiver - device that receives data from the sd line and is clocked by sclk and ws - * Master - when configured as a master, DW_apb_i2s initializes the ws signal and supplies the - * clock gating and clock enabling signals - * Slave - when configured as a slave, DW_apb_i2s responds to externally generated sclk and - * ws signals - */ -#define DEVICE_USE_DESIGNWARE_I2S - -/** - * @defgroup DEVICE_DW_I2S_INFO DesignWare I2S Related Information - * @ingroup DEVICE_DW_I2S - * @brief Types and macro definitions for designware i2s - * @{ - */ -#define DW_I2S_MASTER_SUPPORTED (0x1) /*!< Support Designware I2S Master Mode */ -#define DW_I2S_SLAVE_SUPPORTED (0x2) /*!< Support Designware I2S Slave Mode */ - -#define DW_I2S_CHANNEL0_SUPPORTED (0x1) /*!< Support Designware I2S TX/RX Channel 0 */ -#define DW_I2S_CHANNEL1_SUPPORTED (0x2) /*!< Support Designware I2S TX/RX Channel 1 */ -#define DW_I2S_CHANNEL2_SUPPORTED (0x4) /*!< Support Designware I2S TX/RX Channel 2 */ -#define DW_I2S_CHANNEL3_SUPPORTED (0x8) /*!< Support Designware I2S TX/RX Channel 3 */ - -#define DW_I2S_DATA_LENGTH_16 (1) /*!< Set the length of data 16 bits else 32 bits>*/ - -/*!< I2S TX/RX channel */ -typedef enum { - DW_I2S_CHANNEL0 = 0, /*!< I2S TX/RX channel 0 */ - DW_I2S_CHANNEL1 = 1, /*!< I2S TX/RX channel 1 */ - DW_I2S_CHANNEL2 = 2, /*!< I2S TX/RX channel 2 */ - DW_I2S_CHANNEL3 = 3 /*!< I2S TX/RX channel 3 */ -} DW_I2S_CHANNEL; - -/*!< I2S word select line (ws_out) stays in the left or right sample mode */ -typedef enum { - DW_I2S_WSS_16_CLK = 0, /*!< 16 clock cycles */ - DW_I2S_WSS_24_CLK = 1, /*!< 24 clock cycles */ - DW_I2S_WSS_32_CLK = 2 /*!< 32 clock cycles */ -} DW_I2S_WSS; - -/*!< I2S gating of sclk */ -typedef enum { - DW_I2S_SCLKG_NO = 0, /*!< No clock gating */ - DW_I2S_SCLKG_12_CLK = 1, /*!< Gate after 12 clock cycles */ - DW_I2S_SCLKG_16_CLK = 2, /*!< Gate after 16 clock cycles */ - DW_I2S_SCLKG_20_CLK = 3, /*!< Gate after 20 clock cycles */ - DW_I2S_SCLKG_24_CLK = 4 /*!< Gate after 24 clock cycles */ -} DW_I2S_SCLKG; - -#define DW_I2S_GINT_DISABLED (0) /*!< DesignWare interrupt disabled for control I2S irq/fiq */ -#define DW_I2S_GINT_ENABLE (1 << 0) /*!< DesignWare interrupt enabled for control I2S irq/fiq */ -#define DW_I2S_TXINT_ENABLE (1 << 1) /*!< DesignWare interrupt enabled for control transmit process */ -#define DW_I2S_RXINT_ENABLE (1 << 2) /*!< DesignWare interrupt enabled for control transmit process */ - -/** @} */ - -/** - * @defgroup DEVICE_DW_I2S_REGSTRUCT DesignWare I2S Register Structure - * @ingroup DEVICE_DW_I2S - * @brief Structure definitions for register - * @details Description of DesignWare I2S register information - * @{ - */ -/** - * @brief DesignWare I2S receiver register structure - * @details Detailed struct description of DesignWare I2S receiver - */ -typedef volatile struct { - uint32_t IER; /*!< (0x000) : Enable Register */ - uint32_t IRER; /*!< (0x004) : I2S Receiver Block Enable Register */ - uint32_t ITER; /*!< (0X008) : I2S Transmitter Block Enable Register*/ - uint32_t CER; /*!< (0x00C) : Clock Enable Register */ - uint32_t CCR; /*!< (0x010) : Clock Configuration Register */ - uint32_t RXFFR; /*!< (0x014) : Receiver Block FIFO Register */ - uint32_t TXFFR; /*!< (0x018) : Transmitter Block FIFO Register */ - uint32_t RESERVED0; /*!< (0x01C) : Reserved */ - uint32_t LRBR0; /*!< (0x020) : Left Receive Buffer 0 */ - uint32_t RRBR0; /*!< (0x024) : Right Receive Buffer 0 */ - uint32_t RER0; /*!< (0x028) : Receive Enable Register 0 */ - uint32_t TER0; /*!< (0x02C) : Transmit Enable Register 0 */ - uint32_t RCR0; /*!< (0x030) : Receive Configuration Register 0 */ - uint32_t TCR0; /*!< (0x034) : Transmit Configuration Register 0 */ - uint32_t ISR0; /*!< (0x038) : Interrupt Status Register 0 */ - uint32_t IMR0; /*!< (0x03C) : Interrupt Mask Register 0 */ - uint32_t ROR0; /*!< (0x040) : Receive Overrun Register 0 */ - uint32_t TOR0; /*!< (0x044) : Transmit Overrun Register 0 */ - uint32_t RFCR0; /*!< (0x048) : Receive FIFO Configuration Register 0 */ - uint32_t TFCR0; /*!< (0x04C) : Transmit FIFO Configuration Register 0 */ - uint32_t RFF0; /*!< (0x050) : Receive FIFO Flush 0 */ - uint32_t TFF0; /*!< (0x054) : Transmit FIFO Flush 0 */ - uint32_t RESERVED1[2]; /*!< (0x058) : Reserved */ - uint32_t LRBR1; /*!< (0x060) : Left Receive Buffer 1 */ - uint32_t RRBR1; /*!< (0x064) : Right Receive Buffer 1 */ - uint32_t RER1; /*!< (0x068) : Receive Enable Register 1 */ - uint32_t TER1; /*!< (0x06C) : Transmit Enable Register 1 */ - uint32_t RCR1; /*!< (0x070) : Receive Configuration Register 1 */ - uint32_t TCR1; /*!< (0x074) : Transmit Configuration Register 1 */ - uint32_t ISR1; /*!< (0x078) : Interrupt Status Register 1 */ - uint32_t IMR1; /*!< (0x07C) : Interrupt Mask Register 1 */ - uint32_t ROR1; /*!< (0x080) : Receive Overrun Register 1 */ - uint32_t TOR1; /*!< (0x084) : Transmit Overrun Register 1 */ - uint32_t RFCR1; /*!< (0x088) : Receive FIFO Configuration Register 1 */ - uint32_t TFCR1; /*!< (0x08C) : Transmit FIFO Configuration Register 1 */ - uint32_t RFF1; /*!< (0x090) : Receive FIFO Flush 1 */ - uint32_t TFF1; /*!< (0x094) : Transmit FIFO Flush 1 */ - uint32_t RESERVED2[2]; /*!< (0x098) : Reserved */ - uint32_t LRBR2; /*!< (0x0A0) : Left Receive Buffer 2 */ - uint32_t RRBR2; /*!< (0x0A4) : Right Receive Buffer 2 */ - uint32_t RER2; /*!< (0x0A8) : Receive Enable Register 2 */ - uint32_t TER2; /*!< (0x0AC) : Transmit Enable Register 2 */ - uint32_t RCR2; /*!< (0x0B0) : Receive Configuration Register 2 */ - uint32_t TCR2; /*!< (0x0B4) : Transmit Configuration Register 2 */ - uint32_t ISR2; /*!< (0x0B8) : Interrupt Status Register 2 */ - uint32_t IMR2; /*!< (0x0BC) : Interrupt Mask Register 2 */ - uint32_t ROR2; /*!< (0x0C0) : Receive Overrun Register 2 */ - uint32_t TOR2; /*!< (0x0C4) : Transmit Overrun Register 2 */ - uint32_t RFCR2; /*!< (0x0C8) : Receive FIFO Configuration Register 2 */ - uint32_t TFCR2; /*!< (0x0CC) : Transmit FIFO Configuration Register 2 */ - uint32_t RFF2; /*!< (0x0D0) : Receive FIFO Flush 2 */ - uint32_t TFF2; /*!< (0x0D4) : Transmit FIFO Flush 2 */ - uint32_t RESERVED3[2]; /*!< (0x0D8) : Reserved */ - uint32_t LRBR3; /*!< (0x0E0) : Left Receive Buffer 3 */ - uint32_t RRBR3; /*!< (0x0E4) : Right Receive Buffer 3 */ - uint32_t RER3; /*!< (0x0E8) : Receive Enable Register 3 */ - uint32_t TER3; /*!< (0x0EC) : Transmit Enable Register 3 */ - uint32_t RCR3; /*!< (0x0F0) : Receive Configuration Register 3 */ - uint32_t TCR3; /*!< (0x0F4) : Transmit Configuration Register 3 */ - uint32_t ISR3; /*!< (0x0F8) : Interrupt Status Register 3 */ - uint32_t IMR3; /*!< (0x0FC) : Interrupt Mask Register 3 */ - uint32_t ROR3; /*!< (0x100) : Receive Overrun Register 3 */ - uint32_t TOR3; /*!< (0x104) : Transmit Overrun Register 3 */ - uint32_t RFCR3; /*!< (0x108) : Receive FIFO Configuration Register 3 */ - uint32_t TFCR3; /*!< (0x10C) : Transmit FIFO Configuration Register 3 */ - uint32_t RFF3; /*!< (0x110) : Receive FIFO Flush 3 */ - uint32_t TFF3; /*!< (0x114) : Transmit FIFO Flush 3 */ - uint32_t RESERVED4[42]; /*!< (0x118) : Reserved */ - uint32_t RXDMA; /*!< (0x1C0) : Receiver Block DMA Register */ - uint32_t RRXDMA; /*!< (0x1C4) : Reset Receiver Block DMA Register */ - uint32_t TXDMA; /*!< (0x1C8) : Transmitter Block DMA Register */ - uint32_t RTXDMA; /*!< (0x1CC) : Reset Transmitter Block DMA Register */ - uint32_t RESERVED5[8]; /*!< (0x1D0) : Reserved */ - uint32_t I2S_COMP_PARAM_2; /*!< (0x1F0) : Component Parameter 2 Register */ - uint32_t I2S_COMP_PARAM_1; /*!< (0x1F4) : Component Parameter 1 Register */ - uint32_t I2S_COMP_VERSION; /*!< (0x1F8) : Component Version ID */ - uint32_t I2S_COMP_TYPE; /*!< (0x1FC) : DesignWare Component Type */ -} DW_I2S_RX_REG, *DW_I2S_RX_REG_PTR; - -/** - * @brief Designware I2S transmitter register structure - * @details Detailed struct description of DesignWare I2S transmitter - */ -typedef volatile struct { - uint32_t IER; /*!< (0x000) : Enable Register */ - uint32_t IRER; /*!< (0x004) : I2S Receiver Block Enable Register */ - uint32_t ITER; /*!< (0X008) : I2S Transmitter Block Enable Register*/ - uint32_t CER; /*!< (0x00C) : Clock Enable Register */ - uint32_t CCR; /*!< (0x010) : Clock Configuration Register */ - uint32_t RXFFR; /*!< (0x014) : Receiver Block FIFO Register */ - uint32_t TXFFR; /*!< (0x018) : Transmitter Block FIFO Register */ - uint32_t RESERVED0; /*!< (0x01C) : Reserved */ - uint32_t LTHR0; /*!< (0x020) : Left Transmit Holding Register 0 */ - uint32_t RTHR0; /*!< (0x024) : Right Transmit Holding Register 0 */ - uint32_t RER0; /*!< (0x028) : Receive Enable Register 0 */ - uint32_t TER0; /*!< (0x02C) : Transmit Enable Register 0 */ - uint32_t RCR0; /*!< (0x030) : Receive Configuration Register 0 */ - uint32_t TCR0; /*!< (0x034) : Transmit Configuration Register 0 */ - uint32_t ISR0; /*!< (0x038) : Interrupt Status Register 0 */ - uint32_t IMR0; /*!< (0x03C) : Interrupt Mask Register 0 */ - uint32_t ROR0; /*!< (0x040) : Receive Overrun Register 0 */ - uint32_t TOR0; /*!< (0x044) : Transmit Overrun Register 0 */ - uint32_t RFCR0; /*!< (0x048) : Receive FIFO Configuration Register 0 */ - uint32_t TFCR0; /*!< (0x04C) : Transmit FIFO Configuration Register 0 */ - uint32_t RFF0; /*!< (0x050) : Receive FIFO Flush 0 */ - uint32_t TFF0; /*!< (0x054) : Transmit FIFO Flush 0 */ - uint32_t RESERVED1[2]; /*!< (0x058) : Reserved */ - uint32_t LTHR1; /*!< (0x060) : Left Transmit Holding Register 1 */ - uint32_t RTHR1; /*!< (0x064) : Right Transmit Holding Register 1 */ - uint32_t RER1; /*!< (0x068) : Receive Enable Register 1 */ - uint32_t TER1; /*!< (0x06C) : Transmit Enable Register 1 */ - uint32_t RCR1; /*!< (0x070) : Receive Configuration Register 1 */ - uint32_t TCR1; /*!< (0x074) : Transmit Configuration Register 1 */ - uint32_t ISR1; /*!< (0x078) : Interrupt Status Register 1 */ - uint32_t IMR1; /*!< (0x07C) : Interrupt Mask Register 1 */ - uint32_t ROR1; /*!< (0x080) : Receive Overrun Register 1 */ - uint32_t TOR1; /*!< (0x084) : Transmit Overrun Register 1 */ - uint32_t RFCR1; /*!< (0x088) : Receive FIFO Configuration Register 1 */ - uint32_t TFCR1; /*!< (0x08C) : Transmit FIFO Configuration Register 1 */ - uint32_t RFF1; /*!< (0x090) : Receive FIFO Flush 1 */ - uint32_t TFF1; /*!< (0x094) : Transmit FIFO Flush 1 */ - uint32_t RESERVED2[2]; /*!< (0x098) : Reserved */ - uint32_t LTHR2; /*!< (0x0A0) : Left Transmit Holding Register 2 */ - uint32_t RTHR2; /*!< (0x0A4) : Right Transmit Holding Register 2 */ - uint32_t RER2; /*!< (0x0A8) : Receive Enable Register 2 */ - uint32_t TER2; /*!< (0x0AC) : Transmit Enable Register 2 */ - uint32_t RCR2; /*!< (0x0B0) : Receive Configuration Register 2 */ - uint32_t TCR2; /*!< (0x0B4) : Transmit Configuration Register 2 */ - uint32_t ISR2; /*!< (0x0B8) : Interrupt Status Register 2 */ - uint32_t IMR2; /*!< (0x0BC) : Interrupt Mask Register 2 */ - uint32_t ROR2; /*!< (0x0C0) : Receive Overrun Register 2 */ - uint32_t TOR2; /*!< (0x0C4) : Transmit Overrun Register 2 */ - uint32_t RFCR2; /*!< (0x0C8) : Receive FIFO Configuration Register 2 */ - uint32_t TFCR2; /*!< (0x0CC) : Transmit FIFO Configuration Register 2 */ - uint32_t RFF2; /*!< (0x0D0) : Receive FIFO Flush 2 */ - uint32_t TFF2; /*!< (0x0D4) : Transmit FIFO Flush 2 */ - uint32_t RESERVED3[2]; /*!< (0x0D8) : Reserved */ - uint32_t LTHR3; /*!< (0x0E0) : Left Transmit Holding Register 3 */ - uint32_t RTHR3; /*!< (0x0E4) : Right Transmit Holding Register 3 */ - uint32_t RER3; /*!< (0x0E8) : Receive Enable Register 3 */ - uint32_t TER3; /*!< (0x0EC) : Transmit Enable Register 3 */ - uint32_t RCR3; /*!< (0x0F0) : Receive Configuration Register 3 */ - uint32_t TCR3; /*!< (0x0F4) : Transmit Configuration Register 3 */ - uint32_t ISR3; /*!< (0x0F8) : Interrupt Status Register 3 */ - uint32_t IMR3; /*!< (0x0FC) : Interrupt Mask Register 3 */ - uint32_t ROR3; /*!< (0x100) : Receive Overrun Register 3 */ - uint32_t TOR3; /*!< (0x104) : Transmit Overrun Register 3 */ - uint32_t RFCR3; /*!< (0x108) : Receive FIFO Configuration Register 3 */ - uint32_t TFCR3; /*!< (0x10C) : Transmit FIFO Configuration Register 3 */ - uint32_t RFF3; /*!< (0x110) : Receive FIFO Flush 3 */ - uint32_t TFF3; /*!< (0x114) : Transmit FIFO Flush 3 */ - uint32_t RESERVED4[42]; /*!< (0x118) : Reserved */ - uint32_t RXDMA; /*!< (0x1C0) : Receiver Block DMA Register */ - uint32_t RRXDMA; /*!< (0x1C4) : Reset Receiver Block DMA Register */ - uint32_t TXDMA; /*!< (0x1C8) : Transmitter Block DMA Register */ - uint32_t RTXDMA; /*!< (0x1CC) : Reset Transmitter Block DMA Register */ - uint32_t RESERVED5[8]; /*!< (0x1D0) : Reserved */ - uint32_t I2S_COMP_PARAM_2; /*!< (0x1F0) : Component Parameter 2 Register */ - uint32_t I2S_COMP_PARAM_1; /*!< (0x1F4) : Component Parameter 1 Register */ - uint32_t I2S_COMP_VERSION; /*!< (0x1F8) : Component Version ID */ - uint32_t I2S_COMP_TYPE; /*!< (0x1FC) : DesignWare Component Type */ -} DW_I2S_TX_REG, *DW_I2S_TX_REG_PTR; -/** @} */ - -typedef struct { -#ifdef DW_I2S_DATA_LENGTH_16 - uint16_t *buf; -#else - uint32_t *buf; -#endif - uint32_t ofs; - uint32_t len; -} DW_I2S_BUFFER, *DW_I2S_BUFFER_PTR; - -typedef struct { - uint32_t support_modes; /*!< Supported I2S modes, [DW_I2S_MASTER_SUPPORTED, DW_I2S_SLAVE_SUPPORTED] */ - uint32_t fifo_len; /*!< FIFO length (uint: word) */ - uint32_t channels; /*!< Suppported channels, [DW_I2S_CHANNEL0_SUPPORTED, DW_I2S_CHANNEL3_SUPPORTED] */ - /* Master mode only, clock generation, not available in slave mode */ - uint32_t ws_length; /*!< Number of sclk cycles for which ws_out stays, related to WSS */ - uint32_t sclk_gate; /*!< I2S gating of sclk */ - /* Channel setting */ - uint32_t data_res[4]; /*!< Desired audio data resolution, which can be @ref I2S_AUD_DATA_RES, related WLEN */ - uint32_t sample_rate[4]; /*!< Audio sampling rate, which can be @ref I2S_AUD_SAMPLE_RATE, related to audio reference clk */ - uint32_t intno[4]; /*!< I2S interrupt vector number, bit0-15 tx_emp_intr/rx_da_intr, bit16-31 tx_or_intr/rx_or_intr */ - INT_HANDLER_T dw_i2s_int_handler; /*!< I2S interrupt handler */ -} DW_I2S_CONFIG, *DW_I2S_CONFIG_PTR; - -/** - * @brief Structure definitions for DesignWare I2S control - * @details Structure type for DesignWare I2S implementation - */ -typedef struct { - DW_I2S_RX_REG *dw_i2s_regs; /*!< I2S device registers */ - /* Variables which always change during I2S operation */ - uint32_t int_status[4]; /*!< I2S interrupt status */ - DW_I2S_BUFFER dw_i2s_buf; /*!< I2S read buffer for receive data, left+right data */ -} DW_I2S_RX_CTRL, *DW_I2S_RX_CTRL_PTR; - -typedef struct { - DW_I2S_TX_REG *dw_i2s_regs; /*!< I2S device registers */ - /* Variables which always change during I2S operation */ - uint32_t int_status[4]; /*!< I2S interrupt status */ - DW_I2S_BUFFER dw_i2s_buf; /*!< I2S write buffer for transmit data, left+right data */ -} DW_I2S_TX_CTRL, *DW_I2S_TX_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup DEVICE_DW_I2S_FUNCDLR DesignWare I2S Function Declaration - * @ingroup DEVICE_DW_I2S - * @brief Contains declarations of DesignWare I2S functions - * @details These are only used in I2S object implementation source file - * @{ - */ -extern int32_t dw_i2s_open(DEV_I2S *i2s_obj, uint32_t mode, uint32_t param); -extern int32_t dw_i2s_close(DEV_I2S *i2s_obj); -extern int32_t dw_i2s_control(DEV_I2S *i2s_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_i2s_write(DEV_I2S *i2s_obj, const void *data, uint32_t len, uint32_t channel); -extern int32_t dw_i2s_read(DEV_I2S *i2s_obj, void *data, uint32_t len, uint32_t channel); -extern void dw_i2s_isr_tx(DEV_I2S *i2s_obj, void *ptr); -extern void dw_i2s_isr_rx(DEV_I2S *i2s_obj, void *ptr); -extern uint32_t dw_i2s_write2(DEV_I2S *i2s_obj, const void *data, uint32_t len, uint32_t channel); -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* H_DW_I2S */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s_hal.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s_hal.h deleted file mode 100644 index 1b579e3d..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s_hal.h +++ /dev/null @@ -1,124 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_I2S_HAL -#define H_DW_I2S_HAL - -#include "device/designware/dw_i2s_hal_cfg.h" - -/** IER (I2S Enable Register) */ -#define DW_I2S_IER_IEN 1 - -/** IRER (I2S Receiver Block Enable Register) */ -#define DW_I2S_IRER_RXEN 1 - -/** ITER (I2S Transmitter Block Enable Register) */ -#define DW_I2S_ITER_TXEN 1 - -/** CER (I2S Clock Enable Register) */ -#define DW_I2S_CER_CLKEN 1 - -/** CCR (Clock Configuration Register) */ -#define DW_I2S_CCR_WSS(x) ((x & 0x03) << 3) -#define DW_I2S_CCR_SCLKG(x) (x & 0x07) - -/** RXFFR (Receiver Block FIFO Reset Register) */ -#define DW_I2S_RXFFR_RXFFR 1 - -/** TXFFR (Transmitter Block FIFO Reset Register) */ -#define DW_I2S_TXFFR_TXFFR 1 - -/** LRBRx (Left Receive Buffer Register) */ -#define DW_I2S_LRBR0_LRBR0(x) (x & ((1 << I2S_RX_WORDSIZE_0) - 1)) - -/** LTHRx (Left Transmit Holding Register) */ -#define DW_I2S_LTHR0_LTHR0(x) (x & ((1 << I2S_TX_WORDSIZE_0) - 1)) - -/** RRBRx (Right Receive Buffer Register) */ -#define DW_I2S_RRBR0_RRBR0(x) (x & ((1 << I2S_RX_WORDSIZE_0) - 1)) - -/** RTHRx (Right Transmit Holding Register) */ -#define DW_I2S_RTHR0_RTHR0(x) (x & ((1 << I2S_TX_WORDSIZE_0) - 1)) - -/** RERx (Receive Enable Register) */ -#define DW_I2S_RERX_RXCHENX 1 - -/** TERx (Transmit Enable Register) */ -#define DW_I2S_TERX_TXCHENX 1 - -/** RCRx (Receive Configuration Register) */ -#define DW_I2S_RCRX_WLEN(x) (x & 0x07) - -/** TCRx (Transmit Configuration Register) */ -#define DW_I2S_TCRX_WLEN(x) (x & 0x07) - -/** ISRx (Interrupt Status Register) */ -#define DW_I2S_ISRX_TXFO (1 << 5) -#define DW_I2S_ISRX_TXFE (1 << 4) -#define DW_I2S_ISRX_RXFO (1 << 1) -#define DW_I2S_ISRX_RXDA 1 - -/** IMRx (Interrupt Mask Register) */ -#define DW_I2S_IMRX_TXFOM (1 << 5) -#define DW_I2S_IMRX_TXFEM (1 << 4) -#define DW_I2S_IMRX_RXFOM (1 << 1) -#define DW_I2S_IMRX_RXDAM 1 - -/** RORx (Receive Overrun Register) */ -#define DW_I2S_RORX_RXCHO 1 - -/** TORx (Transmit Overrun Register) */ -#define DW_I2S_TORX_TXCHO 1 - -/** RFCRx (Receive FIFO Configuration Register) */ -#define DW_I2S_RFCRX_RXCHDT(x) (x & 0x0f) - -/** TFCRx (Transmit FIFO Configuration Register) */ -#define DW_I2S_TFCRX_TXCHET(x) (x & 0x0f) - -/** RFFx (Receive FIFO Flush Register) */ -#define DW_I2S_RFFX_RXCHFR 1 - -/** TFFx (Transmit FIFO Flush Register) */ -#define DW_I2S_TFFX_TXCHFR 1 - -/** RXDMA (Receiver Block DMA Register) */ -#define DW_I2S_RXDMA_RXDMA (x & ((1 << APB_DATA_BUS_WIDTH) - 1)) - -/** RRXDMA (Reset Receiver Block DMA Register) */ -#define DW_I2S_RRXDMA_RRXDMA 1 - -/** TXDMA (Transmitter Block DMA Register) */ -#define DW_I2S_TXDMA_TXDMA (x & ((1 << APB_DATA_BUS_WIDTH) - 1)) - -/** RTXDMA (Reset Transmitter Block DMA Register) */ -#define DW_I2S_RTXDMA_RTXDMA 1 - -#endif /* H_DW_I2S_HAL */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s_hal_cfg.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s_hal_cfg.h deleted file mode 100644 index c256e263..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_i2s_hal_cfg.h +++ /dev/null @@ -1,158 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_I2S_HAL_CFG -#define H_DW_I2S_HAL_CFG - -/** Top-level parameters */ - -/** APB data bus width, 8, 16 or 32 bits */ -#ifndef APB_DATA_BUS_WIDTH -#define APB_DATA_BUS_WIDTH 32 -#endif - -/** Receiver block enabled, false (0) or ture (1) */ -#ifndef I2S_RECEIVER_BLOCK -#define I2S_RECEIVER_BLOCK 1 -#endif - -/** Number of receive channels, 1, 2, 3 or 4 channels */ -#ifndef I2S_RX_CHANNELS -#define I2S_RX_CHANNELS 1 -#endif - -/** Transmitter block enabled, false (0) or ture (1) */ -#ifndef I2S_TRANSMITTER_BLOCK -#define I2S_TRANSMITTER_BLOCK 1 -#endif - -/** Number of transmit channels, 1, 2, 3 or 4 channels */ -#ifndef I2S_TX_CHANNELS -#define I2S_TX_CHANNELS 1 -#endif - -/** Set an I2S master, false (0) or ture (1) */ -#ifndef I2S_MODE_EN -#define I2S_MODE_EN 1 -#endif - -/** FIFO depth for RX and TX channels, 2, 4, 8 and 16 words */ -#ifndef I2S_FIFO_DEPTH_GLOBAL -#define I2S_FIFO_DEPTH_GLOBAL 16 -#endif - -/** Word select length, 0 - 16 sclk cycles, 1 - 24 sclk cycles, 2 - 32 sclk cycles */ -#ifndef I2S_WS_LENGTH -#define I2S_WS_LENGTH 32 -#endif - -/** Serial clock gating, 0 - no gating, 1 - 12 clock cycles, 2 - 16 clock cycles, - * 3 - 20 clock cycles, 4 - 24 clock cycles - */ -#ifndef I2S_SCLK_GATE -#define I2S_SCLK_GATE 4 -#endif - -/** Multiple interrupt output ports present, false (0) or ture (1) */ -#ifndef I2S_INTERRUPT_SIGNALS -#define I2S_INTERRUPT_SIGNALS 0 -#endif - -/** Polarity of interrupt signals is acitve high, false (0) or ture (1) */ -#ifndef I2S_INTR_POL -#define I2S_INTR_POL 1 -#endif - -/** Clock domain crossing synchronization depth - * 1 - two-stage synchronization; first stage negative edge, second stage positive edge - * 2 - two-stage synchronization; both stages positive edge - * 3 - three-stage synchronization; all stage positive edge - */ -#ifndef I2S_SYNC_DEPTH -#define I2S_SYNC_DEPTH 2 -#endif - -/** Receiver channel parameters */ - -/** Receiver block DMA enabled, false (0) or ture (1) */ -#ifndef I2S_RX_DMA -#define I2S_RX_DMA 0 -#endif - -/** Max audio resolution - receive channel x, 12, 16, 20, 24 or 32 bits - * only support 0 in this version - */ -#ifndef I2S_RX_WORDSIZE_0 -#define I2S_RX_WORDSIZE_0 16 -#endif - -/** FIFO depth - receive channel x, 2, 4, 8 and 16 words - * only support 0 in this version - */ -#ifndef I2S_RX_FIFO_0 -#define I2S_RX_FIFO_0 I2S_FIFO_DEPTH_GLOBAL -#endif - -/** RX FIFO data available trigger, 0 to I2S_RX_FIFO_x - 1; maximum = 15 - * only support 0 in this version - */ -#ifndef I2S_RX_FIFO_THRE_0 -#define I2S_RX_FIFO_THRE_0 7 -#endif - -/** Transmitter channel parameters */ - -/** Receiver block DMA enabled, false (0) or ture (1) */ -#ifndef I2S_TX_DMA -#define I2S_TX_DMA 0 -#endif - -/** Max audio resolution - transmit channel x, 12, 16, 20, 24 or 32 bits - * only support 0 in this version - */ -#ifndef I2S_TX_WORDSIZE_0 -#define I2S_TX_WORDSIZE_0 16 -#endif - -/** FIFO depth - transmit channel x, 2, 4, 8 and 16 words - * only support 0 in this version - */ -#ifndef I2S_TX_FIFO_0 -#define I2S_TX_FIFO_0 I2S_FIFO_DEPTH_GLOBAL -#endif - -/** TX FIFO data available trigger, 0 to I2S_TX_FIFO_x - 1; maximum = 15 - * only support 0 in this version - */ -#ifndef I2S_TX_FIFO_THRE_0 -#define I2S_TX_FIFO_THRE_0 7 -#endif - -#endif /* H_DW_I2S_HAL_CFG */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic.h deleted file mode 100644 index 4deae889..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic.h +++ /dev/null @@ -1,208 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_IIC -#define H_DW_IIC - -#include "device/ip_hal/dev_iic.h" -#include "arc/arc_exception.h" - -/** - * If this header file is included, - * will indicate that this designware iic device - * is used - */ -#define DEVICE_USE_DESIGNWARE_IIC - -#define DW_IIC_MASTER_SUPPORTED (0x1) /*!< Support Designware IIC Master Mode */ -#define DW_IIC_SLAVE_SUPPORTED (0x2) /*!< Support Designware IIC Slave Mode */ -/*!< Support Designware IIC Both Master and Slave Mode */ -#define DW_IIC_BOTH_SUPPORTED (DW_IIC_MASTER_SUPPORTED | DW_IIC_SLAVE_SUPPORTED) - -#define DW_IIC_INVALID_INTNO (DEV_INTNO_INVALID) - -enum { - DW_IIC_CAP_LOADING_100PF = 0, - DW_IIC_CAP_LOADING_400PF -}; - -/** - * @defgroup DEVICE_DW_IIC_REGSTRUCT DesignWare IIC Register Structure - * @ingroup DEVICE_DW_I2S - * @brief Structure definitions for DesignWare IIC register - * @details Detailed struct description of DesignWare IIC - * block register information, implementation of DEV_IIC_INFO::iic_regs - * @{ - */ -typedef volatile struct { - uint32_t IC_CON; /*!< (0x00) : IIC control */ - uint32_t IC_TAR; /*!< (0x04) : IIC target address */ - uint32_t IC_SAR; /*!< (0x08) : IIC slave address */ - uint32_t IC_HS_MADDR; /*!< (0x0c) : IIC HS Master Mode Code address */ - uint32_t IC_DATA_CMD; /*!< (0x10) : IIC Rx/Tx Data Buffer and Command */ - uint32_t IC_SS_SCL_HCNT; /*!< (0x14) : Standard Speed IIC clock SCL High Count */ - uint32_t IC_SS_SCL_LCNT; /*!< (0x18) : Standard Speed IIC clock SCL Low Count */ - uint32_t IC_FS_SCL_HCNT; /*!< (0x1c) : Fast Speed IIC clock SCL Low Count */ - uint32_t IC_FS_SCL_LCNT; /*!< (0x20) : Fast Speed IIC clock SCL Low Count */ - uint32_t IC_HS_SCL_HCNT; /*!< (0x24) : High Speed IIC clock SCL Low Count */ - uint32_t IC_HS_SCL_LCNT; /*!< (0x28) : High Speed IIC clock SCL Low Count */ - uint32_t IC_INTR_STAT; /*!< (0x2c) : IIC Interrupt Status */ - uint32_t IC_INTR_MASK; /*!< (0x30) : IIC Interrupt Mask */ - uint32_t IC_RAW_INTR_STAT; /*!< (0x34) : IIC Raw Interrupt Status */ - uint32_t IC_RX_TL; /*!< (0x38) : IIC Receive FIFO Threshold */ - uint32_t IC_TX_TL; /*!< (0x3c) : IIC Transmit FIFO Threshold */ - uint32_t IC_CLR_INTR; /*!< (0x40) : Clear combined and Individual Interrupts */ - uint32_t IC_CLR_RX_UNDER; /*!< (0x44) : Clear RX_UNDER Interrupt */ - uint32_t IC_CLR_RX_OVER; /*!< (0x48) : Clear RX_OVER Interrupt */ - uint32_t IC_CLR_TX_OVER; /*!< (0x4c) : Clear TX_OVER Interrupt */ - uint32_t IC_CLR_RD_REQ; /*!< (0x50) : Clear RQ_REQ Interrupt */ - uint32_t IC_CLR_TX_ABRT; /*!< (0x54) : Clear TX_ABRT Interrupt */ - uint32_t IC_CLR_RX_DONE; /*!< (0x58) : Clear RX_DONE Interrupt */ - uint32_t IC_CLR_ACTIVITY; /*!< (0x5c) : Clear ACTIVITY Interrupt */ - uint32_t IC_CLR_STOP_DET; /*!< (0x60) : Clear STOP_DET Interrupt */ - uint32_t IC_CLR_START_DET; /*!< (0x64) : Clear START_DET Interrupt */ - uint32_t IC_CLR_GEN_CALL; /*!< (0x68) : Clear GEN_CALL Interrupt */ - uint32_t IC_ENABLE; /*!< (0x6c) : IIC Enable */ - uint32_t IC_STATUS; /*!< (0x70) : IIC Status */ - uint32_t IC_TXFLR; /*!< (0x74) : Transmit FIFO Level Register */ - uint32_t IC_RXFLR; /*!< (0x78) : Receive FIFO Level Register */ - uint32_t IC_SDA_HOLD; /*!< (0x7c) : SDA Hold Time Length Reg */ - uint32_t IC_TX_ABRT_SOURCE; /*!< (0x80) : IIC Transmit Abort Status Reg */ - uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (0x84) : Generate SLV_DATA_NACK Register */ - uint32_t IC_DMA_CR; /*!< (0x88) : DMA Control Register */ - uint32_t IC_DMA_TDLR; /*!< (0x8c) : DMA Transmit Data Level */ - uint32_t IC_DMA_RDLR; /*!< (0x90) : DMA Receive Data Level */ - uint32_t IC_SDA_SETUP; /*!< (0x94) : SDA Setup Register */ - uint32_t IC_ACK_GENERAL_CALL; /*!< (0x98) : ACK General Call Register */ - uint32_t IC_ENABLE_STATUS; /*!< (0x9c) : Enable Status Register */ - uint32_t IC_FS_SPKLEN; /*!< (0xa0) : ISS and FS spike suppression limit */ - uint32_t IC_HS_SPKLEN; /*!< (0xa4) : HS spike suppression limit */ - uint32_t RESERVED[19]; /*!< (0xa8) : Reserved */ - uint32_t IC_COMP_PARAM_1; /*!< (0xf4) : Component Parameter Register */ - uint32_t IC_COMP_VERSION; /*!< (0xf8) : Component Version ID Reg */ - uint32_t IC_COMP_TYPE; /*!< (0xfc) : Component Type Reg */ -} DW_IIC_REG, *DW_IIC_REG_PTR; -/** @} */ - -/** Spike Suppression Limit Configurations */ -typedef struct { - uint32_t fs_spklen; /*!< value for IC_FS_SPKLEN, Tsp for fast mode is 50ns */ - uint32_t hs_spklen; /*!< value for IC_HS_SPKLEN, Tsp for high-speed mode is 10ns */ -} DW_IIC_SPKLEN, *DW_IIC_SPKLEN_PTR; - -/** IIC Clock SCL High and Low Count Configurations for Different Speed */ -typedef struct { - uint32_t ss_scl_hcnt; /*!< value for IC_SS_SCL_HCNT */ - uint32_t ss_scl_lcnt; /*!< value for IC_SS_SCL_LCNT */ - uint32_t fs_scl_hcnt; /*!< value for IC_FS_SCL_HCNT */ - uint32_t fs_scl_lcnt; /*!< value for IC_FS_SCL_LCNT */ - uint32_t hs_scl_hcnt; /*!< value for IC_HS_SCL_HCNT */ - uint32_t hs_scl_lcnt; /*!< value for IC_HS_SCL_LCNT */ -} DW_IIC_SCL_CNT, *DW_IIC_SCL_CNT_PTR; - -#define DW_IIC_GINT_DISABLED (0) /*!< designware interrupt disabled for control iic irq/fiq */ -#define DW_IIC_GINT_ENABLE (1 << 0) /*!< designware interrupt enabled for control iic irq/fiq */ -#define DW_IIC_TXINT_ENABLE (1 << 1) /*!< designware interrupt enabled for control transmit process */ -#define DW_IIC_RXINT_ENABLE (1 << 2) /*!< designware interrupt enabled for control transmit process */ - -typedef struct { - DEV_BUFFER *buf; - uint32_t ofs; - uint32_t len; -} DW_IIC_BUFFER, *DW_IIC_BUFFER_PTR; - -/** - * @brief Structure definitions for DesignWare IIC control - * @details implement of DEV_IIC_INFO::iic_ctrl - */ -typedef struct { - DW_IIC_REG *dw_iic_regs; /*!< iic device registers */ - /* Variables which should be set during object implementation */ - uint32_t ic_clkhz; /*!< IC clock in HZ */ - uint32_t ic_caploading; /*!< I2C Bus cap loading pf */ - uint32_t support_modes; /*!< supported iic modes */ - uint32_t tx_fifo_len; /*!< transmit fifo length */ - uint32_t rx_fifo_len; /*!< receive fifo length */ - uint32_t iic_master_code; /*!< value for IC_HS_MADDR */ - uint32_t retry_cnt; /*!< retry count for TX or RX */ - uint32_t intno; /*!< iic interrupt vector number */ - INT_HANDLER_T dw_iic_int_handler; /*!< iic interrupt handler */ - DW_IIC_SPKLEN iic_spklen; /*!< iic spike suppression length settings */ - DW_IIC_SCL_CNT iic_scl_cnt; /*!< iic scl count settings */ - /* Variables which always change during iic operation */ - uint32_t int_status; /*!< iic interrupt status */ - uint32_t iic_tx_over; /*!< iic tx overflow count */ - uint32_t iic_rx_over; /*!< iic rx overflow count */ - DW_IIC_BUFFER dw_iic_rxbuf; /*!< iic read buffer for receive data */ -} DW_IIC_CTRL, *DW_IIC_CTRL_PTR; - -/*!< One possible value for @ref DW_IIC_CTRL::retry_cnt */ -#define DW_IIC_MAX_RETRY_COUNT (100000) - -#define DW_IIC_FS_SPKLEN_NS (50) -#define DW_IIC_HS_SPKLEN_NS (10) - -#define MIN_DW_IIC_SS_SCL_LCNT(spklen) ((spklen) + 7) -#define MIN_DW_IIC_FS_SCL_LCNT(spklen) ((spklen) + 7) - -#define MIN_DW_IIC_SS_SCL_HCNT(spklen) ((spklen) + 5) -#define MIN_DW_IIC_FS_SCL_HCNT(spklen) ((spklen) + 5) - -#define MIN_DW_IIC_HS_SCL_LCNT(spklen) ((spklen) + 7) -#define MIN_DW_IIC_HS_SCL_HCNT(spklen) ((spklen) + 5) - -#define MIN_DW_IIC_SS_HIGH_TIME_NS (4000) -#define MIN_DW_IIC_SS_LOW_TIME_NS (4700) - -#define MIN_DW_IIC_FS_HIGH_TIME_NS (600) -#define MIN_DW_IIC_FS_LOW_TIME_NS (1300) - -#define MIN_DW_IIC_HS_100PF_HIGH_TIME_NS (60) -#define MIN_DW_IIC_HS_100PF_LOW_TIME_NS (160) - -#define MIN_DW_IIC_HS_400PF_HIGH_TIME_NS (120) -#define MIN_DW_IIC_HS_400PF_LOW_TIME_NS (320) - -#ifdef __cplusplus -extern "C" { -#endif - -extern int32_t dw_iic_open(DEV_IIC *iic_obj, uint32_t mode, uint32_t param); -extern int32_t dw_iic_close(DEV_IIC *iic_obj); -extern int32_t dw_iic_control(DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_iic_write(DEV_IIC *iic_obj, const void *data, uint32_t len); -extern int32_t dw_iic_read(DEV_IIC *iic_obj, void *data, uint32_t len); -extern void dw_iic_isr(DEV_IIC *iic_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -#endif /* H_DW_IIC */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic_hal.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic_hal.h deleted file mode 100644 index 1fdfa5ed..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic_hal.h +++ /dev/null @@ -1,174 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_IIC_HAL -#define H_DW_IIC_HAL - -#include "device/designware/dw_iic_hal_cfg.h" - -/** Enable Designware IIC */ -#define DW_IIC_ENABLE (1) -/** Disable Designware IIC */ -#define DW_IIC_DISABLE (0) - -/** Stop Condition issue after this byte */ -#define IC_DATA_CMD_STOP (1 << 9) -/** Restart Condition issue after this byte */ -#define IC_DATA_CMD_RESTART (1 << 10) -/** No Restart or stop condition after this byte */ -#define IC_DATA_CMD_NONE (0) - -/** Perform a write request */ -#define IC_DATA_CMD_WRITE_REQ (0) -/** Perform a read request */ -#define IC_DATA_CMD_READ_REQ (1 << 8) - -/** Fields of IC_CON register */ -/* DW_APB I2C IP Config Dependencies. */ -#if DW_IIC_ALLOW_RESTART -#define IC_CON_RESTART_EN (1 << 5) -#else -#define IC_CON_RESTART_EN (0x00) -#endif - -/* Master Addressing Mode Config */ -#if DW_IIC_MST_10_BIT_ADDR_SUPPORT -#define MST_10_BIT_ADDR_MODE (1 << 4) -#define IC_10BITADDR_MASTER (1 << 12) -#else -#define MST_10_BIT_ADDR_MODE (0x00) -#define IC_10BITADDR_MASTER (0x00) -#endif - -/* Slave Addressing Mode Config */ -#if DW_IIC_SLV_10_BIT_ADDR_SUPPORT -#define SLV_10_BIT_ADDR_MODE (1 << 3) -#else -#define SLV_10_BIT_ADDR_MODE (0x00) -#endif - -#if DW_IIC_SPECIAL_START_BYTE -#define IC_TAR_SPECIAL (1 << 11) -#define IC_TAR_GC_OR_START (1 << 10) -#else -#define IC_TAR_SPECIAL (0x00) -#define IC_TAR_GC_OR_START (0x00) -#endif - -/** 7bit IIC address mask for target address register */ -#define IC_TAR_7BIT_ADDR_MASK (0x7F) -/** 7bit IIC address mask for slave address register */ -#define IC_SAR_7BIT_ADDR_MASK (0x7F) -/** 10bit IIC address mask for target address register */ -#define IC_TAR_10BIT_ADDR_MASK (0x3FF) -/** 10bit IIC address mask for slave address register */ -#define IC_SAR_10BIT_ADDR_MASK (0x3FF) - -/** Speed modes of IC_CON */ -#define IC_CON_SPEED_MASK (0x6) -#define IC_CON_SPEED_STANDARD (0x2) -#define IC_CON_SPEED_FAST (0x4) -#define IC_CON_SPEED_HIGH (0x6) -/** Working mode of IC_CON */ -#define IC_CON_MST_SLV_MODE_MASK (0x41) -#define IC_CON_ENA_MASTER_MODE (0x41) -#define IC_CON_ENA_SLAVE_MODE (0) - -/* IIC interrupt control */ -#define IC_INT_DISABLE_ALL (0x0) -#define IC_INT_ENABLE_ALL (0x7FF) -/* Interrupt Register Fields */ -#define IC_INTR_STAT_GEN_CALL (1 << 11) -#define IC_INTR_STAT_START_DET (1 << 10) -#define IC_INTR_STAT_STOP_DET (1 << 9) -#define IC_INTR_STAT_ACTIVITY (1 << 8) -#define IC_INTR_STAT_RX_DONE (1 << 7) -#define IC_INTR_STAT_TX_ABRT (1 << 6) -#define IC_INTR_STAT_RD_REQ (1 << 5) -#define IC_INTR_STAT_TX_EMPTY (1 << 4) -#define IC_INTR_STAT_TX_OVER (1 << 3) -#define IC_INTR_STAT_RX_FULL (1 << 2) -#define IC_INTR_STAT_RX_OVER (1 << 1) -#define IC_INTR_STAT_RX_UNDER (1 << 0) - -/* Interrupt enable mask as master */ -#define IC_INT_MST_TX_ENABLE (IC_INTR_STAT_TX_EMPTY | IC_INTR_STAT_TX_OVER | IC_INTR_STAT_TX_ABRT) -#define IC_INT_MST_RX_ENABLE (IC_INTR_STAT_TX_EMPTY | IC_INTR_STAT_RX_FULL | IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER | IC_INTR_STAT_TX_ABRT) - -/* Interrupt enable mask as master */ -#define IC_INT_SLV_COMMON_ENABLE (IC_INTR_STAT_START_DET | IC_INTR_STAT_STOP_DET) -#define IC_INT_SLV_TX_ENABLE (IC_INTR_STAT_RD_REQ | IC_INTR_STAT_TX_ABRT) -#define IC_INT_SLV_RX_ENABLE (IC_INTR_STAT_RX_FULL | IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER) - -/* IC_ENABLE_STATUS Bits */ -#define IC_ENABLE_STATUS_IC_EN (1 << 0) -#define IC_ENABLE_STATUS_SLV_DIS (1 << 1) -#define IC_ENABLE_STATUS_SLV_RX_LOST (1 << 2) - -/* IIC TX & RX threshold settings */ -#define IIC_TX_THRESHOLD (0) -#define IIC_RX_THRESHOLD (0) - -/* DW_APB IIC (DW_IC_STATUS) Status Register Fields. */ -#define IC_STATUS_ACTIVITY (0x01) -#define IC_STATUS_TFNF (0x02) /* (1 << 1) */ -#define IC_STATUS_TFE (0x04) /* (1 << 2) */ -#define IC_STATUS_RFNE (0x08) /* (1 << 3) */ -#define IC_STATUS_RFF (0x10) /* (1 << 4) */ -#define IC_STATUS_MASTER_ACT (0x20) /* (1 << 5) */ -#define IC_STATUS_SLAVE_ACT (0x40) /* (1 << 6) */ - -/* IC_TX_ABRT_SOURCE Register Bit Fields */ -#define IC_TX_ABRT_7B_ADDR_NOACK (1 << 0) -#define IC_TX_ABRT_10ADDR1_NOACK (1 << 1) -#define IC_TX_ABRT_10ADDR2_NOACK (1 << 2) -#define IC_TX_ABRT_TXDATA_NOACK (1 << 3) -#define IC_TX_ABRT_GCALL_NOACK (1 << 4) -#define IC_TX_ABRT_GCALL_READ (1 << 5) -#define IC_TX_ABRT_HS_ACKDET (1 << 6) -#define IC_TX_ABRT_SBYTE_ACKDET (1 << 7) -#define IC_TX_ABRT_HS_NORSTRT (1 << 8) -#define IC_TX_ABRT_SBYTE_NORSTRT (1 << 9) -#define IC_TX_ABRT_10B_RD_NORSTRT (1 << 10) -#define IC_TX_ABRT_MASTER_DIS (1 << 11) -#define IC_TX_ABRT_ARB_LOST (1 << 12) -#define IC_TX_ABRT_SLVFLUSH_TXFIFO (1 << 13) -#define IC_TX_ABRT_SLV_ARBLOST (1 << 14) -#define IC_TX_ABRT_SLVRD_INTX (1 << 15) - -/* Combined bits for iic abort source as master */ -#define IIC_MST_ABRT_ADDR_NOACK (IC_TX_ABRT_7B_ADDR_NOACK | IC_TX_ABRT_10ADDR1_NOACK | IC_TX_ABRT_10ADDR1_NOACK) -#define IIC_MST_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST) -#define IIC_MST_ABRT_DATA_NOACK (IC_TX_ABRT_TXDATA_NOACK) - -/* Combined bits for iic abort source as slave */ -#define IIC_SLV_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST | IC_TX_ABRT_SLV_ARBLOST) - -#endif /* H_DW_IIC_HAL */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic_hal_cfg.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic_hal_cfg.h deleted file mode 100644 index b5cd4978..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_iic_hal_cfg.h +++ /dev/null @@ -1,62 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_IIC_HAL_CFG -#define H_DW_IIC_HAL_CFG - -#ifndef DW_IIC_ALLOW_RESTART -#define DW_IIC_ALLOW_RESTART (1) /*!< allow restart configuration */ -#endif - -#ifdef DW_IIC_SPECIAL_START_BYTE -#define DW_IIC_SPECIAL_START_BYTE (0) /*!< SPECIAL bit enable in IC_TAR */ -#endif - -#ifndef DW_IIC_MST_10_BIT_ADDR_SUPPORT -#define DW_IIC_MST_10_BIT_ADDR_SUPPORT (1) /*!< enable 10-bit address mode */ -#endif - -#ifdef DW_IIC_SLV_10_BIT_ADDR_SUPPORT -#define DW_IIC_SLV_10_BIT_ADDR_SUPPORT (1) /*!< slave 10-bit addressing mode */ -#endif - -#ifndef DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT -#define DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT (0) /*!< Dynamic target address update support */ -#endif - -#ifndef DW_IIC_DISABLE_MAX_T_POLL_CNT -#define DW_IIC_DISABLE_MAX_T_POLL_CNT (1250) /*!< Timeout count, approximate to be 25us in 50MHz CPU @ Standard mode */ -#endif - -#ifndef DW_IIC_CALC_FIFO_LEN_ENABLE -#define DW_IIC_CALC_FIFO_LEN_ENABLE (1) /*!< Default enable calculate fifo length */ -#endif - -#endif /* H_DW_IIC_HAL_CFG */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_nist_trng.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_nist_trng.h deleted file mode 100644 index 96703c1a..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_nist_trng.h +++ /dev/null @@ -1,169 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_DW_NIST_TRNG -#define H_DW_NIST_TRNG - -#include "device/ip_hal/dev_trng.h" -#include "arc/arc_exception.h" - -#ifdef TRNG_VERSION_NIST - -#define DW_TRNG_GINT_DISABLE (0) -#define DW_TRNG_GINT_ENABLE (1 << 31) -#define DW_TRNG_INT_ZEROIZED_ENABLE (1 << 0) -#define DW_TRNG_INT_KAT_ENABLE (1 << 1) -#define DW_TRNG_INT_NOISE_RDY_ENABLE (1 << 2) -#define DW_TRNG_INT_ALARMS_ENABLE (1 << 3) -#define DW_TRNG_INT_DONE_ENABLE (1 << 4) -#define DW_TRNG_INT_ALL (0x8000001F) -#define DW_TRNG_ISTATE_ALL (0x1F) - -#define DW_TRNG_INVALID_INTNO (DEV_INTNO_INVALID) - -// DesignWare NIST TRNG register structure -typedef volatile struct dw_nist_trng_reg { - uint32_t CTRL; // (0x0) - uint32_t MODE; // (0x4) - union { - uint32_t SMODE; // (0x8) - struct { - uint32_t nonce : 1; - uint32_t secure_en : 1; - uint32_t max_rejecets : 8; - uint32_t rsvd : 22; - } smode; - }; - union { - uint32_t STAT; // (0xC) - struct { - uint32_t last_cmd : 4; - uint32_t sec_alg : 1; - uint32_t nonce_mode : 1; - uint32_t secure : 1; - uint32_t drbg_state : 2; - uint32_t rsvd : 22; - uint32_t busy : 1; - } stat; - }; - union { - uint32_t IE; // (0x10) - struct { - uint32_t zeroized : 1; - uint32_t kat_completed : 1; - uint32_t noise_rdy : 1; - uint32_t alarms : 1; - uint32_t done : 1; - uint32_t rsvd : 26; - uint32_t glbl : 1; - } ie; - }; - union { - uint32_t ISTAT; // (0x14) - struct { - uint32_t zeroized : 1; - uint32_t kat_completed : 1; - uint32_t noise_rdy : 1; - uint32_t alarms : 1; - uint32_t done : 1; - uint32_t rsvd : 27; - } istat; - }; - union { - uint32_t ALARMS; // (0x18) - struct { - uint32_t failed_test_id : 4; - uint32_t illegal_cmd_seq : 1; - uint32_t rsvd : 27; - } alarms; - }; - uint32_t COREKIT_REL; // (0x1C) - uint32_t FEATURES; // (0x20) - uint32_t RAND0; // (0x24) - uint32_t RAND1; // (0x28) - uint32_t RAND2; // (0x2C) - uint32_t RAND3; // (0x30) - uint32_t NPA_DATA0; // (0x34) - uint32_t NPA_DATA1; // (0x38) - uint32_t NPA_DATA2; // (0x3C) - uint32_t NPA_DATA3; // (0x40) - uint32_t NPA_DATA4; // (0x44) - uint32_t NPA_DATA5; // (0x48) - uint32_t NPA_DATA6; // (0x4C) - uint32_t NPA_DATA7; // (0x50) - uint32_t NPA_DATA8; // (0x54) - uint32_t NPA_DATA9; // (0x58) - uint32_t NPA_DATA10; // (0x5C) - uint32_t NPA_DATA11; // (0x60) - uint32_t NPA_DATA12; // (0x64) - uint32_t NPA_DATA13; // (0x68) - uint32_t NPA_DATA14; // (0x6C) - uint32_t NPA_DATA15; // (0x70) - uint32_t SEED0; // (0x74) - uint32_t SEED1; // (0x78) - uint32_t SEED2; // (0x7C) - uint32_t SEED3; // (0x80) - uint32_t SEED4; // (0x84) - uint32_t SEED5; // (0x88) - uint32_t SEED6; // (0x8C) - uint32_t SEED7; // (0x90) - uint32_t SEED8; // (0x94) - uint32_t SEED9; // (0x98) - uint32_t SEED10; // (0x9C) - uint32_t SEED11; // (0xA0) - uint32_t IA_RDATA; // (0xA4) - uint32_t IA_WDATA; // (0xA8) - uint32_t IA_ADDR; // (0xAC) - uint32_t IA_CMD; // (0xB0) -} DW_TRNG_REG, *DW_TRNG_REG_PTR; - -typedef struct dw_trng_ctrl { - DW_TRNG_REG_PTR dw_trng_regs; /*!< dw trng register */ - uint32_t intno; /*!< interrupt vector number */ - INT_HANDLER_T dw_trng_int_handler; /*!< interrupt handler */ - uint32_t int_status; /*!< interrupt status */ -} DW_TRNG_CTRL, *DW_TRNG_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -extern int32_t dw_trng_open(DEV_TRNG_PTR trng_obj); -extern int32_t dw_trng_close(DEV_TRNG_PTR trng_obj); -extern int32_t dw_trng_control(DEV_TRNG_PTR trng_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_trng_read(DEV_TRNG_PTR trng_obj, uint32_t *data_buf); -extern void dw_trng_isr(DEV_TRNG_PTR trng_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -#endif /* TRNG_VERSION_NIST */ - -#endif /* H_DW_NIST_TRNG */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_pwm_timer.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_pwm_timer.h deleted file mode 100644 index 63784322..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_pwm_timer.h +++ /dev/null @@ -1,106 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_DW_PWM_TIMER -#define H_DW_PWM_TIMER - -#include "device/ip_hal/dev_pwm_timer.h" -#include "arc/arc_exception.h" - -#define DW_PWM_TIMER_CH_MAX_COUNT 8 - -#define DW_PWM_TIMER_INVALID_INTNO (DEV_INTNO_INVALID) - -/** - * @name Structure definitions for DesignWare PWM_TIMER Register - * @brief Contains definitions of DesignWare PWM_TIMER register structure - * @{ - */ -typedef volatile struct { - uint32_t LOAD_COUNT; /*!< Value to be loaded into Timer */ - uint32_t CURRENT_VALUE; /*!< Current Value of Timer */ - uint32_t CONTROL_REG; /*!< Control Register for Timer */ - uint32_t EOI; /*!< Clears the interrupt from Timer */ - uint32_t INT_STATUS; /*!< Contains the interrupt status for Timer */ -} CH_CTRL; - -typedef volatile struct { - CH_CTRL CTRL[DW_PWM_TIMER_CH_MAX_COUNT]; /*!< (0x00 ~ 0x9C) */ - uint32_t PWM_TIMERS_INT_STATUS; /*!< (0xA0) Contains the interrupt status of all timers in the component.*/ - uint32_t PWM_TIMERS_EOI; /*!< (0xA4) Read return all zeroes (0) and clears all active interrupts.*/ - uint32_t PWM_TIMERS_RAWINT_STATUS; /*!< (0xA8) Contains the unmasked interrupt status of all timers in the component.*/ - uint32_t PWM_TIMERS_COMP_VER; /*!< (0xAC) Current revision number of the DW_apb_timers component.*/ - uint32_t LOAD_COUNT2[DW_PWM_TIMER_CH_MAX_COUNT]; /*!< (0xB0 ~ 0xCC) Value to be loaded into Timer when toggle output changes from 0 to 1*/ -} DW_PWM_TIMER_REG, *DW_PWM_TIMER_REG_PTR; -/** @} */ - -/** interrupt handler for each pwm_timer channel */ -typedef struct { - uint32_t int_ch_max_cnt; /*!< max channel count for each pwm_timer group */ - DEV_PWM_TIMER_HANDLER *int_ch_handler_ptr; /*!< interrupt handler pointer */ -} DW_PWM_TIMER_CH_ISR, *DW_PWM_TIMER_CH_ISR_PTR; - -/** - * @brief Structure definitions for DesignWare PWM_TIMER control - * @details Structure type for DesignWare PWM_TIMER implementation - */ -typedef struct { - uint32_t id; /*!< pwm_timer group id */ - DW_PWM_TIMER_REG_PTR regs; /*!< pwm_timer port register */ - uint32_t intno; /*!< pwm_timer interrupt vector number */ - uint32_t ch_num; /*!< pwm_timer group channel count */ - uint32_t clock; /*!< pwm_timer clock */ - INT_HANDLER_T int_handler; /*!< pwm_timer interrupt handler pointer */ - DW_PWM_TIMER_CH_ISR_PTR ch_isr; /*!< pwm_timer group channel callback pointer */ - DEV_PWM_TIMER_MODE_PTR mode; /*!< pwm_timer group channel work mode array pointer*/ -} DW_PWM_TIMER_CTRL, *DW_PWM_TIMER_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name DesignWare PWM_TIMER Function Declaration - * @brief Contains declarations of designware pwm_timer functions. - * @details These are only used in pwm_timer object implementation source file - * @{ - */ -extern int32_t dw_pwm_timer_open(DEV_PWM_TIMER *pwm_timer_obj); -extern int32_t dw_pwm_timer_close(DEV_PWM_TIMER *pwm_timer_obj); -extern int32_t dw_pwm_timer_read(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc); -extern int32_t dw_pwm_timer_write(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc); -extern int32_t dw_pwm_timer_control(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t cmd, void *param); -extern int32_t dw_pwm_timer_isr_handler(DEV_PWM_TIMER *pwm_timer_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -#endif /* H_DW_PWM_TIMER */ -/** @} */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_sdio.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_sdio.h deleted file mode 100644 index 39672d92..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_sdio.h +++ /dev/null @@ -1,72 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_DW_SDIO -#define H_DW_SDIO - -#include "device/ip_hal/dev_sdio.h" -#include "arc/arc_builtin.h" - -/** - * @brief Structure definitions for DesignWare SDIO control - * @details Structure type for DesignWare SDIO implementation - */ -typedef struct { - void *reg_base; /*!< sdio registers base */ - uint32_t ref_clk; /* reference clk */ - uint32_t intno; /* interrupt no */ - uint32_t fifo_depth; - /* Variables which should be set during object implementation */ -} DW_SDIO_CTRL, *DW_SDIO_CTRL_PTR; - -/** - * @fn uint32_t dw_sdio_reg_read(DW_SDIO_CTRL_PTR sdio, uint32_t reg) - */ -Inline uint32_t dw_sdio_reg_read(DW_SDIO_CTRL_PTR sdio, uint32_t reg) -{ - return arc_read_uncached_32((void *)((uint32_t)sdio->reg_base + reg)); -} - -/** - * @fn void dw_sdio_reg_write(DW_SDIO_CTRL_PTR sdio, uint32_t reg, uint32_t val) - */ -Inline void dw_sdio_reg_write(DW_SDIO_CTRL_PTR sdio, uint32_t reg, uint32_t val) -{ - arc_write_uncached_32((void *)((uint32_t)sdio->reg_base + reg), val); -} - -extern void dw_sdio_isr(DEV_SDIO *sdio_obj, void *ptr); -extern int32_t dw_sdio_cmd_poll(DEV_SDIO *sdio_obj, SDIO_CMD_PTR cmd, SDIO_DATA_PTR data); -extern int32_t dw_sdio_open(DEV_SDIO *sdio_obj, uint32_t card_number); -extern int32_t dw_sdio_close(DEV_SDIO *sdio_obj, uint32_t card_number); -extern int32_t dw_sdio_cd(DEV_SDIO *sdio_obj, uint32_t card_number); -extern int32_t dw_sdio_wp(DEV_SDIO *sdio_obj, uint32_t card_number); -extern int32_t dw_sdio_control(DEV_SDIO *sdio_obj, SDIO_CTRL_CMD_PTR ctrl_cmd, void *param); - -#endif /* H_DW_SDIO */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_sdio_hal.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_sdio_hal.h deleted file mode 100644 index 9cb69c23..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_sdio_hal.h +++ /dev/null @@ -1,237 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_DW_SDIO_HAL -#define H_DW_SDIO_HAL - -/* register offset */ -#define DWSDIO_REG_CTRL (0x000) -#define DWSDIO_REG_PWREN (0x004) -#define DWSDIO_REG_CLKDIV (0x008) -#define DWSDIO_REG_CLKSRC (0x00C) -#define DWSDIO_REG_CLKENA (0x010) -#define DWSDIO_REG_TMOUT (0x014) -#define DWSDIO_REG_CTYPE (0x018) -#define DWSDIO_REG_BLKSIZ (0x01C) -#define DWSDIO_REG_BYTCNT (0x020) -#define DWSDIO_REG_INTMASK (0x024) -#define DWSDIO_REG_CMDARG (0x028) -#define DWSDIO_REG_CMD (0x02C) -#define DWSDIO_REG_RESP0 (0x030) -#define DWSDIO_REG_RESP1 (0x034) -#define DWSDIO_REG_RESP2 (0x038) -#define DWSDIO_REG_RESP3 (0x03C) -#define DWSDIO_REG_MINTSTS (0x040) -#define DWSDIO_REG_RINTSTS (0x044) -#define DWSDIO_REG_STATUS (0x048) -#define DWSDIO_REG_FIFOTH (0x04C) -#define DWSDIO_REG_CDETECT (0x050) -#define DWSDIO_REG_WRTPRT (0x054) -#define DWSDIO_REG_GPIO (0x058) -#define DWSDIO_REG_TCMCNT (0x05C) -#define DWSDIO_REG_TBBCNT (0x060) -#define DWSDIO_REG_DEBNCE (0x064) -#define DWSDIO_REG_USRID (0x068) -#define DWSDIO_REG_VERID (0x06C) -#define DWSDIO_REG_HCON (0x070) -#define DWSDIO_REG_UHS_REG (0x074) -#define DWSDIO_REG_RST_N (0x078) -#define DWSDIO_REG_BMOD (0x080) -#define DWSDIO_REG_PLDMND (0x084) -#define DWSDIO_REG_DBADDR (0x088) -#define DWSDIO_REG_IDSTS (0x08C) -#define DWSDIO_REG_IDINTEN (0x090) -#define DWSDIO_REG_DSCADDR (0x094) -#define DWSDIO_REG_BUFADDR (0x098) -#define DWSDIO_REG_CARD_THR_CTRL (0x100) -#define DWSDIO_REG_UHS_REG_EXT (0x108) -#define DWSDIO_REG_DATA (0x200) - -/* DW AHB SDIO bit definitions */ -#define DWSDIO_CTRL_BIT_RESET_CTRL 0 -#define DWSDIO_CTRL_RESET_CTRL (1 << DWSDIO_CTRL_BIT_RESET_CTRL) -#define DWSDIO_CTRL_BIT_RESET_FIFO 1 -#define DWSDIO_CTRL_RESET_FIFO (1 << DWSDIO_CTRL_BIT_RESET_FIFO) -#define DWSDIO_CTRL_BIT_RESET_DMA 2 -#define DWSDIO_CTRL_RESET_DMA (1 << DWSDIO_CTRL_BIT_RESET_DMA) - -#define DWSDIO_CTRL_RESET_ALL (DWSDIO_CTRL_RESET_CTRL | DWSDIO_CTRL_RESET_FIFO | DWSDIO_CTRL_RESET_DMA) -#define DWSDIO_CTRL_BIT_INT_ENABLE 4 -#define DWSDIO_CTRL_INT_ENABLE (1 << DWSDIO_CTRL_BIT_INT_ENABLE) - -#define DWSDIO_CTRL_BIT_DMA_ENABLE 5 -#define DWSDIO_CTRL_DMA_ENABLE (1 << DWSDIO_CTRL_BIT_DMA_ENABLE) - -#define DWSDIO_CTRL_BIT_ODPULLUP 24 -#define DWSDIO_CTRL_ODPULLUP (1 << DWSDIO_CTRL_BIT_ODPULLUP) - -#define DWSDIO_CTRL_BIT_INTERNAL_DMA 25 -#define DWSDIO_CTRL_INTERNAL_DMA (1 << DWSDIO_CTRL_BIT_INTERNAL_DMA) - -/* Register CMD field CMD_INDEX */ -#define DWSDIO_CMD_BIT_CMD_INDEX 0 -#define DWSDIO_CMD_MASK_CMD_INDEX 0x0000003FU - -/* Register CMD field RESPONSE_EXPECT */ -#define DWSDIO_CMD_BIT_RESP_EXP 6 -#define DWSDIO_CMD_RESP_EXP (1 << DWSDIO_CMD_BIT_RESP_EXP) - -/* Register CMD field RESPONSE_LENGTH */ -#define DWSDIO_CMD_BIT_RESP_LENGTH 7 -#define DWSDIO_CMD_RESP_LENGTH (1 << DWSDIO_CMD_BIT_RESP_LENGTH) - -/* Register CMD field CHECK_RESPONSE_CRC */ -#define DWSDIO_CMD_BIT_CHECK_CRC 8 -#define DWSDIO_CMD_CHECK_CRC (1 << DWSDIO_CMD_BIT_CHECK_CRC) - -/* Register CMD field DATA_EXPECTED */ -#define DWSDIO_CMD_BIT_DATA_EXP 9 -#define DWSDIO_CMD_DATA_EXP (1 << DWSDIO_CMD_BIT_DATA_EXP) - -/* Register CMD field READ-WRITE */ -#define DWSDIO_CMD_BIT_RW 10 -#define DWSDIO_CMD_RW (1 << DWSDIO_CMD_BIT_RW) - -/* Register CMD field TRANSFER_MODE */ -#define DWSDIO_CMD_BIT_XFER_MODE 11 -#define DWSDIO_CMD_XFER_MODE (1 << DWSDIO_CMD_BIT_XFER_MODE) - -/* Register CMD field SEND_AUTO_STOP */ -#define DWSDIO_CMD_BIT_AUTO_STOP 12 -#define DWSDIO_CMD_AUTO_STOP (1 << DWSDIO_CMD_BIT_AUTO_STOP) - -/* Register CMD field WAIT_PRVDATA_COMPLETE */ -#define DWSDIO_CMD_BIT_PRV_DAT_WAIT 13 -#define DWSDIO_CMD_PRV_DAT_WAIT (1 << DWSDIO_CMD_BIT_PRV_DAT_WAIT) - -/* Register CMD field STOP_ABORT_CMD */ -#define DWSDIO_CMD_BIT_ABORT_STOP 14 -#define DWSDIO_CMD_ABORT_STOP (1 << DWSDIO_CMD_BIT_ABORT_STOP) - -/* Register CMD field SEND_INITIALIZATION */ -#define DWSDIO_CMD_BIT_SEND_INIT 15 -#define DWSDIO_CMD_SEND_INIT (1 << DWSDIO_CMD_BIT_SEND_INIT) - -/* Register CMD field CARD_NUMBER */ -#define DWSDIO_CMD_BIT_CARD_NO 16 -#define DWSDIO_CMD_MASK_CARD_NO 0x001F0000U - -/* Register CMD field UPDATE_CLOCK_REGISTERS_ONLY */ -#define DWSDIO_CMD_BIT_BIT_UPD_CLK 21 -#define DWSDIO_CMD_UPD_CLK (1 << DWSDIO_CMD_BIT_BIT_UPD_CLK) - -/* Register CMD field READ_CEATA_DEVICE */ -#define DWSDIO_CMD_BIT_READ_CEATA_DEVICE 22 -#define DWSDIO_CMD_READ_CEATA_DEVICE (1 << DWSDIO_CMD_BIT_READ_CEATA_DEVICE) - -/* Register CMD field CCS_EXPECTED */ -#define DWSDIO_CMD_BIT_CCS_EXP 23 -#define DWSDIO_CMD_CCS_EXP (1 << DWSDIO_CMD_BIT_CCS_EXP) - -/* Register CMD field ENABLE_BOOT */ -#define DWSDIO_CMD_BIT_ENABLE_BOOT 24 -#define DWSDIO_CMD_ENABLE_BOOT (1 << DWSDIO_CMD_BIT_ENABLE_BOOT) - -/* Register CMD field EXPECT_BOOT_ACK */ -#define DWSDIO_CMD_BIT_BOOT_ACK_EXP 25 -#define DWSDIO_CMD_BOOT_ACK_EXP (1 << DWSDIO_CMD_BIT_BOOT_ACK_EXP) - -/* Register CMD field DISABLE_BOOT */ -#define DWSDIO_CMD_BIT_DISABLE_BOOT 25 -#define DWSDIO_CMD_DISBALE_BOOT (1 << DWSDIO_CMD_BIT_DISABLE_BOOT) - -/* Register CMD field BOOT_MODE */ -#define DWSDIO_CMD_BIT_BOOT_MODE 27 -#define DWSDIO_CMD_BOOT_MODE (1 << DWSDIO_CMD_BIT_BOOT_MODE) - -/* Register CMD field VOLT_SWITCH */ -#define DWSDIO_CMD_BIT_VOLT_SWITCH 28 -#define DWSDIO_CMD_VOLT_SWITCH (1 << DWSDIO_CMD_BIT_VOLT_SWITCH) - -/* Register CMD field USE_HOLD_REG */ -#define DWSDIO_CMD_BIT_USE_HOLD_REG 29 -#define DWSDIO_CMD_USE_HOLD_REG (1 << DWSDIO_CMD_BIT_USE_HOLD_REG) - -/* Register CMD field START_CMD */ -#define DWSDIO_CMD_BIT_START 31 -#define DWSDIO_CMD_START (1 << DWSDIO_CMD_BIT_START) - -/* Register UHS_REG_EXT */ -#define DWSDIO_UHS_REG_EXT_MASK_REFCLK (0xC0000000) -#define DWSDIO_UHS_REG_EXT_BIT_REFCLK 30 - -#define DWSDIO_UHS_REG_EXT_MASK_CLKDRIVE (0x01800000) -#define DWSDIO_UHS_REG_EXT_BIT_CLKDRIVE 23 - -#define DWSDIO_UHX_REG_EXT_MASK_CLKSAMPLE (0x007f0000) -#define DWSDIO_UHX_REG_EXT_BIT_CLKSAMPLE 16 - -#define DWSDIO_STATUS_BIT_FIFO (17) -#define DWSDIO_STATUS_FIFO_FULL (0x8) -#define DWSDIO_STATUS_FIFO_EMPTY (0x4) -#define DWSDIO_STATUS_MASK_FIFO (0x3ffe0000) - -/* status bit */ -#define DWSDIO_STATUS_DATA_BUSY (1 << 9) - -#define DWSDIO_FIFOTH_BIT_RX_WMARK 16 -#define DWSDIO_FIFOTH_MASK_RX_WMARK (0xfff << DWSDIO_FIFOTH_BIT_RX_WMARK) -#define DWSDIO_FIFOTH_BIT_TX_WMARK 0 -#define DWSDIO_FIFOTH_MASK_TX_WMARK (0xfff) -#define DWSDIO_FIFOTH_BIT_DMA_M_SIZE 28 -#define DWSDIO_FIFOTH_MASK_DMA_M_SIZE (0x7 << DWSDIO_FIFOTH_BIT_DMA_M_SIZE) -#define DWSDIO_FIFOTH_M_SIZE(x) ((x) << DWSDIO_FIFOTH_BIT_DMA_M_SIZE) -#define DWSDIO_FIFOTH_TX_WMASK(x) ((x)) -#define DWSDIO_FIFOTH_RX_WMASK(x) ((x) << DWSDIO_FIFOTH_BIT_RX_WMARK) - -/* interrupt status bit */ -#define DWSDIO_INT_CAD (0x1U) // Card Detected -#define DWSDIO_INT_RE (0x2U) // Response error -#define DWSDIO_INT_CD (0x4U) // Command Done -#define DWSDIO_INT_DTO (0x8U) // Data Transfer Over -#define DWSDIO_INT_TXDR (0x10U) // Transmit FiFo Data Request -#define DWSDIO_INT_RXDR (0x20U) // Receive Fifo Data request -#define DWSDIO_INT_RCRC (0x40U) // Response CRC error -#define DWSDIO_INT_DCRC (0x80U) // Data CRC error -#define DWSDIO_INT_RTO (0x100U) // Response Timeout -#define DWSDIO_INT_DRTO (0x200U) // Data read Timeout -#define DWSDIO_INT_HTO (0x400U) // Data starvation by Host timeout -#define DWSDIO_INT_FRUN (0x800U) // Fifo underrun / overrun error -#define DWSDIO_INT_HLE (0x1000U) // Hardware Locked write error -#define DWSDIO_INT_SBE (0x2000U) // Start bit error -#define DWSDIO_INT_ACD (0x4000U) // Auto Command Done -#define DWSDIO_INT_EBE (0x8000U) // End bit error -#define DWSDIO_INT_ALL (0xFFFF) -#define DWSDIO_INT_DATA_ERR (DWSDIO_INT_SBE | DWSDIO_INT_EBE | DWSDIO_INT_HLE | \ - DWSDIO_INT_FRUN | DWSDIO_INT_DCRC) -#define DWSDIO_INT_DATA_TMO (DWSDIO_INT_DRTO | DWSDIO_INT_HTO) - -#define DWSDIO_ENUMERATION_FREQ (400000) /* 400 Khz for card enumeration */ - -#endif /* H_DW_SDIO_HAL */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi.h deleted file mode 100644 index f048af9b..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi.h +++ /dev/null @@ -1,175 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_SPI -#define H_DW_SPI - -#include "device/ip_hal/dev_spi.h" -#include "arc/arc_exception.h" - -/** - * if this header file is included, - * will indicate that this designware spi device - * is used - */ -#define DEVICE_USE_DESIGNWARE_SPI - -#define DW_SPI_IN_FREE (0) /*!< Currently not in spi transfer */ -#define DW_SPI_IN_XFER (DEV_IN_TX | DEV_IN_RX | DEV_IN_XFER) /*!< Currently in spi transfer */ -#define DW_SPI_IN_TX (DEV_IN_TX | DEV_IN_XFER) /*!< Currently in spi tx */ -#define DW_SPI_IN_RX (DEV_IN_RX | DEV_IN_XFER) /*!< Currently in spi rx */ - -#define DW_SPI_GINT_DISABLED (0) /*!< designware interrupt disabled for control spi irq/fiq */ -#define DW_SPI_GINT_ENABLE (1 << 0) /*!< designware interrupt enabled for control spi irq/fiq */ - -#define DW_SPI_MASTER_SUPPORTED (0x1) /*!< Support Designware SPI Master Mode */ -#define DW_SPI_SLAVE_SUPPORTED (0x2) /*!< Support Designware SPI Slave Mode */ -/*!< Support Designware SPI Both Master and Slave Mode */ -#define DW_SPI_BOTH_SUPPORTED (DW_SPI_MASTER_SUPPORTED | DW_SPI_SLAVE_SUPPORTED) - -#define DW_SPI_INVALID_INTNO (DEV_INTNO_INVALID) - -/** - * detailed description of DesignWare SPI register information - */ -/** - * @brief Structure definitions for DesignWare SPI register - * @details Structure type for DesignWare SPI - * block register information, implementation - */ -typedef volatile struct { - /*!< Control Register */ - /*!< SPI Control Register 0 (0x0) */ - uint32_t CTRLR0; - /*!< SPI Control Register 1 (0x4) */ - uint32_t CTRLR1; - /*!< Enable Register */ - /*!< SPI Enable Register (0x8) */ - uint32_t SSIENR; - /*!< SPI Microwire Control Register (0xC) */ - uint32_t MWCR; - /*!< SPI Slave Enable Register (0x10) */ - uint32_t SER; - /*!< SPI Baud Rate Select Register (0x14) */ - uint32_t BAUDR; - /*!< TX and RX FIFO Control Register */ - /*!< SPI Transmit FIFO Threshold Level Register (0x18) */ - uint32_t TXFTLR; - /*!< SPI Receive FIFO Threshold Level Register (0x1C) */ - uint32_t RXFTLR; - /*!< SPI Transmit FIFO Level Register (0x20) */ - uint32_t TXFLR; - /*!< SPI Receive FIFO Level Register (0x24) */ - uint32_t RXFLR; - /*!< SPI Status Register (0x28) */ - uint32_t SR; - /*!< Interrupt Enable/Disable/Control Registers */ - /*!< SPI Interrupt Mask Register (0x2C) */ - uint32_t IMR; - /*!< SPI Interrupt Status Register (0x30) */ - uint32_t ISR; - /*!< SPI Raw Interrupt Status Register (0x34) */ - uint32_t RISR; - /*!< SPI Transmit FIFO Overflow Interrupt Clear Register (0x38) */ - uint32_t TXOICR; - /*!< SPI Receive FIFO Overflow Interrupt Clear Register (0x3C) */ - uint32_t RXOICR; - /*!< SPI Receive FIFO Underflow Interrupt Clear Register (0x40) */ - uint32_t RXUICR; - /*!< SPI Multi-Master Interrupt Clear Register (0x44) */ - uint32_t MSTICR; - /*!< SPI Interrupt Clear Register (0x48) */ - uint32_t ICR; - /*!< DMA Control Register (0x4C) */ - uint32_t DMACR; - /*!< DMA Transmit Data Level (0x50) */ - uint32_t DMATDLR; - /*!< DMA Receive Data Level (0x54) */ - uint32_t DMARDLR; - /*!< SPI Identification Register (0x58) */ - uint32_t IDR; - /*!< SPI CoreKit ID Register (Value after Reset : 0x3332322A) (0x5C) */ - uint32_t SSI_VER_ID; - /*!< Data Register */ - /*!< SPI DATA Register for both Read and Write (0x60) */ - uint32_t DATAREG; - /*!< More SPI DATA Register for both Read and Write (0x64-0xEC) */ - uint32_t DRS[35]; - /** 0xF0, RxD Sample Delay Register */ - uint32_t RX_SAMPLE_DLY; - /** 0xF4, SPI Control Register */ - uint32_t SPI_CTRLR0; -} DW_SPI_REG, *DW_SPI_REG_PTR; - -/** Designware SPI Message Transfer */ -typedef struct { - uint32_t xfer_len; - uint32_t tx_idx; - uint32_t rx_idx; - uint32_t nbytes; - DEV_SPI_TRANSFER *tx_xfer; - DEV_SPI_TRANSFER *rx_xfer; -} DW_SPI_TRANSFER, *DW_SPI_TRANSFER_PTR; - -/** - * @brief Structure definitions for DesignWare SPI control - * @details Structure type for DesignWare SPI implementation - */ -typedef struct { - DW_SPI_REG *dw_spi_regs; /*!< spi register */ - /* Variables which should be set during object implementation */ - uint32_t support_modes; /*!< supported spi modes */ - uint32_t intno; /*!< interrupt no */ - uint32_t dw_apb_bus_freq; /*!< spi ip apb bus frequency */ - uint32_t rx_sampledly; /*!< RxD Sample Delay */ - uint32_t tx_fifo_len; /*!< transmit fifo length */ - uint32_t rx_fifo_len; /*!< receive fifo length */ - INT_HANDLER_T dw_spi_int_handler; /*!< spi interrupt handler */ - /* Variables which always change during spi operation */ - uint32_t int_status; /*!< spi interrupt status */ - DW_SPI_TRANSFER dw_xfer; /*!< designware spi transfer */ -} DW_SPI_CTRL, *DW_SPI_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -extern int32_t dw_spi_open(DEV_SPI *spi_obj, uint32_t mode, uint32_t param); -extern int32_t dw_spi_close(DEV_SPI *spi_obj); -extern int32_t dw_spi_control(DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_spi_write(DEV_SPI *spi_obj, const void *data, uint32_t len); -extern int32_t dw_spi_read(DEV_SPI *spi_obj, void *data, uint32_t len); -extern void dw_spi_isr(DEV_SPI *spi_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -#endif /* H_DW_SPI */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi_hal.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi_hal.h deleted file mode 100644 index 86fdd468..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi_hal.h +++ /dev/null @@ -1,113 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_SPI_HAL -#define H_DW_SPI_HAL - -#include "device/designware/dw_spi_hal_cfg.h" - -/* DW APB SPI bit definitions */ - -/** - * DesignWare SPI hal ctrl0 macros, - * include dfs, scph, scppl, tmod, etc - */ -#define DW_SPI_CTRLR0_DFS_MASK (0xf) - -#define DW_SPI_CTRLR0_SC_OFS (6) -#define DW_SPI_CTRLR0_SC_MASK (0xC0) -#define DW_SPI_CTRLR0_SCPH_HIGH (0x40) -#define DW_SPI_CTRLR0_SCPH_LOW (0) -#define DW_SPI_CTRLR0_SCPOL_HIGH (0x80) -#define DW_SPI_CTRLR0_SCPOL_LOW (0) - -#define DW_SPI_CTRLR0_TMOD_MASK (0x300) -#define DW_SPI_TMOD_TRANSMIT_RECEIVE (0) -#define DW_SPI_TMOD_TRANSMIT_ONLY (0x100) -#define DW_SPI_TMOD_RECEIVE_ONLY (0x200) -#define DW_SPI_TMOD_EEPROM_READ_ONLY (0x300) - -#define DW_SPI_CTRLR0_FRF_MOTOROLA (0x0) -#define DW_SPI_CTRLR0_FRF_TI (0x10) -#define DW_SPI_CTRLR0_FRF_MICROWIRE (0x20) - -#define DW_SPI_CTRLR0_SLV_OE_DISABLE (1 << 10) -#define DW_SPI_CTRLR0_SLV_OE_ENABLE (0) - -/** - * DesignWare SPI hal Interrupt Status Flags - */ -#define DW_SPI_TX_OVERFLOW_ERROR (0x2) -#define DW_SPI_RX_UNDERFLOW_ERROR (0x4) -#define DW_SPI_RX_OVERFLOW_ERROR (0x8) - -#define DW_SPI_ISR_RX_FIFO_INT_MASK (0x10) -#define DW_SPI_ISR_TX_FIFO_INT_MASK (0x1) -#define DW_SPI_ISR_TX_OVERFLOW_INT_MASK (0x2) -#define DW_SPI_ISR_RX_UNDERFLOW_INT_MASK (0x4) -#define DW_SPI_ISR_RX_OVERFLOW_INT_MASK (0x8) - -/** - * DesignWare SPI hal Status Flags - */ -#define DW_SPI_SR_DCOL (0x40) -#define DW_SPI_SR_TXE (0x20) -#define DW_SPI_SR_RFF (0x10) -#define DW_SPI_SR_RFNE (0x8) -#define DW_SPI_SR_TFE (0x4) -#define DW_SPI_SR_TFNF (0x2) -#define DW_SPI_SR_BUSY (0x1) - -/** - * DesignWare SPI hal ssi enable macros - */ -/* Macros */ -#define DW_SPI_SSI_ENABLE (1) /*!< SSI Enable */ -#define DW_SPI_SSI_DISABLE (0) /*!< SSI Disable */ - -/** - * DesignWare SPI hal interrupt mask macros - */ -#define DW_SPI_IMR_MSTIM (0x20) /*!< Multi-Master Contention Interrupt Mask */ -#define DW_SPI_IMR_RXFIM (0x10) /*!< Receive FIFO Full Interrupt Mask */ -#define DW_SPI_IMR_RXOIM (0x08) /*!< Receive FIFO Overflow Interrupt Mask */ -#define DW_SPI_IMR_RXUIM (0x04) /*!< Receive FIFO Underflow Interrupt Mask */ -#define DW_SPI_IMR_TXOIM (0x02) /*!< Transmit FIFO Overflow Interrupt Mask */ -#define DW_SPI_IMR_TXEIM (0x01) /*!< Transmit FIFO Empty Interrupt Mask */ - -#define DW_SPI_IMR_XFER (DW_SPI_IMR_TXEIM | DW_SPI_IMR_RXFIM | DW_SPI_IMR_TXOIM | DW_SPI_IMR_RXOIM | DW_SPI_IMR_RXUIM) - -#define DW_SPI_SSI_IDLE (1) -#define DW_SPI_SPI_TRANSMIT (1) -#define DW_SPI_SPI_RECEIVE (2) -#define DW_SPI_SSI_MASTER (1) -#define DW_SPI_SSI_SLAVE (0) - -#endif /* H_DW_SPI_HAL */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi_hal_cfg.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi_hal_cfg.h deleted file mode 100644 index 2f136b99..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_spi_hal_cfg.h +++ /dev/null @@ -1,46 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_SPI_HAL_CFG -#define H_DW_SPI_HAL_CFG - -#ifndef DW_SPI_CALC_FIFO_LEN_ENABLE -#define DW_SPI_CALC_FIFO_LEN_ENABLE (1) /*!< Defaultly enable calculate fifo length */ -#endif - -#ifndef DW_SPI_MAX_FIFO_LENGTH -#define DW_SPI_MAX_FIFO_LENGTH (256) /*!< Max FIFO depth for designware SPI device */ -#endif - -#ifndef DW_SPI_MIN_FIFO_LENGTH -#define DW_SPI_MIN_FIFO_LENGTH (2) /*!< Min FIFO depth for designware SPI device */ -#endif - -#endif /* H_DW_SPI_HAL_CFG */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_trng.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_trng.h deleted file mode 100644 index f8e2c35d..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_trng.h +++ /dev/null @@ -1,94 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_DW_TRNG -#define H_DW_TRNG - -#include "device/ip_hal/dev_trng.h" -#include "arc/arc_exception.h" - -#ifndef TRNG_VERSION_NIST - -#define DW_TRNG_INVALID_INTNO (DEV_INTNO_INVALID) - -// DesignWare TRNG register structure -typedef volatile struct { - uint32_t CTRL; // (0x0) - uint32_t STAT; // (0x4) - uint32_t MODE; // (0x8) - uint32_t SMODE; // (0xC) - uint32_t IE; // (0x10) - uint32_t ISTAT; // (0x14) - uint32_t COREKIT_REL; // (0x18) - uint32_t FEATURES; // (0x1C) - uint32_t RAND0; // (0x20) - uint32_t RAND1; // (0x24) - uint32_t RAND2; // (0x28) - uint32_t RAND3; // (0x2C) - uint32_t RAND4; // (0x30) - uint32_t RAND5; // (0x34) - uint32_t RAND6; // (0x38) - uint32_t RAND7; // (0x3C) - uint32_t SEED0; // (0x40) - uint32_t SEED1; // (0x44) - uint32_t SEED2; // (0x48) - uint32_t SEED3; // (0x4C) - uint32_t SEED4; // (0x50) - uint32_t SEED5; // (0x54) - uint32_t SEED6; // (0x58) - uint32_t SEED7; // (0x5C) - uint32_t AUTO_RQSTS; // (0x60) - uint32_t AUTO_AGE; // (0x64) - uint32_t BUILD_CONFIG; // (0x68) -} DW_TRNG_REG, *DW_TRNG_REG_PTR; - -typedef struct { - DW_TRNG_REG_PTR dw_trng_regs; /*!< dw trng register */ - uint32_t intno; /*!< interrupt vector number */ - INT_HANDLER_T dw_trng_int_handler; /*!< interrupt handler */ - uint32_t int_status; /*!< interrupt status */ -} DW_TRNG_CTRL, *DW_TRNG_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -extern int32_t dw_trng_open(DEV_TRNG_PTR trng_obj); -extern int32_t dw_trng_close(DEV_TRNG_PTR trng_obj); -extern int32_t dw_trng_control(DEV_TRNG_PTR trng_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_trng_read(DEV_TRNG_PTR trng_obj, uint32_t *data_buf); -extern void dw_trng_isr(DEV_TRNG_PTR trng_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -#endif /* TRNG_VERSION_NIST */ - -#endif /* H_DW_TRNG */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_uart.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_uart.h deleted file mode 100644 index 2da045cf..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_uart.h +++ /dev/null @@ -1,122 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_UART -#define H_DW_UART - -#include "device/ip_hal/dev_uart.h" -#include "arc/arc_exception.h" - -/** - * if this header file is included, - * will indicate that this designware uart device - * is used - */ -#define DEVICE_USE_DESIGNWARE_UART - -/** - * contains definitions of DesignWare UART register structure. - */ -/** - * @brief Structure definitions for DesignWare UART register - * @details Structure type for DesignWare UART - * block register information, implementation - */ -typedef volatile struct { - uint32_t DATA; /*!< data in/out and DLL */ - uint32_t IER; /*!< Interrupt enable register and DLH */ - uint32_t IIR; /*!< Interrupt Id register and FCR */ - uint32_t LCR; /*!< Line control Register */ - uint32_t MCR; /*!< Modem control register */ - uint32_t LSR; /*!< Line Status Register */ - uint32_t MSR; /*!< Modem status Register */ - uint32_t SCRATCHPAD; /*!< Uart scratch pad register */ - uint32_t LPDLL; /*!< Low Power Divisor Latch (Low) Reg */ - uint32_t LPDLH; /*!< Low Power Divisor Latch (High) Reg */ - uint32_t RES1[2]; /*!< Reserved */ - uint32_t SHR[16]; /*!< Shadow data register(SRBR and STHR) */ - uint32_t FAR; /*!< FIFO Access register */ - uint32_t TFR; /*!< Transmit FIFO Read */ - uint32_t RFW; /*!< Receive FIFO write */ - uint32_t USR; /*!< UART status register */ - uint32_t TFL; /*!< Transmit FIFO level */ - uint32_t RFL; /*!< Receive FIFO level */ - uint32_t SRR; /*!< Software reset register */ - uint32_t SRTS; /*!< Shadow request to send */ - uint32_t SBCR; /*!< Shadow break control */ - uint32_t SDMAM; /*!< Shadow DMA mode */ - uint32_t SFE; /*!< Shadow FIFO enable */ - uint32_t SRT; /*!< Shadow RCVR Trigger */ - uint32_t STET; /*!< Shadow TX empty register */ - uint32_t HTX; /*!< Halt TX */ - uint32_t DMASA; /*!< DMA Software ACK */ - uint32_t RES2[18]; /*!< Reserved */ - uint32_t CPR; /*!< Camponent parameter register */ - uint32_t UCV; /*!< UART Component Version */ - uint32_t CTR; /*!< Component typw register */ -} DW_UART_REG, *DW_UART_REG_PTR; - -#define DW_UART_GINT_DISABLED (0) /*!< designware interrupt disabled for control uart irq/fiq */ -#define DW_UART_GINT_ENABLE (1 << 0) /*!< designware interrupt enabled for control uart irq/fiq */ -#define DW_UART_TXINT_ENABLE (1 << 1) /*!< designware interrupt enabled for control transmit process */ -#define DW_UART_RXINT_ENABLE (1 << 2) /*!< designware interrupt enabled for control transmit process */ - -#define DW_UART_INVALID_INTNO (DEV_INTNO_INVALID) - -/** - * @brief Structure definitions for DesignWare UART control structure - * @details Structure type for DesignWare UART implementation - */ -typedef struct { - uint32_t dw_uart_regbase; /*!< uart ip register base */ - uint32_t dw_apb_bus_freq; /*!< uart ip apb bus frequency */ - uint32_t intno; /*!< uart interrupt vector number */ - INT_HANDLER_T dw_uart_int_handler; /*!< uart interrupt handler */ - uint32_t tx_fifo_len; /*!< transmit fifo length, set by user in object implementation */ - uint32_t rx_fifo_len; /*!< receive fifo length, set by user in object implementation */ - uint32_t int_status; /*!< interrupt status for designware uart */ -} DW_UART_CTRL, *DW_UART_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -extern int32_t dw_uart_open(DEV_UART *uart_obj, uint32_t baud); -extern int32_t dw_uart_close(DEV_UART *uart_obj); -extern int32_t dw_uart_control(DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_uart_write(DEV_UART *uart_obj, const void *data, uint32_t len); -extern int32_t dw_uart_read(DEV_UART *uart_obj, void *data, uint32_t len); -extern void dw_uart_isr(DEV_UART *uart_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -#endif /* H_DW_UART */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_uart_hal.h b/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_uart_hal.h deleted file mode 100644 index e7826432..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/designware/dw_uart_hal.h +++ /dev/null @@ -1,203 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -#ifndef H_DW_UART_HAL -#define H_DW_UART_HAL - -/* DW APB UART bit definitions */ - -/** - * DesignWare UART hal IER related macros - */ -/* IER */ -#define DW_UART_IER_DATA_AVAIL (0x01) -#define DW_UART_IER_XMIT_EMPTY (0x02) -#define DW_UART_IER_LINE_STATUS (0x04) -#define DW_UART_IER_MDM_STATUS (0x08) -#define DW_UART_IER_PTIME (0x80) - -/** - * DesignWare UART hal IIR related macros - */ -/* IIR */ -/* IIR READ */ -#define DW_UART_IIR_IP (0x01) -#define DW_UART_IIR_MASK (0x0E) -#define DW_UART_IIR_READ_FIFO_ENABLE (0xC0) - -/* Possible interrupt IIR_MASK values */ -#define DW_UART_IIR_MDM_STATUS (0x00) -#define DW_UART_IIR_XMIT_EMPTY (0x02) -#define DW_UART_IIR_DATA_AVAIL (0x04) -#define DW_UART_IIR_LINE_STATUS (0x06) -#define DW_UART_IIR_RX_TIMEOUT (0x0C) -#define DW_UART_IIR_INT_ID_MASK (0x0f) - -/* IIR WRITE */ -#define DW_UART_IIR_FIFO_ENABLE (0x01) -#define DW_UART_IIR_RCVR_FIFO_RESET (0x02) -#define DW_UART_IIR_XMIT_FIFO_RESET (0x04) -#define DW_UART_IIR_DMA_MODE_SELECT (0x08) -#define DW_UART_IIR_RCV_TRIGGER_MASK (0xC0) - -/* Values for IIR receive trigger */ -#define DW_UART_IIR_TRIGGER_LEVEL_1_CHAR (0x00) -#define DW_UART_IIR_TRIGGER_LEVEL_1_4_FULL (0x40) -#define DW_UART_IIR_TRIGGER_LEVEL_1_2_FULL (0x80) -#define DW_UART_IIR_TRIGGER_LEVEL_2_LESS_FULL (0xC0) - -/** - * DesignWare UART hal LCR related macros - */ -/* LCR */ -#define DW_UART_LCR_WORD_LEN_MASK (0x03) -#define DW_UART_LCR_STOP_BIT_MASK (0x04) -#define DW_UART_LCR_PARITY_MASK (0x38) -#define DW_UART_LCR_DPS_MASK (0x3F) -#define DW_UART_LCR_STICK_PARITY (0x20) -#define DW_UART_LCR_BREAK (0x40) -#define DW_UART_LCR_DLAB (0x80) - -/* Word length values */ -#define DW_UART_LCR_WORD_LEN5 (0x00) -#define DW_UART_LCR_WORD_LEN6 (0x01) -#define DW_UART_LCR_WORD_LEN7 (0x02) -#define DW_UART_LCR_WORD_LEN8 (0x03) - -/* stop bit values */ -#define DW_UART_LCR_1_STOP_BIT (0x00) -#define DW_UART_LCR_1D5_STOP_BIT (0x04) -#define DW_UART_LCR_2_STOP_BIT (0x04) - -/* Parity bit values */ -#define DW_UART_LCR_PARITY_NONE (0x00) -#define DW_UART_LCR_PARITY_ODD (0x08) -#define DW_UART_LCR_PARITY_EVEN (0x18) -#define DW_UART_LCR_PARITY_MARK (0x28) -#define DW_UART_LCR_PARITY_SPACE (0x38) - -/** - * DesignWare UART hal MCR related macros - */ -/* MCR */ -#define DW_UART_MCR_DTR (0x01) -#define DW_UART_MCR_RTS (0x02) -#define DW_UART_MCR_LOOPBACK (0x10) -#define DW_UART_MCR_AFCE (0x20) -#define DW_UART_MCR_SIRE (0x40) - -/** - * DesignWare UART hal LSR related macros - */ -/* LSR */ -#define DW_UART_LSR_DR (0x01) -#define DW_UART_LSR_OVERRUN (0x02) -#define DW_UART_LSR_PARITYERR (0x04) -#define DW_UART_LSR_FRAMEERR (0x08) -#define DW_UART_LSR_BREAKRCVD (0x10) -#define DW_UART_LSR_TXD_EMPTY (0x20) -#define DW_UART_LSR_TX_STATUS (0x40) -#define DW_UART_LSR_RX_FIFOERR (0x80) - -/** - * DesignWare UART hal MSR related macros - */ -/* MSR */ -#define DW_UART_MSR_DCTS (0x01) -#define DW_UART_MSR_DDSR (0x02) -#define DW_UART_MSR_TERI (0x04) -#define DW_UART_MSR_DDCD (0x08) -#define DW_UART_MSR_CTS (0x10) -#define DW_UART_MSR_DSR (0x20) -#define DW_UART_MSR_RIC (0x40) -#define DW_UART_MSR_DCD (0x80) - -/** - * DesignWare UART hal FCR related macros - */ -/* FCR */ -#define DW_UART_FCR_FEN (0x01) -#define DW_UART_FCR_RFR (0x02) -#define DW_UART_FCR_TFR (0x04) -#define DW_UART_FCR_DMS (0x08) -#define DW_UART_FCR_RTL (0xC0) - -/** - * DesignWare UART hal USR related macros - */ -/* USR */ -#define DW_UART_USR_BUSY (0x01) -#define DW_UART_USR_TFNF (0x02) -#define DW_UART_USR_TFE (0x04) -#define DW_UART_USR_RFNE (0x08) -#define DW_UART_USR_RFF (0x10) - -/** - * DesignWare UART hal SFE related macros - */ -/* SFE */ -#define DW_UART_SFE_SHADOW_FIFO_ENABLE (0x01) - -/** - * DesignWare UART hal SRR related macros - */ -/* SRR */ -#define DW_UART_SRR_UR (0x01) -#define DW_UART_SRR_RFR (0x02) -#define DW_UART_SRR_XFR (0x04) - -/** - * DesignWare UART hal SRT related macros - */ -/* SRT */ -#define DW_UART_SRT_TRIGGER_LEVEL_1_CHAR (0x00) -#define DW_UART_SRT_TRIGGER_LEVEL_1_4_FULL (0x01) -#define DW_UART_SRT_TRIGGER_LEVEL_1_2_FULL (0x02) -#define DW_UART_SRT_TRIGGER_LEVEL_2_LESS_FULL (0x03) - -/** - * DesignWare UART hal STET related macros - */ -/* STET*/ -#define DW_UART_STET_FIFO_EMPTY (0x00) -#define DW_UART_STET_2_CHARS_IN_FIFO (0x01) -#define DW_UART_STET_1_4_FULL (0x02) -#define DW_UART_STET_1_2_FULL (0x03) - -/** - * DesignWare UART hal CPR related macros - */ -/* CPR*/ -#define DW_UART_CPR_FIFO_STAT (1 << 10) -#define DW_UART_CPR_FIFO_MODE_OFS (16) -#define DW_UART_CPR_FIFO_MODE_MASK (0xFF) -#define DW_UART_CPR_FIFO_MODE (0xFF0000) - -#endif /* H_DW_UART_HAL */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/dev_common.h b/platform/vendor_bsp/embarc_bsp/include/device/dev_common.h deleted file mode 100644 index 51afc197..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/dev_common.h +++ /dev/null @@ -1,176 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @defgroup DEVICE_HAL_COMMON Common Device Layer Definitions - * @ingroup DEVICE_HAL_DEF - * @brief Common definitions for device layer (@ref dev_common.h) - * - * @{ - * - * @file - * @brief Header file to define common definitions for device layer - * @details Here in this file provide definitions that need by other - * devices in device layer - */ - -#ifndef H_DEV_COMMON -#define H_DEV_COMMON - -#include "embARC_toolchain.h" - -/** - * @defgroup DEVICE_HAL_COMMON_DEVSTATE Common Device State - * @ingroup DEVICE_HAL_COMMON - * @brief Definitions for device state - * @details Common types and macro definitions for device open/close, - * device working good/error, used in @ref DEVICE_HAL_UART, @ref DEVICE_HAL_SPI, - * @ref DEVICE_HAL_IIC, @ref DEVICE_HAL_GPIO - * @{ - */ -/* - * macros for device open and close state - */ -#define DEV_CLOSED (0) /*!< Indicate that device was closed */ -#define DEV_OPENED (1) /*!< Indicate that the device was opened */ - -/* - * macros for device good and error state - */ -#define DEV_GOOD (0) /*!< Indicate device is good */ -#define DEV_ERROR (1) /*!< Indicate device error */ -/** @} */ - -/** - * @defgroup DEVICE_HAL_COMMON_DEVMTHD Common Device Working Method - * @ingroup DEVICE_HAL_COMMON - * @brief Definitions for device working method(interrupt or poll) - * @details Common macro definitions for working method, - * interrupt or poll method,used in @ref DEVICE_HAL_UART, @ref DEVICE_HAL_SPI, - * @ref DEVICE_HAL_IIC, @ref DEVICE_HAL_GPIO - * @{ - */ -/* - * macros for device working method - */ -#define DEV_POLL_METHOD (0) /*!< Indicate that the device running in poll method */ -#define DEV_INTERRUPT_METHOD (1) /*!< Indicate that the device running in interrupt method */ -/** @} */ - -/** - * @defgroup DEVICE_HAL_COMMON_DEVMODE Common Device Working Mode - * @ingroup DEVICE_HAL_COMMON - * @brief Definitions for device working mode(master or slave) - * @details Common macro definitions for working mode, Master or Slave mode, - * used in @ref DEVICE_HAL_IIC, @ref DEVICE_HAL_SPI. - * @{ - */ -/* - * macros for device working mode - */ -#define DEV_MASTER_MODE (0) /*!< Indicate that the device working as master */ -#define DEV_SLAVE_MODE (1) /*!< Indicate that the device working as slave */ -/** @} */ - -/** - * @defgroup DEVICE_HAL_COMMON_DEVSTATUS Common Device Status - * @ingroup DEVICE_HAL_COMMON - * @brief Definitions for device status, 1 bit for 1 function - * @{ - */ -#define DEV_DISABLED (0) /*!< Bit 0 for device enabled state, disabled */ -#define DEV_ENABLED (1 << 0) /*!< Bit 0 for device enabled state, enabled */ -#define DEV_IN_TX (1 << 1) /*!< Bit 1 for device in transmit state */ -#define DEV_IN_RX (1 << 2) /*!< Bit 2 for device in receive state */ -#define DEV_IN_XFER (1 << 3) /*!< Bit 3 for device in transfer state */ -#define DEV_IN_TX_ABRT (1 << 4) /*!< Bit 4 for device in transmit abort state */ -#define DEV_IN_RX_ABRT (1 << 5) /*!< Bit 5 for device in receive abort state */ -#define DEV_IN_XFER_ABRT (1 << 6) /*!< Bit 6 for device in transfer abort state */ -/** @} */ - -/** - * Invalid Interrupt Vector Number - * When interrupt number is set to this value, - * all interrupt related function in the device - * driver source code shouldn't be called, - * that means the interrupt processing maybe done - * in outside of device driver, maybe done in the device - * object instantiation - */ -#define DEV_INTNO_INVALID (0xFFFFFFFF) - -/** - * @defgroup DEVICE_HAL_COMMON_DEFCMD Common Device Defining Command - * @ingroup DEVICE_HAL_COMMON - * @brief Definitions for defining command code - * @details Common macro definitions to define command code, - * in system code, use @ref DEV_SET_SYSCMD to define command code. - * in user code, use @ref DEV_SET_USRCMD to define command code. - * So that there will be no conflicts in system and user defined command code. - * this used used in @ref DEVICE_HAL_UART, @ref DEVICE_HAL_SPI, - * @ref DEVICE_HAL_IIC, @ref DEVICE_HAL_GPIO, and in user code - * @{ - */ -/* - * macros for control command base - */ -#define DEV_SYS_CMDBSE (0x00000000) /*!< default system device control command base(defined by embARC) */ -#define DEV_USR_CMDBSE (0x80000000) /*!< default user device control command base(defined by user) in user implementing */ -#define DEV_SET_SYSCMD(cmd) (DEV_SYS_CMDBSE | (cmd)) /*!< set device system control command */ -#define DEV_SET_USRCMD(cmd) (DEV_USR_CMDBSE | (cmd)) /*!< set device user control command */ - -#define CONV2VOID(param) ((void *)(param)) /*!< convert param into void * type */ -/** @} */ - -/** - * Common Device Buffer Structure - */ -typedef struct { - void *buf; /*!< buffer pointer */ - uint32_t len; /*!< buffer length in bytes */ - uint32_t ofs; /*!< current offset in buffer */ -} DEV_BUFFER; - -/** Init device buffer */ -#define DEV_BUFFER_INIT(devbuf, buffer, size) { \ - (devbuf)->buf = (void *)(buffer); \ - (devbuf)->len = (uint32_t)(size); \ - (devbuf)->ofs = (uint32_t)(0); \ -} - -/** - * Device callback function typedef. - * This is usually used in device callback settings, - * and @b ptr should be the device object pointer, - * such as DEV_IIC * */ -typedef void (*DEV_CALLBACK) (void *ptr); - -/** @} */ -#endif /* H_DEV_COMMON */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/dev_pinmux.h b/platform/vendor_bsp/embarc_bsp/include/device/dev_pinmux.h deleted file mode 100644 index 09417c1a..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/dev_pinmux.h +++ /dev/null @@ -1,124 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_DEV_PINMUX -#define H_DEV_PINMUX - -#include "embARC_toolchain.h" - -#define IO_PINMUX_ENABLE 1 -#define IO_PINMUX_DISABLE 0 - -typedef enum { - ARDUINO_PIN_0 = 0, - ARDUINO_PIN_1, - ARDUINO_PIN_2, - ARDUINO_PIN_3, - ARDUINO_PIN_4, - ARDUINO_PIN_5, - ARDUINO_PIN_6, - ARDUINO_PIN_7, - ARDUINO_PIN_8, - ARDUINO_PIN_9, - ARDUINO_PIN_10, - ARDUINO_PIN_11, - ARDUINO_PIN_12, - ARDUINO_PIN_13, - ARDUINO_PIN_AD0, - ARDUINO_PIN_AD1, - ARDUINO_PIN_AD2, - ARDUINO_PIN_AD3, - ARDUINO_PIN_AD4, - ARDUINO_PIN_AD5, - ARDUINO_PIN_NONE -} ARDUINO_PIN; - -typedef enum { - PMOD_0 = 0, - PMOD_1, - PMOD_2, - PMOD_3, - PMOD_4, - PMOD_5, - PMOD_6, - PMOD_A = 0, - PMOD_B, - PMOD_C, - PMOD_D, - PMOD_E, - PMOD_NUM_NONE, -} PMOD_PORT; - -typedef enum { - PMOD_GPIO = 0, - PMOD_UART, - PMOD_SPI, - PMOD_I2C, - PMOD_PWM_MODE1, - PMOD_PWM_MODE2, - PMOD_PWM_MODE3, - PMOD_NONE -} PMOD_TYPE; - -typedef enum { - ARDUINO_GPIO = 0, - ARDUINO_UART, - ARDUINO_SPI, - ARDUINO_I2C, - ARDUINO_PWM, - ARDUINO_ADC, - ARDUINO_NONE -} ARDUINO_TYPE; - -typedef enum { - PINMUX_TYPE_DEFAULT = 0, - PINMUX_TYPE_ARDUINO, - PINMUX_TYPE_PMOD, - PINMUX_TYPE_MIKRO, - PINMUX_TYPE_NONE -} PINMUX_TYPE; - -#ifdef __cplusplus -extern "C" { -#endif - -extern void io_mux_init(void); -extern int32_t io_pmod_config(uint32_t pmod, uint32_t type, uint32_t config); -extern int32_t io_mikro_config(uint32_t config); -extern int32_t io_arduino_config(uint32_t pin_num, uint32_t type, uint32_t config); - -extern int32_t io_arduino_config_spi(uint32_t config); -extern int32_t io_arduino_config_uart(uint32_t config); -extern int32_t io_arduino_config_i2c(uint32_t config); - -#ifdef __cplusplus -} -#endif - -#endif /* H_DEV_PINMUX */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_gpio.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_gpio.h deleted file mode 100644 index a014203a..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_gpio.h +++ /dev/null @@ -1,498 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @defgroup DEVICE_HAL_GPIO GPIO Device HAL Interface - * @ingroup DEVICE_HAL_DEF - * @brief Definitions for gpio device hardware layer (@ref dev_gpio.h) - * @details Provide interfaces for gpio driver to implement - * - * @{ - * - * @file - * @brief Definitions for gpio device hardware layer - * @details Provide common definitions for gpio device, - * then the software developer can develop gpio driver - * following these definitions, and the applications - * can directly call this definition to realize functions - * - */ - -#ifndef H_DEV_GPIO -#define H_DEV_GPIO - -#include "device/dev_common.h" - -/** - * @defgroup DEVICE_HAL_GPIO_DEFDIR GPIO Port Direction Definition - * @ingroup DEVICE_HAL_GPIO - * @brief Macros definitions for gpio port - * @{ - */ -/* - * defines for gpio directions - */ -#define GPIO_DIR_INPUT (0) /*!< gpio works as input */ -#define GPIO_DIR_OUTPUT (1) /*!< gpio works as output */ -/** @} */ - -/** - * @defgroup DEVICE_HAL_GPIO_PINDEF GPIO Pin definitions - * @ingroup DEVICE_HAL_GPIO - * @brief Macros definitions for gpio pins - * @{ - */ -/** Macro to define a gpio pin, start from 0 */ -#define DEV_GPIO_PIN_DEF(pin) ((pin) & 0xFFFF) -/** gpio pin defintions */ -typedef enum { - DEV_GPIO_PIN_0 = 0, /*!< GPIO Pin 0 */ - DEV_GPIO_PIN_1, /*!< GPIO Pin 1 */ - DEV_GPIO_PIN_2, /*!< GPIO Pin 2 */ - DEV_GPIO_PIN_3, /*!< GPIO Pin 3 */ - DEV_GPIO_PIN_4, /*!< GPIO Pin 4 */ - DEV_GPIO_PIN_5, /*!< GPIO Pin 5 */ - DEV_GPIO_PIN_6, /*!< GPIO Pin 6 */ - DEV_GPIO_PIN_7, /*!< GPIO Pin 7 */ - DEV_GPIO_PIN_8, /*!< GPIO Pin 8 */ - DEV_GPIO_PIN_9, /*!< GPIO Pin 9 */ - DEV_GPIO_PIN_10, /*!< GPIO Pin 10 */ - DEV_GPIO_PIN_11, /*!< GPIO Pin 11 */ - DEV_GPIO_PIN_12, /*!< GPIO Pin 12 */ - DEV_GPIO_PIN_13, /*!< GPIO Pin 13 */ - DEV_GPIO_PIN_14, /*!< GPIO Pin 14 */ - DEV_GPIO_PIN_15, /*!< GPIO Pin 15 */ - DEV_GPIO_PIN_16, /*!< GPIO Pin 16 */ - DEV_GPIO_PIN_17, /*!< GPIO Pin 17 */ - DEV_GPIO_PIN_18, /*!< GPIO Pin 18 */ - DEV_GPIO_PIN_19, /*!< GPIO Pin 19 */ - DEV_GPIO_PIN_20, /*!< GPIO Pin 20 */ - DEV_GPIO_PIN_21, /*!< GPIO Pin 21 */ - DEV_GPIO_PIN_22, /*!< GPIO Pin 22 */ - DEV_GPIO_PIN_23, /*!< GPIO Pin 23 */ - DEV_GPIO_PIN_24, /*!< GPIO Pin 24 */ - DEV_GPIO_PIN_25, /*!< GPIO Pin 25 */ - DEV_GPIO_PIN_26, /*!< GPIO Pin 26 */ - DEV_GPIO_PIN_27, /*!< GPIO Pin 27 */ - DEV_GPIO_PIN_28, /*!< GPIO Pin 28 */ - DEV_GPIO_PIN_29, /*!< GPIO Pin 29 */ - DEV_GPIO_PIN_30, /*!< GPIO Pin 30 */ - DEV_GPIO_PIN_31, /*!< GPIO Pin 31 */ - DEV_GPIO_PIN_NC = 0xFFFFFFFF /*!< GPIO Pin Not Connected */ -} DEV_GPIO_PIN; - -/** Macro to define a gpio port, start from 0 */ -#define DEV_GPIO_PORT_DEF(port) ((port) & 0xFFFF) -/** Macro to define a gpio port-pin(such as P0.0 or PA.0, start from 0 */ -#define DEV_GPIO_PORT_PIN_DEF(port, pin) (((port) << 16) | ((pin) & 0xFFFF)) - -/** gpio port defintions */ -typedef enum { - DEV_GPIO_PORT_0 = 0, /*!< GPIO Port 0 */ - DEV_GPIO_PORT_1, /*!< GPIO Port 1 */ - DEV_GPIO_PORT_2, /*!< GPIO Port 2 */ - DEV_GPIO_PORT_3, /*!< GPIO Port 3 */ - DEV_GPIO_PORT_4, /*!< GPIO Port 4 */ - DEV_GPIO_PORT_5, /*!< GPIO Port 5 */ - DEV_GPIO_PORT_6, /*!< GPIO Port 6 */ - DEV_GPIO_PORT_7, /*!< GPIO Port 7 */ - DEV_GPIO_PORT_8, /*!< GPIO Port 8 */ - DEV_GPIO_PORT_9, /*!< GPIO Port 9 */ - DEV_GPIO_PORT_10, /*!< GPIO Port 10 */ - DEV_GPIO_PORT_A = 0, /*!< GPIO Port A */ - DEV_GPIO_PORT_B = 1, /*!< GPIO Port B */ - DEV_GPIO_PORT_C = 2, /*!< GPIO Port C */ - DEV_GPIO_PORT_D = 3, /*!< GPIO Port D */ - DEV_GPIO_PORT_E = 4, /*!< GPIO Port E */ - DEV_GPIO_PORT_F = 5, /*!< GPIO Port F */ - DEV_GPIO_PORT_G = 6, /*!< GPIO Port G */ - DEV_GPIO_PORT_H = 7, /*!< GPIO Port H */ - DEV_GPIO_PORT_I = 8, /*!< GPIO Port I */ - DEV_GPIO_PORT_J = 9, /*!< GPIO Port J */ - DEV_GPIO_PORT_K = 10, /*!< GPIO Port K */ - DEV_GPIO_PORT_NC = 0xFFFFFFFF /*!< GPIO Port Not Connected */ -} DEV_GPIO_PORT; -/** @} */ - -/** - * @defgroup DEVICE_HAL_GPIO_CTRLCMD GPIO Device Control Commands - * @ingroup DEVICE_HAL_GPIO - * @brief Definitions for gpio control command, used in @ref DEV_GPIO::gpio_control "GPIO IO Control" - * @details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - @ref E_OK, Control device successfully - * - @ref E_CLSED, Device is not opened - * - @ref E_OBJ, Device object is not valid or not exists - * - @ref E_PAR, Parameter is not valid for current control command - * - @ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - @ref E_NOSPT, Control command is not supported or not valid - * @{ - */ -/** - * Set the @ref DEV_GPIO_INFO::direction "direction" of masked bits of gpio port into @ref GPIO_DIR_INPUT "input" - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_DIR_INPUT DEV_SET_SYSCMD(0) -/** - * Set the @ref DEV_GPIO_INFO::direction "direction" of masked bits of gpio port into @ref GPIO_DIR_OUTPUT "output" - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_DIR_OUTPUT DEV_SET_SYSCMD(1) -/** - * Get @ref DEV_GPIO_INFO::direction "gpio port direction". - * - Param type : uint32_t - * - Param usage : 1 bit for 1 bit of gpio port, 0 for input, 1 for output - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_DIR DEV_SET_SYSCMD(2) -/** - * Set gpio interrupt configuration for each bit. - * - Param type : @ref DEV_GPIO_INT_CFG * - * - Param usage : store gpio interrupt configuration for each bit. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_INT_CFG DEV_SET_SYSCMD(3) -/** - * Get gpio interrupt configuration for each bit. - * - Param type : @ref DEV_GPIO_INT_CFG * - * - Param usage : First set int_bit_mask in DEV_GPIO_INT_CFG structure to - * the mask of which bit of GPIO you want to get. And the interrupt configuration - * will be stored in the structure DEV_GPIO_INT_CFG, each bit stand for each bit of port. - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_INT_CFG DEV_SET_SYSCMD(4) -/** - * Set gpio service routine for each bit. - * - Param type : @ref DEV_GPIO_BIT_ISR * - * - Param usage : store gpio handler information for each bit, int handler's param will be DEV_GPIO *. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_ISR DEV_SET_SYSCMD(5) -/** - * Get gpio service routine for each bit. - * - Param type : @ref DEV_GPIO_BIT_ISR * - * - Param usage : By passing int_bit_ofs in DEV_GPIO_BIT_ISR, - * it will return interrupt handler for this bit and store it in int_bit_handler. - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_ISR DEV_SET_SYSCMD(6) -/** - * Enable gpio interrupt of the masked bits. - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_ENA_BIT_INT DEV_SET_SYSCMD(7) -/** - * Disable gpio interrupt of the masked bits. - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_DIS_BIT_INT DEV_SET_SYSCMD(8) -/** - * Get @ref DEV_GPIO_INFO::method "gpio interrupt enable status". - * - Param type : uint32_t * - * - Param usage : 1 bit for 1 bit of gpio port, 0 for poll, 1 for interrupt - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_MTHD DEV_SET_SYSCMD(9) -/** - * Toggle GPIO output of the masked bits(pins). - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_TOGGLE_BITS DEV_SET_SYSCMD(10) -/** @} */ - -/** - * @defgroup DEVICE_HAL_GPIO_INT_CFG_SET GPIO Device Int Configuration Settings - * @ingroup DEVICE_HAL_GPIO - * @brief Structure and macro definitions for gpio interrupt - * @{ - */ - -/* GPIO Mask Defintions */ -/** Mask none bits of the max 32bits */ -#define GPIO_BITS_MASK_NONE (0) -/** Mask all bits of the max 32bits */ -#define GPIO_BITS_MASK_ALL (0XFFFFFFFF) - -/* GPIO Interrupt Type Related Definitions */ - -/** Level sensitive interrupt type for 1 bit */ -#define GPIO_INT_LEVEL_TRIG (0) -/** Edge sensitive interrupt type for 1 bit */ -#define GPIO_INT_EDGE_TRIG (1) -/** Level sensitive interrupt type for all 32 bits */ -#define GPIO_INT_LEVEL_TRIG_ALL (0) -/** Edge sensitive interrupt type for all 32 bits */ -#define GPIO_INT_EDGE_TRIG_ALL (0XFFFFFFFF) - -/* For bit settings */ -/** Set bit interrupt type of gpio into level sensitive */ -#define GPIO_INT_BIT_LEVEL_TRIG(bit_ofs) (GPIO_INT_LEVEL_TRIG << (bit_ofs)) -/** Set bit interrupt type of gpio into edge sensitive */ -#define GPIO_INT_BIT_EDGE_TRIG(bit_ofs) (GPIO_INT_EDGE_TRIG << (bit_ofs)) -/* For bits settings */ -/** Set interrupt type of masked bits of gpio into level sensitive */ -#define GPIO_INT_BITS_LEVEL_TRIG(bit_mask) (GPIO_INT_LEVEL_TRIG_ALL & (bit_mask)) -/** Set bit interrupt type of gpio into edge sensitive */ -#define GPIO_INT_BITS_EDGE_TRIG(bit_mask) (GPIO_INT_EDGE_TRIG_ALL & (bit_mask)) - -/* GPIO Interrupt Polarity Related Definitions */ - -/** GPIO Interrupt polarity type enum */ -typedef enum gpio_int_polarity { - /* Polarity for 1 bit */ - GPIO_INT_ACTIVE_LOW = 0, /*!< Active low for level-sensitive interrupt for 1 bit */ - GPIO_INT_FALLING_EDGE = 0, /*!< Falling-edge for edge-sensitive interrupt for 1 bit */ - GPIO_INT_ACTIVE_HIGH = 1, /*!< Active high for level-sensitive interrupt for 1 bit */ - GPIO_INT_RISING_EDGE = 1, /*!< Rising-edge for edge-sensitive interrupt for 1 bit */ - /* Polartiy for all 32 bits */ - GPIO_INT_ACTIVE_LOW_ALL = 0, /*!< Active low for level-sensitive interrupt for all bits */ - GPIO_INT_FALLING_EDGE_ALL = 0, /*!< Falling-edge for edge-sensitive interrupt for all bits */ - GPIO_INT_ACTIVE_HIGH_ALL = 0XFFFFFFFF, /*!< Active high for level-sensitive interrupt for all bits */ - GPIO_INT_RISING_EDGE_ALL = 0XFFFFFFFF /*!< Rising-edge for edge-sensitive interrupt for all bits */ -} GPIO_INT_POLARITY; - -/* For bit settings */ -/** Set bit polarity of gpio into active low */ -#define GPIO_INT_BIT_POL_ACT_LOW(bit_ofs) (GPIO_INT_ACTIVE_LOW << (bit_ofs)) -/** Set bit polarity of gpio into active high */ -#define GPIO_INT_BIT_POL_ACT_HIGH(bit_ofs) (GPIO_INT_ACTIVE_HIGH << (bit_ofs)) -/** Set bit polarity of gpio into falling edge */ -#define GPIO_INT_BIT_POL_FALL_EDGE(bit_ofs) (GPIO_INT_FALLING_EDGE << (bit_ofs)) -/** Set bit polarity of gpio into rising edge */ -#define GPIO_INT_BIT_POL_RISE_EDGE(bit_ofs) (GPIO_INT_RISING_EDGE << (bit_ofs)) - -/* For bits settings */ -/** Set polarity of masked bits of gpio into active low */ -#define GPIO_INT_BITS_POL_ACT_LOW(bit_mask) (GPIO_INT_ACTIVE_LOW_ALL & (bit_mask)) -/** Set polarity of masked bits of gpio into active high */ -#define GPIO_INT_BITS_POL_ACT_HIGH(bit_mask) (GPIO_INT_ACTIVE_HIGH_ALL & (bit_mask)) -/** Set polarity of masked bits of gpio into falling edge */ -#define GPIO_INT_BITS_POL_FALL_EDGE(bit_mask) (GPIO_INT_FALLING_EDGE_ALL & (bit_mask)) -/** Set polarity of masked bits of gpio into rising edge */ -#define GPIO_INT_BITS_POL_RISE_EDGE(bit_mask) (GPIO_INT_RISING_EDGE_ALL & (bit_mask)) - -/* GPIO Interrupt Debounce Related Definitions */ - -/* For bit settings */ -/** Disable debounce circuitry for 1 bit */ -#define GPIO_INT_NO_DEBOUNCE (0) -/** Enable debounce circuitry for 1 bit */ -#define GPIO_INT_DEBOUNCE (1) - -/* For bits settings */ -/** Disable debounce circuitry for all bits */ -#define GPIO_INT_NO_DEBOUNCE_ALL (0) -/** Enable debounce circuitry for all bits */ -#define GPIO_INT_DEBOUNCE_ALL (0XFFFFFFFF) - -/* For bit settings */ -/** Set bit interrupt debounce of gpio into enabled */ -#define GPIO_INT_BIT_ENA_DEBOUNCE(bit_ofs) (GPIO_INT_DEBOUNCE << (bit_ofs)) -/** Set bit interrupt debounce of gpio into disabled */ -#define GPIO_INT_BIT_DIS_DEBOUNCE(bit_ofs) (GPIO_INT_NO_DEBOUNCE << (bit_ofs)) -/* For bits settings */ -/** Set bit interrupt debounce of gpio into enabled */ -#define GPIO_INT_BITS_ENA_DEBOUNCE(bit_mask) (GPIO_INT_DEBOUNCE_ALL & (bit_mask)) -/** Set bit interrupt debounce of gpio into disabled */ -#define GPIO_INT_BITS_DIS_DEBOUNCE(bit_mask) (GPIO_INT_NO_DEBOUNCE_ALL & (bit_mask)) - -/** GPIO interrupt configuration */ -typedef struct { - uint32_t int_bit_mask; /*!< interrupt bit mask for gpio */ - uint32_t int_bit_type; /*!< @ref GPIO_INT_LEVEL_TRIG "level sensitive" or @ref GPIO_INT_EDGE_TRIG "edge sensitive" for each gpio bit */ - uint32_t int_bit_polarity; /*!< active high or low, refer to @ref GPIO_INT_POLARITY for each gpio bit */ - uint32_t int_bit_debounce; /*!< @ref GPIO_INT_DEBOUNCE "enable" or @ref GPIO_INT_NO_DEBOUNCE "disable" debounce logic for each gpio bit */ -} DEV_GPIO_INT_CFG, *DEV_GPIO_INT_CFG_PTR; - -/** Default interrupt configuration for all gpio bits */ -static const DEV_GPIO_INT_CFG gpio_int_cfg_default = \ -{ GPIO_BITS_MASK_ALL, GPIO_INT_LEVEL_TRIG_ALL, \ - GPIO_INT_ACTIVE_LOW_ALL, GPIO_INT_NO_DEBOUNCE_ALL }; - -/** GPIO interrupt handler or Interrupt Service Routine(ISR) */ -typedef void (*DEV_GPIO_HANDLER) (void *ptr); - -/** interrupt handler for each port bit */ -typedef struct { - uint32_t int_bit_ofs; /*!< int bit offset */ - DEV_GPIO_HANDLER int_bit_handler; /*!< interrupt handler */ -} DEV_GPIO_BIT_ISR, *DEV_GPIO_BIT_ISR_PTR; -/** @} */ - -/** - * @defgroup DEVICE_HAL_GPIO_DEVSTRUCT GPIO Device Interface Definition - * @ingroup DEVICE_HAL_GPIO - * @brief Structure and macro definitions for gpio device structure - * @details This structure will be used in user implemented code, which was called - * @ref DEVICE_IMPL "Device Driver Implement Layer" for gpio to use in implementation code. - * Application developer should use the GPIO API provided here to access to GPIO devices. - * BSP developer should follow the API definition to implement GPIO device drivers. - * @{ - */ -/** - * @brief Gpio information struct definition - * @details Informations about gpio open count, working status - * gpio registers and control block, gpio io direction and interrupt/poll for each bit of gpio - * @note Only available for gpio with max 32bits - */ -typedef struct { - void *gpio_ctrl; /*!< gpio control related pointer, implemented by bsp developer, and this should be set during gpio object implementation */ - uint32_t opn_cnt; /*!< gpio open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t direction; /*!< each bit direction of this GPIO, default all @ref GPIO_DIR_INPUT "input" for first open */ - uint32_t method; /*!< int/poll method for each bit of GPIO, 0 for poll, 1 for interrupt, default all @ref DEV_POLL_METHOD "poll" for first open */ - uint32_t bitofs; /*!< current in response interrupt pin offset */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can @ref DEV_GPIO_INFO_SET_EXTRA_OBJECT "set" - or \ref DEV_GPIO_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_GPIO_INFO, *DEV_GPIO_INFO_PTR; -/** Set extra information pointer of gpio info */ -#define DEV_GPIO_INFO_SET_EXTRA_OBJECT(gpio_info_ptr, extra_info) (gpio_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of gpio info */ -#define DEV_GPIO_INFO_GET_EXTRA_OBJECT(gpio_info_ptr) ((gpio_info_ptr)->extra) - -/** Method of all gpio bits set to poll */ -#define DEV_GPIO_BITS_MTHD_POLL (0) -/** Method of all gpio bits set to interrupt */ -#define DEV_GPIO_BITS_MTHD_INTERRUPT (0xFFFFFFFF) -/** Default method of all gpio bits should be poll for first open */ -#define DEV_GPIO_BITS_MTHD_DEFAULT (DEV_GPIO_BITS_MTHD_POLL) - -/** - * @brief Definitions for gpio device interface - * @details Define gpio device interface, like gpio information structure, - * fuctions to open/close/control gpio, write or read data via gpio - * @note All this details are implemented by user in user porting code - */ -typedef struct { - DEV_GPIO_INFO gpio_info; /*!< gpio device information */ - int32_t (*gpio_open)(uint32_t dir); /*!< open gpio device with pre-defined gpio direction */ - int32_t (*gpio_close)(void); /*!< close gpio device */ - int32_t (*gpio_control)(uint32_t ctrl_cmd, void *param); /*!< control gpio device */ - int32_t (*gpio_write)(uint32_t val, uint32_t mask); /*!< write gpio device with val, only write the masked bits */ - int32_t (*gpio_read)(uint32_t *val, uint32_t mask); /*!< read gpio device val, only read the masked bits */ -} DEV_GPIO, *DEV_GPIO_PTR; - -/** - * @fn int32_t *DEV_GPIO::gpio_open(uint32_t dir) - * @details Open a gpio device with pre-defined io direction. - * @param[in] dir Gpio direction for each bit - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_GPIO_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ - -/** - * @fn int32_t *DEV_GPIO::gpio_close(void) - * @details Close a gpio device, just decrease the @ref DEV_GPIO_INFO::opn_cnt "opn_cnt", - * if @ref DEV_GPIO_INFO::opn_cnt "opn_cnt" equals 0, then close the device - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_GPIO_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ - -/** - * @fn int32_t *DEV_GPIO::gpio_control(uint32_t ctrl_cmd, void *param) - * @details Control an gpio device by ctrl_cmd, with passed param. - * you can control gpio device using predefined gpio control commands defined using @ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as @ref GPIO_CMD_SET_BIT_DIR_INPUT - * "change masked gpio direction to input", and @ref DEVICE_HAL_GPIO_CTRLCMD "more". - * And you can also control gpio device using your own specified commands defined using @ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own gpio device driver implementation. - * @param[in] ctrl_cmd @ref DEVICE_HAL_GPIO_CTRLCMD "control command", to change or get some thing related to gpio - * @param[in,out] param Parameters that maybe argument of the command, or return values of the command - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid, such as interrupt is not supported - */ - -/** - * @fn int32_t *DEV_GPIO::gpio_write(uint32_t val, uint32_t mask) - * @details Write gpio with val, and only change the masked bits of gpio. - * @param[in] val Data that need to write to gpio - * @param[in] mask gpio bit mask - * @retval E_OK Write gpio successfully without any issues - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - */ - -/** - * @fn int32_t *DEV_GPIO::gpio_read(uint32_t *val, uint32_t mask) - * @details Read the masked gpio value - * @param[out] val Pointer to data need to read from gpio - * @param[in] mask GPIO bit mask - * @retval E_OK Read gpio data successfully without any issues - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - */ - -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get an @ref DEV_GPIO "gpio device" by gpio device id. - * For how to use gpio device hal refer to @ref DEV_GPIO "Functions in gpio device structure" - * @param[in] gpio_id ID of gpio, defined by user - * @retval !NULL Pointer to an @ref DEV_GPIO "gpio device structure" - * @retval NULL Failed to find the gpio device by gpio_id - * \note Need to implemented in user code - */ -extern DEV_GPIO_PTR gpio_get_dev(int32_t gpio_id); - -#ifdef __cplusplus -} -#endif - - -#endif /* H_DEV_GPIO */ -/** @} */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_i2s.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_i2s.h deleted file mode 100644 index 94f2bb32..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_i2s.h +++ /dev/null @@ -1,465 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @defgroup DEVICE_HAL_I2S I2S Device HAL Interface - * @ingroup DEVICE_HAL_DEF - * @brief Definitions for I2S device hardware layer (@ref dev_i2s.h) - * @details Provide unified APIs for I2S driver to implement. - * - * @{ - * - * @file - * @brief Definitions for I2S device hardware layer - * @details Provide common definitions for I2S device, - * then software developer can develop I2S driver - * following this definitions, and the applications - * can directly call this definition to realize functions - * - */ - -#ifndef H_DEV_I2S -#define H_DEV_I2S - -#include "device/dev_common.h" - -/** - * @defgroup DEVICE_HAL_I2S_CFG I2S Related Configurations - * @ingroup DEVICE_HAL_I2S - * @brief Type and macro definitions for I2S device - * @{ - */ - -/** - * @defgroup I2S_AUD_DATA_RES I2S Audio Data Resolution - * @ingroup DEVICE_HAL_I2S_CFG - * @brief Definitions for I2S audio data resolution - * @{ - */ -typedef enum { - I2S_AUD_DATA_NA = 0, /*!< N/A data resolution */ - I2S_AUD_DATA_12B = 1, /*!< 12 bits audio data resolution */ - I2S_AUD_DATA_16B = 2, /*!< 16 bits audio data resolution */ - I2S_AUD_DATA_20B = 3, /*!< 20 bits audio data resolution */ - I2S_AUD_DATA_24B = 4, /*!< 24 bits audio data resolution */ - I2S_AUD_DATA_32B = 5 /*!< 32 bits audio data resolution */ -} I2S_AUD_DATA_RES; -/** @} */ - -/** - * @defgroup I2S_AUD_SAMPLE_RATE I2S Audio Sampling Rate - * @ingroup DEVICE_HAL_I2S_CFG - * @brief Definitions for I2S audio sampling rate - * @{ - */ -typedef enum { - I2S_AUD_SR_NA = 0, /*!< N/A audio sample rate */ - I2S_AUD_SR_16K = 1, /*!< 16KHz audio sample rate */ - I2S_AUD_SR_32K = 2, /*!< 32KHz audio sample rate */ - I2S_AUD_SR_44_1K = 3, /*!< 44.1KHz audio sample rate */ - I2S_AUD_SR_48K = 4, /*!< 48KHz audio sample rate */ - I2S_AUD_SR_96K = 5, /*!< 96KHz audio sample rate */ - I2S_AUD_SR_192K = 6 /*!< 192KHz audio sample rate */ -} I2S_AUD_SAMPLE_RATE; -/** @} */ - -/** - * @defgroup I2S_DEVICE_TYPE I2S Device Type - * @ingroup DEVICE_HAL_I2S_CFG - * @brief Definitions for I2S device type - * @{ - */ -typedef enum { - I2S_DEVICE_TRANSMITTER = 0, /*!< I2S TX device */ - I2S_DEVICE_RECEIVER = 1 /*!< I2S RX device */ -} I2S_DEVICE_TYPE; -/** @} */ - -/** - * @defgroup I2S_WORKING_STATE I2S Working State - * @ingroup DEVICE_HAL_I2S_CFG - * @brief Definitions for I2S working state - * @{ - */ -typedef enum { - I2S_FREE = 0, /*!< Currently in I2S device free state */ - I2S_IN_TX = 1, /*!< Currently in I2S master transmit state */ - I2S_IN_RX = 2 /*!< Currently in I2S master receive state */ -} I2S_WORKING_STATE; -/** @} */ - -/** - * @defgroup I2S_ERROR_STATE I2S Error State - * @ingroup DEVICE_HAL_I2S_CFG - * @brief Definitions for I2S error state - * @{ - */ -typedef enum { - I2S_ERR_NONE = 0, /*!< Currently in I2S device free state */ - I2S_ERR_RX_OVERRUN = 1, /*!< RX FIFO data overrun */ - I2S_ERR_TX_OVERRUN = 2, /*!< TX FIFO data overrun */ - I2S_ERR_UNDEF = 3 /*!< Undefined error cases */ -} I2S_ERROR_STATE; -/** @} */ - -/** @} */ - -/** - * @defgroup DEVICE_HAL_I2S_CTRLCMD I2S Device Control Commands - * @ingroup DEVICE_HAL_I2S - * @brief Definitions for I2S control command, used in @ref DEV_I2S::i2s_control "I2S Control" - * @details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - @ref E_OK, Control device successfully - * - @ref E_CLSED, Device is not opened - * - @ref E_OBJ, Device object is not valid or not exists - * - @ref E_PAR, Parameter is not valid for current control command - * - @ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - @ref E_CTX, Control device failed, due to different reasons like in transfer state - * - @ref E_NOSPT, Control command is not supported or not valid - * @{ - */ - -/** Define I2S control commands for common usage */ -#define DEV_SET_I2S_SYSCMD(cmd) DEV_SET_SYSCMD((cmd)) -/** Define I2S control commands for master usage */ -#define DEV_SET_I2S_MST_SYSCMD(cmd) DEV_SET_SYSCMD(0x00010000 | (cmd)) - -/* ++++ Common commands for SPI Device ++++ */ -/** - * Get @ref DEV_I2S_INFO::status "current device status" - * - Param type : uint32_t * - * - Param usage : store result of current status - * - Return value explanation : - */ -#define I2S_CMD_GET_STATUS DEV_SET_I2S_SYSCMD(0) -/** - * Set @ref DEV_I2S_CBS::tx_cb "I2S transmit success callback" function - * when all required bytes are transmitted for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transmit success callback function for I2S - * - Return value explanation : - */ -#define I2S_CMD_SET_TXCB DEV_SET_I2S_SYSCMD(1) -/** - * Set @ref DEV_I2S_CBS::rx_cb "I2S receive success callback" function - * when all required bytes are received for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : receive success callback function for I2S - * - Return value explanation : - */ -#define I2S_CMD_SET_RXCB DEV_SET_I2S_SYSCMD(2) -/** - * Set @ref DEV_I2S_CBS::err_cb "I2S transfer error callback" function - * when something error happened for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transfer error callback function for I2S - * - Return value explanation : - */ -#define I2S_CMD_SET_ERRCB DEV_SET_I2S_SYSCMD(3) -/** - * Enable or disable transmit interrupt - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define I2S_CMD_SET_TXINT DEV_SET_I2S_SYSCMD(4) -/** - * Enable or disable receive interrupt - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define I2S_CMD_SET_RXINT DEV_SET_I2S_SYSCMD(5) -/** - * Do a software reset for I2S device, it will stop current transfer, - * and clear error state and bring device to normal state, set next condition to STOP - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define I2S_CMD_RESET DEV_SET_I2S_SYSCMD(6) -/** - * Flush I2S device transmit buffer or fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define I2S_CMD_FLUSH_TX DEV_SET_I2S_SYSCMD(7) -/** - * Flush I2S device receive buffer or fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define I2S_CMD_FLUSH_RX DEV_SET_I2S_SYSCMD(8) -/** - * Enable I2S device - * - Param type : Device channel nummber - * - Param usage : Specified device channel number - * - Return value explanation : - */ -#define I2S_CMD_ENA_DEV DEV_SET_I2S_SYSCMD(9) -/** - * Disable I2S device, when device is disabled, - * only @ref I2S_CMD_ENA_DEV, @ref I2S_CMD_DIS_DEV, - * @ref I2S_CMD_GET_STATUS and @ref I2S_CMD_RESET - * commands can be executed, other commands will return @ref E_SYS - * - Param type : Device channel nummber - * - Param usage : Specified device channel number - * - Return value explanation : - */ -#define I2S_CMD_DIS_DEV DEV_SET_I2S_SYSCMD(10) -/** - * Set buffer for interrupt transmit, and it will set @ref DEV_I2S_INFO::tx_buf "tx_buf". - * - I2S transmitter command @n - * If setting TX buffer to NULL, when tx interrupt is enabled and entered into tx interrupt, - * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the - * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt - * and call tx callback function if available. - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL - * - Return value explanation : - */ -#define I2S_CMD_SET_TXINT_BUF DEV_SET_I2S_SYSCMD(11) -/** - * Set buffer for interrupt receive, and it will set @ref DEV_I2S_INFO::rx_buf "rx_buf" - * - I2S receiver command @n - * Similiar to @ref I2S_CMD_SET_TXINT_BUF - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL - * - Return value explanation : - */ -#define I2S_CMD_SET_RXINT_BUF DEV_SET_I2S_SYSCMD(12) - -/** - * Set buffer empty threshold in the TX FIFO, these bit program the empty trigger level in the TX FIFO - * - I2S transmitter command @n - * These command is used to set trigger level in the TX FIFO at which empty threshold reached flag/interrupt - * is generated. - * - Param type : uint32_t - * - Param usage : Specified trigger level value (16b) + channel (16b) - * - Return value explanation : - */ -#define I2S_CMD_SET_TXCHET_BUF DEV_SET_I2S_SYSCMD(13) - -/** - * Set buffer available data threshold in the TX FIFO, these bit program the trigger level in the RX FIFO - * - I2S receiver command @n - * These command is used to set trigger level in the RX FIFO at which received data available flag/interrupt - * is generated. - * - Param type : uint32_t - * - Param usage : Specified trigger level value (16b) + channel (16b) - * - Return value explanation : - */ -#define I2S_CMD_SET_RXCHDT_BUF DEV_SET_I2S_SYSCMD(14) - -/* ++++ Master only commands for I2S Device ++++ */ -/** - * Enable or disable clock for master - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define I2S_CMD_MST_SET_CLK DEV_SET_I2S_MST_SYSCMD(0) -/** - * Program the number of sclk cycles for word select line stays - * - Param type : uint32_t - * - Param usage : clock cycles - * - Return value explanation : - */ -#define I2S_CMD_MST_SET_WSS DEV_SET_I2S_MST_SYSCMD(1) -/** - * Program the number of gating of sclk cycles for word select line stays - * - Param type : uint32_t - * - Param usage : gating of sclk cycles - * - Return value explanation : - */ -#define I2S_CMD_MST_SET_SCLKG DEV_SET_I2S_MST_SYSCMD(2) - -/** @} */ - -/** - * @defgroup DEVICE_HAL_I2S_CALLBACK I2S Interrupt Callback Functions - * @ingroup DEVICE_HAL_I2S - * @brief Structure definition for I2S device callback - * @{ - */ -typedef struct { - DEV_CALLBACK tx_cb; /*!< I2S data transmit success required bytes callback */ - DEV_CALLBACK rx_cb; /*!< I2S data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< I2S error callback */ -} DEV_I2S_CBS, *DEV_I2S_CBS_PTR; -/** @} */ - -/** - * @defgroup DEVICE_HAL_I2S_DEVSTRUCT I2S Device Structure - * @ingroup DEVICE_HAL_I2S - * @brief Definitions for I2S device structure. - * @details This structure will be used in user implemented code, which was called - * Device Driver Implement Layer for I2S to realize in user code. - * @{ - */ -/** - * @brief I2S information struct definition - * @details Informations about I2S open state, working state, - * baurate, I2S registers, working method, interrupt number - */ -typedef struct { - void *i2s_ctrl; /*!< I2S control related pointer, implemented by BSP developer, and this should be set during i2s object implementation */ - void *i2s_config; /*!< I2S device configuration, implemented by BSP developer, and this shoud be set in object implementation */ - uint32_t opn_cnt; /*!< I2S open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t status; /*!< current working status, refer to @ref DEVICE_HAL_COMMON_DEVSTATUS, this should be @ref DEV_ENABLED for first open */ - uint32_t device; /*!< device type, refer to @ref I2S_DEVICE_TYPE, this should be set for object initialization */ - uint32_t mode; /*!< current working mode, which can be @ref DEV_MASTER_MODE "master mode" or @ref DEV_SLAVE_MODE "slave mode" */ - uint32_t cur_state; /*!< @ref I2S_WORKING_STATE "current working state for I2S device", this should be @ref I2S_FREE for first open */ - uint32_t err_state; /*!< @ref I2S_ERROR_STATE "current error state for I2S device", this should be @ref I2S_ERR_NONE for first open */ - DEV_BUFFER tx_buf; /*!< transmit buffer via interrupt, this should be all zero for first open */ - DEV_BUFFER rx_buf; /*!< receive buffer via interrupt, this should be all zero for first open */ - DEV_I2S_CBS i2s_cbs; /*!< I2S callbacks, for both master and slave mode, this should be all NULL for first open */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by BSP developer, - this should be NULL for first open and you can @ref DEV_I2S_INFO_SET_EXTRA_OBJECT "set" - or @ref DEV_I2S_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_I2S_INFO, *DEV_I2S_INFO_PTR; - -/** Set extra information pointer of I2S */ -#define DEV_I2S_INFO_SET_EXTRA_OBJECT(i2s_info_ptr, extra_info) (i2s_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of I2S */ -#define DEV_I2S_INFO_GET_EXTRA_OBJECT(i2s_info_ptr) ((i2s_info_ptr)->extra) - -/** - * @brief Definition for I2S device interface - * @details Define I2S device interface, like I2S information structure, - * fuctions to get I2S info, open/close/control I2S, send/receive data by I2S - * @note All this details are implemented by user in user porting code - */ -typedef struct { - DEV_I2S_INFO i2s_info; /*!< I2S device information */ - int32_t (*i2s_open)(uint32_t mode, uint32_t param); /*!< open I2S device in master/slave mode, \ - when in master mode, param stands for speed mode, \ - when in slave mode, param stands for slave address */ - int32_t (*i2s_close)(void); /*!< close I2S device */ - int32_t (*i2s_control)(uint32_t ctrl_cmd, void *param); /*!< control i2s device */ - int32_t (*i2s_write)(const void *data, uint32_t len); /*!< send data by i2s TX device (blocking method) */ - int32_t (*i2s_read)(void *data, uint32_t len); /*!< read data from i2s RX device (blocking method) */ -} DEV_I2S, *DEV_I2S_PTR; - -/** - * @fn int32_t *DEV_I2S::i2s_open(uint32_t mode, uint32_t param) - * @details Open an I2S device with selected mode (master or slave) with defined param - * @param[in] mode Working mode (@ref DEV_MASTER_MODE "master" or @ref DEV_SLAVE_MODE "slave") - * @param[in] param Device type (@ref I2S_DEVICE_TRANSMITTER "transmitter" OR @ref I2S_DEVICE_RECEIVER "receiver") - * @retval E_OK Open successfully without any issues - * @retval E_OPNED Device was opened before - * @retval E_OBJ Device object is not valid - * @retval E_SYS Device initialized parameters are different with parameters in IP - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ - -/** - * @fn int32_t *DEV_I2S::i2s_close(void) - * @details close an I2S device, just decrease the @ref DEV_I2S_INFO::opn_cnt "opn_cnt", - * if @ref DEV_I2S_INFO::opn_cnt "opn_cnt" equals 0, then close the device - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_I2S_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ - -/** - * @fn int32_t *DEV_I2S::i2s_control(uint32_t ctrl_cmd, void *param) - * @details Control an I2S device by ctrl_cmd, with passed param. - * you can control I2S device using predefined I2S control commands defined using @ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), @ref DEVICE_HAL_I2S_CTRLCMD "command details". - * And you can also control I2S device using your own specified commands defined using @ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own I2S device driver implementation. - * @param[in] ctrl_cmd @ref DEVICE_HAL_I2S_CTRLCMD "control command", to change or get some thing related to I2S - * @param[in,out] param Parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ - -/** - * @fn int32_t *DEV_I2S::i2s_write(const void *data, uint32_t len) - * @details Send data through I2S with defined len to RX device. - * @param[in] data Pointer to data need to send by I2S - * @param[in] len Length of data to be sent - * @retval > 0 Byte count that was successfully sent for poll method, - * it might can't send that much due to @ref DEV_I2S_INFO::err_state "different error state". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_CTX Device is still in transfer state - * @retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ - -/** - * @fn int32_t *DEV_I2S::i2s_read(void *data, uint32_t len) - * @details Receive data of defined len through I2S from TX device. - * @param[out] data Pointer to data need to received by I2S - * @param[in] len Length of data to be received - * @retval > 0 Byte count that was successfully received for poll method, - * it might can't send that much due to @ref DEV_I2S_INFO::err_state "different error state". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_CTX Device is still in transfer state - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get an @ref DEV_I2S "i2s device" by i2s device id. - * For how to use i2s device hal refer to @ref DEVICE_HAL_I2S_DEVSTRUCT "Functions in i2s device structure" - * @param[in] i2s_id ID of i2s, defined by user - * @retval !NULL Pointer to an @ref DEV_I2S "i2s device structure" - * @retval NULL Failed to find the i2s device by i2s_id - * @note Need to implemented by user in user code - */ -extern DEV_I2S_PTR i2s_get_dev(int32_t i2s_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* H_DEV_I2S */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_iic.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_iic.h deleted file mode 100644 index f4a88926..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_iic.h +++ /dev/null @@ -1,515 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @defgroup DEVICE_HAL_IIC IIC Device HAL Interface - * @ingroup DEVICE_HAL_DEF - * @brief Definitions for iic device hardware layer (@ref dev_iic.h) - * @details Provide interfaces for iic driver to implement - * - * @{ - * - * @file - * @brief Definitions for iic device hardware layer - * @details Provide common definitions for iic device, - * then software developer can develop iic driver - * following this definitions, and the applications - * can directly call this definition to realize functions - */ - -#ifndef H_DEV_IIC -#define H_DEV_IIC - -#include "device/dev_common.h" - -/** - * @defgroup DEVICE_HAL_IIC_CFG IIC Related Configurations - * @ingroup DEVICE_HAL_IIC - * @brief Macros definitions for for IIC device - * During IIC device during implementation, it is recommended that - * when user set iic speed to a speed maybe not supported in your - * iic device, device driver will set to a supported slower speed. - * @{ - */ -/** IIC Bus possible speed modes */ -typedef enum { - IIC_SPEED_STANDARD = 0, /*!< Bidirectional, Standard-mode (Sm), with a bit rate up to 100 kbit/s */ - IIC_SPEED_FAST = 1, /*!< Bidirectional, Fast-mode (Fm), with a bit rate up to 400 kbit/s */ - IIC_SPEED_FASTPLUS = 2, /*!< Bidirectional, Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s */ - IIC_SPEED_HIGH = 3, /*!< Bidirectional, High-speed mode (Hs-mode), with a bit rate up to 3.4 Mbit/s */ - IIC_SPEED_ULTRA = 4 /*!< Unidirectional(Write only), Ultra Fast-mode (UFm), with a bit rate up to 5 Mbit/s */ -} IIC_SPEED_MODE; - -/** IIC next Condition */ -typedef enum iic_next_condtion { - IIC_MODE_STOP = 0, /*!< Send a STOP condition after write/read operation */ - IIC_MODE_RESTART = 1 /*!< Send a RESTART condition after write/read operation */ -} IIC_NEXT_CONDTION; - -/** IIC Error State */ -typedef enum { - IIC_ERR_NONE = 0, /*!< Currently in iic device free state */ - IIC_ERR_LOST_BUS = 1, /*!< Master or slave lost bus during operation */ - IIC_ERR_ADDR_NOACK = 2, /*!< Slave address is sent but not addressed by any slave devices */ - IIC_ERR_DATA_NOACK = 3, /*!< Data in transfer is not acked when it should be acked */ - IIC_ERR_TIMEOUT = 4, /*!< Transfer timeout, no more data is received or sent */ - IIC_ERR_MSTSTOP = 5, /*!< Slave received a STOP condition from master device */ - IIC_ERR_UNDEF = 6 /*!< Undefined error cases */ -} IIC_ERROR_STATE; - -/** IIC Working State */ -typedef enum { - IIC_FREE = 0, /*!< Currently in iic device free state */ - IIC_IN_TX = 1, /*!< Currently in iic master transmit state */ - IIC_IN_RX = 2 /*!< Currently in iic master receive state */ -} IIC_WORKING_STATE; - -/** IIC Addressing Mode */ -typedef enum { - IIC_7BIT_ADDRESS = 0, /*!< Use 7bit address mode */ - IIC_10BIT_ADDRESS = 1 /*!< Use 10bit address mode */ -} IIC_ADDRESS_MODE; - -/** IIC Slave State */ -typedef enum { - IIC_SLAVE_STATE_FREE = 0, /*!< None state, in free */ - IIC_SLAVE_STATE_START = (1 << 1), /*!< Start or Restart condition, clear it when read */ - IIC_SLAVE_STATE_STOP = (1 << 2), /*!< Stop condition, clear it when read */ - IIC_SLAVE_STATE_RD_REQ = (1 << 3), /*!< Read request from master, this will trigger the slave transmit callback */ - IIC_SLAVE_STATE_RD_DONE = (1 << 4), /*!< Read request done from master, clear it when read */ - IIC_SLAVE_STATE_WR_REQ = (1 << 5), /*!< Write request from master, this will trigger the slave receive callback */ - IIC_SLAVE_STATE_GC_REQ = (1 << 6), /*!< General call request from master */ - IIC_SLAVE_STATE_ERROR = (1 << 7) /*!< Error, clear it when read */ -} IIC_SLAVE_STATE; - -/** 7bit IIC address mask */ -#define IIC_7BIT_ADDRESS_MASK (0x7F) -/** 10bit IIC address mask */ -#define IIC_10BIT_ADDRESS_MASK (0x3FF) -/** @} */ - -/** - * @defgroup DEVICE_HAL_IIC_CTRLCMD IIC Device Control Commands - * @ingroup DEVICE_HAL_IIC - * @brief Definitions for iic control command, used in @ref DEV_IIC::iic_control "IIC IO Control" - * @details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - @ref E_OK, Control device successfully - * - @ref E_CLSED, Device is not opened - * - @ref E_OBJ, Device object is not valid or not exists - * - @ref E_PAR, Parameter is not valid for current control command - * - @ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - @ref E_CTX, Control device failed, due to different reasons like in transfer state - * - @ref E_NOSPT, Control command is not supported or not valid - * @{ - */ - -/** Define IIC control commands for common usage */ -#define DEV_SET_IIC_SYSCMD(cmd) DEV_SET_SYSCMD((cmd)) -/** Define IIC control commands for master usage */ -#define DEV_SET_IIC_MST_SYSCMD(cmd) DEV_SET_SYSCMD(0x00004000 | (cmd)) -/** Define IIC control commands for slave usage */ -#define DEV_SET_IIC_SLV_SYSCMD(cmd) DEV_SET_SYSCMD(0x00008000 | (cmd)) - -/* ++++ Common commands for IIC Device ++++ */ -/** - * Get @ref DEV_IIC_INFO::status "current device status" - * - Param type : uint32_t * - * - Param usage : store result of current status - * - Return value explanation : - */ -#define IIC_CMD_GET_STATUS DEV_SET_IIC_SYSCMD(0) -/** - * Set @ref DEV_IIC_INFO::addr_mode "iic addressing mode". - * - Param type : uint32_t - * - Param usage : iic addressing mode, possible values can be found @ref IIC_ADDRESS_MODE "here" - * - Return value explanation : - */ -#define IIC_CMD_SET_ADDR_MODE DEV_SET_IIC_SYSCMD(1) -/** - * Set @ref DEV_IIC_CBS::tx_cb "iic transmit success callback" function - * when all required bytes are transmitted for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transmit success callback function for iic - * - Return value explanation : - */ -#define IIC_CMD_SET_TXCB DEV_SET_IIC_SYSCMD(2) -/** - * Set @ref DEV_IIC_CBS::rx_cb "iic receive success callback" function - * when all required bytes are received for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : receive success callback function for iic - * - Return value explanation : - */ -#define IIC_CMD_SET_RXCB DEV_SET_IIC_SYSCMD(3) -/** - * Set @ref DEV_IIC_CBS::err_cb "iic transfer error callback" function - * when something error happened for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transfer error callback function for iic - * - Return value explanation : - */ -#define IIC_CMD_SET_ERRCB DEV_SET_IIC_SYSCMD(4) -/** - * Set buffer for interrupt transmit, and it will set @ref DEV_IIC_INFO::tx_buf "tx_buf". - * - IIC master mode use case @n - * For master mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt, - * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the - * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt - * and call tx callback function if available. - * - IIC slave mode use case @n - * For slave mode, the tx buffer is not used, only tx callback function is used, and if tx callback is not set, - * then it will automatically disable the tx interrupt, if tx callback is set, it will call the tx callback function - * and you need to write or read in the tx callback function, to avoid meaningless waiting, you can use control command - * @ref IIC_CMD_GET_TXAVAIL to get how many bytes space existing in transmit fifo, and use iic_write to send the available - * bytes. - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL - * - Return value explanation : - */ -#define IIC_CMD_SET_TXINT_BUF DEV_SET_IIC_SYSCMD(5) -/** - * Set buffer for interrupt receive, and it will set @ref DEV_IIC_INFO::rx_buf "rx_buf" - * - IIC master mode use case @n - * Similar to @ref IIC_CMD_SET_TXINT_BUF - * - IIC slave mode use case @n - * Similiar to @ref IIC_CMD_SET_TXINT_BUF - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL - * - Return value explanation : - */ -#define IIC_CMD_SET_RXINT_BUF DEV_SET_IIC_SYSCMD(6) -/** - * Enable or disable transmit interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if tx interrupt is enabled, then rx interrupt can't be changed. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define IIC_CMD_SET_TXINT DEV_SET_IIC_SYSCMD(7) -/** - * Enable or disable receive interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if rx interrupt is enabled, then tx interrupt can't be changed. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define IIC_CMD_SET_RXINT DEV_SET_IIC_SYSCMD(8) -/** - * Abort current interrupt transmit operation if tx interrupt enabled, - * it will disable transmit interrupt, and set @ref DEV_IN_TX_ABRT - * in @ref DEV_IIC_INFO::status "status" variable, - * and call the transmit callback function, when tx callback is finished, - * it will clear @ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_ABORT_TX DEV_SET_IIC_SYSCMD(9) -/** - * Abort current interrupt receive operation if rx interrupt enabled, - * it will disable receive interrupt, and set @ref DEV_IN_TX_ABRT - * in @ref DEV_IIC_INFO::status "status" variable, - * and call the receive callback function, when rx callback is finished, - * it will clear @ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_ABORT_RX DEV_SET_IIC_SYSCMD(10) -/** - * Do a software reset for IIC device, it will stop current transfer, - * and clear error state and bring device to normal state, set next condition to STOP - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_RESET DEV_SET_IIC_SYSCMD(11) -/** - * Flush iic device transmit buffer or fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_FLUSH_TX DEV_SET_IIC_SYSCMD(12) -/** - * Flush iic device receive buffer or fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_FLUSH_RX DEV_SET_IIC_SYSCMD(13) -/** - * Enable iic device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define IIC_CMD_ENA_DEV DEV_SET_IIC_SYSCMD(14) -/** - * Disable iic device, when device is disabled, - * only @ref IIC_CMD_ENA_DEV, @ref IIC_CMD_DIS_DEV, - * @ref IIC_CMD_GET_STATUS and @ref IIC_CMD_RESET - * commands can be executed, other commands will return @ref E_SYS - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define IIC_CMD_DIS_DEV DEV_SET_IIC_SYSCMD(15) -/** - * Get how many bytes space in iic are available to transmit, - * this can be used in interrupt callback functions, - * cooperate with @ref DEV_IIC::iic_write "iic_write" API to realize non-blocked write - * - Param type : int32_t * - * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available - * - Return value explaination : - */ -#define IIC_CMD_GET_TXAVAIL DEV_SET_IIC_SYSCMD(16) -/** - * Get how many bytes in iic are available to receive, - * this can be used in interrupt callback functions, - * cooperate with @ref DEV_IIC::iic_read "iic_read" API to realize non-blocked read - * - Param type : int32_t * - * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define IIC_CMD_GET_RXAVAIL DEV_SET_IIC_SYSCMD(17) - -/* ++++ Master only commands for IIC Device ++++ */ -/** - * Set @ref DEV_IIC_INFO::speed_mode "iic speed mode". - * - Param type : uint32_t - * - Param usage : iic speed mode, possible values can be found @ref IIC_SPEED_MODE "here", - * and if passing mode is not supported, it will choose a lower supported speed mode - * - Return value explanation : - */ -#define IIC_CMD_MST_SET_SPEED_MODE DEV_SET_IIC_MST_SYSCMD(0) -/** - * Set next condition for following transmit or receive operation. - * For example, you can change next condition before iic_read or iic_write, - * then in iic_read/iic_write operation, it will send a STOP/RESTART condition - * after the last byte of this operation. For interrupt, this is similar. - * - Param type : uint32_t - * - Param usage : next condition can be @ref IIC_NEXT_CONDTION - * - Return value explanation : - */ -#define IIC_CMD_MST_SET_NEXT_COND DEV_SET_IIC_MST_SYSCMD(1) -/** - * Set target slave device address for selecting slave device - * - Param type : uint32_t - * - Param usage : target slave address value - * - Return value explanation : - */ -#define IIC_CMD_MST_SET_TAR_ADDR DEV_SET_IIC_MST_SYSCMD(2) - -/* ++++ Slave only commands for IIC Device ++++ */ -/** - * Set slave address when working as slave iic device - * - Param type : uint32_t - * - Param usage : slave address value - * - Return value explanation : - */ -#define IIC_CMD_SLV_SET_SLV_ADDR DEV_SET_IIC_SLV_SYSCMD(0) -/** - * Get @ref IIC_SLAVE_STATE "slave state" when working as slave iic device - * - Param type : uint32_t * - * - Param usage : slave state - * - Return value explanation : - */ -#define IIC_CMD_SLV_GET_SLV_STATE DEV_SET_IIC_SLV_SYSCMD(1) - -/** @} */ - -/** - * @defgroup DEVICE_HAL_IIC_CALLBACK IIC Interrupt callback functions - * @ingroup DEVICE_HAL_IIC - * @brief Structure definition for IIC device callback - * @{ - */ -typedef struct { - DEV_CALLBACK tx_cb; /*!< iic data transmit success required bytes callback */ - DEV_CALLBACK rx_cb; /*!< iic data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< iic error callback */ -} DEV_IIC_CBS, *DEV_IIC_CBS_PTR; -/** @} */ - -/** - * @defgroup DEVICE_HAL_IIC_DEVSTRUCT IIC Device Structure - * @ingroup DEVICE_HAL_IIC - * @brief Definitions for IIC device structure. - * @details This structure will be used in user implemented code, which was called - * Device Driver Implement Layer for iic to realize in user code. - * @{ - */ -/** - * @brief IIC information struct definition - * @details Informations about iic open state, working state, - * baurate, iic registers, working method, interrupt number - */ -typedef struct { - void *iic_ctrl; /*!< iic control related pointer, implemented by bsp developer, and this should be set during iic object implementation */ - uint32_t opn_cnt; /*!< iic open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t status; /*!< current working status, refer to @ref DEVICE_HAL_COMMON_DEVSTATUS, this should be @ref DEV_ENABLED for first open */ - uint32_t mode; /*!< current working mode, which can be @ref DEV_MASTER_MODE "master mode" or @ref DEV_SLAVE_MODE "slave mode" */ - uint32_t speed_mode; /*!< current working @ref IIC_SPEED_MODE "iic speed mode" */ - uint32_t cur_state; /*!< @ref IIC_WORKING_STATE "current working state for iic device", this should be @ref IIC_FREE for first open */ - uint32_t err_state; /*!< @ref IIC_ERROR_STATE "current error state for iic device", this should be @ref IIC_ERR_NONE for first open */ - uint32_t addr_mode; /*!< @ref IIC_ADDRESS_MODE "current addressing mode", this should be @ref IIC_7BIT_ADDRESS for first open */ - uint32_t slv_addr; /*!< slave address when working as slave iic device, this should be 0 for first open */ - uint32_t tar_addr; /*!< target slave device address when addressing that slave device, this should be 0 for first open */ - uint32_t next_cond; /*!< @ref IIC_NEXT_CONDTION "next condition for master transmit or receive", \ - possible values are STOP or RESTART, it should be STOP for first open */ - DEV_BUFFER tx_buf; /*!< transmit buffer via interrupt, this should be all zero for first open */ - DEV_BUFFER rx_buf; /*!< receive buffer via interrupt, this should be all zero for first open */ - DEV_IIC_CBS iic_cbs; /*!< iic callbacks, for both master and slave mode, this should be all NULL for first open */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can @ref DEV_IIC_INFO_SET_EXTRA_OBJECT "set" - or @ref DEV_IIC_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_IIC_INFO, *DEV_IIC_INFO_PTR; - -/** Set extra information pointer of iic info */ -#define DEV_IIC_INFO_SET_EXTRA_OBJECT(iic_info_ptr, extra_info) (iic_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of iic info */ -#define DEV_IIC_INFO_GET_EXTRA_OBJECT(iic_info_ptr) ((iic_info_ptr)->extra) - -/** - * @brief Definition for IIC device interface - * @details Define iic device interface, like iic information structure, - * fuctions to get iic info, open/close/control iic, send/receive data by iic - * @note All this details are implemented by user in user porting code - */ -typedef struct { - DEV_IIC_INFO iic_info; /*!< iic device information */ - int32_t (*iic_open)(uint32_t mode, uint32_t param); /*!< open iic device in master/slave mode, \ - when in master mode, param stands for speed mode, \ - when in slave mode, param stands for slave address */ - int32_t (*iic_close)(void); /*!< close iic device */ - int32_t (*iic_control)(uint32_t ctrl_cmd, void *param); /*!< control iic device */ - int32_t (*iic_write)(const void *data, uint32_t len); /*!< send data by iic device (blocking method) */ - int32_t (*iic_read)(void *data, uint32_t len); /*!< read data from iic device (blocking method) */ -} DEV_IIC, *DEV_IIC_PTR; - -/** - * @fn int32_t *DEV_IIC::iic_open(uint32_t mode, uint32_t param) - * @details Open an iic device with selected mode (master or slave) with defined param - * @param[in] mode Working mode (@ref DEV_MASTER_MODE "master" or @ref DEV_SLAVE_MODE "slave") - * @param[in] param When mode is @ref DEV_MASTER_MODE, param stands for @ref DEV_IIC_INFO::speed_mode "speed mode", - * when mode is @ref DEV_SLAVE_MODE, param stands for @ref DEV_IIC_INFO::slv_addr "slave device 7bit address" - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_IIC_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ - -/** - * @fn int32_t *DEV_IIC::iic_close(void) - * @details Close an iic device, just decrease the @ref DEV_IIC_INFO::opn_cnt "opn_cnt", - * if @ref DEV_IIC_INFO::opn_cnt "opn_cnt" equals 0, then close the device - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_IIC_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ - -/** - * @fn int32_t *DEV_IIC::iic_control(uint32_t ctrl_cmd, void *param) - * @details Control an iic device by ctrl_cmd, with passed param. - * you can control iic device using predefined iic control commands defined using @ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as @ref IIC_CMD_MST_SET_SPEED_MODE "set iic speed mode", - * @ref IIC_CMD_FLUSH_TX "flush tx" and @ref DEVICE_HAL_IIC_CTRLCMD "more". - * And you can also control iic device using your own specified commands defined using @ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own iic device driver implementation. - * @param[in] ctrl_cmd @ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic - * @param[in,out] param Parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ - -/** - * @fn int32_t *DEV_IIC::iic_write(const void *data, uint32_t len) - * @details Send data through iic with defined len to slave device which slave address is slv_addr. - * @param[in] data Pointer to data need to send by iic - * @param[in] len Length of data to be sent - * @retval >0 Byte count that was successfully sent for poll method, - * it might can't send that much due to @ref DEV_IIC_INFO::err_state "different error state". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_CTX Device is still in transfer state - * @retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ - -/** - * @fn int32_t *DEV_IIC::iic_read(void *data, uint32_t len) - * @details Receive data of defined len through iic from slave device which slave address is slv_addr. - * @param[out] data Pointer to data need to received by iic - * @param[in] len Length of data to be received - * @retval >0 Byte count that was successfully received for poll method, - * it might can't send that much due to @ref DEV_IIC_INFO::err_state "different error state". - * @retval E_OBJ Device object is not valid or not exists - * @retval E_CTX Device is still in transfer state - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get an @ref DEV_IIC "iic device" by iic device id. - * For how to use iic device hal refer to @ref DEVICE_HAL_IIC_DEVSTRUCT "Functions in iic device structure" - * @param[in] iic_id ID of iic, defined by user - * @retval !NULL Pointer to an @ref DEV_IIC "iic device structure" - * @retval NULL Failed to find the iic device by iic_id - * @note Need to implemented by user in user code - */ -extern DEV_IIC_PTR iic_get_dev(int32_t iic_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* H_DEV_IIC */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_pwm_timer.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_pwm_timer.h deleted file mode 100644 index 442074bd..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_pwm_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/** - * @defgroup DEVICE_HAL_PWM_TIMER PWM_TIMER Device HAL Interface - * @ingroup DEVICE_HAL_DEF - * @brief Definitions for pwm_timer device hardware layer (@ref dev_pwm_timer.h) - * @details Provide unified APIs for pwm_timer driver to implement. - * - * @{ - * - * @file - * @brief Definitions for pwm_timer device hardware layer - * @details Provide common definitions for pwm_timer device, - * then software developer can develop pwm_timer driver - * following this definitions, and the applications - * can directly call this definition to realize functions - * - */ - -#ifndef H_DEV_PWM_TIMER -#define H_DEV_PWM_TIMER - -#include "device/dev_common.h" - -/** - * @defgroup DEVICE_HAL_PWM_TIMER_CTRLCMD PWM_TIMER Device Control Commands - * @ingroup DEVICE_HAL_PWM_TIMER - * @brief Definitions for pwm_timer control command, used in @ref DEV_PWM_TIMER::pwm_timer_control "PWM_TIMER IO Control" - * @details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - @ref E_OK, Control device successfully - * - @ref E_CLSED, Device is not opened - * - @ref E_OBJ, Device object is not valid or not exists - * - @ref E_PAR, Parameter is not valid for current control command - * - @ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - @ref E_CTX, Control device failed, due to different reasons like in transfer state - * - @ref E_NOSPT, Control command is not supported or not valid - * @{ - */ - -#define PWM_TIMER_CMD_SET_CFG DEV_SET_SYSCMD(0) - -#define PWM_TIMER_CMD_GET_CFG DEV_SET_SYSCMD(1) - -#define PWM_TIMER_CMD_ENA_CH DEV_SET_SYSCMD(2) - -#define PWM_TIMER_CMD_DIS_CH DEV_SET_SYSCMD(3) - -#define PWM_TIMER_CMD_SET_ISR DEV_SET_SYSCMD(4) - -#define PWM_TIMER_CMD_GET_ISR DEV_SET_SYSCMD(5) - -#define PWM_TIMER_CMD_DIS_ISR DEV_SET_SYSCMD(6) - -#define PWM_TIMER_CMD_ENA_ISR DEV_SET_SYSCMD(7) - -/** @} */ - -/** PWM_TIMER interrupt handler or Interrupt Service Routine(ISR) */ -typedef void (*DEV_PWM_TIMER_HANDLER) (void *ptr); - -/** interrupt handler for each pwm_timer channel */ -typedef struct { - uint32_t int_ch_num; /*!< pwm_timer channel num*/ - DEV_PWM_TIMER_HANDLER int_ch_handler; /*!< interrupt handler */ -} DEV_PWM_TIMER_CH_ISR, *DEV_PWM_TIMER_CH_ISR_PTR; - -/** - * PWM_TIMER Device Work Mode Types Enum - */ -typedef enum { - DEV_PWM_TIMER_MODE_CLOSE = 0, /*!< mode close */ - DEV_PWM_TIMER_MODE_TIMER = 1, /*!< mode timer */ - DEV_PWM_TIMER_MODE_PWM = 2 /*!< mode pwm */ -} DEV_PWM_TIMER_MODE, *DEV_PWM_TIMER_MODE_PTR; - -/** - * PWM_TIMER Device Config Struct - */ -typedef struct { - DEV_PWM_TIMER_MODE mode; /*!< work mode*/ - uint16_t count_low; /*!< count for timer or pwm period low*/ - uint16_t count_high; /*!< count for pwm period high*/ - DEV_PWM_TIMER_HANDLER isr_hander; /*!< channel ch isr hander*/ -} DEV_PWM_TIMER_CFG, *DEV_PWM_TIMER_CFG_PTR; - -/** - * @defgroup DEVICE_HAL_PWM_TIMER_DEVSTRUCT PWM_TIMER Device Interface Definition - * @ingroup DEVICE_HAL_PWM_TIMER - * @brief Structure definition for pwm_timer device - * @details This structure will be used in user implemented code, which was called - * @ref DEVICE_IMPL "Device Driver Implement Layer" for pwm_timer to use in implementation code. - * Application developer should use the PWM_TIMER API provided here to access to PWM_TIMER devices. - * BSP developer should follow the API definition to implement PWM_TIMER device drivers. - * @{ - */ -/** - * @brief PWM_TIMER information struct definition - * @details Informations about pwm_timer open count, working status, - * pwm_timer registers and ctrl structure - */ -typedef struct { - void *pwm_timer_ctrl; - uint32_t opn_cnt; - // uint32_t status; - // uint32_t mode; -} DEV_PWM_TIMER_INFO, *DEV_PWM_TIMER_INFO_PTR; - -/** - * @brief PWM_TIMER device interface definition - * @details Define pwm_timer device interface, like pwm_timer information structure, - * provide functions to open/close/control pwm_timer, send/receive data by pwm_timer - * @note All this details are implemented by user in user porting code - */ -typedef struct { - DEV_PWM_TIMER_INFO pwm_timer_info; /*!< PWM_TIMER device information */ - int32_t (*pwm_timer_open)(void); /*!< Open pwm_timer device */ - int32_t (*pwm_timer_close)(void); /*!< Close pwm_timer device */ - int32_t (*pwm_timer_control)(uint32_t ch, uint32_t cmd, void *param2); /*!< Control pwm_timer device */ - int32_t (*pwm_timer_write)(uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc); /*!< Set the configuration of pwm_timer*/ - int32_t (*pwm_timer_read)(uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc); /*!< Read the configuration of pwm_timer*/ -} DEV_PWM_TIMER, *DEV_PWM_TIMER_PTR; -/** - * @fn int32_t *DEV_PWM_TIMER::pwm_timer_open(void) - * @details Open pwm_timer device - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_PWM_TIMER_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ - -/** - * @fn int32_t *DEV_PWM_TIMER::pwm_timer_close(void) - * @details Close an pwm_timer device, just decrease the @ref DEV_PWM_TIMER_INFO::opn_cnt "opn_cnt", - * if @ref DEV_PWM_TIMER_INFO::opn_cnt "opn_cnt" equals 0, then close the device - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_PWM_TIMER_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ - -/** - * @fn int32_t *DEV_PWM_TIMER::pwm_timer_control(uint32_t ch, uint32_t cmd, void *param2) - * @details Control a pwm_timer device [channel number: ch] by ctrl_cmd, with passed param. - * @param[in] ch Channel number of pwm_timer to control, must >= 0 - * @param[in] ctrl_cmd Control command, to change or get some thing related to pwm_timer - * @param[in,out] param Parameters that maybe argument of the command, or return values of the command - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ - -/** - * @fn int32_t *DEV_PWM_TIMER::pwm_timer_write(uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc) - * @details Set the configuration of pwm_timer. - * @param[in] ch Channel number of pwm_timer to write, must >= 0 - * @param[in] mode Set the mode of pwm_timer, must not be NULL - * @param[in] freq Set the frequency of pwm_timer, must not be NULL - * @param[in] dc Set the duty cycle of pwm_timer, must not be NULL - * @retval E_OK Set device successfully - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ - -/** - * @fn int32_t *DEV_PWM_TIMER::pwm_timer_read(uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc) - * @details Read the configuration of pwm_timer. - * @param[in] ch Channel number of pwm_timer to read, must >= 0 - * @param[out] mode Pointer to data mode of pwm_timer, must not be NULL - * @param[out] freq Pointer to data frequency of pwm_timer, must not be NULL - * @param[out] dc Pointer to data duty cycle of pwm_timer, must not be NULL - * @retval E_OK Read device successfully - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get an @ref DEV_PWM_TIMER "pwm_timer device" by pwm_timer device id. - * For how to use pwm_timer device hal refer to @ref DEV_PWM_TIMER "Functions in pwm_timer device structure" - * @param[in] pwm_timer_id ID of pwm_timer, defined by user - * @retval !NULL Pointer to an @ref DEV_PWM_TIMER "pwm_timer device structure" - * @retval NULL Failed to find the pwm_timer device by pwm_timer_id - * @note Need to implemented by user in user code - */ -extern DEV_PWM_TIMER_PTR pwm_timer_get_dev(int32_t pwm_timer_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* H_DEV_PWM_TIMER */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_sdio.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_sdio.h deleted file mode 100644 index 491c00a5..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_sdio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_DEV_SDIO -#define H_DEV_SDIO - -#include "device/dev_common.h" - -#define SDIO_CMD_SET_BUS_WIDTH DEV_SET_SYSCMD(1) /* set bus width */ -#define SDIO_CMD_SET_BUS_FREQ DEV_SET_SYSCMD(2) /* set bus freq */ - -#define SDIO_OCR_BUSY (0x80000000) -#define SDIO_OCR_HCS (0x40000000) -#define SDIO_OCR_VOLTAGE_MASK (0x00FF8000) - -#define SDIO_RSP_PRESENT (1 << 0) -#define SDIO_RSP_136 (1 << 1) /* 136 bit response */ -#define SDIO_RSP_CRC (1 << 2) /* expect valid crc */ -#define SDIO_RSP_BUSY (1 << 3) /* card may send busy */ -#define SDIO_RSP_OPCODE (1 << 4) /* response contains opcode */ - -#define SDIO_RSP_NONE (0) -#define SDIO_RSP_R1 (SDIO_RSP_PRESENT | SDIO_RSP_CRC | SDIO_RSP_OPCODE) -#define SDIO_RSP_R1b (SDIO_RSP_PRESENT | SDIO_RSP_CRC | SDIO_RSP_OPCODE | SDIO_RSP_BUSY) -#define SDIO_RSP_R2 (SDIO_RSP_PRESENT | SDIO_RSP_136 | SDIO_RSP_CRC) -#define SDIO_RSP_R3 (SDIO_RSP_PRESENT) -#define SDIO_RSP_R4 (SDIO_RSP_PRESENT) -#define SDIO_RSP_R5 (SDIO_RSP_PRESENT | SDIO_RSP_CRC | SDIO_RSP_OPCODE) -#define SDIO_RSP_R6 (SDIO_RSP_PRESENT | SDIO_RSP_CRC | SDIO_RSP_OPCODE) -#define SDIO_RSP_R7 (SDIO_RSP_PRESENT | SDIO_RSP_CRC | SDIO_RSP_OPCODE) - -#define SDIO_STATUS_MASK_ERR (~0x0206BF7F) -#define SDIO_STATUS_SWITCH_ERROR (1 << 7) -#define SDIO_STATUS_RDY_FOR_DATA (1 << 8) -#define SDIO_STATUS_CURR_STATE (0xf << 9) -#define SDIO_STATUS_ERROR (1 << 19) - -#define SDIO_STATUS_STATE_PRG (7 << 9) - -#define SDIO_DATA_WRITE 1 -#define SDIO_DATA_READ 2 - -typedef struct { - uint16_t card; /* card numer */ - uint16_t cmdidx; /* cmd index */ - uint32_t resp_type; /* respone type */ - uint32_t arg; /* cmd argument */ - uint32_t resp[4]; /* respone */ -} SDIO_CMD, *SDIO_CMD_PTR; - -typedef struct { - union { - uint8_t *in; /* read */ - const uint8_t *out; /* write */ - }; - uint32_t flags; /* r/w flags */ - uint32_t blkcnt; - uint32_t blksz; -} SDIO_DATA, *SDIO_DATA_PTR; - -typedef struct { - uint16_t card; /* card number */ - uint16_t cmd; /* ctrl cmd */ -} SDIO_CTRL_CMD, *SDIO_CTRL_CMD_PTR; - -typedef struct dev_sdio_info { - void *sdio_ctrl; /* hardward specific data */ - uint32_t opn_cnt; - uint32_t status; - DEV_CALLBACK cb; /* current operation callback */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer */ -} DEV_SDIO_INFO, *DEV_SDIO_INFO_PTR; - -typedef struct { - DEV_SDIO_INFO sdio_info; /*!< sdio device information */ - int32_t (*open)(uint32_t card); /*!< Open sdio device */ - int32_t (*close)(uint32_t card); /*!< Close sdio device */ - int32_t (*control)(SDIO_CTRL_CMD_PTR ctrl_cmd, void *param); /*!< Control sdio device */ - int32_t (*cmd_poll)(SDIO_CMD_PTR cmd, SDIO_DATA_PTR data); - int32_t (*cmd_int)(SDIO_CMD_PTR cmd, SDIO_DATA_PTR data, DEV_CALLBACK cb); /* interrupt based operation */ - int32_t (*cd)(uint32_t card); - int32_t (*wp)(uint32_t card); -} DEV_SDIO, *DEV_SDIO_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -extern DEV_SDIO_PTR sdio_get_dev(uint32_t sdio_id); - -#ifdef __cplusplus -} -#endif -#endif /* H_DEV_SDIO */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_spi.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_spi.h deleted file mode 100644 index 4e65e728..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_spi.h +++ /dev/null @@ -1,634 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @defgroup DEVICE_HAL_SPI SPI Device HAL Interface - * @ingroup DEVICE_HAL_DEF - * @brief Definitions for spi device hardware layer (@ref dev_spi.h) - * @details Provide interfaces for spi driver to implement - * - * @{ - * - * @file - * @brief Definitions for spi device hardware layer - * @details Provide common definitions for spi device, - * then software developer can develop spi driver - * following this definitions, and the applications - * can directly call this definition to realize functions - */ - -#ifndef H_DEV_SPI -#define H_DEV_SPI - -#include "device/dev_common.h" - -/** - * @defgroup DEVICE_HAL_SPI_CTRLCMD SPI Device Control Commands - * @ingroup DEVICE_HAL_SPI - * @brief Definitions for spi control command, used in @ref DEV_SPI::spi_control "SPI IO Control" - * @details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - @ref E_OK, Control device successfully - * - @ref E_CLSED, Device is not opened - * - @ref E_OBJ, Device object is not valid or not exists - * - @ref E_PAR, Parameter is not valid for current control command - * - @ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - @ref E_CTX, Control device failed, due to different reasons like in transfer state - * - @ref E_NOSPT, Control command is not supported or not valid - * - Usage Comment - * - For SPI poll or interrupt read/write/transfer operations, only 1 operation can be triggered. - * If there is a operation is running, any other operation will return @ref E_CTX - * - If SPI is in transfer, then the following operations may return @ref E_CTX. Like - * @ref SPI_CMD_SET_CLK_MODE, @ref SPI_CMD_SET_TXINT_BUF, @ref SPI_CMD_SET_RXINT_BUF, - * @ref SPI_CMD_SET_TXINT, @ref SPI_CMD_SET_RXINT, @ref SPI_CMD_ABORT_TX, @ref SPI_CMD_ABORT_RX, - * @ref SPI_CMD_FLUSH_TX, @ref SPI_CMD_FLUSH_RX, @ref SPI_CMD_SET_DFS, @ref SPI_CMD_TRANSFER_POLLING, - * @ref SPI_CMD_TRANSFER_INT, @ref SPI_CMD_ABORT_XFER, @ref SPI_CMD_MST_SEL_DEV, @ref SPI_CMD_MST_DSEL_DEV, - * @ref SPI_CMD_MST_SET_FREQ and @ref DEV_SPI::spi_write "SPI Poll Write" or @ref DEV_SPI::spi_read "SPI Poll Read". - * @{ - */ - -/** Define SPI control commands for common usage */ -#define DEV_SET_SPI_SYSCMD(cmd) DEV_SET_SYSCMD((cmd)) -/** Define SPI control commands for master usage */ -#define DEV_SET_SPI_MST_SYSCMD(cmd) DEV_SET_SYSCMD(0x00001000 | (cmd)) -/** Define SPI control commands for slave usage */ -#define DEV_SET_SPI_SLV_SYSCMD(cmd) DEV_SET_SYSCMD(0x00002000 | (cmd)) - -/* ++++ Common commands for SPI Device ++++ */ -/** - * Get @ref DEV_SPI_INFO::status "current device status" - * - Param type : uint32_t * - * - Param usage : store result of current status - * - Return value explanation : - */ -#define SPI_CMD_GET_STATUS DEV_SET_SPI_SYSCMD(0) -/** - * Set the @ref DEV_SPI_INFO::clk_mode "clock mode" of spi transfer - * - Param type : uint32_t - * - Param usage : spi clock mode to choose clock phase and clock polarity - * - Return value explanation : - */ -#define SPI_CMD_SET_CLK_MODE DEV_SET_SPI_SYSCMD(1) -/** - * Set spi @ref DEV_SPI_INFO::dfs "data frame size" - * - Param type : uint32_t - * - Param usage : should > 0 - * - Return value explanation : If dfs is not supported, then return @ref E_SYS - */ -#define SPI_CMD_SET_DFS DEV_SET_SPI_SYSCMD(2) -/** - * Set the @ref DEV_SPI_INFO::dummy "dummy data" during spi transfer - * - Param type : uint32_t - * - Param usage : dummy data to transfer - * - Return value explanation : - */ -#define SPI_CMD_SET_DUMMY_DATA DEV_SET_SPI_SYSCMD(3) -/** - * Set @ref DEV_SPI_CBS::tx_cb "spi transmit success callback" function - * when all required bytes are transmitted for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transmit success callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_TXCB DEV_SET_SPI_SYSCMD(4) -/** - * Set @ref DEV_SPI_CBS::rx_cb "spi receive success callback" function - * when all required bytes are received for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : receive success callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_RXCB DEV_SET_SPI_SYSCMD(5) -/** - * Set @ref DEV_SPI_CBS::xfer_cb "spi transfer success callback" function - * when all required transfer are done for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transfer success callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_XFERCB DEV_SET_SPI_SYSCMD(6) -/** - * Set @ref DEV_SPI_CBS::err_cb "spi transfer error callback" function - * when something error happened for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transfer error callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_ERRCB DEV_SET_SPI_SYSCMD(7) -/** - * Set buffer in interrupt transmit, and it will set @ref DEV_SPI_INFO::xfer "spi tranfer". - * - SPI master and slave mode use case @n - * For both master and slave mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt, - * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the - * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt - * and call tx callback function if available. - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty - * - Return value explanation : - */ -#define SPI_CMD_SET_TXINT_BUF DEV_SET_SPI_SYSCMD(8) -/** - * Set buffer in interrupt receive, and it will set @ref DEV_SPI_INFO::xfer "spi tranfer". - * - SPI master mode use case @n - * Similar to @ref SPI_CMD_SET_TXINT_BUF - * - SPI slave mode use case @n - * Similiar to @ref SPI_CMD_SET_TXINT_BUF - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty - * - Return value explanation : - */ -#define SPI_CMD_SET_RXINT_BUF DEV_SET_SPI_SYSCMD(9) -/** - * Enable or disable transmit interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if tx interrupt is enabled, then rx interrupt can't be enabled. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define SPI_CMD_SET_TXINT DEV_SET_SPI_SYSCMD(10) -/** - * Enable or disable receive interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if rx interrupt is enabled, then tx interrupt can't be enabled. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define SPI_CMD_SET_RXINT DEV_SET_SPI_SYSCMD(11) -/** - * Start the transfer by polling - * - Param type : @ref DEV_SPI_TRANSFER * - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_TRANSFER_POLLING DEV_SET_SPI_SYSCMD(12) -/** - * Start the transfer by interrupt - * - Param type : @ref DEV_SPI_TRANSFER * or NULL - * - Param usage : If NULL, it will disable transfer interrupt, if not NULL, it will enable transfer interrupt - * - Return value explanation : - */ -#define SPI_CMD_TRANSFER_INT DEV_SET_SPI_SYSCMD(13) -/** - * Abort current interrupt transmit operation if tx interrupt enabled, - * it will disable transmit interrupt, and set @ref DEV_IN_TX_ABRT - * in @ref DEV_SPI_INFO::status "status" variable, - * and call the transmit callback function, when tx callback is finished, - * it will clear @ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_ABORT_TX DEV_SET_SPI_SYSCMD(14) -/** - * Abort current interrupt receive operation if rx interrupt enabled, - * it will disable receive interrupt, and set @ref DEV_IN_TX_ABRT - * in @ref DEV_SPI_INFO::status "status" variable, - * and call the receive callback function, when rx callback is finished, - * it will clear @ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_ABORT_RX DEV_SET_SPI_SYSCMD(15) -/** - * Abort current interrupt transfer operation if transfer is issued, - * it will disable transfer interrupt, and set @ref DEV_IN_XFER_ABRT - * in @ref DEV_SPI_INFO::status "status" variable, - * and call the transfer callback function, when xfer callback is finished, - * it will clear @ref DEV_IN_XFER_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_ABORT_XFER DEV_SET_SPI_SYSCMD(16) -/** - * Do a software reset for SPI device, it will stop current transfer, - * and clear error state and bring device to normal state, set next condition to STOP - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_RESET DEV_SET_SPI_SYSCMD(17) -/** - * Flush spi tx fifo, this will clear the data in tx fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_FLUSH_TX DEV_SET_SPI_SYSCMD(18) -/** - * Flush spi rx fifo, this will clear the data in rx fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_FLUSH_RX DEV_SET_SPI_SYSCMD(19) -/** - * Enable spi device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define SPI_CMD_ENA_DEV DEV_SET_SPI_SYSCMD(20) -/** - * Disable spi device, when device is disabled, - * only @ref SPI_CMD_ENA_DEV, @ref SPI_CMD_DIS_DEV, - * @ref SPI_CMD_GET_STATUS and @ref SPI_CMD_RESET - * commands can be executed, other commands will return @ref E_SYS - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define SPI_CMD_DIS_DEV DEV_SET_SPI_SYSCMD(21) -/** - * Get how many bytes space in spi are available to transmit, - * this can be used in interrupt callback functions, - * cooperate with @ref DEV_SPI::spi_write "spi_write" API to realize non-blocked write - * - Param type : int32_t * - * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define SPI_CMD_GET_TXAVAIL DEV_SET_SPI_SYSCMD(22) -/** - * Get how many bytes in spi are available to receive, - * this can be used in interrupt callback functions, - * cooperate with @ref DEV_SPI::spi_read "spi_read" API to realize non-blocked read - * - Param type : int32_t * - * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define SPI_CMD_GET_RXAVAIL DEV_SET_SPI_SYSCMD(23) -/** - * Start the transfer by quad read - * - Param type : @ref DEV_SPI_PAK * - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_QUAD_READ DEV_SET_SPI_SYSCMD(24) - -/* ++++ Master only commands for SPI Device ++++ */ -/** - * select spi slave device - * - Param type : uint32_t - * - Param usage : the number of spi slave device to select - * - Return value explanation : return @ref E_SYS when selection can't be done, return @ref E_CTX during transfer - */ -#define SPI_CMD_MST_SEL_DEV DEV_SET_SPI_MST_SYSCMD(0) -/** - * de-select spi slave device - * - Param type : uint32_t - * - Param usage : the number of spi slave device to de-select - * - Return value explanation : return @ref E_SYS when selection can't be done, return @ref E_CTX during transfer - */ -#define SPI_CMD_MST_DSEL_DEV DEV_SET_SPI_MST_SYSCMD(1) -/** - * Set @ref DEV_SPI_INFO::freq "spi frequency". - * - Param type : uint32_t - * - Param usage : spi freq - * - Return value explanation : no return - */ -#define SPI_CMD_MST_SET_FREQ DEV_SET_SPI_MST_SYSCMD(2) - -/* ++++ Slave only commands for SPI Device ++++ */ - -/* @todo add spi slave related CMDs */ - -/** @} */ - -/** - * @defgroup DEVICE_HAL_SPI_CALLBACK SPI Interrupt callback functions - * @ingroup DEVICE_HAL_SPI - * @brief callback function structure for SPI device - * @{ - */ -typedef struct { - DEV_CALLBACK tx_cb; /*!< spi data transmit success required bytes callback */ - DEV_CALLBACK rx_cb; /*!< spi data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< spi error callback */ - DEV_CALLBACK xfer_cb; /*!< transfer callback */ -} DEV_SPI_CBS, *DEV_SPI_CBS_PTR; -/** @} */ - -/** - * @defgroup DEVICE_HAL_SPI_CLK_MODE SPI Clock Mode - * @ingroup DEVICE_HAL_SPI - * @brief spi clock mode settings - * @{ - */ -/** SPI Clock Mode */ -typedef enum { - SPI_CPOL_0_CPHA_0 = 0, /*!< Inactive state of serial clock is low, serial clock toggles in middle of first data bit */ - SPI_CPOL_0_CPHA_1 = 1, /*!< Inactive state of serial clock is low, serial clock toggles at start of first data bit */ - SPI_CPOL_1_CPHA_0 = 2, /*!< Inactive state of serial clock is high, serial clock toggles in middle of first data bit */ - SPI_CPOL_1_CPHA_1 = 3, /*!< Inactive state of serial clock is high, serial clock toggles at start of first data bit */ - - SPI_CLK_MODE_0 = SPI_CPOL_0_CPHA_0, /*!< Equal to @ref SPI_CPOL_0_CPHA_0 */ - SPI_CLK_MODE_1 = SPI_CPOL_0_CPHA_1, /*!< Equal to @ref SPI_CPOL_0_CPHA_1 */ - SPI_CLK_MODE_2 = SPI_CPOL_1_CPHA_0, /*!< Equal to @ref SPI_CPOL_1_CPHA_0 */ - SPI_CLK_MODE_3 = SPI_CPOL_1_CPHA_1 /*!< Equal to @ref SPI_CPOL_1_CPHA_1 */ -} SPI_CLK_MODE; - -typedef SPI_CLK_MODE DEV_SPI_CLK_MODE; - -/*!< Default SPI device clock mode */ -#define SPI_CLK_MODE_DEFAULT SPI_CPOL_0_CPHA_0 -/** @} */ - -/** - * @defgroup DEVICE_HAL_SPI_SLAVE_SELECT SPI Slave Select Line - * @ingroup DEVICE_HAL_SPI - * @brief spi slave select line definition - * @{ - */ -/** SPI Slave Select Line, start from 0 */ -#define DEV_SPI_CS_LINE_DEF(line) (line) -typedef enum { - DEV_SPI_CS_LINE_0 = 0, /*!< SPI slave select line 0 */ - DEV_SPI_CS_LINE_1, /*!< SPI slave select line 1 */ - DEV_SPI_CS_LINE_2, /*!< SPI slave select line 2 */ - DEV_SPI_CS_LINE_3, /*!< SPI slave select line 3 */ - DEV_SPI_CS_LINE_4, /*!< SPI slave select line 4 */ - DEV_SPI_CS_LINE_5, /*!< SPI slave select line 5 */ - DEV_SPI_CS_LINE_6, /*!< SPI slave select line 6 */ - DEV_SPI_CS_LINE_7, /*!< SPI slave select line 7 */ - DEV_SPI_CS_LINE_8, /*!< SPI slave select line 8 */ - DEV_SPI_CS_LINE_9, /*!< SPI slave select line 9 */ - DEV_SPI_CS_LINE_10, /*!< SPI slave select line 10 */ - DEV_SPI_CS_LINE_11, /*!< SPI slave select line 11 */ - DEV_SPI_CS_LINE_12, /*!< SPI slave select line 12 */ - DEV_SPI_CS_LINE_13, /*!< SPI slave select line 13 */ - DEV_SPI_CS_LINE_14, /*!< SPI slave select line 14 */ - DEV_SPI_CS_LINE_15, /*!< SPI slave select line 15 */ - DEV_SPI_CS_LINE_16, /*!< SPI slave select line 16 */ - DEV_SPI_CS_LINE_17, /*!< SPI slave select line 17 */ - DEV_SPI_CS_LINE_18, /*!< SPI slave select line 18 */ - DEV_SPI_CS_LINE_19, /*!< SPI slave select line 19 */ - DEV_SPI_CS_LINE_20, /*!< SPI slave select line 20 */ - DEV_SPI_CS_LINE_21, /*!< SPI slave select line 21 */ - DEV_SPI_CS_LINE_22, /*!< SPI slave select line 22 */ - DEV_SPI_CS_LINE_23, /*!< SPI slave select line 23 */ - DEV_SPI_CS_LINE_24, /*!< SPI slave select line 24 */ - DEV_SPI_CS_LINE_25, /*!< SPI slave select line 25 */ - DEV_SPI_CS_LINE_26, /*!< SPI slave select line 26 */ - DEV_SPI_CS_LINE_27, /*!< SPI slave select line 27 */ - DEV_SPI_CS_LINE_28, /*!< SPI slave select line 28 */ - DEV_SPI_CS_LINE_29, /*!< SPI slave select line 29 */ - DEV_SPI_CS_LINE_30, /*!< SPI slave select line 30 */ - DEV_SPI_CS_LINE_31 /*!< SPI slave select line 31 */ -} DEV_SPI_CS_LINE; -/** @} */ - -/** - * @defgroup DEVICE_HAL_SPI_DEVSTRUCT SPI Device Structure - * @ingroup DEVICE_HAL_SPI - * @brief Structure definitions for spi device - * @details These structure will be used in user implemented code, which was called - * Device Driver Implement Layer for spi to realize in user code. - * @{ - */ -typedef struct dev_spi_transfer DEV_SPI_TRANSFER, *DEV_SPI_TRANSFER_PTR; -/** - * @brief SPI read and write data structure used by @ref SPI_CMD_TRANSFER_INT or @ref SPI_CMD_TRANSFER_POLLING - * spi write then read data - * - */ -struct dev_spi_transfer { - DEV_SPI_TRANSFER *next; - /* Calc by software */ - /** tot_len = (tx_totlen>rx_totlen)?tx_totlen:rx_totlen */ - uint32_t tot_len; - /* Set by user */ - uint8_t *tx_buf; - uint32_t tx_ofs; - uint32_t tx_len; - uint8_t *rx_buf; - uint32_t rx_ofs; - uint32_t rx_len; - /* Should auto set to proper value during set buffer value */ - uint32_t tx_idx; - uint32_t tx_totlen; /** tx_totlen = tx_len + tx_ofs */ - uint32_t rx_idx; - uint32_t rx_totlen; /** rx_totlen = rx_len + rx_ofs */ -}; - -/** Set tx buffer of device spi transfer */ -#define DEV_SPI_XFER_SET_TXBUF(xfer, buf, ofs, len) { \ - (xfer)->tx_buf = (uint8_t *)(buf); \ - (xfer)->tx_len = (uint32_t)(len); \ - (xfer)->tx_ofs = (uint32_t)(ofs); \ - (xfer)->tx_idx = 0; \ - (xfer)->tx_totlen = ((uint32_t)(len) \ - + (uint32_t)(ofs)); \ -} - -/** Set rx buffer of device spi transfer */ -#define DEV_SPI_XFER_SET_RXBUF(xfer, buf, ofs, len) { \ - (xfer)->rx_buf = (uint8_t *)(buf); \ - (xfer)->rx_len = (uint32_t)(len); \ - (xfer)->rx_ofs = (uint32_t)(ofs); \ - (xfer)->rx_idx = 0; \ - (xfer)->rx_totlen = ((uint32_t)(len) \ - + (uint32_t)(ofs)); \ -} - -/** Calculate total length of current transfer without next transfer */ -#define DEV_SPI_XFER_CALC_TOTLEN(xfer) (xfer)->tot_len = \ - ((xfer)->tx_totlen > (xfer)->rx_totlen) ? (xfer)->tx_totlen : (xfer)->rx_totlen; - -/** Set next SPI transfer */ -#define DEV_SPI_XFER_SET_NEXT(xfer, next_xfer) (xfer)->next = (next_xfer); - -/** Init spi transfer */ -#define DEV_SPI_XFER_INIT(xfer) { \ - (xfer)->tx_idx = 0; \ - (xfer)->rx_idx = 0; \ - (xfer)->tx_totlen = ((xfer)->tx_len \ - + (xfer)->tx_ofs); \ - (xfer)->rx_totlen = ((xfer)->rx_len \ - + (xfer)->rx_ofs); \ - DEV_SPI_XFER_CALC_TOTLEN(xfer); \ -} - -/** - * @brief SPI read and write data structure used by @ref SPI_CMD_QUAD_READ - * spi write cmd and address then read data - * - */ -typedef struct { - uint8_t cmd; - uint32_t addr32; - uint8_t *data_ptr; - uint32_t data_len; -} DEV_SPI_PAK, *DEV_SPI_PAK_PTR; - -/** - * @brief Structure definitions for spi information - * @details Informations about spi open state, working state, - * frequency, spi registers, working method, interrupt number - */ -typedef struct { - void *spi_ctrl; /*!< spi control related */ - uint32_t status; /*!< current working status, refer to @ref DEVICE_HAL_COMMON_DEVSTATUS, this should be @ref DEV_ENABLED for first open */ - uint32_t freq; /*!< spi working baudrate */ - uint8_t mode; /*!< spi working mode (master/slave) */ - uint8_t clk_mode; /*!< spi clock phase and polarity, this should be @ref SPI_CLK_MODE_DEFAULT for first open */ - uint8_t opn_cnt; /*!< spi open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint8_t slave; /*!< current selected slave device no, start from 0, this should be @ref SPI_SLAVE_NOT_SELECTED for first open */ - uint8_t dfs; /*!< data frame size, this should be @ref SPI_DFS_DEFAULT for first open */ - - DEV_SPI_TRANSFER xfer; /*!< spi transfer, this should be set to all zero for first open */ - DEV_SPI_CBS spi_cbs; /*!< spi callbacks, for both master and slave mode, this should be all NULL for first open */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can @ref DEV_SPI_INFO_SET_EXTRA_OBJECT "set" - or @ref DEV_SPI_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ - uint32_t dummy; /*!< dummy write data when send and receive, this should be @ref SPI_DUMMY_DEFAULT for first open */ -} DEV_SPI_INFO, *DEV_SPI_INFO_PTR; - -/** Set extra information pointer of spi info */ -#define DEV_SPI_INFO_SET_EXTRA_OBJECT(spi_info_ptr, extra_info) (spi_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of spi info */ -#define DEV_SPI_INFO_GET_EXTRA_OBJECT(spi_info_ptr) ((spi_info_ptr)->extra) - -#define SPI_DFS_DEFAULT 8 /*!< Default spi data frame size */ -#define SPI_SLAVE_NOT_SELECTED (0xFF) /*!< Slave is not selected */ -#define SPI_DUMMY_DEFAULT (0xFF) /*!< default dummy value for first open */ - -/** - * @brief Structure definitions for spi device - * @details Define spi device interface, like spi information structure, - * fuctions to get spi info, open/close/control spi, send/receive data by spi - * @note All this details are implemented by user in user porting code - */ -typedef struct { - DEV_SPI_INFO spi_info; /*!< spi device information */ - int32_t (*spi_open)(uint32_t mode, uint32_t param); /*!< open spi device in master/slave mode, \ - when in master mode, param stands for frequency, \ - when in slave mode, param stands for clock mode */ - int32_t (*spi_close)(void); /*!< close spi device */ - int32_t (*spi_control)(uint32_t ctrl_cmd, void *param); /*!< control spi device */ - int32_t (*spi_write)(const void *data, uint32_t len); /*!< send data to spi device (blocking method) */ - int32_t (*spi_read)(void *data, uint32_t len); /*!< read data from spi device (blocking method) */ -} DEV_SPI, *DEV_SPI_PTR; - -/** - * @fn int32_t *DEV_SPI::spi_open(uint32_t mode, uint32_t param) - * @details Open an spi device with selected mode (master or slave) with defined param - * @param[in] mode Working mode (@ref DEV_MASTER_MODE "master" or @ref DEV_SLAVE_MODE "slave") - * @param[in] param When mode is @ref DEV_MASTER_MODE, param stands for @ref DEV_SPI_INFO::freq "frequency", - * when mode is @ref DEV_SLAVE_MODE, param stands for @ref DEV_SPI_INFO::clk_mode "slave clock mode" - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_SPI_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ - -/** - * @fn int32_t *DEV_SPI::spi_close(void) - * @details Close an spi device, just decrease the @ref DEV_SPI_INFO::opn_cnt "opn_cnt", - * if @ref DEV_SPI_INFO::opn_cnt "opn_cnt" equals 0, then close the device - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_SPI_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ - -/** - * @fn int32_t *DEV_SPI::spi_control(uint32_t ctrl_cmd, void *param) - * @details Control an spi device by ctrl_cmd, with passed param. - * you can control spi device using predefined spi control commands defined using @ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as @ref SPI_CMD_MST_SET_FREQ "set spi master frequency", - * @ref SPI_CMD_FLUSH_TX "flush tx" and @ref DEVICE_HAL_SPI_CTRLCMD "more". - * And you can also control spi device using your own specified commands defined using @ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own spi device driver implementation. - * @param[in] ctrl_cmd @ref DEVICE_HAL_SPI_CTRLCMD "control command", to change or get some thing related to spi - * @param[in,out] param Parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ - -/** - * @fn int32_t *DEV_SPI::spi_write(const void *data, uint32_t len) - * @details Send data through spi with defined len to slave device . - * @param[in] data Pointer to data need to send by spi - * @param[in] len Length of data to be sent - * @retval > 0 Byte count that was successfully sent for poll method - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_CTX Device is still in transfer state - * @retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ - -/** - * @fn int32_t *DEV_SPI::spi_read(void *data, uint32_t len) - * @details receive data of defined len through spi from slave device . - * @param[out] data Pointer to data need to received by spi - * @param[in] len Length of data to be received - * @retval > 0 Byte count that was successfully received for poll method - * @retval E_OBJ Device object is not valid or not exists - * @retval E_CTX Device is still in transfer state - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get an @ref DEV_SPI "spi device" by spi device id. - * For how to use spi device hal refer to @ref DEV_SPI "Functions in spi device structure" - * @param[in] spi_id ID of spi, defined by user - * @retval !NULL Pointer to an @ref DEV_SPI "spi device structure" - * @retval NULL Failed to find the spi device by spi_id - * @note Need to implemented by user in user code - */ -extern DEV_SPI_PTR spi_get_dev(int32_t spi_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* H_DEV_SPI */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_trng.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_trng.h deleted file mode 100644 index cad2cc72..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_trng.h +++ /dev/null @@ -1,153 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2019, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/** - * @defgroup DEVICE_HAL_TRNG TRNG Device HAL Interface - * @ingroup DEVICE_HAL_DEF - * @brief Definitions for trng device hardware layer (@ref dev_trng.h) - * @details Provide interfaces for trng driver to implement - * - * @{ - */ -#ifndef H_DEV_TRNG -#define H_DEV_TRNG - -#include "device/dev_common.h" - -#define TRNG_VERSION_NIST // switch between DW_NIST_TRNG version and DW_TRNG version: define this value to choose NIST, otherwise undefine it. - -#define TRNG_CMD_SET_RAND_128_BIT_OUTPUT DEV_SET_SYSCMD(0) - -#define TRNG_CMD_SET_RAND_256_BIT_OUTPUT DEV_SET_SYSCMD(1) - -#define TRNG_CMD_SET_RAND_RESEED_AUTO DEV_SET_SYSCMD(2) - -#define TRNG_CMD_SET_RAND_RESEED_NONCE DEV_SET_SYSCMD(3) - -#define TRNG_CMD_SET_IN_CB DEV_SET_SYSCMD(4) - -#define TRNG_CMD_SET_OUT_CB DEV_SET_SYSCMD(5) - -#define TRNG_CMD_SET_ERR_CB DEV_SET_SYSCMD(6) - -typedef struct { - DEV_CALLBACK in_cb; /*!< trng data transmit success required bytes callback */ - DEV_CALLBACK out_cb; /*!< trng data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< trng error callback */ -} DEV_TRNG_CBS, *DEV_TRNG_CBS_PTR; - -/** - * @defgroup DEVICE_HAL_TRNG_DEVSTRUCT TRNG Device Interface Definition - * @ingroup DEVICE_HAL_TRNG - * @brief Structure definitions for trng device interface - * @details This structure will be used in user implemented code, which was called - * @ref DEVICE_IMPL "Device Driver Implement Layer" for trng to use in implementation code. - * Application developer should use the TRNG API provided here to access to TRNG devices. - * BSP developer should follow the API definition to implement TRNG device drivers. - * @{ - */ -/** - * @brief Structure definitions for trng information - * @details Informations about trng open count, working status, - * baudrate, trng registers and ctrl structure, trng dps format - */ -typedef struct { - void *trng_ctrl; /*!< trng control related pointer, implemented by bsp developer, and this should be set during trng object implementation */ - uint32_t opn_cnt; /*!< trng open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t length; /*!< output length */ - uint32_t byte_generated; /*!< count the bytes generated since last reseed, can be a reference and a reminder for next reseed operation */ - DEV_BUFFER in_buf; /*!< input buffer via interrupt, this should be all zero for first open */ - DEV_BUFFER out_buf; /*!< output buffer via interrupt, this should be all zero for first open */ - DEV_TRNG_CBS trng_cbs; - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can @ref DEV_TRNG_INFO_SET_EXTRA_OBJECT "set" - or @ref DEV_TRNG_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_TRNG_INFO, *DEV_TRNG_INFO_PTR; - -/** Set extra information pointer of trng info */ -#define DEV_TRNG_INFO_SET_EXTRA_OBJECT(trng_info_ptr, extra_info) (trng_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of trng info */ -#define DEV_TRNG_INFO_GET_EXTRA_OBJECT(trng_info_ptr) ((trng_info_ptr)->extra) - -typedef struct { - DEV_TRNG_INFO trng_info; /*!< device information */ - - int32_t (*trng_open)(void); /*!< Open trng device */ - int32_t (*trng_close)(void); /*!< Close trng device */ - int32_t (*trng_control)(uint32_t ctrl_cmd, void *param); /*!< Control trng device */ - int32_t (*trng_read)(uint32_t *data_buf); /*!< Read data from trng device(blocked) */ -} DEV_TRNG, *DEV_TRNG_PTR; -/** - * @fn int32_t *DEV_TRNG::trng_open(void) - * @details Open trng device - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_TRNG_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ - -/** - * @fn int32_t *DEV_TRNG::trng_close(void) - * @details Close an trng device, just decrease the @ref DEV_TRNG_INFO::opn_cnt "opn_cnt", - * if @ref DEV_TRNG_INFO::opn_cnt "opn_cnt" equals 0, then close the device - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_TRNG_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ - -/** - * @fn int32_t *DEV_TRNG::trng_control(uint32_t ch, uint32_t cmd, void *param2) - * @details Control a trng device [channel number: ch] by ctrl_cmd, with passed param. - * @param[in] ch Channel number of trng to control, must >= 0 - * @param[in] ctrl_cmd Control command, to change or get some thing related to trng - * @param[in,out] param Parameters that maybe argument of the command, or return values of the command - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ - -/** - * @fn int32_t *DEV_TRNG::trng_read(uint32_t *data_buf) - * @details Read the configuration of trng. - * @param[out] data_buf pointer to data buffer read from trng, must not be NULL - * @retval E_OK Read device successfully - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -/** @} */ -#endif /* H_DEV_TRNG */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_uart.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_uart.h deleted file mode 100644 index a482ad65..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/dev_uart.h +++ /dev/null @@ -1,461 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @defgroup DEVICE_HAL_UART UART Device HAL Interface - * @ingroup DEVICE_HAL_DEF - * @brief Definitions for uart device hardware layer (@ref dev_uart.h) - * @details Provide unified APIs for uart driver to implement. - * - * @{ - * - * @file - * @brief Definitions for uart device hardware layer - * @details Provide common definitions for uart device, - * then software developer can develop uart driver - * following this definitions, and the applications - * can directly call this definition to realize functions - * - */ - -#ifndef H_DEV_UART -#define H_DEV_UART - -#include "device/dev_common.h" - -/** - * @defgroup DEVICE_HAL_UART_BAUD UART Device Baudrate Definitions - * @ingroup DEVICE_HAL_UART - * @brief Macro definitions for uart baud rate - * @details Macro definitions for baud rate from 4800 to 115200bps. - * @{ - */ -/* - * defines for uart baudrates - */ -#define UART_BAUDRATE_110 (110) /*!< uart baudrate 110bps */ -#define UART_BAUDRATE_300 (300) /*!< uart baudrate 300bps */ -#define UART_BAUDRATE_600 (600) /*!< uart baudrate 600bps */ -#define UART_BAUDRATE_1200 (1200) /*!< uart baudrate 1200bps */ -#define UART_BAUDRATE_2400 (2400) /*!< uart baudrate 2400bps */ -#define UART_BAUDRATE_4800 (4800) /*!< uart baudrate 4800bps */ -#define UART_BAUDRATE_9600 (9600) /*!< uart baudrate 9600bps */ -#define UART_BAUDRATE_14400 (14400) /*!< uart baudrate 14400bps */ -#define UART_BAUDRATE_19200 (19200) /*!< uart baudrate 19200bps */ -#define UART_BAUDRATE_38400 (38400) /*!< uart baudrate 38400bps */ -#define UART_BAUDRATE_57600 (57600) /*!< uart baudrate 57600bps */ -#define UART_BAUDRATE_115200 (115200) /*!< uart baudrate 115200bps */ -#define UART_BAUDRATE_230400 (230400) /*!< uart baudrate 230400bps */ -#define UART_BAUDRATE_460800 (460800) /*!< uart baudrate 460800bps */ -#define UART_BAUDRATE_921600 (921600) /*!< uart baudrate 921600bps */ -/** @} */ - -/** - * @defgroup DEVICE_HAL_UART_FORMAT UART Device Format Definitions - * @ingroup DEVICE_HAL_UART - * @brief Macro definitions for uart format - * @details Macro definitions for uart format like databits, parity, stopbits. - * @{ - */ -/** - * UART Device Parity Types Enum - */ -typedef enum { - UART_PARITY_NONE = 0, /*!< no parity bit */ - UART_PARITY_ODD = 1, /*!< odd parity bit */ - UART_PARITY_EVEN = 2, /*!< even parity bit */ - UART_PARITY_MARK = 3, /*!< mark parity bit, always logical 1 */ - UART_PARITY_SPACE = 4 /*!< space parity bit, always logical 0 */ -} UART_PARITY; - -/** - * UART Device Stop Bits Enum - */ -typedef enum { - UART_STPBITS_ONE = 0, /*!< 1 stop bit */ - UART_STPBITS_ONEHALF = 1, /*!< 1.5 stop bits */ - UART_STPBITS_TWO = 2 /*!< 2 stop bits */ -} UART_STOPBITS; - -/** - * UART DPS Format: databits/parity/stopbits - */ -typedef struct { - uint32_t databits; /*!< data bits */ - UART_PARITY parity; /*!< parity bit type */ - UART_STOPBITS stopbits; /*!< stop bits */ -} UART_DPS_FORMAT; - -#define UART_DATABITS_DEFAULT 8 /*!< default data bits */ - -/** Default UART DPS format */ -#define UART_DPS_FORMAT_DEFAULT(format) \ - format.databits = UART_DATABITS_DEFAULT; \ - format.parity = UART_PARITY_NONE; \ - format.stopbits = UART_STPBITS_ONE -/** @} */ - -/** - * UART Device Hardware Flow Control Types Enum - */ -typedef enum { - UART_FC_DEFAULT = 0, /*!< Default hardware flow control method */ - UART_FC_NONE = 0, /*!< Non hardware flow control */ - UART_FC_RTS = 1, /*!< Request To Send */ - UART_FC_CTS = 2, /*!< Clear To Send */ - UART_FC_BOTH = 3 /*!< Both hardware flow control methods */ -} UART_HW_FLOW_CONTROL; - -/** - * @defgroup DEVICE_HAL_UART_CTRLCMD UART Device Control Commands - * @ingroup DEVICE_HAL_UART - * @brief Macro definitions for uart control command, used in @ref DEV_UART::uart_control "UART IO Control" - * @details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - @ref E_OK, Control device successfully - * - @ref E_CLSED, Device is not opened - * - @ref E_OBJ, Device object is not valid or not exists - * - @ref E_PAR, Parameter is not valid for current control command - * - @ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - @ref E_CTX, Control device failed, due to different reasons like in transfer state - * - @ref E_NOSPT, Control command is not supported or not valid - * @{ - */ -/** - * Set @ref DEV_UART_INFO::baudrate "uart baudrate". - * - Param type : uint32_t - * - Param usage : uart baudrate, must above zero. Here is a list of @ref DEVICE_HAL_UART_BAUD "possible baudrates" - * - Return value explanation : - */ -#define UART_CMD_SET_BAUD DEV_SET_SYSCMD(0) -/** - * Get @ref DEV_UART_INFO::status "current device status" - * - Param type : uint32_t * - * - Param usage : store result of current status - * - Return value explanation : - */ -#define UART_CMD_GET_STATUS DEV_SET_SYSCMD(1) -/** - * Enable uart device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_ENA_DEV DEV_SET_SYSCMD(2) -/** - * Disable uart device, when device is disabled, - * only @ref UART_CMD_ENA_DEV, @ref UART_CMD_DIS_DEV and - * @ref UART_CMD_GET_STATUS commands can be executed, - * other commands will return @ref E_SYS - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_DIS_DEV DEV_SET_SYSCMD(3) -/** - * Flush uart device output - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_FLUSH_OUTPUT DEV_SET_SYSCMD(4) -/** - * Get how many bytes space in uart are available to transmit, - * this can be used in interrupt callback functions, - * cooperate with @ref DEV_UART::uart_write "uart_write" API to realize non-blocked write - * - Param type : int32_t * - * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define UART_CMD_GET_TXAVAIL DEV_SET_SYSCMD(5) -/** - * Get how many bytes in uart are available to receive, - * this can be used in interrupt callback functions, - * cooperate with @ref DEV_UART::uart_read "uart_read" API to realize non-blocked read - * - Param type : int32_t * - * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define UART_CMD_GET_RXAVAIL DEV_SET_SYSCMD(6) -/** - * Cause a break condition to be transmitted to the receiving device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_BREAK_SET DEV_SET_SYSCMD(7) -/** - * Clear break condition and return to normal - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_BREAK_CLR DEV_SET_SYSCMD(8) -/** - * Change uart @ref DEV_UART_INFO::dps_format "D/P/S(Data/Parity/Stop) format" - * - Param type : @ref UART_DPS_FORMAT * - * - Param usage : uart dps format including databits, parity and stopbits - * - Return value explanation : - */ -#define UART_CMD_SET_DPS_FORMAT DEV_SET_SYSCMD(9) -/** - * Set uart device @ref DEV_UART_INFO::hwfc "hardware flow control" - * - Param type : @ref UART_HW_FLOW_CONTROL - * - Param usage : uart dps format including databits, parity and stopbits - * - Return value explanation : - */ -#define UART_CMD_SET_HWFC DEV_SET_SYSCMD(10) -/** - * Set @ref DEV_UART_CBS::tx_cb "uart transmit success callback" function - * when all required bytes are transmitted for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transmit success callback function for uart - * - Return value explanation : - */ -#define UART_CMD_SET_TXCB DEV_SET_SYSCMD(11) -/** - * Set @ref DEV_UART_CBS::rx_cb "uart receive success callback" function - * when all required bytes are received for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : receive success callback function for uart - * - Return value explanation : - */ -#define UART_CMD_SET_RXCB DEV_SET_SYSCMD(12) -/** - * Set @ref DEV_UART_CBS::err_cb "uart transfer error callback" function - * when something error happened for interrupt method - * - Param type : @ref DEV_CALLBACK * or NULL - * - Param usage : transfer error callback function for uart - * - Return value explanation : - */ -#define UART_CMD_SET_ERRCB DEV_SET_SYSCMD(13) -/** - * Set transmit buffer via interrupt, and it will set @ref DEV_UART_INFO::tx_buf "tx_buf" - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL - * - Return value explanation : - */ -#define UART_CMD_SET_TXINT_BUF DEV_SET_SYSCMD(14) -/** - * Set receive buffer via interrupt, and it will set @ref DEV_UART_INFO::rx_buf "rx_buf" - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL - * - Return value explanation : - */ -#define UART_CMD_SET_RXINT_BUF DEV_SET_SYSCMD(15) -/** - * Enable or disable transmit interrupt - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define UART_CMD_SET_TXINT DEV_SET_SYSCMD(16) -/** - * Enable or disable receive interrupt - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define UART_CMD_SET_RXINT DEV_SET_SYSCMD(17) -/** - * Abort current interrupt transmit operation if tx interrupt enabled, - * it will disable transmit interrupt, and set @ref DEV_IN_TX_ABRT - * in @ref DEV_UART_INFO::status "status" variable, - * and call the transmit callback function, when tx callback is finished, - * it will clear @ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define UART_CMD_ABORT_TX DEV_SET_SYSCMD(18) -/** - * Abort current interrupt receive operation if rx interrupt enabled, - * it will disable receive interrupt, and set @ref DEV_IN_TX_ABRT - * in @ref DEV_UART_INFO::status "status" variable, - * and call the receive callback function, when rx callback is finished, - * it will clear @ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define UART_CMD_ABORT_RX DEV_SET_SYSCMD(19) - -/** @} */ - -/** - * @defgroup DEVICE_HAL_UART_CALLBACK UART Interrupt callback functions - * @ingroup DEVICE_HAL_UART - * @brief Structure definition for uart device callback - * @{ - */ -typedef struct { - DEV_CALLBACK tx_cb; /*!< uart data transmit success required bytes callback */ - DEV_CALLBACK rx_cb; /*!< uart data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< uart error callback */ -} DEV_UART_CBS, *DEV_UART_CBS_PTR; -/** @} */ - -/** - * @defgroup DEVICE_HAL_UART_DEVSTRUCT UART Device Interface Definition - * @ingroup DEVICE_HAL_UART - * @brief Structure definitions for uart device interface - * @details This structure will be used in user implemented code, which was called - * @ref DEVICE_IMPL "Device Driver Implement Layer" for uart to use in implementation code. - * Application developer should use the UART API provided here to access to UART devices. - * BSP developer should follow the API definition to implement UART device drivers. - * @{ - */ -/** - * @brief Structure definition for uart information - * @details Informations about uart open count, working status, - * baudrate, uart registers and ctrl structure, uart dps format - */ -typedef struct { - void *uart_ctrl; /*!< uart control related pointer, implemented by bsp developer, and this should be set during uart object implementation */ - uint32_t opn_cnt; /*!< uart open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t status; /*!< current working status, refer to @ref DEVICE_HAL_COMMON_DEVSTATUS, this should be @ref DEV_ENABLED for first open */ - uint32_t baudrate; /*!< uart baud rate, this should be the value of baud passing by uart_open if first successfully opened */ - UART_DPS_FORMAT dps_format; /*!< D/P/S format settings for uart device, here is @ref UART_DATABITS_DEFAULT "default settings for first open" */ - UART_HW_FLOW_CONTROL hwfc; /*!< UART hardware flow control, here is @ref UART_HW_FLOW_CONTROL::UART_FC_DEFAULT "default hardware flow control settings for first open" */ - DEV_BUFFER tx_buf; /*!< transmit buffer via interrupt, this should be all zero for first open */ - DEV_BUFFER rx_buf; /*!< receive buffer via interrupt, this should be all zero for first open */ - DEV_UART_CBS uart_cbs; /*!< uart callbacks, callback arguments should be @ref DEV_UART * or NULL, this should be all NULL for first open */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can @ref DEV_UART_INFO_SET_EXTRA_OBJECT "set" - or @ref DEV_UART_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_UART_INFO, *DEV_UART_INFO_PTR; - -/** Set extra information pointer of uart info */ -#define DEV_UART_INFO_SET_EXTRA_OBJECT(uart_info_ptr, extra_info) (uart_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of uart info */ -#define DEV_UART_INFO_GET_EXTRA_OBJECT(uart_info_ptr) ((uart_info_ptr)->extra) - -/** - * @brief Structure definition for uart interface - * @details Define uart device interface, like uart information structure, - * provide functions to open/close/control uart, send/receive data by uart - * @note All this details are implemented by user in user porting code - */ -typedef struct { - DEV_UART_INFO uart_info; /*!< UART device information */ - int32_t (*uart_open)(uint32_t baud); /*!< Open uart device */ - int32_t (*uart_close)(void); /*!< Close uart device */ - int32_t (*uart_control)(uint32_t ctrl_cmd, void *param); /*!< Control uart device */ - int32_t (*uart_write)(const void *data, uint32_t len); /*!< Send data by uart device(blocked) */ - int32_t (*uart_read)(void *data, uint32_t len); /*!< Read data from uart device(blocked) */ -} DEV_UART, *DEV_UART_PTR; - -/** - * @fn int32_t *DEV_UART::uart_open(uint32_t baud) - * @details Open an uart device with defined baudrate - * param[in] baud @ref DEVICE_HAL_UART_BAUD "initial baudrate of uart", must > 0 - * @retval E_OK Open successfully without any issues - * @retval E_OPNED If device was opened before with different parameters, - * then just increase the @ref DEV_UART_INFO::opn_cnt "opn_cnt" and return @ref E_OPNED - * @retval E_OBJ Device object is not valid - * @retval E_PAR Parameter is not valid - * @retval E_NOSPT Open settings are not supported - */ - -/** - * @fn int32_t *DEV_UART::uart_close(void) - * @details Close an uart device, just decrease the @ref DEV_UART_INFO::opn_cnt "opn_cnt", - * if @ref DEV_UART_INFO::opn_cnt "opn_cnt" equals 0, then close the device - * @retval E_OK Close successfully without any issues(including scenario that device is already closed) - * @retval E_OPNED Device is still opened, the device @ref DEV_UART_INFO::opn_cnt "opn_cnt" decreased by 1 - * @retval E_OBJ Device object is not valid - */ - -/** - * @fn int32_t *DEV_UART::uart_control(uint32_t ctrl_cmd, void *param) - * @details Control an uart device by ctrl_cmd, with passed param. - * you can control uart device using predefined uart control commands defined using @ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as @ref UART_CMD_SET_BAUD "change baudrate", - * @ref UART_CMD_FLUSH_OUTPUT "flush output" and @ref DEVICE_HAL_UART_CTRLCMD "more". - * And you can also control uart device using your own specified commands defined using @ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own uart device driver implementation. - * param[in] ctrl_cmd @ref DEVICE_HAL_UART_CTRLCMD "control command", to change or get some thing related to uart - * param[in,out] param Parameters that maybe argument of the command, or return values of the command - * @retval E_OK Control device successfully - * @retval E_CLSED Device is not opened - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid for current control command - * @retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * @retval E_CTX Control device failed, due to different reasons like in transfer state - * @retval E_NOSPT Control command is not supported or not valid - */ - -/** - * @fn int32_t *DEV_UART::uart_write(const void *data, uint32_t len) - * @details Send data through uart with defined len(blocked). - * param[in] data Pointer to data need to send by uart, must not be NULL - * param[in] len Length of data to be sent, must > 0 - * @retval > 0 Byte count that was successfully sent for poll method - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ - -/** - * @fn int32_t *DEV_UART::uart_read(void *data, uint32_t len) - * @details Receive data of defined len through uart(blocked). - * param[out] data Pointer to data need to received by uart, must not be NULL - * param[in] len Length of data to be received, must > 0 - * @retval > 0 Byte count that was successfully received for poll method - * @retval E_OBJ Device object is not valid or not exists - * @retval E_PAR Parameter is not valid - * @retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get an @ref DEV_UART "uart device" by uart device id. - * For how to use uart device hal refer to @ref DEVICE_HAL_UART_DEVSTRUCT "Functions in uart device structure" - * param[in] uart_id ID of uart, defined by user - * @retval !NULL Pointer to an @ref DEV_UART "uart device structure" - * @retval NULL Failed to find the uart device by uart_id - * @note Need to implemented by user in user code - */ -extern DEV_UART_PTR uart_get_dev(int32_t uart_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* H_DEV_UART */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/ioctl.h b/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/ioctl.h deleted file mode 100644 index 61251f07..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/ip_hal/ioctl.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_IOCTL -#define H_IOCTL - -typedef void (*IO_CB_FUNC) (uint32_t); - -typedef struct { - IO_CB_FUNC cb; -} io_cb_t; - -// IO devices common control commands -#define IO_SET_CB_RX (0x01) -#define IO_SET_CB_TX (0x02) -#define IO_SET_CB_ERR (0x03) - -/* the following are necessary definitions in embARC_OSP */ -#include "arc/arc_exception.h" -#include "arc/arc_builtin.h" - -#undef _Interrupt -#define _Interrupt - -#define _setvecti(x, y) int_handler_install(x, y); - -#if defined(__GNU__) -#undef _Uncached -#define _Uncached volatile -#define _Usually(x) arc_compiler_usually(x) -#define _sr(x, y) arc_aux_write(y, x) -#define _lr(x) arc_aux_read(x) -#endif - -#undef __Xdmac - -#endif /* H_IOCTL */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/creg_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/creg_master.h deleted file mode 100644 index 769a4e7b..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/creg_master.h +++ /dev/null @@ -1,57 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-2.1.13 - * ========================================================================== */ - -#ifndef H_CREG_MASTER -#define H_CREG_MASTER - -/* Function: io_creg_master_read - * Reads the content of CREG data control register that is current output of CREG bus - * - * Parameters: - * dev_id Identifier of CREG master instance - * reg_val Address that on successful function return contains the value stored in - * data control register - * - */ -extern void io_creg_master_read(uint32_t dev_id, uint32_t *reg_val); - -/* Function: io_creg_master_write - * Writes provided value to CREG data control register to be seen on CREG bus - * - * Parameters: - * dev_id Identifier of CREG master instance - * reg_val The value to be written to data control register. - * - */ -extern void io_creg_master_write(uint32_t dev_id, uint32_t reg_val); - -#endif /* H_CREG_MASTER */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/creg_slave.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/creg_slave.h deleted file mode 100644 index 38c08f1c..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/creg_slave.h +++ /dev/null @@ -1,47 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-2.1.13 - * ========================================================================== */ - -#ifndef H_CREG_SLAVE -#define H_CREG_SLAVE - -/* Function: io_creg_slave_read - * Reads the content of CREG data observation register that is the value seen on CREG bus - * - * Parameters: - * dev_id Identifier of CREG slave instance - * reg_val Address that on successful function return contains the value stored in - * data observation register - * - */ -extern void io_creg_slave_read(uint32_t dev_id, uint32_t *reg_val); - -#endif /* H_CREG_SLAVE */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/gpio.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/gpio.h deleted file mode 100644 index cb2214b7..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/gpio.h +++ /dev/null @@ -1,91 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_GPIO -#define H_GPIO - -#include "device/ip_hal/ioctl.h" - -// convenience macro to get unique device IDs for 32b/8b/4b GPIO; max nr of instances per kind = 4 -#define IO_GPIO_DEV_ID(id, width) (uint8_t)((width == 32) ? (id) : (12 - width + id)) - -#define IO_GPIO_SET_DIRECTION (0x20) -#define IO_GPIO_SET_INT_ENABLE (0x21) -#define IO_GPIO_GET_INT_ENABLE (0x22) -#define IO_GPIO_SET_INT_MASK (0x23) -#define IO_GPIO_GET_INT_MASK (0x24) -#define IO_GPIO_SET_INT_TYPE (0x25) -#define IO_GPIO_SET_INT_POLARITY (0x26) -#define IO_GPIO_SET_INT_BOTHEDGE (0x27) -#define IO_GPIO_SET_DEBOUNCE (0x28) -#define IO_GPIO_GET_DIRECTION (0x29) -#define IO_GPIO_GET_GPO (0x30) - -extern uint32_t io_gpio_open(uint32_t dev_id); -extern void io_gpio_close(uint32_t dev_id); -extern void io_gpio_read(uint32_t dev_id, uint32_t *data); -extern void io_gpio_write(uint32_t dev_id, uint32_t data); - -/* GPIO valid IOCTLs - cmd arg type arg value - IO_SET_CB_RX io_cb_t Callback function invoked from ISR whenever the interrupt is triggered on one of - GPIO inputs configured to operate as interrupts. The callback's argument is initialized - with bitmask where each bit represents corresponding GPIO signal and is set to 1 if - that signal raises interrupt. - IO_GPIO_SET_DIRECTION uint32_t Bitmask, where each bit's value controls the direction of the corresponding GPIO signal as follows: - 0 - input, 1 - output. Default value of the control is zero that corresponds to all signals are inputs - on device opening. - IO_GPIO_SET_INT_ENABLE uint32_t Bitmask, where each bit's value specifies if corresponding GPIO input shall act as interrupt or as a normal - (IO_GPIO_GET_INT_ENABLE) GPIO signal as follows: 0 - normal signal, 1 - interrupt. Default value of the control is zero that corresponds - to all inputs are normal GPIO signals on device opening. - IO_GPIO_SET_INT_MASK uint32_t Bitmask, where each bit's value specifies if corresponding GPIO interrupt signal is masked: - (IO_GPIO_GET_INT_MASK) 0 - unmasked, 1 - masked. Default value of the control is zero that corresponds to - all interrupts are unmasked on device opening. - IO_GPIO_SET_INT_TYPE uint32_t Bitmask, where each bit's value specifies the type of corresponding GPIO interrupt as follows: - 0 - level-sensitive, 1 - edge-sensitive. Default value of the control is zero that corresponds to - all interrupts are level-sensitive on device opening. - IO_GPIO_SET_INT_POLARITY uint32_t Bitmask, where each bit's value specifies the polarity of corresponding GPIO interrupt as follows: - 0 - active-low (falling edge), 1 - active-high(raising edge). Default value of the control is zero - that corresponds to all interrupts are active-low on device opening. - IO_GPIO_SET_INT_BOTHEDGE uint32_t Bitmask, where each bit's value specifies the type of corresponding GPIO interrupt as follows: - 0 - interrupt defined by INT_TYPE and INT_POLARITY, 1 - interrupt edge sensitive for both rising and falling edge - that corresponds to all interrupts are defined by INT_TYPE and INT_POLARITY. - IO_GPIO_SET_DEBOUNCE uint32_t Bitmask, where each bit's value specify if corresponding GPIO signal configured as interrupt source needs - to be debounced as follows: 0 - no debounce, 1 - enable debounce. Default value of the control is zero - that corresponds to all GPIO signals aren't debounced on device opening. - IO_GPIO_GET_DIRECTION uint32_t Same as IO_GPIO_SET_DIRECTION. - IO_GPIO_GET_GPO uint32_t Last value written to the port data register using io_gpio_write() service, does not depend on GPIO direction - settings and can be different compare to data returened by io_gpio_read() service. - */ -extern void io_gpio_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); - -#endif /* H_GPIO */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_master.h deleted file mode 100644 index d04a5a46..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_master.h +++ /dev/null @@ -1,83 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_I2C_MASTER -#define H_I2C_MASTER - -#include "device/ip_hal/ioctl.h" - -/* I2C working speeds. */ -#define I2C_STANDARD_SPEED (0x01) -#define I2C_FAST_SPEED (0x02) - -/* I2C devices common control commands */ -#define IO_I2C_MASTER_SET_HOLD_TIME_RX (0x06) -#define IO_I2C_MASTER_SET_HOLD_TIME_TX (0x07) -#define IO_I2C_MASTER_SET_SPKLEN (0x08) -#define IO_I2C_MASTER_SET_RX_THRESHOLD (0x09) -#define IO_I2C_MASTER_SET_TX_THRESHOLD (0x0a) -#define IO_I2C_MASTER_SET_10BIT_ADDR (0x0b) -/* I2C master control commands */ -#define IO_I2C_MASTER_SET_TARGET_ADDR (0x20) -#define IO_I2C_MASTER_SET_SPEED (0x21) -#define IO_I2C_MASTER_SET_SS_SCL_HCNT (0x22) -#define IO_I2C_MASTER_SET_SS_SCL_LCNT (0x23) -#define IO_I2C_MASTER_SET_FS_SCL_HCNT (0x24) -#define IO_I2C_MASTER_SET_FS_SCL_LCNT (0x25) -#define IO_I2C_MASTER_SET_NEXT_COND (0x26) - -extern uint32_t io_i2c_master_open(uint32_t dev_id); -extern void io_i2c_master_close(uint32_t dev_id); - -/* I2C master valid IOCTLs - cmd arg type arg value - IO_SET_CB_RX io_cb_t Callback function invoked from ISR when read successfully finishes - IO_SET_CB_TX io_cb_t Callback function invoked from ISR when write successfully finishes - IO_SET_CB_ERR io_cb_t Callback function invoked from ISR when read/write fails - IO_I2C_MASTER_SET_HOLD_TIME_RX uint32_t SDA hold delay, in I2C clocks - IO_I2C_MASTER_SET_HOLD_TIME_TX uint32_t SDA hold delay, in I2C clocks - IO_I2C_MASTER_SET_SPKLEN uint32_t Threshold of spike suppression logic counters, in I2C clocks - IO_I2C_MASTER_SET_TARGET_ADDR uint32_t Address of I2C slave device - IO_I2C_MASTER_SET_SPEED uint32_t I2C_STANDARD_SPEED <= 100 kbit/s, I2C_FAST_SPEED <= 400 kbit/s - IO_I2C_MASTER_SET_SS_SCL_HCNT uint32_t SCL high level duration for standard speed, in I2C clocks - IO_I2C_MASTER_SET_SS_SCL_LCNT uint32_t SCL low level duration for standard speed, in I2C clocks - IO_I2C_MASTER_SET_FS_SCL_HCNT uint32_t SCL high level duration for fast speed, in I2C clocks - IO_I2C_MASTER_SET_FS_SCL_LCNT uint32_t SCL low level duration for fast speed, in I2C clocks - IO_I2C_MASTER_SET_RX_THRESHOLD uint32_t threshold level rx fifo - IO_I2C_MASTER_SET_TX_THRESHOLD uint32_t threshold level tx fifo - IO_I2C_MASTER_SET_10BIT_ADDR uint32_t 0 - 7 bit address, 1 - 10 bit address - */ -extern void io_i2c_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); -extern void io_i2c_master_read(uint32_t dev_id, uint8_t *data, uint32_t *size); -extern void io_i2c_master_write(uint32_t dev_id, uint8_t *data, uint32_t *size); - -#endif /* H_I2C_MASTER */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_priv.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_priv.h deleted file mode 100644 index 7aa3985f..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_priv.h +++ /dev/null @@ -1,139 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_I2C_PRIV -#define H_I2C_PRIV - -#include "device/ip_hal/ioctl.h" - -/* EIA I2C device registers */ -#define I2C_CON (0x00) -#define I2C_TAR (0x04) // master only -#define I2C_SAR (0x08) // slave only -#define I2C_DATA_CMD (0x10) -#define I2C_SS_SCL_HCNT (0x14) -#define I2C_SS_SCL_LCNT (0x18) -#define I2C_FS_SCL_HCNT (0x1c) -#define I2C_FS_SCL_LCNT (0x20) -#define I2C_INTR_STAT (0x2c) -#define I2C_INTR_MASK (0x30) -#define I2C_RX_TL (0x38) -#define I2C_TX_TL (0x3c) -#define I2C_CLR_INTR (0x40) -#define I2C_CLR_RX_OVER (0x48) -#define I2C_CLR_TX_OVER (0x4c) -#define I2C_CLR_RD_REQ (0x50) -#define I2C_CLR_TX_ABRT (0x54) -#define I2C_CLR_STOP_DET (0x60) -#define I2C_ENABLE (0x6c) -#define I2C_STATUS (0x70) -#define I2C_TXFLR (0x74) -#define I2C_RXFLR (0x78) -#define I2C_SDA_HOLD (0x7c) -#define I2C_TX_ABRT_SOURCE (0x80) -#define I2C_SDA_SETUP (0x94) // slave only -#define I2C_ENABLE_STATUS (0x9c) -#define I2C_FS_SPKLEN (0xa0) -#define I2C_CLKEN (0xc0) - -/* Interrupt Register Fields */ -#define R_START_DET (0x1 << 10) -#define R_STOP_DET (0x1 << 9) -#define R_ACTIVITY (0x1 << 8) -#define R_RX_DONE (0x1 << 7) -#define R_TX_ABRT (0x1 << 6) -#define R_RD_REQ (0x1 << 5) -#define R_TX_EMPTY (0x1 << 4) -#define R_TX_OVER (0x1 << 3) -#define R_RX_FULL (0x1 << 2) -#define R_RX_OVER (0x1 << 1) -#define R_RX_UNDER (0x1 << 0) - -/* Other macros. */ -#define I2C_RESTART_CMD (0x1 << 10) -#define I2C_STOP_CMD (0x1 << 9) -#define I2C_READ_CMD (0x1 << 8) - -#define DMA_NONE (0xff) - -typedef _Interrupt void (*I2C_ISR) (); - -/* Private data structure maintained by the driver */ -typedef struct i2c_info { - uint32_t reg_base; // base address of device register set - uint8_t instID; - /* TX & RX Buffer and lengths */ - uint8_t *tx_data; - uint32_t tx_size; - uint32_t tx_count; - uint32_t *p_txsize; - uint8_t *rx_data; - uint32_t rx_size; - uint32_t rx_count; - uint32_t *p_rxsize; - uint32_t rx_req_count; - uint8_t handling_tx; - uint8_t handling_rx; - uint8_t stop_detected; - uint8_t rd_req_detected; - uint16_t fifo_depth; - uint16_t dmarxchanid, dmatxchanid; - uint16_t next_cond; -#ifdef __Xdmac - _Uncached uint32_t *dmarxdescriptor, *dmatxdescriptor; - uint16_t dmatx_last; -#endif - /* Callbacks */ - IO_CB_FUNC tx_cb; - IO_CB_FUNC rx_cb; - IO_CB_FUNC err_cb; - /* Interrupt numbers and handlers */ - uint8_t vector_err; - uint8_t vector_rx_avail; - uint8_t vector_tx_req; - uint8_t vector_stop_det; - uint8_t vector_rd_req; // slave only - uint8_t vector_restart_det; // slave only - I2C_ISR isr_err; - I2C_ISR isr_rx_avail; - I2C_ISR isr_tx_req; - I2C_ISR isr_stop_det; - I2C_ISR isr_rd_req; -} i2c_info_t, *i2c_info_pt; - -/* I2C IOCTLs default values */ -#define I2C_SS_SCL_HIGH_COUNT (0x0190) // WHY? hw-default is 0x30 -#define I2C_SS_SCL_LOW_COUNT (0x01d6) // WHY? hw-default is 0x38 -#define I2C_FS_SCL_HIGH_COUNT (0x003c) -#define I2C_FS_SCL_LOW_COUNT (0x0082) - -#endif /* H_I2C_PRIV */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_slave.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_slave.h deleted file mode 100644 index d5a90148..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2c_slave.h +++ /dev/null @@ -1,69 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_I2C_SLAVE -#define H_I2C_SLAVE - -#include "device/ip_hal/ioctl.h" - -/* I2C devices common control commands */ -#define IO_I2C_SLAVE_SET_SETUP_TIME (0x05) -#define IO_I2C_SLAVE_SET_HOLD_TIME_RX (0x06) -#define IO_I2C_SLAVE_SET_HOLD_TIME_TX (0x07) -#define IO_I2C_SLAVE_SET_SPKLEN (0x08) -#define IO_I2C_SLAVE_SET_RX_THRESHOLD (0x09) -#define IO_I2C_SLAVE_SET_TX_THRESHOLD (0x0a) -#define IO_I2C_SLAVE_SET_10BIT_ADDR (0x0b) -/* I2C slave control commands */ -#define IO_I2C_SLAVE_SET_ADDR (0x10) - -extern uint32_t io_i2c_slave_open(uint32_t dev_id); -extern void io_i2c_slave_close(uint32_t dev_id); -/* I2C slave valid IOCTLs - cmd arg type arg value - IO_SET_CB_RX io_cb_t Callback function invoked from ISR when read successfully finishes - IO_SET_CB_TX io_cb_t Callback function invoked from ISR when write successfully finishes - IO_SET_CB_ERR io_cb_t Callback function invoked from ISR when read/write fails - IO_I2C_SLAVE_SET_HOLD_TIME_RX uint32_t SDA hold delay, in I2C clocks - IO_I2C_SLAVE_SET_HOLD_TIME_TX uint32_t SDA hold delay, in I2C clocks - IO_I2C_SLAVE_SET_SETUP_TIME uint32_t SDA setup delay, in I2C clocks - IO_I2C_SLAVE_SET_SPKLEN uint32_t Threshold of spike suppression logic counters, in I2C clocks - IO_I2C_SLAVE_SET_ADDR uint32_t I2C slave address - IO_I2C_SLAVE_SET_RX_THRESHOLD uint32_t threshold level rx fifo - IO_I2C_SLAVE_SET_TX_THRESHOLD uint32_t threshold level tx fifo - IO_I2C_SLAVE_SET_10BIT_ADDR uint32_t 0 - 7 bit address, 1 - 10 bit address - */ -extern void io_i2c_slave_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); -extern void io_i2c_slave_read(uint32_t dev_id, uint8_t *data, uint32_t *size); -extern void io_i2c_slave_write(uint32_t dev_id, uint8_t *data, uint32_t *size); - -#endif /* H_I2C_SLAVE */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2s_rx_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2s_rx_master.h deleted file mode 100644 index 528c1d04..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2s_rx_master.h +++ /dev/null @@ -1,70 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_I2S_RX_MASTER -#define H_I2S_RX_MASTER - -#include "device/ip_hal/ioctl.h" - -/* I2S Rx master IO control commands */ -#define IO_I2S_RX_MASTER_SET_SAMPLE_WIDTH (0x20) -#define IO_I2S_RX_MASTER_SET_FIFO_THRESHOLD (0x21) -#define IO_I2S_RX_MASTER_SET_BITCLOCK (0x22) - -extern uint32_t io_i2s_rx_master_open(uint32_t dev_id); -extern void io_i2s_rx_master_close(uint32_t dev_id); - -/* Function: io_i2s_rx_master_read - * Parameters: - * dev_id [In] Identifier of I2S device instance. - * data [In] Address of input buffer where requested number of acquired samples shall be stored - * size [In/Out] Address of variable that holds input buffer size specifying the number of samples to be acquired. - * On invocation of callback, registerd by IO_SET_CB_RX command, the address contains the number - * of samples actually acquired. - * Returns: - * none - */ -extern void io_i2s_rx_master_read(uint32_t dev_id, uint32_t *data, - uint32_t *size); - -/* I2S valid IOCTLs - cmd arg type arg value - IO_SET_CB_RX io_cb_t Callback function invoked from ISR whenever a series of samples - is available in the buffer provided by io_i2s_rx_master_read - IO_SET_CB_ERR io_cb_t Callback function invoked from ISR whenever input buffer overflow condition whould occur - IO_I2S_RX_MASTER_SET_FIFO_THRESHOLD uint32_t threshold value for the Rx FIFO (accepts command before first io_i2s_rx_master_read) - IO_I2S_RX_MASTER_SET_SAMPLE_WIDTH uint32_t sample width value 16 or 12 bits (accepts command before first io_i2s_rx_master_read) - IO_I2S_RX_MASTER_SET_BITCLOCK uint32_t 0/1 - disable/enable i2s bit clock ans WS (accepts command before first io_i2s_rx_master_read) - */ -extern void io_i2s_rx_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); - -#endif /* H_I2S_RX_MASTER */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2s_tx_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2s_tx_master.h deleted file mode 100644 index 9f861e1f..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/i2s_tx_master.h +++ /dev/null @@ -1,69 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_I2S_TX_MASTER -#define H_I2S_TX_MASTER - -#include "device/ip_hal/ioctl.h" - -/* I2S Tx master IO control commands */ -#define IO_I2S_TX_MASTER_SET_SAMPLE_WIDTH (0x20) -#define IO_I2S_TX_MASTER_SET_FIFO_THRESHOLD (0x21) -#define IO_I2S_TX_MASTER_SET_BITCLOCK (0x22) - -extern uint32_t io_i2s_tx_master_open(uint32_t dev_id); -extern void io_i2s_tx_master_close(uint32_t dev_id); - -/* Function: io_i2s_tx_master_write - * Parameters: - * dev_id [In] Identifier of I2S device instance. - * data [In] Address of output buffer where requested number of samples shall be stored - * size [In/Out] Address of variable that holds input buffer size specifying the number of samples to be acquired. - * On invocation of callback, registerd by IO_SET_CB_TX command, the address contains the number - * of samples actually acquired. - * Returns: - * none - */ -extern void io_i2s_tx_master_write(uint32_t dev_id, uint32_t *data, uint32_t *size); - -/* I2S valid IOCTLs - cmd arg type arg value - IO_SET_CB_TX io_cb_t Callback function invoked from ISR whenever a series of samples - is available in the buffer provided by io_i2s_tx_master_read - IO_SET_CB_ERR io_cb_t Callback function invoked from ISR whenever input buffer overflow condition whould occur - IO_I2S_TX_MASTER_SET_FIFO_THRESHOLD uint32_t threshold value for the Tx FIFO (must be set before actual transmission is started) - IO_I2S_TX_MASTER_SET_SAMPLE_WIDTH uint32_t sample width value 16 or 12 bits (must be set before actual transmission is started) - IO_I2S_TX_MASTER_SET_BITCLOCK uint32_t 0/1 - disable/enable i2s bit clock and WS (must be set before actual transmission is started) - */ -extern void io_i2s_tx_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); - -#endif /* H_I2S_TX_MASTER */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_master.h deleted file mode 100644 index c25c4cff..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_master.h +++ /dev/null @@ -1,118 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_SPI_MASTER -#define H_SPI_MASTER - -#include "device/ip_hal/ioctl.h" -#include "device/ip_hal/dev_spi.h" - -/* SPI control commands */ -#define IO_SPI_MASTER_SET_SRL_MODE (0x20) -#define IO_SPI_MASTER_SET_TRANSFER_MODE (0x21) -#define IO_SPI_MASTER_SET_BAUD (0x22) -#define IO_SPI_MASTER_SET_SCPH (0x23) -#define IO_SPI_MASTER_SET_SCPL (0x24) -#define IO_SPI_MASTER_SET_DFS (0x25) -#define IO_SPI_MASTER_SET_SE (0x26) -#define IO_SPI_MASTER_SET_RX_THRESHOLD (0x28) -#define IO_SPI_MASTER_SET_TX_THRESHOLD (0x29) -#define IO_SPI_MASTER_SET_RX_DELAY (0x2a) -#define IO_SPI_MASTER_SET_PACKING (0x2b) - -#define IO_SPI_MASTER_GET_XFER_SIZE (0x2c) // undocumented: for verification purposes - -/* SPI shift register modes */ -#define SPI_NORMAL_SRL_MODE (0) -#define SPI_TEST_SRL_MODE (1) - -/* SPI transfer modes */ -#define SPI_TRANSMIT_RECEIVE_MODE (0) -#define SPI_TRANSMIT_ONLY_MODE (1) -#define SPI_RECEIVE_ONLY_MODE (2) -#define SPI_EEPROM_RDONLY_MODE (3) -#define SPI_RECEIVE_AFTER_TRANSMIT_MODE (SPI_EEPROM_RDONLY_MODE) - -/* SPI clock phase */ -#define SPI_SCPH_LOW (0) -#define SPI_SCPH_HIGH (1) -/* SPI clock phase */ -#define SPI_SCPOL_LOW (0) -#define SPI_SCPOL_HIGH (1) - -/* SPI Slave Select line codes */ -#define SPI_SE_1 (0x01) -#define SPI_SE_2 (0x02) -#define SPI_SE_3 (0x04) -#define SPI_SE_4 (0x08) - -extern uint32_t io_spi_master_open(uint32_t dev_id); -extern void io_spi_master_close(uint32_t dev_id); -extern void io_spi_master_read(uint32_t dev_id, uint8_t *data, uint32_t *size); -extern void io_spi_master_write(uint32_t dev_id, uint8_t *data, uint32_t *size); -/* I2C master valid IOCTLs - cmd arg type arg value - IO_SET_CB_RX io_cb_t Callback function invoked from ISR when read successfully finishes - IO_SET_CB_TX io_cb_t Callback function invoked from ISR when write successfully finishes - IO_SET_CB_ERR io_cb_t Callback function invoked from ISR when read/write fails - IO_SPI_MASTER_SET_SRL_MODE uint32_t SPI shift register operation mode: - SPI_NORMAL_SRL_MODE - normal operation mode, Tx to Rx register loop disabled - SPI_TEST_SRL_MODE - test operation mode, Tx to Rx register loop enabled - IO_SPI_MASTER_SET_TRANSFER_MODE uint32_t SPI transfer mode: - SPI_TRAMSMIT_RECEIVE_MODE - transmit and receive - SPI_TRANSMIT_ONLY_MODE - transmit only - SPI_RECEIVE_ONLY_MODE - receive only - SPI_EEPROM_RDONLY_MODE - EEPROM read - IO_SPI_MASTER_SET_BAUD uint32_t SPI clock divider corresponding to desired bitrate, in the range from 2 to 65534 - IO_SPI_MASTER_SET_SCPH uint32_t SPI closk phase: - SPI_SCPH_LOW - inactive state of SPI clock is low - SPI_SCPH_HIGH - inactive state of SPI clock is high - IO_SPI_MASTER_SET_SCPL uint32_t SPI clock polarity: - SPI_SCPOL_LOW - SPI clock toggles in middle of first data bit - SPI_SCPOL_HIGH - SPI clock toggles at start of first data bit - IO_SPI_MASTER_SET_DFS uint32_t SPI frame size in bits - IO_SPI_MASTER_SET_SE uint32_t SPI Slave Select line: - SPI_SE_1 - SPI_SE_2 - SPI_SE_3 - SPI_SE_4 - IO_SPI_MASTER_SET_RX_THRESHOLD uint32_t threshold value for the Rx FIFO - IO_SPI_MASTER_SET_TX_THRESHOLD uint32_t threshold value for the Tx FIFO - IO_SPI_MASTER_SET_RX_DELAY uint32_t rx sample delay - IO_SPI_MASTER_SET_PACKING uint32_t 1|0 - enable|disable data packing in Rx/Tx data buffer. - */ - -extern void io_spi_master_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); - -extern void io_spi_master_polling(uint32_t dev_id, DEV_SPI_TRANSFER *xfer); - -#endif /* H_SPI_MASTER */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_priv.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_priv.h deleted file mode 100644 index 4a2e7007..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_priv.h +++ /dev/null @@ -1,111 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_SPI_PRIV -#define H_SPI_PRIV - -#include "device/ip_hal/ioctl.h" - -/* EIA SPI device registers */ -#define CTRL0 (0x00) -#define CTRL1 (0x01) // master only -#define SPIEN (0x02) -#define SER (0x04) // master only -#define BAUDR (0x05) // master only -#define TXFTLR (0x06) -#define RXFTLR (0x07) -#define TXFLR (0x08) -#define RXFLR (0x09) -#define SR (0x0a) -#define IMR (0x0b) -#define ISR (0x0c) -#define RISR (0x0d) -#define TXOICR (0x0e) -#define RXOICR (0x0f) -#define RXUICR (0x10) -#define ICR (0x12) -#define CLK_ENA (0x16) -#define DR (0x18) -#define RX_SAMPLE_DLY (0x3c) // master only - -/* Interrupt Register Fields */ -#define R_IDLE (0x1 << 6) -#define R_TX_UNDER (0x1 << 5) // slave only -#define R_RX_FULL (0x1 << 4) -#define R_RX_OVER (0x1 << 3) -#define R_RX_UNDER (0x1 << 2) -#define R_TX_OVER (0x1 << 1) -#define R_TX_EMPTY (0x1 << 0) - -/* Other macros. */ -#define DMA_NONE (0xff) - -typedef _Interrupt void (*SPI_ISR) (); - -/* Private data structure maintained by the driver. */ -typedef struct spi_info_struct { - uint32_t reg_base; /* base address of device register set */ - uint8_t instID; - /* TX & RX Buffer and lengths */ - uint32_t rx_size; - uint32_t *p_rxsize; - uint32_t rx_count; - void *rx_buff; - uint32_t tx_size; - uint32_t tx_count; - void *tx_buff; - uint8_t handling_rx, handling_tx; - uint16_t log_xfer_size; - uint16_t max_xfer_size; - uint16_t fifo_depth; - uint16_t dmarxchanid, dmatxchanid; -#ifdef __Xdmac - _Uncached uint32_t *dmarxdescriptor, *dmatxdescriptor; /* 2 descriptors each: 2nd one for future use */ - uint16_t dmarx_last16, dmatx_last16; - uint32_t dmarx_last32, dmatx_last32; -#endif - /* Callbacks */ - IO_CB_FUNC tx_cb; - IO_CB_FUNC rx_cb; - IO_CB_FUNC err_cb; - /* Interrupt numbers and handlers */ - uint8_t rx_vector; /* ISR vectors */ - uint8_t tx_vector; - uint8_t err_vector; - uint8_t idle_vector; - SPI_ISR rx_isr; /* SPI device ISRs */ - SPI_ISR tx_isr; - SPI_ISR err_isr; - SPI_ISR idle_isr; -} spi_info_t, *spi_info_pt; - -#endif /* H_SPI_PRIV */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_slave.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_slave.h deleted file mode 100644 index d410d7a8..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/spi_slave.h +++ /dev/null @@ -1,77 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_SPI_SLAVE -#define H_SPI_SLAVE - -#include "device/ip_hal/ioctl.h" - -/* SPI slave control commands */ -#define IO_SPI_SLAVE_SET_SRL_MODE (0x20) -#define IO_SPI_SLAVE_SET_TRANSFER_MODE (0x21) -#define IO_SPI_SLAVE_SET_SCPH (0x23) -#define IO_SPI_SLAVE_SET_SCPL (0x24) -#define IO_SPI_SLAVE_SET_DFS (0x25) -#define IO_SPI_SLAVE_SET_OUTPUT_ENABLE (0x26) -#define IO_SPI_SLAVE_SET_RX_THRESHOLD (0x28) -#define IO_SPI_SLAVE_SET_TX_THRESHOLD (0x29) -#define IO_SPI_SLAVE_SET_PACKING (0x30) - -extern uint32_t io_spi_slave_open(uint32_t dev_id); -extern void io_spi_slave_close(uint32_t dev_id); -/* I2C master valid IOCTLs - cmd arg type arg value - IO_SET_CB_RX io_cb_t Callback function invoked from ISR when read successfully finishes - IO_SET_CB_TX io_cb_t Callback function invoked from ISR when write successfully finishes - IO_SET_CB_ERR io_cb_t Callback function invoked from ISR when read/write fails - IO_SPI_SLAVE_SET_SRL_MODE uint32_t SPI shift register operation mode: - 0 = normal operation mode, Tx to Rx register loop disabled - 1 = test operation mode, Tx to Rx register loop enabled - IO_SPI_SLAVE_SET_TRANSFER_MODE uint32_t SPI transfer mode: - 0 = transmit and receive - 1 = transmit only - 2 = receive only - IO_SPI_SLAVE_SET_SCPH uint32_t SPI closk phase: inactive state of SPI clock is low (0) or high (1) - IO_SPI_SLAVE_SET_SCPL uint32_t SPI clock polarity: SPI clock toggles in middle of first data bit (0) or at start of first data bit (1) - IO_SPI_SLAVE_SET_DFS uint32_t SPI frame size in bits - IO_SPI_SLAVE_SET_OUTPUT_ENABLE uint32_t Enables (1) or disables (0) slave output - IO_SPI_SLAVE_SET_RX_THRESHOLD uint32_t threshold value for the Rx FIFO - IO_SPI_SLAVE_SET_TX_THRESHOLD uint32_t threshold value for the Tx FIFO - IO_SPI_SLAVE_SET_PACKING uint32_t 1|0 = enable|disable data packing in Rx/Tx buffer - - */ - -extern void io_spi_slave_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); -extern void io_spi_slave_read(uint32_t dev_id, uint8_t *data, uint32_t *size); -extern void io_spi_slave_write(uint32_t dev_id, uint8_t *data, uint32_t *size); - -#endif /* H_SPI_SLAVE */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_gpio.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_gpio.h deleted file mode 100644 index ebec8cba..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_gpio.h +++ /dev/null @@ -1,59 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SS_GPIO -#define H_SS_GPIO -/* the wrapper of subsystem gpio driver */ - -#include "device/ip_hal/dev_gpio.h" - -typedef struct ss_gpio_dev_context { - uint32_t reg_base; - - uint8_t dev_id; - uint8_t width; - uint8_t intno; - uint8_t reserved; - - DEV_CALLBACK int_cb; - DEV_GPIO_HANDLER *handlers; - DEV_GPIO_INFO *info; - uint32_t int_bit_type; - uint32_t int_bit_polarity; - uint32_t int_bit_debounce; -} SS_GPIO_DEV_CONTEXT; - -extern int32_t ss_gpio_open(SS_GPIO_DEV_CONTEXT *ctx, uint32_t dir); -extern int32_t ss_gpio_close(SS_GPIO_DEV_CONTEXT *ctx); -extern int32_t ss_gpio_control(SS_GPIO_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param); -extern int32_t ss_gpio_write(SS_GPIO_DEV_CONTEXT *ctx, uint32_t val, uint32_t mask); -extern int32_t ss_gpio_read(SS_GPIO_DEV_CONTEXT *ctx, uint32_t *val, uint32_t mask); -extern void ss_gpio_int_cb(SS_GPIO_DEV_CONTEXT *ctx, void *param); - -#endif /* H_SS_GPIO */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_i2c_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_i2c_master.h deleted file mode 100644 index ddf40ed5..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_i2c_master.h +++ /dev/null @@ -1,81 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SS_I2C_MASTER -#define H_SS_I2C_MASTER -/* the wrapper of subsystem i2c master driver */ - -#include "device/ip_hal/dev_iic.h" - -#define SS_IIC_MASTER_FLAG_TX (1 << 0) /* interrupt tx */ -#define SS_IIC_MASTER_FLAG_RX (1 << 1) /* interrupt rx */ -#define SS_IIC_MASTER_FLAG_BUSY (1 << 2) -#define SS_IIC_MASTER_FLAG_TX_RX (1 << 3) /* both tx and rx */ -#define SS_IIC_MASTER_FLAG_ERROR (1 << 4) - -#define IC_TX_RX_FIFO_SIZE 16 /* TX/RX FIFO size in hardware */ - -/* IIC STATUS register */ -#define IC_STATUS_TFNF (0x02) /* (1 << 1) */ -#define IC_STATUS_RFNE (0x08) /* (1 << 3) */ - -/* interrupt callback routines select macros definitions */ -#define SS_IIC_MASTER_RDY_SND (0x1) /* ready to send callback */ -#define SS_IIC_MASTER_RDY_RCV (0x2) /* ready to receive callback */ - -/** check expressions used in DFSS IIC driver implementation */ -#define SS_IIC_MASTER_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -typedef struct ss_iic_master_dev_context { - uint32_t reg_base; - uint32_t dev_id; /* Device ID */ - - uint8_t int_err; /* Interrupt nunmber ERR */ - uint8_t int_rx_avail; /* Interrupt number RX_AVAIL */ - uint8_t int_tx_req; /* Interrupt TX_REQ */ - uint8_t int_stop_det; /* Interrupt STOP_DET */ - - DEV_CALLBACK int_rx_cb; - DEV_CALLBACK int_tx_cb; - DEV_CALLBACK int_err_cb; - - volatile uint32_t flags; /* flag */ - DEV_IIC_INFO *info; /* IIC device information */ -} SS_IIC_MASTER_DEV_CONTEXT; - -extern int32_t ss_iic_master_close(SS_IIC_MASTER_DEV_CONTEXT *ctx); -extern int32_t ss_iic_master_control(SS_IIC_MASTER_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param); -extern int32_t ss_iic_master_open(SS_IIC_MASTER_DEV_CONTEXT *ctx, uint32_t param); -extern int32_t ss_iic_master_write(SS_IIC_MASTER_DEV_CONTEXT *ctx, const void *data, uint32_t len); -extern int32_t ss_iic_master_read(SS_IIC_MASTER_DEV_CONTEXT *ctx, const void *data, uint32_t len); -extern void ss_iic_master_rx_cb(SS_IIC_MASTER_DEV_CONTEXT *ctx, void *param); -extern void ss_iic_master_tx_cb(SS_IIC_MASTER_DEV_CONTEXT *ctx, void *param); -extern void ss_iic_master_err_cb(SS_IIC_MASTER_DEV_CONTEXT *ctx, void *param); - -#endif /* H_SS_I2C_MASTER */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_i2s_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_i2s_master.h deleted file mode 100644 index d916eb28..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_i2s_master.h +++ /dev/null @@ -1,74 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SS_I2S_MASTER -#define H_SS_I2S_MASTER -/* the wrapper of subsystem i2s master driver */ - -#include "device/ip_hal/dev_i2s.h" - -#define SS_I2S_TX 1 -#define SS_I2S_RX 2 - -#define SS_I2S_MASTER_FLAG_TX (1 << 0) /* interrupt tx */ -#define SS_I2S_MASTER_FLAG_RX (1 << 1) /* interrupt rx */ -#define SS_I2S_MASTER_FLAG_BUSY (1 << 2) - -#define SS_I2S_MASTER_FLAG_TX_ERROR (1 << 5) -#define SS_I2S_MASTER_FLAG_RX_ERROR (1 << 6) - -typedef struct ss_i2s_mst_dev_context { - uint32_t reg_base; - - uint8_t dev_id; - uint8_t io_mode; - - uint8_t int_tx_req; /* Interrupt number of TX_REQ */ - uint8_t int_tx_err; /* Interrupt number of TX_ERR */ - uint8_t int_rx_avil; /* Interrupt number of RX_AVIL */ - uint8_t int_rx_err; /* Interrupt number of RX_ERR */ - - DEV_CALLBACK int_tx_cb; - DEV_CALLBACK int_rx_cb; - DEV_CALLBACK int_err_cb; - - volatile uint32_t flags; /* flag */ - DEV_I2S_INFO_PTR info; -} SS_I2S_MST_DEV_CONTEXT; - -extern int32_t ss_i2s_mst_open(SS_I2S_MST_DEV_CONTEXT *ctx, uint32_t mode, uint32_t param); -extern int32_t ss_i2s_mst_close(SS_I2S_MST_DEV_CONTEXT *ctx); -extern int32_t ss_i2s_mst_read(SS_I2S_MST_DEV_CONTEXT *ctx, void *data, uint32_t len); -extern int32_t ss_i2s_mst_write(SS_I2S_MST_DEV_CONTEXT *ctx, void *data, uint32_t len); -extern int32_t ss_i2s_mst_control(SS_I2S_MST_DEV_CONTEXT *ctx, uint32_t cmd, void *param); -extern void ss_i2s_mst_int_tx_cb(SS_I2S_MST_DEV_CONTEXT *ctx, void *param); -extern void ss_i2s_mst_int_rx_cb(SS_I2S_MST_DEV_CONTEXT *ctx, void *param); -extern void ss_i2s_mst_int_err_cb(SS_I2S_MST_DEV_CONTEXT *ctx, void *param); - -#endif /* H_SS_I2S_MASTER*/ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_spi_master.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_spi_master.h deleted file mode 100644 index 61c6e252..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_spi_master.h +++ /dev/null @@ -1,74 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - - * 1) Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SS_SPI_MASTER -#define H_SS_SPI_MASTER - -/* the wrapper of subsystem spi master driver */ - -#include "device/ip_hal/dev_spi.h" - -#define SS_SPI_MASTER_FLAG_TX_READY (1 << 0) /* interrupt tx */ -#define SS_SPI_MASTER_FLAG_RX_READY (1 << 1) /* interrupt rx */ -#define SS_SPI_MASTER_FLAG_BUSY (1 << 2) -#define SS_SPI_MASTER_FLAG_TX_RX (1 << 3) /* both tx and rx */ -#define SS_SPI_MASTER_FLAG_ERROR (1 << 4) - -typedef struct ss_spi_master_dev_context { - uint32_t reg_base; - uint32_t dev_id; - - uint8_t intno_rx; - uint8_t intno_tx; - uint8_t intno_idle; - uint8_t intno_err; - - uint32_t bus_freq; - volatile uint32_t flags; - - DEV_CALLBACK int_rx_cb; - DEV_CALLBACK int_tx_cb; - DEV_CALLBACK int_err_cb; - DEV_SPI_INFO *info; -} SS_SPI_MASTER_DEV_CONTEXT; - -extern int32_t ss_spi_master_open(SS_SPI_MASTER_DEV_CONTEXT *ctx, uint32_t mode, uint32_t param); -extern int32_t ss_spi_master_close(SS_SPI_MASTER_DEV_CONTEXT *ctx); -extern int32_t ss_spi_master_control(SS_SPI_MASTER_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param); -extern int32_t ss_spi_master_write(SS_SPI_MASTER_DEV_CONTEXT *ctx, const void *data, uint32_t len); -extern int32_t ss_spi_master_read(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *data, uint32_t len); -extern void ss_spi_master_tx_cb(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *param); -extern void ss_spi_master_rx_cb(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *param); -extern void ss_spi_master_err_cb(SS_SPI_MASTER_DEV_CONTEXT *ctx, void *param); - -#endif /* H_SS_SPI_MASTER */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_spi_slave.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_spi_slave.h deleted file mode 100644 index 2ec021fd..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_spi_slave.h +++ /dev/null @@ -1,39 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - - * 1) Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SS_SPI_SLAVE -#define H_SS_SPI_SLAVE - -/* the wrapper of subsystem spi slave driver */ - -#endif /* H_SS_SPI_SLAVE */ diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_uart.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_uart.h deleted file mode 100644 index 8359e457..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/ss_uart.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#ifndef H_SS_UART -#define H_SS_UART -/* the wrapper of subsystem uart driver */ - -#include "device/ip_hal/dev_uart.h" - -#define SS_UART_FLAG_TX (1 << 0) /* interrupt tx */ -#define SS_UART_FLAG_RX (1 << 1) /* interrupt rx */ -#define SS_UART_FLAG_BUSY (1 << 2) -#define SS_UART_FLAG_TX_RX (1 << 3) /* both tx and rx */ -#define SS_UART_FLAG_ERROR (1 << 4) - -typedef struct ss_uart_dev_context { - uint32_t reg_base; - uint8_t dev_id; - - uint8_t intno; - volatile uint16_t flags; - - uint32_t bus_freq; - - DEV_CALLBACK tx_cb; - DEV_CALLBACK rx_cb; - DEV_CALLBACK err_cb; - - DEV_UART_INFO *info; -} SS_UART_DEV_CONTEXT; - -extern int32_t ss_uart_open(SS_UART_DEV_CONTEXT *ctx, uint32_t baud); -extern int32_t ss_uart_close(SS_UART_DEV_CONTEXT *ctx); -extern int32_t ss_uart_control(SS_UART_DEV_CONTEXT *ctx, uint32_t ctrl_cmd, void *param); -extern int32_t ss_uart_write(SS_UART_DEV_CONTEXT *ctx, const void *data, uint32_t len); -extern int32_t ss_uart_read(SS_UART_DEV_CONTEXT *ctx, void *data, uint32_t len); -extern void ss_uart_tx_cb(SS_UART_DEV_CONTEXT *ctx, void *param); -extern void ss_uart_rx_cb(SS_UART_DEV_CONTEXT *ctx, void *param); -extern void ss_uart_err_cb(SS_UART_DEV_CONTEXT *ctx, void *param); - -#endif /* H_SS_UART */ \ No newline at end of file diff --git a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/uart.h b/platform/vendor_bsp/embarc_bsp/include/device/subsystem/uart.h deleted file mode 100644 index e1c4ab8f..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/device/subsystem/uart.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ========================================================================== - * Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and - * documentation (hereinafter, "Software") is an Unsupported proprietary work - * of Synopsys, Inc. unless otherwise expressly agreed to in writing between - * Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -/*========================================================================== - * Library DW_DFSS-1.1.6 - * ========================================================================== */ - -#ifndef H_UART -#define H_UART - -#include "device/ip_hal/ioctl.h" - -/* UART control commands */ -#define IO_UART_SET_LCR (0x20) -#define IO_UART_GET_LCR (0x21) -#define IO_UART_SET_DLx (0x22) -#define IO_UART_GET_DLx (0x23) -#define IO_UART_SET_RX_THRESHOLD (0x24) -#define IO_UART_SET_TX_THRESHOLD (0x25) -#define IO_UART_SET_FLOW_CONTROL (0x26) - -extern uint32_t io_uart_open(uint32_t dev_id); -extern void io_uart_close(uint32_t dev_id); -extern void io_uart_read(uint32_t dev_id, uint8_t *data, uint32_t *size); -extern void io_uart_write(uint32_t dev_id, uint8_t *data, - uint32_t *size); -/* UART valid IOCTLs - cmd arg type arg value - IO_SET_CB_RX io_cb_t Callback function invoked from ISR when read successfully finishes - IO_SET_CB_TX io_cb_t Callback function invoked from ISR when write successfully finishes - IO_SET_CB_ERR io_cb_t Callback function invoked from ISR when read/write fails - IO_UART_SET_LCR uint32_t 7 bits LCR[6:0] = { BC, Stick Parity, EPS, PEN, STOP, DLS[1:0] } - IO_UART_GET_LCR uint32_t 7 bits LCR[6:0] = { BC, Stick Parity, EPS, PEN, STOP, DLS[1:0] } - IO_UART_SET_DLx uint32_t 16 bits DLH[7:0];DLL[7:0] - IO_UART_GET_DLx uint32_t 16 bits DLH[7:0];DLL[7:0] - IO_UART_SET_RX_THRESHOLD uint32_t 2 bits encoding the rx-fifo (if any) threshold - IO_UART_SET_TX_THRESHOLD uint32_t 2 bits encoding the tx-fifo (if any) threshold - IO_UART_SET_FLOW_CONTROL uint32_t 0 - disable flow control; 1 - enable flow control - */ -extern void io_uart_ioctl(uint32_t dev_id, uint32_t cmd, void *arg); - -#endif /* H_UART */ diff --git a/platform/vendor_bsp/embarc_bsp/include/embARC.h b/platform/vendor_bsp/embarc_bsp/include/embARC.h deleted file mode 100644 index 27fab616..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/embARC.h +++ /dev/null @@ -1,78 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup CORE_ERROR - * @brief header files wrapper - */ -#ifndef H_EMBARC -#define H_EMBARC - -/* toolchain definition */ -#include "embARC_toolchain.h" - -/* error code related definitions */ -#include "embARC_error.h" - -/* ARC HAL */ -#include "arc/arc_builtin.h" -#include "arc/arc_timer.h" -#include "arc/arc_exception.h" -#if ARC_FEATURE_ICACHE_PRESENT || ARC_FEATURE_DCACHE_PRESENT -#include "arc/arc_cache.h" -#endif -#if ARC_FEATURE_DMAC_PRESENT -#include "arc/arc_udma.h" -#endif -#if ARC_FEATURE_MPU_PRESENT -#include "arc/arc_mpu.h" -#endif -#if ARC_FEATURE_CONNECT_PRESENT -#include "arc/arc_connect.h" -#endif -#include "arc/arc_mp.h" -#if ARC_FEATURE_XY_MEM -#include "arc/arc_xy_agu.h" -#endif - -/* boards */ -#include "board.h" - -/* libraries */ -#ifdef LIB_CONSOLE -#include "console/console_io.h" -#include "console/xprintf/xprintf.h" -#endif -#ifdef LIB_CLIB -#include "clib/embARC_syscalls.h" -#endif - -#endif /* H_EMBARC */ diff --git a/platform/vendor_bsp/embarc_bsp/include/embARC_assert.h b/platform/vendor_bsp/embarc_bsp/include/embARC_assert.h deleted file mode 100644 index 6fbe3f27..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/embARC_assert.h +++ /dev/null @@ -1,94 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup EMBARC_ASSERT - * @brief Necessary definitions of assert - */ - -#ifndef H_EMBARC_ASSERT -#define H_EMBARC_ASSERT - -#include "embARC_debug.h" - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#include "embARC_toolchain.h" - -extern void _exit_loop(); - -#define ASSERT_FORMAT "%s: Line %d: assert(%s) failed.\r\n" -#define HALT_FORMAT "%s: Line %d: halt reason:" - -/** - * @fn void embARC_abort(void) - * @brief Abort current execution - * processor will jump to _exit_loop - */ -Inline void embARC_abort(void) -{ - _exit_loop(); -} - -/** - * @fn void embARC_assert(const char *exptext, const char *file, uint32_t line) - * @brief Output assert message - * - * @param exptext Expression text - * @param file File name - * @param line Line number - */ -Inline void embARC_assert(const char *exptext, const char *file, uint32_t line) -{ - EMBARC_PRINTF(ASSERT_FORMAT, file, line, exptext); - _exit_loop(); -} - -/* check whether the expr is true */ -#define EMBARC_ASSERT(expr) \ - ((void)(!(expr) ? (embARC_assert(#expr, __FILE__, __LINE__), 0) : 0)) - -#define EMBARC_HALT(fmt, ...) ({ \ - EMBARC_PRINTF(HALT_FORMAT, __FILE__, __LINE__); \ - EMBARC_PRINTF(fmt, ##__VA_ARGS__); \ - EMBARC_PRINTF("\r\n"); \ - _exit_loop(); \ - }) - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_EMBARC_ASSERT */ diff --git a/platform/vendor_bsp/embarc_bsp/include/embARC_debug.h b/platform/vendor_bsp/embarc_bsp/include/embARC_debug.h deleted file mode 100644 index fff46ba5..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/embARC_debug.h +++ /dev/null @@ -1,104 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup EMBARC_DEBUG - * @brief Necessary definitions of debug - */ - -#ifndef H_EMBARC_DEBUG -#define H_EMBARC_DEBUG - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -/* comment this to disable exception readable dumping. - * By doing so could save some code space - */ -#ifndef CONFIG_ARC_EXCEPTION_DEBUG -#define CONFIG_ARC_EXCEPTION_DEBUG -#endif - -#ifndef EMBARC_PRINTF - #ifdef LIB_CONSOLE - #include "console/xprintf/xprintf.h" - #define EMBARC_PRINTF xprintf - #else - #include - #define EMBARC_PRINTF printf - #endif -#endif - -/* - * if you want to use DBG or dbg_printf, - * please define DEBUG or DBG_LESS or DBG_MORE before include embARC_debug.h - * DEBUG: enable debug print - * DBG_LESS: enable less debug msg - * DBG_MORE: enable more debug msg - **/ - -#if defined(DEBUG) -#if defined(DEBUG_HOSTLINK) -#include -#define DBG(fmt, ...) printf(fmt, ##__VA_ARGS__) -#else -#define DBG(fmt, ...) EMBARC_PRINTF(fmt, ##__VA_ARGS__) -#endif -#else -#define DBG(fmt, ...) -#endif - -#define DBG_LESS_INFO 0x01 /* less debug messages */ -#define DBG_MORE_INFO 0x02 /* more debug messages */ - -#if defined (DBG_LESS) -#define DBG_TYPE (DBG_LESS_INFO) -#elif defined (DBG_MORE) -#define DBG_TYPE ((DBG_LESS_INFO) | (DBG_MORE_INFO)) -#else -#define DBG_TYPE 0 -#endif - -#if DBG_TYPE > 0 -#define dbg_printf(type, fmt, ...) \ - if (((type) & DBG_TYPE)) { EMBARC_PRINTF(fmt, ##__VA_ARGS__); } -#else -#define dbg_printf(type, fmt, ...) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_EMBARC_DEBUG */ diff --git a/platform/vendor_bsp/embarc_bsp/include/embARC_error.h b/platform/vendor_bsp/embarc_bsp/include/embARC_error.h deleted file mode 100644 index 20b56a3b..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/embARC_error.h +++ /dev/null @@ -1,154 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup EMBARC_ERROR - * @brief Common definitions for error management - */ - -/** - * @addtogroup EMBARC_ERROR - * @{ - */ - -#ifndef H_EMBARC_ERROR -#define H_EMBARC_ERROR - -#include -#include "arc/arc_builtin.h" - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif -/** - * @name Main Error Code Definitions - * @{ - */ -#define E_OK (0) /*!< ok */ -#define E_SYS (-5) /*!< system error */ -#define E_NOSPT (-9) /*!< unsupported features */ -#define E_RSFN (-10) /*!< reserved function code */ -#define E_RSATR (-11) /*!< reserved attribute */ -#define E_PAR (-17) /*!< parameter error */ -#define E_ID (-18) /*!< invalid ID number */ -#define E_CTX (-25) /*!< context error */ -#define E_MACV (-26) /*!< memory access violation */ -#define E_OACV (-27) /*!< object access violation */ -#define E_ILUSE (-28) /*!< illegal service call use */ -#define E_NOMEM (-33) /*!< insufficient memory */ -#define E_NOID (-34) /*!< no ID number available */ -#define E_NORES (-35) /*!< no resource available */ -#define E_OBJ (-41) /*!< object state error */ -#define E_NOEXS (-42) /*!< non-existent object */ -#define E_QOVR (-43) /*!< queue overflow */ -#define E_RLWAI (-49) /*!< forced release from waiting */ -#define E_TMOUT (-50) /*!< polling failure or timeout */ -#define E_DLT (-51) /*!< waiting object deleted */ -#define E_CLS (-52) /*!< waiting object state changed */ -#define E_WBLK (-57) /*!< non-blocking accepted */ -#define E_BOVR (-58) /*!< buffer overflow */ -#define E_OPNED (-6) /*!< device is opened */ -#define E_CLSED (-7) /*!< device is closed */ -/** @} end of name */ - -/** - * @name Generate And Decompose Error Code - * @{ - */ -#ifndef ERCD -/** generate error code using main error code and sub error code */ -#define ERCD(mercd, sercd) \ - ((uint32_t)((((uint32_t) sercd) << 8) | (((uint32_t) mercd) & 0xffU))) -#endif /* ERCD */ - -#ifndef MERCD -#ifdef INT8_MAX -/** get main error code from error code */ -#define MERCD(ercd) ((uint32_t)((int8_t)(ercd))) -#else /* INT8_MAX */ -/** get main error code from error code */ -#define MERCD(ercd) ((uint32_t)(((uint32_t) ercd) | ~0xffU)) -#endif /* INT8_MAX */ -#endif /* MERCD */ - -#ifndef SERCD -/** get sub error code from error code */ -#define SERCD(ercd) ((uint32_t)((ercd) >> 8)) -#endif /* SERCD */ -/** @} end of name */ - -/** - * @name Check Error - * @{ - */ -/** - * @brief Check an expression to see if it is right, and when error - * set the ercd, and goto exit_label - * @param EXPR Expression that need to be checked (==0 failed) - * @param _ERCD MUST pass a variable to here to get the error code - * @param ERROR_CODE Error code that pass to _ERCD - * @param EXIT_LABEL Label to go when error happens - */ -#define CHECK_EXP(EXPR, _ERCD, ERROR_CODE, EXIT_LABEL) { \ - if (arc_compiler_rarely(!(EXPR))) { \ - _ERCD = (ERROR_CODE); \ - goto EXIT_LABEL; \ - } \ -} -/** - * @brief Check an expression to see if it is right, and when error - * directly goto exit_label - * @param EXPR Expression that need to be checked (==0 failed) - * @param EXIT_LABEL Label to go when error happens - */ -#define CHECK_EXP_NOERCD(EXPR, EXIT_LABEL) { \ - if (arc_compiler_rarely(!(EXPR))) { \ - goto EXIT_LABEL; \ - } \ -} -/** check cnt bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_BYTES(pointer, cnt) ((((uint32_t)(pointer)) & (cnt - 1)) == 0) -/** check 2 bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_2BYTES(pointer) ((((uint32_t)(pointer)) & 0x1) == 0) -/** check 4 bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_4BYTES(pointer) ((((uint32_t)(pointer)) & 0x3) == 0) -/** check 8 bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_8BYTES(pointer) ((((uint32_t)(pointer)) & 0x7) == 0) -/** @} end of name */ - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* H_EMBARC_ERROR */ -/** @} end of group EMBARC_ERROR */ diff --git a/platform/vendor_bsp/embarc_bsp/include/embARC_test.h b/platform/vendor_bsp/embarc_bsp/include/embARC_test.h deleted file mode 100644 index e4ae2350..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/embARC_test.h +++ /dev/null @@ -1,174 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/* Copyright 2011,2012 Bas van den Berg - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * @file - * @ingroup EMBARC_TEST - * @brief a light unit test framework based on CTest and Contiki App Unittest - */ - -/** - * @addtogroup EMBARC_TEST - * @{ - */ -#ifndef H_EMBARC_TEST -#define H_EMBARC_TEST -#include "embARC_toolchain.h" - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -typedef void (*TEST_SETUP_FUNC_T)(void *); /*!< setup function before test case */ -typedef void (*TEST_TEARDOWN_FUNC_T)(void *); /*!< teardown function after test case */ - -/** - * @brief Unit test structure - */ -struct unit_test { - const char *ssname; /*!< test suite name */ - const char *ttname; /*!< test case name */ - void (*run)(); /*!< test case function */ - int32_t skip; /*!< whether to skip ? */ - - void *data; /*!< data to test function */ - TEST_SETUP_FUNC_T setup; /*!< setup function */ - TEST_TEARDOWN_FUNC_T teardown; /*!< teardown function */ - - uint32_t magic; /*!< magic number to identify test case */ -}; - -#define US_FNAME(sname, tname) unit_test_##sname##_##tname##_run /*!< generate test case function name */ -#define US_TNAME(sname, tname) unit_test_##sname##_##tname /*!< generate structure name */ -#define US_UNIT_TEST_MAGIC (0xdeadbeef) - -/** all unit test data will be placed in a special data section .data.unittest */ -#define US_UNIT_TEST_SECTION __attribute__ ((used, section(".embarc_unittest"))) - -#define US_UNIT_TEST_STRUCT(sname, tname, _skip, __data, __setup, __teardown) \ - static struct unit_test US_TNAME(sname, tname) US_UNIT_TEST_SECTION = { \ - .ssname =#sname, \ - .ttname =#tname, \ - .run = US_FNAME(sname, tname), \ - .skip = _skip, \ - .data = __data, \ - .setup = (TEST_SETUP_FUNC_T)__setup, \ - .teardown = (TEST_TEARDOWN_FUNC_T)__teardown, \ - .magic = US_UNIT_TEST_MAGIC }; - -/** data wrapper of test suite */ -#define UNIT_TEST_DATA(sname) struct sname##_data - -/** setup function of test suite */ -#define UNIT_TEST_SETUP(sname) \ - void EMBARC_WEAK sname##_setup(struct sname##_data *data) -/** teardown function of test suite */ -#define UNIT_TEST_TEARDOWN(sname) \ - void EMBARC_WEAK sname##_teardown(struct sname##_data *data) - -/** naming macros of setup and tear down functions */ -#define SETUP_FNAME(sname) sname##_setup -#define TEARDOWN_FNAME(sname) sname##_teardown - -#define US_UNIT_TEST_INTERNAL(sname, tname, _skip) \ - static void US_FNAME(sname, tname)(); \ - US_UNIT_TEST_STRUCT(sname, tname, _skip, NULL, NULL, NULL) \ - static void US_FNAME(sname, tname)() - -#define US_UNIT_TEST2_INTERNAL(sname, tname, _skip) \ - static struct sname##_data __unit_test_##sname##_data; \ - UNIT_TEST_SETUP(sname); \ - UNIT_TEST_TEARDOWN(sname); \ - static void US_FNAME(sname, tname)(struct sname##_data *data); \ - US_UNIT_TEST_STRUCT(sname, tname, _skip, &__unit_test_##sname##_data, SETUP_FNAME(sname), TEARDOWN_FNAME(sname)) \ - static void US_FNAME(sname, tname)(struct sname##_data *data) - -#define UNIT_TEST(sname, tname) US_UNIT_TEST_INTERNAL(sname, tname, 0) -#define UNIT_TEST_SKIP(sname, tname) US_UNIT_TEST_INTERNAL(sname, tname, 1) - -#define UNIT_TEST2(sname, tname) US_UNIT_TEST2_INTERNAL(sname, tname, 0) -#define UNIT_TEST2_SKIP(sname, tname) US_UNIT_TEST2_INTERNAL(sname, tname, 1) - -/** check macros for unit test */ -extern void unit_test_assert_str(const char *expect, const char *real, const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_STR(expect, real) unit_test_assert_str(expect, real, __FILE__, __LINE__) - -extern void unit_test_assert_data( \ - const uint8_t *expect, int32_t expsize, \ - const uint8_t *real, int32_t realsize, \ - const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_DATA(expect, expsize, real, realsize) \ - unit_test_assert_data(expect, expsize, real, realsize, __FILE__, __LINE__) - -extern void unit_test_assert_equal(int32_t expect, int32_t real, const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_EQUAL(expect, real) unit_test_assert_equal(expect, real, __FILE__, __LINE__) - -extern void unit_test_assert_not_equal(int32_t expect, int32_t real, const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_NOT_EQUAL(expect, real) unit_test_assert_not_equal(expect, real, __FILE__, __LINE__) - -extern void unit_test_assert_null(void *real, const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_NULL(real) unit_test_assert_null((void *)real, __FILE__, __LINE__) - -extern void unit_test_assert_not_null(const void *real, const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_NOT_NULL(real) unit_test_assert_not_null(real, __FILE__, __LINE__) - -extern void unit_test_assert_true(int32_t real, const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_TRUE(real) unit_test_assert_true(real, __FILE__, __LINE__) - -extern void unit_test_assert_false(int32_t real, const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_FALSE(real) unit_test_assert_false(real, __FILE__, __LINE__) - -extern void unit_test_assert_fail(const char *caller, int32_t line); -#define UNIT_TEST_ASSERT_FAIL() unit_test_assert_fail(__FILE__, __LINE__) - -extern int32_t unit_test_run(const char *test_suite); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /*H_EMBARC_TEST */ -/** @} end of group EMBARC_TEST */ diff --git a/platform/vendor_bsp/embarc_bsp/include/embARC_toolchain.h b/platform/vendor_bsp/embarc_bsp/include/embARC_toolchain.h deleted file mode 100644 index 230ff861..00000000 --- a/platform/vendor_bsp/embarc_bsp/include/embARC_toolchain.h +++ /dev/null @@ -1,143 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup TOOLCHAIN - * @brief Toolchain dependent definitions - */ - -/** - * @addtogroup TOOLCHAIN - * @{ - */ - -#ifndef H_EMBARC_TOOLCHAIN -#define H_EMBARC_TOOLCHAIN - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" { -#endif - -#include /* C99 standard lib */ -#include /* C99 standard lib */ -#include /* C99 standard lib */ -#include /* C99 standard lib */ - -/* - * macro definitions of compiler extend function - */ -#ifndef __cplusplus /* C++ supports inline */ -#if __STDC_VERSION__ < 199901L /* C99 supports inline */ -#define inline __inline__ /* inline function */ -#endif /* __STDC_VERSION__ < 199901L */ -#endif /* __cplusplus */ - -#define Inline static inline /* inline function */ - -#define Asm __asm__ volatile /* inline asm (no optimization) */ - -/* compiler attributes */ -#define EMBARC_FORCEINLINE __attribute__((always_inline)) -#define EMBARC_NOINLINE __attribute__((noinline)) -#define EMBARC_PACKED __attribute__((packed)) -#define EMBARC_WEAK __attribute__((weak)) -#define EMBARC_ALIAS(f) __attribute__((weak, alias(#f))) -#define EMBARC_LINKTO(f) __attribute__((alias(#f))) -#define EMBARC_NORETURN __attribute__((noreturn)) -#define EMBARC_NAKED __attribute__((naked)) /* function without return */ -#define EMBARC_ALIGNED(x) __attribute__((aligned(x))) - -/* array count macro */ -#define EMBARC_ARRAY_COUNT(x) (sizeof(x) / sizeof(x[0])) - -/* convert macro argument to string - * note: this needs one level of indirection, accomplished with the helper macro - * US_EMBARC_TO_STRING - */ -#define US_EMBARC_TO_STRING(x) #x -#define EMBARC_TO_STRING(x) US_EMBARC_TO_STRING(x) -#define EMBARC_CLZ(x) (x == 0 ? 32 : __builtin_clz(x)) -#define EMBARC_BITS(x) (32 - EMBARC_CLZ(x)) -/* x must be > 0 */ -#define EMBARC_POW2_CEIL(x) ((1 << (31 - EMBARC_CLZ(x))) < x ? \ - 1 << (31 - EMBARC_CLZ(x) + 1) : \ - 1 << (31 - EMBARC_CLZ(x))) - -#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) - -#if defined(__GNU__) -/* GNU tool specific definitions */ - -/** - * @brief call c++ class constructors - * - */ -extern void arc_gnu_do_global_ctors_aux(void); - -/** - * @brief call c++ initialization arrary - * - */ -extern void arc_gnu_do_init_array_aux(void); - -/** - * @brief call c++ class deconstructors - * - */ -extern void arc_gnu_do_global_dtors_aux(void); - -#elif defined(__MW__) -/* Metaware tool specific definitions */ -/* Metaware toolchain related definitions */ -/** - * @brief call c++ related initialization - * - */ -extern void arc_mwdt_init(void); - -/** - * @brief call c++ related finish processing - * - */ -extern void arc_mwdt_fini(void); - -#else -#error "unsupported toolchain" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* H_EMBARC_TOOLCHAIN */ -/** @} */ diff --git a/platform/vendor_bsp/embarc_bsp/library/clib/embARC_sbrk.c b/platform/vendor_bsp/embarc_bsp/library/clib/embARC_sbrk.c deleted file mode 100644 index 091f6f10..00000000 --- a/platform/vendor_bsp/embarc_bsp/library/clib/embARC_sbrk.c +++ /dev/null @@ -1,106 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include -#include -#include -#include -#include -#include "clib/embARC_syscalls.h" - -#ifndef _HOSTLINK_ /* Not using hostlink library */ - -/* Memory Management */ -/** Allocating Memory */ -#define EMBARC_WITH_MWSBRK - -/* Whether heap has been initialized. */ -#if defined(__MW__) && defined(EMBARC_WITH_MWSBRK) - -static int32_t __heap_init = 0; -static char *__heap_end, *__heap_cur; -extern char _f_heap[]; -extern char _e_heap[]; - -/** Allocating Memory */ -void *SYSCALL_PREFIX(_sbrk)(uint32_t size){ - char *new_cur; - - if (__heap_init == 0) { - __heap_cur = _f_heap; - __heap_end = _e_heap; - __heap_init = 1; - } - new_cur = __heap_cur + size; - if (__heap_cur <= new_cur && new_cur <= __heap_end) { - void *p = (void *)__heap_cur; - __heap_cur = new_cur; - return (void *)p; /** return old __heap_cur */ - } - - return NULL; -} - -/** Freeing Memory */ -void *SYSCALL_PREFIX(_brk)(void *p){ - __heap_cur = p; - return NULL; -} - -#pragma weak sbrk = _sbrk -#pragma weak brk = _brk - -#elif defined(__GNU__) - -extern char __start_heap; -extern char __end_heap; - -caddr_t *SYSCALL_PREFIX(_sbrk)(size_t nbytes){ - static char *heap_ptr = NULL; - char *prev_heap_ptr; - - if (heap_ptr == NULL) { - heap_ptr = &__start_heap; - } - - /* Align the 'heap_ptr' so that memory will always be allocated at word - boundaries. */ - heap_ptr = (char *) ((((uint32_t) heap_ptr) + 7) & ~7); - prev_heap_ptr = heap_ptr; - - if ((heap_ptr + nbytes) < &__end_heap) { - heap_ptr += nbytes; - return (caddr_t *) prev_heap_ptr; - } - errno = ENOMEM; - return (caddr_t *) -1; -} -#endif - -#endif /* !defined(_HOSTLINK_) */ diff --git a/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.c b/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.c deleted file mode 100644 index ab99e617..00000000 --- a/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.c +++ /dev/null @@ -1,184 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef __GNU__ -#include -#include -#include -#include -#endif - -#include "clib/embARC_syscalls.h" -#include "embARC_debug.h" -#include "embARC.h" - -/** - * @todo Consider hostlink and nsim support - */ - -#ifndef _HOSTLINK_ /* Not using hostlink library */ - -#ifndef BOARD_CONSOLE_UART_ID -#define BOARD_CONSOLE_UART_ID 1 -#endif - -#ifndef BOARD_CONSOLE_UART_BAUD -#define BOARD_CONSOLE_UART_BAUD UART_BAUDRATE_115200 -#endif - -#ifndef EMBARC_CFG_STDIO_CRLF -#define EMBARC_CFG_STDIO_CRLF 1 -#endif - -#define STDIO_FID_OFS 3 - -static int32_t stdio_uart_inited = 0; -static DEV_UART *stdio_uart_obj; - -/** - * @brief Initialize the uart used for stdio - * - */ -static void init_stdio_serial(void) -{ - if (stdio_uart_inited) { - return; - } - stdio_uart_inited = 1; - stdio_uart_obj = uart_get_dev(BOARD_CONSOLE_UART_ID); - if (stdio_uart_obj) { - stdio_uart_obj->uart_open(BOARD_CONSOLE_UART_BAUD); - stdio_uart_obj->uart_control(UART_CMD_SET_BAUD, CONV2VOID(BOARD_CONSOLE_UART_BAUD)); - } else { - stdio_uart_inited = -1; - } -} - -/** - * @brief Read stdio - * - * @param buffer Buffer to read - * @param length Length to read - * @return real Data's number - */ -static int32_t stdio_read(char *buffer, uint32_t length) -{ - if (!stdio_uart_obj) { - return -1; - } - uint32_t avail_len; - stdio_uart_obj->uart_control(UART_CMD_GET_RXAVAIL, (void *)(&avail_len)); - length = (length < avail_len) ? length : avail_len; - if (length == 0) { - length = 1; - } - - return stdio_uart_obj->uart_read((void *)buffer, (uint32_t)length); -} - -/** - * @brief Write char into stdio - * - * @param data Data to write; - */ -static void stdio_write_char(char data) -{ - char val = data; - - stdio_uart_obj->uart_write((const void *)(&val), 1); -} - -/** - * @brief Write data into stdio - * - * @param buffer Data to write - * @param length Data length - * @return Written data number - */ -static int32_t stdio_write(const char *buffer, uint32_t length) -{ - if (!stdio_uart_obj) { - return -1; - } - -#if EMBARC_CFG_STDIO_CRLF - int32_t i = 0; - while (i < length) { - if (arc_compiler_rarely(buffer[i] == '\n')) { - stdio_write_char('\r'); - } - stdio_write_char(buffer[i]); - i++; - } - return i; -#else - return stdio_uart_obj->uart_write((const void *)buffer, (uint32_t)length); -#endif -} - -/** - * @brief _read for C library - * - */ -int32_t SYSCALL_PREFIX(_read)(int32_t handle, char *buffer, uint32_t length){ - if (handle < STDIO_FID_OFS) { - init_stdio_serial(); - return stdio_read(buffer, length); - } - return -1; -} - -/** - * @brief _write for C library - * - */ -int32_t SYSCALL_PREFIX(_write)(int32_t handle, const char *buffer, uint32_t length){ - if (handle < STDIO_FID_OFS) { - init_stdio_serial(); - return stdio_write(buffer, length); - } - return -1; -} - -#if __MW__ -#pragma weak read = _read -#pragma weak write = _write -#endif - -#endif /* !defined(_HOSTLINK_) */ diff --git a/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.h b/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.h deleted file mode 100644 index 524d4841..00000000 --- a/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.h +++ /dev/null @@ -1,58 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @ingroup EMBARC_SYSCALL - * @brief Header file for syscall - */ -#ifndef H_EMBARC_SYSCALLS -#define H_EMBARC_SYSCALLS - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(__GNU__) && !defined(_HAVE_LIBGLOSS_) -/* _HAVE_LIBGLOSS_ is defined in options/toolchain/toolchain_gnu.mk */ -#include -#define SYSCALL_PREFIX(x) syscall##x - -#endif /* __GNU__ && !_HAVE_LIBGLOSS_ */ - -#ifndef SYSCALL_PREFIX -#define SYSCALL_PREFIX(x) x -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* H_EMBARC_SYSCALLS */ diff --git a/platform/vendor_bsp/embarc_bsp/library/console/console_io.c b/platform/vendor_bsp/embarc_bsp/library/console/console_io.c deleted file mode 100644 index b749d992..00000000 --- a/platform/vendor_bsp/embarc_bsp/library/console/console_io.c +++ /dev/null @@ -1,76 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @brief implemantation of simple console - */ -#include -#include "embARC.h" - -static DEV_UART *console_uart; /*!< console uart device pointer */ - -/** put one char */ -static int32_t console_putchar(uint8_t chr) -{ - if (console_uart == NULL) { - return -1; - } - - console_uart->uart_write((const void *)(&chr), 1); - - return 0; -} - -/** get one char*/ -static int32_t console_getchar(void) -{ - uint8_t data; - - if (console_uart == NULL) { - return -1; - } - - while (!console_uart->uart_read((void *)(&data), 1)) { - ; - } - - return (int32_t)data; -} - -/** xprintf need functions api setup */ -void xprintf_setup(void) -{ - console_uart = uart_get_dev(BOARD_CONSOLE_UART_ID); - console_uart->uart_open(BOARD_CONSOLE_UART_BAUD); - - xdev_in(console_getchar); - xdev_out(console_putchar); -} diff --git a/platform/vendor_bsp/embarc_bsp/library/console/console_io.h b/platform/vendor_bsp/embarc_bsp/library/console/console_io.h deleted file mode 100644 index 17d918cd..00000000 --- a/platform/vendor_bsp/embarc_bsp/library/console/console_io.h +++ /dev/null @@ -1,48 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ - -/** - * @file - * @brief header file of simple console - */ -#ifndef H_CONSOLE_IO -#define H_CONSOLE_IO - -#ifdef __cplusplus -extern "C" { -#endif - -extern void xprintf_setup(void); - -#ifdef __cplusplus -} -#endif - -#endif /* H_CONSOLE_IO */ diff --git a/platform/vendor_bsp/embarc_bsp/library/console/xprintf/xprintf.c b/platform/vendor_bsp/embarc_bsp/library/console/xprintf/xprintf.c deleted file mode 100644 index d6bf7459..00000000 --- a/platform/vendor_bsp/embarc_bsp/library/console/xprintf/xprintf.c +++ /dev/null @@ -1,512 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/*------------------------------------------------------------------------/ - / Universal string handler for user console interface - /-------------------------------------------------------------------------/ - / - / Copyright (C) 2011, ChaN, all right reserved. - / - / * This software is a free software and there is NO WARRANTY. - / * No restriction on use. You can use, modify and redistribute it for - / personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. - / * Redistributions of source code must retain the above copyright notice. - / - /-------------------------------------------------------------------------*/ - -#include "console/xprintf/xprintf.h" - -#if XPRINTF_USE_XFUNC_OUT -#include -void (*xfunc_out)(uint8_t); /* Pointer to the output stream */ -static char *outptr; - -/** - * @brief Put a character - * - * @param c Character to put - */ -void xputc(uint8_t c) -{ - if (XPRINTF_CR_CRLF && c == '\n') { - xputc('\r'); /* CR -> CRLF */ - - } - if (outptr) { - *outptr++ = (uint8_t)c; - return; - } - - if (xfunc_out) { - xfunc_out((uint8_t)c); - } -} - -/*----------------------------------------------*/ -/* Put a null-terminated string */ -/*----------------------------------------------*/ - -/** - * @brief Put a string to the default device - * - * @param str Pointer to the string - */ -void xputs(const char *str) -{ - while (*str) { - xputc(*str++); - } -} - -/** - * @brief Put a string to the specified device - * - * @param func Pointer to the output function - * @param str Pointer to the string - */ -void xfputs(void (*func)(uint8_t), const char *str) -{ - void (*pf)(uint8_t); - - pf = xfunc_out; /* Save current output device */ - xfunc_out = func; /* Switch output to specified device */ - while (*str) { /* Put the string */ - xputc(*str++); - } - xfunc_out = pf; /* Restore output device */ -} - -/** - * @brief Formatted string output - * xprintf("%d", 1234); "1234" - * xprintf("%6d,%3d%%", -200, 5); " -200, 5%" - * xprintf("%-6u", 100); "100 " - * xprintf("%ld", 12345678L); "12345678" - * xprintf("%04x", 0xA3); "00a3" - * xprintf("%08LX", 0x123ABC); "00123ABC" - * xprintf("%016b", 0x550F); "0101010100001111" - * xprintf("%s", "String"); "String" - * xprintf("%-4s", "abc"); "abc " - * xprintf("%4s", "abc"); abc" - * xprintf("%c", 'a'); "a" - * xprintf("%f", 10.0); "xprintf lacks floating point support" - * @param fmt Pointer to the format string - * @param arp Pointer to arguments - */ -void xvprintf(const char *fmt, va_list arp) -{ - uint32_t r, i, j, w, f; - uint32_t v; - char s[16], c, d, *p; - - for (;;) { - r = 0; - c = *fmt++; /* Get a char */ - if (!c) { - break; /* End of format? */ - } - if (c != '%') { /* Pass through it if not a % sequence */ - xputc(c); - continue; - } - f = 0; - c = *fmt++; /* Get first char of the sequence */ - if (c == '0') { /* Flag: '0' padded */ - f = 1; - c = *fmt++; - } else { - if (c == '-') { /* Flag: left justified */ - f = 2; - c = *fmt++; - } - } - for (w = 0; c >= '0' && c <= '9'; c = *fmt++) { /* Minimum width */ - w = w * 10 + c - '0'; - } - if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ - f |= 4; - c = *fmt++; - } - if (!c) { - break; /* End of format? */ - } - d = c; - if (d >= 'a') { - d -= 0x20; - } - switch (d) { /* Type is... */ - case 'S': /* String */ - p = va_arg(arp, char *); - for (j = 0; p[j]; j++) { - ; - } - while (!(f & 2) && j++ < w) { - xputc(' '); - } - xputs(p); - while (j++ < w) { - xputc(' '); - } - break; - case 'C': /* Character */ - xputc((char)va_arg(arp, int32_t)); - break; - case 'B': /* Binary */ - r = 2; - break; - case 'O': /* Octal */ - r = 8; - break; - case 'D': /* Signed decimal */ - case 'U': /* Unsigned decimal */ - r = 10; - break; - case 'X': /* Hexdecimal */ - r = 16; - break; - default: /* Unknown type (passthrough) */ - xputc(c); - break; - } - - if (r == 0) { - continue; - } - - /* Get an argument and put it in numeral */ - v = (f & 4) ? va_arg(arp, int32_t) : ((d == 'D') ? (int32_t)va_arg(arp, int32_t) : (int32_t)va_arg(arp, uint32_t)); - if (d == 'D' && (v & 0x80000000)) { - v = 0 - v; - f |= 8; - } - i = 0; - do { - d = (char)(v % r); v /= r; - if (d > 9) { - d += (c == 'x') ? 0x27 : 0x07; - } - s[i++] = d + '0'; - } while (v && i < sizeof(s)); - if ((f & 8) && (i < sizeof(s))) { - s[i++] = '-'; - } - j = i; d = (f & 1) ? '0' : ' '; - while (!(f & 2) && j++ < w) { - xputc(d); - } - do { - xputc(s[--i]); - } while (i); - while (j++ < w) { - xputc(' '); - } - } -} - -/** - * @brief Put a formatted string to the default device - * - * @param fmt Pointer to the format string - * @param ... Optional arguments - */ -void xprintf(const char *fmt, ...) -{ - va_list arp; - - va_start(arp, fmt); - xvprintf(fmt, arp); - va_end(arp); -} - -/** - * @brief Put a formatted string to the memory - * - * @param buff Pointer to the output buffer - * @param fmt Pointer to the format string - * @param ... Optional arguments - */ -void xsprintf(char *buff, const char *fmt, ...) -{ - va_list arp; - - outptr = buff; /* Switch destination for memory */ - - va_start(arp, fmt); - xvprintf(fmt, arp); - va_end(arp); - - *outptr = 0; /* Terminate output string with a \0 */ - outptr = 0; /* Switch destination for device */ -} - -/** - * @brief Put a formatted string to the specified device - * - * @param func Pointer to the output function - * @param fmt Pointer to the format string - * @param ... Optional arguments - */ -void xfprintf(void (*func)(uint8_t), const char *fmt, ...) -{ - va_list arp; - - void (*pf)(uint8_t); - - pf = xfunc_out; /* Save current output device */ - xfunc_out = func; /* Switch output to specified device */ - - va_start(arp, fmt); - xvprintf(fmt, arp); - va_end(arp); - - xfunc_out = pf; /* Restore output device */ -} - -/** - * @brief Dump a line of binary dump - * - * @param buff Pointer to the array to be dumped - * @param addr Heading address value - * @param len Number of items to be dumped - * @param width Size of the items (DF_8BIT, DF_16BIT, DF_32BIT) - */ -void put_dump(const void *buff, uint32_t addr, int32_t len, int32_t width) -{ - int32_t i; - const uint8_t *bp; - const uint16_t *sp; - const uint32_t *lp; - - /* address */ - xprintf("%08lX ", addr); - - switch (width) { - case DW_8BIT: - bp = buff; - /* Hexdecimal dump */ - for (i = 0; i < len; i++) { - xprintf(" %02X", bp[i]); - } - xputc(' '); - /* ASCII dump */ - for (i = 0; i < len; i++) { - xputc((bp[i] >= ' ' && bp[i] <= '~') ? bp[i] : '.'); - } - break; - case DW_16BIT: - sp = buff; - /* Hexdecimal dump */ - do { - xprintf(" %04X", *sp++); - } while (--len); - break; - case DW_32BIT: - lp = buff; - /* Hexdecimal dump */ - do { - xprintf(" %08LX", *lp++); - } while (--len); - break; - default: - break; - } - - xputc('\n'); -} - -#endif /* XPRINTF_USE_XFUNC_OUT */ - -#if XPRINTF_USE_XFUNC_IN -uint8_t (*xfunc_in)(void); /* Pointer to the input stream */ - -/** - * @brief Get a line from the input - * - * @param buff Pointer to the buffer - * @param len Buffer length - * @return 0:End of stream, 1:A line arrived - */ -int32_t xgets(char *buff, int32_t len) -{ - int32_t c, i; - - /* No input function specified */ - if (!xfunc_in) { - return 0; - } - - i = 0; - for (;;) { - /* Get a char from the incoming stream */ - c = xfunc_in(); - /* End of stream? */ - if (!c) { - return 0; - } - /* End of line? */ - if (c == '\r') { - break; - } - /* Back space? */ - if (c == '\b' && i) { - i--; - if (XPRINTF_LINE_ECHO) { - xputc(c); - } - continue; - } - /* Visible chars */ - if (c >= ' ' && i < len - 1) { - buff[i++] = c; - if (XPRINTF_LINE_ECHO) { - xputc(c); - } - } - } - /* Terminate with a \0 */ - buff[i] = 0; - if (XPRINTF_LINE_ECHO) { - xputc('\n'); - } - return 1; -} - -/** - * @brief Get a line from the input - * - * @param func Pointer to the input stream function - * @param buff Pointer to the buffer - * @param len Buffer length - * @return 0:End of stream, 1:A line arrived - */ -int32_t xfgets(uint8_t (*func)(void), char *buff, int32_t len) -{ - uint8_t (*pf)(void); - int32_t n; - - pf = xfunc_in; /* Save current input device */ - xfunc_in = func; /* Switch input to specified device */ - n = xgets(buff, len); /* Get a line */ - xfunc_in = pf; /* Restore input device */ - - return n; -} - -/** - * @brief Get a value of the string - * "123 -5 0x3ff 0b1111 0377 w " - * ^ 1st call returns 123 and next ptr - * ^ 2nd call returns -5 and next ptr - * ^ 3rd call returns 1023 and next ptr - * ^ 4th call returns 15 and next ptr - * ^ 5th call returns 255 and next ptr - * ^ 6th call fails and returns 0 - * @param str Pointer to pointer to the string - * @param res Pointer to the variable to store the value - * @return Failed, 1:Successful - */ -int32_t xatoi(char **str, int32_t *res) -{ - uint32_t val; - uint8_t c, r, s = 0; - - *res = 0; - - /* Skip leading spaces */ - while ((c = **str) == ' ') { - (*str)++; - - } - /* negative? */ - if (c == '-') { - s = 1; - c = *(++(*str)); - } - - if (c == '0') { - c = *(++(*str)); - switch (c) { - /* hexdecimal */ - case 'x': - r = 16; - c = *(++(*str)); - break; - /* binary */ - case 'b': - r = 2; - c = *(++(*str)); - break; - default: - /* single zero */ - if (c <= ' ') { - return 1; - } - /* invalid char */ - if (c < '0' || c > '9') { - return 0; - } - /* octal */ - r = 8; - break; - } - } else { - /* EOL or invalid char */ - if (c < '0' || c > '9') { - return 0; - } - /* decimal */ - r = 10; - } - - val = 0; - while (c > ' ') { - if (c >= 'a') { - c -= 0x20; - } - c -= '0'; - if (c >= 17) { - c -= 7; - } - /* invalid char for current radix */ - if (c >= r) { - return 0; - } - val = val * r + c; - c = *(++(*str)); - } - if (s) { - /* apply sign if needed */ - val = 0 - val; - - } - *res = val; - return 1; -} - -#endif /* XPRINTF_USE_XFUNC_IN */ diff --git a/platform/vendor_bsp/embarc_bsp/library/console/xprintf/xprintf.h b/platform/vendor_bsp/embarc_bsp/library/console/xprintf/xprintf.h deleted file mode 100644 index 8cdba80d..00000000 --- a/platform/vendor_bsp/embarc_bsp/library/console/xprintf/xprintf.h +++ /dev/null @@ -1,78 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - --------------------------------------------- */ -/*------------------------------------------------------------------------*/ -/* Universal string handler for user console interface (C)ChaN, 2011 */ -/*------------------------------------------------------------------------*/ - -#ifndef H_XPRINTF -#define H_XPRINTF - -#include -#include "embARC_toolchain.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define XPRINTF_USE_XFUNC_OUT 1 /* 1: Use output functions */ -#define XPRINTF_CR_CRLF 1 /* 1: Convert \n ==> \r\n in the output char */ - -#define XPRINTF_USE_XFUNC_IN 1 /* 1: Use input function */ -#define XPRINTF_LINE_ECHO 1 /* 1: Echo back input chars in xgets function */ - -#if XPRINTF_USE_XFUNC_OUT -#define xdev_out(func) xfunc_out = (void (*)(uint8_t))(func) -extern void (*xfunc_out)(uint8_t); -extern void xputc(uint8_t c); -extern void xputs(const char *str); -extern void xfputs(void (*func)(uint8_t), const char *str); -extern void xvprintf(const char *fmt, va_list arp); -extern void xprintf(const char *fmt, ...); -extern void xsprintf(char *buff, const char *fmt, ...); -extern void xfprintf(void (*func)(uint8_t), const char *fmt, ...); -extern void put_dump(const void *buff, uint32_t addr, int32_t len, int32_t width); -#define DW_8BIT sizeof(uint8_t) -#define DW_16BIT sizeof(uint16_t) -#define DW_32BIT sizeof(uint32_t) -#endif - -#if XPRINTF_USE_XFUNC_IN -#define xdev_in(func) xfunc_in = (uint8_t (*)(void))(func) -extern uint8_t (*xfunc_in)(void); -extern int32_t xgets(char *buff, int32_t len); -extern int32_t xfgets(uint8_t (*func)(void), char *buff, int32_t len); -extern int32_t xatoi(char **str, int32_t *res); -#endif - -#ifdef __cplusplus -} -#endif - -#endif