PowLu/TencentOS-tiny
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

delete some code

Browse Source
This commit is contained in:
supowang
2021-08-05 20:10:56 +08:00
parent 90859c8754
commit 1f694e2156
3228 changed files with 79 additions and 1492933 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
platform/hal/Microchip/CortexM3/Keil/cpu_types.h
View File

@@ -1,30 +0,0 @@
/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef __CPU_TYPES_H
#define __CPU_TYPES_H 1
#include <stdint.h>
/*------------------------------------------------------------------------------
*/
typedef unsigned int size_t;
/*------------------------------------------------------------------------------
* addr_t: address type.
* Used to specify the address of peripherals present in the processor's memory
* map.
*/
typedef unsigned int addr_t;
/*------------------------------------------------------------------------------
* psr_t: processor state register.
* Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
* processor's state between disabling and restoring interrupts.
*/
typedef unsigned int psr_t;
#endif /* __CPU_TYPES_H */

32
platform/hal/Microchip/CortexM3/Keil/hal.s
View File

@@ -1,32 +0,0 @@
;-------------------------------------------------------------------------------
; (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
;
; Interrupt disabling/restoration for critical section protection.
;
; SVN $Revision: 5261 $
; SVN $Date: 2013-03-21 19:52:41 +0530 (Thu, 21 Mar 2013) $
;
AREA |.text|, CODE, READONLY
EXPORT HAL_disable_interrupts
EXPORT HAL_restore_interrupts
;-------------------------------------------------------------------------------
;
;
HAL_disable_interrupts \
PROC
mrs r0, PRIMASK
cpsid I
bx lr
ENDP
;-------------------------------------------------------------------------------
;
;
HAL_restore_interrupts \
PROC
msr PRIMASK, r0
bx lr
ENDP
END

96
platform/hal/Microchip/CortexM3/Keil/hw_macros.h
View File

@@ -1,96 +0,0 @@
/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Hardware registers access macros.
*
* THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW
* DEVELOPMENT.
*
* These macros are used to access peripheral's registers. They allow access to
* 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
* be done through these macros in order to ease porting accross different
* processors/bus architectures.
*
* Some of these macros also allow to access a specific register field.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef __HW_REGISTER_MACROS_H
#define __HW_REGISTER_MACROS_H 1
/*------------------------------------------------------------------------------
* 32 bits registers access:
*/
#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint32_t) \
( \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 32 bits memory access:
*/
#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
/*------------------------------------------------------------------------------
* 16 bits registers access:
*/
#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint16_t) \
( \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits registers access:
*/
#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint8_t) \
( \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits memory access:
*/
#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
#endif /* __HW_REGISTER_MACROS_H */

175
platform/hal/Microchip/CortexM3/Keil/hw_reg_access.s
View File

@@ -1,175 +0,0 @@
;******************************************************************************
; (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
;
; SVN $Revision: 5258 $
; SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
;
AREA |.text|, CODE, READONLY
EXPORT HW_set_32bit_reg
EXPORT HW_get_32bit_reg
EXPORT HW_set_32bit_reg_field
EXPORT HW_get_32bit_reg_field
EXPORT HW_set_16bit_reg
EXPORT HW_get_16bit_reg
EXPORT HW_set_16bit_reg_field
EXPORT HW_get_16bit_reg_field
EXPORT HW_set_8bit_reg
EXPORT HW_get_8bit_reg
EXPORT HW_set_8bit_reg_field
EXPORT HW_get_8bit_reg_field
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint32_t value
;
HW_set_32bit_reg \
PROC
STR R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_32bit_reg \
PROC
LDR R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint32_t mask
; R3: uint32_t value
;
HW_set_32bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDR R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STR R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint32_t mask
;
HW_get_32bit_reg_field \
PROC
LDR R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint_fast16_t value
;
HW_set_16bit_reg \
PROC
STRH R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_16bit_reg \
PROC
LDRH R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast16_t mask
; R3: uint_fast16_t value
;
HW_set_16bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDRH R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STRH R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast16_t mask
;
HW_get_16bit_reg_field \
PROC
LDRH R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint_fast8_t value
;
HW_set_8bit_reg \
PROC
STRB R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_8bit_reg \
PROC
LDRB R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr,
; R1: int_fast8_t shift
; R2: uint_fast8_t mask
; R3: uint_fast8_t value
;
HW_set_8bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDRB R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STRB R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast8_t mask
;
HW_get_8bit_reg_field \
PROC
LDRB R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
END

209
platform/hal/Microchip/CortexM3/cortex_nvic.c
View File

@@ -1,209 +0,0 @@
/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Legacy Actel HAL Cortex NVIC control functions.
* The use of these functions should be replaced by calls to the equivalent
* CMSIS function in your application code.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $
*/
#include "cortex_nvic.h"
#ifdef MSCC_NO_RELATIVE_PATHS
#include "mss_assert.h"
#else
#include "../../CMSIS/mss_assert.h"
#endif
/***************************************************************************//**
*
*/
void NVIC_init( void )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Simply remove the call to NVIC_init() from your application code.
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_set_handler
(
uint32_t interrupt_number,
hal_nvic_irq_handler_t handler
)
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please remove the call to NVIC_set_handler() from your application code
* and provide a function using one of the following function prototypes to
* handle interrupts from peripherals implemeted in the SmartFusion2 FPGA
* fabric:
* - void FabricIrq0_IRQHandler(void)
* - void FabricIrq1_IRQHandler(void)
* - void FabricIrq2_IRQHandler(void)
* - void FabricIrq3_IRQHandler(void)
* - void FabricIrq4_IRQHandler(void)
* - void FabricIrq5_IRQHandler(void)
* - void FabricIrq6_IRQHandler(void)
* - void FabricIrq7_IRQHandler(void)
* - void FabricIrq8_IRQHandler(void)
* - void FabricIrq9_IRQHandler(void)
* - void FabricIrq10_IRQHandler(void)
* - void FabricIrq11_IRQHandler(void)
* - void FabricIrq12_IRQHandler(void)
* - void FabricIrq13_IRQHandler(void)
* - void FabricIrq14_IRQHandler(void)
* - void FabricIrq15_IRQHandler(void)
* The function to implement depends on which MSS_INT_F2M[n] signal is used
* in your Libero design to connect the interrupt signal of the peripheral
* generating the interrupt.
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_set_priority
(
uint32_t interrupt_number,
uint8_t priority_level
)
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_set_priority() with a call to the CMSIS
* void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) function where
* IRQn is one of the following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_enable_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_enable_interrupt() with a call to the CMSIS
* void NVIC_EnableIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_disable_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_disable_interrupt() with a call to the CMSIS
* void NVIC_DisableIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_clear_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_clear_interrupt() with a call to the CMSIS
* void NVIC_ClearPendingIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}

56
platform/hal/Microchip/CortexM3/cortex_nvic.h
View File

@@ -1,56 +0,0 @@
/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Legacy Actel HAL Cortex NVIC control functions.
* The use of these functions should be replaced by calls to the equivalent
* CMSIS function in your application code.
*
* SVN $Revision: 5257 $
* SVN $Date: 2013-03-21 17:54:10 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef CORTEX_NVIC_H_
#define CORTEX_NVIC_H_
#include <stdint.h>
typedef void (*hal_nvic_irq_handler_t)(void);
/*------------------------------------------------------------------------------
*
*/
void NVIC_init( void );
/*------------------------------------------------------------------------------
*
*/
void NVIC_set_handler
(
uint32_t interrupt_number,
hal_nvic_irq_handler_t handler
);
/*------------------------------------------------------------------------------
*
*/
void NVIC_set_priority
(
uint32_t interrupt_number,
uint8_t priority_level
);
/*------------------------------------------------------------------------------
*
*/
void NVIC_enable_interrupt( uint32_t interrupt_number );
/*------------------------------------------------------------------------------
*
*/
void NVIC_disable_interrupt( uint32_t interrupt_number );
/*------------------------------------------------------------------------------
*
*/
void NVIC_clear_interrupt( uint32_t interrupt_number );
#endif /*CORTEX_NVIC_H_*/

206
platform/hal/Microchip/hal.h
View File

@@ -1,206 +0,0 @@
/***************************************************************************//**
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Hardware abstraction layer functions.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef HAL_H_
#define HAL_H_
#include "cpu_types.h"
#include "hw_reg_access.h"
/***************************************************************************//**
* Enable all interrupts at the processor level.
*/
void HAL_enable_interrupts( void );
/***************************************************************************//**
* Disable all interrupts at the processor core level.
* Return the interrupts enable state before disabling occured so that it can
* later be restored.
*/
psr_t HAL_disable_interrupts( void );
/***************************************************************************//**
* Restore the interrupts enable state at the processor core level.
* This function is normally passed the value returned from a previous call to
* HAL_disable_interrupts().
*/
void HAL_restore_interrupts( psr_t saved_psr );
/***************************************************************************//**
*/
#define FIELD_OFFSET(FIELD_NAME) (FIELD_NAME##_OFFSET)
#define FIELD_SHIFT(FIELD_NAME) (FIELD_NAME##_SHIFT)
#define FIELD_MASK(FIELD_NAME) (FIELD_NAME##_MASK)
/***************************************************************************//**
* The macro HAL_set_32bit_reg() allows writing a 32 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint32_t containing the value to write.
*/
#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_32bit_reg() is used to read the value of a 32 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint32_t value.
*/
#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) ))
/***************************************************************************//**
* The macro HAL_set_32bit_reg_field() is used to write a field within a
* 32 bits wide register. The field written can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* VALUE: A variable of type uint32_t containing the field value to write.
*/
#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_32bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_32bit_reg_field() is used to read a register field from
* within a 32 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint32_t value.
*/
#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_32bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
/***************************************************************************//**
* The macro HAL_set_16bit_reg() allows writing a 16 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint_fast16_t containing the value to write.
*/
#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_16bit_reg() is used to read the value of a 16 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint16_t value.
*/
#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
/***************************************************************************//**
* The macro HAL_set_16bit_reg_field() is used to write a field within a
* 16 bits wide register. The field written can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* VALUE: A variable of type uint16_t containing the field value to write.
*/
#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_16bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_16bit_reg_field() is used to read a register field from
* within a 8 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint16_t value.
*/
#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_16bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
/***************************************************************************//**
* The macro HAL_set_8bit_reg() allows writing a 8 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint_fast8_t containing the value to write.
*/
#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint8_t value.
*/
#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
/***************************************************************************//**
*/
#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_8bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_8bit_reg_field() is used to read a register field from
* within a 8 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint8_t value.
*/
#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_8bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
#endif /*HAL_H_*/

34
platform/hal/Microchip/hal_assert.h
View File

@@ -1,34 +0,0 @@
/*******************************************************************************
* (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $
*/
#ifndef HAL_ASSERT_HEADER
#define HAL_ASSERT_HEADER
#ifdef MSCC_NO_RELATIVE_PATHS
#include "mss_assert.h"
#else
#include "../CMSIS/mss_assert.h"
#endif
#if defined(NDEBUG)
/***************************************************************************//**
* HAL_ASSERT() is defined out when the NDEBUG symbol is used.
******************************************************************************/
#define HAL_ASSERT(CHECK)
#else
/***************************************************************************//**
* Default behaviour for HAL_ASSERT() macro:
*------------------------------------------------------------------------------
* Using the HAL_ASSERT() macro is the same as directly using the SmartFusion2
* CMSIS ASSERT() macro. The behaviour is toolchain specific and project
* setting specific.
******************************************************************************/
#define HAL_ASSERT(CHECK) ASSERT(CHECK);
#endif /* NDEBUG */
#endif /* HAL_ASSERT_HEADER */

227
platform/hal/Microchip/hw_reg_access.h
View File

@@ -1,227 +0,0 @@
/***************************************************************************//**
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Hardware registers access functions.
* The implementation of these function is platform and toolchain specific.
* The functions declared here are implemented using assembler as part of the
* processor/toolchain specific HAL.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef HW_REG_ACCESS
#define HW_REG_ACCESS
/***************************************************************************//**
* HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_32bit_reg
(
addr_t reg_addr,
uint32_t value
);
/***************************************************************************//**
* HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 32 bits value read from the peripheral register.
*/
uint32_t
HW_get_32bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void
HW_set_32bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint32_t mask,
uint32_t value
);
/***************************************************************************//**
* HW_get_32bit_reg_field is used to read the content of a field out of a
* 32 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 32 bits value containing the register field value specified
* as parameter.
*/
uint32_t
HW_get_32bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint32_t mask
);
/***************************************************************************//**
* HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_16bit_reg
(
addr_t reg_addr,
uint_fast16_t value
);
/***************************************************************************//**
* HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 16 bits value read from the peripheral register.
*/
uint16_t
HW_get_16bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void HW_set_16bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast16_t mask,
uint_fast16_t value
);
/***************************************************************************//**
* HW_get_16bit_reg_field is used to read the content of a field from a
* 16 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 16 bits value containing the register field value specified
* as parameter.
*/
uint16_t HW_get_16bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast16_t mask
);
/***************************************************************************//**
* HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_8bit_reg
(
addr_t reg_addr,
uint_fast8_t value
);
/***************************************************************************//**
* HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 8 bits value read from the peripheral register.
*/
uint8_t
HW_get_8bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void HW_set_8bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast8_t mask,
uint_fast8_t value
);
/***************************************************************************//**
* HW_get_8bit_reg_field is used to read the content of a field from a
* 8 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 16 bits value containing the register field value specified
* as parameter.
*/
uint8_t HW_get_8bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast8_t mask
);
#endif /* HW_REG_ACCESS */

111
platform/hal/nationz/N32G020XX/src/tos_hal_uart.c
View File

@@ -1,111 +0,0 @@
#include "tos_k.h"
#include "tos_hal.h"
#include "n32g020xx_common.h"
#include "n32g020xx.h"
#include "n32g020xx_timer.h"
#include "n32g020xx_uart.h"
#include "n32g020xx_it.h"
typedef struct __UART_HandleTypeDef
{
UartChannel channel;
} UART_HandleTypeDef;
typedef enum {
HAL_ERROR = -1,
HAL_OK = 0x00U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
UART_HandleTypeDef huart0;
UART_HandleTypeDef huart1;
UART_HandleTypeDef huart2;
UART_HandleTypeDef huart3;
void NBIoT_UartRcvProtocal(int32_t val) { AT_UART_DataParse((char)val); }
__API__ int tos_hal_uart_init(hal_uart_t *uart, hal_uart_port_t port)
{
UartConfig config;
if (!uart) {
return -1;
}
if (port == HAL_UART_PORT_0) {
huart0.channel = UART_CH0;
uart->private_uart = &huart0;
config.frequence = UART_FREQ_INTERAL;
config.baudrate = 9600;
config.parity_type = UART_PARITY_NONE;
config.callback = NBIoT_UartRcvProtocal;
config.io = UART_CH0_GPIO22_GPIO23;
if (UART_SUCCESS != UART_Init(UART_CH0, &config))
{
printf("Init uart int failed.\r\n");
}
} else if (port == HAL_UART_PORT_1) {
huart0.channel = UART_CH1;
uart->private_uart = &huart1;
} else if (port == HAL_UART_PORT_2) {
uart->private_uart = &huart2;
huart0.channel = UART_CH2;
uart->private_uart = &huart2;
}
return 0;
}
__API__ int tos_hal_uart_write(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout)
{
HAL_StatusTypeDef hal_status;
UART_HandleTypeDef *uart_handle;
if (!uart || !buf) {
return -1;
}
if (!uart->private_uart) {
return -1;
}
uart_handle = (UART_HandleTypeDef *)uart->private_uart;
hal_status = UART_SendData(uart_handle->channel, (uint8_t *)buf, size);
if (hal_status != HAL_OK) {
return -1;
}
return 0;
}
__API__ int tos_hal_uart_read(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout)
{
return 0;
}
__API__ int tos_hal_uart_deinit(hal_uart_t *uart)
{
HAL_StatusTypeDef hal_status;
UART_HandleTypeDef *uart_handle;
if (!uart) {
return -1;
}
if (!uart->private_uart) {
return -1;
}
uart_handle = (UART_HandleTypeDef *)uart->private_uart;
hal_status = UART_Close(uart_handle->channel);
if (hal_status != HAL_OK) {
return -1;
}
return 0;
}