diff --git a/arch/arm/arm-v6m/common/include/tos_cpu.h b/arch/arm/arm-v6m/common/include/tos_cpu.h index 2ad847fb..86e673f4 100644 --- a/arch/arm/arm-v6m/common/include/tos_cpu.h +++ b/arch/arm/arm-v6m/common/include/tos_cpu.h @@ -58,25 +58,25 @@ __API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); #endif -__KERNEL__ void cpu_init(void); +__KNL__ void cpu_init(void); -__KERNEL__ void cpu_reset(void); +__KNL__ void cpu_reset(void); -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); -__KERNEL__ void cpu_sched_start(void); +__KNL__ void cpu_sched_start(void); -__KERNEL__ void cpu_context_switch(void); +__KNL__ void cpu_context_switch(void); -__KERNEL__ void cpu_irq_context_switch(void); +__KNL__ void cpu_irq_context_switch(void); #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); #endif -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -84,29 +84,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ void cpu_systick_resume(void); +__KNL__ void cpu_systick_resume(void); -__KERNEL__ void cpu_systick_suspend(void); +__KNL__ void cpu_systick_suspend(void); -__KERNEL__ void cpu_systick_reload_reset(void); +__KNL__ void cpu_systick_reload_reset(void); -__KERNEL__ void cpu_systick_pending_reset(void); +__KNL__ void cpu_systick_pending_reset(void); -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); -__KERNEL__ void cpu_systick_reset(void); +__KNL__ void cpu_systick_reset(void); #endif #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void); +__KNL__ void cpu_sleep_mode_enter(void); -__KERNEL__ void cpu_stop_mode_enter(void); +__KNL__ void cpu_stop_mode_enter(void); -__KERNEL__ void cpu_standby_mode_enter(void); +__KNL__ void cpu_standby_mode_enter(void); #endif @@ -114,11 +114,11 @@ __KERNEL__ void cpu_standby_mode_enter(void); #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void); +__KNL__ void cpu_flush_fpu(void); #endif /* TOS_CFG_CPU_ARM_FPU_EN */ -__KERNEL__ void cpu_fault_diagnosis(void); +__KNL__ void cpu_fault_diagnosis(void); #endif diff --git a/arch/arm/arm-v6m/common/include/tos_cpu_def.h b/arch/arm/arm-v6m/common/include/tos_cpu_def.h index f71d7c8e..50d0d838 100644 --- a/arch/arm/arm-v6m/common/include/tos_cpu_def.h +++ b/arch/arm/arm-v6m/common/include/tos_cpu_def.h @@ -18,17 +18,13 @@ #ifndef _TOS_CPU_DEF_H_ #define _TOS_CPU_DEF_H_ -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 #endif /* _TOS_CPU_DEF_H_ */ diff --git a/arch/arm/arm-v6m/common/include/tos_fault.h b/arch/arm/arm-v6m/common/include/tos_fault.h index 784c5f9d..46ada763 100644 --- a/arch/arm/arm-v6m/common/include/tos_fault.h +++ b/arch/arm/arm-v6m/common/include/tos_fault.h @@ -226,9 +226,9 @@ __STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); -__KERNEL__ int fault_default_log_writer(const char *format, ...); +__KNL__ int fault_default_log_writer(const char *format, ...); -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); #endif diff --git a/arch/arm/arm-v6m/common/tos_cpu.c b/arch/arm/arm-v6m/common/tos_cpu.c index 2dc1ef25..bf01ff9e 100644 --- a/arch/arm/arm-v6m/common/tos_cpu.c +++ b/arch/arm/arm-v6m/common/tos_cpu.c @@ -76,7 +76,7 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) port_cpsr_restore(cpsr); } -__KERNEL__ void cpu_init(void) +__KNL__ void cpu_init(void) { k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; cpu_systick_init(k_cpu_cycle_per_tick); @@ -86,27 +86,27 @@ __KERNEL__ void cpu_init(void) #endif } -__KERNEL__ void cpu_reset(void) +__KNL__ void cpu_reset(void) { port_cpu_reset(); } -__KERNEL__ void cpu_sched_start(void) +__KNL__ void cpu_sched_start(void) { port_sched_start(); } -__KERNEL__ void cpu_context_switch(void) +__KNL__ void cpu_context_switch(void) { port_context_switch(); } -__KERNEL__ void cpu_irq_context_switch(void) +__KNL__ void cpu_irq_context_switch(void) { port_irq_context_switch(); } -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); port_systick_config(cycle_per_tick); @@ -131,7 +131,7 @@ __STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) * * @return None */ -__KERNEL__ void cpu_systick_resume(void) +__KNL__ void cpu_systick_resume(void) { port_systick_resume(); } @@ -141,17 +141,17 @@ __KERNEL__ void cpu_systick_resume(void) * * @return None */ -__KERNEL__ void cpu_systick_suspend(void) +__KNL__ void cpu_systick_suspend(void) { port_systick_suspend(); } -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void) { return port_systick_max_delay_millisecond(); } -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) +__KNL__ void cpu_systick_expires_set(k_time_t millisecond) { k_cycle_t cycles; @@ -160,12 +160,12 @@ __KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) cpu_systick_reload(cycles - 12); /* interrupt delay */ } -__KERNEL__ void cpu_systick_pending_reset(void) +__KNL__ void cpu_systick_pending_reset(void) { port_systick_pending_reset(); } -__KERNEL__ void cpu_systick_reset(void) +__KNL__ void cpu_systick_reset(void) { cpu_systick_reload(k_cpu_cycle_per_tick); } @@ -174,24 +174,24 @@ __KERNEL__ void cpu_systick_reset(void) #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void) +__KNL__ void cpu_sleep_mode_enter(void) { port_sleep_mode_enter(); } -__KERNEL__ void cpu_stop_mode_enter(void) +__KNL__ void cpu_stop_mode_enter(void) { port_stop_mode_enter(); } -__KERNEL__ void cpu_standby_mode_enter(void) +__KNL__ void cpu_standby_mode_enter(void) { port_standby_mode_enter(); } #endif /* TOS_CFG_PWR_MGR_EN */ -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -248,7 +248,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) { uint8_t *slot; uint8_t *sp, *bp; @@ -278,13 +278,13 @@ __KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_ #if TOS_CFG_FAULT_BACKTRACE_EN > 0u #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void) +__KNL__ void cpu_flush_fpu(void) { (void)__get_FPSCR(); } #endif -__KERNEL__ void cpu_fault_diagnosis(void) +__KNL__ void cpu_fault_diagnosis(void) { port_fault_diagnosis(); } diff --git a/arch/arm/arm-v6m/common/tos_fault.c b/arch/arm/arm-v6m/common/tos_fault.c index 65ae7e02..23958806 100644 --- a/arch/arm/arm-v6m/common/tos_fault.c +++ b/arch/arm/arm-v6m/common/tos_fault.c @@ -222,7 +222,7 @@ __STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); } -__KERNEL__ int fault_default_log_writer(const char *format, ...) +__KNL__ int fault_default_log_writer(const char *format, ...) { int len; va_list ap; @@ -239,7 +239,7 @@ __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) k_fault_log_writer = log_writer; } -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) { fault_info_t info; diff --git a/arch/arm/arm-v7a/common/include/tos_cpu.h b/arch/arm/arm-v7a/common/include/tos_cpu.h index 625af65e..cafc4f60 100644 --- a/arch/arm/arm-v7a/common/include/tos_cpu.h +++ b/arch/arm/arm-v7a/common/include/tos_cpu.h @@ -62,25 +62,25 @@ __API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); #endif -__KERNEL__ void cpu_init(void); +__KNL__ void cpu_init(void); -__KERNEL__ void cpu_reset(void); +__KNL__ void cpu_reset(void); -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); -__KERNEL__ void cpu_sched_start(void); +__KNL__ void cpu_sched_start(void); -__KERNEL__ void cpu_context_switch(void); +__KNL__ void cpu_context_switch(void); -__KERNEL__ void cpu_irq_context_switch(void); +__KNL__ void cpu_irq_context_switch(void); #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); #endif -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -88,29 +88,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ void cpu_systick_resume(void); +__KNL__ void cpu_systick_resume(void); -__KERNEL__ void cpu_systick_suspend(void); +__KNL__ void cpu_systick_suspend(void); -__KERNEL__ void cpu_systick_reload_reset(void); +__KNL__ void cpu_systick_reload_reset(void); -__KERNEL__ void cpu_systick_pending_reset(void); +__KNL__ void cpu_systick_pending_reset(void); -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); -__KERNEL__ void cpu_systick_reset(void); +__KNL__ void cpu_systick_reset(void); #endif #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void); +__KNL__ void cpu_sleep_mode_enter(void); -__KERNEL__ void cpu_stop_mode_enter(void); +__KNL__ void cpu_stop_mode_enter(void); -__KERNEL__ void cpu_standby_mode_enter(void); +__KNL__ void cpu_standby_mode_enter(void); #endif @@ -118,11 +118,11 @@ __KERNEL__ void cpu_standby_mode_enter(void); #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void); +__KNL__ void cpu_flush_fpu(void); #endif /* TOS_CFG_CPU_ARM_FPU_EN */ -__KERNEL__ void cpu_fault_diagnosis(void); +__KNL__ void cpu_fault_diagnosis(void); #endif diff --git a/arch/arm/arm-v7a/common/include/tos_cpu_def.h b/arch/arm/arm-v7a/common/include/tos_cpu_def.h index f71d7c8e..50d0d838 100644 --- a/arch/arm/arm-v7a/common/include/tos_cpu_def.h +++ b/arch/arm/arm-v7a/common/include/tos_cpu_def.h @@ -18,17 +18,13 @@ #ifndef _TOS_CPU_DEF_H_ #define _TOS_CPU_DEF_H_ -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 #endif /* _TOS_CPU_DEF_H_ */ diff --git a/arch/arm/arm-v7a/common/include/tos_fault.h b/arch/arm/arm-v7a/common/include/tos_fault.h index 784c5f9d..46ada763 100644 --- a/arch/arm/arm-v7a/common/include/tos_fault.h +++ b/arch/arm/arm-v7a/common/include/tos_fault.h @@ -226,9 +226,9 @@ __STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); -__KERNEL__ int fault_default_log_writer(const char *format, ...); +__KNL__ int fault_default_log_writer(const char *format, ...); -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); #endif diff --git a/arch/arm/arm-v7a/common/include/tos_gic.h b/arch/arm/arm-v7a/common/include/tos_gic.h index 3017833a..9faa77da 100644 --- a/arch/arm/arm-v7a/common/include/tos_gic.h +++ b/arch/arm/arm-v7a/common/include/tos_gic.h @@ -92,15 +92,15 @@ typedef struct gic_data_st { gic_cpu_t *cpu; } gic_data_t; -__KERNEL__ uint32_t gic_interrupt_id_get(uint32_t gic_nr); +__KNL__ uint32_t gic_interrupt_id_get(uint32_t gic_nr); -__KERNEL__ void gic_interrupt_end(uint32_t gic_nr, uint32_t vector); +__KNL__ void gic_interrupt_end(uint32_t gic_nr, uint32_t vector); -__KERNEL__ int gic_init(uint32_t gic_nr); +__KNL__ int gic_init(uint32_t gic_nr); -__KERNEL__ void gic_interrupt_enable(uint32_t gic_nr, uint32_t vector); +__KNL__ void gic_interrupt_enable(uint32_t gic_nr, uint32_t vector); -__KERNEL__ void gic_interrupt_disable(uint32_t gic_nr, uint32_t vector); +__KNL__ void gic_interrupt_disable(uint32_t gic_nr, uint32_t vector); #endif /* _TOS_GIC_H_ */ diff --git a/arch/arm/arm-v7a/common/include/tos_interrupt.h b/arch/arm/arm-v7a/common/include/tos_interrupt.h index 682a01ad..e699e338 100644 --- a/arch/arm/arm-v7a/common/include/tos_interrupt.h +++ b/arch/arm/arm-v7a/common/include/tos_interrupt.h @@ -51,15 +51,15 @@ typedef struct int_frame_st { cpu_data_t spsr; } int_frame_t; -__KERNEL__ void interrupt_irq(int_frame_t *int_frame); +__KNL__ void interrupt_irq(int_frame_t *int_frame); -__KERNEL__ int interrupt_init(void); +__KNL__ int interrupt_init(void); -__API__ int tos_interrupt_handler_register(uint32_t vector, int_handler_t handler, void *arg); +__API__ int tos_interrupt_handler_register(uint32_t vector, int_handler_t handler, void *arg); -__API__ void tos_interrupt_enable(uint32_t vector); +__API__ void tos_interrupt_enable(uint32_t vector); -__API__ void tos_interrupt_disable(uint32_t vector); +__API__ void tos_interrupt_disable(uint32_t vector); #endif /* _TOS_INTERRUPT_H_ */ diff --git a/arch/arm/arm-v7a/common/tos_cpu.c b/arch/arm/arm-v7a/common/tos_cpu.c index 968b7332..8baa75d9 100644 --- a/arch/arm/arm-v7a/common/tos_cpu.c +++ b/arch/arm/arm-v7a/common/tos_cpu.c @@ -76,7 +76,7 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) port_cpsr_restore(cpsr); } -__KERNEL__ void cpu_init(void) +__KNL__ void cpu_init(void) { k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; @@ -84,27 +84,27 @@ __KERNEL__ void cpu_init(void) chip_init(); } -__KERNEL__ void cpu_reset(void) +__KNL__ void cpu_reset(void) { port_cpu_reset(); } -__KERNEL__ void cpu_sched_start(void) +__KNL__ void cpu_sched_start(void) { port_sched_start(); } -__KERNEL__ void cpu_context_switch(void) +__KNL__ void cpu_context_switch(void) { port_context_switch(); } -__KERNEL__ void cpu_irq_context_switch(void) +__KNL__ void cpu_irq_context_switch(void) { port_irq_context_switch(); } -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); port_systick_config(cycle_per_tick); @@ -129,7 +129,7 @@ __STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) * * @return None */ -__KERNEL__ void cpu_systick_resume(void) +__KNL__ void cpu_systick_resume(void) { port_systick_resume(); } @@ -139,17 +139,17 @@ __KERNEL__ void cpu_systick_resume(void) * * @return None */ -__KERNEL__ void cpu_systick_suspend(void) +__KNL__ void cpu_systick_suspend(void) { port_systick_suspend(); } -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void) { return port_systick_max_delay_millisecond(); } -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) +__KNL__ void cpu_systick_expires_set(k_time_t millisecond) { k_cycle_t cycles; @@ -158,12 +158,12 @@ __KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) cpu_systick_reload(cycles - 12); /* interrupt delay */ } -__KERNEL__ void cpu_systick_pending_reset(void) +__KNL__ void cpu_systick_pending_reset(void) { port_systick_pending_reset(); } -__KERNEL__ void cpu_systick_reset(void) +__KNL__ void cpu_systick_reset(void) { cpu_systick_reload(k_cpu_cycle_per_tick); } @@ -172,24 +172,24 @@ __KERNEL__ void cpu_systick_reset(void) #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void) +__KNL__ void cpu_sleep_mode_enter(void) { port_sleep_mode_enter(); } -__KERNEL__ void cpu_stop_mode_enter(void) +__KNL__ void cpu_stop_mode_enter(void) { port_stop_mode_enter(); } -__KERNEL__ void cpu_standby_mode_enter(void) +__KNL__ void cpu_standby_mode_enter(void) { port_standby_mode_enter(); } #endif /* TOS_CFG_PWR_MGR_EN */ -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -241,7 +241,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) { uint8_t *slot; uint8_t *sp, *bp; @@ -271,13 +271,13 @@ __KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_ #if TOS_CFG_FAULT_BACKTRACE_EN > 0u #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void) +__KNL__ void cpu_flush_fpu(void) { (void)__get_FPSCR(); } #endif -__KERNEL__ void cpu_fault_diagnosis(void) +__KNL__ void cpu_fault_diagnosis(void) { port_fault_diagnosis(); } diff --git a/arch/arm/arm-v7a/common/tos_fault.c b/arch/arm/arm-v7a/common/tos_fault.c index 908264ee..f6ae2d21 100644 --- a/arch/arm/arm-v7a/common/tos_fault.c +++ b/arch/arm/arm-v7a/common/tos_fault.c @@ -222,7 +222,7 @@ __STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); } -__KERNEL__ int fault_default_log_writer(const char *format, ...) +__KNL__ int fault_default_log_writer(const char *format, ...) { int len; va_list ap; @@ -239,7 +239,7 @@ __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) k_fault_log_writer = log_writer; } -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) { fault_info_t info; diff --git a/arch/arm/arm-v7a/common/tos_gic.c b/arch/arm/arm-v7a/common/tos_gic.c index 0a941420..ed17e169 100644 --- a/arch/arm/arm-v7a/common/tos_gic.c +++ b/arch/arm/arm-v7a/common/tos_gic.c @@ -81,7 +81,7 @@ __STATIC_INLINE__ gic_data_t *gic_get(uint32_t gic_nr) return K_NULL; } -__KERNEL__ uint32_t gic_interrupt_id_get(uint32_t gic_nr) +__KNL__ uint32_t gic_interrupt_id_get(uint32_t gic_nr) { gic_data_t *gic = gic_get(gic_nr); @@ -93,7 +93,7 @@ __KERNEL__ uint32_t gic_interrupt_id_get(uint32_t gic_nr) return (uint32_t)-1; } -__KERNEL__ void gic_interrupt_end(uint32_t gic_nr, uint32_t vector) +__KNL__ void gic_interrupt_end(uint32_t gic_nr, uint32_t vector) { gic_data_t *gic = gic_get(gic_nr); @@ -102,7 +102,7 @@ __KERNEL__ void gic_interrupt_end(uint32_t gic_nr, uint32_t vector) } } -__KERNEL__ int gic_init(uint32_t gic_nr) +__KNL__ int gic_init(uint32_t gic_nr) { gic_data_t *gic; @@ -119,7 +119,7 @@ __KERNEL__ int gic_init(uint32_t gic_nr) return 0; } -__KERNEL__ void gic_interrupt_enable(uint32_t gic_nr, uint32_t vector) +__KNL__ void gic_interrupt_enable(uint32_t gic_nr, uint32_t vector) { int reg; uint32_t mask; @@ -134,7 +134,7 @@ __KERNEL__ void gic_interrupt_enable(uint32_t gic_nr, uint32_t vector) } } -__KERNEL__ void gic_interrupt_disable(uint32_t gic_nr, uint32_t vector) +__KNL__ void gic_interrupt_disable(uint32_t gic_nr, uint32_t vector) { int reg; uint32_t mask; diff --git a/arch/arm/arm-v7a/common/tos_interrupt.c b/arch/arm/arm-v7a/common/tos_interrupt.c index ebd5f86f..43bfbea4 100644 --- a/arch/arm/arm-v7a/common/tos_interrupt.c +++ b/arch/arm/arm-v7a/common/tos_interrupt.c @@ -19,7 +19,7 @@ __STATIC__ int_handle_t int_handle_table[INTERRUPT_MAX]; -__KERNEL__ void interrupt_irq(int_frame_t *int_frame) +__KNL__ void interrupt_irq(int_frame_t *int_frame) { uint32_t vector; int_handle_t *handle; @@ -38,7 +38,7 @@ __KERNEL__ void interrupt_irq(int_frame_t *int_frame) gic_interrupt_end(0u, vector); } -__KERNEL__ int interrupt_init(void) +__KNL__ int interrupt_init(void) { gic_init(0u); return 0; diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/imx6ul.c b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/imx6ul.c index 04056555..c50b8403 100644 --- a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/imx6ul.c +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/imx6ul.c @@ -18,7 +18,7 @@ #include "tos_k.h" #include "imx6ul.h" -__KERNEL__ void chip_init(void) +__KNL__ void chip_init(void) { clock_init(); clock_enable(); diff --git a/arch/arm/arm-v7m/common/include/tos_cpu.h b/arch/arm/arm-v7m/common/include/tos_cpu.h index 2ad847fb..86e673f4 100644 --- a/arch/arm/arm-v7m/common/include/tos_cpu.h +++ b/arch/arm/arm-v7m/common/include/tos_cpu.h @@ -58,25 +58,25 @@ __API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); #endif -__KERNEL__ void cpu_init(void); +__KNL__ void cpu_init(void); -__KERNEL__ void cpu_reset(void); +__KNL__ void cpu_reset(void); -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); -__KERNEL__ void cpu_sched_start(void); +__KNL__ void cpu_sched_start(void); -__KERNEL__ void cpu_context_switch(void); +__KNL__ void cpu_context_switch(void); -__KERNEL__ void cpu_irq_context_switch(void); +__KNL__ void cpu_irq_context_switch(void); #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); #endif -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -84,29 +84,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ void cpu_systick_resume(void); +__KNL__ void cpu_systick_resume(void); -__KERNEL__ void cpu_systick_suspend(void); +__KNL__ void cpu_systick_suspend(void); -__KERNEL__ void cpu_systick_reload_reset(void); +__KNL__ void cpu_systick_reload_reset(void); -__KERNEL__ void cpu_systick_pending_reset(void); +__KNL__ void cpu_systick_pending_reset(void); -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); -__KERNEL__ void cpu_systick_reset(void); +__KNL__ void cpu_systick_reset(void); #endif #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void); +__KNL__ void cpu_sleep_mode_enter(void); -__KERNEL__ void cpu_stop_mode_enter(void); +__KNL__ void cpu_stop_mode_enter(void); -__KERNEL__ void cpu_standby_mode_enter(void); +__KNL__ void cpu_standby_mode_enter(void); #endif @@ -114,11 +114,11 @@ __KERNEL__ void cpu_standby_mode_enter(void); #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void); +__KNL__ void cpu_flush_fpu(void); #endif /* TOS_CFG_CPU_ARM_FPU_EN */ -__KERNEL__ void cpu_fault_diagnosis(void); +__KNL__ void cpu_fault_diagnosis(void); #endif diff --git a/arch/arm/arm-v7m/common/include/tos_cpu_def.h b/arch/arm/arm-v7m/common/include/tos_cpu_def.h index f71d7c8e..50d0d838 100644 --- a/arch/arm/arm-v7m/common/include/tos_cpu_def.h +++ b/arch/arm/arm-v7m/common/include/tos_cpu_def.h @@ -18,17 +18,13 @@ #ifndef _TOS_CPU_DEF_H_ #define _TOS_CPU_DEF_H_ -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 #endif /* _TOS_CPU_DEF_H_ */ diff --git a/arch/arm/arm-v7m/common/include/tos_fault.h b/arch/arm/arm-v7m/common/include/tos_fault.h index 784c5f9d..46ada763 100644 --- a/arch/arm/arm-v7m/common/include/tos_fault.h +++ b/arch/arm/arm-v7m/common/include/tos_fault.h @@ -226,9 +226,9 @@ __STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); -__KERNEL__ int fault_default_log_writer(const char *format, ...); +__KNL__ int fault_default_log_writer(const char *format, ...); -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); #endif diff --git a/arch/arm/arm-v7m/common/tos_cpu.c b/arch/arm/arm-v7m/common/tos_cpu.c index 2dc1ef25..bf01ff9e 100644 --- a/arch/arm/arm-v7m/common/tos_cpu.c +++ b/arch/arm/arm-v7m/common/tos_cpu.c @@ -76,7 +76,7 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) port_cpsr_restore(cpsr); } -__KERNEL__ void cpu_init(void) +__KNL__ void cpu_init(void) { k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; cpu_systick_init(k_cpu_cycle_per_tick); @@ -86,27 +86,27 @@ __KERNEL__ void cpu_init(void) #endif } -__KERNEL__ void cpu_reset(void) +__KNL__ void cpu_reset(void) { port_cpu_reset(); } -__KERNEL__ void cpu_sched_start(void) +__KNL__ void cpu_sched_start(void) { port_sched_start(); } -__KERNEL__ void cpu_context_switch(void) +__KNL__ void cpu_context_switch(void) { port_context_switch(); } -__KERNEL__ void cpu_irq_context_switch(void) +__KNL__ void cpu_irq_context_switch(void) { port_irq_context_switch(); } -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); port_systick_config(cycle_per_tick); @@ -131,7 +131,7 @@ __STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) * * @return None */ -__KERNEL__ void cpu_systick_resume(void) +__KNL__ void cpu_systick_resume(void) { port_systick_resume(); } @@ -141,17 +141,17 @@ __KERNEL__ void cpu_systick_resume(void) * * @return None */ -__KERNEL__ void cpu_systick_suspend(void) +__KNL__ void cpu_systick_suspend(void) { port_systick_suspend(); } -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void) { return port_systick_max_delay_millisecond(); } -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) +__KNL__ void cpu_systick_expires_set(k_time_t millisecond) { k_cycle_t cycles; @@ -160,12 +160,12 @@ __KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) cpu_systick_reload(cycles - 12); /* interrupt delay */ } -__KERNEL__ void cpu_systick_pending_reset(void) +__KNL__ void cpu_systick_pending_reset(void) { port_systick_pending_reset(); } -__KERNEL__ void cpu_systick_reset(void) +__KNL__ void cpu_systick_reset(void) { cpu_systick_reload(k_cpu_cycle_per_tick); } @@ -174,24 +174,24 @@ __KERNEL__ void cpu_systick_reset(void) #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void) +__KNL__ void cpu_sleep_mode_enter(void) { port_sleep_mode_enter(); } -__KERNEL__ void cpu_stop_mode_enter(void) +__KNL__ void cpu_stop_mode_enter(void) { port_stop_mode_enter(); } -__KERNEL__ void cpu_standby_mode_enter(void) +__KNL__ void cpu_standby_mode_enter(void) { port_standby_mode_enter(); } #endif /* TOS_CFG_PWR_MGR_EN */ -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -248,7 +248,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) { uint8_t *slot; uint8_t *sp, *bp; @@ -278,13 +278,13 @@ __KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_ #if TOS_CFG_FAULT_BACKTRACE_EN > 0u #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void) +__KNL__ void cpu_flush_fpu(void) { (void)__get_FPSCR(); } #endif -__KERNEL__ void cpu_fault_diagnosis(void) +__KNL__ void cpu_fault_diagnosis(void) { port_fault_diagnosis(); } diff --git a/arch/arm/arm-v7m/common/tos_fault.c b/arch/arm/arm-v7m/common/tos_fault.c index 65ae7e02..23958806 100644 --- a/arch/arm/arm-v7m/common/tos_fault.c +++ b/arch/arm/arm-v7m/common/tos_fault.c @@ -222,7 +222,7 @@ __STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); } -__KERNEL__ int fault_default_log_writer(const char *format, ...) +__KNL__ int fault_default_log_writer(const char *format, ...) { int len; va_list ap; @@ -239,7 +239,7 @@ __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) k_fault_log_writer = log_writer; } -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) { fault_info_t info; diff --git a/arch/arm/arm-v8m/common/include/tos_cpu.h b/arch/arm/arm-v8m/common/include/tos_cpu.h index 2ad847fb..86e673f4 100644 --- a/arch/arm/arm-v8m/common/include/tos_cpu.h +++ b/arch/arm/arm-v8m/common/include/tos_cpu.h @@ -58,25 +58,25 @@ __API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); #endif -__KERNEL__ void cpu_init(void); +__KNL__ void cpu_init(void); -__KERNEL__ void cpu_reset(void); +__KNL__ void cpu_reset(void); -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); -__KERNEL__ void cpu_sched_start(void); +__KNL__ void cpu_sched_start(void); -__KERNEL__ void cpu_context_switch(void); +__KNL__ void cpu_context_switch(void); -__KERNEL__ void cpu_irq_context_switch(void); +__KNL__ void cpu_irq_context_switch(void); #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); #endif -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -84,29 +84,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ void cpu_systick_resume(void); +__KNL__ void cpu_systick_resume(void); -__KERNEL__ void cpu_systick_suspend(void); +__KNL__ void cpu_systick_suspend(void); -__KERNEL__ void cpu_systick_reload_reset(void); +__KNL__ void cpu_systick_reload_reset(void); -__KERNEL__ void cpu_systick_pending_reset(void); +__KNL__ void cpu_systick_pending_reset(void); -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); -__KERNEL__ void cpu_systick_reset(void); +__KNL__ void cpu_systick_reset(void); #endif #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void); +__KNL__ void cpu_sleep_mode_enter(void); -__KERNEL__ void cpu_stop_mode_enter(void); +__KNL__ void cpu_stop_mode_enter(void); -__KERNEL__ void cpu_standby_mode_enter(void); +__KNL__ void cpu_standby_mode_enter(void); #endif @@ -114,11 +114,11 @@ __KERNEL__ void cpu_standby_mode_enter(void); #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void); +__KNL__ void cpu_flush_fpu(void); #endif /* TOS_CFG_CPU_ARM_FPU_EN */ -__KERNEL__ void cpu_fault_diagnosis(void); +__KNL__ void cpu_fault_diagnosis(void); #endif diff --git a/arch/arm/arm-v8m/common/include/tos_cpu_def.h b/arch/arm/arm-v8m/common/include/tos_cpu_def.h index f71d7c8e..50d0d838 100644 --- a/arch/arm/arm-v8m/common/include/tos_cpu_def.h +++ b/arch/arm/arm-v8m/common/include/tos_cpu_def.h @@ -18,17 +18,13 @@ #ifndef _TOS_CPU_DEF_H_ #define _TOS_CPU_DEF_H_ -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 #endif /* _TOS_CPU_DEF_H_ */ diff --git a/arch/arm/arm-v8m/common/include/tos_fault.h b/arch/arm/arm-v8m/common/include/tos_fault.h index 784c5f9d..46ada763 100644 --- a/arch/arm/arm-v8m/common/include/tos_fault.h +++ b/arch/arm/arm-v8m/common/include/tos_fault.h @@ -226,9 +226,9 @@ __STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); -__KERNEL__ int fault_default_log_writer(const char *format, ...); +__KNL__ int fault_default_log_writer(const char *format, ...); -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); #endif diff --git a/arch/arm/arm-v8m/common/tos_cpu.c b/arch/arm/arm-v8m/common/tos_cpu.c index 2dc1ef25..bf01ff9e 100644 --- a/arch/arm/arm-v8m/common/tos_cpu.c +++ b/arch/arm/arm-v8m/common/tos_cpu.c @@ -76,7 +76,7 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) port_cpsr_restore(cpsr); } -__KERNEL__ void cpu_init(void) +__KNL__ void cpu_init(void) { k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; cpu_systick_init(k_cpu_cycle_per_tick); @@ -86,27 +86,27 @@ __KERNEL__ void cpu_init(void) #endif } -__KERNEL__ void cpu_reset(void) +__KNL__ void cpu_reset(void) { port_cpu_reset(); } -__KERNEL__ void cpu_sched_start(void) +__KNL__ void cpu_sched_start(void) { port_sched_start(); } -__KERNEL__ void cpu_context_switch(void) +__KNL__ void cpu_context_switch(void) { port_context_switch(); } -__KERNEL__ void cpu_irq_context_switch(void) +__KNL__ void cpu_irq_context_switch(void) { port_irq_context_switch(); } -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); port_systick_config(cycle_per_tick); @@ -131,7 +131,7 @@ __STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) * * @return None */ -__KERNEL__ void cpu_systick_resume(void) +__KNL__ void cpu_systick_resume(void) { port_systick_resume(); } @@ -141,17 +141,17 @@ __KERNEL__ void cpu_systick_resume(void) * * @return None */ -__KERNEL__ void cpu_systick_suspend(void) +__KNL__ void cpu_systick_suspend(void) { port_systick_suspend(); } -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void) { return port_systick_max_delay_millisecond(); } -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) +__KNL__ void cpu_systick_expires_set(k_time_t millisecond) { k_cycle_t cycles; @@ -160,12 +160,12 @@ __KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) cpu_systick_reload(cycles - 12); /* interrupt delay */ } -__KERNEL__ void cpu_systick_pending_reset(void) +__KNL__ void cpu_systick_pending_reset(void) { port_systick_pending_reset(); } -__KERNEL__ void cpu_systick_reset(void) +__KNL__ void cpu_systick_reset(void) { cpu_systick_reload(k_cpu_cycle_per_tick); } @@ -174,24 +174,24 @@ __KERNEL__ void cpu_systick_reset(void) #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void) +__KNL__ void cpu_sleep_mode_enter(void) { port_sleep_mode_enter(); } -__KERNEL__ void cpu_stop_mode_enter(void) +__KNL__ void cpu_stop_mode_enter(void) { port_stop_mode_enter(); } -__KERNEL__ void cpu_standby_mode_enter(void) +__KNL__ void cpu_standby_mode_enter(void) { port_standby_mode_enter(); } #endif /* TOS_CFG_PWR_MGR_EN */ -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -248,7 +248,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) { uint8_t *slot; uint8_t *sp, *bp; @@ -278,13 +278,13 @@ __KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_ #if TOS_CFG_FAULT_BACKTRACE_EN > 0u #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void) +__KNL__ void cpu_flush_fpu(void) { (void)__get_FPSCR(); } #endif -__KERNEL__ void cpu_fault_diagnosis(void) +__KNL__ void cpu_fault_diagnosis(void) { port_fault_diagnosis(); } diff --git a/arch/arm/arm-v8m/common/tos_fault.c b/arch/arm/arm-v8m/common/tos_fault.c index 65ae7e02..23958806 100644 --- a/arch/arm/arm-v8m/common/tos_fault.c +++ b/arch/arm/arm-v8m/common/tos_fault.c @@ -222,7 +222,7 @@ __STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); } -__KERNEL__ int fault_default_log_writer(const char *format, ...) +__KNL__ int fault_default_log_writer(const char *format, ...) { int len; va_list ap; @@ -239,7 +239,7 @@ __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) k_fault_log_writer = log_writer; } -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) { fault_info_t info; diff --git a/arch/linux/common/include/tos_cpu.h b/arch/linux/common/include/tos_cpu.h index 736077a9..9a8c0c8d 100644 --- a/arch/linux/common/include/tos_cpu.h +++ b/arch/linux/common/include/tos_cpu.h @@ -45,25 +45,25 @@ __API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); #endif -__KERNEL__ void cpu_init(void); +__KNL__ void cpu_init(void); -__KERNEL__ void cpu_reset(void); +__KNL__ void cpu_reset(void); -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); -__KERNEL__ void cpu_sched_start(void); +__KNL__ void cpu_sched_start(void); -__KERNEL__ void cpu_context_switch(void); +__KNL__ void cpu_context_switch(void); -__KERNEL__ void cpu_irq_context_switch(void); +__KNL__ void cpu_irq_context_switch(void); #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); #endif -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -71,29 +71,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ void cpu_systick_resume(void); +__KNL__ void cpu_systick_resume(void); -__KERNEL__ void cpu_systick_suspend(void); +__KNL__ void cpu_systick_suspend(void); -__KERNEL__ void cpu_systick_reload_reset(void); +__KNL__ void cpu_systick_reload_reset(void); -__KERNEL__ void cpu_systick_pending_reset(void); +__KNL__ void cpu_systick_pending_reset(void); -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); -__KERNEL__ void cpu_systick_reset(void); +__KNL__ void cpu_systick_reset(void); #endif #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void); +__KNL__ void cpu_sleep_mode_enter(void); -__KERNEL__ void cpu_stop_mode_enter(void); +__KNL__ void cpu_stop_mode_enter(void); -__KERNEL__ void cpu_standby_mode_enter(void); +__KNL__ void cpu_standby_mode_enter(void); #endif @@ -101,11 +101,11 @@ __KERNEL__ void cpu_standby_mode_enter(void); #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void); +__KNL__ void cpu_flush_fpu(void); #endif /* TOS_CFG_CPU_ARM_FPU_EN */ -__KERNEL__ void cpu_fault_diagnosis(void); +__KNL__ void cpu_fault_diagnosis(void); #endif diff --git a/arch/linux/common/include/tos_cpu_def.h b/arch/linux/common/include/tos_cpu_def.h index f71d7c8e..50d0d838 100644 --- a/arch/linux/common/include/tos_cpu_def.h +++ b/arch/linux/common/include/tos_cpu_def.h @@ -18,17 +18,13 @@ #ifndef _TOS_CPU_DEF_H_ #define _TOS_CPU_DEF_H_ -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 #endif /* _TOS_CPU_DEF_H_ */ diff --git a/arch/linux/common/include/tos_fault.h b/arch/linux/common/include/tos_fault.h index 784c5f9d..46ada763 100644 --- a/arch/linux/common/include/tos_fault.h +++ b/arch/linux/common/include/tos_fault.h @@ -226,9 +226,9 @@ __STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); -__KERNEL__ int fault_default_log_writer(const char *format, ...); +__KNL__ int fault_default_log_writer(const char *format, ...); -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); #endif diff --git a/arch/linux/common/tos_cpu.c b/arch/linux/common/tos_cpu.c index 246ec2bf..f697b62c 100644 --- a/arch/linux/common/tos_cpu.c +++ b/arch/linux/common/tos_cpu.c @@ -76,7 +76,7 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) port_cpsr_restore(cpsr); } -__KERNEL__ void cpu_init(void) +__KNL__ void cpu_init(void) { port_init(); k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; @@ -87,27 +87,27 @@ __KERNEL__ void cpu_init(void) #endif } -__KERNEL__ void cpu_reset(void) +__KNL__ void cpu_reset(void) { port_cpu_reset(); } -__KERNEL__ void cpu_sched_start(void) +__KNL__ void cpu_sched_start(void) { port_sched_start(); } -__KERNEL__ void cpu_context_switch(void) +__KNL__ void cpu_context_switch(void) { port_context_switch(); } -__KERNEL__ void cpu_irq_context_switch(void) +__KNL__ void cpu_irq_context_switch(void) { port_irq_context_switch(); } -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { port_systick_config(cycle_per_tick); } @@ -131,7 +131,7 @@ __STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) * * @return None */ -__KERNEL__ void cpu_systick_resume(void) +__KNL__ void cpu_systick_resume(void) { port_systick_resume(); } @@ -141,17 +141,17 @@ __KERNEL__ void cpu_systick_resume(void) * * @return None */ -__KERNEL__ void cpu_systick_suspend(void) +__KNL__ void cpu_systick_suspend(void) { port_systick_suspend(); } -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void) { return port_systick_max_delay_millisecond(); } -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) +__KNL__ void cpu_systick_expires_set(k_time_t millisecond) { k_cycle_t cycles; @@ -160,12 +160,12 @@ __KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) cpu_systick_reload(cycles - 12); /* interrupt delay */ } -__KERNEL__ void cpu_systick_pending_reset(void) +__KNL__ void cpu_systick_pending_reset(void) { port_systick_pending_reset(); } -__KERNEL__ void cpu_systick_reset(void) +__KNL__ void cpu_systick_reset(void) { cpu_systick_reload(k_cpu_cycle_per_tick); } @@ -174,24 +174,24 @@ __KERNEL__ void cpu_systick_reset(void) #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void) +__KNL__ void cpu_sleep_mode_enter(void) { port_sleep_mode_enter(); } -__KERNEL__ void cpu_stop_mode_enter(void) +__KNL__ void cpu_stop_mode_enter(void) { port_stop_mode_enter(); } -__KERNEL__ void cpu_standby_mode_enter(void) +__KNL__ void cpu_standby_mode_enter(void) { port_standby_mode_enter(); } #endif /* TOS_CFG_PWR_MGR_EN */ -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -219,7 +219,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) { uint8_t *slot; uint8_t *sp, *bp; @@ -249,13 +249,13 @@ __KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_ #if TOS_CFG_FAULT_BACKTRACE_EN > 0u #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void) +__KNL__ void cpu_flush_fpu(void) { (void)__get_FPSCR(); } #endif -__KERNEL__ void cpu_fault_diagnosis(void) +__KNL__ void cpu_fault_diagnosis(void) { port_fault_diagnosis(); } diff --git a/arch/linux/common/tos_fault.c b/arch/linux/common/tos_fault.c index 65ae7e02..23958806 100644 --- a/arch/linux/common/tos_fault.c +++ b/arch/linux/common/tos_fault.c @@ -222,7 +222,7 @@ __STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); } -__KERNEL__ int fault_default_log_writer(const char *format, ...) +__KNL__ int fault_default_log_writer(const char *format, ...) { int len; va_list ap; @@ -239,7 +239,7 @@ __API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) k_fault_log_writer = log_writer; } -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) { fault_info_t info; diff --git a/arch/msp430/common/include/tos_cpu.h b/arch/msp430/common/include/tos_cpu.h index c85ce18c..9c7041d1 100644 --- a/arch/msp430/common/include/tos_cpu.h +++ b/arch/msp430/common/include/tos_cpu.h @@ -5,7 +5,7 @@ typedef struct cpu_context_st { cpu_data_t _R0; //PC //cpu_data_t _R1; //SP cpu_data_t _R2; //SR - //cpu_data_t _R3; + //cpu_data_t _R3; cpu_data_t _R4; cpu_data_t _R5; cpu_data_t _R6; @@ -38,25 +38,25 @@ __API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); #endif -__KERNEL__ void cpu_init(void); +__KNL__ void cpu_init(void); -__KERNEL__ void cpu_reset(void); +__KNL__ void cpu_reset(void); -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); -__KERNEL__ void cpu_sched_start(void); +__KNL__ void cpu_sched_start(void); -__KERNEL__ void cpu_context_switch(void); +__KNL__ void cpu_context_switch(void); -__KERNEL__ void cpu_irq_context_switch(void); +__KNL__ void cpu_irq_context_switch(void); #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); #endif -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -64,29 +64,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ void cpu_systick_resume(void); +__KNL__ void cpu_systick_resume(void); -__KERNEL__ void cpu_systick_suspend(void); +__KNL__ void cpu_systick_suspend(void); -__KERNEL__ void cpu_systick_reload_reset(void); +__KNL__ void cpu_systick_reload_reset(void); -__KERNEL__ void cpu_systick_pending_reset(void); +__KNL__ void cpu_systick_pending_reset(void); -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); -__KERNEL__ void cpu_systick_reset(void); +__KNL__ void cpu_systick_reset(void); #endif #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void); +__KNL__ void cpu_sleep_mode_enter(void); -__KERNEL__ void cpu_stop_mode_enter(void); +__KNL__ void cpu_stop_mode_enter(void); -__KERNEL__ void cpu_standby_mode_enter(void); +__KNL__ void cpu_standby_mode_enter(void); #endif @@ -94,11 +94,11 @@ __KERNEL__ void cpu_standby_mode_enter(void); #if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void); +__KNL__ void cpu_flush_fpu(void); #endif /* TOS_CFG_CPU_ARM_FPU_EN */ -__KERNEL__ void cpu_fault_diagnosis(void); +__KNL__ void cpu_fault_diagnosis(void); #endif diff --git a/arch/msp430/common/include/tos_cpu_def.h b/arch/msp430/common/include/tos_cpu_def.h index cde7ce52..f4e48687 100644 --- a/arch/msp430/common/include/tos_cpu_def.h +++ b/arch/msp430/common/include/tos_cpu_def.h @@ -1,17 +1,13 @@ #ifndef _TOS_CPU_DEF_H_ #define _TOS_CPU_DEF_H_ -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 #endif /* _TOS_CPU_DEF_H_ */ diff --git a/arch/msp430/common/tos_cpu.c b/arch/msp430/common/tos_cpu.c index e22e535e..ad08b392 100644 --- a/arch/msp430/common/tos_cpu.c +++ b/arch/msp430/common/tos_cpu.c @@ -78,32 +78,32 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) port_cpsr_restore(cpsr); } -__KERNEL__ void cpu_init(void) +__KNL__ void cpu_init(void) { } -__KERNEL__ void cpu_reset(void) +__KNL__ void cpu_reset(void) { port_cpu_reset(); } -__KERNEL__ void cpu_sched_start(void) +__KNL__ void cpu_sched_start(void) { port_sched_start(); } -__KERNEL__ void cpu_context_switch(void) +__KNL__ void cpu_context_switch(void) { port_context_switch(); } -__KERNEL__ void cpu_irq_context_switch(void) +__KNL__ void cpu_irq_context_switch(void) { irq_context_switch_flag = 1;//port_irq_context_switch(); } -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); port_systick_config(cycle_per_tick); @@ -128,7 +128,7 @@ __STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) * * @return None */ -__KERNEL__ void cpu_systick_resume(void) +__KNL__ void cpu_systick_resume(void) { port_systick_resume(); } @@ -138,17 +138,17 @@ __KERNEL__ void cpu_systick_resume(void) * * @return None */ -__KERNEL__ void cpu_systick_suspend(void) +__KNL__ void cpu_systick_suspend(void) { port_systick_suspend(); } -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void) { return port_systick_max_delay_millisecond(); } -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) +__KNL__ void cpu_systick_expires_set(k_time_t millisecond) { k_cycle_t cycles; @@ -157,12 +157,12 @@ __KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) cpu_systick_reload(cycles - 12); /* interrupt delay */ } -__KERNEL__ void cpu_systick_pending_reset(void) +__KNL__ void cpu_systick_pending_reset(void) { port_systick_pending_reset(); } -__KERNEL__ void cpu_systick_reset(void) +__KNL__ void cpu_systick_reset(void) { cpu_systick_reload(k_cpu_cycle_per_tick); } @@ -171,25 +171,25 @@ __KERNEL__ void cpu_systick_reset(void) #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void) +__KNL__ void cpu_sleep_mode_enter(void) { __bis_SR_register( LPM4_bits + GIE ); __no_operation(); } -__KERNEL__ void cpu_stop_mode_enter(void) +__KNL__ void cpu_stop_mode_enter(void) { } -__KERNEL__ void cpu_standby_mode_enter(void) +__KNL__ void cpu_standby_mode_enter(void) { } #endif /* TOS_CFG_PWR_MGR_EN */ -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -273,7 +273,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) { uint8_t *slot; uint8_t *sp, *bp; @@ -302,7 +302,7 @@ __KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_ #if TOS_CFG_FAULT_BACKTRACE_EN > 0u -__KERNEL__ void cpu_fault_diagnosis(void) +__KNL__ void cpu_fault_diagnosis(void) { port_fault_diagnosis(); } diff --git a/arch/risc-v/common/include/tos_cpu.h b/arch/risc-v/common/include/tos_cpu.h index 9e23f78e..a306c0c1 100644 --- a/arch/risc-v/common/include/tos_cpu.h +++ b/arch/risc-v/common/include/tos_cpu.h @@ -65,19 +65,19 @@ __API__ cpu_cpsr_t tos_cpu_cpsr_save(void); __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr); -__KERNEL__ void cpu_init(void); +__KNL__ void cpu_init(void); -__KERNEL__ void cpu_reset(void); +__KNL__ void cpu_reset(void); -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); -__KERNEL__ void cpu_sched_start(void); +__KNL__ void cpu_sched_start(void); -__KERNEL__ void cpu_context_switch(void); +__KNL__ void cpu_context_switch(void); -__KERNEL__ void cpu_irq_context_switch(void); +__KNL__ void cpu_irq_context_switch(void); -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, @@ -85,29 +85,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ void cpu_systick_resume(void); +__KNL__ void cpu_systick_resume(void); -__KERNEL__ void cpu_systick_suspend(void); +__KNL__ void cpu_systick_suspend(void); -__KERNEL__ void cpu_systick_reload_reset(void); +__KNL__ void cpu_systick_reload_reset(void); -__KERNEL__ void cpu_systick_pending_reset(void); +__KNL__ void cpu_systick_pending_reset(void); -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); -__KERNEL__ void cpu_systick_reset(void); +__KNL__ void cpu_systick_reset(void); #endif #if TOS_CFG_PWR_MGR_EN > 0u -__KERNEL__ void cpu_sleep_mode_enter(void); +__KNL__ void cpu_sleep_mode_enter(void); -__KERNEL__ void cpu_stop_mode_enter(void); +__KNL__ void cpu_stop_mode_enter(void); -__KERNEL__ void cpu_standby_mode_enter(void); +__KNL__ void cpu_standby_mode_enter(void); #endif diff --git a/arch/risc-v/common/include/tos_cpu_def.h b/arch/risc-v/common/include/tos_cpu_def.h index b4126252..6fbb054a 100644 --- a/arch/risc-v/common/include/tos_cpu_def.h +++ b/arch/risc-v/common/include/tos_cpu_def.h @@ -18,16 +18,13 @@ #ifndef _TOS_CPU_DEF_H_ #define _TOS_CPU_DEF_H_ -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 #endif /* _TOS_CPU_DEF_H_ */ + diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c index 25e9cd81..3704db4f 100644 --- a/arch/risc-v/common/tos_cpu.c +++ b/arch/risc-v/common/tos_cpu.c @@ -26,13 +26,13 @@ k_stack_t k_irq_stk[TOS_CFG_IRQ_STK_SIZE]; k_stack_t *k_irq_stk_top = k_irq_stk + TOS_CFG_IRQ_STK_SIZE; -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); port_systick_config(cycle_per_tick); } -__KERNEL__ void cpu_init(void) { +__KNL__ void cpu_init(void) { // reserve storage space for sp registers k_irq_stk_top = (k_stack_t *)(((cpu_addr_t) k_irq_stk_top) - sizeof(cpu_data_t)); @@ -67,17 +67,17 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) } -__KERNEL__ void cpu_context_switch(void) +__KNL__ void cpu_context_switch(void) { port_context_switch(); } -__KERNEL__ void cpu_irq_context_switch(void) +__KNL__ void cpu_irq_context_switch(void) { // DO NOTHING } -__KERNEL__ void cpu_sched_start(void) +__KNL__ void cpu_sched_start(void) { port_sched_start(); } @@ -120,7 +120,7 @@ Inx Offset Register */ -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, void *arg, void *exit, k_stack_t *stk_base, diff --git a/arch/stm8/common/include/tos_cpu.h b/arch/stm8/common/include/tos_cpu.h new file mode 100644 index 00000000..9ae1c052 --- /dev/null +++ b/arch/stm8/common/include/tos_cpu.h @@ -0,0 +1,133 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_H_ +#define _TOS_CPU_H_ + +typedef struct cpu_context_st { + cpu_data_t b15; + cpu_data_t b14; + cpu_data_t b13; + cpu_data_t b12; + cpu_data_t b11; + cpu_data_t b10; + cpu_data_t b9; + cpu_data_t b8; + + cpu_data_t CC; + cpu_data_t A; + cpu_data_t XH; + cpu_data_t XL; + cpu_data_t YH; + cpu_data_t YL; + cpu_data_t PCH; + cpu_data_t PCL; +} cpu_context_t; + +__API__ uint32_t tos_cpu_clz(uint32_t val); + +__API__ void tos_cpu_int_disable(void); + +__API__ void tos_cpu_int_enable(void); + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void); + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr); + +#if (TOS_CFG_CPU_HRTIMER_EN > 0u) + +__API__ void tos_cpu_hrtimer_init(void); + +__API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); + +#endif + +__KNL__ void cpu_init(void); + +__KNL__ void cpu_reset(void); + +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); + +__KNL__ void cpu_sched_start(void); + +__KNL__ void cpu_context_switch(void); + +__KNL__ void cpu_irq_context_switch(void); + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); + +#endif + +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size); + +#if TOS_CFG_TICKLESS_EN > 0u + +__KNL__ void cpu_systick_resume(void); + +__KNL__ void cpu_systick_suspend(void); + +__KNL__ void cpu_systick_reload_reset(void); + +__KNL__ void cpu_systick_pending_reset(void); + +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); + +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); + +__KNL__ void cpu_systick_reset(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__KNL__ void cpu_sleep_mode_enter(void); + +__KNL__ void cpu_stop_mode_enter(void); + +__KNL__ void cpu_standby_mode_enter(void); + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +__KNL__ void cpu_fault_diagnosis(void); + +#endif + +/* Allocates CPU status register word. */ +#define TOS_CPU_CPSR_ALLOC() cpu_cpsr_t cpu_cpsr = (cpu_cpsr_t)0u + +/* Save CPU status word & disable interrupts.*/ +#define TOS_CPU_INT_DISABLE() \ + do { \ + cpu_cpsr = tos_cpu_cpsr_save(); \ + } while (0) + +/* Restore CPU status word. */ +#define TOS_CPU_INT_ENABLE() \ + do { \ + tos_cpu_cpsr_restore(cpu_cpsr); \ + } while (0) + +#endif /* _TOS_CPU_H_ */ + diff --git a/arch/stm8/common/include/tos_cpu_def.h b/arch/stm8/common/include/tos_cpu_def.h new file mode 100644 index 00000000..50d0d838 --- /dev/null +++ b/arch/stm8/common/include/tos_cpu_def.h @@ -0,0 +1,30 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_DEF_H_ +#define _TOS_CPU_DEF_H_ + +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 + +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 + +#endif /* _TOS_CPU_DEF_H_ */ + diff --git a/arch/stm8/common/include/tos_cpu_types.h b/arch/stm8/common/include/tos_cpu_types.h new file mode 100644 index 00000000..62d9e014 --- /dev/null +++ b/arch/stm8/common/include/tos_cpu_types.h @@ -0,0 +1,57 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_TYPES_H_ +#define _TOS_CPU_TYPES_H_ + +/* CPU address type based on address bus size. */ +#if (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_addr_t; +#elif (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_addr_t; +#else +typedef uint8_t cpu_addr_t; +#endif + +/* CPU data type based on data bus size. */ +#if (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_data_t; +#elif (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_data_t; +#else +typedef uint8_t cpu_data_t; +#endif + +#if (TOS_CFG_CPU_HRTIMER_EN > 0) +#if (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_08) +typedef uint8_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_64) +typedef uint64_t cpu_hrtimer_t; +#else +typedef uint32_t cpu_hrtimer_t; +#endif +#else +typedef uint32_t cpu_hrtimer_t; +#endif + +//typedef cpu_addr_t size_t; +typedef cpu_addr_t cpu_cpsr_t; + +#endif + diff --git a/arch/stm8/common/include/tos_fault.h b/arch/stm8/common/include/tos_fault.h new file mode 100644 index 00000000..e0fc0781 --- /dev/null +++ b/arch/stm8/common/include/tos_fault.h @@ -0,0 +1,206 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_FAULT_H_ +#define _TOS_FAULT_H_ + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +typedef int (*k_fault_log_writer_t)(const char *format, ...); + +#define K_FAULT_STACK_DUMP_DEPTH 10u + +#define K_FAULT_CALL_STACK_BACKTRACE_DEPTH 5u + +typedef struct fault_cpu_frame_st { + cpu_data_t r0; + cpu_data_t r1; + cpu_data_t r2; + cpu_data_t r3; + cpu_data_t r12; + cpu_data_t lr; + cpu_data_t pc; + cpu_data_t spsr; +} fault_cpu_frame_t; + +typedef struct fault_exc_frame_st { + fault_cpu_frame_t cpu_frame; +} fault_exc_frame_t; + +/** + * information we need to do fault backtrace + */ +typedef struct fault_information_st { + int is_thumb : 1; /**< whether it is thumb we use when we fall into fault? */ + int is_on_task : 1; /**< whether we are on a task when fall into fault? */ + int is_stk_ovrf : 1; /**< whether we get a stack overflow */ + + cpu_addr_t pc; /**< just where fault happens */ + + cpu_addr_t sp_before_fault; /**< original sp just before the cpu push the fault exception frame */ + + /** + * we need main_stack_start & main_stack_limit to do call stack backtrace + * when we fall into fault during a task, we should do the call stack backtrace on the task's stack + * but if not, which means we are in kernel, we should do the call stack backtrace on the main stack + * in arm v7-m, this should be the MSP's start and limit + * in arm v7-a, call stack backtrace is another story(much more elegant because we have FP). + */ + cpu_addr_t stack_start; /**< current sp start address we use. if on task, it'll be the task's stack, otherwise it'll be the msp */ + cpu_addr_t stack_limit; /**< current sp limit address */ + cpu_addr_t code_start; /**< current code start address */ + cpu_addr_t code_limit; /**< current code limit address */ +} fault_info_t; + +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + +#define DEFAULT_CODE_SECTION_NAME ER_IROM1 +#define DEFAULT_CSTACK_SECTION_NAME STACK + +#define SECTION_START(_name_) _name_##$$Base +#define SECTION_END(_name_) _name_##$$Limit +#define IMAGE_SECTION_START(_name_) Image$$##_name_##$$Base +#define IMAGE_SECTION_END(_name_) Image$$##_name_##$$Limit +#define CSTACK_BLOCK_START(_name_) SECTION_START(_name_) +#define CSTACK_BLOCK_END(_name_) SECTION_END(_name_) +#define CODE_SECTION_START(_name_) IMAGE_SECTION_START(_name_) +#define CODE_SECTION_END(_name_) IMAGE_SECTION_END(_name_) + +extern const int CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME); +extern const int CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME); +extern const int CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME); +extern const int CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME); + +__STATIC_INLINE__ cpu_addr_t fault_code_start(void) +{ + return (cpu_addr_t)&CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) +{ + return (cpu_addr_t)&CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) +{ + return (cpu_addr_t)&CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) +{ + return (cpu_addr_t)&CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME); +} + +#elif defined(__ICCARM__) + +#define DEFAULT_CODE_SECTION_NAME ".text" +#define DEFAULT_CSTACK_SECTION_NAME "CSTACK" + +#pragma section=DEFAULT_CSTACK_SECTION_NAME +#pragma section=DEFAULT_CODE_SECTION_NAME + +__STATIC_INLINE__ cpu_addr_t fault_code_start(void) +{ + return (cpu_addr_t)__section_begin(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) +{ + return (cpu_addr_t)__section_end(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) +{ + return (cpu_addr_t)__section_begin(DEFAULT_CSTACK_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) +{ + return (cpu_addr_t)__section_end(DEFAULT_CSTACK_SECTION_NAME); +} + +#elif defined(__GNUC__) + +/** + * if we are using keil(armcc) or mdk(iccarm), we probably use the defult link script supplied by the IDE. + * the way to locate the text/stack section start and limit is to find them in default link script. + * but if we build our project by makefile(or something like scons, cmake, etc), we probably need to write + * our own link scrpit, if so, we should do like this(just a demo): + * + _stext = .; + .text : { + *(.text.startup) + *(.text) + *(.text.*) + } + _etext = .; + + __bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + *(COMMON) + _sstack = .; + *(.cstack) + _estack = .; + } + __bss_end = .; + * by this, we can locate text/stack section start and limit by _stext/_etext and _sstack/_estack + */ +#define DEFAULT_CODE_SECTION_START _stext +#define DEFAULT_CODE_SECTION_END _etext +#define DEFAULT_CSTACK_SECTION_START _sstack +#define DEFAULT_CSTACK_SECTION_END _estack + +extern const int DEFAULT_CODE_SECTION_START; +extern const int DEFAULT_CODE_SECTION_END; + +extern const int DEFAULT_CSTACK_SECTION_START; +extern const int DEFAULT_CSTACK_SECTION_END; + +__STATIC_INLINE__ cpu_addr_t fault_code_start(void) +{ + return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_START)); +} + +__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) +{ + return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_END)); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) +{ + return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_START)); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) +{ + return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_END)); +} + +#endif + +__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); + +__KNL__ int fault_default_log_writer(const char *format, ...); + +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); + +#endif + +#endif /* _TOS_FAULT_H_ */ + diff --git a/arch/stm8/common/tos_cpu.c b/arch/stm8/common/tos_cpu.c new file mode 100644 index 00000000..92f12b9a --- /dev/null +++ b/arch/stm8/common/tos_cpu.c @@ -0,0 +1,297 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ uint32_t tos_cpu_clz(uint32_t val) +{ +#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 0u) + uint32_t nbr_lead_zeros = 0; + + if (!(val & 0XFFFF0000)) { + val <<= 16; + nbr_lead_zeros += 16; + } + + if (!(val & 0XFF000000)) { + val <<= 8; + nbr_lead_zeros += 8; + } + + if (!(val & 0XF0000000)) { + val <<= 4; + nbr_lead_zeros += 4; + } + + if (!(val & 0XC0000000)) { + val <<= 2; + nbr_lead_zeros += 2; + } + + if (!(val & 0X80000000)) { + nbr_lead_zeros += 1; + } + + if (!val) { + nbr_lead_zeros += 1; + } + + return (nbr_lead_zeros); +#else + return port_clz(val); +#endif +} + +__API__ void tos_cpu_int_disable(void) +{ + port_int_disable(); +} + +__API__ void tos_cpu_int_enable(void) +{ + port_int_enable(); +} + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void) +{ + return port_cpsr_save(); +} + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) +{ + port_cpsr_restore(cpsr); +} + +__KNL__ void cpu_init(void) +{ + k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; + cpu_systick_init(k_cpu_cycle_per_tick); + +#if (TOS_CFG_CPU_HRTIMER_EN > 0) + tos_cpu_hrtimer_init(); +#endif +} + +__KNL__ void cpu_reset(void) +{ + port_cpu_reset(); +} + +__KNL__ void cpu_sched_start(void) +{ + port_sched_start(); +} + +__KNL__ void cpu_context_switch(void) +{ + port_context_switch(); +} + +__KNL__ void cpu_irq_context_switch(void) +{ + port_irq_context_switch(); +} + +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +{ +#if 0 + port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); + port_systick_config(cycle_per_tick); +#endif +} + +#if TOS_CFG_TICKLESS_EN > 0u + +/** + * @brief Set value to systick reload value register + * + * @param cycles The value set to register + * + * @return None + */ +__STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) +{ + port_systick_reload(cycle_per_tick); +} + +/** + * @brief Enable systick interrupt + * + * @return None + */ +__KNL__ void cpu_systick_resume(void) +{ + port_systick_resume(); +} + +/** + * @brief Disable systick interrupt + * + * @return None + */ +__KNL__ void cpu_systick_suspend(void) +{ + port_systick_suspend(); +} + +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void) +{ + return port_systick_max_delay_millisecond(); +} + +__KNL__ void cpu_systick_expires_set(k_time_t millisecond) +{ + k_cycle_t cycles; + + cycles = (k_cycle_t)((uint64_t)millisecond * TOS_CFG_CPU_CLOCK / K_TIME_MILLISEC_PER_SEC); /* CLOCK means cycle per second */ + + cpu_systick_reload(cycles - 12); /* interrupt delay */ +} + +__KNL__ void cpu_systick_pending_reset(void) +{ + port_systick_pending_reset(); +} + +__KNL__ void cpu_systick_reset(void) +{ + cpu_systick_reload(k_cpu_cycle_per_tick); +} + +#endif /* TOS_CFG_TICKLESS_EN */ + +#if TOS_CFG_PWR_MGR_EN > 0u + +__KNL__ void cpu_sleep_mode_enter(void) +{ + port_sleep_mode_enter(); +} + +__KNL__ void cpu_stop_mode_enter(void) +{ + port_stop_mode_enter(); +} + +__KNL__ void cpu_standby_mode_enter(void) +{ + port_standby_mode_enter(); +} + +#endif /* TOS_CFG_PWR_MGR_EN */ + +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size) +{ + cpu_data_t *sp; + + sp = (cpu_data_t *)&stk_base[stk_size]; + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + uint8_t *slot = (uint8_t *)&stk_base[0]; + for (; slot < (uint8_t *)sp; ++slot) { + *slot = 0xCC; + } +#endif + + *--sp = (cpu_data_t)((uint16_t)entry & 0xFF); /* PCL */ + *--sp = (cpu_data_t)(((uint16_t)entry >> 8) & 0xFF); /* PCH */ + + *--sp = (cpu_data_t)0x59; /* YL */ + *--sp = (cpu_data_t)0x59; /* YH */ + + *--sp = (cpu_data_t)((uint16_t)arg & 0xFF); /* XL */ + *--sp = (cpu_data_t)(((uint16_t)arg >> 8) & 0xFF); /* XH */ + + *--sp = 0xAA; /* A */ + + /* + ----------------------------------- + | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | + ----------------------------------- + | C | Z | N | I0 | H | I1 | - | V | + ----------------------------------- + + Interruptability levels: + ---------------------------------------------- + | Interruptability | Priority | I1 | I0 | + ---------------------------------------------- + | Interruptable Main | Lowest | 1 | 0 | + ------------------------| |---------- + | Interruptable Level 1 | ^ | 0 | 1 | + ------------------------| | |---------- + | Interruptable Level 2 | | | 0 | 0 | + ------------------------| |---------- + | Non Interruptable | Highest | 1 | 1 | + ------------------------------------------------ + */ + *--sp = 0x00; /* CC */ + + *--sp = 0x08; /* b8 */ + *--sp = 0x09; /* b9 */ + *--sp = 0x10; /* b10 */ + *--sp = 0x11; /* b11 */ + *--sp = 0x12; /* b12 */ + *--sp = 0x13; /* b13 */ + *--sp = 0x14; /* b14 */ + *--sp = 0x15; /* b15 */ + + /* ATTENTION: + must do a sp decrease here in STM8 + */ + return (k_stack_t *)(--sp); +} + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + +__KNL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +{ + uint8_t *slot; + uint8_t *sp, *bp; + int the_depth = 0; + + bp = (uint8_t *)&stk_base[0]; + + sp = &stk_base[stk_size]; + + for (slot = sp - 1; slot >= bp; --slot) { + if (*slot != 0xCC) { + the_depth = sp - slot; + } + } + + *depth = the_depth; + if (the_depth == stk_size) { + return K_ERR_TASK_STK_OVERFLOW; + } + + return K_ERR_NONE; +} + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +__KNL__ void cpu_fault_diagnosis(void) +{ + port_fault_diagnosis(); +} + +#endif /* TOS_CFG_FAULT_BACKTRACE_EN */ + diff --git a/arch/stm8/common/tos_fault.c b/arch/stm8/common/tos_fault.c new file mode 100644 index 00000000..1bdbd215 --- /dev/null +++ b/arch/stm8/common/tos_fault.c @@ -0,0 +1,205 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +__STATIC_INLINE__ void fault_spin(void) +{ + tos_knl_sched_lock(); + tos_cpu_int_disable(); + while (K_TRUE) { + ; + } +} + +/* EXC_RETURN: + 31 - 28 : EXC_RETURN flag + 27 - 5 : reserved + 4 : 1, basic stack frame; 0, extended stack frame + 3 : 1, return to Thread mode; 0, return to Handler mode + 2 : 1, return to PSP; 0, return to MSP + 1 : reserved, 0 + 0 : reserved, 1 + */ +__STATIC_INLINE__ int fault_is_on_task(cpu_data_t lr) +{ + return (lr & (1u << 2)) != 0; +} + +__STATIC_INLINE__ int fault_is_thumb(cpu_data_t psr) +{ + return (psr & (1u << 24)) != 0; +} + +__STATIC_INLINE__ int fault_is_code(fault_info_t *info, cpu_data_t value) +{ + return value >= info->code_start && value <= info->code_limit; +} + +__STATIC__ void fault_dump_cpu_frame(fault_cpu_frame_t *cpu_frame) +{ + k_fault_log_writer("\n\n====================== CPU Registers =======================\n"); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "R0 ", cpu_frame->r0, + "R1 ", cpu_frame->r1, + "R2 ", cpu_frame->r2, + "R3 ", cpu_frame->r3); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "R12", cpu_frame->r12, + "LR ", cpu_frame->lr, + "PC ", cpu_frame->pc, + "PSR", cpu_frame->spsr); +} + +__STATIC__ void fault_dump_stack(fault_info_t *info, size_t depth) +{ + cpu_addr_t sp = info->sp_before_fault;; + + k_fault_log_writer("\nTASK STACK DUMP:\n"); + while (sp <= info->stack_limit && depth--) { + k_fault_log_writer(" addr: %08x data: %08x\n", sp, (cpu_data_t)*(cpu_data_t *)sp); + sp += sizeof(cpu_addr_t); + } +} + +__STATIC__ void fault_call_stack_backtrace(fault_info_t *info, size_t depth) +{ + cpu_data_t value; + cpu_addr_t sp = info->sp_before_fault; + + if (info->is_stk_ovrf) { + return; + } + + k_fault_log_writer("\n\n====================== Dump Call Stack =====================\n"); + + k_fault_log_writer(" %x\n", info->pc); + + /* walk through the stack, check every content on stack whether is a instruction(code) */ + for (; sp < info->stack_limit && depth; sp += sizeof(cpu_addr_t)) { + value = *((cpu_addr_t *)sp) - sizeof(cpu_addr_t); + + /* if thumb, a instruction's first bit must be 1 */ + if (info->is_thumb && !(value & 1)) { + continue; + } + + if (fault_is_code(info, value)) { + k_fault_log_writer(" %x\n", value); + --depth; + } + } +} + +__STATIC__ void fault_dump_task(fault_info_t *info) +{ + k_task_t *task; + + if (!info->is_on_task) { + return; + } + + task = k_curr_task; + k_fault_log_writer("\n\n====================== Fault on task =======================\n"); + k_fault_log_writer(" TASK NAME: %s\n", task->name); + k_fault_log_writer(" STK BASE: %x\n", info->stack_start); + k_fault_log_writer(" STK SIZE: %x\n", task->stk_size * sizeof(k_stack_t)); + k_fault_log_writer(" STK LIMIT: %x\n", info->stack_limit); + + if (!info->is_stk_ovrf) { + fault_dump_stack(info, K_FAULT_STACK_DUMP_DEPTH); + } +} + +__STATIC__ void fault_dump_information(fault_info_t *info) +{ + k_fault_log_writer("\n\n================== Dump Fault Information ==================\n"); + k_fault_log_writer(" THUMB: %s\n", info->is_thumb ? "TRUE" : "FALSE"); + k_fault_log_writer(" ON TASK: %s\n", info->is_on_task? "TRUE" : "FALSE"); + k_fault_log_writer(" STK OVRF: %s\n", info->is_stk_ovrf? "TRUE" : "FALSE"); + + k_fault_log_writer(" PC: %08x\n", info->pc); + k_fault_log_writer(" SP: %08x\n", info->sp_before_fault); + k_fault_log_writer(" STK START: %08x\n", info->stack_start); + k_fault_log_writer(" STK LIMIT: %08x\n", info->stack_limit); + k_fault_log_writer(" COD START: %08x\n", info->code_start); + k_fault_log_writer(" COD LIMIT: %08x\n", info->code_limit); +} + +__STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame, fault_info_t *info) +{ + info->is_thumb = fault_is_thumb(frame->cpu_frame.spsr); + info->is_on_task = fault_is_on_task(lr); + + info->pc = frame->cpu_frame.pc; + + info->sp_before_fault = (cpu_addr_t)frame + sizeof(fault_cpu_frame_t); + + info->code_start = fault_code_start(); + info->code_limit = fault_code_limit(); + + if (info->is_on_task) { + info->stack_start = (cpu_addr_t)k_curr_task->stk_base; + info->stack_limit = info->stack_start + k_curr_task->stk_size * sizeof(k_task_t); + } else { + info->stack_start = fault_msp_start(); + info->stack_limit = fault_msp_limit(); + } + + info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); +} + +__KNL__ int fault_default_log_writer(const char *format, ...) +{ + int len; + va_list ap; + + va_start(ap, format); + len = vprintf(format, ap); + va_end(ap); + + return len; +} + +__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) +{ + k_fault_log_writer = log_writer; +} + +__KNL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) +{ + fault_info_t info; + + fault_gather_information(lr, frame, &info); + + fault_dump_information(&info); + + fault_dump_task(&info); + + fault_dump_cpu_frame(&frame->cpu_frame); + + fault_call_stack_backtrace(&info, K_FAULT_CALL_STACK_BACKTRACE_DEPTH); + + cpu_fault_diagnosis(); + + fault_spin(); +} + +#endif + diff --git a/arch/stm8/iccarm/port.h b/arch/stm8/iccarm/port.h new file mode 100644 index 00000000..5c77cfa1 --- /dev/null +++ b/arch/stm8/iccarm/port.h @@ -0,0 +1,70 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_H_ +#define _PORT_H_ + +#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u) +__PORT__ uint32_t port_clz(uint32_t val); +#endif + +__PORT__ void port_int_disable(void); + +__PORT__ void port_int_enable(void); + +__PORT__ cpu_cpsr_t port_cpsr_save(void); + +__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); + +__PORT__ void port_cpu_reset(void); + +__PORT__ void port_sched_start(void) __NO_RETURN__; + +__PORT__ void port_context_switch(void); + +__PORT__ void port_irq_context_switch(void); + +__PORT__ void port_systick_config(uint32_t cycle_per_tick); + +__PORT__ void port_systick_priority_set(uint32_t prio); + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ void port_systick_resume(void); + +__PORT__ void port_systick_suspend(void); + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick); + +__PORT__ void port_systick_pending_reset(void); + +__PORT__ k_time_t port_systick_max_delay_millisecond(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void); + +__PORT__ void port_stop_mode_enter(void); + +__PORT__ void port_standby_mode_enter(void); + +#endif + +#endif /* _PORT_H_ */ + diff --git a/arch/stm8/iccarm/port_c.c b/arch/stm8/iccarm/port_c.c new file mode 100644 index 00000000..e258b678 --- /dev/null +++ b/arch/stm8/iccarm/port_c.c @@ -0,0 +1,296 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +/* + * The MIT License (MIT) + * + * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com) + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "tos_k.h" + +__PORT__ void port_cpu_reset(void) +{ +#if 0 + NVIC_SystemReset(); +#endif +} + +__PORT__ void port_systick_config(uint32_t cycle_per_tick) +{ +#if 0 + (void)SysTick_Config(cycle_per_tick); +#endif +} + +__PORT__ void port_systick_priority_set(uint32_t prio) +{ +#if 0 + NVIC_SetPriority(SysTick_IRQn, prio); +#endif +} + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ k_time_t port_systick_max_delay_millisecond(void) +{ + k_time_t max_millisecond; + uint32_t max_cycle; + + max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit + max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second + return max_millisecond; +} + +__PORT__ void port_systick_resume(void) +{ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +__PORT__ void port_systick_suspend(void) +{ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +__PORT__ k_cycle_t port_systick_max_reload_cycle(void) +{ + return SysTick_LOAD_RELOAD_Msk; +} + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick) +{ + uint32_t max_cycle; + + max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit + + if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) { + SysTick->LOAD = max_cycle; + } else { + SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL; + } + + SysTick->VAL = 0; +} + +__PORT__ void port_systick_pending_reset(void) +{ + SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk; +} + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void) +{ +#if 1 + HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); +#else + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); +#endif +} + +__PORT__ void port_stop_mode_enter(void) +{ + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); +} + +__PORT__ void port_standby_mode_enter(void) +{ + HAL_PWR_EnterSTANDBYMode(); +} + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs) +{ + k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n"); + + if (regs->hfsr.bits.VECTBL) { + k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]); + } + if (regs->hfsr.bits.FORCED) { + /* Memory Management Fault */ + if (regs->cfsr.part.mfsr.value) { + if (regs->cfsr.part.mfsr.bits.IACCVIOL) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]); + } + if (regs->cfsr.part.mfsr.bits.DACCVIOL) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]); + } + if (regs->cfsr.part.mfsr.bits.MUNSTKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]); + } + if (regs->cfsr.part.mfsr.bits.MSTKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]); + } + + if (regs->cfsr.part.mfsr.bits.MLSPERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]); + } + + if (regs->cfsr.part.mfsr.bits.MMARVALID) { + if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) { + k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar); + } + } + } + /* Bus Fault */ + if (regs->cfsr.part.bfsr.value) { + if (regs->cfsr.part.bfsr.bits.IBUSERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]); + } + if (regs->cfsr.part.bfsr.bits.PRECISERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]); + } + if (regs->cfsr.part.bfsr.bits.IMPREISERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]); + } + if (regs->cfsr.part.bfsr.bits.UNSTKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]); + } + if (regs->cfsr.part.bfsr.bits.STKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]); + } + + if (regs->cfsr.part.bfsr.bits.LSPERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]); + } + + if (regs->cfsr.part.bfsr.bits.BFARVALID) { + if (regs->cfsr.part.bfsr.bits.PRECISERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar); + } + } + + } + /* Usage Fault */ + if (regs->cfsr.part.ufsr.value) { + if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]); + } + if (regs->cfsr.part.ufsr.bits.INVSTATE) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]); + } + if (regs->cfsr.part.ufsr.bits.INVPC) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]); + } + if (regs->cfsr.part.ufsr.bits.NOCP) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]); + } + if (regs->cfsr.part.ufsr.bits.UNALIGNED) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]); + } + if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]); + } + } + } + /* Debug Fault */ + if (regs->hfsr.bits.DEBUGEVT) { + if (regs->dfsr.value) { + if (regs->dfsr.bits.HALTED) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]); + } + if (regs->dfsr.bits.BKPT) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]); + } + if (regs->dfsr.bits.DWTTRAP) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]); + } + if (regs->dfsr.bits.VCATCH) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]); + } + if (regs->dfsr.bits.EXTERNAL) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]); + } + } + } +} + +__PORT__ void port_fault_diagnosis(void) +{ + port_fault_regs_t regs; + + regs.syshndctrl.value = SCB->SHCSR; + regs.cfsr.value = SCB->CFSR; + regs.mmar = SCB->MMFAR; + regs.bfar = SCB->BFAR; + regs.hfsr.value = SCB->HFSR; + regs.dfsr.value = SCB->DFSR; + regs.afsr = SCB->AFSR; + + port_fault_do_diagnosis(®s); +} + +/*------------------ RealView Compiler -----------------*/ +/* V5 */ +#if defined(__CC_ARM) + +__PORT__ __ASM__ void HardFault_Handler(void) +{ + IMPORT fault_backtrace + + MOV r0, lr + TST lr, #0x04 + ITE EQ + MRSEQ r1, MSP + MRSNE r1, PSP + BL fault_backtrace +} + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +__PORT__ void __NAKED__ HardFault_Handler(void) +{ + __ASM__ __VOLATILE__ ( + "MOV r0, lr\n\t" + "TST lr, #0x04\n\t" + "ITE EQ\n\t" + "MRSEQ r1, MSP\n\t" + "MRSNE r1, PSP\n\t" + "BL fault_backtrace\n\t" + ); +} + +#endif /* ARMCC VERSION */ + +#endif /* TOS_CFG_FAULT_BACKTRACE_EN */ + diff --git a/arch/stm8/iccarm/port_config.h b/arch/stm8/iccarm/port_config.h new file mode 100644 index 00000000..8259022b --- /dev/null +++ b/arch/stm8/iccarm/port_config.h @@ -0,0 +1,30 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_CONFIG_H_ +#define _PORT_CONFIG_H_ + +#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_08 +#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_08 +#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING +#define TOS_CFG_CPU_HRTIMER_EN 0u +#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u + +#define TOS_CFG_CPU_ARM_FPU_EN 0u + +#endif /* _PORT_CONFIG_H_ */ + diff --git a/arch/stm8/iccarm/port_s.S b/arch/stm8/iccarm/port_s.S new file mode 100644 index 00000000..a55d2b62 --- /dev/null +++ b/arch/stm8/iccarm/port_s.S @@ -0,0 +1,100 @@ + SECTION .near_func.text:code + +; Get definitions for virtual registers used by the compiler +#include "vregs.inc" + + EXTERN k_curr_task + EXTERN k_next_task + + PUBLIC port_int_disable + PUBLIC port_int_enable + PUBLIC port_cpsr_save + PUBLIC port_cpsr_restore + PUBLIC port_sched_start + PUBLIC port_irq_context_switch + PUBLIC port_context_switch + +port_int_disable + SIM + RET + + +port_int_enable + RIM + RET + + +port_cpsr_save + /* does not work: + LD A, CC + */ + PUSH CC + POP A + SIM + RET + + +port_cpsr_restore + /* does not work: + LD CC, A + */ + PUSH A + POP CC + RIM + RET + + +port_sched_start: + JP _context_restore + + +port_irq_context_switch: +port_context_switch: +_context_save: + PUSHW Y + PUSHW X + PUSH A + PUSH CC + + PUSH ?b8 + PUSH ?b9 + PUSH ?b10 + PUSH ?b11 + PUSH ?b12 + PUSH ?b13 + PUSH ?b14 + PUSH ?b15 + + /* k_curr_task->sp = SP */ + LDW X, k_curr_task /* equls to: "ldr r0, =k_curr_task; ldr r0, [r0]" */ + LDW Y, SP + LDW (X), Y + +_context_restore: + ; k_curr_task = k_next_task + LDW X, k_next_task + LDW Y, #k_curr_task /* equls to: "ldr r0, =k_curr_task "*/ + LDW (Y), X + + /* SP = k_next_task->sp */ + LDW X, (X) + LDW SP, X + + POP ?b15 + POP ?b14 + POP ?b13 + POP ?b12 + POP ?b11 + POP ?b10 + POP ?b9 + POP ?b8 + + POP CC + POP A + POPW X + POPW Y + + RET + + END + diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/system.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/system.h index 77d0dcf0..6e329cb4 100644 --- a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/system.h +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/system.h @@ -217,7 +217,7 @@ do { \ : \ : "memory", "cc"); \ }) - + /* * Enable IRQs */ diff --git a/board/STM8L052R8T6/BSP/include/rtc.h b/board/STM8L052R8T6/BSP/include/rtc.h new file mode 100644 index 00000000..0652a9bc --- /dev/null +++ b/board/STM8L052R8T6/BSP/include/rtc.h @@ -0,0 +1,20 @@ +#ifndef __RTC_H_ +#define __RTC_H_ + +typedef struct +{ + uint8_t cSecond; + uint8_t cMinute; + uint8_t cHour; + uint8_t cWeek; + uint8_t cDay; + uint8_t cMonth; + uint8_t cYear; +} StruCLOCK; +extern StruCLOCK clock; + +void RTC_Setting_Init(void); +void RTC_Get_Time(void); + +#endif + diff --git a/board/STM8L052R8T6/BSP/include/tim.h b/board/STM8L052R8T6/BSP/include/tim.h new file mode 100644 index 00000000..23c36201 --- /dev/null +++ b/board/STM8L052R8T6/BSP/include/tim.h @@ -0,0 +1,7 @@ +#ifndef __TIM_H_ +#define __TIM_H_ + +void Timer2_Init(uint32_t clock, uint32_t tick_per_second); + +#endif + diff --git a/board/STM8L052R8T6/BSP/include/uart.h b/board/STM8L052R8T6/BSP/include/uart.h new file mode 100644 index 00000000..b1ed14ee --- /dev/null +++ b/board/STM8L052R8T6/BSP/include/uart.h @@ -0,0 +1,10 @@ +#ifndef __USART_H_ +#define __USART_H_ + +void UART1_Init(uint32_t uiBaudRate); +void UART1_Send_Byte(uint8_t ucData); +void UART1_Send_String(char *Str); +void UART1_Send_Dec(unsigned int num, unsigned char ucNumCount); + +#endif + diff --git a/board/STM8L052R8T6/BSP/src/rtc.c b/board/STM8L052R8T6/BSP/src/rtc.c new file mode 100644 index 00000000..11be8801 --- /dev/null +++ b/board/STM8L052R8T6/BSP/src/rtc.c @@ -0,0 +1,61 @@ +#include "stm8l15x.h" +#include "rtc.h" + +StruCLOCK clock; + +const uint8_t MonthLength[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +void RTC_Setting_Init(void) +{ + RTC_InitTypeDef RTC_InitStr; + RTC_TimeTypeDef RTC_TimeStr; + RTC_DateTypeDef RTC_DateStr; + + //RTC Clock Init + CLK_LSEConfig(CLK_LSE_ON); //Open LSE Clock 32.768K + while (CLK_GetFlagStatus(CLK_FLAG_LSERDY) == RESET) //wait is ready + ; + RTC_DeInit(); + CLK_RTCClockConfig(CLK_RTCCLKSource_LSE, CLK_RTCCLKDiv_1); //select LSE no div 32.768K + CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE); + RTC_WakeUpCmd(DISABLE); + + + RTC_InitStr.RTC_HourFormat = RTC_HourFormat_24; + RTC_InitStr.RTC_AsynchPrediv = 0x7f; //32.768K/(127+1)=256 + RTC_InitStr.RTC_SynchPrediv = 0x0ff; //256/(255+1)=1 + RTC_Init(&RTC_InitStr); + + //Write default time 18.1.1 00:00:00 + RTC_DateStructInit(&RTC_DateStr); + RTC_DateStr.RTC_Date = 1; + RTC_DateStr.RTC_Month = RTC_Month_January; + RTC_DateStr.RTC_Year = 18; + RTC_SetDate(RTC_Format_BIN, &RTC_DateStr); + + RTC_TimeStructInit(&RTC_TimeStr); + RTC_TimeStr.RTC_Hours = 0; + RTC_TimeStr.RTC_Minutes = 0; + RTC_TimeStr.RTC_Seconds = 0; + RTC_SetTime(RTC_Format_BIN, &RTC_TimeStr); + +} + +void RTC_Get_Time(void) +{ + RTC_TimeTypeDef time; + RTC_DateTypeDef date; + + RTC_GetTime(RTC_Format_BIN, &time); //get the time + RTC_GetDate(RTC_Format_BIN, &date); //get the date + + clock.cHour = time.RTC_Hours; + clock.cMinute = time.RTC_Minutes; + clock.cSecond = time.RTC_Seconds; + + clock.cYear = date.RTC_Year; + clock.cMonth = date.RTC_Month; + clock.cDay = date.RTC_Date; + clock.cWeek = date.RTC_WeekDay; +} + diff --git a/board/STM8L052R8T6/BSP/src/tim.c b/board/STM8L052R8T6/BSP/src/tim.c new file mode 100644 index 00000000..38081170 --- /dev/null +++ b/board/STM8L052R8T6/BSP/src/tim.c @@ -0,0 +1,24 @@ +#include "stm8l15x.h" +#include "tim.h" + +void Timer2_Init(uint32_t clock, uint32_t tick_per_second) +{ + uint32_t tick_time; + + tick_time = clock / tick_per_second; + + CLK_PeripheralClockConfig(CLK_Peripheral_TIM2, ENABLE); + + TIM2_TimeBaseInit(TIM2_Prescaler_1, TIM2_CounterMode_Up, (uint16_t)tick_time); + + /* Clear TIM2 update flag */ + TIM2_ClearFlag(TIM2_FLAG_Update); + TIM2_ARRPreloadConfig(ENABLE); + + /* Enable update interrupt */ + TIM2_ITConfig(TIM2_IT_Update, ENABLE); + TIM2_Cmd(ENABLE); + + enableInterrupts(); +} + diff --git a/board/STM8L052R8T6/BSP/src/uart.c b/board/STM8L052R8T6/BSP/src/uart.c new file mode 100644 index 00000000..0de5c6b4 --- /dev/null +++ b/board/STM8L052R8T6/BSP/src/uart.c @@ -0,0 +1,115 @@ +#include "stm8l15x.h" +#include "uart.h" + +const uint8_t HEX_TABLE[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +void UART1_Send_Byte(uint8_t ucData) +{ + USART_SendData8(USART1, ucData); + while (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == 0) + ; +} + +//send string +void UART1_Send_String(char *Str) +{ + + while (*Str != '\0') // "\0" meaning is the end of a string + { + UART1_Send_Byte(*Str); + Str++; + } +} + +void UART1_Send_Dec(unsigned int num, unsigned char ucNumCount) +{ + char disp_buffer1[2]; + char disp_buffer2[3]; + char disp_buffer3[4]; + char disp_buffer4[5]; + char disp_buffer5[6]; + char disp_buffer6[7]; + + switch (ucNumCount) + { + case 1: + + disp_buffer1[0] = HEX_TABLE[num % 10]; + disp_buffer1[1] = 0; + + UART1_Send_String(disp_buffer1); + break; + + case 2: + disp_buffer2[0] = HEX_TABLE[(num % 100) / 10]; + disp_buffer2[1] = HEX_TABLE[num % 10]; + disp_buffer2[2] = 0; + UART1_Send_String(disp_buffer2); + break; + case 3: + disp_buffer3[0] = HEX_TABLE[num / 100]; + disp_buffer3[1] = HEX_TABLE[(num % 100) / 10]; + disp_buffer3[2] = HEX_TABLE[num % 10]; + disp_buffer3[3] = 0; + + UART1_Send_String(disp_buffer3); + break; + + case 4: + disp_buffer4[0] = HEX_TABLE[(num % 10000) / 1000]; + disp_buffer4[1] = HEX_TABLE[(num % 1000) / 100]; + disp_buffer4[2] = HEX_TABLE[(num % 100) / 10]; + disp_buffer4[3] = HEX_TABLE[num % 10]; + disp_buffer4[4] = 0; + + UART1_Send_String(disp_buffer4); + break; + + case 5: + + disp_buffer5[0] = HEX_TABLE[(num % 100000) / 10000]; + disp_buffer5[1] = HEX_TABLE[(num % 10000) / 1000]; + disp_buffer5[2] = HEX_TABLE[(num % 1000) / 100]; + disp_buffer5[3] = HEX_TABLE[(num % 100) / 10]; + disp_buffer5[4] = HEX_TABLE[num % 10]; + disp_buffer5[5] = 0; + + UART1_Send_String(disp_buffer5); + break; + + case 6: + + disp_buffer6[0] = HEX_TABLE[num / 100000]; + disp_buffer6[1] = HEX_TABLE[(num % 100000) / 10000]; + disp_buffer6[2] = HEX_TABLE[(num % 10000) / 1000]; + disp_buffer6[3] = HEX_TABLE[(num % 1000) / 100]; + disp_buffer6[4] = HEX_TABLE[(num % 100) / 10]; + disp_buffer6[5] = HEX_TABLE[num % 10]; + disp_buffer6[6] = 0; + + UART1_Send_String(disp_buffer6); + break; + + default: + + break; + } +} + +void UART1_Init(uint32_t uiBaudRate) +{ + //INIT UART1 PINS + GPIO_Init(GPIOC, GPIO_Pin_3, GPIO_Mode_Out_PP_High_Fast); + GPIO_Init(GPIOC, GPIO_Pin_2, GPIO_Mode_In_PU_No_IT); + GPIO_SetBits(GPIOC, GPIO_Pin_3); + + //enable UART1 Clock + CLK_PeripheralClockConfig(CLK_Peripheral_USART1, ENABLE); + + //setting the UART1 + USART_Init(USART1, uiBaudRate, USART_WordLength_8b, USART_StopBits_1, USART_Parity_No, + (USART_Mode_TypeDef)(USART_Mode_Tx | USART_Mode_Rx)); + + //enable UART1 + USART_Cmd(USART1, ENABLE); +} \ No newline at end of file diff --git a/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.cspy.bat b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.cspy.bat new file mode 100644 index 00000000..f4925a4e --- /dev/null +++ b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"D:\Program Files\Embedded Workbench 8.3 STM8\common\bin\cspybat" -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.general.xcl" --backend -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"D:\Program Files\Embedded Workbench 8.3 STM8\common\bin\cspybat" -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.general.xcl" "--debug_file=%~1" --backend -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.cspy.ps1 b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.cspy.ps1 new file mode 100644 index 00000000..3fb24bad --- /dev/null +++ b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "D:\Program Files\Embedded Workbench 8.3 STM8\common\bin\cspybat" -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.general.xcl" --backend -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.driver.xcl" +} +else +{ +& "D:\Program Files\Embedded Workbench 8.3 STM8\common\bin\cspybat" -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.general.xcl" --debug_file=$debugfile --backend -f "D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\settings\stm8_project.Debug.driver.xcl" +} diff --git a/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.driver.xcl b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.driver.xcl new file mode 100644 index 00000000..0d1f84f5 --- /dev/null +++ b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.driver.xcl @@ -0,0 +1,11 @@ +"-p" + +"D:\Program Files\Embedded Workbench 8.3 STM8\stm8\config\ddf\iostm8l052r8.ddf" + +"--mcuname" + +"STM8L052R8" + + + + diff --git a/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.general.xcl b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.general.xcl new file mode 100644 index 00000000..d921706b --- /dev/null +++ b/board/STM8L052R8T6/IAR/hello_world/settings/stm8_project.Debug.general.xcl @@ -0,0 +1,11 @@ +"D:\Program Files\Embedded Workbench 8.3 STM8\stm8\bin\stm8proc.dll" + +"D:\Program Files\Embedded Workbench 8.3 STM8\stm8\bin\stm8stlink.dll" + +"D:\TOS\TencentOS-tiny\board\STM8L052R8T6\IAR\hello_world\Debug\Exe\stm8_project.out" + +--plugin="D:\Program Files\Embedded Workbench 8.3 STM8\stm8\bin\stm8bat.dll" + + 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$PROJ_DIR$\..\..\..\..\kernel\core\tos_mmheap.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_mutex.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_pend.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_priority_mail_queue.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_priority_message_queue.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_priority_queue.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_ring_queue.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_robin.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_sched.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_sem.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_sys.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_task.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_tick.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_time.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_timer.c + + + + lib + + inc + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_adc.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_aes.h + + + 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$PROJ_DIR$\..\..\LIB\src\stm8l15x_rst.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_rtc.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_spi.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_syscfg.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim1.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim2.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim3.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim4.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim5.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_usart.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_wfe.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_wwdg.c + + + + + TOS-CONFIG + + $PROJ_DIR$\..\..\TOS-CONFIG\tos_config.h + + + + user + + $PROJ_DIR$\..\..\USER\main.c + + + $PROJ_DIR$\..\..\USER\stm8l15x_it.c + + + diff --git a/board/STM8L052R8T6/IAR/hello_world/stm8_project.ewt b/board/STM8L052R8T6/IAR/hello_world/stm8_project.ewt new file mode 100644 index 00000000..90ff2051 --- /dev/null +++ b/board/STM8L052R8T6/IAR/hello_world/stm8_project.ewt @@ -0,0 +1,2463 @@ + + + 3 + + Debug + + STM8 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$PROJ_DIR$\..\..\..\..\kernel\core\tos_sys.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_task.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_tick.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_time.c + + + $PROJ_DIR$\..\..\..\..\kernel\core\tos_timer.c + + + + lib + + inc + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_adc.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_aes.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_beep.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_clk.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_comp.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_dac.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_dma.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_exti.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_flash.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_gpio.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_i2c.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_irtim.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_itc.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_iwdg.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_lcd.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_pwr.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_rst.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_rtc.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_spi.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_syscfg.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_tim1.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_tim2.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_tim3.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_tim4.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_tim5.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_usart.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_wfe.h + + + $PROJ_DIR$\..\..\LIB\inc\stm8l15x_wwdg.h + + + + src + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_adc.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_aes.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_beep.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_clk.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_comp.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_dac.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_dma.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_exti.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_flash.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_gpio.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_i2c.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_irtim.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_itc.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_iwdg.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_lcd.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_pwr.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_rst.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_rtc.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_spi.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_syscfg.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim1.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim2.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim3.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim4.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_tim5.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_usart.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_wfe.c + + + $PROJ_DIR$\..\..\LIB\src\stm8l15x_wwdg.c + + + + + TOS-CONFIG + + $PROJ_DIR$\..\..\TOS-CONFIG\tos_config.h + + + + user + + $PROJ_DIR$\..\..\USER\main.c + + + $PROJ_DIR$\..\..\USER\stm8l15x_it.c + + + diff --git a/board/STM8L052R8T6/IAR/hello_world/stm8_project.eww b/board/STM8L052R8T6/IAR/hello_world/stm8_project.eww new file mode 100644 index 00000000..25d51551 --- /dev/null +++ b/board/STM8L052R8T6/IAR/hello_world/stm8_project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\stm8_project.ewp + + + diff --git a/board/STM8L052R8T6/LIB/inc/stm8l15x.h b/board/STM8L052R8T6/LIB/inc/stm8l15x.h new file mode 100644 index 00000000..0a2f5beb --- /dev/null +++ b/board/STM8L052R8T6/LIB/inc/stm8l15x.h @@ -0,0 +1,3030 @@ +/** + ****************************************************************************** + * @file stm8l15x.h + * @author MCD Application Team + * @version V1.6.1 + * @date 30-September-2014 + * @brief This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM8L15x devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8L15x_H + #define __STM8L15x_H + +/** @addtogroup STM8L15x_StdPeriph_Driver + * @{ + */ +/* Uncomment the line below according to the target STM8L15x device used in your + application + */ +/* #define STM8L15X_LD */ /*!< STM8L15X_LD: STM8L15x Low density devices */ +/* #define STM8L15X_MD */ /*!< STM8L15X_MD: STM8L15x Medium density devices */ +/* #define STM8L15X_MDP */ /*!< STM8L15X_MDP: STM8L15x Medium density plus devices */ +/* #define STM8L15X_HD */ /*!< STM8L15X_HD: STM8L15x/16x High density devices */ +/* #define STM8L05X_LD_VL */ /*!< STM8L05X_LD_VL: STM8L051xx3 Low density value line devices */ +/* #define STM8L05X_MD_VL */ /*!< STM8L05X_MD_VL: STM8L052xx6 Medium density value line devices */ +/* #define STM8L05X_HD_VL */ /*!< STM8L05X_HD_VL: STM8L052xx8 High density value line devices */ +/* #define STM8AL31_L_MD */ /*!< STM8AL31_L_MD: STM8AL3x Medium density devices */ + + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low density STM8L15x devices are STM8L151C3, STM8L151K3, STM8L151G3, STM8L151F3, + STM8L151C2, STM8L151K2, STM8L151G2 and STM8L151F2 microcontrollers where the + Flash memory density ranges between 4 and 8 Kbytes. + - Medium density STM8L15x devices are STM8L151C4, STM8L151C6, STM8L152C4, + STM8L152C6, STM8L151K4, STM8L151K6, STM8L152K4, STM8L152K6, STM8L151G4, + STM8L151G6, STM8L152G4 and STM8L152G6 microcontrollers where the Flash memory + density ranges between 16 and 32 Kbytes. + - Medium density Plus devices are STM8L151R6, STM8L152R6 microcontrollers where + the Flash memory density is fixed and equal to 32 Kbytes and a wider range of + peripheral than the medium density devices. + - High density STM8L15x devices are STM8L151x8, STM8L152x8, STM8L162R8 and STM8L162M8 + microcontrollers where the Flash memory density is fixed and equal to 64 Kbytes with + the same peripheral set than Medium Density Plus devices. + - Value line low density STM8L05xx devices are STM8L051x3 microcontrollers + with 8-KB Flash + - Value line medium density STM8L05xx devices are STM8L052x6 microcontrollers + with 32-KB Flash + - Value line high density STM8L05xx devices: STM8L052x8 microcontrollers + with 64-KB Flash + - Medium density STM8AL31xx/STM8AL3Lxx devices: STM8AL3168, STM8AL3166, + STM8AL3148,STM8AL3146, STM8AL3138, STM8AL3136, STM8AL3L68, STM8AL3L66, + STM8AL3L48, STM8AL3L46 microcontrollers with 8-KB, 16-KB or 32-KB Flash + */ + +#if !defined (STM8L15X_MD) && !defined (STM8L15X_MDP) && !defined (STM8L15X_HD) && !defined (STM8L15X_LD) \ +&& !defined (STM8L05X_LD_VL) && !defined (STM8L05X_MD_VL) && !defined (STM8L05X_HD_VL) && !defined (STM8AL31_L_MD) + #error "Please select first the target STM8L device used in your application (in stm8l15x.h file)" +#endif + +/******************************************************************************/ +/* Library configuration section */ +/******************************************************************************/ +/* Check the used compiler */ +#if defined(__CSMC__) + #define _COSMIC_ +#elif defined(__RCSTM8__) + #define _RAISONANCE_ +#elif defined(__ICCSTM8__) + #define _IAR_ +#else + #error "Unsupported Compiler!" /* Compiler defines not found */ +#endif + +#if !defined USE_STDPERIPH_DRIVER +/* Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will be + based on direct access to peripherals registers */ + #define USE_STDPERIPH_DRIVER +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #define HSE_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSE in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief Definition of External Low Speed oscillator (LSE) frequency + */ +#if !defined LSE_VALUE + #define LSE_VALUE ((uint32_t)32768) /*!< Typical Value of the LSE in Hz */ +#endif /* LSE_VALUE */ +/** + * @brief Definition of Device on-chip RC oscillator frequencies + */ +#if !defined HSI_VALUE + #define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ +#endif /* HSI_VALUE */ + +#if !defined LSI_VALUE + #define LSI_VALUE ((uint32_t)38000) /*!< Typical Value of the LSI in Hz */ +#endif /* LSI_VALUE */ + +#ifdef _COSMIC_ + #define FAR @far + #define NEAR @near + #define TINY @tiny + #define EEPROM @eeprom + #define CONST const +#elif defined (_RAISONANCE_) /* __RCSTM8__ */ + #define FAR far + #define NEAR data + #define TINY page0 + #define EEPROM eeprom + #define CONST code + #if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L05X_MD_VL) || \ + defined (STM8AL31_L_MD) + /*!< Used with memory Models for code less than 64K */ + #define MEMCPY memcpy + #elif defined (STM8L15X_HD) || defined (STM8L05X_HD_VL) + /*!< Used with memory Models for code higher than 64K */ + #define MEMCPY fmemcpy + #endif /* STM8L15X_MD or STM8L15X_MDP or STM8L05X_MD_VL or STM8AL31_L_MD*/ +#else /*_IAR_*/ + #define FAR __far + #define NEAR __near + #define TINY __tiny + #define EEPROM __eeprom + #define CONST const +#endif /* __CSMC__ */ + +/** + * @brief Legacy definition + */ +#define __CONST CONST + +#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) || \ +defined (STM8L05X_LD_VL) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD) +/*!< Used with memory Models for code smaller than 64K */ + #define PointerAttr NEAR + #define MemoryAddressCast uint16_t +#elif defined (STM8L15X_HD) || defined (STM8L05X_HD_VL) +/*!< Used with memory Models for code higher than 64K */ + #define PointerAttr FAR + #define MemoryAddressCast uint32_t +#endif /* STM8L15X_MD or STM8L15X_MDP or STM8L15X_LD or STM8L05X_LD_VL or STM8L05X_MD_VL + or STM8AL31_L_MD */ + +/* Uncomment the line below to enable the FLASH functions execution from RAM */ +#if !defined (RAM_EXECUTION) +/* #define RAM_EXECUTION (1) */ +#endif /* RAM_EXECUTION */ + +#ifdef RAM_EXECUTION + #ifdef _COSMIC_ + #define IN_RAM(a) a + #elif defined (_RAISONANCE_) /* __RCSTM8__ */ + #define IN_RAM(a) a inram + #else /*_IAR_*/ + #define IN_RAM(a) __ramfunc a + #endif /* _COSMIC_ */ +#else + #define IN_RAM(a) a +#endif /* RAM_EXECUTION */ + +/*!< [31:16] STM8L15X Standard Peripheral Library main version */ +#define __STM8L15X_STDPERIPH_VERSION_MAIN ((uint8_t)0x01) /*!< [31:24] main version */ +#define __STM8L15X_STDPERIPH_VERSION_SUB1 ((uint8_t)0x06) /*!< [23:16] sub1 version */ +#define __STM8L15X_STDPERIPH_VERSION_SUB2 ((uint8_t)0x01) /*!< [15:8] sub2 version */ +#define __STM8L15X_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ +#define __STM8L15X_STDPERIPH_VERSION ( (__STM8L15X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM8L15X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM8L15X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM8L15X_STDPERIPH_VERSION_RC)) + +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types and constants ----------------------------------------------*/ + +/** @addtogroup Exported_types + * @{ + */ + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*!< Signed integer types */ +#include "stdint.h" +#if 0 +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed long int32_t; + +/*!< Unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; +#endif + +/*!< STM8Lx Standard Peripheral Library old types (maintained for legacy purpose) */ + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX (255) +#define S8_MAX (127) +#define S8_MIN (-128) +#define U16_MAX (65535u) +#define S16_MAX (32767) +#define S16_MIN (-32768) +#define U32_MAX (4294967295uL) +#define S32_MAX (2147483647) +#define S32_MIN (-2147483648uL) + +/** + * @} + */ + +/** @addtogroup MAP_FILE_Exported_Types_and_Constants + * @{ + */ + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*----------------------------------------------------------------------------*/ +/** + * @brief General Purpose I/Os (GPIO) + */ +typedef struct GPIO_struct +{ + __IO uint8_t ODR; /*!< Output Data Register */ + __IO uint8_t IDR; /*!< Input Data Register */ + __IO uint8_t DDR; /*!< Data Direction Register */ + __IO uint8_t CR1; /*!< Configuration Register 1 */ + __IO uint8_t CR2; /*!< Configuration Register 2 */ +} +GPIO_TypeDef; + +/** @addtogroup GPIO_Registers_Reset_Value + * @{ + */ +#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) +/** + * @} + */ +/*----------------------------------------------------------------------------*/ + +/** + * @brief Real-Time Clock (RTC) peripheral registers. + */ +typedef struct RTC_struct +{ + __IO uint8_t TR1; /*!< Time Register 1*/ + __IO uint8_t TR2; /*!< Time Register 2*/ + __IO uint8_t TR3; /*!< Time Register 3*/ + + uint8_t RESERVED0; + + __IO uint8_t DR1; /*!< Date Register 1*/ + __IO uint8_t DR2; /*!< Date Register 2*/ + __IO uint8_t DR3; /*!< Date Register 3*/ + + uint8_t RESERVED1; + + __IO uint8_t CR1; /*!< Control Register 1*/ + __IO uint8_t CR2; /*!< Control Register 2*/ + __IO uint8_t CR3; /*!< Control Register 3*/ + + uint8_t RESERVED2; + + __IO uint8_t ISR1; /*!< Initialisation and Status Register 1 */ + __IO uint8_t ISR2; /*!< Initialisation and Status Register 2 */ + + uint8_t RESERVED3; + uint8_t RESERVED4; + + __IO uint8_t SPRERH; /*!< Synchronous Prediv high Register */ + __IO uint8_t SPRERL; /*!< Synchronous Prediv Low Register */ + __IO uint8_t APRER; /*!< Asynchronous Prediv Register */ + + uint8_t RESERVED5; + + __IO uint8_t WUTRH; /*!< Wake-Up Timer High Register */ + __IO uint8_t WUTRL; /*!< Wake-Up Timer Low Register */ + + uint8_t RESERVED6; + + __IO uint8_t SSRH; /*!< Sub Second High Register */ + __IO uint8_t SSRL; /*!< Sub Second Low Register */ + + __IO uint8_t WPR; /*!< Write Protection Register */ + + __IO uint8_t SHIFTRH; /*!< Shift control High Register */ + __IO uint8_t SHIFTRL; /*!< Shift control Low Register */ + + __IO uint8_t ALRMAR1; /*!< ALARM A Register 1 */ + __IO uint8_t ALRMAR2; /*!< ALARM A Register 2 */ + __IO uint8_t ALRMAR3; /*!< ALARM A Register 3 */ + __IO uint8_t ALRMAR4; /*!< ALARM A Register 4 */ + + uint8_t RESERVED7[4]; + + __IO uint8_t ALRMASSRH; /*!< ALARM A Subsecond Register High */ + __IO uint8_t ALRMASSRL; /*!< ALARM A Subsecond Register Low */ + __IO uint8_t ALRMASSMSKR; /*!< ALARM A Subsecond Mask Register */ + + uint8_t RESERVED8[3]; + + __IO uint8_t CALRH; /*!< Calibration register high */ + __IO uint8_t CALRL; /*!< Calibration register low */ + + __IO uint8_t TCR1; /*!< Tamper control register 1 */ + __IO uint8_t TCR2; /*!< Tamper control register 2 */ +} +RTC_TypeDef; + +/** @addtogroup RTC_Registers_Reset_Value + * @{ + */ +#define RTC_TR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_TR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_TR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_DR1_RESET_VALUE ((uint8_t)0x01) +#define RTC_DR2_RESET_VALUE ((uint8_t)0x21) +#define RTC_DR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_CR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_CR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_CR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ISR1_RESET_VALUE ((uint8_t)0x07) +#define RTC_ISR2_RESET_VALUE ((uint8_t)0x00) + +#define RTC_SPRERH_RESET_VALUE ((uint8_t)0x00) +#define RTC_SPRERL_RESET_VALUE ((uint8_t)0xFF) +#define RTC_APRER_RESET_VALUE ((uint8_t)0x7F) + +#define RTC_WUTRH_RESET_VALUE ((uint8_t)0xFF) +#define RTC_WUTRL_RESET_VALUE ((uint8_t)0xFF) + +#define RTC_WPR_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ALRMAR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR3_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR4_RESET_VALUE ((uint8_t)0x00) + +#define RTC_SHIFTRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_SHIFTRL_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ALRMASSRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMASSRL_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMASSMSKR_RESET_VALUE ((uint8_t)0x00) + +#define RTC_CALRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_CALRL_RESET_VALUE ((uint8_t)0x00) + +#define RTC_TCR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_TCR2_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup RTC_Registers_Bits_Definition + * @{ + */ + +/* Bits definition for RTC_TR1 register*/ +#define RTC_TR1_ST ((uint8_t)0x70) +#define RTC_TR1_SU ((uint8_t)0x0F) + +/* Bits definition for RTC_TR2 register*/ +#define RTC_TR2_MNT ((uint8_t)0x70) +#define RTC_TR2_MNU ((uint8_t)0x0F) + +/* Bits definition for RTC_TR3 register*/ +#define RTC_TR3_PM ((uint8_t)0x40) +#define RTC_TR3_HT ((uint8_t)0x30) +#define RTC_TR3_HU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR1 register*/ +#define RTC_DR1_DT ((uint8_t)0x30) +#define RTC_DR1_DU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR2 register*/ +#define RTC_DR2_WDU ((uint8_t)0xE0) +#define RTC_DR2_MT ((uint8_t)0x10) +#define RTC_DR2_MU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR3 register*/ +#define RTC_DR3_YT ((uint8_t)0xF0) +#define RTC_DR3_YU ((uint8_t)0x0F) + +/* Bits definition for RTC_CR1 register*/ +#define RTC_CR1_FMT ((uint8_t)0x40) +#define RTC_CR1_RATIO ((uint8_t)0x20) +#define RTC_CR1_WUCKSEL ((uint8_t)0x07) +#define RTC_CR1_BYPSHAD ((uint8_t)0x10) + + +/* Bits definition for RTC_CR2 register*/ +#define RTC_CR2_WUTIE ((uint8_t)0x40) +#define RTC_CR2_ALRAIE ((uint8_t)0x10) +#define RTC_CR2_WUTE ((uint8_t)0x04) +#define RTC_CR2_ALRAE ((uint8_t)0x01) +#define RTC_CR2_ALRIE ((uint8_t)0x20) + + + +/* Bits definition for RTC_CR3 register*/ +#define RTC_CR3_COE ((uint8_t)0x80) +#define RTC_CR3_OSEL ((uint8_t)0x60) +#define RTC_CR3_POL ((uint8_t)0x10) +#define RTC_CR3_COSEL ((uint8_t)0x08) +#define RTC_CR3_BCK ((uint8_t)0x04) +#define RTC_CR3_SUB1H ((uint8_t)0x02) +#define RTC_CR3_ADD1H ((uint8_t)0x01) + + +/* Bits definition for RTC_ISR1 register*/ +#define RTC_ISR1_INIT ((uint8_t)0x80) +#define RTC_ISR1_INITF ((uint8_t)0x40) +#define RTC_ISR1_RSF ((uint8_t)0x20) +#define RTC_ISR1_INITS ((uint8_t)0x10) +#define RTC_ISR1_SHPF ((uint8_t)0x08) +#define RTC_ISR1_WUTWF ((uint8_t)0x04) +#define RTC_ISR1_RECALPF ((uint8_t)0x02) +#define RTC_ISR1_ALRAWF ((uint8_t)0x01) + + +/* Bits definition for RTC_ISR2 register*/ +#define RTC_ISR2_WUTF ((uint8_t)0x04) +#define RTC_ISR2_ALRAF ((uint8_t)0x01) +#define RTC_ISR2_TAMP3F ((uint8_t)0x80) +#define RTC_ISR2_TAMP2F ((uint8_t)0x40) +#define RTC_ISR2_TAMP1F ((uint8_t)0x20) + +/* Bits definition for RTC_SHIFTRH register*/ +#define RTC_SHIFTRH_ADD1S ((uint8_t)0x80) +#define RTC_SHIFTRH_SUBFS ((uint8_t)0x7F) + +/* Bits definition for RTC_SHIFTRL register*/ +#define RTC_SHIFTRL_SUBFS ((uint8_t)0xFF) + + +/* Bits definition for RTC_ALRMAR1 register*/ +#define RTC_ALRMAR1_MSK1 ((uint8_t)0x80) +#define RTC_ALRMAR1_ST ((uint8_t)0x70) +#define RTC_ALRMAR1_SU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR2 register*/ +#define RTC_ALRMAR2_MSK2 ((uint8_t)0x80) +#define RTC_ALRMAR2_MNT ((uint8_t)0x70) +#define RTC_ALRMAR2_MNU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR3 register*/ +#define RTC_ALRMAR3_MSK3 ((uint8_t)0x80) +#define RTC_ALRMAR3_PM ((uint8_t)0x40) +#define RTC_ALRMAR3_HT ((uint8_t)0x30) +#define RTC_ALRMAR3_HU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR4 register*/ +#define RTC_ALRMAR4_MSK4 ((uint8_t)0x80) +#define RTC_ALRMAR4_WDSEL ((uint8_t)0x40) +#define RTC_ALRMAR4_DT ((uint8_t)0x30) +#define RTC_ALRMAR4_DU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMASSRH register*/ +#define RTC_ALRMASSRH_ALSS ((uint8_t)0x7F) + +/* Bits definition for RTC_ALRMASSRL register*/ +#define RTC_ALRMASSRL_ALSS ((uint8_t)0xFF) + +/* Bits definition for RTC_ALRMASSMSKR register*/ +#define RTC_ALRMASSMSKR_MASKSS ((uint8_t)0x1F) + + +/* Bits definition for RTC_CALRH register*/ +#define RTC_CALRH_CALP ((uint8_t)0x80) +#define RTC_CALRH_CALW8 ((uint8_t)0x40) +#define RTC_CALRH_CALW16 ((uint8_t)0x20) +#define RTC_CALRH_CALWx ((uint8_t)0x60) +#define RTC_CALRH_CALM ((uint8_t)0x01) + +/* Bits definition for RTC_CALRL register*/ +#define RTC_CALRL_CALM ((uint8_t)0xFF) + +/* Bits definition for RTC_TCR1 register*/ +#define RTC_TCR1_TAMP3LEVEL ((uint8_t)0x40) +#define RTC_TCR1_TAMP3E ((uint8_t)0x20) +#define RTC_TCR1_TAMP2LEVEL ((uint8_t)0x10) +#define RTC_TCR1_TAMP2E ((uint8_t)0x08) +#define RTC_TCR1_TAMP1LEVEL ((uint8_t)0x04) +#define RTC_TCR1_TAMP1E ((uint8_t)0x02) +#define RTC_TCR1_TAMPIE ((uint8_t)0x01) + +/* Bits definition for RTC_TCR2 register*/ +#define RTC_TCR2_TAMPPUDIS ((uint8_t)0x80) +#define RTC_TCR2_TAMPPRCH ((uint8_t)0x60) +#define RTC_TCR2_TAMPFLT ((uint8_t)0x18) +#define RTC_TCR2_TAMPFREQ ((uint8_t)0x07) + + +/*RTC special defines */ +#define RTC_WPR_EnableKey ((uint8_t)0xFF) +#define RTC_WPR_DisableKey1 ((uint8_t)0xCA) +#define RTC_WPR_DisableKey2 ((uint8_t)0x53) + +/** + * @} + */ + +/** + * @brief CSS on LSE registers. + */ +typedef struct CSSLSE_struct +{ + __IO uint8_t CSR; /*!< Control and Status Register*/ +} +CSSLSE_TypeDef; + +/** @addtogroup CSSLSE_Registers_Reset_Value + * @{ + */ +#define CSSLSE_CSR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup CSSLSE_Registers_Bits_Definition + * @{ + */ + +/* Bits definition for CSSLSE_CSR register*/ +#define CSSLSE_CSR_SWITCHF ((uint8_t)0x10) +#define CSSLSE_CSR_CSSF ((uint8_t)0x08) +#define CSSLSE_CSR_CSSIE ((uint8_t)0x04) +#define CSSLSE_CSR_SWITCHEN ((uint8_t)0x02) +#define CSSLSE_CSR_CSSEN ((uint8_t)0x01) + +/** + * @} + */ +/*----------------------------------------------------------------------------*/ +/** + * @brief Beeper (BEEP) peripheral registers. + */ + +typedef struct BEEP_struct +{ + __IO uint8_t CSR1; /*!< BEEP Control status register1 */ + uint8_t RSERVED1; + uint8_t RESERVED2; + __IO uint8_t CSR2; /*!< BEEP Control status register2 */ +} +BEEP_TypeDef; + +/** @addtogroup BEEP_Registers_Reset_Value + * @{ + */ +#define BEEP_CSR1_RESET_VALUE ((uint8_t)0x00) +#define BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup BEEP_Registers_Bits_Definition + * @{ + */ + +#define BEEP_CSR1_MSR ((uint8_t)0x01) /*!< Measurement enable mask */ + +#define BEEP_CSR2_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ +#define BEEP_CSR2_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ +#define BEEP_CSR2_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Configuration Registers (CFG) + */ + +typedef struct CFG_struct +{ + __IO uint8_t GCR; /*!< Global Configuration register */ +} +CFG_TypeDef; + +/** @addtogroup CFG_Registers_Reset_Value + * @{ + */ + +#define CFG_GCR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup CFG_Registers_Bits_Definition + * @{ + */ + +#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */ +#define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief SYSCFG + */ + +typedef struct SYSCFG_struct +{ + __IO uint8_t RMPCR3; /*!< Remap control register 3 */ + __IO uint8_t RMPCR1; /*!< Remap control register 1 */ + __IO uint8_t RMPCR2; /*!< Remap control register 2 */ +} +SYSCFG_TypeDef; + +/** @addtogroup SYSCFG_Registers_Reset_Value + * @{ + */ +#define SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C) +#define SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00) +#define SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup SYSCFG_Registers_Bits_Definition + * @{ + */ + +/* For DMA Channel Mapping*/ +#define SYSCFG_RMPCR1_ADC1DMA_REMAP ((uint8_t)0x03) /*!< ADC1 DMA channel remapping */ +#define SYSCFG_RMPCR1_TIM4DMA_REMAP ((uint8_t)0x0C) /*!< TIM4 DMA channel remapping */ + + +/* For GPIO Reapping*/ +#define SYSCFG_RMPCR1_USART1TR_REMAP ((uint8_t)0x30) /*!< USART1_TX and USART1_RX remapping */ +#define SYSCFG_RMPCR1_USART1CK_REMAP ((uint8_t)0x40) /*!< USART1_CK remapping */ +#define SYSCFG_RMPCR1_SPI1_REMAP ((uint8_t)0x80) /*!< SPI1 remapping */ + +#define SYSCFG_RMPCR2_ADC1TRIG_REMAP ((uint8_t)0x01) /*!< ADC1 External Trigger remap */ +#define SYSCFG_RMPCR2_TIM2TRIG_REMAP ((uint8_t)0x02) /*!< TIM2 Trigger remap */ +#define SYSCFG_RMPCR2_TIM3TRIG_REMAP1 ((uint8_t)0x04) /*!< TIM3 Trigger remap 1 */ +#define SYSCFG_RMPCR2_TIM2TRIG_LSE ((uint8_t)0x08) /*!< TIM2 Trigger remap to LSE */ +#define SYSCFG_RMPCR2_TIM3TRIG_LSE ((uint8_t)0x10) /*!< TIM3 Trigger remap to LSE */ +#define SYSCFG_RMPCR2_SPI2_REMAP ((uint8_t)0x20) /*!< SPI2 remapping */ +#define SYSCFG_RMPCR2_TIM3TRIG_REMAP2 ((uint8_t)0x40) /*!< TIM3 Trigger remap 2 */ +#define SYSCFG_RMPCR2_TIM23BKIN_REMAP ((uint8_t)0x80) /*!< TIM2 & TIM3 Break input remap */ + +#define SYSCFG_RMPCR3_SPI1_REMAP ((uint8_t)0x01) /*!< SPI1 remapping */ +#define SYSCFG_RMPCR3_USART3TR_REMAP ((uint8_t)0x02) /*!< USART3_TX and USART3_RX remapping */ +#define SYSCFG_RMPCR3_USART3CK_REMAP ((uint8_t)0x04) /*!< USART3_CK remapping */ +#define SYSCFG_RMPCR3_TIM3CH1_REMAP ((uint8_t)0x08) /*!< TIM3 channel 1 remapping */ +#define SYSCFG_RMPCR3_TIM3CH2_REMAP ((uint8_t)0x10) /*!< TIM3 channel 2 remapping */ +#define SYSCFG_RMPCR3_CCO_REMAP ((uint8_t)0x20) /*!< CCO remapping */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Clock Controller (CLK) + */ +typedef struct CLK_struct +{ + __IO uint8_t CKDIVR; /*!< Clock Master Divider Register */ + __IO uint8_t CRTCR; /*!< RTC Clock selection Register */ + __IO uint8_t ICKCR; /*!< Internal Clocks Control Register */ + __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ + __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ + __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ + __IO uint8_t ECKCR; /*!< External Clocks Control Register */ + __IO uint8_t SCSR; /*!< System clock status Register */ + __IO uint8_t SWR; /*!< System clock Switch Register */ + __IO uint8_t SWCR; /*!< Switch Control Register */ + __IO uint8_t CSSR; /*!< Clock Security Sytem Register */ + __IO uint8_t CBEEPR; /*!< Clock BEEP Register */ + __IO uint8_t HSICALR; /*!< HSI Calibration Register */ + __IO uint8_t HSITRIMR; /*!< HSI clock Calibration Trimmer Register */ + __IO uint8_t HSIUNLCKR; /*!< HSI Unlock Register */ + __IO uint8_t REGCSR; /*!< Main regulator control status register */ + __IO uint8_t PCKENR3; /*!< Peripheral Clock Gating Register 3 */ +} +CLK_TypeDef; + +/** @addtogroup CLK_Registers_Reset_Value + * @{ + */ +#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x03) +#define CLK_CRTCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_ICKCR_RESET_VALUE ((uint8_t)0x11) +#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0x00) +#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0x80) +#define CLK_PCKENR3_RESET_VALUE ((uint8_t)0x00) +#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) +#define CLK_ECKCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_SCSR_RESET_VALUE ((uint8_t)0x01) +#define CLK_SWR_RESET_VALUE ((uint8_t)0x01) +#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CBEEPR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSICALR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00) +#define CLK_REGCSR_RESET_VALUE ((uint8_t)0xB9) +/** + * @} + */ + +/** @addtogroup CLK_Registers_Bits_Definition + * @{ + */ + +#define CLK_CKDIVR_CKM ((uint8_t)0x07) /*!< System clock prescaler mask */ + +#define CLK_CRTCR_RTCDIV ((uint8_t)0xE0) /*!< RTC clock prescaler mask*/ +#define CLK_CRTCR_RTCSEL ((uint8_t)0x1E) /*!< RTC clock output selection mask */ +#define CLK_CRTCR_RTCSWBSY ((uint8_t)0x01) /*!< RTC clock switch busy */ + +#define CLK_ICKCR_BEEPAHALT ((uint8_t)0x40) /*!< BEEP clock Active Halt/Halt mode */ +#define CLK_ICKCR_FHWU ((uint8_t)0x20) /*!< Fast Wake-up from Active Halt/Halt mode */ +#define CLK_ICKCR_SAHALT ((uint8_t)0x10) /*!< Slow Active-halt mode */ +#define CLK_ICKCR_LSIRDY ((uint8_t)0x08) /*!< Low speed internal RC oscillator ready */ +#define CLK_ICKCR_LSION ((uint8_t)0x04) /*!< Low speed internal RC oscillator enable */ +#define CLK_ICKCR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ +#define CLK_ICKCR_HSION ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ + +#define CLK_PCKENR1_TIM2 ((uint8_t)0x01) /*!< Timer 2 clock enable */ +#define CLK_PCKENR1_TIM3 ((uint8_t)0x02) /*!< Timer 3 clock enable */ +#define CLK_PCKENR1_TIM4 ((uint8_t)0x04) /*!< Timer 4 clock enable */ +#define CLK_PCKENR1_I2C1 ((uint8_t)0x08) /*!< I2C1 clock enable */ +#define CLK_PCKENR1_SPI1 ((uint8_t)0x10) /*!< SPI1 clock enable */ +#define CLK_PCKENR1_USART1 ((uint8_t)0x20) /*!< USART1 clock enable */ +#define CLK_PCKENR1_BEEP ((uint8_t)0x40) /*!< BEEP clock enable */ +#define CLK_PCKENR1_DAC ((uint8_t)0x80) /*!< DAC clock enable */ + +#define CLK_PCKENR2_ADC1 ((uint8_t)0x01) /*!< ADC1 clock enable */ +#define CLK_PCKENR2_TIM1 ((uint8_t)0x02) /*!< TIM1 clock enable */ +#define CLK_PCKENR2_RTC ((uint8_t)0x04) /*!< RTC clock enable */ +#define CLK_PCKENR2_LCD ((uint8_t)0x08) /*!< LCD clock enable */ +#define CLK_PCKENR2_DMA1 ((uint8_t)0x10) /*!< DMA1 clock enable */ +#define CLK_PCKENR2_COMP ((uint8_t)0x20) /*!< Comparator clock enable */ +#define CLK_PCKENR2_BOOTROM ((uint8_t)0x80) /*!< Boot ROM clock enable */ + +#define CLK_PCKENR3_AES ((uint8_t)0x01) /*!< AES clock enable */ +#define CLK_PCKENR3_TIM5 ((uint8_t)0x02) /*!< Timer 5 clock enable */ +#define CLK_PCKENR3_SPI2 ((uint8_t)0x04) /*!< SPI2 clock enable */ +#define CLK_PCKENR3_UASRT2 ((uint8_t)0x08) /*!< USART2 clock enable */ +#define CLK_PCKENR3_USART3 ((uint8_t)0x10) /*!< USART3 clock enable */ + +#define CLK_CCOR_CCODIV ((uint8_t)0xE0) /*!< Configurable Clock output prescaler */ +#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ +#define CLK_CCOR_CCOSWBSY ((uint8_t)0x01) /*!< Configurable clock output switch busy flag */ + +#define CLK_ECKCR_LSEBYP ((uint8_t)0x20) /*!< Low speed external clock bypass */ +#define CLK_ECKCR_HSEBYP ((uint8_t)0x10) /*!< High speed external clock bypass */ +#define CLK_ECKCR_LSERDY ((uint8_t)0x08) /*!< Low speed external crystal oscillator ready */ +#define CLK_ECKCR_LSEON ((uint8_t)0x04) /*!< Low speed external crystal oscillator enable */ +#define CLK_ECKCR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ +#define CLK_ECKCR_HSEON ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ + +#define CLK_SCSR_CKM ((uint8_t)0x0F) /*!< System clock status bits */ + +#define CLK_SWR_SWI ((uint8_t)0x0F) /*!< System clock selection bits */ + +#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ +#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ +#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ +#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy */ + +#define CLK_CSSR_CSSDGON ((uint8_t)0x10) /*!< Clock security sytem deglitcher system */ +#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security sytem detection */ +#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ +#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ +#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ + +#define CLK_CBEEPR_CLKBEEPSEL ((uint8_t)0x06) /*!< Configurable BEEP clock source selection */ +#define CLK_CBEEPR_BEEPSWBSY ((uint8_t)0x01) /*!< BEEP clock busy in switch */ + +#define CLK_HSICALR_HSICAL ((uint8_t)0xFF) /*!< Copy of otpion byte trimming HSI oscillator */ + +#define CLK_HSITRIMR_HSITRIM ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer */ + +#define CLK_HSIUNLCKR_HSIUNLCK ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer unlock */ + +#define CLK_REGCSR_EEREADY ((uint8_t)0x80) /*!< Flash program memory and Data EEPROM ready */ +#define CLK_REGCSR_EEBUSY ((uint8_t)0x40) /*!< Flash program memory and Data EEPROM busy */ +#define CLK_REGCSR_LSEPD ((uint8_t)0x20) /*!< LSE power-down */ +#define CLK_REGCSR_HSEPD ((uint8_t)0x10) /*!< HSE power-down */ +#define CLK_REGCSR_LSIPD ((uint8_t)0x08) /*!< LSI power-down */ +#define CLK_REGCSR_HSIPD ((uint8_t)0x04) /*!< HSI power-down */ +#define CLK_REGCSR_REGOFF ((uint8_t)0x02) /*!< Main regulator OFF */ +#define CLK_REGCSR_REGREADY ((uint8_t)0x01) /*!< Main regulator ready */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Comparator interface (COMP) + */ + +typedef struct COMP_struct +{ + __IO uint8_t CSR1; /*!< Control status register 1 */ + __IO uint8_t CSR2; /*!< Control status register 2 */ + __IO uint8_t CSR3; /*!< Control status register 3 */ + __IO uint8_t CSR4; /*!< Control status register 4 */ + __IO uint8_t CSR5; /*!< Control status register 5 */ +} +COMP_TypeDef; + + +/** @addtogroup COMP_Registers_Reset_Value + * @{ + */ +#define COMP_CSR1_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR2_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR3_RESET_VALUE ((uint8_t)0xC0) +#define COMP_CSR4_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR5_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup COMP_Registers_Bits_Definition + * @{ + */ + +/* CSR1 */ +#define COMP_CSR1_IE1 ((uint8_t)0x20) /*!< Comparator 1 Interrupt Enable Mask. */ +#define COMP_CSR1_EF1 ((uint8_t)0x10) /*!< Comparator 1 Event Flag Mask. */ +#define COMP_CSR1_CMP1OUT ((uint8_t)0x08) /*!< Comparator 1 Ouptput Mask. */ +#define COMP_CSR1_STE ((uint8_t)0x04) /*!< Schmitt trigger enable Mask. */ +#define COMP_CSR1_CMP1 ((uint8_t)0x03) /*!< Comparator 1 Configuration Mask. */ + +/* CSR2 */ +#define COMP_CSR2_IE2 ((uint8_t)0x20) /*!< Comparator 2 Interrupt Enable Mask. */ +#define COMP_CSR2_EF2 ((uint8_t)0x10) /*!< Comparator 2 Event Flag Mask. */ +#define COMP_CSR2_CMP2OUT ((uint8_t)0x08) /*!< Comparator 2 Ouptput Mask. */ +#define COMP_CSR2_SPEED ((uint8_t)0x04) /*!< Comparator 2 speed modeMask. */ +#define COMP_CSR2_CMP2 ((uint8_t)0x03) /*!< Comparator 2 Configuration Mask. */ + +/* CSR3 */ +#define COMP_CSR3_OUTSEL ((uint8_t)0xC0) /*!< Comparator 2 output selection Mask. */ +#define COMP_CSR3_INSEL ((uint8_t)0x38) /*!< Inversion input selection Mask. */ +#define COMP_CSR3_VREFEN ((uint8_t)0x04) /*!< Internal reference voltage Enable Mask. */ +#define COMP_CSR3_WNDWE ((uint8_t)0x02) /*!< Window Mode Enable Mask. */ +#define COMP_CSR3_VREFOUTEN ((uint8_t)0x01) /*!< VREF Output Enable Mask. */ + +/* CSR4 */ +#define COMP_CSR4_NINVTRIG ((uint8_t)0x38) /*!< COMP2 non-inverting input Mask. */ +#define COMP_CSR4_INVTRIG ((uint8_t)0x07) /*!< COMP2 inverting input Mask. */ + +/* CSR5 */ +#define COMP_CSR5_DACTRIG ((uint8_t)0x38) /*!< DAC outputs Mask. */ +#define COMP_CSR5_VREFTRIG ((uint8_t)0x07) /*!< VREF outputs Mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief External Interrupt Controller (EXTI) + */ +typedef struct EXTI_struct +{ + __IO uint8_t CR1; /*!< The four LSB EXTI pin sensitivity */ + __IO uint8_t CR2; /*!< The four MSB EXTI pin sensitivity */ + __IO uint8_t CR3; /*!< EXTI port B & port D sensitivity */ + __IO uint8_t SR1; /*!< Pins Status flag register 1 */ + __IO uint8_t SR2; /*!< Ports Status flage register 2 */ + __IO uint8_t CONF1; /*!< Port interrupt selector */ + uint8_t RESERVED[4]; /*!< reserved area */ + __IO uint8_t CR4; /*!< EXTI port G & port H sensitivity */ + __IO uint8_t CONF2; /*!< Port interrupt selector */ +} +EXTI_TypeDef; + +/** @addtogroup EXTI_Registers_Reset_Value + * @{ + */ + +#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR3_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CONF1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_SR1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_SR2_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR4_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CONF2_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup EXTI_Registers_Bits_Definition + * @{ + */ +/* CR1 */ +#define EXTI_CR1_P3IS ((uint8_t)0xC0) /*!< EXTI Pin 3 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P2IS ((uint8_t)0x30) /*!< EXTI Pin 2 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P1IS ((uint8_t)0x0C) /*!< EXTI Pin 1 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P0IS ((uint8_t)0x03) /*!< EXTI Pin 0 external interrupt sensitivity bit Mask */ + +/* CR2 */ +#define EXTI_CR2_P7IS ((uint8_t)0xC0) /*!< EXTI Pin 7 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P6IS ((uint8_t)0x30) /*!< EXTI Pin 6 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P5IS ((uint8_t)0x0C) /*!< EXTI Pin 5 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P4IS ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */ + +/* CR3 */ +#define EXTI_CR3_PBIS ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PDIS ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PEIS ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PFIS ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */ + +/* CONF1 */ +#define EXTI_CONF1_PBLIS ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */ +#define EXTI_CONF1_PBHIS ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */ +#define EXTI_CONF1_PDLIS ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */ +#define EXTI_CONF1_PDHIS ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */ +#define EXTI_CONF1_PELIS ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */ +#define EXTI_CONF1_PEHIS ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */ +#define EXTI_CONF1_PFLIS ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */ +#define EXTI_CONF1_PFES ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */ + +/* CR4 */ +#define EXTI_CR4_PGIS ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */ +#define EXTI_CR4_PHIS ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */ + +/* CONF2 */ +#define EXTI_CONF2_PFHIS ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */ +#define EXTI_CONF2_PGLIS ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */ +#define EXTI_CONF2_PGHIS ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */ +#define EXTI_CONF2_PHLIS ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */ +#define EXTI_CONF2_PHHIS ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */ +#define EXTI_CONF2_PGBS ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */ +#define EXTI_CONF2_PHDS ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief FLASH and Data EEPROM + */ +typedef struct FLASH_struct +{ + __IO uint8_t CR1; /*!< Flash control register 1 */ + __IO uint8_t CR2; /*!< Flash control register 2 */ + __IO uint8_t PUKR; /*!< Flash program memory unprotection register */ + __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */ + __IO uint8_t IAPSR; /*!< Flash in-application programming status register */ +} +FLASH_TypeDef; + +/** @addtogroup FLASH_Registers_Reset_Value + * @{ + */ +#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00) +#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00) +#define FLASH_PUKR_RESET_VALUE ((uint8_t)0xAE) +#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x56) +#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40) + + +/** + * @} + */ + +/** @addtogroup FLASH_Registers_Bits_Definition + * @{ + */ +#define FLASH_CR1_EEPM ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */ +#define FLASH_CR1_WAITM ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */ +#define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */ +#define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time Mask */ + +#define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Enable write access to option bytes*/ +#define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word write once Mask */ +#define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block Mask */ +#define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode Mask */ +#define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block Mask */ + +#define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag Mask */ +#define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */ +#define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag Mask */ +#define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */ +#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page Mask */ + +#define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */ + +#define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */ + + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Inter-Integrated Circuit (I2C) + */ +typedef struct I2C_struct +{ + __IO uint8_t CR1; /*!< I2C control register 1 */ + __IO uint8_t CR2; /*!< I2C control register 2 */ + __IO uint8_t FREQR; /*!< I2C frequency register */ + __IO uint8_t OARL; /*!< I2C own address register 1 LSB */ + __IO uint8_t OARH; /*!< I2C own address register 1 MSB */ + __IO uint8_t OAR2; /*!< I2C own address register 2 */ + __IO uint8_t DR; /*!< I2C data register */ + __IO uint8_t SR1; /*!< I2C status register 1 */ + __IO uint8_t SR2; /*!< I2C status register 2 */ + __IO uint8_t SR3; /*!< I2C status register 3 */ + __IO uint8_t ITR; /*!< I2C interrupt & DMA register */ + __IO uint8_t CCRL; /*!< I2C clock control register low */ + __IO uint8_t CCRH; /*!< I2C clock control register high */ + __IO uint8_t TRISER; /*!< I2C maximum rise time register */ + __IO uint8_t PECR; /*!< I2CPacket Error Checking register */ +} +I2C_TypeDef; + +/** @addtogroup I2C_Registers_Reset_Value + * @{ + */ +#define I2C_CR1_RESET_VALUE ((uint8_t)0x00) +#define I2C_CR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00) +#define I2C_OARL_RESET_VALUE ((uint8_t)0x00) +#define I2C_OARH_RESET_VALUE ((uint8_t)0x00) +#define I2C_OAR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_DR_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR1_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR3_RESET_VALUE ((uint8_t)0x00) +#define I2C_ITR_RESET_VALUE ((uint8_t)0x00) +#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00) +#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00) +#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02) +#define I2C_PECR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup I2C_Registers_Bits_Definition + * @{ + */ + +#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */ +#define I2C_CR1_ENPEC ((uint8_t)0x20) /*!< PEC Enable */ +#define I2C_CR1_ARP ((uint8_t)0x10) /*!< ARP Enable */ +#define I2C_CR1_SMBTYPE ((uint8_t)0x08) /*!< SMBus type */ +#define I2C_CR1_SMBUS ((uint8_t)0x02) /*!< SMBus mode */ +#define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */ + +#define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */ +#define I2C_CR2_ALERT ((uint8_t)0x20) /*!< SMBus Alert*/ +#define I2C_CR2_PEC ((uint8_t)0x10) /*!< Packet Error Checking */ +#define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */ +#define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */ +#define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */ +#define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */ + +#define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */ + +#define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ +#define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */ + +#define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */ +#define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address mode configuration */ +#define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */ + +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ + +#define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */ + +#define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */ + +#define I2C_SR2_SMBALERT ((uint8_t)0x80) /*!< SMBus Alert */ +#define I2C_SR2_TIMEOUT ((uint8_t)0x40) /*!< Time out or TLow error */ +#define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */ +#define I2C_SR2_PECERR ((uint8_t)0x10) /*!< PEC error in reception */ +#define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */ +#define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */ +#define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */ +#define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */ + +#define I2C_SR3_DUALF ((uint8_t)0x80) /*!< Dual flag (Slave mode) */ +#define I2C_SR3_SMBHOST ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR3_SMBDEFAULT ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */ +#define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */ +#define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */ +#define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */ +#define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */ + +#define I2C_ITR_LAST ((uint8_t)0x10) /*!< DMA Last transfer */ +#define I2C_ITR_DMAEN ((uint8_t)0x08) /*!< DMA request Enable */ +#define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */ +#define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */ +#define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */ + +#define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */ + +#define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */ +#define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */ +#define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */ + +#define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +#define I2C_PECR_PEC ((uint8_t)0xFF) /*!< Packet error checking */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief IR digital interface (IRTIM) + */ +typedef struct IRTIM_struct +{ + __IO uint8_t CR; /*!< control register */ +} +IRTIM_TypeDef; +/** @addtogroup IRTIM_Registers_Reset_Value + * @{ + */ +#define IRTIM_CR_RESET_VALUE ((uint8_t)0x00) + + +/** +* @} +*/ + +/** @addtogroup IRTIM_Registers_Bits_Definition + * @{ + */ +/* CR*/ +#define IRTIM_CR_EN ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */ +#define IRTIM_CR_HSEN ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Interrupt Controller (ITC) + */ +typedef struct ITC_struct +{ + __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */ + __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */ + __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */ + __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */ + __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */ + __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */ + __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */ + __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */ +} +ITC_TypeDef; + +/** @addtogroup ITC_Registers_Reset_Value + * @{ + */ +#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Internal Low Speed Watchdog (IWDG) + */ +typedef struct IWDG_struct +{ + __IO uint8_t KR; /*!< Low Speed Watchdog Key Register */ + __IO uint8_t PR; /*!< Low Speed Watchdog Prescaler Register */ + __IO uint8_t RLR; /*!< Low Speed Watchdog Reload Register */ +} +IWDG_TypeDef; + +/** @addtogroup IWDG_Registers_Reset_Value + * @{ + */ +#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF) /*! + #define enableInterrupts() _rim_() /*! + #define enableInterrupts() __enable_interrupt() /* enable interrupts */ + #define disableInterrupts() __disable_interrupt() /* disable interrupts */ + #define rim() __enable_interrupt() /* enable interrupts */ + #define sim() __disable_interrupt() /* disable interrupts */ + #define nop() __no_operation() /* No Operation */ + #define trap() __trap() /* Trap (soft IT) */ + #define wfi() __wait_for_interrupt() /* Wait For Interrupt */ + #define wfe() __wait_for_event(); /* Wait for event */ + #define halt() __halt() /* Halt */ +#endif /* _RAISONANCE_ */ + +/*============================== Interrupt vector Handling ========================*/ + +#ifdef _COSMIC_ + #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) + #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) +#endif /* _COSMIC_ */ + +#ifdef _RAISONANCE_ + #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b + #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap +#endif /* _RAISONANCE_ */ + +#ifdef _IAR_ + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define INTERRUPT_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define INTERRUPT_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) +#endif /* _IAR_ */ + +/*============================== Interrupt Handler declaration ========================*/ +#ifdef _COSMIC_ + #define INTERRUPT @far @interrupt +#elif defined(_IAR_) + #define INTERRUPT __interrupt +#endif /* _COSMIC_ */ + +/*============================== Handling bits ====================================*/ +/*----------------------------------------------------------------------------- +Method : I +Description : Handle the bit from the character variables. +Comments : The different parameters of commands are + - VAR : Name of the character variable where the bit is located. + - Place : Bit position in the variable (7 6 5 4 3 2 1 0) + - Value : Can be 0 (reset bit) or not 0 (set bit) + The "MskBit" command allows to select some bits in a source + variables and copy it in a destination var (return the value). + The "ValBit" command returns the value of a bit in a char + variable: the bit is reset if it returns 0 else the bit is set. + This method generates not an optimised code yet. +-----------------------------------------------------------------------------*/ +#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) + +#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define AffBit(VAR,Place,Value) ((Value) ? \ + ((VAR) |= ((uint8_t)1<<(Place))) : \ + ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) +#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) + +#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) + +#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ +#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ +#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ +#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ + +/*============================== Assert Macros ====================================*/ +#define IS_STATE_VALUE(STATE) \ + (((STATE) == SET) || \ + ((STATE) == RESET)) + +/*----------------------------------------------------------------------------- +Method : II +Description : Handle directly the bit. +Comments : The idea is to handle directly with the bit name. For that, it is + necessary to have RAM area descriptions (example: HW register...) + and the following command line for each area. + This method generates the most optimized code. +-----------------------------------------------------------------------------*/ + +#define AREA 0x00 /* The area of bits begins at address 0x10. */ + +#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) +#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) +#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) + + +#endif /* __STM8L15x_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/board/STM8L052R8T6/LIB/inc/stm8l15x_adc.h b/board/STM8L052R8T6/LIB/inc/stm8l15x_adc.h new file mode 100644 index 00000000..cfb1d662 --- /dev/null +++ b/board/STM8L052R8T6/LIB/inc/stm8l15x_adc.h @@ -0,0 +1,386 @@ +/** + ****************************************************************************** + * @file stm8l15x_adc.h + * @author MCD Application Team + * @version V1.6.1 + * @date 30-September-2014 + * @brief This file contains all the functions prototypes for the ADC + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8L15x_ADC_H +#define __STM8L15x_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm8l15x.h" + +/** @addtogroup STM8L15x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Types + * @{ + */ + + +/** @defgroup ADC_Channels + * @{ + */ +typedef enum +{ + ADC_Channel_0 = ((uint16_t)0x0301), /*!< Channel 00 */ + ADC_Channel_1 = ((uint16_t)0x0302), /*!< Channel 01 */ + ADC_Channel_2 = ((uint16_t)0x0304), /*!< Channel 02 */ + ADC_Channel_3 = ((uint16_t)0x0308), /*!< Channel 03 */ + ADC_Channel_4 = ((uint16_t)0x0310), /*!< Channel 04 */ + ADC_Channel_5 = ((uint16_t)0x0320), /*!< Channel 05 */ + ADC_Channel_6 = ((uint16_t)0x0340), /*!< Channel 06 */ + ADC_Channel_7 = ((uint16_t)0x0380), /*!< Channel 07 */ + + ADC_Channel_8 = ((uint16_t)0x0201), /*!< Channel 08 */ + ADC_Channel_9 = ((uint16_t)0x0202), /*!< Channel 09 */ + ADC_Channel_10 = ((uint16_t)0x0204), /*!< Channel 10 */ + ADC_Channel_11 = ((uint16_t)0x0208), /*!< Channel 11 */ + ADC_Channel_12 = ((uint16_t)0x0210), /*!< Channel 12 */ + ADC_Channel_13 = ((uint16_t)0x0220), /*!< Channel 13 */ + ADC_Channel_14 = ((uint16_t)0x0240), /*!< Channel 14 */ + ADC_Channel_15 = ((uint16_t)0x0280), /*!< Channel 15 */ + + ADC_Channel_16 = ((uint16_t)0x0101), /*!< Channel 16 */ + ADC_Channel_17 = ((uint16_t)0x0102), /*!< Channel 17 */ + ADC_Channel_18 = ((uint16_t)0x0104), /*!< Channel 18 */ + ADC_Channel_19 = ((uint16_t)0x0108), /*!< Channel 19 */ + ADC_Channel_20 = ((uint16_t)0x0110), /*!< Channel 20 */ + ADC_Channel_21 = ((uint16_t)0x0120), /*!< Channel 21 */ + ADC_Channel_22 = ((uint16_t)0x0140), /*!< Channel 22 */ + ADC_Channel_23 = ((uint16_t)0x0180), /*!< Channel 23 */ + + ADC_Channel_24 = ((uint16_t)0x0001), /*!< Channel 24 */ + ADC_Channel_25 = ((uint16_t)0x0002), /*!< Channel 25 */ + ADC_Channel_26 = ((uint16_t)0x0004), /*!< Channel 26 */ + ADC_Channel_27 = ((uint16_t)0x0008), /*!< Channel 27 */ + + ADC_Channel_Vrefint = ((uint16_t)0x0010), /*!< Vrefint Channel */ + ADC_Channel_TempSensor = ((uint16_t)0x0020), /*!< Temperature sensor Channel */ + + /* combination*/ + ADC_Channel_00To07 = ((uint16_t)0x03FF), /*!