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adjust the order of registers on the stack

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This commit is contained in:
acevest
2019-10-08 14:42:58 +08:00
parent b147d060fb
commit 41ad2d711e
3 changed files with 268 additions and 218 deletions
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70
arch/risc-v/common/include/tos_cpu.h
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@@ -2,47 +2,41 @@
#define _TOS_CPU_H_ #define _TOS_CPU_H_
typedef struct cpu_context_st { typedef struct cpu_context_st {
union { cpu_data_t s0, x8, fp; }; cpu_data_t mepc;
union { cpu_data_t s1, x9; };
union { cpu_data_t s2, x18; };
union { cpu_data_t s3, x19; };
union { cpu_data_t s4, x20; };
union { cpu_data_t s5, x21; };
union { cpu_data_t s6, x22; };
union { cpu_data_t s7, x23; };
union { cpu_data_t s8, x24; };
union { cpu_data_t s9, x25; };
union { cpu_data_t s10,x26; };
union { cpu_data_t s11,x27; };
// caller save
union { cpu_data_t ra, x1; };
union { cpu_data_t gp, x3; };
union { cpu_data_t tp, x4; };
union { cpu_data_t t0, x5; };
union { cpu_data_t t1, x6; };
union { cpu_data_t t2, x7; };
union { cpu_data_t t3, x28; };
union { cpu_data_t t4, x29; };
union { cpu_data_t t5, x30; };
union { cpu_data_t t6, x31; };
union { cpu_data_t a0, x10; };
union { cpu_data_t a1, x11; };
union { cpu_data_t a2, x12; };
union { cpu_data_t a3, x13; };
union { cpu_data_t a4, x14; };
union { cpu_data_t a5, x15; };
union { cpu_data_t a6, x16; };
union { cpu_data_t a7, x17; };
cpu_data_t epc;
cpu_data_t mstatus; cpu_data_t mstatus;
union { cpu_data_t x1, ra; };
union { cpu_data_t x3, gp; };
union { cpu_data_t x4, tp; };
union { cpu_data_t x5, t0; };
union { cpu_data_t x6, t1; };
union { cpu_data_t x7, t2; };
union { cpu_data_t x8, s0, fp; };
union { cpu_data_t x9, s1; };
union { cpu_data_t x10, a0; };
union { cpu_data_t x11, a1; };
union { cpu_data_t x12, a2; };
union { cpu_data_t x13, a3; };
union { cpu_data_t x14, a4; };
union { cpu_data_t x15, a5; };
union { cpu_data_t x16, a6; };
union { cpu_data_t x17, a7; };
union { cpu_data_t x18, s2; };
union { cpu_data_t x19, s3; };
union { cpu_data_t x20, s4; };
union { cpu_data_t x21, s5; };
union { cpu_data_t x22, s6; };
union { cpu_data_t x23, s7; };
union { cpu_data_t x24, s8; };
union { cpu_data_t x25, s9; };
union { cpu_data_t x26, s10; };
union { cpu_data_t x27, s11; };
union { cpu_data_t x28, t3; };
union { cpu_data_t x29, t4; };
union { cpu_data_t x30, t5; };
union { cpu_data_t x31, t6; };
} cpu_context_t; } cpu_context_t;
__API__ uint32_t tos_cpu_clz(uint32_t val); __API__ uint32_t tos_cpu_clz(uint32_t val);
__API__ void tos_cpu_int_disable(void); __API__ void tos_cpu_int_disable(void);

4
arch/risc-v/common/tos_cpu.c
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@@ -74,7 +74,7 @@ Inx Offset Register
03 012 x3 gp 03 012 x3 gp
02 008 x1 ra 02 008 x1 ra
01 004 mstatus 01 004 mstatus
00 000 epc 00 000 mepc
*/ */
@@ -107,7 +107,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry,
regs->a0 = (cpu_data_t)arg; // a0: argument regs->a0 = (cpu_data_t)arg; // a0: argument
regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address
regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt
regs->epc = (cpu_data_t)entry; regs->mepc = (cpu_data_t)entry;
return (k_stack_t*)sp; return (k_stack_t*)sp;

412
arch/risc-v/rv32i/gcc/port_s.S
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@@ -24,8 +24,6 @@
.equ MIP_MTIP, (1 << 7) // machine mode timer interrupt pending .equ MIP_MTIP, (1 << 7) // machine mode timer interrupt pending
.equ REGBYTES, 4
.text .text
.align 2 .align 2
@@ -67,6 +65,75 @@ port_systick_pending_reset:
csrc mip, t0 csrc mip, t0
ret ret
#define __reg_mepc_OFFSET 0x00
#define __reg_mstatus_OFFSET 0x04
#define __reg_x1_OFFSET 0x08
#define __reg_x3_OFFSET 0x0C
#define __reg_x4_OFFSET 0x10
#define __reg_x5_OFFSET 0x14
#define __reg_x6_OFFSET 0x18
#define __reg_x7_OFFSET 0x1C
#define __reg_x8_OFFSET 0x20
#define __reg_x9_OFFSET 0x24
#define __reg_x10_OFFSET 0x28
#define __reg_x11_OFFSET 0x2C
#define __reg_x12_OFFSET 0x30
#define __reg_x13_OFFSET 0x34
#define __reg_x14_OFFSET 0x38
#define __reg_x15_OFFSET 0x3C
#define __reg_x16_OFFSET 0x40
#define __reg_x17_OFFSET 0x44
#define __reg_x18_OFFSET 0x48
#define __reg_x19_OFFSET 0x4C
#define __reg_x20_OFFSET 0x50
#define __reg_x21_OFFSET 0x54
#define __reg_x22_OFFSET 0x58
#define __reg_x23_OFFSET 0x5C
#define __reg_x24_OFFSET 0x60
#define __reg_x25_OFFSET 0x64
#define __reg_x26_OFFSET 0x68
#define __reg_x27_OFFSET 0x6C
#define __reg_x28_OFFSET 0x70
#define __reg_x29_OFFSET 0x74
#define __reg_x30_OFFSET 0x78
#define __reg_x31_OFFSET 0x7C
#define __reg_mepc__OFFSET __reg_mepc_OFFSET
#define __reg_mstatus__OFFSET __reg_mstatus_OFFSET
#define __reg_ra__OFFSET __reg_x1_OFFSET
#define __reg_gp__OFFSET __reg_x3_OFFSET
#define __reg_tp__OFFSET __reg_x4_OFFSET
#define __reg_t0__OFFSET __reg_x5_OFFSET
#define __reg_t1__OFFSET __reg_x6_OFFSET
#define __reg_t2__OFFSET __reg_x7_OFFSET
#define __reg_s0__OFFSET __reg_x8_OFFSET
#define __reg_fp__OFFSET __reg_x8_OFFSET
#define __reg_s1__OFFSET __reg_x9_OFFSET
#define __reg_a0__OFFSET __reg_x10_OFFSET
#define __reg_a1__OFFSET __reg_x11_OFFSET
#define __reg_a2__OFFSET __reg_x12_OFFSET
#define __reg_a3__OFFSET __reg_x13_OFFSET
#define __reg_a4__OFFSET __reg_x14_OFFSET
#define __reg_a5__OFFSET __reg_x15_OFFSET
#define __reg_a6__OFFSET __reg_x16_OFFSET
#define __reg_a7__OFFSET __reg_x17_OFFSET
#define __reg_s2__OFFSET __reg_x18_OFFSET
#define __reg_s3__OFFSET __reg_x19_OFFSET
#define __reg_s4__OFFSET __reg_x20_OFFSET
#define __reg_s5__OFFSET __reg_x21_OFFSET
#define __reg_s6__OFFSET __reg_x22_OFFSET
#define __reg_s7__OFFSET __reg_x23_OFFSET
#define __reg_s8__OFFSET __reg_x24_OFFSET
#define __reg_s9__OFFSET __reg_x25_OFFSET
#define __reg_s10__OFFSET __reg_x26_OFFSET
#define __reg_s11__OFFSET __reg_x27_OFFSET
#define __reg_t3__OFFSET __reg_x28_OFFSET
#define __reg_t4__OFFSET __reg_x29_OFFSET
#define __reg_t5__OFFSET __reg_x30_OFFSET
#define __reg_t6__OFFSET __reg_x31_OFFSET
.align 2 .align 2
.type port_sched_start, %function .type port_sched_start, %function
port_sched_start: port_sched_start:
@@ -80,51 +147,47 @@ port_sched_start:
lw sp, (t0) // sp = k_curr_task->sp lw sp, (t0) // sp = k_curr_task->sp
// save sp to stack // save sp to stack
addi t1, sp, 32*REGBYTES addi t1, sp, 128
sw t1, (t0) sw t1, (t0)
// restore context // restore context
lw t0, 30*REGBYTES(sp) lw t0, __reg_mepc__OFFSET(sp)
csrw mepc, t0 csrw mepc, t0
lw t0, 31*REGBYTES(sp) lw t0, __reg_mstatus__OFFSET(sp)
csrw mstatus, t0 csrw mstatus, t0
lw s0, 0*REGBYTES(sp) lw x3, __reg_x3_OFFSET(sp)
lw s1, 1*REGBYTES(sp) lw x4, __reg_x4_OFFSET(sp)
lw s2, 2*REGBYTES(sp) lw x5, __reg_x5_OFFSET(sp)
lw s3, 3*REGBYTES(sp) lw x6, __reg_x6_OFFSET(sp)
lw s4, 4*REGBYTES(sp) lw x7, __reg_x7_OFFSET(sp)
lw s5, 5*REGBYTES(sp) lw x8, __reg_x8_OFFSET(sp)
lw s6, 6*REGBYTES(sp) lw x9, __reg_x9_OFFSET(sp)
lw s7, 7*REGBYTES(sp) lw x10, __reg_x10_OFFSET(sp)
lw s8, 8*REGBYTES(sp) lw x11, __reg_x11_OFFSET(sp)
lw s9, 9*REGBYTES(sp) lw x12, __reg_x12_OFFSET(sp)
lw s10, 10*REGBYTES(sp) lw x13, __reg_x13_OFFSET(sp)
lw s11, 11*REGBYTES(sp) lw x14, __reg_x14_OFFSET(sp)
lw x15, __reg_x15_OFFSET(sp)
lw x16, __reg_x16_OFFSET(sp)
lw x17, __reg_x17_OFFSET(sp)
lw x18, __reg_x18_OFFSET(sp)
lw x19, __reg_x19_OFFSET(sp)
lw x20, __reg_x20_OFFSET(sp)
lw x21, __reg_x21_OFFSET(sp)
lw x22, __reg_x22_OFFSET(sp)
lw x23, __reg_x23_OFFSET(sp)
lw x24, __reg_x24_OFFSET(sp)
lw x25, __reg_x25_OFFSET(sp)
lw x26, __reg_x26_OFFSET(sp)
lw x27, __reg_x27_OFFSET(sp)
lw x28, __reg_x28_OFFSET(sp)
lw x29, __reg_x29_OFFSET(sp)
lw x30, __reg_x30_OFFSET(sp)
lw x31, __reg_x31_OFFSET(sp)
// caller save addi sp, sp, 128
lw ra, 12*REGBYTES(sp)
lw gp, 13*REGBYTES(sp)
lw tp, 14*REGBYTES(sp)
lw t0, 15*REGBYTES(sp)
lw t1, 16*REGBYTES(sp)
lw t2, 17*REGBYTES(sp)
lw t3, 18*REGBYTES(sp)
lw t4, 19*REGBYTES(sp)
lw t5, 20*REGBYTES(sp)
lw t6, 21*REGBYTES(sp)
lw a0, 22*REGBYTES(sp)
lw a1, 23*REGBYTES(sp)
lw a2, 24*REGBYTES(sp)
lw a3, 25*REGBYTES(sp)
lw a4, 26*REGBYTES(sp)
lw a5, 27*REGBYTES(sp)
lw a6, 28*REGBYTES(sp)
lw a7, 29*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret mret
@@ -132,47 +195,44 @@ port_sched_start:
.align 2 .align 2
.type port_context_switch, %function .type port_context_switch, %function
port_context_switch: port_context_switch:
addi sp, sp, -32*REGBYTES addi sp, sp, -128
sw x3, __reg_x3_OFFSET(sp)
sw x4, __reg_x4_OFFSET(sp)
sw x5, __reg_x5_OFFSET(sp)
sw x6, __reg_x6_OFFSET(sp)
sw x7, __reg_x7_OFFSET(sp)
sw x8, __reg_x8_OFFSET(sp)
sw x9, __reg_x9_OFFSET(sp)
sw x10, __reg_x10_OFFSET(sp)
sw x11, __reg_x11_OFFSET(sp)
sw x12, __reg_x12_OFFSET(sp)
sw x13, __reg_x13_OFFSET(sp)
sw x14, __reg_x14_OFFSET(sp)
sw x15, __reg_x15_OFFSET(sp)
sw x16, __reg_x16_OFFSET(sp)
sw x17, __reg_x17_OFFSET(sp)
sw x18, __reg_x18_OFFSET(sp)
sw x19, __reg_x19_OFFSET(sp)
sw x20, __reg_x20_OFFSET(sp)
sw x21, __reg_x21_OFFSET(sp)
sw x22, __reg_x22_OFFSET(sp)
sw x23, __reg_x23_OFFSET(sp)
sw x24, __reg_x24_OFFSET(sp)
sw x25, __reg_x25_OFFSET(sp)
sw x26, __reg_x26_OFFSET(sp)
sw x27, __reg_x27_OFFSET(sp)
sw x28, __reg_x28_OFFSET(sp)
sw x29, __reg_x29_OFFSET(sp)
sw x30, __reg_x30_OFFSET(sp)
sw x31, __reg_x31_OFFSET(sp)
sw s0, 0*REGBYTES(sp)
sw s1, 1*REGBYTES(sp)
sw s2, 2*REGBYTES(sp)
sw s3, 3*REGBYTES(sp)
sw s4, 4*REGBYTES(sp)
sw s5, 5*REGBYTES(sp)
sw s6, 6*REGBYTES(sp)
sw s7, 7*REGBYTES(sp)
sw s8, 8*REGBYTES(sp)
sw s9, 9*REGBYTES(sp)
sw s10, 10*REGBYTES(sp)
sw s11, 11*REGBYTES(sp)
// caller save sw ra, __reg_mepc_OFFSET(sp)
sw ra, 12*REGBYTES(sp)
sw gp, 13*REGBYTES(sp)
sw tp, 14*REGBYTES(sp)
sw t0, 15*REGBYTES(sp)
sw t1, 16*REGBYTES(sp)
sw t2, 17*REGBYTES(sp)
sw t3, 18*REGBYTES(sp)
sw t4, 19*REGBYTES(sp)
sw t5, 20*REGBYTES(sp)
sw t6, 21*REGBYTES(sp)
sw a0, 22*REGBYTES(sp)
sw a1, 23*REGBYTES(sp)
sw a2, 24*REGBYTES(sp)
sw a3, 25*REGBYTES(sp)
sw a4, 26*REGBYTES(sp)
sw a5, 27*REGBYTES(sp)
sw a6, 28*REGBYTES(sp)
sw a7, 29*REGBYTES(sp)
sw ra, 30*REGBYTES(sp)
csrr t0, mstatus csrr t0, mstatus
li t1, MSTATUS_MPP li t1, MSTATUS_MPP
or t0, t0, t1 or t0, t0, t1
sw t0, 31*REGBYTES(sp) sw t0, __reg_mstatus_OFFSET(sp)
// save sp to k_curr_task.sp // save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task la t0, k_curr_task // t0 = &k_curr_task
@@ -189,46 +249,43 @@ port_context_switch:
lw sp, (t1) lw sp, (t1)
// restore context // restore context
lw t0, 30*REGBYTES(sp) lw t0, __reg_mepc_OFFSET(sp)
csrw mepc, t0 csrw mepc, t0
lw t0, 31*REGBYTES(sp) lw t0, __reg_mstatus_OFFSET(sp)
csrw mstatus, t0 csrw mstatus, t0
lw x3, __reg_x3_OFFSET(sp)
lw x4, __reg_x4_OFFSET(sp)
lw x5, __reg_x5_OFFSET(sp)
lw x6, __reg_x6_OFFSET(sp)
lw x7, __reg_x7_OFFSET(sp)
lw x8, __reg_x8_OFFSET(sp)
lw x9, __reg_x9_OFFSET(sp)
lw x10, __reg_x10_OFFSET(sp)
lw x11, __reg_x11_OFFSET(sp)
lw x12, __reg_x12_OFFSET(sp)
lw x13, __reg_x13_OFFSET(sp)
lw x14, __reg_x14_OFFSET(sp)
lw x15, __reg_x15_OFFSET(sp)
lw x16, __reg_x16_OFFSET(sp)
lw x17, __reg_x17_OFFSET(sp)
lw x18, __reg_x18_OFFSET(sp)
lw x19, __reg_x19_OFFSET(sp)
lw x20, __reg_x20_OFFSET(sp)
lw x21, __reg_x21_OFFSET(sp)
lw x22, __reg_x22_OFFSET(sp)
lw x23, __reg_x23_OFFSET(sp)
lw x24, __reg_x24_OFFSET(sp)
lw x25, __reg_x25_OFFSET(sp)
lw x26, __reg_x26_OFFSET(sp)
lw x27, __reg_x27_OFFSET(sp)
lw x28, __reg_x28_OFFSET(sp)
lw x29, __reg_x29_OFFSET(sp)
lw x30, __reg_x30_OFFSET(sp)
lw x31, __reg_x31_OFFSET(sp)
lw s0, 0*REGBYTES(sp) addi sp, sp, 128
lw s1, 1*REGBYTES(sp)
lw s2, 2*REGBYTES(sp)
lw s3, 3*REGBYTES(sp)
lw s4, 4*REGBYTES(sp)
lw s5, 5*REGBYTES(sp)
lw s6, 6*REGBYTES(sp)
lw s7, 7*REGBYTES(sp)
lw s8, 8*REGBYTES(sp)
lw s9, 9*REGBYTES(sp)
lw s10, 10*REGBYTES(sp)
lw s11, 11*REGBYTES(sp)
// caller save
lw ra, 12*REGBYTES(sp)
lw gp, 13*REGBYTES(sp)
lw tp, 14*REGBYTES(sp)
lw t0, 15*REGBYTES(sp)
lw t1, 16*REGBYTES(sp)
lw t2, 17*REGBYTES(sp)
lw t3, 18*REGBYTES(sp)
lw t4, 19*REGBYTES(sp)
lw t5, 20*REGBYTES(sp)
lw t6, 21*REGBYTES(sp)
lw a0, 22*REGBYTES(sp)
lw a1, 23*REGBYTES(sp)
lw a2, 24*REGBYTES(sp)
lw a3, 25*REGBYTES(sp)
lw a4, 26*REGBYTES(sp)
lw a5, 27*REGBYTES(sp)
lw a6, 28*REGBYTES(sp)
lw a7, 29*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret mret
@@ -236,31 +293,32 @@ port_context_switch:
.align 2 .align 2
.global rv32_exception_entry .global rv32_exception_entry
rv32_exception_entry: rv32_exception_entry:
addi sp, sp, -20*REGBYTES addi sp, sp, -128
sw ra, (12-12)*REGBYTES(sp)
sw gp, (13-12)*REGBYTES(sp) sw ra, __reg_ra__OFFSET(sp)
sw tp, (14-12)*REGBYTES(sp) sw gp, __reg_gp__OFFSET(sp)
sw t0, (15-12)*REGBYTES(sp) sw tp, __reg_tp__OFFSET(sp)
sw t1, (16-12)*REGBYTES(sp) sw t0, __reg_t0__OFFSET(sp)
sw t2, (17-12)*REGBYTES(sp) sw t1, __reg_t1__OFFSET(sp)
sw t3, (18-12)*REGBYTES(sp) sw t2, __reg_t2__OFFSET(sp)
sw t4, (19-12)*REGBYTES(sp) sw t3, __reg_t3__OFFSET(sp)
sw t5, (20-12)*REGBYTES(sp) sw t4, __reg_t4__OFFSET(sp)
sw t6, (21-12)*REGBYTES(sp) sw t5, __reg_t5__OFFSET(sp)
sw a0, (22-12)*REGBYTES(sp) sw t6, __reg_t6__OFFSET(sp)
sw a1, (23-12)*REGBYTES(sp) sw a0, __reg_a0__OFFSET(sp)
sw a2, (24-12)*REGBYTES(sp) sw a1, __reg_a1__OFFSET(sp)
sw a3, (25-12)*REGBYTES(sp) sw a2, __reg_a2__OFFSET(sp)
sw a4, (26-12)*REGBYTES(sp) sw a3, __reg_a3__OFFSET(sp)
sw a5, (27-12)*REGBYTES(sp) sw a4, __reg_a4__OFFSET(sp)
sw a6, (28-12)*REGBYTES(sp) sw a5, __reg_a5__OFFSET(sp)
sw a7, (29-12)*REGBYTES(sp) sw a6, __reg_a6__OFFSET(sp)
sw a7, __reg_a7__OFFSET(sp)
csrr t0, mepc csrr t0, mepc
sw t0, (30-12)*REGBYTES(sp) sw t0, __reg_mepc__OFFSET(sp)
csrr t0, mstatus csrr t0, mstatus
sw t0, (31-12)*REGBYTES(sp) sw t0, __reg_mstatus__OFFSET(sp)
// get irq num and call irq handler // get irq num and call irq handler
li t0, SOC_MCAUSE_EXP_MASK li t0, SOC_MCAUSE_EXP_MASK
@@ -272,19 +330,19 @@ rv32_exception_entry:
la t1, k_next_task la t1, k_next_task
beq t0, t1, irq_restore beq t0, t1, irq_restore
addi sp, sp, -12*REGBYTES
sw s0, 0*REGBYTES(sp) sw s0, __reg_s0__OFFSET(sp)
sw s1, 1*REGBYTES(sp) sw s1, __reg_s1__OFFSET(sp)
sw s2, 2*REGBYTES(sp) sw s2, __reg_s2__OFFSET(sp)
sw s3, 3*REGBYTES(sp) sw s3, __reg_s3__OFFSET(sp)
sw s4, 4*REGBYTES(sp) sw s4, __reg_s4__OFFSET(sp)
sw s5, 5*REGBYTES(sp) sw s5, __reg_s5__OFFSET(sp)
sw s6, 6*REGBYTES(sp) sw s6, __reg_s6__OFFSET(sp)
sw s7, 7*REGBYTES(sp) sw s7, __reg_s7__OFFSET(sp)
sw s8, 8*REGBYTES(sp) sw s8, __reg_s8__OFFSET(sp)
sw s9, 9*REGBYTES(sp) sw s9, __reg_s9__OFFSET(sp)
sw s10, 10*REGBYTES(sp) sw s10, __reg_s10__OFFSET(sp)
sw s11, 11*REGBYTES(sp) sw s11, __reg_s11__OFFSET(sp)
// save sp to k_curr_task.sp // save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task la t0, k_curr_task // t0 = &k_curr_task
@@ -298,47 +356,45 @@ rv32_exception_entry:
// load new task sp // load new task sp
lw sp, (t1) lw sp, (t1)
lw s0, 0*REGBYTES(sp) lw s0, __reg_s0__OFFSET(sp)
lw s1, 1*REGBYTES(sp) lw s1, __reg_s1__OFFSET(sp)
lw s2, 2*REGBYTES(sp) lw s2, __reg_s2__OFFSET(sp)
lw s3, 3*REGBYTES(sp) lw s3, __reg_s3__OFFSET(sp)
lw s4, 4*REGBYTES(sp) lw s4, __reg_s4__OFFSET(sp)
lw s5, 5*REGBYTES(sp) lw s5, __reg_s5__OFFSET(sp)
lw s6, 6*REGBYTES(sp) lw s6, __reg_s6__OFFSET(sp)
lw s7, 7*REGBYTES(sp) lw s7, __reg_s7__OFFSET(sp)
lw s8, 8*REGBYTES(sp) lw s8, __reg_s8__OFFSET(sp)
lw s9, 9*REGBYTES(sp) lw s9, __reg_s9__OFFSET(sp)
lw s10, 10*REGBYTES(sp) lw s10, __reg_s10__OFFSET(sp)
lw s11, 11*REGBYTES(sp) lw s11, __reg_s11__OFFSET(sp)
addi sp, sp, 12*REGBYTES
irq_restore: irq_restore:
// restore context lw t0, __reg_mepc_OFFSET(sp)
lw t0, (30-12)*REGBYTES(sp)
csrw mepc, t0 csrw mepc, t0
lw t0, (31-12)*REGBYTES(sp) lw t0, __reg_mstatus_OFFSET(sp)
csrw mstatus, t0 csrw mstatus, t0
lw ra, (12-12)*REGBYTES(sp) lw ra, __reg_ra__OFFSET(sp)
lw gp, (13-12)*REGBYTES(sp) lw gp, __reg_gp__OFFSET(sp)
lw tp, (14-12)*REGBYTES(sp) lw tp, __reg_tp__OFFSET(sp)
lw t0, (15-12)*REGBYTES(sp) lw t0, __reg_t0__OFFSET(sp)
lw t1, (16-12)*REGBYTES(sp) lw t1, __reg_t1__OFFSET(sp)
lw t2, (17-12)*REGBYTES(sp) lw t2, __reg_t2__OFFSET(sp)
lw t3, (18-12)*REGBYTES(sp) lw t3, __reg_t3__OFFSET(sp)
lw t4, (19-12)*REGBYTES(sp) lw t4, __reg_t4__OFFSET(sp)
lw t5, (20-12)*REGBYTES(sp) lw t5, __reg_t5__OFFSET(sp)
lw t6, (21-12)*REGBYTES(sp) lw t6, __reg_t6__OFFSET(sp)
lw a0, (22-12)*REGBYTES(sp) lw a0, __reg_a0__OFFSET(sp)
lw a1, (23-12)*REGBYTES(sp) lw a1, __reg_a1__OFFSET(sp)
lw a2, (24-12)*REGBYTES(sp) lw a2, __reg_a2__OFFSET(sp)
lw a3, (25-12)*REGBYTES(sp) lw a3, __reg_a3__OFFSET(sp)
lw a4, (26-12)*REGBYTES(sp) lw a4, __reg_a4__OFFSET(sp)
lw a5, (27-12)*REGBYTES(sp) lw a5, __reg_a5__OFFSET(sp)
lw a6, (28-12)*REGBYTES(sp) lw a6, __reg_a6__OFFSET(sp)
lw a7, (29-12)*REGBYTES(sp) lw a7, __reg_a7__OFFSET(sp)
addi sp, sp, 20*REGBYTES addi sp, sp, 128
mret mret