add iccarm support for cm3
1. IAR project, see TencentOS-tiny\board\STM32F103_SIM800A\iar
This commit is contained in:
daishengdong
312
arch/arm/arm-v7m/cortex-m3/iccarm/port.h
Normal file
312
arch/arm/arm-v7m/cortex-m3/iccarm/port.h
Normal file
@@ -0,0 +1,312 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Tencent is pleased to support the open source community by making TencentOS
|
||||
* available.
|
||||
*
|
||||
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
|
||||
* If you have downloaded a copy of the TencentOS binary from Tencent, please
|
||||
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
|
||||
*
|
||||
* If you have downloaded a copy of the TencentOS source code from Tencent,
|
||||
* please note that TencentOS source code is licensed under the BSD 3-Clause
|
||||
* License, except for the third-party components listed below which are
|
||||
* subject to different license terms. Your integration of TencentOS into your
|
||||
* own projects may require compliance with the BSD 3-Clause License, as well
|
||||
* as the other licenses applicable to the third-party components included
|
||||
* within TencentOS.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* 'Software'), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
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||||
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||||
#ifndef _PORT_H_
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#define _PORT_H_
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#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
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typedef struct port_fault_regs {
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union {
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/* System Handler Control and State Register (0xE000ED24) */
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uint32_t value;
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struct {
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/* Read as 1 if memory management fault is active */
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uint32_t MEMFAULTACT : 1;
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/* Read as 1 if bus fault exception is active */
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uint32_t BUSFAULTACT : 1;
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uint32_t UnusedBits1 : 1;
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/* Read as 1 if usage fault exception is active */
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uint32_t USGFAULTACT : 1;
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uint32_t UnusedBits2 : 3;
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/* Read as 1 if SVC exception is active */
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uint32_t SVCALLACT : 1;
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/* Read as 1 if debug monitor exception is active */
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uint32_t MONITORACT : 1;
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uint32_t UnusedBits3 : 1;
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/* Read as 1 if PendSV exception is active */
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uint32_t PENDSVACT : 1;
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/* Read as 1 if SYSTICK exception is active */
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uint32_t SYSTICKACT : 1;
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/* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
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uint32_t USGFAULTPENDED : 1;
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/* Memory management fault pended; memory management fault started but was replaced by a
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higher-priority exception */
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uint32_t MEMFAULTPENDED : 1;
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/* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
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exception */
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uint32_t BUSFAULTPENDED : 1;
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/* SVC pended; SVC was started but was replaced by a higher-priority exception */
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uint32_t SVCALLPENDED : 1;
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/* Memory management fault handler enable */
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uint32_t MEMFAULTENA : 1;
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/* Bus fault handler enable */
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uint32_t BUSFAULTENA : 1;
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/* Usage fault handler enable */
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uint32_t USGFAULTENA : 1;
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} bits;
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} syshndctrl;
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union {
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uint32_t value;
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struct {
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union {
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/* Memory Management Fault Status Register (0xE000ED28) */
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uint8_t value;
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struct {
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/* Instruction access violation */
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uint8_t IACCVIOL : 1;
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/* Data access violation */
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uint8_t DACCVIOL : 1;
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uint8_t UnusedBits : 1;
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/* Unstacking error */
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uint8_t MUNSTKERR : 1;
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/* Stacking error */
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uint8_t MSTKERR : 1;
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/* Floating-point lazy state preservation (M4/M7) */
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uint8_t MLSPERR : 1;
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uint8_t UnusedBits2 : 1;
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/* Indicates the MMAR is valid */
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uint8_t MMARVALID : 1;
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} bits;
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} mfsr;
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union {
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/* Bus Fault Status Register (0xE000ED29) */
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uint8_t value;
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struct {
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/* Instruction access violation */
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uint8_t IBUSERR : 1;
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/* Precise data access violation */
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uint8_t PRECISERR : 1;
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/* Imprecise data access violation */
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uint8_t IMPREISERR : 1;
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/* Unstacking error */
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uint8_t UNSTKERR : 1;
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/* Stacking error */
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uint8_t STKERR : 1;
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/* Floating-point lazy state preservation (M4/M7) */
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uint8_t LSPERR : 1;
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uint8_t UnusedBits : 1;
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/* Indicates BFAR is valid */
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uint8_t BFARVALID : 1;
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} bits;
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} bfsr;
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union {
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/* Usage Fault Status Register (0xE000ED2A) */
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uint16_t value;
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struct {
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/* Attempts to execute an undefined instruction */
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uint16_t UNDEFINSTR : 1;
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/* Attempts to switch to an invalid state (e.g., ARM) */
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uint16_t INVSTATE : 1;
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/* Attempts to do an exception with a bad value in the EXC_RETURN number */
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uint16_t INVPC : 1;
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/* Attempts to execute a coprocessor instruction */
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uint16_t NOCP : 1;
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uint16_t UnusedBits : 4;
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/* Indicates that an unaligned access fault has taken place */
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uint16_t UNALIGNED : 1;
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/* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
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uint16_t DIVBYZERO0 : 1;
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} bits;
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} ufsr;
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} part;
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} cfsr;
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/* Memory Management Fault Address Register (0xE000ED34) */
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uint32_t mmar;
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/* Bus Fault Manage Address Register (0xE000ED38) */
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uint32_t bfar;
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union {
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/* Hard Fault Status Register (0xE000ED2C) */
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uint32_t value;
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struct {
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uint32_t UnusedBits : 1;
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/* Indicates hard fault is caused by failed vector fetch */
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uint32_t VECTBL : 1;
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uint32_t UnusedBits2 : 28;
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/* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
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uint32_t FORCED : 1;
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/* Indicates hard fault is triggered by debug event */
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uint32_t DEBUGEVT : 1;
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} bits;
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} hfsr;
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union {
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/* Debug Fault Status Register (0xE000ED30) */
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uint32_t value;
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struct {
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/* Halt requested in NVIC */
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uint32_t HALTED : 1;
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/* BKPT instruction executed */
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uint32_t BKPT : 1;
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/* DWT match occurred */
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uint32_t DWTTRAP : 1;
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/* Vector fetch occurred */
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uint32_t VCATCH : 1;
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/* EDBGRQ signal asserted */
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uint32_t EXTERNAL : 1;
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} bits;
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} dfsr;
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/* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
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uint32_t afsr;
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} port_fault_regs_t;
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enum fault_info {
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FAULT_INFO_ASSERT_ON_THREAD,
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FAULT_INFO_HFSR_VECTBL,
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FAULT_INFO_MFSR_IACCVIOL,
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FAULT_INFO_MFSR_DACCVIOL,
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FAULT_INFO_MFSR_MUNSTKERR,
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FAULT_INFO_MFSR_MSTKERR,
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FAULT_INFO_MFSR_MLSPERR,
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FAULT_INFO_BFSR_IBUSERR,
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FAULT_INFO_BFSR_PRECISERR,
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FAULT_INFO_BFSR_IMPREISERR,
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FAULT_INFO_BFSR_UNSTKERR,
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FAULT_INFO_BFSR_STKERR,
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FAULT_INFO_BFSR_LSPERR,
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FAULT_INFO_UFSR_UNDEFINSTR,
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FAULT_INFO_UFSR_INVSTATE,
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FAULT_INFO_UFSR_INVPC,
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FAULT_INFO_UFSR_NOCP,
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FAULT_INFO_UFSR_UNALIGNED,
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FAULT_INFO_UFSR_DIVBYZERO0,
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FAULT_INFO_DFSR_HALTED,
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FAULT_INFO_DFSR_BKPT,
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FAULT_INFO_DFSR_DWTTRAP,
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FAULT_INFO_DFSR_VCATCH,
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FAULT_INFO_DFSR_EXTERNAL,
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FAULT_INFO_MMAR,
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FAULT_INFO_BFAR,
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};
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static const char *const fault_msg[] = {
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[FAULT_INFO_ASSERT_ON_THREAD] = "Assert on thread %s\n",
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[FAULT_INFO_HFSR_VECTBL] = "Hard fault is caused by failed vector fetch\n",
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[FAULT_INFO_MFSR_IACCVIOL] = "Memory management fault: instruction access violation\n",
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[FAULT_INFO_MFSR_DACCVIOL] = "Memory management fault: data access violation\n",
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[FAULT_INFO_MFSR_MUNSTKERR] = "Memory management fault: unstacking error\n",
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[FAULT_INFO_MFSR_MSTKERR] = "Memory management fault: stacking error\n",
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[FAULT_INFO_MFSR_MLSPERR] = "Memory management fault: floating-point lazy state preservation\n",
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[FAULT_INFO_BFSR_IBUSERR] = "Bus fault: instruction access violation\n",
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[FAULT_INFO_BFSR_PRECISERR] = "Bus fault: precise data access violation\n",
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[FAULT_INFO_BFSR_IMPREISERR] = "Bus fault: imprecise data access violation\n",
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[FAULT_INFO_BFSR_UNSTKERR] = "Bus fault: unstacking error\n",
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[FAULT_INFO_BFSR_STKERR] = "Bus fault: stacking error\n",
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[FAULT_INFO_BFSR_LSPERR] = "Bus fault: floating-point lazy state preservation\n",
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[FAULT_INFO_UFSR_UNDEFINSTR] = "Usage fault: undefined instruction\n",
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[FAULT_INFO_UFSR_INVSTATE] = "Usage fault: invalid state (e.g., ARM)\n",
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[FAULT_INFO_UFSR_INVPC] = "Usage fault: invalid EXC_RETURN\n",
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[FAULT_INFO_UFSR_NOCP] = "Usage fault: coprocessor instruction\n",
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[FAULT_INFO_UFSR_UNALIGNED] = "Usage fault: unaligned access\n",
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[FAULT_INFO_UFSR_DIVBYZERO0] = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
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[FAULT_INFO_DFSR_HALTED] = "Debug fault: halt requested in NVIC\n",
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[FAULT_INFO_DFSR_BKPT] = "Debug fault: BKPT instruction executed\n",
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[FAULT_INFO_DFSR_DWTTRAP] = "Debug fault: DWT match occurred\n",
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[FAULT_INFO_DFSR_VCATCH] = "Debug fault: Vector fetch occurred\n",
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[FAULT_INFO_DFSR_EXTERNAL] = "Debug fault: EDBGRQ signal asserted\n",
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[FAULT_INFO_MMAR] = "The memory management fault occurred address is %08x\n",
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[FAULT_INFO_BFAR] = "The bus fault occurred address is %08x\n",
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};
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__PORT__ void HardFault_Handler(void);
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__PORT__ void port_fault_diagnosis(void);
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#endif
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#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
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__PORT__ uint32_t port_clz(uint32_t val);
|
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#endif
|
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|
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__PORT__ void port_int_disable(void);
|
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|
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__PORT__ void port_int_enable(void);
|
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|
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__PORT__ cpu_cpsr_t port_cpsr_save(void);
|
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|
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__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
|
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|
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__PORT__ void port_cpu_reset(void);
|
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|
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__PORT__ void port_sched_start(void) __NO_RETURN__;
|
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__PORT__ void port_context_switch(void);
|
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|
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__PORT__ void port_irq_context_switch(void);
|
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|
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__PORT__ void port_systick_config(uint32_t cycle_per_tick);
|
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|
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__PORT__ void port_systick_priority_set(uint32_t prio);
|
||||
|
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#if TOS_CFG_TICKLESS_EN > 0u
|
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|
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__PORT__ void port_systick_resume(void);
|
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|
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__PORT__ void port_systick_suspend(void);
|
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|
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__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
|
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|
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__PORT__ void port_systick_pending_reset(void);
|
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|
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__PORT__ k_time_t port_systick_max_delay_millisecond(void);
|
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|
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#endif
|
||||
|
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#if TOS_CFG_PWR_MGR_EN > 0u
|
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|
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__PORT__ void port_sleep_mode_enter(void);
|
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|
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__PORT__ void port_stop_mode_enter(void);
|
||||
|
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__PORT__ void port_standby_mode_enter(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _PORT_H_ */
|
||||
|
||||
261
arch/arm/arm-v7m/cortex-m3/iccarm/port_c.c
Normal file
261
arch/arm/arm-v7m/cortex-m3/iccarm/port_c.c
Normal file
@@ -0,0 +1,261 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Tencent is pleased to support the open source community by making TencentOS
|
||||
* available.
|
||||
*
|
||||
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
|
||||
* If you have downloaded a copy of the TencentOS binary from Tencent, please
|
||||
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
|
||||
*
|
||||
* If you have downloaded a copy of the TencentOS source code from Tencent,
|
||||
* please note that TencentOS source code is licensed under the BSD 3-Clause
|
||||
* License, except for the third-party components listed below which are
|
||||
* subject to different license terms. Your integration of TencentOS into your
|
||||
* own projects may require compliance with the BSD 3-Clause License, as well
|
||||
* as the other licenses applicable to the third-party components included
|
||||
* within TencentOS.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* 'Software'), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "tos_k.h"
|
||||
#include "core_cm3.h"
|
||||
|
||||
__PORT__ void port_cpu_reset(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
|
||||
{
|
||||
(void)SysTick_Config(cycle_per_tick);
|
||||
}
|
||||
|
||||
__PORT__ void port_systick_priority_set(uint32_t prio)
|
||||
{
|
||||
NVIC_SetPriority(SysTick_IRQn, prio);
|
||||
}
|
||||
|
||||
#if TOS_CFG_TICKLESS_EN > 0u
|
||||
|
||||
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
|
||||
{
|
||||
k_time_t max_millisecond;
|
||||
uint32_t max_cycle;
|
||||
|
||||
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
|
||||
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
|
||||
return max_millisecond;
|
||||
}
|
||||
|
||||
__PORT__ void port_systick_resume(void)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
__PORT__ void port_systick_suspend(void)
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
|
||||
{
|
||||
return SysTick_LOAD_RELOAD_Msk;
|
||||
}
|
||||
|
||||
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
|
||||
{
|
||||
port_systick_config(cycle_per_tick);
|
||||
}
|
||||
|
||||
__PORT__ void port_systick_pending_reset(void)
|
||||
{
|
||||
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if TOS_CFG_PWR_MGR_EN > 0u
|
||||
|
||||
__PORT__ void port_sleep_mode_enter(void)
|
||||
{
|
||||
#if 1
|
||||
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
|
||||
#else
|
||||
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
|
||||
#endif
|
||||
}
|
||||
|
||||
__PORT__ void port_stop_mode_enter(void)
|
||||
{
|
||||
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
|
||||
}
|
||||
|
||||
__PORT__ void port_standby_mode_enter(void)
|
||||
{
|
||||
HAL_PWR_EnterSTANDBYMode();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
|
||||
__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
|
||||
{
|
||||
k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
|
||||
|
||||
if (regs->hfsr.bits.VECTBL) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
|
||||
}
|
||||
if (regs->hfsr.bits.FORCED) {
|
||||
/* Memory Management Fault */
|
||||
if (regs->cfsr.part.mfsr.value) {
|
||||
if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
|
||||
}
|
||||
if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
|
||||
}
|
||||
if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
|
||||
}
|
||||
if (regs->cfsr.part.mfsr.bits.MSTKERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
|
||||
}
|
||||
|
||||
if (regs->cfsr.part.mfsr.bits.MLSPERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
|
||||
}
|
||||
|
||||
if (regs->cfsr.part.mfsr.bits.MMARVALID) {
|
||||
if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Bus Fault */
|
||||
if (regs->cfsr.part.bfsr.value) {
|
||||
if (regs->cfsr.part.bfsr.bits.IBUSERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
|
||||
}
|
||||
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
|
||||
}
|
||||
if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
|
||||
}
|
||||
if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
|
||||
}
|
||||
if (regs->cfsr.part.bfsr.bits.STKERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
|
||||
}
|
||||
|
||||
if (regs->cfsr.part.bfsr.bits.LSPERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
|
||||
}
|
||||
|
||||
if (regs->cfsr.part.bfsr.bits.BFARVALID) {
|
||||
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
/* Usage Fault */
|
||||
if (regs->cfsr.part.ufsr.value) {
|
||||
if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
|
||||
}
|
||||
if (regs->cfsr.part.ufsr.bits.INVSTATE) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
|
||||
}
|
||||
if (regs->cfsr.part.ufsr.bits.INVPC) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
|
||||
}
|
||||
if (regs->cfsr.part.ufsr.bits.NOCP) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
|
||||
}
|
||||
if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
|
||||
}
|
||||
if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Debug Fault */
|
||||
if (regs->hfsr.bits.DEBUGEVT) {
|
||||
if (regs->dfsr.value) {
|
||||
if (regs->dfsr.bits.HALTED) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
|
||||
}
|
||||
if (regs->dfsr.bits.BKPT) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
|
||||
}
|
||||
if (regs->dfsr.bits.DWTTRAP) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
|
||||
}
|
||||
if (regs->dfsr.bits.VCATCH) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
|
||||
}
|
||||
if (regs->dfsr.bits.EXTERNAL) {
|
||||
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
__PORT__ void port_fault_diagnosis(void)
|
||||
{
|
||||
port_fault_regs_t regs;
|
||||
|
||||
regs.syshndctrl.value = SCB->SHCSR;
|
||||
regs.cfsr.value = SCB->CFSR;
|
||||
regs.mmar = SCB->MMFAR;
|
||||
regs.bfar = SCB->BFAR;
|
||||
regs.hfsr.value = SCB->HFSR;
|
||||
regs.dfsr.value = SCB->DFSR;
|
||||
regs.afsr = SCB->AFSR;
|
||||
|
||||
port_fault_do_diagnosis(®s);
|
||||
}
|
||||
|
||||
__PORT__ void __NAKED__ HardFault_Handler(void)
|
||||
{
|
||||
__ASM__ __VOLATILE__ (
|
||||
"MOV r0, lr\n\t"
|
||||
"TST lr, #0x04\n\t"
|
||||
"ITE EQ\n\t"
|
||||
"MRSEQ r1, MSP\n\t"
|
||||
"MRSNE r1, PSP\n\t"
|
||||
"LDR r2, =fault_backtrace\n\t"
|
||||
"BX r2\n\t"
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
|
||||
|
||||
36
arch/arm/arm-v7m/cortex-m3/iccarm/port_config.h
Normal file
36
arch/arm/arm-v7m/cortex-m3/iccarm/port_config.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Tencent is pleased to support the open source community by making TencentOS
|
||||
* available.
|
||||
*
|
||||
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
|
||||
* If you have downloaded a copy of the TencentOS binary from Tencent, please
|
||||
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
|
||||
*
|
||||
* If you have downloaded a copy of the TencentOS source code from Tencent,
|
||||
* please note that TencentOS source code is licensed under the BSD 3-Clause
|
||||
* License, except for the third-party components listed below which are
|
||||
* subject to different license terms. Your integration of TencentOS into your
|
||||
* own projects may require compliance with the BSD 3-Clause License, as well
|
||||
* as the other licenses applicable to the third-party components included
|
||||
* within TencentOS.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _PORT_CONFIG_H_
|
||||
#define _PORT_CONFIG_H_
|
||||
|
||||
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
|
||||
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
|
||||
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
|
||||
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
|
||||
#define TOS_CFG_CPU_HRTIMER_EN 0u
|
||||
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 1u
|
||||
#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN
|
||||
|
||||
#ifndef __ARMVFP__
|
||||
#define TOS_CFG_CPU_ARM_FPU_EN 0u
|
||||
#else
|
||||
#define TOS_CFG_CPU_ARM_FPU_EN 1u
|
||||
#endif
|
||||
|
||||
#endif /* _PORT_CONFIG_H_ */
|
||||
|
||||
176
arch/arm/arm-v7m/cortex-m3/iccarm/port_s.S
Normal file
176
arch/arm/arm-v7m/cortex-m3/iccarm/port_s.S
Normal file
@@ -0,0 +1,176 @@
|
||||
PUBLIC port_int_disable
|
||||
PUBLIC port_int_enable
|
||||
|
||||
PUBLIC port_cpsr_save
|
||||
PUBLIC port_cpsr_restore
|
||||
|
||||
PUBLIC port_sched_start
|
||||
PUBLIC port_context_switch
|
||||
PUBLIC port_irq_context_switch
|
||||
|
||||
PUBLIC port_clz
|
||||
|
||||
PUBLIC PendSV_Handler
|
||||
|
||||
EXTERN k_curr_task
|
||||
EXTERN k_next_task
|
||||
|
||||
SCB_VTOR EQU 0xE000ED08
|
||||
NVIC_INT_CTRL EQU 0xE000ED04
|
||||
NVIC_SYSPRI14 EQU 0xE000ED22
|
||||
NVIC_PENDSV_PRI EQU 0xFF
|
||||
NVIC_PENDSVSET EQU 0x10000000
|
||||
|
||||
|
||||
RSEG CODE:CODE:NOROOT(2)
|
||||
THUMB
|
||||
|
||||
|
||||
port_int_disable
|
||||
CPSID I
|
||||
BX LR
|
||||
|
||||
|
||||
port_int_enable
|
||||
CPSIE I
|
||||
BX LR
|
||||
|
||||
|
||||
port_cpsr_save
|
||||
MRS R0, PRIMASK
|
||||
CPSID I
|
||||
BX LR
|
||||
|
||||
|
||||
port_cpsr_restore
|
||||
MSR PRIMASK, R0
|
||||
BX LR
|
||||
|
||||
|
||||
port_clz
|
||||
CLZ R0, R0
|
||||
BX LR
|
||||
|
||||
|
||||
port_sched_start
|
||||
CPSID I
|
||||
|
||||
; set pendsv priority lowest
|
||||
; otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
|
||||
; that would be a disaster
|
||||
MOV32 R0, NVIC_SYSPRI14
|
||||
MOV32 R1, NVIC_PENDSV_PRI
|
||||
STRB R1, [R0]
|
||||
|
||||
LDR R0, =SCB_VTOR
|
||||
LDR R0, [R0]
|
||||
LDR R0, [R0]
|
||||
MSR MSP, R0
|
||||
|
||||
; k_curr_task = k_next_task
|
||||
MOV32 R0, k_curr_task
|
||||
MOV32 R1, k_next_task
|
||||
LDR R2, [R1]
|
||||
STR R2, [R0]
|
||||
|
||||
; sp = k_next_task->sp
|
||||
LDR R0, [R2]
|
||||
; PSP = sp
|
||||
MSR PSP, R0
|
||||
|
||||
; using PSP
|
||||
MRS R0, CONTROL
|
||||
ORR R0, R0, #2
|
||||
MSR CONTROL, R0
|
||||
|
||||
ISB
|
||||
|
||||
; restore r4-11 from new process stack
|
||||
LDMFD SP!, {R4 - R11}
|
||||
|
||||
#if defined(__ARMVFP__)
|
||||
; ignore EXC_RETURN the first switch
|
||||
LDMFD SP!, {R0}
|
||||
#endif
|
||||
|
||||
; restore r0, r3
|
||||
LDMFD SP!, {R0 - R3}
|
||||
; load R12 and LR
|
||||
LDMFD SP!, {R12, LR}
|
||||
; load PC and discard xPSR
|
||||
LDMFD SP!, {R1, R2}
|
||||
|
||||
CPSIE I
|
||||
BX R1
|
||||
|
||||
|
||||
port_context_switch
|
||||
LDR R0, =NVIC_INT_CTRL
|
||||
LDR R1, =NVIC_PENDSVSET
|
||||
STR R1, [R0]
|
||||
BX LR
|
||||
|
||||
|
||||
port_irq_context_switch
|
||||
LDR R0, =NVIC_INT_CTRL
|
||||
LDR R1, =NVIC_PENDSVSET
|
||||
STR R1, [R0]
|
||||
BX LR
|
||||
|
||||
|
||||
PendSV_Handler
|
||||
CPSID I
|
||||
MRS R0, PSP
|
||||
|
||||
_context_save
|
||||
; R0-R3, R12, LR, PC, xPSR is saved automatically here
|
||||
#if defined(__ARMVFP__)
|
||||
; is it extended frame?
|
||||
TST LR, #0x10
|
||||
IT EQ
|
||||
VSTMDBEQ R0!, {S16 - S31}
|
||||
; S0 - S16, FPSCR saved automatically here
|
||||
|
||||
; save EXC_RETURN
|
||||
STMFD R0!, {LR}
|
||||
#endif
|
||||
|
||||
; save remaining regs r4-11 on process stack
|
||||
STMFD R0!, {R4 - R11}
|
||||
|
||||
; k_curr_task->sp = PSP
|
||||
MOV32 R5, k_curr_task
|
||||
LDR R6, [R5]
|
||||
; R0 is SP of process being switched out
|
||||
STR R0, [R6]
|
||||
|
||||
_context_restore
|
||||
; k_curr_task = k_next_task
|
||||
MOV32 R1, k_next_task
|
||||
LDR R2, [R1]
|
||||
STR R2, [R5]
|
||||
|
||||
; R0 = k_next_task->sp
|
||||
LDR R0, [R2]
|
||||
|
||||
; restore R4 - R11
|
||||
LDMFD R0!, {R4 - R11}
|
||||
|
||||
#if defined(__ARMVFP__)
|
||||
; restore EXC_RETURN
|
||||
LDMFD R0!, {LR}
|
||||
; is it extended frame?
|
||||
TST LR, #0x10
|
||||
IT EQ
|
||||
VLDMIAEQ R0!, {S16 - S31}
|
||||
#endif
|
||||
|
||||
; Load PSP with new process SP
|
||||
MSR PSP, R0
|
||||
CPSIE I
|
||||
; R0-R3, R12, LR, PC, xPSR restored automatically here
|
||||
; S0 - S16, FPSCR restored automatically here if FPCA = 1
|
||||
BX LR
|
||||
|
||||
END
|
||||
|
||||
Reference in New Issue
Block a user