diff --git a/board/Sipeed_LonganNano/BSP/Hardware/lcd/lcd.c b/board/Sipeed_LonganNano/BSP/Hardware/lcd/lcd.c
index f8b58a23..fb308a59 100644
--- a/board/Sipeed_LonganNano/BSP/Hardware/lcd/lcd.c
+++ b/board/Sipeed_LonganNano/BSP/Hardware/lcd/lcd.c
@@ -305,11 +305,11 @@ void LCD_Init(void)
rcu_periph_clock_enable(RCU_GPIOB);
#if USE_HARDWARE_SPI
- rcu_periph_clock_enable(RCU_AF);
+ rcu_periph_clock_enable(RCU_AF);
rcu_periph_clock_enable(RCU_SPI0);
/* SPI0 GPIO config: NSS/PA4, SCK/PA5, MOSI/PA7 */
- gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 |GPIO_PIN_6| GPIO_PIN_7);
- gpio_init(GPIOB, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
+ gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7);
+ //gpio_init(GPIOB, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
spi_config();
#endif
diff --git a/board/Sipeed_LonganNano/eclipse/nRF24L01/.cproject b/board/Sipeed_LonganNano/eclipse/nRF24L01/.cproject
new file mode 100644
index 00000000..c9f0361d
--- /dev/null
+++ b/board/Sipeed_LonganNano/eclipse/nRF24L01/.cproject
@@ -0,0 +1,440 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/board/Sipeed_LonganNano/eclipse/nRF24L01/.gitignore b/board/Sipeed_LonganNano/eclipse/nRF24L01/.gitignore
new file mode 100644
index 00000000..3df573fe
--- /dev/null
+++ b/board/Sipeed_LonganNano/eclipse/nRF24L01/.gitignore
@@ -0,0 +1 @@
+/Debug/
diff --git a/board/Sipeed_LonganNano/eclipse/nRF24L01/.project b/board/Sipeed_LonganNano/eclipse/nRF24L01/.project
new file mode 100644
index 00000000..9b7ff94d
--- /dev/null
+++ b/board/Sipeed_LonganNano/eclipse/nRF24L01/.project
@@ -0,0 +1,99 @@
+
+
+ nRF24L01
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
+ Application
+ 2
+ virtual:/virtual
+
+
+ GD32VF103_Firmware_Library
+ 2
+ $%7BPARENT-4-PROJECT_LOC%7D/platform/vendor_bsp/gd/GD32VF103_Firmware_Library
+
+
+ TencentOS_tiny
+ 2
+ virtual:/virtual
+
+
+ Application/Hardware
+ 2
+ $%7BPARENT-2-PROJECT_LOC%7D/BSP/Hardware
+
+
+ Application/Inc
+ 2
+ $%7BPARENT-2-PROJECT_LOC%7D/BSP/Inc
+
+
+ Application/Src
+ 2
+ $%7BPARENT-2-PROJECT_LOC%7D/BSP/Src
+
+
+ Application/tos_config.h
+ 1
+ $%7BPARENT-2-PROJECT_LOC%7D/TOS_CONFIG/tos_config.h
+
+
+ TencentOS_tiny/arch
+ 2
+ virtual:/virtual
+
+
+ TencentOS_tiny/kernel
+ 2
+ $%7BPARENT-4-PROJECT_LOC%7D/kernel
+
+
+ TencentOS_tiny/arch/risc-v
+ 2
+ virtual:/virtual
+
+
+ TencentOS_tiny/arch/risc-v/bumblebee
+ 2
+ TOP_DIR/arch/risc-v/bumblebee/gcc
+
+
+ TencentOS_tiny/arch/risc-v/common
+ 2
+ $%7BPARENT-4-PROJECT_LOC%7D/arch/risc-v/common
+
+
+ TencentOS_tiny/arch/risc-v/rv32i
+ 2
+ TOP_DIR/arch/risc-v/rv32i/gcc
+
+
+
+
+ TOP_DIR
+ $%7BPARENT-4-PROJECT_LOC%7D
+
+
+
diff --git a/board/Sipeed_LonganNano/eclipse/nRF24L01/gd32vf103_libopt.h b/board/Sipeed_LonganNano/eclipse/nRF24L01/gd32vf103_libopt.h
new file mode 100644
index 00000000..c07eaa8c
--- /dev/null
+++ b/board/Sipeed_LonganNano/eclipse/nRF24L01/gd32vf103_libopt.h
@@ -0,0 +1,61 @@
+/*!
+ \file gd32vf103_libopt.h
+ \brief library optional for gd32vf103
+
+ \version 2019-6-5, V1.0.0, demo for GD32VF103
+*/
+
+/*
+ Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_LIBOPT_H
+#define GD32VF103_LIBOPT_H
+
+#include "gd32vf103_adc.h"
+#include "gd32vf103_bkp.h"
+#include "gd32vf103_can.h"
+#include "gd32vf103_crc.h"
+#include "gd32vf103_dac.h"
+#include "gd32vf103_dma.h"
+#include "gd32vf103_eclic.h"
+#include "gd32vf103_exmc.h"
+#include "gd32vf103_exti.h"
+#include "gd32vf103_fmc.h"
+#include "gd32vf103_gpio.h"
+#include "gd32vf103_i2c.h"
+#include "gd32vf103_fwdgt.h"
+#include "gd32vf103_dbg.h"
+#include "gd32vf103_pmu.h"
+#include "gd32vf103_rcu.h"
+#include "gd32vf103_rtc.h"
+#include "gd32vf103_spi.h"
+#include "gd32vf103_timer.h"
+#include "gd32vf103_usart.h"
+#include "gd32vf103_wwdgt.h"
+#include "n200_func.h"
+
+#endif /* GD32VF103_LIBOPT_H */
diff --git a/board/Sipeed_LonganNano/eclipse/nRF24L01/link.lds b/board/Sipeed_LonganNano/eclipse/nRF24L01/link.lds
new file mode 100644
index 00000000..1c32e640
--- /dev/null
+++ b/board/Sipeed_LonganNano/eclipse/nRF24L01/link.lds
@@ -0,0 +1,175 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
+ ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
+*/
+}
+
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+
+ .init :
+ {
+ KEEP (*(SORT_NONE(.init)))
+ } >flash AT>flash
+
+ .ilalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _ilm_lma = . );
+ } >flash AT>flash
+
+ .ialign :
+ {
+ PROVIDE( _ilm = . );
+ } >flash AT>flash
+
+ .text :
+ {
+ *(.rodata .rodata.*)
+ *(.text.unlikely .text.unlikely.*)
+ *(.text.startup .text.startup.*)
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >flash AT>flash
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ } >flash AT>flash
+
+ . = ALIGN(4);
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);/*0x80022c8*/
+ PROVIDE (etext = .);/*0x80022c8*/
+ PROVIDE( _eilm = . );
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >flash AT>flash
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >flash AT>flash
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >flash AT>flash
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >flash AT>flash
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >flash AT>flash
+
+ . = ALIGN(4);
+ PROVIDE( _eilm = . );
+
+ .lalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data_lma = . );
+ } >flash AT>flash
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data = . );
+ } >ram AT>flash
+
+
+ .data :
+ {
+ *(.rdata)
+
+ *(.gnu.linkonce.r.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800);
+ *(.sdata .sdata.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ } >ram AT>flash
+
+ . = ALIGN(4);
+ PROVIDE( _edata = . );
+ PROVIDE( edata = . );
+
+ PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/
+ PROVIDE( __bss_start = . );
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >ram AT>ram
+
+ . = ALIGN(8);
+ PROVIDE( _end = . ); /*0X2000,0340*/
+ PROVIDE( end = . );
+
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
+}
diff --git a/board/Sipeed_LonganNano/eclipse/nRF24L01/main.c b/board/Sipeed_LonganNano/eclipse/nRF24L01/main.c
new file mode 100644
index 00000000..4903c463
--- /dev/null
+++ b/board/Sipeed_LonganNano/eclipse/nRF24L01/main.c
@@ -0,0 +1,120 @@
+#include "mcu_init.h"
+#include "tos_k.h"
+#include "lcd.h"
+#include "nrf24.h"
+
+#define TASK_SIZE 1024
+
+
+ k_task_t task1_handle;
+ k_task_t task2_handle;
+ k_task_t led_handle;
+
+uint8_t task1_stk[TASK_SIZE];
+uint8_t task2_stk[TASK_SIZE];
+uint8_t led_stk[TASK_SIZE/2];
+
+int share = 0xCBA7F9;
+k_sem_t sem;
+
+typedef struct {
+ int port;
+ int pin;
+} Led_t;
+
+Led_t leds[] = {
+ { LEDR_GPIO_PORT, LEDR_PIN },
+ { LEDG_GPIO_PORT, LEDG_PIN },
+ { LEDB_GPIO_PORT, LEDB_PIN }
+};
+
+
+void task1(void *arg)
+{
+ int task_cnt1 = 0;
+ while (1) {
+ printf("hello world from %s cnt: %d\n", __func__, task_cnt1++);
+
+ for(int i=0; i= 6 || pipe >= 6) {
+ return -1;
+ }
+
+ if(pipe >= 2) {
+ addrlen = 1;
+ }
+
+ uint8_t reg = REG_RX_ADDR_P0 + pipe;
+
+
+ return nrf_hal_write_reg(reg, addr, addrlen);
+}
+
+int nrf_set_txaddr(uint8_t *addr, uint8_t addrlen) {
+ if(addrlen >= 6) {
+ return -1;
+ }
+ return nrf_hal_write_reg(REG_TX_ADDR, addr, addrlen);
+}
+
+int nrf_enable_rxaddr(uint8_t pipe) {
+ if(pipe >= 6) {
+ return -1;
+ }
+
+ nrf_hal_write_reg_byte(REG_EN_RXADDR, pipe);
+ return 0;
+}
+
+void nrf_reset_registers() {
+ nrf_hal_write_reg_byte(REG_CONFIG, _BV(EN_CRC));
+ nrf_hal_write_reg_byte(REG_EN_AA, _BV(ENAA_P0) | _BV(ENAA_P1) | _BV(ENAA_P2) | _BV(ENAA_P3) | _BV(ENAA_P4) | _BV(ENAA_P5));
+ nrf_hal_write_reg_byte(REG_EN_RXADDR, _BV(ERX_P0) | _BV(ERX_P1));
+ nrf_hal_write_reg_byte(REG_SETUP_AW, _VV(AW_5BYTES, AW));
+ nrf_hal_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC));
+ nrf_hal_write_reg_byte(REG_RF_CH, 0b00000010);
+ nrf_hal_write_reg_byte(REG_RF_SETUP, _BV(RF_DR_HIGH) | _VV(RF_PWR_0dBm, RF_PWR));
+
+ uint8_t status = 0;
+ nrf_hal_read_reg_byte(REG_STATUS, &status);
+ if(status & _BV(RX_DR)) {
+ nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR));
+ }
+ if(status & _BV(TX_DS)) {
+ nrf_hal_set_reg_bit(REG_STATUS, _BV(TX_DS));
+ }
+ if(status & _BV(MAX_RT)) {
+ nrf_hal_set_reg_bit(REG_STATUS, _BV(MAX_RT));
+ }
+
+ nrf_hal_write_reg_byte(REG_RX_PW_P0, 0);
+ nrf_hal_write_reg_byte(REG_RX_PW_P1, 0);
+ nrf_hal_write_reg_byte(REG_RX_PW_P2, 0);
+ nrf_hal_write_reg_byte(REG_RX_PW_P3, 0);
+ nrf_hal_write_reg_byte(REG_RX_PW_P4, 0);
+ nrf_hal_write_reg_byte(REG_RX_PW_P5, 0);
+ nrf_hal_write_reg_byte(REG_DYNPD, 0);
+ nrf_hal_write_reg_byte(REG_FEATURE, 0);
+
+ uint8_t addrp0[] = {0xE7, 0xE7, 0xE7, 0xE7, 0xE7};
+ uint8_t addrp1[] = {0xC2, 0xC2, 0xC2, 0xC2, 0xC2};
+ nrf_hal_write_reg(REG_TX_ADDR, addrp0, 5);
+ nrf_hal_write_reg(REG_RX_ADDR_P0, addrp0, 5);
+ nrf_hal_write_reg(REG_RX_ADDR_P1, addrp1, 5);
+ nrf_hal_write_reg_byte(REG_RX_ADDR_P2, 0xC3);
+ nrf_hal_write_reg_byte(REG_RX_ADDR_P3, 0xC4);
+ nrf_hal_write_reg_byte(REG_RX_ADDR_P4, 0xC5);
+ nrf_hal_write_reg_byte(REG_RX_ADDR_P5, 0xC6);
+
+ nrf_flush_rx();
+ nrf_flush_tx();
+}
+
+void nrf_set_standby_mode() {
+ nrf_hal_ce(0);
+ nrf_powerdown();
+ nrf_reset_registers();
+ nrf_delay(10);
+
+ nrf_powerup();
+ nrf_delay(10); // 10m > 1.5~2ms
+}
+
+
+
+void nrf_set_receive_mode() {
+ nrf_hal_set_reg_bit(REG_CONFIG, PRIM_RX);
+
+ nrf_hal_ce(1);
+
+ nrf_delay(1); // 1ms > 120~130us
+}
+
+void nrf_set_send_mode() {
+ nrf_hal_clear_reg_bit(REG_CONFIG, PRIM_RX);
+
+ nrf_hal_ce(1);
+
+ nrf_delay(1); // 1ms > 120~130us
+}
+
+void nrf_enable_autoack(uint8_t pipe) {
+ if(pipe >= 6) {
+ return ;
+ }
+
+ nrf_hal_set_reg_bit(REG_EN_AA, pipe);
+}
+
+void nrf_disable_autoack(uint8_t pipe) {
+ if(pipe >= 6) {
+ return ;
+ }
+
+ nrf_hal_clear_reg_bit(REG_EN_AA, pipe);
+}
+
+
+void nrf_set_datarate(uint8_t dr) {
+
+ if(NRF_1Mbps == dr) {
+ dr = 0;
+ } else if(NRF_2Mbps == dr) {
+ nrf_hal_write_reg_byte(REG_RF_SETUP, 0b00001110);
+ nrf_hal_write_reg_byte(REG_SETUP_RETR, 0b00010011);
+ } else {
+
+ }
+
+}
+
+
+int nrf_enable_dynamic_payload(uint8_t pipe) {
+ if(pipe >= 6) {
+ return -1;
+ }
+
+ uint8_t feature = 0;
+ uint8_t dynpd = 0;
+
+ nrf_hal_read_reg_byte(REG_FEATURE, &feature);
+ nrf_hal_read_reg_byte(REG_DYNPD, &dynpd);
+
+ feature |= _BV(EN_DPL);
+ dynpd |= _BV(pipe);
+
+ nrf_hal_write_reg_byte(REG_DYNPD, dynpd);
+ nrf_hal_write_reg_byte(REG_FEATURE, feature);
+
+ return 0;
+}
+
+
+int nrf_read_payload(uint8_t *buf, uint8_t *len) {
+
+ nrf_hal_cmd_read_byte(CMD_R_RX_PL_WID, len);
+
+ nrf_hal_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
+
+ return 0;
+}
+
+int nrf_write_payload(uint8_t *buf, uint8_t len) {
+ return nrf_hal_cmd_write(CMD_W_TX_PAYLOAD_NOACK, buf, len);
+}
+
+void print_addr(uint8_t pipe) {
+ uint8_t addr[5];
+ nrf_hal_read_reg(REG_RX_ADDR_P0+pipe, addr, 5);
+
+ printf("pipe %u addr: ", pipe);
+ for(int i=0; i<5; i++) {
+ printf("%u ", addr[i]);
+ }
+ printf("\n");
+}
+
+uint8_t nrf_received_data = 0;
+uint8_t nrf_hal_test_rx() {
+
+ uint8_t data = 0;
+
+ nrf_delay(200);
+
+ nrf_hal_csn(1);
+ nrf_hal_ce(0);
+
+ nrf_delay(200);
+
+
+ nrf_set_standby_mode();
+
+ nrf_set_receive_mode();
+ nrf_disable_rx_irq();
+
+
+ nrf_set_rf_channel(64);
+ nrf_set_datarate(NRF_2Mbps);
+ uint8_t rxaddr[] = { 1, 2, 3, 4, 1 };
+ uint8_t txaddr[] = { 1, 2, 3, 4, 2 };
+ nrf_set_rxaddr(0, rxaddr, 5);
+ nrf_set_txaddr(txaddr, 5);
+
+ nrf_enable_dynamic_payload(0);
+ nrf_enable_dynamic_payload(1);
+
+ nrf_enable_rxaddr(0);
+ nrf_enable_rxaddr(1);
+
+ print_addr(0);
+ print_addr(1);
+ print_addr(2);
+
+
+ nrf_flush_rx();
+ while(1) {
+ uint8_t buf[32];
+ uint8_t len = 0;
+ uint8_t status = 0;
+ nrf_hal_read_reg_byte(REG_STATUS, &status);
+ nrf_read_payload(buf, &len);
+
+ if(status & _BV(RX_DR)) {
+ nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR));
+ nrf_flush_rx();
+
+ if(len > 0) {
+ uint8_t pipe = status;
+ pipe >>= 1;
+ pipe &= 0x07;
+ printf("received %u bytes from pipe %u: ", len, pipe);
+ if(pipe >= 6) {
+ printf("\n");
+ continue;
+ }
+ for(int i=0; i