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detach nrf24l01 hal from nrf24l01

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This commit is contained in:
acevest
2020-04-02 16:20:26 +08:00
parent 019b69f592
commit 602ad7d308
6 changed files with 255 additions and 182 deletions
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1
board/TencentOS_tiny_EVB_MX/STM32CubeIDE/nRF24L01/Src/main.c
View File

@@ -69,7 +69,6 @@ void task2(void *arg)
{
int task_cnt2 = 0;
tos_task_delay(200);
nrf_init();
nrf_hal_test();
while (1) {
task_cnt2--;

250
board/TencentOS_tiny_EVB_MX/STM32CubeIDE/nRF24L01/Src/nrf24l01.c
View File

@@ -9,121 +9,17 @@
#include "nrf24l01.h"
#include "tos_k.h"
extern SPI_HandleTypeDef hspi1;
static SPI_HandleTypeDef *spi;
void nrf_init() {
spi = &hspi1;
}
void nrf_csn(uint8_t mode) {
HAL_GPIO_WritePin(CSN_GPIO_Port, CSN_Pin, mode == 0 ? GPIO_PIN_RESET : GPIO_PIN_SET);
}
void nrf_ce(uint8_t mode) {
HAL_GPIO_WritePin(CE_GPIO_Port, CE_Pin, mode == 0 ? GPIO_PIN_RESET : GPIO_PIN_SET);
}
int _nrf_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) {
uint8_t cmd = CMD_R_REGISTER | reg;
nrf_csn(0);
if(HAL_OK != HAL_SPI_Transmit(spi, &cmd, 1, HAL_MAX_DELAY)) {
return -1;
}
if(HAL_OK != HAL_SPI_Receive(spi, buf, len, HAL_MAX_DELAY)){
return -1;
}
nrf_csn(1);
return 0;
}
uint8_t _nrf_read_reg_byte(uint8_t reg, uint8_t *v) {
return _nrf_read_reg(reg, v, 1);
}
int _nrf_write_reg(uint8_t reg, uint8_t *buf, uint8_t len)
{
uint8_t cmd = CMD_W_REGISTER | reg;
nrf_csn(0);
if(HAL_OK != HAL_SPI_Transmit(spi, &cmd, 1, HAL_MAX_DELAY)) {
return -1;
}
if(HAL_OK != HAL_SPI_Transmit(spi, buf, len, HAL_MAX_DELAY)) {
return -1;
}
nrf_csn(1);
return 0;
}
int _nrf_write_reg_byte(uint8_t reg, uint8_t byte)
{
return _nrf_write_reg(reg, &byte, 1);
}
void _nrf_set_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
_nrf_read_reg_byte(reg, &v);
v |= _BV(bit);
_nrf_write_reg_byte(reg, v);
}
void _nrf_clear_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
_nrf_read_reg_byte(reg, &v);
v &= ~_BV(bit);
_nrf_write_reg_byte(reg, v);
}
int _nrf_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len) {
nrf_csn(0);
HAL_SPI_Transmit(spi, &cmd, 1, HAL_MAX_DELAY);
HAL_SPI_Receive(spi, data, len, HAL_MAX_DELAY);
nrf_csn(1);
return 0;
}
int _nrf_cmd_read_byte(uint8_t cmd, uint8_t *data) {
return _nrf_cmd_read(cmd, data, 1);
}
void _nrf_write_cmd(uint8_t cmd) {
nrf_csn(0);
HAL_SPI_Transmit(spi, &cmd, 1, HAL_MAX_DELAY);
nrf_csn(1);
int nrf_init(SPI_HandleTypeDef* spi, GPIO_TypeDef* csn_gpio_port, uint16_t csn_pin, GPIO_TypeDef* ce_gpio_port, uint16_t ce_pin) {
return nrf_hal_init(spi, csn_gpio_port, csn_pin, ce_gpio_port, ce_pin);
}
void nrf_flush_rx() {
_nrf_write_cmd(CMD_FLUSH_RX);
nrf_hal_write_cmd(CMD_FLUSH_RX);
}
void nrf_flush_tx() {
_nrf_write_cmd(CMD_FLUSH_TX);
nrf_hal_write_cmd(CMD_FLUSH_TX);
}
@@ -132,41 +28,41 @@ void nrf_delay(uint32_t delay) {
}
void nrf_powerup() {
_nrf_set_reg_bit(REG_CONFIG, PWR_UP);
int nrf_powerup() {
return nrf_hal_set_reg_bit(REG_CONFIG, PWR_UP);
}
void nrf_powerdown() {
_nrf_clear_reg_bit(REG_CONFIG, PWR_UP);
int nrf_powerdown() {
return nrf_hal_clear_reg_bit(REG_CONFIG, PWR_UP);
}
void nrf_enable_rx_irq() {
_nrf_clear_reg_bit(REG_CONFIG, MASK_RX_DR);
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_RX_DR);
}
void nrf_disable_rx_irq() {
_nrf_set_reg_bit(REG_CONFIG, MASK_RX_DR);
nrf_hal_set_reg_bit(REG_CONFIG, MASK_RX_DR);
}
void nrf_enable_tx_irq() {
_nrf_clear_reg_bit(REG_CONFIG, MASK_TX_DS);
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_TX_DS);
}
void nrf_disable_tx_irq() {
_nrf_set_reg_bit(REG_CONFIG, MASK_TX_DS);
nrf_hal_set_reg_bit(REG_CONFIG, MASK_TX_DS);
}
void nrf_enable_max_rt_irq() {
_nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
}
void nrf_disable_max_rt_irq() {
_nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
}
void nrf_set_rf_channel(uint8_t channel) {
channel &= 0x7F;
_nrf_write_reg_byte(REG_RF_CH, channel);
nrf_hal_write_reg_byte(REG_RF_CH, channel);
}
int nrf_set_rxaddr(uint8_t pipe, uint8_t *addr, uint8_t addrlen) {
@@ -181,14 +77,14 @@ int nrf_set_rxaddr(uint8_t pipe, uint8_t *addr, uint8_t addrlen) {
uint8_t reg = REG_RX_ADDR_P0 + pipe;
return _nrf_write_reg(reg, addr, addrlen);
return nrf_hal_write_reg(reg, addr, addrlen);
}
int nrf_set_txaddr(uint8_t *addr, uint8_t addrlen) {
if(addrlen >= 6) {
return -1;
}
return _nrf_write_reg(REG_TX_ADDR, addr, addrlen);
return nrf_hal_write_reg(REG_TX_ADDR, addr, addrlen);
}
int nrf_enable_rxaddr(uint8_t pipe) {
@@ -196,56 +92,56 @@ int nrf_enable_rxaddr(uint8_t pipe) {
return -1;
}
_nrf_write_reg_byte(REG_EN_RXADDR, pipe);
nrf_hal_write_reg_byte(REG_EN_RXADDR, pipe);
return 0;
}
void nrf_reset_registers() {
_nrf_write_reg_byte(REG_CONFIG, _BV(EN_CRC));
_nrf_write_reg_byte(REG_EN_AA, _BV(ENAA_P0) | _BV(ENAA_P1) | _BV(ENAA_P2) | _BV(ENAA_P3) | _BV(ENAA_P4) | _BV(ENAA_P5));
_nrf_write_reg_byte(REG_EN_RXADDR, _BV(ERX_P0) | _BV(ERX_P1));
_nrf_write_reg_byte(REG_SETUP_AW, _VV(AW_5BYTES, AW));
_nrf_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC));
_nrf_write_reg_byte(REG_RF_CH, 0b00000010);
_nrf_write_reg_byte(REG_RF_SETUP, _BV(RF_DR_HIGH) | _VV(RF_PWR_0dBm, RF_PWR));
nrf_hal_write_reg_byte(REG_CONFIG, _BV(EN_CRC));
nrf_hal_write_reg_byte(REG_EN_AA, _BV(ENAA_P0) | _BV(ENAA_P1) | _BV(ENAA_P2) | _BV(ENAA_P3) | _BV(ENAA_P4) | _BV(ENAA_P5));
nrf_hal_write_reg_byte(REG_EN_RXADDR, _BV(ERX_P0) | _BV(ERX_P1));
nrf_hal_write_reg_byte(REG_SETUP_AW, _VV(AW_5BYTES, AW));
nrf_hal_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC));
nrf_hal_write_reg_byte(REG_RF_CH, 0b00000010);
nrf_hal_write_reg_byte(REG_RF_SETUP, _BV(RF_DR_HIGH) | _VV(RF_PWR_0dBm, RF_PWR));
uint8_t status = 0;
_nrf_read_reg_byte(REG_STATUS, &status);
nrf_hal_read_reg_byte(REG_STATUS, &status);
if(status & _BV(RX_DR)) {
_nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR));
}
if(status & _BV(TX_DS)) {
_nrf_set_reg_bit(REG_STATUS, _BV(TX_DS));
nrf_hal_set_reg_bit(REG_STATUS, _BV(TX_DS));
}
if(status & _BV(MAX_RT)) {
_nrf_set_reg_bit(REG_STATUS, _BV(MAX_RT));
nrf_hal_set_reg_bit(REG_STATUS, _BV(MAX_RT));
}
_nrf_write_reg_byte(REG_RX_PW_P0, 0);
_nrf_write_reg_byte(REG_RX_PW_P1, 0);
_nrf_write_reg_byte(REG_RX_PW_P2, 0);
_nrf_write_reg_byte(REG_RX_PW_P3, 0);
_nrf_write_reg_byte(REG_RX_PW_P4, 0);
_nrf_write_reg_byte(REG_RX_PW_P5, 0);
_nrf_write_reg_byte(REG_DYNPD, 0);
_nrf_write_reg_byte(REG_FEATURE, 0);
nrf_hal_write_reg_byte(REG_RX_PW_P0, 0);
nrf_hal_write_reg_byte(REG_RX_PW_P1, 0);
nrf_hal_write_reg_byte(REG_RX_PW_P2, 0);
nrf_hal_write_reg_byte(REG_RX_PW_P3, 0);
nrf_hal_write_reg_byte(REG_RX_PW_P4, 0);
nrf_hal_write_reg_byte(REG_RX_PW_P5, 0);
nrf_hal_write_reg_byte(REG_DYNPD, 0);
nrf_hal_write_reg_byte(REG_FEATURE, 0);
uint8_t addrp0[] = {0xE7, 0xE7, 0xE7, 0xE7, 0xE7};
uint8_t addrp1[] = {0xC2, 0xC2, 0xC2, 0xC2, 0xC2};
_nrf_write_reg(REG_TX_ADDR, addrp0, 5);
_nrf_write_reg(REG_RX_ADDR_P0, addrp0, 5);
_nrf_write_reg(REG_RX_ADDR_P1, addrp1, 5);
_nrf_write_reg_byte(REG_RX_ADDR_P2, 0xC3);
_nrf_write_reg_byte(REG_RX_ADDR_P3, 0xC4);
_nrf_write_reg_byte(REG_RX_ADDR_P4, 0xC5);
_nrf_write_reg_byte(REG_RX_ADDR_P5, 0xC6);
nrf_hal_write_reg(REG_TX_ADDR, addrp0, 5);
nrf_hal_write_reg(REG_RX_ADDR_P0, addrp0, 5);
nrf_hal_write_reg(REG_RX_ADDR_P1, addrp1, 5);
nrf_hal_write_reg_byte(REG_RX_ADDR_P2, 0xC3);
nrf_hal_write_reg_byte(REG_RX_ADDR_P3, 0xC4);
nrf_hal_write_reg_byte(REG_RX_ADDR_P4, 0xC5);
nrf_hal_write_reg_byte(REG_RX_ADDR_P5, 0xC6);
nrf_flush_rx();
nrf_flush_tx();
}
void nrf_set_standby_mode() {
nrf_ce(0);
nrf_hal_ce(0);
nrf_powerdown();
nrf_reset_registers();
nrf_delay(10);
@@ -253,7 +149,7 @@ void nrf_set_standby_mode() {
printf("\n");
for(int i=0; i<=7; i++) {
uint8_t v = 0;
_nrf_read_reg_byte(i, &v);
nrf_hal_read_reg_byte(i, &v);
printf("--reg %u val %x\n", i, v);
}
@@ -265,9 +161,9 @@ void nrf_set_standby_mode() {
void nrf_set_receive_mode() {
_nrf_set_reg_bit(REG_CONFIG, PRIM_RX);
nrf_hal_set_reg_bit(REG_CONFIG, PRIM_RX);
nrf_ce(1);
nrf_hal_ce(1);
nrf_delay(1); // 1ms > 120~130us
}
@@ -277,7 +173,7 @@ void nrf_enable_autoack(uint8_t pipe) {
return ;
}
_nrf_set_reg_bit(REG_EN_AA, pipe);
nrf_hal_set_reg_bit(REG_EN_AA, pipe);
}
void nrf_disable_autoack(uint8_t pipe) {
@@ -285,7 +181,7 @@ void nrf_disable_autoack(uint8_t pipe) {
return ;
}
_nrf_clear_reg_bit(REG_EN_AA, pipe);
nrf_hal_clear_reg_bit(REG_EN_AA, pipe);
}
@@ -294,8 +190,8 @@ void nrf_set_datarate(uint8_t dr) {
if(NRF_1Mbps == dr) {
dr = 0;
} else if(NRF_2Mbps == dr) {
_nrf_write_reg_byte(REG_RF_SETUP, 0b00001110);
_nrf_write_reg_byte(REG_SETUP_RETR, 0b00010011);
nrf_hal_write_reg_byte(REG_RF_SETUP, 0b00001110);
nrf_hal_write_reg_byte(REG_SETUP_RETR, 0b00010011);
} else {
}
@@ -311,14 +207,14 @@ int nrf_enable_dynamic_payload(uint8_t pipe) {
uint8_t feature = 0;
uint8_t dynpd = 0;
_nrf_read_reg_byte(REG_FEATURE, &feature);
_nrf_read_reg_byte(REG_DYNPD, &dynpd);
nrf_hal_read_reg_byte(REG_FEATURE, &feature);
nrf_hal_read_reg_byte(REG_DYNPD, &dynpd);
feature |= _BV(EN_DPL);
dynpd |= _BV(pipe);
_nrf_write_reg_byte(REG_DYNPD, dynpd);
_nrf_write_reg_byte(REG_FEATURE, feature);
nrf_hal_write_reg_byte(REG_DYNPD, dynpd);
nrf_hal_write_reg_byte(REG_FEATURE, feature);
return 0;
}
@@ -326,16 +222,16 @@ int nrf_enable_dynamic_payload(uint8_t pipe) {
int nrf_read_payload(uint8_t *buf, uint8_t *len) {
_nrf_cmd_read_byte(CMD_R_RX_PL_WID, len);
nrf_hal_cmd_read_byte(CMD_R_RX_PL_WID, len);
_nrf_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
nrf_hal_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
return 0;
}
void print_addr(uint8_t pipe) {
uint8_t addr[5];
_nrf_read_reg(REG_RX_ADDR_P0+pipe, addr, 5);
nrf_hal_read_reg(REG_RX_ADDR_P0+pipe, addr, 5);
printf("pipe %u addr: ", pipe);
for(int i=0; i<5; i++) {
@@ -349,20 +245,19 @@ uint8_t nrf_received_data = 0;
uint8_t nrf_hal_test() {
uint8_t data = 0;
nrf_init();
extern SPI_HandleTypeDef hspi1;
nrf_init(&hspi1, CSN_GPIO_Port, CSN_Pin, CE_GPIO_Port, CE_Pin);
#if 1
nrf_delay(200);
nrf_csn(1);
nrf_ce(0);
nrf_hal_csn(1);
nrf_hal_ce(0);
nrf_delay(200);
nrf_set_standby_mode();
nrf_set_receive_mode();
//nrf_disable_rx_irq();
@@ -388,7 +283,7 @@ uint8_t nrf_hal_test() {
printf("\n");
for(int i=0; i<=7; i++) {
uint8_t v = 0;
_nrf_read_reg_byte(i, &v);
nrf_hal_read_reg_byte(i, &v);
printf("reg %u val %x\n", i, v);
}
@@ -396,7 +291,7 @@ uint8_t nrf_hal_test() {
print_addr(1);
print_addr(2);
#endif
nrf_flush_rx();
while(1) {
#if 1
@@ -404,18 +299,21 @@ uint8_t nrf_hal_test() {
uint8_t len = 0;
uint8_t status = 0;
_nrf_read_reg_byte(REG_STATUS, &status);
nrf_hal_read_reg_byte(REG_STATUS, &status);
nrf_read_payload(buf, &len);
if(status & _BV(RX_DR)) {
nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR));
nrf_flush_rx();
if(len > 0) {
uint8_t pipe = status;
pipe >>= 1;
pipe &= 0x07;
printf("received %u bytes from pipe %u: ", len, pipe);
if(pipe >= 6) {
nrf_flush_rx();
_nrf_read_reg_byte(REG_STATUS, _BV(RX_DR));
printf("\n");
continue;
}
@@ -426,15 +324,11 @@ uint8_t nrf_hal_test() {
printf("\n");
}
nrf_flush_rx();
_nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
} else {
printf("nodata %x\n", status);
nrf_flush_rx();
_nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
nrf_delay(100);
}
#endif
nrf_delay(100);
}

8
board/TencentOS_tiny_EVB_MX/STM32CubeIDE/nRF24L01/Src/nrf24l01.h
View File

@@ -1,12 +1,14 @@
#ifndef NRF24L01_H_
#define NRF24L01_H_
#include "nrf24l01_hal.h"
#if defined(__SI24R1__) && defined(__NRF24L01__)
#error "you must choose chip between SI24R1 and NRF24L01"
#endif
#if !defined(__SI24R1__) && !defined(__NRF24L01__)
#define __NRF24L01__
#error "you must specify the core chip of NRF24L01"
#endif
#define REG_CONFIG 0x00
@@ -275,9 +277,9 @@
#define _BV(n) (1<<(n))
#define _VV(v, n) ((v)<<(n))
void nrf_powerup();
int nrf_powerup();
void nrf_init();
int nrf_init(SPI_HandleTypeDef* spi, GPIO_TypeDef* csn_gpio_port, uint16_t csn_pin, GPIO_TypeDef* ce_gpio_port, uint16_t ce_pin);
uint8_t nrf_hal_test();

0
board/TencentOS_tiny_EVB_MX/STM32CubeIDE/nRF24L01/Src/nrf24l01_hal Normal file
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140
board/TencentOS_tiny_EVB_MX/STM32CubeIDE/nRF24L01/Src/nrf24l01_hal.c Normal file
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@@ -0,0 +1,140 @@
#include "nrf24l01.h"
static SPI_HandleTypeDef *nrf_spi;
static GPIO_TypeDef* nrf_csn_gpio_port;
static uint16_t nrf_csn_pin;
static GPIO_TypeDef* nrf_ce_gpio_port;
static uint16_t nrf_ce_pin;
int nrf_hal_init(SPI_HandleTypeDef* spi, GPIO_TypeDef* csn_gpio_port, uint16_t csn_pin, GPIO_TypeDef* ce_gpio_port, uint16_t ce_pin) {
nrf_spi = spi;
nrf_csn_gpio_port = csn_gpio_port;
nrf_csn_pin = csn_pin;
nrf_ce_gpio_port = ce_gpio_port;
nrf_ce_pin = ce_pin;
return 0;
}
void nrf_hal_csn(uint8_t mode) {
HAL_GPIO_WritePin(nrf_csn_gpio_port, nrf_csn_pin, mode == 0 ? GPIO_PIN_RESET : GPIO_PIN_SET);
}
void nrf_hal_ce(uint8_t mode) {
HAL_GPIO_WritePin(nrf_ce_gpio_port, nrf_ce_pin, mode == 0 ? GPIO_PIN_RESET : GPIO_PIN_SET);
}
int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) {
uint8_t cmd = CMD_R_REGISTER | reg;
nrf_hal_csn(0);
if(HAL_OK != HAL_SPI_Transmit(nrf_spi, &cmd, 1, HAL_MAX_DELAY)) {
return -1;
}
if(HAL_OK != HAL_SPI_Receive(nrf_spi, buf, len, HAL_MAX_DELAY)){
return -1;
}
nrf_hal_csn(1);
return 0;
}
int nrf_hal_read_reg_byte(uint8_t reg, uint8_t *v) {
return nrf_hal_read_reg(reg, v, 1);
}
int nrf_hal_write_reg(uint8_t reg, uint8_t *buf, uint8_t len)
{
uint8_t cmd = CMD_W_REGISTER | reg;
nrf_hal_csn(0);
if(HAL_OK != HAL_SPI_Transmit(nrf_spi, &cmd, 1, HAL_MAX_DELAY)) {
return -1;
}
if(HAL_OK != HAL_SPI_Transmit(nrf_spi, buf, len, HAL_MAX_DELAY)) {
return -1;
}
nrf_hal_csn(1);
return 0;
}
int nrf_hal_write_reg_byte(uint8_t reg, uint8_t byte)
{
return nrf_hal_write_reg(reg, &byte, 1);
}
int nrf_hal_set_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
if(0 != nrf_hal_read_reg_byte(reg, &v)) {
return -1;
}
v |= _BV(bit);
if(0 != nrf_hal_write_reg_byte(reg, v)) {
return -1;
}
return 0;
}
int nrf_hal_clear_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
if(0 != nrf_hal_read_reg_byte(reg, &v)) {
return -1;
}
v &= ~_BV(bit);
if(0 != nrf_hal_write_reg_byte(reg, v)) {
return -1;
}
return 0;
}
int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len) {
nrf_hal_csn(0);
if(HAL_OK != HAL_SPI_Transmit(nrf_spi, &cmd, 1, HAL_MAX_DELAY)) {
return -1;
}
if(HAL_OK != HAL_SPI_Receive(nrf_spi, data, len, HAL_MAX_DELAY)) {
return -1;
}
nrf_hal_csn(1);
return 0;
}
int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data) {
return nrf_hal_cmd_read(cmd, data, 1);
}
int nrf_hal_write_cmd(uint8_t cmd) {
nrf_hal_csn(0);
if(HAL_OK != HAL_SPI_Transmit(nrf_spi, &cmd, 1, HAL_MAX_DELAY)) {
return -1;
}
nrf_hal_csn(1);
return 0;
}

38
board/TencentOS_tiny_EVB_MX/STM32CubeIDE/nRF24L01/Src/nrf24l01_hal.h Normal file
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@@ -0,0 +1,38 @@
#ifndef NRF24L01_HAL_H_
#define NRF24L01_HAL_H_
#define __SI24R1__
#ifdef STM32L431xx
#include "stm32l4xx_hal.h"
#endif
int nrf_hal_init(SPI_HandleTypeDef* spi, GPIO_TypeDef* csn_gpio_port, uint16_t csn_pin, GPIO_TypeDef* ce_gpio_port, uint16_t ce_pin);
void nrf_hal_csn(uint8_t mode);
void nrf_hal_ce(uint8_t mode);
int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len);
int nrf_hal_read_reg_byte(uint8_t reg, uint8_t *v);
int nrf_hal_write_reg(uint8_t reg, uint8_t *buf, uint8_t len);
int nrf_hal_write_reg_byte(uint8_t reg, uint8_t byte);
int nrf_hal_set_reg_bit(uint8_t reg, uint8_t bit);
int nrf_hal_clear_reg_bit(uint8_t reg, uint8_t bit);
int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len);
int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data);
int nrf_hal_write_cmd(uint8_t cmd);
#endif /* NRF24L01_HAL_H_ */