arch :arc: add the ARC port

Signed-off-by: Jingru <jingru@synopsys.com>
2020-03-17 15:16:14 +08:00
parent 9675ebb11d
commit 65f55e73e5
154 changed files with 47346 additions and 0 deletions
--- a/board/ARC_NSIM_EM/BSP/Inc/core_config.h
+++ b/board/ARC_NSIM_EM/BSP/Inc/core_config.h
@@ -0,0 +1,253 @@
+#ifndef H_CORE_CONFIG
+	#define H_CORE_CONFIG
+	#define	core_config_cir_identity	0x00000043
+	#define	core_config_cir_identity_chipid	0
+	#define	core_config_cir_identity_arcnum	0
+	#define	core_config_cir_identity_arcver	67
+	#define	core_config_cir_identity_family	4
+	#define	core_config_cir_identity_corever	3
+	#define	core_config_cir_aux_dccm	0x80000000
+	#define	core_config_bcr_bcr_ver	0x00000002
+	#define	core_config_bcr_bcr_ver_version	2
+	#define	core_config_bcr_vecbase_ac_build	0x00000010
+	#define	core_config_bcr_mpu_build	0x00010002
+	#define	core_config_bcr_mpu_build_i	0
+	#define	core_config_bcr_mpu_build_s	0
+	#define	core_config_bcr_mpu_build_regions	16
+	#define	core_config_bcr_mpu_build_version	2
+	#define	core_config_bcr_rf_build	0x0000c902
+	#define	core_config_bcr_rf_build_version	2
+	#define	core_config_bcr_rf_build_p	1
+	#define	core_config_bcr_rf_build_e	0
+	#define	core_config_bcr_rf_build_r	0
+	#define	core_config_bcr_rf_build_b	1
+	#define	core_config_bcr_rf_build_d	3
+	#define	core_config_bcr_d_cache_build	0x00215104
+	#define	core_config_bcr_d_cache_build_version	4
+	#define	core_config_bcr_d_cache_build_assoc	1
+	#define	core_config_bcr_d_cache_build_capacity	5
+	#define	core_config_bcr_d_cache_build_bsize	1
+	#define	core_config_bcr_d_cache_build_fl	2
+	#define	core_config_bcr_d_cache_build_ioc	0
+	#define	core_config_bcr_d_cache_build_cp	0
+	#define	core_config_bcr_d_cache_build_u	0
+	#define	core_config_bcr_d_cache_build_cycles	0
+	#define	core_config_bcr_dccm_build	0x00010904
+	#define	core_config_bcr_dccm_build_cycles	0
+	#define	core_config_bcr_dccm_build_interleave	1
+	#define	core_config_bcr_dccm_build_size1	0
+	#define	core_config_bcr_dccm_build_size0	9
+	#define	core_config_bcr_dccm_build_version	4
+	#define	core_config_bcr_timer_build	0x00010304
+	#define	core_config_bcr_timer_build_sp1	0
+	#define	core_config_bcr_timer_build_sp0	0
+	#define	core_config_bcr_timer_build_p1	0
+	#define	core_config_bcr_timer_build_p0	1
+	#define	core_config_bcr_timer_build_st1	0
+	#define	core_config_bcr_timer_build_st0	0
+	#define	core_config_bcr_timer_build_rtc	0
+	#define	core_config_bcr_timer_build_rtsc_ver	1
+	#define	core_config_bcr_timer_build_rtsc	0
+	#define	core_config_bcr_timer_build_t0	1
+	#define	core_config_bcr_timer_build_t1	1
+	#define	core_config_bcr_timer_build_version	4
+	#define	core_config_bcr_ap_build	0x00000405
+	#define	core_config_bcr_ap_build_version	5
+	#define	core_config_bcr_ap_build_type	4
+	#define	core_config_bcr_i_cache_build	0x00225104
+	#define	core_config_bcr_i_cache_build_assoc	1
+	#define	core_config_bcr_i_cache_build_version	4
+	#define	core_config_bcr_i_cache_build_capacity	5
+	#define	core_config_bcr_i_cache_build_bsize	2
+	#define	core_config_bcr_i_cache_build_fl	2
+	#define	core_config_bcr_i_cache_build_d	0
+	#define	core_config_bcr_iccm_build	0x00000a04
+	#define	core_config_bcr_iccm_build_iccm1_size1	0
+	#define	core_config_bcr_iccm_build_iccm0_size1	0
+	#define	core_config_bcr_iccm_build_iccm1_size0	0
+	#define	core_config_bcr_iccm_build_iccm0_size0	10
+	#define	core_config_bcr_iccm_build_version	4
+	#define	core_config_bcr_xy_build	0x00001520
+	#define	core_config_bcr_xy_build_memsize	1
+	#define	core_config_bcr_xy_build_interleaved	1
+	#define	core_config_bcr_xy_build_config	1
+	#define	core_config_bcr_xy_build_version	32
+	#define	core_config_bcr_dsp_build	0x00003521
+	#define	core_config_bcr_dsp_build_wide	0
+	#define	core_config_bcr_dsp_build_itu_pa	0
+	#define	core_config_bcr_dsp_build_acc_shift	2
+	#define	core_config_bcr_dsp_build_comp	1
+	#define	core_config_bcr_dsp_build_divsqrt	1
+	#define	core_config_bcr_dsp_build_version	33
+	#define	core_config_bcr_multiply_build	0x00022a06
+	#define	core_config_bcr_multiply_build_version16x16	2
+	#define	core_config_bcr_multiply_build_dsp	2
+	#define	core_config_bcr_multiply_build_cyc	2
+	#define	core_config_bcr_multiply_build_type	2
+	#define	core_config_bcr_multiply_build_version32x32	6
+	#define	core_config_bcr_swap_build	0x00000003
+	#define	core_config_bcr_swap_build_version	3
+	#define	core_config_bcr_norm_build	0x00000003
+	#define	core_config_bcr_norm_build_version	3
+	#define	core_config_bcr_minmax_build	0x00000002
+	#define	core_config_bcr_minmax_build_version	2
+	#define	core_config_bcr_barrel_build	0x00000303
+	#define	core_config_bcr_barrel_build_version	3
+	#define	core_config_bcr_barrel_build_shift_option	3
+	#define	core_config_bcr_isa_config	0x12047402
+	#define	core_config_bcr_isa_config_d	1
+	#define	core_config_bcr_isa_config_c	2
+	#define	core_config_bcr_isa_config_l	0
+	#define	core_config_bcr_isa_config_n	0
+	#define	core_config_bcr_isa_config_a	0
+	#define	core_config_bcr_isa_config_b	0
+	#define	core_config_bcr_isa_config_addr_size	4
+	#define	core_config_bcr_isa_config_lpc_size	7
+	#define	core_config_bcr_isa_config_pc_size	4
+	#define	core_config_bcr_isa_config_version	2
+	#define	core_config_bcr_fpu_build	0x01000f02
+	#define	core_config_bcr_fpu_build_da	1
+	#define	core_config_bcr_fpu_build_dd	0
+	#define	core_config_bcr_fpu_build_dc	0
+	#define	core_config_bcr_fpu_build_df	0
+	#define	core_config_bcr_fpu_build_dp	0
+	#define	core_config_bcr_fpu_build_fd	0
+	#define	core_config_bcr_fpu_build_fm	0
+	#define	core_config_bcr_fpu_build_sd	1
+	#define	core_config_bcr_fpu_build_sc	1
+	#define	core_config_bcr_fpu_build_sf	1
+	#define	core_config_bcr_fpu_build_sp	1
+	#define	core_config_bcr_fpu_build_version	2
+	#define	core_config_bcr_bs_build	0x00000002
+	#define	core_config_bcr_bs_build_version	2
+	#define	core_config_bcr_agu_build	0x01988c02
+	#define	core_config_bcr_agu_build_accordian	1
+	#define	core_config_bcr_agu_build_wb_size	4
+	#define	core_config_bcr_agu_build_num_modifier	24
+	#define	core_config_bcr_agu_build_num_offset	8
+	#define	core_config_bcr_agu_build_num_addr	12
+	#define	core_config_bcr_agu_build_version	2
+	#define	core_config_bcr_stack_region_build	0x00000002
+	#define	core_config_bcr_dmac_build	0x000a0101
+	#define	core_config_bcr_dmac_build_int_cfg	1
+	#define	core_config_bcr_dmac_build_fifo	1
+	#define	core_config_bcr_dmac_build_chan_mem	0
+	#define	core_config_bcr_dmac_build_channels	1
+	#define	core_config_bcr_dmac_build_version	1
+	#define	core_config_bcr_core_config	0x00000101
+	#define	core_config_bcr_core_config_turbo_boost	1
+	#define	core_config_bcr_core_config_version	1
+	#define	core_config_bcr_irq_build	0x13101401
+	#define	core_config_bcr_irq_build_raz	0
+	#define	core_config_bcr_irq_build_f	1
+	#define	core_config_bcr_irq_build_p	3
+	#define	core_config_bcr_irq_build_exts	16
+	#define	core_config_bcr_irq_build_irqs	20
+	#define	core_config_bcr_irq_build_version	1
+	#define	core_config_bcr_pct_build	0x08080102
+	#define	core_config_bcr_pct_build_version	2
+	#define	core_config_bcr_pct_build_s	1
+	#define	core_config_bcr_pct_build_i	0
+	#define	core_config_bcr_pct_build_c	8
+	#define	core_config_bcr_cc_build	0x006f0004
+	#define	core_config_bcr_cc_build_version	4
+	#define	core_config_bcr_cc_build_cc	111
+	#define	core_config_bcr_smart_build	0x00002003
+	#define	core_config_bcr_smart_build_version	3
+	#define	core_config_bcr_smart_build_stack_size	8
+	#define	core_config_cir_aux_iccm	0x00000000
+	#define	core_config_cir_dmp_peripheral	0xf0000000
+	#define	core_config_mpu_present	1
+	#define	core_config_mpu	1
+	#define	core_config_mpu_regions	16
+	#define	core_config_family	4
+	#define	core_config_core_version	2
+	#define	core_config_family_name	"arcv2em"
+	#define	core_config_rgf_num_banks	2
+	#define	core_config_rgf_banked_regs	32
+	#define	core_config_rgf_num_wr_ports	2
+	#define	core_config_endian	"little"
+	#define	core_config_endian_little	1
+	#define	core_config_endian_big	0
+	#define	core_config_lpc_size	32
+	#define	core_config_pc_size	32
+	#define	core_config_addr_size	32
+	#define	core_config_code_density	1
+	#define	core_config_div_rem	"radix2"
+	#define	core_config_div_rem_radix2	1
+	#define	core_config_dsp_itu	1
+	#define	core_config_turbo_boost	1
+	#define	core_config_swap	1
+	#define	core_config_bitscan	1
+	#define	core_config_mpy_option	"mpyd"
+	#define	core_config_mpy_option_num	8
+	#define	core_config_shift_assist	1
+	#define	core_config_barrel_shifter	1
+	#define	core_config_dsp	1
+	#define	core_config_dsp2	1
+	#define	core_config_dsp_complex	1
+	#define	core_config_dsp_divsqrt	"radix2"
+	#define	core_config_dsp_divsqrt_radix2	1
+	#define	core_config_dsp_accshift	"full"
+	#define	core_config_dsp_accshift_full	1
+	#define	core_config_agu_large	1
+	#define	core_config_agu_wb_depth	4
+	#define	core_config_agu_accord	1
+	#define	core_config_xy	1
+	#define	core_config_xy_config	"dccm_y"
+	#define	core_config_xy_config_dccm_y	1
+	#define	core_config_xy_size	8192
+	#define	core_config_xy_size_KM	"8K"
+	#define	core_config_xy_interleave	1
+	#define	core_config_xy_y_base	0xe0000000
+	#define	core_config_fpus_div	1
+	#define	core_config_fpu_mac	1
+	#define	core_config_fpus_mpy_fast	1
+	#define	core_config_fpus_div_slow	1
+	#define	core_config_bitstream	1
+	#define	core_config_timer0	1
+	#define	core_config_timer0_level	1
+	#define	core_config_timer0_vector	16
+	#define	core_config_timer1	1
+	#define	core_config_timer1_level	0
+	#define	core_config_timer1_vector	17
+	#define	core_config_action_points	2
+	#define	core_config_stack_check	1
+	#define	core_config_smart_stack_entries	8
+	#define	core_config_interrupts_present	1
+	#define	core_config_interrupts_number	20
+	#define	core_config_interrupts_priorities	4
+	#define	core_config_interrupts_externals	16
+	#define	core_config_interrupts	20
+	#define	core_config_interrupt_priorities	4
+	#define	core_config_ext_interrupts	16
+	#define	core_config_interrupts_firq	1
+	#define	core_config_interrupts_base	0x0
+	#define	core_config_dcache_present	1
+	#define	core_config_dcache_size	16384
+	#define	core_config_dcache_line_size	32
+	#define	core_config_dcache_ways	2
+	#define	core_config_dcache_feature	2
+	#define	core_config_icache_present	1
+	#define	core_config_icache_size	16384
+	#define	core_config_icache_line_size	32
+	#define	core_config_icache_ways	2
+	#define	core_config_icache_feature	2
+	#define	core_config_dccm_present	1
+	#define	core_config_dccm_size	0x80000
+	#define	core_config_dccm_base	0x80000000
+	#define	core_config_dccm_interleave	1
+	#define	core_config_iccm_present	1
+	#define	core_config_iccm0_present	1
+	#define	core_config_iccm_size	0x80000
+	#define	core_config_iccm0_size	0x40000
+	#define	core_config_iccm_base	0x00000000
+	#define	core_config_iccm0_base	0x00000000
+	#define	core_config_pct_counters	8
+	#define	core_config_dmac	1
+	#define	core_config_dmac_channels	2
+	#define	core_config_dmac_registers	0
+	#define	core_config_dmac_fifo_depth	2
+	#define	core_config_dmac_int_config	"single_internal"
+#endif /* H_CORE_CONFIG */
+
--- a/board/ARC_NSIM_EM/BSP/Inc/nsim.h
+++ b/board/ARC_NSIM_EM/BSP/Inc/nsim.h
@@ -0,0 +1,73 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+   --------------------------------------------- */
+#ifndef H_NSIM
+#define H_NSIM
+
+#include "arc/arc_feature_config.h"
+#include "arc/arc_em.h"
+
+#include "nsim_uart_obj.h"
+
+/** CPU Clock Frequency definition */
+#if defined(BOARD_CPU_FREQ)
+/*!< Get cpu clock frequency definition from build system */
+	#define CLK_CPU         (BOARD_CPU_FREQ)
+#elif defined(ARC_FEATURE_CPU_CLOCK_FREQ)
+/*!< Get cpu clock frequency definition from tcf file */
+	#define CLK_CPU         (ARC_FEATURE_CPU_CLOCK_FREQ)
+#else
+/*!< Default cpu clock frequency */
+	#define CLK_CPU         (1000000)
+#endif
+
+/* common macros must be defined by all boards */
+
+#define BOARD_CONSOLE_UART_ID       NSIM_UART_0_ID
+#define BOARD_CONSOLE_UART_BAUD     115200
+
+#define BOARD_SYS_TIMER_ID          TIMER_0
+#define BOARD_SYS_TIMER_INTNO       INTNO_TIMER0
+#define BOARD_SYS_TIMER_HZ          (1000)
+
+/** board timer 1ms means what HZ count */
+#define BOARD_SYS_TIMER_MS_HZ       (1000)
+/** board ms counter convention based on the global timer counter */
+#define BOARD_SYS_TIMER_MS_CONV     (BOARD_SYS_TIMER_MS_HZ / BOARD_SYS_TIMER_HZ)
+
+#define BOARD_OS_TIMER_ID           TIMER_0
+#define BOARD_OS_TIMER_INTNO        INTNO_TIMER0
+
+#define BOARD_CPU_CLOCK             CLK_CPU
+
+#define button_read(x)              1
+#define led_write(x, y)             EMBARC_PRINTF("led out: %x, %x\r\n", x, y)
+#define BOARD_LED_MASK              0xff
+
+#endif  /* H_NSIM */
--- a/board/ARC_NSIM_EM/BSP/Inc/nsim_uart_obj.h
+++ b/board/ARC_NSIM_EM/BSP/Inc/nsim_uart_obj.h
@@ -0,0 +1,58 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+   --------------------------------------------- */
+#ifndef H_NSIM_UART_OBJ
+#define H_NSIM_UART_OBJ
+
+#include "device/ip_hal/dev_uart.h"
+
+/**
+ * NSIM UART Object Number
+ */
+#define DW_UART_NUM (1) /*!< NSIM UART valid number */
+
+/**
+ * NSIM UART Object ID Macros
+ */
+#define NSIM_UART_0_ID  (0) /*!< uart 0 id macro */
+
+/**
+ * NSIM UART Object Control Macros
+ */
+#define USE_NSIM_UART_0 (1) /*!< enable use nsim uart 0 (stdio) */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_NSIM_UART_OBJ */
--- a/board/ARC_NSIM_EM/BSP/Src/core_config.s
+++ b/board/ARC_NSIM_EM/BSP/Src/core_config.s
@@ -0,0 +1,252 @@
+.ifndef __core_config_s
+	.define __core_config_s, 1
+	.define	core_config_cir_identity,0x00000043
+	.define	core_config_cir_identity_chipid,0
+	.define	core_config_cir_identity_arcnum,0
+	.define	core_config_cir_identity_arcver,67
+	.define	core_config_cir_identity_family,4
+	.define	core_config_cir_identity_corever,3
+	.define	core_config_cir_aux_dccm,0x80000000
+	.define	core_config_bcr_bcr_ver,0x00000002
+	.define	core_config_bcr_bcr_ver_version,2
+	.define	core_config_bcr_vecbase_ac_build,0x00000010
+	.define	core_config_bcr_mpu_build,0x00010002
+	.define	core_config_bcr_mpu_build_i,0
+	.define	core_config_bcr_mpu_build_s,0
+	.define	core_config_bcr_mpu_build_regions,16
+	.define	core_config_bcr_mpu_build_version,2
+	.define	core_config_bcr_rf_build,0x0000c902
+	.define	core_config_bcr_rf_build_version,2
+	.define	core_config_bcr_rf_build_p,1
+	.define	core_config_bcr_rf_build_e,0
+	.define	core_config_bcr_rf_build_r,0
+	.define	core_config_bcr_rf_build_b,1
+	.define	core_config_bcr_rf_build_d,3
+	.define	core_config_bcr_d_cache_build,0x00215104
+	.define	core_config_bcr_d_cache_build_version,4
+	.define	core_config_bcr_d_cache_build_assoc,1
+	.define	core_config_bcr_d_cache_build_capacity,5
+	.define	core_config_bcr_d_cache_build_bsize,1
+	.define	core_config_bcr_d_cache_build_fl,2
+	.define	core_config_bcr_d_cache_build_ioc,0
+	.define	core_config_bcr_d_cache_build_cp,0
+	.define	core_config_bcr_d_cache_build_u,0
+	.define	core_config_bcr_d_cache_build_cycles,0
+	.define	core_config_bcr_dccm_build,0x00010904
+	.define	core_config_bcr_dccm_build_cycles,0
+	.define	core_config_bcr_dccm_build_interleave,1
+	.define	core_config_bcr_dccm_build_size1,0
+	.define	core_config_bcr_dccm_build_size0,11
+	.define	core_config_bcr_dccm_build_version,4
+	.define	core_config_bcr_timer_build,0x00010304
+	.define	core_config_bcr_timer_build_sp1,0
+	.define	core_config_bcr_timer_build_sp0,0
+	.define	core_config_bcr_timer_build_p1,0
+	.define	core_config_bcr_timer_build_p0,1
+	.define	core_config_bcr_timer_build_st1,0
+	.define	core_config_bcr_timer_build_st0,0
+	.define	core_config_bcr_timer_build_rtc,0
+	.define	core_config_bcr_timer_build_rtsc_ver,1
+	.define	core_config_bcr_timer_build_rtsc,0
+	.define	core_config_bcr_timer_build_t0,1
+	.define	core_config_bcr_timer_build_t1,1
+	.define	core_config_bcr_timer_build_version,4
+	.define	core_config_bcr_ap_build,0x00000405
+	.define	core_config_bcr_ap_build_version,5
+	.define	core_config_bcr_ap_build_type,4
+	.define	core_config_bcr_i_cache_build,0x00225104
+	.define	core_config_bcr_i_cache_build_assoc,1
+	.define	core_config_bcr_i_cache_build_version,4
+	.define	core_config_bcr_i_cache_build_capacity,5
+	.define	core_config_bcr_i_cache_build_bsize,2
+	.define	core_config_bcr_i_cache_build_fl,2
+	.define	core_config_bcr_i_cache_build_d,0
+	.define	core_config_bcr_iccm_build,0x00000a04
+	.define	core_config_bcr_iccm_build_iccm1_size1,0
+	.define	core_config_bcr_iccm_build_iccm0_size1,0
+	.define	core_config_bcr_iccm_build_iccm1_size0,0
+	.define	core_config_bcr_iccm_build_iccm0_size0,11
+	.define	core_config_bcr_iccm_build_version,4
+	.define	core_config_bcr_xy_build,0x00001520
+	.define	core_config_bcr_xy_build_memsize,1
+	.define	core_config_bcr_xy_build_interleaved,1
+	.define	core_config_bcr_xy_build_config,1
+	.define	core_config_bcr_xy_build_version,32
+	.define	core_config_bcr_dsp_build,0x00003521
+	.define	core_config_bcr_dsp_build_wide,0
+	.define	core_config_bcr_dsp_build_itu_pa,0
+	.define	core_config_bcr_dsp_build_acc_shift,2
+	.define	core_config_bcr_dsp_build_comp,1
+	.define	core_config_bcr_dsp_build_divsqrt,1
+	.define	core_config_bcr_dsp_build_version,33
+	.define	core_config_bcr_multiply_build,0x00022a06
+	.define	core_config_bcr_multiply_build_version16x16,2
+	.define	core_config_bcr_multiply_build_dsp,2
+	.define	core_config_bcr_multiply_build_cyc,2
+	.define	core_config_bcr_multiply_build_type,2
+	.define	core_config_bcr_multiply_build_version32x32,6
+	.define	core_config_bcr_swap_build,0x00000003
+	.define	core_config_bcr_swap_build_version,3
+	.define	core_config_bcr_norm_build,0x00000003
+	.define	core_config_bcr_norm_build_version,3
+	.define	core_config_bcr_minmax_build,0x00000002
+	.define	core_config_bcr_minmax_build_version,2
+	.define	core_config_bcr_barrel_build,0x00000303
+	.define	core_config_bcr_barrel_build_version,3
+	.define	core_config_bcr_barrel_build_shift_option,3
+	.define	core_config_bcr_isa_config,0x12047402
+	.define	core_config_bcr_isa_config_d,1
+	.define	core_config_bcr_isa_config_c,2
+	.define	core_config_bcr_isa_config_l,0
+	.define	core_config_bcr_isa_config_n,0
+	.define	core_config_bcr_isa_config_a,0
+	.define	core_config_bcr_isa_config_b,0
+	.define	core_config_bcr_isa_config_addr_size,4
+	.define	core_config_bcr_isa_config_lpc_size,7
+	.define	core_config_bcr_isa_config_pc_size,4
+	.define	core_config_bcr_isa_config_version,2
+	.define	core_config_bcr_fpu_build,0x01000f02
+	.define	core_config_bcr_fpu_build_da,1
+	.define	core_config_bcr_fpu_build_dd,0
+	.define	core_config_bcr_fpu_build_dc,0
+	.define	core_config_bcr_fpu_build_df,0
+	.define	core_config_bcr_fpu_build_dp,0
+	.define	core_config_bcr_fpu_build_fd,0
+	.define	core_config_bcr_fpu_build_fm,0
+	.define	core_config_bcr_fpu_build_sd,1
+	.define	core_config_bcr_fpu_build_sc,1
+	.define	core_config_bcr_fpu_build_sf,1
+	.define	core_config_bcr_fpu_build_sp,1
+	.define	core_config_bcr_fpu_build_version,2
+	.define	core_config_bcr_agu_build,0x01988c02
+	.define	core_config_bcr_agu_build_accordian,1
+	.define	core_config_bcr_agu_build_wb_size,4
+	.define	core_config_bcr_agu_build_num_modifier,24
+	.define	core_config_bcr_agu_build_num_offset,8
+	.define	core_config_bcr_agu_build_num_addr,12
+	.define	core_config_bcr_agu_build_version,2
+	.define	core_config_bcr_stack_region_build,0x00000002
+	.define	core_config_bcr_dmac_build,0x000a0101
+	.define	core_config_bcr_dmac_build_int_cfg,1
+	.define	core_config_bcr_dmac_build_fifo,1
+	.define	core_config_bcr_dmac_build_chan_mem,0
+	.define	core_config_bcr_dmac_build_channels,1
+	.define	core_config_bcr_dmac_build_version,1
+	.define	core_config_bcr_core_config,0x00000101
+	.define	core_config_bcr_core_config_turbo_boost,1
+	.define	core_config_bcr_core_config_version,1
+	.define	core_config_bcr_irq_build,0x13101401
+	.define	core_config_bcr_irq_build_raz,0
+	.define	core_config_bcr_irq_build_f,1
+	.define	core_config_bcr_irq_build_p,3
+	.define	core_config_bcr_irq_build_exts,16
+	.define	core_config_bcr_irq_build_irqs,20
+	.define	core_config_bcr_irq_build_version,1
+	.define	core_config_bcr_pct_build,0x08080102
+	.define	core_config_bcr_pct_build_version,2
+	.define	core_config_bcr_pct_build_s,1
+	.define	core_config_bcr_pct_build_i,0
+	.define	core_config_bcr_pct_build_c,8
+	.define	core_config_bcr_cc_build,0x006f0004
+	.define	core_config_bcr_cc_build_version,4
+	.define	core_config_bcr_cc_build_cc,111
+	.define	core_config_bcr_smart_build,0x00002003
+	.define	core_config_bcr_smart_build_version,3
+	.define	core_config_bcr_smart_build_stack_size,8
+	.define	core_config_cir_aux_iccm,0x00000000
+	.define	core_config_cir_dmp_peripheral,0xf0000000
+	.define	core_config_family,4
+	.define	core_config_core_version,2
+	.define	core_config_family_name,"arcv2em"
+	.define	core_config_rgf_num_banks,2
+	.define	core_config_rgf_banked_regs,32
+	.define	core_config_rgf_num_wr_ports,2
+	.define	core_config_endian,"little"
+	.define	core_config_endian_little,1
+	.define	core_config_endian_big,0
+	.define	core_config_lpc_size,32
+	.define	core_config_pc_size,32
+	.define	core_config_addr_size,32
+	.define	core_config_code_density,1
+	.define	core_config_div_rem,"radix2"
+	.define	core_config_div_rem_radix2,1
+	.define	core_config_dsp_itu,1
+	.define	core_config_turbo_boost,1
+	.define	core_config_swap,1
+	.define	core_config_bitscan,1
+	.define	core_config_mpy_option,"mpyd"
+	.define	core_config_mpy_option_num,8
+	.define	core_config_shift_assist,1
+	.define	core_config_barrel_shifter,1
+	.define	core_config_mpu_present,1
+	.define	core_config_mpu,1
+	.define	core_config_mpu_regions,16
+	.define	core_config_dsp,1
+	.define	core_config_dsp2,1
+	.define	core_config_dsp_complex,1
+	.define	core_config_dsp_divsqrt,"radix2"
+	.define	core_config_dsp_divsqrt_radix2,1
+	.define	core_config_dsp_accshift,"full"
+	.define	core_config_dsp_accshift_full,1
+	.define	core_config_agu_large,1
+	.define	core_config_agu_wb_depth,4
+	.define	core_config_agu_accord,1
+	.define	core_config_xy,1
+	.define	core_config_xy_config,"dccm_y"
+	.define	core_config_xy_config_dccm_y,1
+	.define	core_config_xy_size,8192
+	.define	core_config_xy_size_KM,"8K"
+	.define	core_config_xy_interleave,1
+	.define	core_config_xy_y_base,0xe0000000
+	.define	core_config_fpus_div,1
+	.define	core_config_fpu_mac,1
+	.define	core_config_fpuda,1
+	.define	core_config_fpus_mpy_slow,1
+	.define	core_config_fpus_div_slow,1
+	.define	core_config_bitstream,1
+	.define	core_config_timer0,1
+	.define	core_config_timer0_level,1
+	.define	core_config_timer0_vector,16
+	.define	core_config_timer1,1
+	.define	core_config_timer1_level,0
+	.define	core_config_timer1_vector,17
+	.define	core_config_action_points,2
+	.define	core_config_stack_check,1
+	.define	core_config_smart_stack_entries,8
+	.define	core_config_interrupts_present,1
+	.define	core_config_interrupts_number,20
+	.define	core_config_interrupts_priorities,4
+	.define	core_config_interrupts_externals,16
+	.define	core_config_interrupts,20
+	.define	core_config_interrupt_priorities,4
+	.define	core_config_ext_interrupts,16
+	.define	core_config_interrupts_firq,1
+	.define	core_config_interrupts_base,0x0
+	.define	core_config_dcache_present,1
+	.define	core_config_dcache_size,16384
+	.define	core_config_dcache_line_size,32
+	.define	core_config_dcache_ways,2
+	.define	core_config_dcache_feature,2
+	.define	core_config_icache_present,1
+	.define	core_config_icache_size,16384
+	.define	core_config_icache_line_size,32
+	.define	core_config_icache_ways,2
+	.define	core_config_icache_feature,2
+	.define	core_config_dccm_present,1
+	.define	core_config_dccm_size,0x80000
+	.define	core_config_dccm_base,0x80000000
+	.define	core_config_dccm_interleave,1
+	.define	core_config_iccm_present,1
+	.define	core_config_iccm0_present,1
+	.define	core_config_iccm_size,0x80000
+	.define	core_config_iccm0_size,0x80000
+	.define	core_config_iccm_base,0x00000000
+	.define	core_config_iccm0_base,0x00000000
+	.define	core_config_pct_counters,8
+	.define	core_config_dmac,1
+	.define	core_config_dmac_channels,2
+	.define	core_config_dmac_registers,0
+	.define	core_config_dmac_fifo_depth,2
+	.define	core_config_dmac_int_config,"single_internal"
+.endif ; __core_config_s
+
--- a/board/ARC_NSIM_EM/BSP/Src/nsim_init.c
+++ b/board/ARC_NSIM_EM/BSP/Src/nsim_init.c
@@ -0,0 +1,41 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+   --------------------------------------------- */
+#include "arc/arc_timer.h"
+#include "board.h"
+
+/**
+ * @brief necessary board hardware initialization
+ * @note It is better to disable interrupts when calling this function
+ * remember to enable interrupt when you want to use them
+ */
+void board_init(void)
+{
+	arc_timer_init();
+}
--- a/board/ARC_NSIM_EM/BSP/Src/nsim_uart_obj.c
+++ b/board/ARC_NSIM_EM/BSP/Src/nsim_uart_obj.c
@@ -0,0 +1,129 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+   --------------------------------------------- */
+#include <stdio.h>
+#include "nsim.h"
+
+/**
+ * NSIM UART 0 Object Instantiation
+ */
+#if (USE_NSIM_UART_0)
+
+static DEV_UART nsim_uart_0;                   /*!< nsim uart object */
+
+/** nsim uart 0 open */
+static int32_t nsim_uart_0_open(uint32_t baud)
+{
+	/* no need to open, stdio is used */
+	return 0;
+}
+/** nsim uart 0 close */
+static int32_t nsim_uart_0_close(void)
+{
+	return 0;
+}
+/** nsim uart 0 control */
+static int32_t nsim_uart_0_control(uint32_t ctrl_cmd, void *param)
+{
+	return 0;
+}
+/** nsim uart 0 write */
+static int32_t nsim_uart_0_write(const void *data, uint32_t len)
+{
+	return fwrite(data, len, sizeof(uint8_t), stdout);
+}
+/** nsim uart 0 close */
+static int32_t nsim_uart_0_read(void *data, uint32_t len)
+{
+	uint32_t i;
+	int32_t c;
+
+	for (i = 0; i < len; i++) {
+		c = getchar();
+		if (c < 0) {
+			break;
+		}
+		if (c == 10) {
+			c = 13;
+		}
+		*((uint8_t *)data) = (uint8_t)c;
+		data++;
+	}
+
+	return i;
+}
+
+/** install nsim uart 0 to system */
+static void nsim_uart_0_install(void)
+{
+	DEV_UART *nsim_uart_ptr = &nsim_uart_0;
+
+	/** uart dev init */
+	nsim_uart_ptr->uart_open = nsim_uart_0_open;
+	nsim_uart_ptr->uart_close = nsim_uart_0_close;
+	nsim_uart_ptr->uart_control = nsim_uart_0_control;
+	nsim_uart_ptr->uart_write = nsim_uart_0_write;
+	nsim_uart_ptr->uart_read = nsim_uart_0_read;
+
+}
+#endif /* USE_DW_UART_0 */
+
+/**
+ * \brief	install all uart objects
+ * \note	\b MUST be called during system init
+ */
+static void nsim_uart_all_install(void)
+{
+#if (USE_NSIM_UART_0)
+	nsim_uart_0_install();
+#endif
+}
+
+/** get one uart device structure */
+DEV_UART_PTR uart_get_dev(int32_t uart_id)
+{
+	static uint32_t install_flag = 0;
+
+	/* intall device objects */
+	if (install_flag == 0) {
+		install_flag = 1;
+		nsim_uart_all_install();
+	}
+
+	switch (uart_id) {
+#if (USE_NSIM_UART_0)
+	case NSIM_UART_0_ID:
+		return &nsim_uart_0;
+		break;
+#endif
+	default:
+		break;
+	}
+	return NULL;
+}
--- a/board/ARC_NSIM_EM/GCC/hello_world/Makefile
+++ b/board/ARC_NSIM_EM/GCC/hello_world/Makefile
@@ -0,0 +1,231 @@
+##########################################################################################################################
+# File automatically-generated by tool: [projectgenerator] version: [3.3.0] date: [Mon Aug 05 10:29:11 CST 2019]
+##########################################################################################################################
+
+# ------------------------------------------------
+# Generic Makefile (based on gcc)
+#
+# ChangeLog :
+#	2017-02-10 - Several enhancements + project update mode
+#   2015-07-22 - first version
+# ------------------------------------------------
+
+######################################
+# target
+######################################
+TARGET = TencentOS_tiny
+
+
+######################################
+# building variables
+######################################
+# debug build?
+DEBUG = 1
+# optimization
+OPT = -O0
+
+TOP_DIR = ../../../../
+#######################################
+# paths
+#######################################
+# Build path
+BUILD_DIR = build
+
+######################################
+# source
+######################################
+# C sources
+KERNEL_SRC =  \
+		${wildcard $(TOP_DIR)/kernel/core/*.c}
+		C_SOURCES += $(KERNEL_SRC)
+
+ARCH_SRC = \
+		${wildcard $(TOP_DIR)/arch/arc/nsim/em/gcc/*.c} \
+		${wildcard $(TOP_DIR)/arch/arc/nsim/common/*.c}
+		C_SOURCES += $(ARCH_SRC)
+
+CMSIS_SRC =  \
+		${wildcard $(TOP_DIR)/osal/cmsis_os/*.c}
+		C_SOURCES += $(CMSIS_SRC)
+
+HAL_DRIVER_SRC =  \
+		$(TOP_DIR)/board/ARC_NSIM_EM/BSP/Src/nsim_init.c \
+		$(TOP_DIR)/board/ARC_NSIM_EM/BSP/Src/nsim_uart_obj.c \
+		$(TOP_DIR)/examples/hello_world/hello_world.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/board/board.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/startup/arc_cxx_support.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_cache.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_connect.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_exception.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_mp.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_mpu.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_timer.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_udma.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_util.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library/clib/embARC_sbrk.c \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library/clib/embARC_syscalls.c
+		C_SOURCES += $(HAL_DRIVER_SRC) 
+
+# ASM sources
+ASM_SOURCES =  \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/startup/arc_startup.s \
+		$(TOP_DIR)/platform/vendor_bsp/embarc_bsp/arc/arc_exc_asm.s
+
+
+ASM_SOURCES_S =  \
+$(TOP_DIR)/arch/arc/nsim/em/gcc/port_s.S
+
+
+#######################################
+# binaries
+#######################################
+PREFIX = arc-elf32-
+# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
+# either it can be added to the PATH environment variable.
+ifdef GCC_PATH
+CC = $(GCC_PATH)/$(PREFIX)gcc
+AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
+CP = $(GCC_PATH)/$(PREFIX)objcopy
+SZ = $(GCC_PATH)/$(PREFIX)size
+else
+CC = $(PREFIX)gcc
+AS = $(PREFIX)gcc -x assembler-with-cpp
+CP = $(PREFIX)objcopy
+SZ = $(PREFIX)size
+endif
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary -S
+ 
+#######################################
+# CFLAGS
+#######################################
+# cpu
+# CPU = -mcpu=cortex-m4
+
+# # fpu
+# FPU = -mfpu=fpv4-sp-d16
+
+# # float-abi
+# FLOAT-ABI = -mfloat-abi=hard
+
+# # mcu
+# MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
+
+# macros for gcc
+# AS defines
+AS_DEFS = 
+
+# C defines -DLIB_CONSOLE 
+C_DEFS =  \
+-DBOARD_NSIM \
+-DCURRENT_CORE=arcem \
+-DEMBARC_TCF_GENERATED \
+-DHW_VERSION=10 \
+-DLIB_CLIB \
+-D_HAVE_LIBGLOSS_ \
+-D_HEAPSIZE=8192 \
+-D_HOSTLINK_ \
+-D_NSIM_ \
+-D_STACKSIZE=2048 \
+-D__GNU__
+
+
+
+# AS includes
+AS_INCLUDES = 
+
+# C includes
+KERNEL_INC = \
+		-I $(TOP_DIR)/kernel/core/include  \
+		-I $(TOP_DIR)/kernel/pm/include  \
+		-I $(TOP_DIR)/kernel/hal/include \
+		-I $(TOP_DIR)/arch/arc/nsim/common/include \
+		-I $(TOP_DIR)/arch/arc/nsim/em/gcc \
+		-I $(TOP_DIR)/board/ARC_NSIM_EM/TOS-CONFIG
+		C_INCLUDES += $(KERNEL_INC)
+CMSIS_INC = \
+		-I $(TOP_DIR)/osal/cmsis_os
+		C_INCLUDES += $(CMSIS_INC)
+	
+HAL_DRIVER_INC =  \
+		-I $(TOP_DIR)/board/ARC_NSIM_EM/BSP/Inc \
+		-I $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/include \
+		-I $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/board \
+		-I $(TOP_DIR)/platform/vendor_bsp/embarc_bsp/library
+		C_INCLUDES += $(HAL_DRIVER_INC)
+
+# compile gcc flags
+ASFLAGS = -mcpu=em4_dmips -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter --param l1-cache-size=16384 --param l1-cache-line-size=32 $(C_DEFS) $(C_INCLUDES) $(OPT) -fdata-sections -ffunction-sections -std=gnu99
+
+CFLAGS = -mcpu=em4_dmips -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter --param l1-cache-size=16384 --param l1-cache-line-size=32  $(C_DEFS) $(C_INCLUDES) $(OPT) -fdata-sections -ffunction-sections -std=gnu99
+
+# ifeq ($(DEBUG), 1)
+# CFLAGS += -g -gdwarf-2
+# endif
+
+
+# Generate dependency information
+CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
+
+
+#######################################
+# LDFLAGS
+#######################################
+# link script
+LDSCRIPT = linker_template_gnu.ldf
+
+# libraries
+LIBS = -lc -lm -lnosys 
+LIBDIR = 
+LDFLAGS = --specs=nsim.specs -mcpu=em4_dmips -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter --param l1-cache-size=16384 --param l1-cache-line-size=32 $(LIBDIR) $(LIBS) -mno-sdata -nostartfiles -Wl,-M,-Map=$(BUILD_DIR)/$(TARGET).map -lm -Wl,--script=$(LDSCRIPT)
+
+# default action: build all
+all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
+
+
+#######################################
+# build the application
+#######################################
+# list of objects
+OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
+vpath %.c $(sort $(dir $(C_SOURCES)))
+# list of ASM program objects
+OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
+vpath %.s $(sort $(dir $(ASM_SOURCES)))
+OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES_S:.S=.o)))
+vpath %.S $(sort $(dir $(ASM_SOURCES_S)))
+
+$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 
+	$(CC) -c $(CFLAGS) $< -o $@
+
+$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
+	$(AS) -c $(CFLAGS) $< -o $@
+	
+$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR)
+	$(AS) -c $(CFLAGS) $< -o $@
+
+$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
+	$(CC) $(OBJECTS) $(LDFLAGS) -o $@
+	$(SZ) $@
+
+$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+	$(HEX) $< $@
+	
+$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+	$(BIN) $< $@	
+	
+$(BUILD_DIR):
+	mkdir $@		
+
+#######################################
+# clean up
+#######################################
+clean:
+	-rm -fR $(BUILD_DIR)
+  
+#######################################
+# dependencies
+#######################################
+-include $(wildcard $(BUILD_DIR)/*.d)
+
+# *** EOF ***
--- a/board/ARC_NSIM_EM/GCC/hello_world/linker_template_gnu.ldf
+++ b/board/ARC_NSIM_EM/GCC/hello_world/linker_template_gnu.ldf
@@ -0,0 +1,96 @@
+MEMORY
+{
+ ICCM : ORIGIN = 0x00000000, LENGTH = 0x80000
+ DCCM : ORIGIN = 0x80000000, LENGTH = 0x80000
+}
+ENTRY(_start)
+SECTIONS
+{
+ .init :
+ {
+  _f_init = .;
+  KEEP (*(.init_vector))
+  KEEP (*(.init_bootstrap))
+  _e_init = .;
+ } > ICCM
+ .vector : ALIGN(1024)
+ {
+  _f_vector = .;
+  *(.vector)
+  _e_vector = .;
+ } > ICCM
+ .text : ALIGN(4)
+ {
+  _f_text = .;
+  *(.text .text.* .gnu.linkonce.t.*)
+  _e_text = .;
+ } > ICCM
+ .rodata : ALIGN(4)
+ {
+  _f_rodata = .;
+  . = ALIGN(4);
+  __CTOR_LIST__ = .;
+  LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+  KEEP(*(SORT_BY_NAME(".ctors*")))
+  LONG(0)
+  __CTOR_END__ = .;
+  . = ALIGN(4);
+  __init_array_start = .;
+  KEEP(*(SORT_BY_NAME(".init_array*")))
+  __init_array_end = .;
+  . = ALIGN(4);
+  __DTOR_LIST__ = .;
+  LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+  KEEP(*(SORT_BY_NAME(".dtors*")))
+  LONG(0)
+  __DTOR_END__ = .;
+  *(.rodata .rodata.* .gnu.linkonce.r.*)
+  _e_rodata = .;
+ } > ICCM
+ .data : ALIGN(4)
+ {
+  _f_data = .;
+  *(.data .data.* .gnu.linkonce.d.*)
+  _f_sdata = .;
+  __SDATA_BEGIN__ = .;
+  *(.sdata .sdata.* .gnu.linkonce.s.*)
+  _e_sdata = .;
+  _e_data = .;
+ } > DCCM AT > ICCM
+ .bss (NOLOAD) : ALIGN(8)
+ {
+  PROVIDE (__sbss_start = .);
+  PROVIDE (___sbss_start = .);
+  _f_bss = .;
+  _f_sbss = .;
+  *(.dynsbss)
+  *(.sbss .sbss.* .gnu.linkonce.sb.*)
+  *(.scommon)
+  _e_sbss = .;
+  PROVIDE (__sbss_end = .);
+  PROVIDE (___sbss_end = .);
+  *(.dynbss)
+  *(.bss .bss.* .gnu.linkonce.b.*)
+  *(COMMON)
+  _e_bss = .;
+ } > DCCM
+ .stack (NOLOAD) :
+ {
+  . = ALIGN(4);
+  _f_stack = .;
+  . = . + 2048;
+  _e_stack = .;
+ } > DCCM
+ .heap (NOLOAD) :
+ {
+  . = ALIGN(4);
+  __start_heap = . ;
+  _f_heap = .;
+  . = . + 8192;
+  _e_heap = .;
+  __end_heap = . ;
+ } > DCCM
+ _load_addr_text = LOADADDR(.text);
+ _load_addr_rodata = LOADADDR(.rodata);
+ _load_addr_data = LOADADDR(.data);
+}
--- a/board/ARC_NSIM_EM/TOS-CONFIG/tos_config.h
+++ b/board/ARC_NSIM_EM/TOS-CONFIG/tos_config.h
@@ -0,0 +1,55 @@
+#ifndef _TOS_CONFIG_H_
+#define  _TOS_CONFIG_H_
+
+#include "nsim.h"
+
+#define TOS_CFG_TASK_PRIO_MAX           10u
+
+#define TOS_CFG_ROUND_ROBIN_EN          0u
+
+#define TOS_CFG_OBJECT_VERIFY_EN           1u
+
+#define TOS_CFG_TASK_DYNAMIC_CREATE_EN  1u
+
+#define TOS_CFG_EVENT_EN                1u
+
+#define TOS_CFG_MMBLK_EN                1u
+
+#define TOS_CFG_MMHEAP_EN               1u
+
+#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN  1u
+
+#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE        0x8000
+
+#define TOS_CFG_MUTEX_EN                1u
+
+#define TOS_CFG_MESSAGE_QUEUE_EN        1u
+
+#define TOS_CFG_MAIL_QUEUE_EN           1u
+
+#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN	1u
+
+#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN	1u
+
+#define TOS_CFG_TIMER_EN                1u
+
+#define TOS_CFG_PWR_MGR_EN              0u
+
+#define TOS_CFG_TICKLESS_EN             0u
+
+#define TOS_CFG_SEM_EN                  1u
+
+#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN      1u
+
+#define TOS_CFG_FAULT_BACKTRACE_EN      0u
+
+#define TOS_CFG_IDLE_TASK_STK_SIZE      128u
+
+#define TOS_CFG_CPU_TICK_PER_SECOND     1000u
+
+#define TOS_CFG_CPU_CLOCK               (CLK_CPU)
+
+#define TOS_CFG_TIMER_AS_PROC           1u
+
+#endif
+