PowLu/TencentOS-tiny
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

add ch32v307 risc-v support,IDE is MounRiver Studio

Browse Source
This commit is contained in:
supowang
2022-03-04 14:16:19 +08:00
parent 9de2090de9
commit 7375f16efc
88 changed files with 31620 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

94
arch/risc-v/risc-v3a/rv32i/gcc/port.h Normal file
View File

@@ -0,0 +1,94 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_H_
#define _PORT_H_
#ifndef __ASSEMBLER__
/* defined by wch */
#define GET_INT_SP() {asm("mv t0, sp");asm("lw sp, k_irq_stk_top");asm("sw t0,0(sp)");}
#define FREE_INT_SP() {asm("lw sp,0(sp)");}
__PORT__ void sw_clearpend(void);
__PORT__ void port_int_disable(void); //at port.s
__PORT__ void port_int_enable(void); //at port.s
/* risc-v <20><>cpsr<73><72><EFBFBD>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD>ȡmstatus,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MIE */
__PORT__ cpu_cpsr_t port_cpsr_save(void); //at port.s
/* risc-v <20><>cpsr,<2C>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD>mstatus<75><73>ֵ */
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); //at port.s
__PORT__ void port_cpu_reset(void); //at port.c
__PORT__ void port_sched_start(void) __NO_RETURN__; //at port.s
__PORT__ void port_context_switch(void); //at port.c
__PORT__ void port_irq_context_switch(void); //at port.c
__PORT__ void port_systick_config(uint32_t cycle_per_tick); //at port.c
__PORT__ void port_systick_priority_set(uint32_t prio); //at port.c
__PORT__ void port_cpu_init(); //at port.c
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#endif /* __ASSEMBLER__ */
#define REGBYTES 4
#endif /* _PORT_H_ */

148
arch/risc-v/risc-v3a/rv32i/gcc/port_c.c Normal file
View File

@@ -0,0 +1,148 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include <tos_k.h>
#include "ch32v30x.h"
#include "core_riscv.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
/* clear soft interrupt */
__PORT__ void sw_clearpend(void)
{
SysTick->CTLR &= ~(1<<31);
}
/* trigger software interrupt */
__PORT__ void port_context_switch(void)
{
SysTick->CTLR |= (1<<31);
}
/* trigger software interrupt */
__PORT__ void port_irq_context_switch(void)
{
SysTick->CTLR |= (1<<31);
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
SysTick->CTLR=0;
SysTick->SR=0;
SysTick->CNT=0;
SysTick->CMP=cycle_per_tick-1;
SysTick->CTLR=0xF;
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTicK_IRQn, prio);
}
__PORT__ void port_cpu_init()
{
NVIC_SetPriority(Software_IRQn,0xf0);
NVIC_EnableIRQ(SysTicK_IRQn);
NVIC_EnableIRQ(Software_IRQn);
}
void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void SysTick_Handler(void)
{
GET_INT_SP(); /* <20>л<EFBFBD><D0BB>ж<EFBFBD>ջ */
if (tos_knl_is_running())
{
tos_knl_irq_enter();
SysTick->SR=0;
tos_tick_handler();
tos_knl_irq_leave();
}
FREE_INT_SP(); /* <20>ͷ<EFBFBD><CDB7>ж<EFBFBD>ջ */
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = 0xffffffff; // systick <20><>64λ<34><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>32λ
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTLR |= (3<<0);
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTLR &= ~(3<<0);
}
__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
{
return 0xffffffff;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
port_systick_config(cycle_per_tick);
}
__PORT__ void port_systick_pending_reset(void)
{
PFIC->IPRR[0] |= (1<<12); //clear pend
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
/* only CPU sleep */
PFIC->SCTLR |= (1<<2);
__WFI();
PFIC->SCTLR &= ~(1<<2);
}
__PORT__ void port_stop_mode_enter(void)
{
PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
PWR_EnterSTANDBYMode();
}
#endif

142
arch/risc-v/risc-v3a/rv32i/gcc/port_config.h Normal file
View File

@@ -0,0 +1,142 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
/* FPU is used */
#define ARCH_RISCV_FPU 0u
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u
#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN
/* int reg offset table */
#define __reg_mepc_OFFSET 0x00
#define __reg_mstatus_OFFSET 0x04
#define __reg_x1_OFFSET 0x08
#define __reg_x3_OFFSET 0x0C
#define __reg_x4_OFFSET 0x10
#define __reg_x5_OFFSET 0x14
#define __reg_x6_OFFSET 0x18
#define __reg_x7_OFFSET 0x1C
#define __reg_x8_OFFSET 0x20
#define __reg_x9_OFFSET 0x24
#define __reg_x10_OFFSET 0x28
#define __reg_x11_OFFSET 0x2C
#define __reg_x12_OFFSET 0x30
#define __reg_x13_OFFSET 0x34
#define __reg_x14_OFFSET 0x38
#define __reg_x15_OFFSET 0x3C
#define __reg_x16_OFFSET 0x40
#define __reg_x17_OFFSET 0x44
#define __reg_x18_OFFSET 0x48
#define __reg_x19_OFFSET 0x4C
#define __reg_x20_OFFSET 0x50
#define __reg_x21_OFFSET 0x54
#define __reg_x22_OFFSET 0x58
#define __reg_x23_OFFSET 0x5C
#define __reg_x24_OFFSET 0x60
#define __reg_x25_OFFSET 0x64
#define __reg_x26_OFFSET 0x68
#define __reg_x27_OFFSET 0x6C
#define __reg_x28_OFFSET 0x70
#define __reg_x29_OFFSET 0x74
#define __reg_x30_OFFSET 0x78
#define __reg_x31_OFFSET 0x7C
#define __reg_mepc__OFFSET __reg_mepc_OFFSET
#define __reg_mstatus__OFFSET __reg_mstatus_OFFSET
#define __reg_ra__OFFSET __reg_x1_OFFSET
#define __reg_gp__OFFSET __reg_x3_OFFSET
#define __reg_tp__OFFSET __reg_x4_OFFSET
#define __reg_t0__OFFSET __reg_x5_OFFSET
#define __reg_t1__OFFSET __reg_x6_OFFSET
#define __reg_t2__OFFSET __reg_x7_OFFSET
#define __reg_s0__OFFSET __reg_x8_OFFSET
#define __reg_fp__OFFSET __reg_x8_OFFSET
#define __reg_s1__OFFSET __reg_x9_OFFSET
#define __reg_a0__OFFSET __reg_x10_OFFSET
#define __reg_a1__OFFSET __reg_x11_OFFSET
#define __reg_a2__OFFSET __reg_x12_OFFSET
#define __reg_a3__OFFSET __reg_x13_OFFSET
#define __reg_a4__OFFSET __reg_x14_OFFSET
#define __reg_a5__OFFSET __reg_x15_OFFSET
#define __reg_a6__OFFSET __reg_x16_OFFSET
#define __reg_a7__OFFSET __reg_x17_OFFSET
#define __reg_s2__OFFSET __reg_x18_OFFSET
#define __reg_s3__OFFSET __reg_x19_OFFSET
#define __reg_s4__OFFSET __reg_x20_OFFSET
#define __reg_s5__OFFSET __reg_x21_OFFSET
#define __reg_s6__OFFSET __reg_x22_OFFSET
#define __reg_s7__OFFSET __reg_x23_OFFSET
#define __reg_s8__OFFSET __reg_x24_OFFSET
#define __reg_s9__OFFSET __reg_x25_OFFSET
#define __reg_s10__OFFSET __reg_x26_OFFSET
#define __reg_s11__OFFSET __reg_x27_OFFSET
#define __reg_t3__OFFSET __reg_x28_OFFSET
#define __reg_t4__OFFSET __reg_x29_OFFSET
#define __reg_t5__OFFSET __reg_x30_OFFSET
#define __reg_t6__OFFSET __reg_x31_OFFSET
#if ARCH_RISCV_FPU
/* float reg offset table */
#define __reg_f0_OFFSET 0x00
#define __reg_f1_OFFSET 0x04
#define __reg_f2_OFFSET 0x08
#define __reg_f3_OFFSET 0x0C
#define __reg_f4_OFFSET 0x10
#define __reg_f5_OFFSET 0x14
#define __reg_f6_OFFSET 0x18
#define __reg_f7_OFFSET 0x1C
#define __reg_f8_OFFSET 0x20
#define __reg_f9_OFFSET 0x24
#define __reg_f10_OFFSET 0x28
#define __reg_f11_OFFSET 0x2C
#define __reg_f12_OFFSET 0x30
#define __reg_f13_OFFSET 0x34
#define __reg_f14_OFFSET 0x38
#define __reg_f15_OFFSET 0x3C
#define __reg_f16_OFFSET 0x40
#define __reg_f17_OFFSET 0x44
#define __reg_f18_OFFSET 0x48
#define __reg_f19_OFFSET 0x4C
#define __reg_f20_OFFSET 0x50
#define __reg_f21_OFFSET 0x54
#define __reg_f22_OFFSET 0x58
#define __reg_f23_OFFSET 0x5C
#define __reg_f24_OFFSET 0x60
#define __reg_f25_OFFSET 0x64
#define __reg_f26_OFFSET 0x68
#define __reg_f27_OFFSET 0x6C
#define __reg_f28_OFFSET 0x70
#define __reg_f29_OFFSET 0x74
#define __reg_f30_OFFSET 0x78
#define __reg_f31_OFFSET 0x7C
#endif
#endif /* _PORT_CONFIG_H_ */

322
arch/risc-v/risc-v3a/rv32i/gcc/port_s.S Normal file
View File

@@ -0,0 +1,322 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include "port_config.h"
.global port_int_disable
.global port_int_enable
.global port_cpsr_save
.global port_cpsr_restore
.global port_sched_start
.extern k_curr_task
.extern k_next_task
.text
.align 2
.type port_int_disable, %function
port_int_disable:
csrci mstatus, 0x8
ret
.type port_int_enable, %function
port_int_enable:
csrsi mstatus, 0x8
ret
.type port_cpsr_save, %function
port_cpsr_save:
csrrci a0, mstatus, 0x8
ret
.type port_cpsr_restore, %function
port_cpsr_restore:
csrw mstatus, a0
ret
.align 2
.type port_sched_start, %function
port_sched_start:
/* load sp from k_curr_task->sp */
lw t0, k_curr_task
/* sp = k_curr_task->sp */
lw sp, (t0)
j restore_context
.align 2
.type restore_context, %function
restore_context:
// restore context
lw t0, __reg_mepc_OFFSET(sp)
csrw mepc, t0
lw t0, __reg_mstatus_OFFSET(sp)
csrw mstatus, t0
lw x1, __reg_x1_OFFSET(sp)
lw x3, __reg_x3_OFFSET(sp)
lw x4, __reg_x4_OFFSET(sp)
lw x5, __reg_x5_OFFSET(sp)
lw x6, __reg_x6_OFFSET(sp)
lw x7, __reg_x7_OFFSET(sp)
lw x8, __reg_x8_OFFSET(sp)
lw x9, __reg_x9_OFFSET(sp)
lw x10, __reg_x10_OFFSET(sp)
lw x11, __reg_x11_OFFSET(sp)
lw x12, __reg_x12_OFFSET(sp)
lw x13, __reg_x13_OFFSET(sp)
lw x14, __reg_x14_OFFSET(sp)
lw x15, __reg_x15_OFFSET(sp)
lw x16, __reg_x16_OFFSET(sp)
lw x17, __reg_x17_OFFSET(sp)
lw x18, __reg_x18_OFFSET(sp)
lw x19, __reg_x19_OFFSET(sp)
lw x20, __reg_x20_OFFSET(sp)
lw x21, __reg_x21_OFFSET(sp)
lw x22, __reg_x22_OFFSET(sp)
lw x23, __reg_x23_OFFSET(sp)
lw x24, __reg_x24_OFFSET(sp)
lw x25, __reg_x25_OFFSET(sp)
lw x26, __reg_x26_OFFSET(sp)
lw x27, __reg_x27_OFFSET(sp)
lw x28, __reg_x28_OFFSET(sp)
lw x29, __reg_x29_OFFSET(sp)
lw x30, __reg_x30_OFFSET(sp)
lw x31, __reg_x31_OFFSET(sp)
addi sp, sp, 128
#if ARCH_RISCV_FPU
flw f0, __reg_f0_OFFSET(sp)
flw f1, __reg_f1_OFFSET(sp)
flw f2, __reg_f2_OFFSET(sp)
flw f3, __reg_f3_OFFSET(sp)
flw f4, __reg_f4_OFFSET(sp)
flw f5, __reg_f5_OFFSET(sp)
flw f6, __reg_f6_OFFSET(sp)
flw f7, __reg_f7_OFFSET(sp)
flw f8, __reg_f8_OFFSET(sp)
flw f9, __reg_f9_OFFSET(sp)
flw f10, __reg_f10_OFFSET(sp)
flw f11, __reg_f11_OFFSET(sp)
flw f12, __reg_f12_OFFSET(sp)
flw f13, __reg_f13_OFFSET(sp)
flw f14, __reg_f14_OFFSET(sp)
flw f15, __reg_f15_OFFSET(sp)
flw f16, __reg_f16_OFFSET(sp)
flw f17, __reg_f17_OFFSET(sp)
flw f18, __reg_f18_OFFSET(sp)
flw f19, __reg_f19_OFFSET(sp)
flw f20, __reg_f20_OFFSET(sp)
flw f21, __reg_f21_OFFSET(sp)
flw f22, __reg_f22_OFFSET(sp)
flw f23, __reg_f23_OFFSET(sp)
flw f24, __reg_f24_OFFSET(sp)
flw f25, __reg_f25_OFFSET(sp)
flw f26, __reg_f26_OFFSET(sp)
flw f27, __reg_f27_OFFSET(sp)
flw f28, __reg_f28_OFFSET(sp)
flw f29, __reg_f29_OFFSET(sp)
flw f30, __reg_f30_OFFSET(sp)
flw f31, __reg_f31_OFFSET(sp)
addi sp, sp, 128
#endif
mret
/* just switch at Software interrupt */
.align 2
.global SW_handler
SW_handler:
#if ARCH_RISCV_FPU
addi sp, sp, -128
fsw f0, __reg_f0_OFFSET(sp)
fsw f1, __reg_f1_OFFSET(sp)
fsw f2, __reg_f2_OFFSET(sp)
fsw f3, __reg_f3_OFFSET(sp)
fsw f4, __reg_f4_OFFSET(sp)
fsw f5, __reg_f5_OFFSET(sp)
fsw f6, __reg_f6_OFFSET(sp)
fsw f7, __reg_f7_OFFSET(sp)
fsw f8, __reg_f8_OFFSET(sp)
fsw f9, __reg_f9_OFFSET(sp)
fsw f10, __reg_f10_OFFSET(sp)
fsw f11, __reg_f11_OFFSET(sp)
fsw f12, __reg_f12_OFFSET(sp)
fsw f13, __reg_f13_OFFSET(sp)
fsw f14, __reg_f14_OFFSET(sp)
fsw f15, __reg_f15_OFFSET(sp)
fsw f16, __reg_f16_OFFSET(sp)
fsw f17, __reg_f17_OFFSET(sp)
fsw f18, __reg_f18_OFFSET(sp)
fsw f19, __reg_f19_OFFSET(sp)
fsw f20, __reg_f20_OFFSET(sp)
fsw f21, __reg_f21_OFFSET(sp)
fsw f22, __reg_f22_OFFSET(sp)
fsw f23, __reg_f23_OFFSET(sp)
fsw f24, __reg_f24_OFFSET(sp)
fsw f25, __reg_f25_OFFSET(sp)
fsw f26, __reg_f26_OFFSET(sp)
fsw f27, __reg_f27_OFFSET(sp)
fsw f28, __reg_f28_OFFSET(sp)
fsw f29, __reg_f29_OFFSET(sp)
fsw f30, __reg_f30_OFFSET(sp)
fsw f31, __reg_f31_OFFSET(sp)
#endif
addi sp, sp, -128
sw t0, __reg_x5_OFFSET(sp)
/* disable HPE */
li t0, 0x20
csrs 0x804, t0
csrr t0, mstatus
sw t0, __reg_mstatus_OFFSET(sp)
csrr t0, mepc
sw t0, __reg_mepc_OFFSET(sp)
sw x1, __reg_x1_OFFSET(sp)
sw x3, __reg_x3_OFFSET(sp)
sw x4, __reg_x4_OFFSET(sp)
sw x6, __reg_x6_OFFSET(sp)
sw x7, __reg_x7_OFFSET(sp)
sw x8, __reg_x8_OFFSET(sp)
sw x9, __reg_x9_OFFSET(sp)
sw x10, __reg_x10_OFFSET(sp)
sw x11, __reg_x11_OFFSET(sp)
sw x12, __reg_x12_OFFSET(sp)
sw x13, __reg_x13_OFFSET(sp)
sw x14, __reg_x14_OFFSET(sp)
sw x15, __reg_x15_OFFSET(sp)
sw x16, __reg_x16_OFFSET(sp)
sw x17, __reg_x17_OFFSET(sp)
sw x18, __reg_x18_OFFSET(sp)
sw x19, __reg_x19_OFFSET(sp)
sw x20, __reg_x20_OFFSET(sp)
sw x21, __reg_x21_OFFSET(sp)
sw x22, __reg_x22_OFFSET(sp)
sw x23, __reg_x23_OFFSET(sp)
sw x24, __reg_x24_OFFSET(sp)
sw x25, __reg_x25_OFFSET(sp)
sw x26, __reg_x26_OFFSET(sp)
sw x27, __reg_x27_OFFSET(sp)
sw x28, __reg_x28_OFFSET(sp)
sw x29, __reg_x29_OFFSET(sp)
sw x30, __reg_x30_OFFSET(sp)
sw x31, __reg_x31_OFFSET(sp)
/* switch to irq stk */
mv t0, sp
lw sp, k_irq_stk_top /* cpu_init<EFBFBD>м<EFBFBD>ȥһ<EFBFBD><EFBFBD><EFBFBD>ֿռ<EFBFBD> */
sw t0, 0(sp)
/* clear software interrupt */
call sw_clearpend
/* resume sp */
lw sp, 0(sp)
la t0, k_curr_task // t0 = &k_curr_task
la t1, k_next_task // t1 = &k_next_task
// save sp to k_curr_task.sp
lw t2, (t0)
sw sp, (t2)
# switch task
# k_curr_task = k_next_task
lw t1, (t1)
sw t1, (t0)
# load new task sp
lw sp, (t1)
/* new thread restore */
lw t0, __reg_mstatus_OFFSET(sp)
csrw mstatus, t0
lw t0, __reg_mepc_OFFSET(sp)
csrw mepc, t0
lw x1, __reg_x1_OFFSET(sp)
lw x3, __reg_x3_OFFSET(sp)
lw x4, __reg_x4_OFFSET(sp)
lw x5, __reg_x5_OFFSET(sp)
lw x6, __reg_x6_OFFSET(sp)
lw x7, __reg_x7_OFFSET(sp)
lw x8, __reg_x8_OFFSET(sp)
lw x9, __reg_x9_OFFSET(sp)
lw x10, __reg_x10_OFFSET(sp)
lw x11, __reg_x11_OFFSET(sp)
lw x12, __reg_x12_OFFSET(sp)
lw x13, __reg_x13_OFFSET(sp)
lw x14, __reg_x14_OFFSET(sp)
lw x15, __reg_x15_OFFSET(sp)
lw x16, __reg_x16_OFFSET(sp)
lw x17, __reg_x17_OFFSET(sp)
lw x18, __reg_x18_OFFSET(sp)
lw x19, __reg_x19_OFFSET(sp)
lw x20, __reg_x20_OFFSET(sp)
lw x21, __reg_x21_OFFSET(sp)
lw x22, __reg_x22_OFFSET(sp)
lw x23, __reg_x23_OFFSET(sp)
lw x24, __reg_x24_OFFSET(sp)
lw x25, __reg_x25_OFFSET(sp)
lw x26, __reg_x26_OFFSET(sp)
lw x27, __reg_x27_OFFSET(sp)
lw x28, __reg_x28_OFFSET(sp)
lw x29, __reg_x29_OFFSET(sp)
lw x30, __reg_x30_OFFSET(sp)
lw x31, __reg_x31_OFFSET(sp)
addi sp, sp, 128
#if ARCH_RISCV_FPU
flw f0, __reg_f0_OFFSET(sp)
flw f1, __reg_f1_OFFSET(sp)
flw f2, __reg_f2_OFFSET(sp)
flw f3, __reg_f3_OFFSET(sp)
flw f4, __reg_f4_OFFSET(sp)
flw f5, __reg_f5_OFFSET(sp)
flw f6, __reg_f6_OFFSET(sp)
flw f7, __reg_f7_OFFSET(sp)
flw f8, __reg_f8_OFFSET(sp)
flw f9, __reg_f9_OFFSET(sp)
flw f10, __reg_f10_OFFSET(sp)
flw f11, __reg_f11_OFFSET(sp)
flw f12, __reg_f12_OFFSET(sp)
flw f13, __reg_f13_OFFSET(sp)
flw f14, __reg_f14_OFFSET(sp)
flw f15, __reg_f15_OFFSET(sp)
flw f16, __reg_f16_OFFSET(sp)
flw f17, __reg_f17_OFFSET(sp)
flw f18, __reg_f18_OFFSET(sp)
flw f19, __reg_f19_OFFSET(sp)
flw f20, __reg_f20_OFFSET(sp)
flw f21, __reg_f21_OFFSET(sp)
flw f22, __reg_f22_OFFSET(sp)
flw f23, __reg_f23_OFFSET(sp)
flw f24, __reg_f24_OFFSET(sp)
flw f25, __reg_f25_OFFSET(sp)
flw f26, __reg_f26_OFFSET(sp)
flw f27, __reg_f27_OFFSET(sp)
flw f28, __reg_f28_OFFSET(sp)
flw f29, __reg_f29_OFFSET(sp)
flw f30, __reg_f30_OFFSET(sp)
flw f31, __reg_f31_OFFSET(sp)
addi sp, sp, 128
#endif
mret