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fix bug in nrf_enable_rxaddr

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This commit is contained in:
acevest
2020-04-15 18:50:19 +08:00
parent 1585e3731b
commit 7e519fba6a
6 changed files with 130 additions and 160 deletions
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1
arch/risc-v/common/tos_cpu.c
View File

@@ -159,7 +159,6 @@ void cpu_trap_entry(cpu_data_t cause, cpu_context_t *regs)
} }
} }
void eclic_mtip_handler();
void cpu_irq_entry(cpu_data_t irq) void cpu_irq_entry(cpu_data_t irq)
{ {
typedef void (*irq_handler_t)(); typedef void (*irq_handler_t)();

45
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24.c
View File

@@ -141,57 +141,29 @@ void task_nrf24() {
} }
uint8_t data = 0;
nrf_delay(200); nrf_delay(200);
nrf_csn(1);
nrf_hal_csn(1); nrf_ce(0);
nrf_hal_ce(0);
nrf_delay(200); nrf_delay(200);
nrf_set_standby_mode(); nrf_set_standby_mode();
nrf_set_receive_mode(); nrf_set_receive_mode();
nrf_enable_rx_irq();
nrf_enable_rx_irq();
nrf_set_rf_channel(64); nrf_set_rf_channel(64);
nrf_set_datarate(NRF_2Mbps); nrf_set_datarate(NRF_2Mbps);
uint8_t rxaddr[ADDRLEN] = { 0xAA, 0xCC, 0xEE, 0x00, 0x00 }; uint8_t rxaddr[ADDRLEN] = { 0xAA, 0xCC, 0xEE, 0x00, 0x00 };
nrf_set_rxaddr(0, rxaddr, ADDRLEN); nrf_set_rxaddr(0, rxaddr, ADDRLEN);
nrf_enable_dynamic_payload(0); nrf_enable_dynamic_payload(0);
nrf_enable_dynamic_payload(1);
nrf_enable_rxaddr(0); nrf_enable_rxaddr(0);
nrf_enable_rxaddr(1);
print_rxaddr(0);
print_rxaddr(1);
print_rxaddr(2);
nrf_flush_rx();
while(1) { while(1) {
tos_sem_pend(&sem_nrf_recv, ~0); tos_sem_pend(&sem_nrf_recv, ~0);
uint8_t buf[32]; uint8_t buf[32];
uint8_t len = 0; uint8_t len = 0;
uint8_t status = 0; uint8_t pipe = 0xFF;
nrf_hal_read_reg_byte(REG_STATUS, &status); nrf_read_payload(buf, &len, &pipe);
uint8_t pipe = ((status>>1) & 0x07);
nrf_read_payload(buf, &len);
if(pipe >= 6) {
printf("shit happens\n");
}
nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR));
nrf_flush_rx();
printf("received %u bytes from pipe %u: ", len, pipe); printf("received %u bytes from pipe %u: ", len, pipe);
@@ -201,12 +173,10 @@ void task_nrf24() {
printf("%x ", buf[i]); printf("%x ", buf[i]);
} }
printf("\n"); printf("\n");
}
} }
} #if 0
uint8_t nrf_hal_test_rx_old() { uint8_t nrf_hal_test_rx_old() {
uint8_t data = 0; uint8_t data = 0;
@@ -341,3 +311,4 @@ uint8_t nrf_hal_test_tx() {
return data; return data;
} }
#endif

91
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01.c
View File

@@ -1,6 +1,37 @@
#include "nrf24l01.h" #include "nrf24l01.h"
#include "tos_k.h" #include "tos_k.h"
static int _nrf_clear_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
if(0 != nrf_hal_read_reg_byte(reg, &v)) {
return -1;
}
v &= ~_BV(bit);
if(0 != nrf_hal_write_reg_byte(reg, v)) {
return -1;
}
return 0;
}
static int _nrf_set_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
if(0 != nrf_hal_read_reg_byte(reg, &v)) {
return -1;
}
v |= _BV(bit);
if(0 != nrf_hal_write_reg_byte(reg, v)) {
return -1;
}
return 0;
}
int nrf_init(void *ni) { int nrf_init(void *ni) {
return nrf_hal_init(ni); return nrf_hal_init(ni);
@@ -21,35 +52,35 @@ void nrf_delay(uint32_t delay) {
int nrf_powerup() { int nrf_powerup() {
return nrf_hal_set_reg_bit(REG_CONFIG, PWR_UP); return _nrf_set_reg_bit(REG_CONFIG, PWR_UP);
} }
int nrf_powerdown() { int nrf_powerdown() {
return nrf_hal_clear_reg_bit(REG_CONFIG, PWR_UP); return _nrf_clear_reg_bit(REG_CONFIG, PWR_UP);
} }
void nrf_enable_rx_irq() { void nrf_enable_rx_irq() {
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_RX_DR); _nrf_clear_reg_bit(REG_CONFIG, MASK_RX_DR);
} }
void nrf_disable_rx_irq() { void nrf_disable_rx_irq() {
nrf_hal_set_reg_bit(REG_CONFIG, MASK_RX_DR); _nrf_set_reg_bit(REG_CONFIG, MASK_RX_DR);
} }
void nrf_enable_tx_irq() { void nrf_enable_tx_irq() {
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_TX_DS); _nrf_clear_reg_bit(REG_CONFIG, MASK_TX_DS);
} }
void nrf_disable_tx_irq() { void nrf_disable_tx_irq() {
nrf_hal_set_reg_bit(REG_CONFIG, MASK_TX_DS); _nrf_set_reg_bit(REG_CONFIG, MASK_TX_DS);
} }
void nrf_enable_max_rt_irq() { void nrf_enable_max_rt_irq() {
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_MAX_RT); _nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
} }
void nrf_disable_max_rt_irq() { void nrf_disable_max_rt_irq() {
nrf_hal_clear_reg_bit(REG_CONFIG, MASK_MAX_RT); _nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
} }
void nrf_set_rf_channel(uint8_t channel) { void nrf_set_rf_channel(uint8_t channel) {
@@ -75,7 +106,7 @@ int nrf_set_rxaddr(uint8_t pipe, uint8_t *addr, uint8_t addrlen) {
int nrf_get_addrlen() { int nrf_get_addrlen() {
uint8_t v = 0; uint8_t v = 0;
uint8_t addrlen = 0; uint8_t addrlen = 0;
if(0 != nrf_hal_read_reg_byte(REG_SETUP_AW, v)) { if(0 != nrf_hal_read_reg_byte(REG_SETUP_AW, &v)) {
return 0; return 0;
} }
@@ -124,7 +155,8 @@ int nrf_enable_rxaddr(uint8_t pipe) {
return -1; return -1;
} }
nrf_hal_write_reg_byte(REG_EN_RXADDR, pipe); _nrf_set_reg_bit(REG_EN_RXADDR, pipe);
return 0; return 0;
} }
@@ -135,18 +167,18 @@ void nrf_reset_registers() {
nrf_hal_write_reg_byte(REG_SETUP_AW, _VV(AW_5BYTES, AW)); nrf_hal_write_reg_byte(REG_SETUP_AW, _VV(AW_5BYTES, AW));
nrf_hal_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC)); nrf_hal_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC));
nrf_hal_write_reg_byte(REG_RF_CH, 0b00000010); nrf_hal_write_reg_byte(REG_RF_CH, 0b00000010);
nrf_hal_write_reg_byte(REG_RF_SETUP, _BV(RF_DR_HIGH) | _VV(RF_PWR_0dBm, RF_PWR)); nrf_hal_write_reg_byte(REG_RF_SETUP, _BV(RF_DR) | _VV(RF_PWR_0dBm, RF_PWR));
uint8_t status = 0; uint8_t status = 0;
nrf_hal_read_reg_byte(REG_STATUS, &status); nrf_hal_read_reg_byte(REG_STATUS, &status);
if(status & _BV(RX_DR)) { if(status & _BV(RX_DR)) {
nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR)); _nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
} }
if(status & _BV(TX_DS)) { if(status & _BV(TX_DS)) {
nrf_hal_set_reg_bit(REG_STATUS, _BV(TX_DS)); _nrf_set_reg_bit(REG_STATUS, _BV(TX_DS));
} }
if(status & _BV(MAX_RT)) { if(status & _BV(MAX_RT)) {
nrf_hal_set_reg_bit(REG_STATUS, _BV(MAX_RT)); _nrf_set_reg_bit(REG_STATUS, _BV(MAX_RT));
} }
nrf_hal_write_reg_byte(REG_RX_PW_P0, 0); nrf_hal_write_reg_byte(REG_RX_PW_P0, 0);
@@ -185,7 +217,7 @@ void nrf_set_standby_mode() {
void nrf_set_receive_mode() { void nrf_set_receive_mode() {
nrf_hal_set_reg_bit(REG_CONFIG, PRIM_RX); _nrf_set_reg_bit(REG_CONFIG, PRIM_RX);
nrf_hal_ce(1); nrf_hal_ce(1);
@@ -193,7 +225,7 @@ void nrf_set_receive_mode() {
} }
void nrf_set_send_mode() { void nrf_set_send_mode() {
nrf_hal_clear_reg_bit(REG_CONFIG, PRIM_RX); _nrf_clear_reg_bit(REG_CONFIG, PRIM_RX);
nrf_hal_ce(1); nrf_hal_ce(1);
@@ -205,7 +237,7 @@ void nrf_enable_autoack(uint8_t pipe) {
return ; return ;
} }
nrf_hal_set_reg_bit(REG_EN_AA, pipe); _nrf_set_reg_bit(REG_EN_AA, pipe);
} }
void nrf_disable_autoack(uint8_t pipe) { void nrf_disable_autoack(uint8_t pipe) {
@@ -213,7 +245,7 @@ void nrf_disable_autoack(uint8_t pipe) {
return ; return ;
} }
nrf_hal_clear_reg_bit(REG_EN_AA, pipe); _nrf_clear_reg_bit(REG_EN_AA, pipe);
} }
@@ -252,15 +284,36 @@ int nrf_enable_dynamic_payload(uint8_t pipe) {
} }
int nrf_read_payload(uint8_t *buf, uint8_t *len) { int nrf_read_payload(uint8_t *buf, uint8_t *len, uint8_t *pipe) {
// 读数据通道
uint8_t status = 0;
nrf_hal_read_reg_byte(REG_STATUS, &status);
*pipe = ((status>>1) & 0x07);
// 读数据长度
nrf_hal_cmd_read_byte(CMD_R_RX_PL_WID, len); nrf_hal_cmd_read_byte(CMD_R_RX_PL_WID, len);
// 读数据
nrf_hal_cmd_read(CMD_R_RX_PAYLOAD, buf, *len); nrf_hal_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
// 清除数据标志位
_nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
// 清空接收缓冲区
nrf_flush_rx();
return 0; return 0;
} }
int nrf_write_payload(uint8_t *buf, uint8_t len) { int nrf_write_payload(uint8_t *buf, uint8_t len) {
return nrf_hal_cmd_write(CMD_W_TX_PAYLOAD_NOACK, buf, len); return nrf_hal_cmd_write(CMD_W_TX_PAYLOAD_NOACK, buf, len);
} }
void nrf_ce(uint8_t mode) {
nrf_hal_ce(mode);
}
void nrf_csn(uint8_t mode) {
nrf_hal_csn(mode);
}

69
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01.h
View File

@@ -3,14 +3,6 @@
#include "nrf24l01_hal.h" #include "nrf24l01_hal.h"
#if defined(__SI24R1__) && defined(__NRF24L01__)
#error "you must choose chip between SI24R1 and NRF24L01"
#endif
#if !defined(__SI24R1__) && !defined(__NRF24L01__)
#error "you must specify the core chip of NRF24L01"
#endif
typedef struct { typedef struct {
void *private; void *private;
} nrf_init_t; } nrf_init_t;
@@ -126,45 +118,63 @@ typedef struct {
#define REG_RF_SETUP 0x06 #define REG_RF_SETUP 0x06
#define RF_DR_LOW 5
#define PLL_LOCK 4 // 仅用在测试 #define PLL_LOCK 4 // 仅用在测试
#define RF_DR_HIGH 3
// Air Data Rate // Air Data Rate
// 0 1Mbps // 0 1Mbps
// 1 2Mbps // 1 2Mbps
// 2 250Kbps
#define RF_DR 3 #define RF_DR 3
#define NRF_1Mbps 0 #define NRF_1Mbps 0
#define NRF_2Mbps 1 #define NRF_2Mbps 1
#define NRF_250Kbps 2 // 对于250Kbps的配置需要特别注意
// 因为nRF24L01P(也就是nRF24L01+)和nRF24L01在这里不一样
// nRF24L01P只定义了第3比特位的RF_DR，0为1Mbps,1为2Mbps
// nRF24L01则定义了第3比特位的RF_DR_HIGH和第5比特位的RF_DR_LOW，当RF_DR_HIGH==0 && RF_DR_LOW == 1时设置为250Kbps
// 然而nRF24L01的第5比特位只允许为0，所以无法发送250Kbps
// 因此为了避免两个不同的产品在250Kbps不能通信带来的疑惑和调式程序的麻烦，本程序直接删除了NRF_250Kbps的定义
// 如果确实想用250Kbps，可以自己手动设置
// PWR, 占2:1共2个比特
// 仅用在nRF24L01P芯片上
#define RF_DR_LOW 5
#define RF_DR_HIGH 3
// PWR, 占2:1共2个比特，仅nRF24L01P、nRF24L01有效
// 00 -18dBm // 00 -18dBm
// 01 -12dBm // 01 -12dBm
// 10 -6dBm // 10 -6dBm
// 11 0dBm // 11 0dBm
#if defined(__NRF24L01__)
#define RF_PWR 1 #define RF_PWR 1
#define RF_PWR_n18dBm 0 #define RF_PWR_n18dBm 0
#define RF_PWR_n12dBm 1 #define RF_PWR_n12dBm 1
#define RF_PWR_n6dBm 2 #define RF_PWR_n6dBm 2
#define RF_PWR_0dBm 3 #define RF_PWR_0dBm 3
// Non-P omissions // 仅nRF24L01有效，nRF24L01P没有这位定义
#define LNA_HCURR 0 #define LNA_HCURR 0
#endif
#if defined(__SI24R1__) // 在SI24R1中，针对nRF24L01P没有使用这一位就直接拿来扩充RF_PWR的位数了
#define RF_PWR 0 // 因此在SI24R1中 RF_PWR == 0 占用0:2共3个比特位
#define RF_PWR_n12dBm 0 // 与nRF24L01P的对应关系如下
#define RF_PWR_n6dBm 1 // [2:0] SI24R1 nRF24L01P
#define RF_PWR_n4dBm 2 // 000 -12dBm -18dBm
#define RF_PWR_0dBm 3 // 001 -6dBm
#define RF_PWR_1dBm 4 // 010 -4dBm -12dBm
#define RF_PWR_3dBm 5 // 011 0dBm
#define RF_PWR_4dBm 6 // 100 1dBm -6dBm
#define RF_PWR_7dBm 7 // 101 3dBm
#endif // 110 4dBm 0dBm
// 111 7dBm
// 以下定义仅SI24R1芯片有效
#define SI24R1_PWR 0
#define SI24R1_PWR_n12dBm 0
#define SI24R1_PWR_n6dBm 1
#define SI24R1_PWR_n4dBm 2
#define SI24R1_PWR_0dBm 3
#define SI24R1_PWR_1dBm 4
#define SI24R1_PWR_3dBm 5
#define SI24R1_PWR_4dBm 6
#define SI24R1_PWR_7dBm 7
#define REG_STATUS 0x07 #define REG_STATUS 0x07
@@ -334,9 +344,12 @@ void nrf_set_datarate(uint8_t dr);
int nrf_enable_dynamic_payload(uint8_t pipe); int nrf_enable_dynamic_payload(uint8_t pipe);
int nrf_read_payload(uint8_t *buf, uint8_t *len); int nrf_read_payload(uint8_t *buf, uint8_t *len, uint8_t *pipe);
int nrf_write_payload(uint8_t *buf, uint8_t len); int nrf_write_payload(uint8_t *buf, uint8_t len);
void nrf_ce(uint8_t mode);
void nrf_csn(uint8_t mode);
#endif /* NRF24L01_H_ */ #endif /* NRF24L01_H_ */

60
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01_hal.c
View File

@@ -35,7 +35,6 @@ uint8_t _spi_transfer(uint32_t spi, uint8_t data) {
} }
#if 1
void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) { void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) {
for(uint8_t i=0; i<len; i++) { for(uint8_t i=0; i<len; i++) {
_spi_transfer(spi, buf[i]); _spi_transfer(spi, buf[i]);
@@ -46,34 +45,8 @@ void _spi_recv(uint32_t spi, uint8_t *buf, uint8_t len) {
buf[i] = _spi_transfer(spi, 0xFF); buf[i] = _spi_transfer(spi, 0xFF);
} }
} }
#else
void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) {
int cnt = 0;
//while(cnt < len) {
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_TBE));
spi_i2s_data_transmit(spi, buf[cnt]);
cnt++;
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_RBNE));
spi_i2s_data_receive(spi);
//}
}
void _spi_recv(uint32_t spi, uint8_t *buf, uint8_t len) {
int cnt = 0;
//while(cnt < len) {
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_TBE));
spi_i2s_data_transmit(spi, 0xFF);
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_RBNE));
buf[cnt] = (uint8_t)spi_i2s_data_receive(spi);
cnt++;
//}
}
#endif
int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) { int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) {
uint8_t cmd = CMD_R_REGISTER | reg; uint8_t cmd = CMD_R_REGISTER | reg;
@@ -113,38 +86,6 @@ int nrf_hal_write_reg_byte(uint8_t reg, uint8_t byte)
return nrf_hal_write_reg(reg, &byte, 1); return nrf_hal_write_reg(reg, &byte, 1);
} }
int nrf_hal_set_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
if(0 != nrf_hal_read_reg_byte(reg, &v)) {
return -1;
}
v |= _BV(bit);
if(0 != nrf_hal_write_reg_byte(reg, v)) {
return -1;
}
return 0;
}
int nrf_hal_clear_reg_bit(uint8_t reg, uint8_t bit) {
uint8_t v = 0;
if(0 != nrf_hal_read_reg_byte(reg, &v)) {
return -1;
}
v &= ~_BV(bit);
if(0 != nrf_hal_write_reg_byte(reg, v)) {
return -1;
}
return 0;
}
int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len) { int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len) {
nrf_hal_csn(0); nrf_hal_csn(0);
@@ -170,6 +111,7 @@ int nrf_hal_cmd_write(uint8_t cmd, uint8_t *data, uint8_t len) {
return 0; return 0;
} }
int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data) { int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data) {
return nrf_hal_cmd_read(cmd, data, 1); return nrf_hal_cmd_read(cmd, data, 1);
} }

8
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01_hal.h
View File

@@ -1,8 +1,6 @@
#ifndef NRF24L01_HAL_H_ #ifndef NRF24L01_HAL_H_
#define NRF24L01_HAL_H_ #define NRF24L01_HAL_H_
#define __SI24R1__
#include "gd32vf103.h" #include "gd32vf103.h"
typedef struct { typedef struct {
@@ -26,14 +24,8 @@ int nrf_hal_read_reg_byte(uint8_t reg, uint8_t *v);
int nrf_hal_write_reg(uint8_t reg, uint8_t *buf, uint8_t len); int nrf_hal_write_reg(uint8_t reg, uint8_t *buf, uint8_t len);
int nrf_hal_write_reg_byte(uint8_t reg, uint8_t byte); int nrf_hal_write_reg_byte(uint8_t reg, uint8_t byte);
int nrf_hal_set_reg_bit(uint8_t reg, uint8_t bit);
int nrf_hal_clear_reg_bit(uint8_t reg, uint8_t bit);
int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len); int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len);
int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data); int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data);