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debug nrf24 on longan nano

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This commit is contained in:
acevest
2020-04-14 07:36:45 +08:00
parent 5e87b05e0c
commit 81cf6f0c23
5 changed files with 60 additions and 41 deletions
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3
board/Sipeed_LonganNano/BSP/Src/mcu_init.c
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@@ -3,7 +3,7 @@
void board_init() { void board_init() {
SystemInit(); SystemInit();
#if 0
rcu_periph_clock_enable(RCU_GPIOA); rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOC); rcu_periph_clock_enable(RCU_GPIOC);
@@ -17,4 +17,5 @@ void board_init() {
LCD_Init(); // init LCD LCD_Init(); // init LCD
LCD_Clear(BLACK); LCD_Clear(BLACK);
#endif
} }

16
board/Sipeed_LonganNano/eclipse/nRF24L01/main.c
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@@ -11,7 +11,7 @@
k_task_t led_handle; k_task_t led_handle;
uint8_t task1_stk[TASK_SIZE]; uint8_t task1_stk[TASK_SIZE];
uint8_t task2_stk[TASK_SIZE]; uint8_t task2_stk[TASK_SIZE*8];
uint8_t led_stk[TASK_SIZE/2]; uint8_t led_stk[TASK_SIZE/2];
int share = 0xCBA7F9; int share = 0xCBA7F9;
@@ -85,15 +85,23 @@ void task_led(void *arg)
} }
void main(void) { void main(void) {
board_init(); //board_init();
SystemInit();
nrf24l01_init();
nrf_hal_test_rx();
while(1) { }
usart0_init(115200); usart0_init(115200);
tos_knl_init(); tos_knl_init();
tos_task_create(&task1_handle, "task1", task1, NULL, 3, task1_stk, TASK_SIZE, 0); //tos_task_create(&task1_handle, "task1", task1, NULL, 2, task1_stk, TASK_SIZE, 0);
tos_task_create(&task2_handle, "task2", task2, NULL, 3, task2_stk, TASK_SIZE*4, 0); tos_task_create(&task2_handle, "task2", task2, NULL, 3, task2_stk, TASK_SIZE*8, 0);
//tos_task_create(&led_handle, "led", task_led, NULL, 2, led_stk, TASK_SIZE/2, 0); //tos_task_create(&led_handle, "led", task_led, NULL, 2, led_stk, TASK_SIZE/2, 0);
k_err_t err = tos_sem_create(&sem, 1); k_err_t err = tos_sem_create(&sem, 1);

40
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24.c
View File

@@ -3,9 +3,9 @@
void nrf24l01_init() { void nrf24l01_init() {
rcu_periph_clock_enable(RCU_GPIOA); rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOB); rcu_periph_clock_enable(RCU_GPIOB);
rcu_periph_clock_enable(RCU_AF); //rcu_periph_clock_enable(RCU_AF);
rcu_periph_clock_enable(RCU_SPI0); rcu_periph_clock_enable(RCU_SPI0);
uint32_t spi = SPI0; #define SPIx SPI0
/* spi GPIO config:SCK/PB13, MISO/PB14, MOSI/PB15 */ /* spi GPIO config:SCK/PB13, MISO/PB14, MOSI/PB15 */
@@ -18,12 +18,13 @@ void nrf24l01_init() {
gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
nrf_hal_init_t nhi; nrf_hal_init_t nhi;
nhi.spi = spi; nhi.spi = SPIx;
nhi.ce_port = GPIOA; nhi.ce_port = GPIOA;
nhi.ce_pin = GPIO_PIN_3; nhi.ce_pin = GPIO_PIN_3;
nhi.csn_port= GPIOA; nhi.csn_port= GPIOB;
nhi.csn_pin = GPIO_PIN_4; nhi.csn_pin = GPIO_PIN_5;
gpio_init(nhi.ce_port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, nhi.ce_pin); gpio_init(nhi.ce_port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, nhi.ce_pin);
gpio_init(nhi.csn_port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, nhi.csn_pin); gpio_init(nhi.csn_port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, nhi.csn_pin);
@@ -31,29 +32,36 @@ void nrf24l01_init() {
gpio_bit_set(nhi.ce_port, nhi.ce_pin); gpio_bit_set(nhi.ce_port, nhi.ce_pin);
gpio_bit_set(nhi.csn_port, nhi.csn_pin); gpio_bit_set(nhi.csn_port, nhi.csn_pin);
nrf_init(&nhi);
spi_parameter_struct spi_init_struct; spi_parameter_struct spi_init_struct;
/* deinitilize SPI and the parameters */ /* deinitilize SPI and the parameters */
spi_i2s_deinit(spi); spi_i2s_deinit(SPIx);
spi_struct_para_init(&spi_init_struct); spi_struct_para_init(&spi_init_struct);
/* spi parameter config */ /* spi parameter config */
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_MASTER; spi_init_struct.device_mode = SPI_MASTER;
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
spi_init_struct.nss = SPI_NSS_SOFT; spi_init_struct.nss = SPI_NSS_SOFT;
spi_init_struct.prescale = SPI_PSC_16; spi_init_struct.prescale = SPI_PSC_16;
spi_init_struct.endian = SPI_ENDIAN_MSB; spi_init_struct.endian = SPI_ENDIAN_MSB;
spi_init(spi, &spi_init_struct);
//spi_i2s_data_frame_format_config(spi, SPI_FRAMESIZE_8BIT);
//spi_crc_polynomial_set(spi,7);
//spi_crc_on(spi);
//spi_ti_mode_disable(spi); // use motorola mode
//spi_nssp_mode_enable(spi);
spi_enable(spi); spi_init(SPIx, &spi_init_struct);
//spi_i2s_data_frame_format_config(SPIx, SPI_FRAMESIZE_8BIT);
spi_crc_polynomial_set(SPIx,7);
//spi_crc_on(SPIx);
//spi_ti_mode_disable(SPIx); // use motorola mode
//spi_nssp_mode_enable(SPIx);
//spi_i2s_interrupt_disable(SPIx, SPI_I2S_INT_TBE);
//spi_i2s_interrupt_disable(SPIx, SPI_I2S_INT_RBNE);
//spi_i2s_interrupt_disable(SPIx, SPI_I2S_INT_ERR);
spi_enable(SPIx);
nrf_init(&nhi);
} }

7
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01.c
View File

@@ -248,6 +248,13 @@ uint8_t nrf_hal_test_rx() {
nrf_delay(200); nrf_delay(200);
while(1) {
nrf_hal_write_reg_byte(REG_CONFIG, _BV(EN_CRC));
nrf_hal_read_reg_byte(REG_CONFIG, &data);
nrf_delay(100);
}
nrf_set_standby_mode(); nrf_set_standby_mode();

29
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01_hal.c
View File

@@ -15,43 +15,38 @@ int nrf_hal_init(nrf_hal_init_t *private) {
} }
void nrf_hal_csn(uint8_t mode) { void nrf_hal_csn(uint8_t mode) {
gpio_bit_write(nhi.csn_port, nhi.csn_pin, mode == 0 ? RESET : SET); //gpio_bit_write(nhi.csn_port, nhi.csn_pin, mode == 0 ? RESET : SET);
//mode == 0 ? gpio_bit_reset(nhi.csn_port, nhi.csn_pin) : gpio_bit_set(nhi.csn_port, nhi.csn_pin); mode == 0 ? gpio_bit_reset(nhi.csn_port, nhi.csn_pin) : gpio_bit_set(nhi.csn_port, nhi.csn_pin);
} }
void nrf_hal_ce(uint8_t mode) { void nrf_hal_ce(uint8_t mode) {
gpio_bit_write(nhi.ce_port, nhi.ce_pin, mode == 0 ? RESET : SET); //gpio_bit_write(nhi.ce_port, nhi.ce_pin, mode == 0 ? RESET : SET);
//mode == 0 ? gpio_bit_reset(nhi.ce_port, nhi.ce_pin) : gpio_bit_set(nhi.ce_port, nhi.ce_pin); mode == 0 ? gpio_bit_reset(nhi.ce_port, nhi.ce_pin) : gpio_bit_set(nhi.ce_port, nhi.ce_pin);
} }
void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) { void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) {
if(buf == 0) {
return;
}
int cnt = 0; int cnt = 0;
while(cnt < len) { while(cnt < len) {
if(SET == spi_i2s_flag_get(spi, SPI_FLAG_TBE)) { if(RESET == spi_i2s_flag_get(spi, SPI_FLAG_TBE)) {
continue;
}
spi_i2s_data_transmit(spi, buf[cnt]); spi_i2s_data_transmit(spi, buf[cnt]);
cnt++; cnt++;
} }
}
} }
void _spi_recv(uint32_t spi, uint8_t *buf, uint8_t len) { void _spi_recv(uint32_t spi, uint8_t *buf, uint8_t len) {
if(buf == 0) {
return ;
}
int cnt = 0; int cnt = 0;
while(cnt < len) { while(cnt < len) {
FlagStatus ret = spi_i2s_flag_get(spi, SPI_FLAG_RBNE); if(RESET == spi_i2s_flag_get(spi, SPI_FLAG_RBNE)) {
if(SET == ret) { continue;
}
buf[cnt] = (uint8_t)spi_i2s_data_receive(spi); buf[cnt] = (uint8_t)spi_i2s_data_receive(spi);
cnt++; cnt++;
} }
}
} }
int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) { int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) {