add mqttclient to the component, and add fire stm32f429 board demo.
This commit is contained in:
jiejieTop
@@ -0,0 +1,48 @@
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// File: STM32F405_415_407_417_427_437_429_439.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
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// refer to STM32F40x STM32F41x datasheets
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// refer to STM32F42x STM32F43x datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug Standby Mode
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// <o.1> DBG_STOP <i> Debug Stop Mode
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// <o.0> DBG_SLEEP <i> Debug Sleep Mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
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// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
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// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
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// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
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// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <<< end of configuration section >>>
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@@ -0,0 +1,9 @@
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<?xml version="1.0" encoding="utf-8"?>
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<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
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<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
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<events>
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</events>
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</component_viewer>
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@@ -0,0 +1,15 @@
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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LR_IROM1 0x08000000 0x00100000 { ; load region size_region
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ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 0x20000000 0x00030000 { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@@ -0,0 +1,20 @@
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/*
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* Auto generated Run-Time-Environment Component Configuration File
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* *** Do not modify ! ***
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*
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* Project: 'TencentOS_tiny'
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* Target: 'TencentOS_tiny'
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*/
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#ifndef RTE_COMPONENTS_H
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#define RTE_COMPONENTS_H
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/*
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* Define the Device Header File:
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*/
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#define CMSIS_device_header "stm32f4xx.h"
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#endif /* RTE_COMPONENTS_H */
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@@ -0,0 +1,235 @@
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/**
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******************************************************************************
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* @file lwipopts.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 31-July-2013
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* @brief lwIP Options Configuration.
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* This file is based on Utilities\lwip_v1.4.1\src\include\lwip\opt.h
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* and contains the lwIP configuration for the STM32F4x7 demonstration.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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#ifndef __LWIPOPTS_H__
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#define __LWIPOPTS_H__
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/**
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* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
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* critical regions during buffer allocation, deallocation and memory
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* allocation and deallocation.
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*/
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#define SYS_LIGHTWEIGHT_PROT 1
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/**
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* NO_SYS==1: Provides VERY minimal functionality. Otherwise,
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* use lwIP facilities.
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*/
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#define NO_SYS 0
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/**
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* NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
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* Mainly for compatibility to old versions.
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*/
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#define NO_SYS_NO_TIMERS 0
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/* ---------- Memory options ---------- */
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/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
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lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
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byte alignment -> define MEM_ALIGNMENT to 2. */
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#define MEM_ALIGNMENT 4
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/* MEM_SIZE: the size of the heap memory. If the application will send
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a lot of data that needs to be copied, this should be set high. */
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#define MEM_SIZE (5 * 1024)
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/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
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sends a lot of data out of ROM (or other static memory), this
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should be set high. */
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#define MEMP_NUM_PBUF 25
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/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
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per active UDP "connection". */
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#define MEMP_NUM_UDP_PCB 4
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/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
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connections. */
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#define MEMP_NUM_TCP_PCB 6
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/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
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connections. */
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#define MEMP_NUM_TCP_PCB_LISTEN 6
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/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
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segments. */
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#define MEMP_NUM_TCP_SEG 150
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/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
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timeouts. */
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#define MEMP_NUM_SYS_TIMEOUT 6
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/* ---------- Pbuf options ---------- */
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/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
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#define PBUF_POOL_SIZE 25
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/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
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#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS + 40 + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN)
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/* ---------- TCP options ---------- */
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#define LWIP_TCP 1
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#define TCP_TTL 255
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/* Controls if TCP should queue segments that arrive out of
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order. Define to 0 if your device is low on memory. */
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#define TCP_QUEUE_OOSEQ 0
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/* TCP Maximum segment size. */
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#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */
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/* TCP sender buffer space (bytes). */
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#define TCP_SND_BUF (7 * TCP_MSS)
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/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
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as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */
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#define TCP_SND_QUEUELEN (8 * TCP_SND_BUF / TCP_MSS)
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/* TCP receive window. */
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#define TCP_WND (9 * TCP_MSS)
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/* ---------- ICMP options ---------- */
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#define LWIP_ICMP 1
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/* ---------- DHCP options ---------- */
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/* Define LWIP_DHCP to 1 if you want DHCP configuration of
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interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
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turning this on does currently not work. */
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#define LWIP_DHCP 1
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/* ---------- UDP options ---------- */
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#define LWIP_UDP 1
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#define UDP_TTL 255
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/* ---------- Statistics options ---------- */
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#define LWIP_STATS 0
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#define LWIP_PROVIDE_ERRNO 1
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/* ---------- link callback options ---------- */
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/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
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* whenever the link changes (i.e., link down)
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*/
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#define LWIP_NETIF_LINK_CALLBACK 0
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/*
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--------------------------------------
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---------- Checksum options ----------
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--------------------------------------
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*/
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/*
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The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
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- To use this feature let the following define uncommented.
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- To disable it and process by CPU comment the the checksum.
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*/
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#define CHECKSUM_BY_HARDWARE
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//#undef CHECKSUM_BY_HARDWARE
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#ifdef CHECKSUM_BY_HARDWARE
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/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
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#define CHECKSUM_GEN_IP 0
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/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
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#define CHECKSUM_GEN_UDP 0
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/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
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#define CHECKSUM_GEN_TCP 0
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/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
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#define CHECKSUM_CHECK_IP 0
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/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
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#define CHECKSUM_CHECK_UDP 0
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/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
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#define CHECKSUM_CHECK_TCP 0
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/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/
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#define CHECKSUM_GEN_ICMP 0
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#else
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/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
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#define CHECKSUM_GEN_IP 1
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/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
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#define CHECKSUM_GEN_UDP 1
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/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
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#define CHECKSUM_GEN_TCP 1
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/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
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#define CHECKSUM_CHECK_IP 1
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/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
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#define CHECKSUM_CHECK_UDP 1
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/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
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#define CHECKSUM_CHECK_TCP 1
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/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/
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#define CHECKSUM_GEN_ICMP 1
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#endif
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|
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#define LWIP_TCPIP_CORE_LOCKING 1
|
||||
|
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/*
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----------------------------------------------
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---------- Sequential layer options ----------
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----------------------------------------------
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*/
|
||||
/**
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* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
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*/
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#define LWIP_NETCONN 1
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|
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/*
|
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------------------------------------
|
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---------- Socket options ----------
|
||||
------------------------------------
|
||||
*/
|
||||
/**
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* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
|
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*/
|
||||
#define LWIP_SOCKET 1
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||||
|
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/*
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---------------------------------
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---------- OS options ----------
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||||
---------------------------------
|
||||
*/
|
||||
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#define DEFAULT_UDP_RECVMBOX_SIZE 10
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#define DEFAULT_TCP_RECVMBOX_SIZE 10
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#define DEFAULT_ACCEPTMBOX_SIZE 10
|
||||
#define DEFAULT_THREAD_STACKSIZE 1024 * 2
|
||||
|
||||
#define TCPIP_THREAD_NAME "lwip"
|
||||
#define TCPIP_THREAD_STACKSIZE 1024
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||||
#define TCPIP_MBOX_SIZE 10
|
||||
#define TCPIP_THREAD_PRIO 1
|
||||
|
||||
#define LWIP_DNS_API_DECLARE_STRUCTS 1
|
||||
#define LWIP_DNS 1
|
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|
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/** DNS server IP address */
|
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#ifndef DNS_SERVER_ADDRESS
|
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#define DNS_SERVER_ADDRESS(ipaddr) (ip4_addr_set_u32(ipaddr, ipaddr_addr("208.67.222.222"))) /* resolver1.opendns.com */
|
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#endif
|
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|
||||
/*
|
||||
----------------------------------------
|
||||
---------- Lwip Debug options ----------
|
||||
----------------------------------------
|
||||
*/
|
||||
#define LWIP_DEBUG 0
|
||||
|
||||
#define ethernet_with_mac 1
|
||||
|
||||
#endif /* __LWIPOPTS_H__ */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,45 @@
|
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/*
|
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* @Author: jiejie
|
||||
* @Github: https://github.com/jiejieTop
|
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* @Date: 2019-12-15 00:42:16
|
||||
* @LastEditTime : 2020-01-16 00:39:23
|
||||
* @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
|
||||
*/
|
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#ifndef _MQTT_CONFIG_H_
|
||||
#define _MQTT_CONFIG_H_
|
||||
|
||||
#define MQTT_NO 0
|
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#define MQTT_YES 1
|
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|
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#define MQTT_MAX_PACKET_ID (0xFFFF - 1)
|
||||
#define MQTT_TOPIC_LEN_MAX 128
|
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#define MQTT_ACK_HANDLER_NUM_MAX 64
|
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#define MQTT_DEFAULT_BUF_SIZE 1024
|
||||
#define MQTT_DEFAULT_CMD_TIMEOUT 4000
|
||||
#define MQTT_MAX_CMD_TIMEOUT 20000
|
||||
#define MQTT_MIN_CMD_TIMEOUT 1000
|
||||
#define MQTT_KEEP_ALIVE_INTERVAL 20 // unit: second
|
||||
#define MQTT_VERSION 4 // 4 is mqtt 3.1.1
|
||||
#define MQTT_RECONNECT_DEFAULT_DURATION 1000
|
||||
#define MQTT_THREAD_STACK_SIZE 2048
|
||||
#define MQTT_THREAD_PRIO 5
|
||||
#define MQTT_THREAD_TICK 50
|
||||
|
||||
|
||||
#define MQTT_NETWORK_TYPE_TLS MQTT_NO
|
||||
|
||||
|
||||
#if MQTT_NETWORK_TYPE_TLS
|
||||
|
||||
#define MQTT_TLS_HANDSHAKE_TIMEOUT (5 * 1000)
|
||||
|
||||
#include "mbedtls/config.h"
|
||||
#include "mbedtls/ssl.h"
|
||||
#include "mbedtls/entropy.h"
|
||||
#include "mbedtls/net_sockets.h"
|
||||
#include "mbedtls/ctr_drbg.h"
|
||||
#include "mbedtls/error.h"
|
||||
#include "mbedtls/debug.h"
|
||||
#endif /* MQTT_NETWORK_TYPE_TLS */
|
||||
|
||||
#endif /* _MQTT_CONFIG_H_ */
|
||||
@@ -0,0 +1,53 @@
|
||||
#ifndef _TOS_CONFIG_H_
|
||||
#define _TOS_CONFIG_H_
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
#define TOS_CFG_TASK_PRIO_MAX 10u
|
||||
|
||||
#define TOS_CFG_ROUND_ROBIN_EN 1u
|
||||
|
||||
#define TOS_CFG_OBJECT_VERIFY_EN 1u
|
||||
|
||||
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
|
||||
|
||||
#define TOS_CFG_EVENT_EN 1u
|
||||
|
||||
#define TOS_CFG_MMBLK_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x12000
|
||||
|
||||
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u
|
||||
|
||||
#define TOS_CFG_MUTEX_EN 1u
|
||||
|
||||
#define TOS_CFG_TIMER_EN 1u
|
||||
|
||||
#define TOS_CFG_MESSAGE_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_MAIL_QUEUE_EN 0u
|
||||
|
||||
#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 0u
|
||||
|
||||
#define TOS_CFG_SEM_EN 1u
|
||||
|
||||
#define TOS_CFG_PWR_MGR_EN 0u
|
||||
|
||||
#define TOS_CFG_TICKLESS_EN 0u
|
||||
|
||||
#define TOS_CFG_VFS_EN 1u
|
||||
|
||||
#define TOS_CFG_IDLE_TASK_STK_SIZE 80u
|
||||
|
||||
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
|
||||
|
||||
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
|
||||
|
||||
#define TOS_CFG_TIMER_AS_PROC 1u
|
||||
|
||||
#endif
|
||||
|
||||
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3711
board/Fire_STM32F429/KEIL/mqttclient_iothub/TencentOS_tiny.uvoptx
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board/Fire_STM32F429/KEIL/mqttclient_iothub/TencentOS_tiny.uvoptx
Normal file
File diff suppressed because it is too large
Load Diff
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board/Fire_STM32F429/KEIL/mqttclient_iothub/TencentOS_tiny.uvprojx
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1877
board/Fire_STM32F429/KEIL/mqttclient_iothub/TencentOS_tiny.uvprojx
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|
||||
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f429xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32F429x devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
HASH_RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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Reference in New Issue
Block a user