Add NXP i.MXRT1060 EVK board bsp support and IAR demo
This commit is contained in:
Chan Luo
290
board/NXP_EVK_IMXRT1060/bsp/Inc/board.h
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290
board/NXP_EVK_IMXRT1060/bsp/Inc/board.h
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/*
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* Copyright 2018-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#include "clock_config.h"
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#include "fsl_common.h"
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#include "fsl_gpio.h"
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#include "fsl_clock.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief The board name */
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#define BOARD_NAME "MIMXRT1060-EVK"
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/* The UART to use for debug messages. */
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#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
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#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
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#define BOARD_DEBUG_UART_INSTANCE 1U
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#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
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#define BOARD_UART_IRQ LPUART1_IRQn
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#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
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#ifndef BOARD_DEBUG_UART_BAUDRATE
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#define BOARD_DEBUG_UART_BAUDRATE (115200U)
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#endif /* BOARD_DEBUG_UART_BAUDRATE */
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/*! @brief The USER_LED used for board */
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#define LOGIC_LED_ON (0U)
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#define LOGIC_LED_OFF (1U)
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#ifndef BOARD_USER_LED_GPIO
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#define BOARD_USER_LED_GPIO GPIO1
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#endif
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#ifndef BOARD_USER_LED_GPIO_PIN
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#define BOARD_USER_LED_GPIO_PIN (9U)
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#endif
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#define USER_LED_INIT(output) \
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GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
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BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
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#define USER_LED_ON() \
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GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
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#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
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#define USER_LED_TOGGLE() \
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GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
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0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
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/*! @brief Define the port interrupt number for the board switches */
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#ifndef BOARD_USER_BUTTON_GPIO
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#define BOARD_USER_BUTTON_GPIO GPIO5
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#endif
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#ifndef BOARD_USER_BUTTON_GPIO_PIN
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#define BOARD_USER_BUTTON_GPIO_PIN (0U)
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#endif
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#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
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#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
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#define BOARD_USER_BUTTON_NAME "SW8"
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/*! @brief The board flash size */
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#define BOARD_FLASH_SIZE (0x800000U)
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/*! @brief The ENET PHY address. */
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#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
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/* USB PHY condfiguration */
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#define BOARD_USB_PHY_D_CAL (0x0CU)
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#define BOARD_USB_PHY_TXCAL45DP (0x06U)
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#define BOARD_USB_PHY_TXCAL45DM (0x06U)
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#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
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#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
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#define BOARD_ARDUINO_I2C_INDEX (1)
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#define BOARD_USDHC1_BASEADDR USDHC1
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#define BOARD_USDHC2_BASEADDR USDHC2
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#define BOARD_USDHC_CD_GPIO_BASE GPIO2
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#define BOARD_USDHC_CD_GPIO_PIN 28
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#define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
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#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
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#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
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#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
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#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
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#define BOARD_USDHC_CD_GPIO_INIT() \
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{ \
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gpio_pin_config_t sw_config = { \
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kGPIO_DigitalInput, \
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0, \
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kGPIO_IntRisingOrFallingEdge, \
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}; \
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GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
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GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
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GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
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}
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#define BOARD_HAS_SDCARD (1U)
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#define BOARD_SD_POWER_RESET_GPIO (GPIO1)
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#define BOARD_SD_POWER_RESET_GPIO_PIN (19U)
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#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
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#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
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#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
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{ \
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gpio_pin_config_t sw_config = { \
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kGPIO_DigitalOutput, \
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0, \
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kGPIO_NoIntmode, \
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}; \
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GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
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GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
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}
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#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
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{ \
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gpio_pin_config_t sw_config = { \
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kGPIO_DigitalOutput, \
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0, \
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kGPIO_NoIntmode, \
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}; \
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GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
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}
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#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
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(GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
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#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
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#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
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#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
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#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
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#define BOARD_SD_HOST_IRQ USDHC1_IRQn
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#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
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#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
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#define BOARD_MMC_HOST_IRQ USDHC2_IRQn
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#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
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#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
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/* we are using the BB SD socket to DEMO the MMC example,but the
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* SD socket provide 4bit bus only, so we define this macro to avoid
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* 8bit data bus test
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*/
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#define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
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#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
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#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
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/*! @brief The WIFI-QCA shield pin. */
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#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
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#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
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#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
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#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
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#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
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#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
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#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
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#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
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#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
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#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
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#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
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#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
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#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
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#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
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#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
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#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
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#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
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#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
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#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
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#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
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#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
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#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
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#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
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#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
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#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
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#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
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#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
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#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
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/* @Brief Board accelerator sensor configuration */
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#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
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/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
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#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
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/* Clock divider for LPI2C clock source */
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#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
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#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
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#define BOARD_CODEC_I2C_BASEADDR LPI2C1
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#define BOARD_CODEC_I2C_INSTANCE 1U
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#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
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#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
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#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
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/* @Brief Board CAMERA configuration */
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#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
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#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
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#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
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#define BOARD_CAMERA_I2C_CLOCK_FREQ \
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(CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
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#define BOARD_CAMERA_I2C_SCL_GPIO GPIO1
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#define BOARD_CAMERA_I2C_SCL_PIN 16
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#define BOARD_CAMERA_I2C_SDA_GPIO GPIO1
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#define BOARD_CAMERA_I2C_SDA_PIN 17
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#define BOARD_CAMERA_PWDN_GPIO GPIO1
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#define BOARD_CAMERA_PWDN_PIN 4
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/* @Brief Board Bluetooth HCI UART configuration */
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#define BOARD_BT_UART_BASEADDR LPUART3
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#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
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#define BOARD_BT_UART_IRQ LPUART3_IRQn
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#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/*******************************************************************************
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* API
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******************************************************************************/
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uint32_t BOARD_DebugConsoleSrcFreq(void);
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void BOARD_InitDebugConsole(void);
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void BOARD_ConfigMPU(void);
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
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status_t BOARD_LPI2C_Send(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subaddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize);
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status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subaddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize);
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status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subaddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize);
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status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subaddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize);
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void BOARD_Accel_I2C_Init(void);
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status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
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status_t BOARD_Accel_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
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void BOARD_Codec_I2C_Init(void);
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status_t BOARD_Codec_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
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status_t BOARD_Codec_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
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void BOARD_Camera_I2C_Init(void);
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status_t BOARD_Camera_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
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status_t BOARD_Camera_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
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status_t BOARD_Camera_I2C_SendSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
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status_t BOARD_Camera_I2C_ReceiveSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
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void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus */
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#endif /* _BOARD_H_ */
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124
board/NXP_EVK_IMXRT1060/bsp/Inc/clock_config.h
Normal file
124
board/NXP_EVK_IMXRT1060/bsp/Inc/clock_config.h
Normal file
@@ -0,0 +1,124 @@
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/*
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* Copyright 2018-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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#include "fsl_common.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes default configuration of clocks.
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*
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*/
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void BOARD_InitBootClocks(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockRUN configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
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/* Clock outputs (values are in Hz): */
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#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
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#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
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#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
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#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
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#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
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#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
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#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
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#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
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#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
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#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
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#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
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#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
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||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
|
||||
|
||||
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
73
board/NXP_EVK_IMXRT1060/bsp/Inc/pin_mux.h
Normal file
73
board/NXP_EVK_IMXRT1060/bsp/Inc/pin_mux.h
Normal file
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
|
||||
#define BOARD_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
|
||||
#define BOARD_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */
|
||||
|
||||
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
|
||||
#define BOARD_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
|
||||
#define BOARD_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
420
board/NXP_EVK_IMXRT1060/bsp/Src/board.c
Normal file
420
board/NXP_EVK_IMXRT1060/bsp/Src/board.c
Normal file
@@ -0,0 +1,420 @@
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
#include "fsl_lpi2c.h"
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
#include "tos_k.h"
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
if (tos_knl_is_running())
|
||||
{
|
||||
tos_knl_irq_enter();
|
||||
tos_tick_handler();
|
||||
tos_knl_irq_leave();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Get debug console frequency. */
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
/* To make it simple, we assume default PLL and divider settings, and the only variable
|
||||
from application is use PLL3 source or OSC source */
|
||||
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
|
||||
{
|
||||
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
|
||||
{
|
||||
lpi2c_master_config_t lpi2cConfig = {0};
|
||||
|
||||
/*
|
||||
* lpi2cConfig.debugEnable = false;
|
||||
* lpi2cConfig.ignoreAck = false;
|
||||
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
|
||||
* lpi2cConfig.baudRate_Hz = 100000U;
|
||||
* lpi2cConfig.busIdleTimeout_ns = 0;
|
||||
* lpi2cConfig.pinLowTimeout_ns = 0;
|
||||
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
|
||||
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
|
||||
*/
|
||||
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
|
||||
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = txBuff;
|
||||
xfer.dataSize = txBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = txBuff;
|
||||
xfer.dataSize = txBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
status_t status;
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = NULL;
|
||||
xfer.dataSize = 0;
|
||||
|
||||
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
|
||||
if (kStatus_Success == status)
|
||||
{
|
||||
xfer.subaddressSize = 0;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void BOARD_Accel_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||
{
|
||||
uint8_t data = (uint8_t)txBuff;
|
||||
|
||||
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Camera_I2C_Init(void)
|
||||
{
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
|
||||
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
/* MPU configuration. */
|
||||
void BOARD_ConfigMPU(void)
|
||||
{
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$RW_m_ncache$$Base[];
|
||||
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
|
||||
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
|
||||
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
|
||||
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
|
||||
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
|
||||
0 :
|
||||
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
|
||||
#elif defined(__MCUXPRESSO)
|
||||
extern uint32_t __base_NCACHE_REGION;
|
||||
extern uint32_t __top_NCACHE_REGION;
|
||||
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
|
||||
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
|
||||
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||
extern uint32_t __NCACHE_REGION_START[];
|
||||
extern uint32_t __NCACHE_REGION_SIZE[];
|
||||
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
|
||||
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
|
||||
#endif
|
||||
uint32_t i = 0;
|
||||
|
||||
/* Disable I cache and D cache */
|
||||
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableICache();
|
||||
}
|
||||
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* MPU configure:
|
||||
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
||||
* SubRegionDisable, Size)
|
||||
* API in mpu_armv7.h.
|
||||
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
||||
* disabled.
|
||||
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
||||
* Privileged mode.
|
||||
* Use MACROS defined in mpu_armv7.h:
|
||||
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
||||
* 0 x 0 0 Strongly Ordered shareable
|
||||
* 0 x 0 1 Device shareable
|
||||
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 0 1 1 0 Normal shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 1 1 1 Normal shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 1 0 0 0 Normal not shareable outer and inner
|
||||
* noncache
|
||||
* 1 1 0 0 Normal shareable outer and inner
|
||||
* noncache
|
||||
* 1 0 1 1 Normal not shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 1 1 1 1 Normal shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 2 x 0 0 Device not shareable
|
||||
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
||||
* policy.
|
||||
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
||||
* mpu_armv7.h.
|
||||
*/
|
||||
|
||||
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||
/* Region 2 setting: Memory with Normal type, not shareable, outer/inner write back. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
|
||||
#endif
|
||||
|
||||
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
|
||||
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
|
||||
while ((size >> i) > 0x1U)
|
||||
{
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i != 0)
|
||||
{
|
||||
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||
assert(!(nonCacheStart % size));
|
||||
assert(size == (uint32_t)(1 << i));
|
||||
assert(i >= 5);
|
||||
|
||||
/* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||||
}
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
|
||||
{
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
}
|
||||
|
||||
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
|
||||
{
|
||||
}
|
||||
521
board/NXP_EVK_IMXRT1060/bsp/Src/clock_config.c
Normal file
521
board/NXP_EVK_IMXRT1060/bsp/Src/clock_config.c
Normal file
@@ -0,0 +1,521 @@
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||
*
|
||||
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||
*
|
||||
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
|
||||
*
|
||||
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
|
||||
*
|
||||
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
|
||||
*
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v7.0
|
||||
processor: MIMXRT1062xxxxA
|
||||
package_id: MIMXRT1062DVL6A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.7.1
|
||||
board: MIMXRT1060-EVK
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
|
||||
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
|
||||
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
settings:
|
||||
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
|
||||
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.div, value: '22'}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
|
||||
- {id: CCM_ANALOG.PLL5.num, value: '0'}
|
||||
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
|
||||
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
|
||||
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
|
||||
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.postDivider = 8, /* Divider after PLL */
|
||||
.numerator =
|
||||
0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.denominator =
|
||||
1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Enable XTAL 24MHz clock source. */
|
||||
CLOCK_InitExternalClk(0);
|
||||
/* Enable internal RC. */
|
||||
CLOCK_InitRcOsc24M();
|
||||
/* Switch clock source to external OSC. */
|
||||
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||
/* Set Oscillator ready counter value. */
|
||||
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
|
||||
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
|
||||
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||
{
|
||||
}
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Disable IPG clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||
CLOCK_DisableClock(kCLOCK_Adc2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar3);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Disable PERCLK clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Disable USDHC1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||
/* Set USDHC1_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
|
||||
/* Set Usdhc1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||
/* Disable USDHC2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc2);
|
||||
/* Set USDHC2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
|
||||
* unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
|
||||
* well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
|
||||
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
|
||||
* well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
|
||||
#endif
|
||||
/* Disable Flexspi2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi2);
|
||||
/* Set FLEXSPI2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
|
||||
/* Set Flexspi2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
|
||||
/* Disable CSI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Csi);
|
||||
/* Set CSI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
|
||||
/* Set Csi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CsiMux, 0);
|
||||
/* Disable LPSPI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Disable SAI2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Disable SAI3 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Disable Lpi2c clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Disable CAN clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Can1);
|
||||
CLOCK_DisableClock(kCLOCK_Can2);
|
||||
CLOCK_DisableClock(kCLOCK_Can3);
|
||||
CLOCK_DisableClock(kCLOCK_Can1S);
|
||||
CLOCK_DisableClock(kCLOCK_Can2S);
|
||||
CLOCK_DisableClock(kCLOCK_Can3S);
|
||||
/* Set CAN_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||||
/* Set Can clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||
/* Disable UART clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Disable LCDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_LcdPixel);
|
||||
/* Set LCDIF_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
|
||||
/* Set LCDIF_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
|
||||
/* Set Lcdif pre clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
|
||||
/* Disable SPDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Disable Flexio1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Disable Flexio2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio2);
|
||||
/* Set FLEXIO2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
|
||||
/* Set FLEXIO2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
|
||||
/* Set Flexio2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* Init ARM PLL. */
|
||||
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
|
||||
* unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
|
||||
* well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||||
#endif
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System pfd0. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||
/* Init System pfd1. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||||
/* Init System pfd2. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
|
||||
/* Init System pfd3. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
|
||||
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
|
||||
* well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
/* Init Usb1 pfd0. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
|
||||
/* Init Usb1 pfd1. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||
/* Init Usb1 pfd2. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||
/* Init Usb1 pfd3. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
|
||||
/* Disable Usb1 PLL output for USBPHY1. */
|
||||
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
/* Bypass Audio PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||
/* Set divider for Audio PLL. */
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* Init Video PLL. */
|
||||
uint32_t pllVideo;
|
||||
/* Disable Video PLL output before initial Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* Bypass PLL first */
|
||||
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
|
||||
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
|
||||
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
|
||||
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
|
||||
pllVideo =
|
||||
(CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
|
||||
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
CCM_ANALOG->PLL_VIDEO = pllVideo;
|
||||
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
/* Disable bypass for Video PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
|
||||
/* DeInit Enet PLL. */
|
||||
CLOCK_DeinitEnetPll();
|
||||
/* Bypass Enet PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||
/* Set Enet output divider. */
|
||||
CCM_ANALOG->PLL_ENET =
|
||||
(CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||
/* Enable Enet output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
/* Set Enet2 output divider. */
|
||||
CCM_ANALOG->PLL_ENET =
|
||||
(CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
|
||||
/* Enable Enet2 output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
|
||||
/* Enable Enet25M output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||
/* DeInit Usb2 PLL. */
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
/* Bypass Usb2 PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
|
||||
/* Enable Usb2 PLL output. */
|
||||
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set lvds1 clock source. */
|
||||
CCM_ANALOG->MISC1 =
|
||||
(CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||
/* Set clock out2 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||
/* Set clock out2 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
|
||||
/* Set clock out1 drives clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||
/* Disable clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||
/* Disable clock out2. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET1 Tx clock source. */
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
|
||||
/* Set ENET2 Tx clock source. */
|
||||
#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
|
||||
#else
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
|
||||
#endif
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
75
board/NXP_EVK_IMXRT1060/bsp/Src/hello_world.c
Normal file
75
board/NXP_EVK_IMXRT1060/bsp/Src/hello_world.c
Normal file
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
#include "cmsis_os.h"
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#define TASK1_STK_SIZE 1024
|
||||
void task1(void *arg);
|
||||
osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE);
|
||||
|
||||
#define TASK2_STK_SIZE 1024
|
||||
void task2(void *arg);
|
||||
osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);
|
||||
|
||||
void task1(void *arg)
|
||||
{
|
||||
int count = 0;
|
||||
while(1)
|
||||
{
|
||||
PRINTF("********This is Task 1, count is %d \r\n",count++);
|
||||
osDelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void task2(void *arg)
|
||||
{
|
||||
int count = 0;
|
||||
while(1)
|
||||
{
|
||||
PRINTF("++++++++This is Task 2, count is %d \r\n",count++);
|
||||
osDelay(2000);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Main function
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
/* Init board hardware. */
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
BOARD_InitDebugConsole();
|
||||
|
||||
PRINTF("Hello world from i.MX RT1060.\r\n");
|
||||
PRINTF("Welcome to TencentOS tiny\r\n");
|
||||
osKernelInitialize(); // TencentOS Tiny kernel initialize
|
||||
osThreadCreate(osThread(task1), NULL); // Create task1
|
||||
osThreadCreate(osThread(task2), NULL); // Create task2
|
||||
osKernelStart(); // Start TencentOS Tiny
|
||||
}
|
||||
90
board/NXP_EVK_IMXRT1060/bsp/Src/pin_mux.c
Normal file
90
board/NXP_EVK_IMXRT1060/bsp/Src/pin_mux.c
Normal file
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v6.0
|
||||
processor: MIMXRT1062xxxxA
|
||||
package_id: MIMXRT1062DVL6A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.0.20
|
||||
board: MIMXRT1060-EVK
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
|
||||
0x10B0U); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
|
||||
0x10B0U); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "evkmimxrt1060_flexspi_nor_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_100MHz,
|
||||
.sflashA1Size = 8u * 1024u * 1024u,
|
||||
.lookupTable =
|
||||
{
|
||||
// Read LUTs
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
@@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_120MHz = 7,
|
||||
kFlexSpiSerialClk_133MHz = 8,
|
||||
kFlexSpiSerialClk_166MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
//!@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
//!@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
//!@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
|
||||
320
board/NXP_EVK_IMXRT1060/bsp/xip/evkmimxrt1060_sdram_ini_dcd.c
Normal file
320
board/NXP_EVK_IMXRT1060/bsp/xip/evkmimxrt1060_sdram_ini_dcd.c
Normal file
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#include "evkmimxrt1060_sdram_ini_dcd.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.dcd_data")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.dcd_data"
|
||||
#endif
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: DCDx V2.0
|
||||
processor: MIMXRT1062xxxxA
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.0.20
|
||||
output_format: c_array
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
|
||||
const uint8_t dcd_data[] = {
|
||||
/* HEADER */
|
||||
/* Tag */
|
||||
0xD2,
|
||||
/* Image Length */
|
||||
0x04, 0x30,
|
||||
/* Version */
|
||||
0x41,
|
||||
|
||||
/* COMMANDS */
|
||||
|
||||
/* group: 'Imported Commands' */
|
||||
/* #1.1-117, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x03, 0xAC, 0x04,
|
||||
/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
|
||||
0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
|
||||
/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
|
||||
0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
|
||||
/* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
|
||||
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
|
||||
/* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||
/* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24,
|
||||
/* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24,
|
||||
/* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
|
||||
/* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
|
||||
/* #1.100, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
|
||||
/* #1.101, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
|
||||
/* #1.102, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
|
||||
/* #1.103, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
|
||||
/* #1.104, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
|
||||
/* #1.105, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
|
||||
/* #1.106, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.107, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
|
||||
/* #1.108, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
|
||||
/* #1.109, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
|
||||
/* #1.110, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
|
||||
/* #1.111, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
|
||||
/* #1.112, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.113, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
|
||||
/* #1.114, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
|
||||
/* #1.115, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.116, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #1.117, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||
/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #3.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #5.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #7.1-3, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x1C, 0x04,
|
||||
/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
|
||||
/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
|
||||
/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
|
||||
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09};
|
||||
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
|
||||
|
||||
#else
|
||||
const uint8_t dcd_data[] = {0x00};
|
||||
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef __EVKMIMXRT1060_SDRAM_INI_DCD__
|
||||
#define __EVKMIMXRT1060_SDRAM_INI_DCD__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*************************************
|
||||
* DCD Data
|
||||
*************************************/
|
||||
#define DCD_TAG_HEADER (0xD2)
|
||||
#define DCD_VERSION (0x41)
|
||||
#define DCD_TAG_HEADER_SHIFT (24)
|
||||
#define DCD_ARRAY_SIZE 1
|
||||
|
||||
#endif /* __EVKMIMXRT1060_SDRAM_INI_DCD__ */
|
||||
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1062CVJ5A
|
||||
** MIMXRT1062CVL5A
|
||||
** MIMXRT1062DVJ6A
|
||||
** MIMXRT1062DVL6A
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b191015
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
|
||||
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
|
||||
|
||||
define symbol m_interrupts_start = 0x60002000;
|
||||
define symbol m_interrupts_end = 0x600023FF;
|
||||
|
||||
define symbol m_text_start = 0x60002400;
|
||||
define symbol m_text_end = 0x607FFFFF;
|
||||
|
||||
define symbol m_interrupts_ram_start = 0x20000000;
|
||||
define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
|
||||
|
||||
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
|
||||
define symbol m_data_end = 0x2001FFFF;
|
||||
|
||||
define symbol m_data2_start = 0x20200000;
|
||||
define symbol m_data2_end = 0x202BFFFF;
|
||||
|
||||
define exported symbol m_boot_hdr_conf_start = 0x60000000;
|
||||
define symbol m_boot_hdr_ivt_start = 0x60001000;
|
||||
define symbol m_boot_hdr_boot_data_start = 0x60001020;
|
||||
define symbol m_boot_hdr_dcd_data_start = 0x60001030;
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __NCACHE_REGION_START = m_data2_start;
|
||||
define exported symbol __NCACHE_REGION_SIZE = 0x0;
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
||||
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
||||
|
||||
initialize by copy { readwrite, section .textrw };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
|
||||
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
|
||||
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
|
||||
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
|
||||
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
|
||||
|
||||
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
|
||||
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { last block HEAP };
|
||||
place in DATA_region { block NCACHE_VAR };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
@@ -0,0 +1,83 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1062CVJ5A
|
||||
** MIMXRT1062CVL5A
|
||||
** MIMXRT1062DVJ6A
|
||||
** MIMXRT1062DVL6A
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b191015
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol m_interrupts_start = 0x00000000;
|
||||
define symbol m_interrupts_end = 0x000003FF;
|
||||
|
||||
define symbol m_text_start = 0x00000400;
|
||||
define symbol m_text_end = 0x0001FFFF;
|
||||
|
||||
define symbol m_data_start = 0x20000000;
|
||||
define symbol m_data_end = 0x2001FFFF;
|
||||
|
||||
define symbol m_data2_start = 0x20200000;
|
||||
define symbol m_data2_end = 0x202BFFFF;
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __NCACHE_REGION_START = m_data2_start;
|
||||
define exported symbol __NCACHE_REGION_SIZE = 0x0;
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
||||
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
||||
|
||||
initialize by copy { readwrite, section .textrw };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { last block HEAP };
|
||||
place in DATA_region { block NCACHE_VAR };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
@@ -0,0 +1,83 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1062CVJ5A
|
||||
** MIMXRT1062CVL5A
|
||||
** MIMXRT1062DVJ6A
|
||||
** MIMXRT1062DVL6A
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b190730
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol m_interrupts_start = 0x00001400;
|
||||
define symbol m_interrupts_end = 0x000017FF;
|
||||
|
||||
define symbol m_text_start = 0x00001800;
|
||||
define symbol m_text_end = 0x0001FFFF;
|
||||
|
||||
define symbol m_data_start = 0x20000000;
|
||||
define symbol m_data_end = 0x2001FFFF;
|
||||
|
||||
define symbol m_data2_start = 0x20200000;
|
||||
define symbol m_data2_end = 0x202BFFFF;
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __NCACHE_REGION_START = m_data2_start;
|
||||
define exported symbol __NCACHE_REGION_SIZE = 0x0;
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
||||
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
||||
|
||||
initialize by copy { readwrite, section .textrw };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { last block HEAP };
|
||||
place in DATA_region { block NCACHE_VAR };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
87
board/NXP_EVK_IMXRT1060/iar/hello_world/evkmimxrt1060.mac
Normal file
87
board/NXP_EVK_IMXRT1060/iar/hello_world/evkmimxrt1060.mac
Normal file
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
_load_dcdc_trim()
|
||||
{
|
||||
__var ocotp_base;
|
||||
__var ocotp_fuse_bank0_base;
|
||||
__var dcdc_base;
|
||||
__var reg;
|
||||
__var trim_value;
|
||||
__var dcdc_trim_loaded;
|
||||
__var index;
|
||||
|
||||
ocotp_base = 0x401F4000;
|
||||
ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
|
||||
dcdc_base = 0x40080000;
|
||||
|
||||
dcdc_trim_loaded = 0;
|
||||
|
||||
reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
|
||||
if (reg & (1<<10))
|
||||
{
|
||||
// DCDC: REG0->VBG_TRM
|
||||
trim_value = (reg & (0x1F << 11)) >> 11;
|
||||
reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
|
||||
__writeMemory32(reg, dcdc_base + 0x4, "Memory");
|
||||
dcdc_trim_loaded = 1;
|
||||
}
|
||||
|
||||
reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
|
||||
if (reg & (1<<30))
|
||||
{
|
||||
index = (reg & (3 << 28)) >> 28;
|
||||
if (index < 4)
|
||||
{
|
||||
// DCDC: REG3->TRG
|
||||
reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
|
||||
__writeMemory32(reg, dcdc_base + 0xC, "Memory");
|
||||
dcdc_trim_loaded = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (dcdc_trim_loaded)
|
||||
{
|
||||
// delay 1ms for dcdc to get stable
|
||||
__delay(1);
|
||||
__message "DCDC trim value loaded.\n";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
_load_dcdc_trim();
|
||||
}
|
||||
|
||||
execUserReset()
|
||||
{
|
||||
_load_dcdc_trim();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,261 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
_load_dcdc_trim()
|
||||
{
|
||||
__var dcdc_trim_loaded;
|
||||
__var ocotp_base;
|
||||
__var ocotp_fuse_bank0_base;
|
||||
__var dcdc_base;
|
||||
__var reg;
|
||||
__var trim_value;
|
||||
__var index;
|
||||
|
||||
ocotp_base = 0x401F4000;
|
||||
ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
|
||||
dcdc_base = 0x40080000;
|
||||
|
||||
dcdc_trim_loaded = 0;
|
||||
|
||||
reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
|
||||
if (reg & (1<<10))
|
||||
{
|
||||
// DCDC: REG0->VBG_TRM
|
||||
trim_value = (reg & (0x1F << 11)) >> 11;
|
||||
reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
|
||||
__writeMemory32(reg, dcdc_base + 0x4, "Memory");
|
||||
dcdc_trim_loaded = 1;
|
||||
}
|
||||
|
||||
reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
|
||||
if (reg & (1<<30))
|
||||
{
|
||||
index = (reg & (3 << 28)) >> 28;
|
||||
if (index < 4)
|
||||
{
|
||||
// DCDC: REG3->TRG
|
||||
reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
|
||||
__writeMemory32(reg, dcdc_base + 0xC, "Memory");
|
||||
dcdc_trim_loaded = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (dcdc_trim_loaded)
|
||||
{
|
||||
// delay 1ms for dcdc to get stable
|
||||
__delay(1);
|
||||
__message "DCDC trim value loaded.\n";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
SDRAM_WaitIpCmdDone()
|
||||
{
|
||||
__var reg;
|
||||
do
|
||||
{
|
||||
reg = __readMemory32(0x402F003C, "Memory");
|
||||
}while((reg & 0x3) == 0);
|
||||
|
||||
__writeMemory32(0x00000003, 0x402F003C, "Memory"); // clear IPCMDERR and IPCMDDONE bits
|
||||
}
|
||||
|
||||
_clock_init()
|
||||
{
|
||||
__var reg;
|
||||
// Enable all clocks
|
||||
__writeMemory32(0xffffffff, 0x400FC068, "Memory");
|
||||
__writeMemory32(0xffffffff, 0x400FC06C, "Memory");
|
||||
__writeMemory32(0xffffffff, 0x400FC070, "Memory");
|
||||
__writeMemory32(0xffffffff, 0x400FC074, "Memory");
|
||||
__writeMemory32(0xffffffff, 0x400FC078, "Memory");
|
||||
__writeMemory32(0xffffffff, 0x400FC07C, "Memory");
|
||||
__writeMemory32(0xffffffff, 0x400FC080, "Memory");
|
||||
|
||||
// PERCLK_PODF: 1 divide by 2
|
||||
__writeMemory32(0x04900001, 0x400FC01C, "Memory");
|
||||
// Enable SYS PLL but keep it bypassed.
|
||||
__writeMemory32(0x00012001, 0x400D8030, "Memory");
|
||||
do
|
||||
{
|
||||
reg = __readMemory32(0x400D8030, "Memory");
|
||||
}while((reg & 0x80000000) == 0);
|
||||
// Disable bypass of SYS PLL
|
||||
__writeMemory32(0x00002001, 0x400D8030, "Memory");
|
||||
|
||||
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
|
||||
// Ungate SYS PLL PFD2
|
||||
__writeMemory32(0x001d0000, 0x400D8100, "Memory");
|
||||
|
||||
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
|
||||
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
|
||||
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
|
||||
__writeMemory32(0x00010D40, 0x400FC014, "Memory");
|
||||
|
||||
__message "clock init done\n";
|
||||
}
|
||||
|
||||
_sdr_Init()
|
||||
{
|
||||
// Config IOMUX
|
||||
__writeMemory32(0x00000000, 0x401F8014, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8018, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F801C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8020, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8024, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8028, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F802C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8030, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8034, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8038, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F803C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8040, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8044, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8048, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F804C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8050, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8054, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8058, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F805C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8060, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8064, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8068, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F806C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8070, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8074, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8078, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F807C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8080, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8084, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8088, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F808C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8090, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8094, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F8098, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F809C, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F80A0, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F80A4, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F80A8, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F80AC, "Memory");
|
||||
__writeMemory32(0x00000010, 0x401F80B0, "Memory"); // EMC_39, DQS PIN, enable SION
|
||||
__writeMemory32(0x00000000, 0x401F80B4, "Memory");
|
||||
__writeMemory32(0x00000000, 0x401F80B8, "Memory");
|
||||
|
||||
// PAD ctrl
|
||||
// drive strength = 0x7 to increase drive strength
|
||||
// otherwise the data7 bit may fail.
|
||||
__writeMemory32(0x000110F9, 0x401F8204, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8208, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F820C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8210, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8214, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8218, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F821C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8220, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8224, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8228, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F822C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8230, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8234, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8238, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F823C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8240, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8244, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8248, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F824C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8250, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8254, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8258, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F825C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8260, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8264, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8268, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F826C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8270, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8274, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8278, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F827C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8280, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8284, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8288, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F828C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8290, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8294, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F8298, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F829C, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F82A0, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F82A4, "Memory");
|
||||
__writeMemory32(0x000110F9, 0x401F82A8, "Memory");
|
||||
|
||||
// Config SDR Controller Registers/
|
||||
__writeMemory32(0x10000004, 0x402F0000, "Memory"); // MCR
|
||||
__writeMemory32(0x00030524, 0x402F0008, "Memory"); // BMCR0
|
||||
__writeMemory32(0x06030524, 0x402F000C, "Memory"); // BMCR1
|
||||
__writeMemory32(0x8000001B, 0x402F0010, "Memory"); // BR0, 32MB
|
||||
|
||||
__writeMemory32(0x00000F31, 0x402F0040, "Memory"); // SDRAMCR0
|
||||
__writeMemory32(0x00662A22, 0x402F0044, "Memory"); // SDRAMCR1
|
||||
__writeMemory32(0x000A0A0A, 0x402F0048, "Memory"); // SDRAMCR2
|
||||
__writeMemory32(0x08080A00, 0x402F004C, "Memory"); // SDRAMCR3
|
||||
|
||||
__writeMemory32(0x80000000, 0x402F0090, "Memory"); // IPCR0
|
||||
__writeMemory32(0x00000002, 0x402F0094, "Memory"); // IPCR1
|
||||
__writeMemory32(0x00000000, 0x402F0098, "Memory"); // IPCR2
|
||||
|
||||
__writeMemory32(0xA55A000F, 0x402F009C, "Memory"); // IPCMD, SD_CC_IPREA
|
||||
SDRAM_WaitIpCmdDone();
|
||||
__writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
|
||||
SDRAM_WaitIpCmdDone();
|
||||
__writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
|
||||
SDRAM_WaitIpCmdDone();
|
||||
__writeMemory32(0x00000033, 0x402F00A0, "Memory"); // IPTXDAT
|
||||
__writeMemory32(0xA55A000A, 0x402F009C, "Memory"); // SD_CC_IMS
|
||||
SDRAM_WaitIpCmdDone();
|
||||
|
||||
__writeMemory32(0x08080A01, 0x402F004C, "Memory"); // enable sdram self refresh after initialization done.
|
||||
|
||||
__message "SDRAM init done\n";
|
||||
}
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
_load_dcdc_trim();
|
||||
_clock_init();
|
||||
_sdr_Init();
|
||||
__message "execUserPreload() done.\n";
|
||||
}
|
||||
|
||||
execUserReset()
|
||||
{
|
||||
_load_dcdc_trim();
|
||||
_clock_init();
|
||||
_sdr_Init();
|
||||
__message "execUserReset() done.\n";
|
||||
}
|
||||
|
||||
8914
board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.ewd
Normal file
8914
board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.ewd
Normal file
File diff suppressed because it is too large
Load Diff
6849
board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.ewp
Normal file
6849
board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.ewp
Normal file
File diff suppressed because it is too large
Load Diff
143
board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.eww
Normal file
143
board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.eww
Normal file
@@ -0,0 +1,143 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
<workspace>
|
||||
<batchBuild>
|
||||
<batchDefinition>
|
||||
<name>all</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>ram_0x1400_debug</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>ram_0x1400_release</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_txt_debug</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_txt_release</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>release</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_sdram_debug</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_sdram_release</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>debug</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_debug</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_release</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_debug</configuration>
|
||||
</member>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_release</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>ram_0x1400_debug</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>ram_0x1400_debug</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>ram_0x1400_release</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>ram_0x1400_release</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>sdram_txt_debug</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_txt_debug</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>sdram_txt_release</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_txt_release</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>release</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>release</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>flexspi_nor_sdram_debug</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_sdram_debug</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>flexspi_nor_sdram_release</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_sdram_release</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>debug</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>debug</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>sdram_debug</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_debug</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>sdram_release</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>sdram_release</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>flexspi_nor_debug</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_debug</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
<batchDefinition>
|
||||
<name>flexspi_nor_release</name>
|
||||
<member>
|
||||
<project>hello_world</project>
|
||||
<configuration>flexspi_nor_release</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
</batchBuild>
|
||||
<project>
|
||||
<path>$WS_DIR$/hello_world.ewp</path>
|
||||
</project>
|
||||
</workspace>
|
||||
55
board/NXP_EVK_IMXRT1060/tos_config/tos_config.h
Normal file
55
board/NXP_EVK_IMXRT1060/tos_config/tos_config.h
Normal file
@@ -0,0 +1,55 @@
|
||||
#ifndef _TOS_CONFIG_H_
|
||||
#define _TOS_CONFIG_H_
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#define TOS_CFG_TASK_PRIO_MAX 10u
|
||||
|
||||
#define TOS_CFG_ROUND_ROBIN_EN 0u
|
||||
|
||||
#define TOS_CFG_OBJECT_VERIFY_EN 1u
|
||||
|
||||
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 1u
|
||||
|
||||
#define TOS_CFG_EVENT_EN 1u
|
||||
|
||||
#define TOS_CFG_MMBLK_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x1000
|
||||
|
||||
#define TOS_CFG_MUTEX_EN 1u
|
||||
|
||||
#define TOS_CFG_MESSAGE_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_MAIL_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_TIMER_EN 1u
|
||||
|
||||
#define TOS_CFG_PWR_MGR_EN 0u
|
||||
|
||||
#define TOS_CFG_TICKLESS_EN 0u
|
||||
|
||||
#define TOS_CFG_SEM_EN 1u
|
||||
|
||||
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u
|
||||
|
||||
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
|
||||
|
||||
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
|
||||
|
||||
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
|
||||
|
||||
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
|
||||
|
||||
#define TOS_CFG_TIMER_AS_PROC 1u
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user