From 97cb277bd8960a8cf0c85a3ce2def1b9432f86e7 Mon Sep 17 00:00:00 2001 From: thomas_li Date: Mon, 10 Feb 2020 10:11:00 +0800 Subject: [PATCH] SDK: add project of mqtt --- board/NUCLEO_STM32L496ZG/BSP/Inc/main.h | 16 + board/NUCLEO_STM32L496ZG/BSP/Inc/usart.h | 6 + board/NUCLEO_STM32L496ZG/BSP/Src/gpio.c | 23 + board/NUCLEO_STM32L496ZG/BSP/Src/main.c | 12 +- board/NUCLEO_STM32L496ZG/BSP/Src/mcu_init.c | 28 +- .../NUCLEO_STM32L496ZG/BSP/Src/stm32l4xx_it.c | 67 +- board/NUCLEO_STM32L496ZG/BSP/Src/usart.c | 215 +- .../KEIL/hello_world/TencentOS_tiny.uvoptx | 40 +- .../TencentOS_tiny.uvoptx | 2597 +++++++++++++++++ .../TencentOS_tiny.uvprojx | 1392 +++++++++ .../startup_stm32l496xx.s | 450 +++ .../TOS-CONFIG/tos_config.h | 55 + .../TOS_CONFIG/tos_config.h | 37 - 13 files changed, 4865 insertions(+), 73 deletions(-) create mode 100644 board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvoptx create mode 100644 board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvprojx create mode 100644 board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/startup_stm32l496xx.s create mode 100644 board/NUCLEO_STM32L496ZG/TOS-CONFIG/tos_config.h delete mode 100644 board/NUCLEO_STM32L496ZG/TOS_CONFIG/tos_config.h diff --git a/board/NUCLEO_STM32L496ZG/BSP/Inc/main.h b/board/NUCLEO_STM32L496ZG/BSP/Inc/main.h index f518da18..94c1a1af 100644 --- a/board/NUCLEO_STM32L496ZG/BSP/Inc/main.h +++ b/board/NUCLEO_STM32L496ZG/BSP/Inc/main.h @@ -58,6 +58,22 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ +#define B1_Pin GPIO_PIN_13 +#define B1_GPIO_Port GPIOC +#define LD3_Pin GPIO_PIN_14 +#define LD3_GPIO_Port GPIOB +#define STLK_RX_Pin GPIO_PIN_7 +#define STLK_RX_GPIO_Port GPIOG +#define STLK_TX_Pin GPIO_PIN_8 +#define STLK_TX_GPIO_Port GPIOG +#define TMS_Pin GPIO_PIN_13 +#define TMS_GPIO_Port GPIOA +#define TCK_Pin GPIO_PIN_14 +#define TCK_GPIO_Port GPIOA +#define SWO_Pin GPIO_PIN_3 +#define SWO_GPIO_Port GPIOB +#define LD2_Pin GPIO_PIN_7 +#define LD2_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ diff --git a/board/NUCLEO_STM32L496ZG/BSP/Inc/usart.h b/board/NUCLEO_STM32L496ZG/BSP/Inc/usart.h index 852ad54d..0537a48e 100644 --- a/board/NUCLEO_STM32L496ZG/BSP/Inc/usart.h +++ b/board/NUCLEO_STM32L496ZG/BSP/Inc/usart.h @@ -31,12 +31,18 @@ /* USER CODE END Includes */ extern UART_HandleTypeDef hlpuart1; +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart2; +extern UART_HandleTypeDef huart3; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_LPUART1_UART_Init(void); +void MX_USART1_UART_Init(void); +void MX_USART2_UART_Init(void); +void MX_USART3_UART_Init(void); /* USER CODE BEGIN Prototypes */ diff --git a/board/NUCLEO_STM32L496ZG/BSP/Src/gpio.c b/board/NUCLEO_STM32L496ZG/BSP/Src/gpio.c index 82df0054..9dbaeef5 100644 --- a/board/NUCLEO_STM32L496ZG/BSP/Src/gpio.c +++ b/board/NUCLEO_STM32L496ZG/BSP/Src/gpio.c @@ -40,10 +40,33 @@ void MX_GPIO_Init(void) { + GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); HAL_PWREx_EnableVddIO2(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LD3_Pin|LD2_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = B1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PBPin PBPin */ + GPIO_InitStruct.Pin = LD3_Pin|LD2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + } diff --git a/board/NUCLEO_STM32L496ZG/BSP/Src/main.c b/board/NUCLEO_STM32L496ZG/BSP/Src/main.c index eaeba803..646bdf65 100644 --- a/board/NUCLEO_STM32L496ZG/BSP/Src/main.c +++ b/board/NUCLEO_STM32L496ZG/BSP/Src/main.c @@ -1,7 +1,8 @@ #include "mcu_init.h" #include "cmsis_os.h" -#define APPLICATION_TASK_STK_SIZE 1024 +#define APPLICATION_TASK_STK_SIZE 4096 + extern void application_entry(void *arg); osThreadDef(application_entry, osPriorityNormal, 1, APPLICATION_TASK_STK_SIZE); @@ -16,8 +17,9 @@ __weak void application_entry(void *arg) int main(void) { board_init(); - printf("Welcome to TencentOS tiny NUCLEO_STM32L496ZG IAR Project\r\n"); - osKernelInitialize(); - osThreadCreate(osThread(application_entry), NULL); - osKernelStart(); + printf("Welcome to TencentOS tiny\r\n"); + osKernelInitialize(); // TOS Tiny kernel initialize + osThreadCreate(osThread(application_entry), NULL); // Create TOS Tiny task + osKernelStart(); // Start TOS Tiny } + diff --git a/board/NUCLEO_STM32L496ZG/BSP/Src/mcu_init.c b/board/NUCLEO_STM32L496ZG/BSP/Src/mcu_init.c index e146eed3..5fe3edf7 100644 --- a/board/NUCLEO_STM32L496ZG/BSP/Src/mcu_init.c +++ b/board/NUCLEO_STM32L496ZG/BSP/Src/mcu_init.c @@ -18,22 +18,20 @@ int _write(int fd, char *ptr, int len) int fgetc(FILE *f) { /* Place your implementation of fgetc here */ - /* e.g. readwrite a character to the LPUSART1 and Loop until the end of transmission */ + /* e.g. readwrite a character to the USART2 and Loop until the end of transmission */ uint8_t ch = 0; - //uint32_t recv_size; HAL_UART_Receive(&hlpuart1, &ch, 1,30000); return ch; } - void board_init(void) { - HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_LPUART1_UART_Init(); - + MX_USART2_UART_Init(); + MX_USART3_UART_Init(); } /** @@ -48,13 +46,14 @@ void SystemClock_Config(void) /** Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLN = 40; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; @@ -68,14 +67,17 @@ void SystemClock_Config(void) |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_USART3 + |RCC_PERIPHCLK_LPUART1; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { @@ -113,7 +115,7 @@ void Error_Handler(void) * @param line: assert_param error line source number * @retval None */ -void assert_failed(uint8_t *file, uint32_t line) +void assert_failed(char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, diff --git a/board/NUCLEO_STM32L496ZG/BSP/Src/stm32l4xx_it.c b/board/NUCLEO_STM32L496ZG/BSP/Src/stm32l4xx_it.c index aeae9102..0728963b 100644 --- a/board/NUCLEO_STM32L496ZG/BSP/Src/stm32l4xx_it.c +++ b/board/NUCLEO_STM32L496ZG/BSP/Src/stm32l4xx_it.c @@ -22,6 +22,7 @@ #include "main.h" #include "stm32l4xx_it.h" #include "tos_k.h" +#include "tos_at.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -57,7 +58,9 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ - +extern UART_HandleTypeDef hlpuart1; +extern UART_HandleTypeDef huart2; +extern UART_HandleTypeDef huart3; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -186,12 +189,13 @@ void SysTick_Handler(void) /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - if(tos_knl_is_running()) + if (tos_knl_is_running()) { - tos_knl_irq_enter(); - tos_tick_handler(); - tos_knl_irq_leave(); + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); } + //HAL_SYSTICK_IRQHandler(); /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ @@ -204,7 +208,58 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32l4xx.s). */ /******************************************************************************/ -/* USER CODE BEGIN 1 */ +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + +/** + * @brief This function handles USART3 global interrupt. + */ +void USART3_IRQHandler(void) +{ + /* USER CODE BEGIN USART3_IRQn 0 */ + + /* USER CODE END USART3_IRQn 0 */ + HAL_UART_IRQHandler(&huart3); + /* USER CODE BEGIN USART3_IRQn 1 */ + + /* USER CODE END USART3_IRQn 1 */ +} + +/** + * @brief This function handles LPUART1 global interrupt. + */ +void LPUART1_IRQHandler(void) +{ + /* USER CODE BEGIN LPUART1_IRQn 0 */ + + /* USER CODE END LPUART1_IRQn 0 */ + tos_knl_irq_enter(); + HAL_UART_IRQHandler(&hlpuart1); + tos_knl_irq_leave(); + /* USER CODE BEGIN LPUART1_IRQn 1 */ + + /* USER CODE END LPUART1_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + extern uint8_t data; + if (huart->Instance == USART2) { + HAL_UART_Receive_IT(&huart2, &data, 1); + tos_at_uart_input_byte(data); + } +} /* USER CODE END 1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/board/NUCLEO_STM32L496ZG/BSP/Src/usart.c b/board/NUCLEO_STM32L496ZG/BSP/Src/usart.c index 69bfff09..288b7db2 100644 --- a/board/NUCLEO_STM32L496ZG/BSP/Src/usart.c +++ b/board/NUCLEO_STM32L496ZG/BSP/Src/usart.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2020 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -21,10 +21,13 @@ #include "usart.h" /* USER CODE BEGIN 0 */ - +uint8_t data; /* USER CODE END 0 */ UART_HandleTypeDef hlpuart1; +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; +UART_HandleTypeDef huart3; /* LPUART1 init function */ @@ -45,6 +48,69 @@ void MX_LPUART1_UART_Init(void) Error_Handler(); } +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + +} +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + HAL_UART_Receive_IT(&huart2, &data, 1); +} +/* USART3 init function */ + +void MX_USART3_UART_Init(void) +{ + + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + } void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) @@ -65,17 +131,98 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) PG7 ------> LPUART1_TX PG8 ------> LPUART1_RX */ - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8; + GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); /* USER CODE BEGIN LPUART1_MspInit 1 */ /* USER CODE END LPUART1_MspInit 1 */ } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART2 GPIO Configuration + PD5 ------> USART2_TX + PD6 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* USART3 clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**USART3 GPIO Configuration + PC4 ------> USART3_TX + PC5 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USART3 interrupt Init */ + HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART3_IRQn); + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } } void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) @@ -93,12 +240,72 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) PG7 ------> LPUART1_TX PG8 ------> LPUART1_RX */ - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7|GPIO_PIN_8); + HAL_GPIO_DeInit(GPIOG, STLK_RX_Pin|STLK_TX_Pin); + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); /* USER CODE BEGIN LPUART1_MspDeInit 1 */ /* USER CODE END LPUART1_MspDeInit 1 */ } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PD5 ------> USART2_TX + PD6 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6); + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PC4 ------> USART3_TX + PC5 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5); + + /* USART3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART3_IRQn); + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ diff --git a/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx b/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx index 2e241979..10118f1f 100644 --- a/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx +++ b/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx @@ -145,10 +145,34 @@ 0 ST-LINKIII-KEIL_SWO - -U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM) + -U0674FF525750877267153432 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM) - + + + 0 + 0 + 573 + 1 +
134226432
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\..\..\..\kernel\core\tos_mmheap.c + + \\TencentOS_tiny\../../../../kernel/core/tos_mmheap.c\573 + + + + + 0 + 1 + k_mmheap_default_pool + + 0 @@ -203,7 +227,7 @@ Application/MDK-ARM - 0 + 1 0 0 0 @@ -551,7 +575,7 @@ Drivers/CMSIS - 0 + 1 0 0 0 @@ -571,7 +595,7 @@ tos/arch - 0 + 1 0 0 0 @@ -615,7 +639,7 @@ tos/kernel - 0 + 1 0 0 0 @@ -911,7 +935,7 @@ tos/cmsis_os - 0 + 1 0 0 0 @@ -931,7 +955,7 @@ examples - 0 + 1 0 0 0 diff --git a/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvoptx b/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvoptx new file mode 100644 index 00000000..fa1d0b0e --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvoptx @@ -0,0 +1,2597 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\..\..\..\components\connectivity\TencentCloud_SDK\source\include\qcloud_config.h + qcloud_config.h + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvprojx b/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvprojx new file mode 100644 index 00000000..0405a8dc --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/TencentOS_tiny.uvprojx @@ -0,0 +1,1392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + TencentOS_tiny + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32L496ZGTx + STMicroelectronics + Keil.STM32L4xx_DFP.2.2.0 + http://www.keil.com/pack + IRAM(0x20000000,0x00040000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM)) + 0 + $$Device:STM32L496ZGTx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + + + + + + + + + + $$Device:STM32L496ZGTx$CMSIS\SVD\STM32L4x6.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + TencentOS_tiny + 1 + 0 + 1 + 1 + 0 + .\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4107 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER,STM32L496xx,MBEDTLS_CONFIG_FILE=<qcloud/tls_psk_config.h> + + ..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32L4xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\kernel\core\include;..\..\..\..\platform\arch\arm\cortex-m4\keil;..\..\..\..\kernel\pm\include;..\..\..\..\kernel\hal\include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\..\..\osal\cmsis_os;..\..\..\..\devices\esp8266;..\..\..\..\devices\rhf76_lora;..\..\..\..\devices\esp8266_tencent_firmware;..\..\..\..\devices\bc35_28_95;..\..\BSP\Hardware\DHT11;..\..\BSP\Hardware\OLED;..\..\BSP\Hardware\BH1750;..\..\TOS-CONFIG;..\..\..\..\examples\helloworld;..\..\..\..\components\connectivity\TencentCloud_SDK\source\include;..\..\..\..\components\security\mbedtls\3rdparty\include;..\..\..\..\components\security\mbedtls\wrapper\include;..\..\..\..\net\at\include;..\..\..\..\net\sal_module_wrapper;..\..\..\..\net\lora_module_wrapper;..\..\..\..\net\tencent_firmware_module_wrapper + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32l496xx.s + 2 + .\startup_stm32l496xx.s + + + + + Application/User + + + gpio.c + 1 + ..\..\BSP\Src\gpio.c + + + main.c + 1 + ..\..\BSP\Src\main.c + + + mcu_init.c + 1 + ..\..\BSP\Src\mcu_init.c + + + stm32l4xx_hal_msp.c + 1 + ..\..\BSP\Src\stm32l4xx_hal_msp.c + + + usart.c + 1 + ..\..\BSP\Src\usart.c + + + stm32l4xx_it.c + 1 + ..\..\BSP\Src\stm32l4xx_it.c + + + + + examples + + + mqtt_sample.c + 1 + ..\..\..\..\examples\tencent_cloud_sdk_mqtt\mqtt_sample.c + + + tencent_cloud_sdk_mqtt.c + 1 + ..\..\..\..\examples\tencent_cloud_sdk_mqtt\tencent_cloud_sdk_mqtt.c + + + + + Drivers/STM32L4xx_HAL_Driver + + + stm32l4xx_hal_tim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c + + + stm32l4xx_hal_tim_ex.c + 1 + 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+ ..\..\..\..\kernel\core\tos_countdownlatch.c + + + tos_event.c + 1 + ..\..\..\..\kernel\core\tos_event.c + + + tos_global.c + 1 + ..\..\..\..\kernel\core\tos_global.c + + + tos_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_mail_queue.c + + + tos_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_message_queue.c + + + tos_mmblk.c + 1 + ..\..\..\..\kernel\core\tos_mmblk.c + + + tos_mmheap.c + 1 + ..\..\..\..\kernel\core\tos_mmheap.c + + + tos_mutex.c + 1 + ..\..\..\..\kernel\core\tos_mutex.c + + + tos_pend.c + 1 + ..\..\..\..\kernel\core\tos_pend.c + + + tos_priority_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + + + tos_priority_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + + + tos_priority_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_queue.c + + + tos_ring_queue.c + 1 + ..\..\..\..\kernel\core\tos_ring_queue.c + + + tos_robin.c + 1 + ..\..\..\..\kernel\core\tos_robin.c + + + tos_sched.c + 1 + ..\..\..\..\kernel\core\tos_sched.c + + + tos_sem.c + 1 + ..\..\..\..\kernel\core\tos_sem.c + + + tos_sys.c + 1 + ..\..\..\..\kernel\core\tos_sys.c + + + tos_task.c + 1 + ..\..\..\..\kernel\core\tos_task.c + + + tos_tick.c + 1 + ..\..\..\..\kernel\core\tos_tick.c + + + tos_time.c + 1 + ..\..\..\..\kernel\core\tos_time.c + + + tos_timer.c + 1 + ..\..\..\..\kernel\core\tos_timer.c + + + + + cpu + + + port_s.S + 2 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S + + + tos_cpu.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + + + port_c.c + 1 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c + + + + + cmsis + + + cmsis_os.c + 1 + ..\..\..\..\osal\cmsis_os\cmsis_os.c + + + + + module_wrapper + + + sal_module_wrapper.c + 1 + ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c + + + tencent_firmware_module_wrapper.c + 1 + ..\..\..\..\net\tencent_firmware_module_wrapper\tencent_firmware_module_wrapper.c + + + + + devices + + + esp8266.c + 1 + ..\..\..\..\devices\esp8266\esp8266.c + + + + + config + + + tos_config.h + 5 + ..\..\TOS-CONFIG\tos_config.h + + + + + hal + + + tos_hal_uart.c + 1 + ..\..\..\..\platform\hal\st\stm32l4xx\src\tos_hal_uart.c + + + + + at-framwork + + + tos_at.c + 1 + ..\..\..\..\net\at\src\tos_at.c + + + tos_at_utils.c + 1 + ..\..\..\..\net\at\src\tos_at_utils.c + + + + + mbedtls + + + entropy_hardware_alt.c + 1 + ..\..\..\..\components\security\mbedtls\wrapper\src\entropy_hardware_alt.c + + + net_module_alt.c + 1 + ..\..\..\..\components\security\mbedtls\wrapper\src\net_module_alt.c + + + timing_alt.c + 1 + ..\..\..\..\components\security\mbedtls\wrapper\src\timing_alt.c + + + aes.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\aes.c + + + aesni.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\aesni.c + + + arc4.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\arc4.c + + + aria.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\aria.c + + + asn1parse.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\asn1parse.c + + + asn1write.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\asn1write.c + + + base64.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\base64.c + + + bignum.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\bignum.c + + + blowfish.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\blowfish.c + + + camellia.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\camellia.c + + + ccm.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ccm.c + + + certs.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\certs.c + + + chacha20.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\chacha20.c + + + chachapoly.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\chachapoly.c + + + cipher.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\cipher.c + + + cipher_wrap.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\cipher_wrap.c + + + cmac.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\cmac.c + + + ctr_drbg.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ctr_drbg.c + + + debug.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\debug.c + + + des.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\des.c + + + dhm.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\dhm.c + + + ecdh.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ecdh.c + + + ecdsa.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ecdsa.c + + + ecjpake.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ecjpake.c + + + ecp.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ecp.c + + + ecp_curves.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ecp_curves.c + + + entropy.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\entropy.c + + + entropy_poll.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\entropy_poll.c + + + error.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\error.c + + + gcm.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\gcm.c + + + havege.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\havege.c + + + hkdf.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\hkdf.c + + + hmac_drbg.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\hmac_drbg.c + + + md.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\md.c + + + md_wrap.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\md_wrap.c + + + md2.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\md2.c + + + md4.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\md4.c + + + md5.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\md5.c + + + memory_buffer_alloc.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\memory_buffer_alloc.c + + + net_sockets.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\net_sockets.c + + + nist_kw.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\nist_kw.c + + + oid.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\oid.c + + + padlock.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\padlock.c + + + pem.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pem.c + + + pk.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pk.c + + + pk_wrap.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pk_wrap.c + + + pkcs5.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pkcs5.c + + + pkcs11.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pkcs11.c + + + pkcs12.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pkcs12.c + + + pkparse.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pkparse.c + + + pkwrite.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\pkwrite.c + + + platform.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\platform.c + + + platform_util.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\platform_util.c + + + poly1305.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\poly1305.c + + + ripemd160.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ripemd160.c + + + rsa.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\rsa.c + + + rsa_internal.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\rsa_internal.c + + + sha1.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\sha1.c + + + sha256.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\sha256.c + + + sha512.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\sha512.c + + + ssl_cache.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ssl_cache.c + + + ssl_ciphersuites.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ssl_ciphersuites.c + + + ssl_cli.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ssl_cli.c + + + ssl_cookie.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ssl_cookie.c + + + ssl_srv.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ssl_srv.c + + + ssl_ticket.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ssl_ticket.c + + + ssl_tls.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\ssl_tls.c + + + threading.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\threading.c + + + timing.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\timing.c + + + version.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\version.c + + + version_features.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\version_features.c + + + x509.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\x509.c + + + x509_create.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\x509_create.c + + + x509_crl.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\x509_crl.c + + + x509_crt.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\x509_crt.c + + + x509_csr.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\x509_csr.c + + + x509write_crt.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\x509write_crt.c + + + x509write_csr.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\x509write_csr.c + + + xtea.c + 1 + ..\..\..\..\components\security\mbedtls\3rdparty\src\xtea.c + + + + + qcloud + + + qcloud_log.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\qcloud_log.c + + + qcloud_network.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\qcloud_network.c + + + qcloud_device.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\qcloud_device.c + + + qcloud_tls.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\qcloud_tls.c + + + + + qcloud/utils + + + qcloud_aes.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_aes.c + + + qcloud_base64.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_base64.c + + + qcloud_hmac.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_hmac.c + + + qcloud_httpc.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_httpc.c + + + qcloud_json_parser.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_json_parser.c + + + qcloud_json_token.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_json_token.c + + + qcloud_md5.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_md5.c + + + qcloud_sha1.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_sha1.c + + + qcloud_string_utils.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\utils\qcloud_string_utils.c + + + + + qcloud/mqtt + + + qcloud_mqtt_client.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_client.c + + + qcloud_mqtt_common.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_common.c + + + qcloud_mqtt_connect.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_connect.c + + + qcloud_mqtt_glue.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_glue.c + + + qcloud_mqtt_publish.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_publish.c + + + qcloud_mqtt_subscribe.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_subscribe.c + + + qcloud_mqtt_unsubscribe.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_unsubscribe.c + + + qcloud_mqtt_yield.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\mqtt\qcloud_mqtt_yield.c + + + + + qcloud/port + + + osal_dtls.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\port\TencentOS_tiny\osal_dtls.c + + + osal_os.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\port\TencentOS_tiny\osal_os.c + + + osal_tcp_module.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\port\TencentOS_tiny\osal_tcp_module.c + + + osal_timer.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\port\TencentOS_tiny\osal_timer.c + + + osal_tls.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\port\TencentOS_tiny\osal_tls.c + + + osal_udp_module.c + 1 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\src\port\TencentOS_tiny\osal_udp_module.c + + + + + qcloud/config + + + qcloud_config.h + 5 + ..\..\..\..\components\connectivity\TencentCloud_SDK\source\include\qcloud_config.h + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/startup_stm32l496xx.s b/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/startup_stm32l496xx.s new file mode 100644 index 00000000..3ebfcc32 --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/tencent_cloud_sdk_mqtt/startup_stm32l496xx.s @@ -0,0 +1,450 @@ +;******************************************************************************* +;* File Name : startup_stm32l496xx.s +;* Author : MCD Application Team +;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD DMA2D_IRQHandler ; DMA2D global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +DCMI_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +DMA2D_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/board/NUCLEO_STM32L496ZG/TOS-CONFIG/tos_config.h b/board/NUCLEO_STM32L496ZG/TOS-CONFIG/tos_config.h new file mode 100644 index 00000000..f3fd4f22 --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/TOS-CONFIG/tos_config.h @@ -0,0 +1,55 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "stm32l4xx.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 0u + +#define TOS_CFG_OBJECT_VERIFY_EN 1u + +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 1u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 1u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x8000 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_MESSAGE_QUEUE_EN 1u + +#define TOS_CFG_MAIL_QUEUE_EN 1u + +#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u + +#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 1u + +#define TOS_CFG_TIMER_EN 1u + +#define TOS_CFG_PWR_MGR_EN 0u + +#define TOS_CFG_TICKLESS_EN 0u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u + +#define TOS_CFG_FAULT_BACKTRACE_EN 0u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 128u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK (SystemCoreClock) + +#define TOS_CFG_TIMER_AS_PROC 1u + +#endif + diff --git a/board/NUCLEO_STM32L496ZG/TOS_CONFIG/tos_config.h b/board/NUCLEO_STM32L496ZG/TOS_CONFIG/tos_config.h deleted file mode 100644 index 1c4b16e6..00000000 --- a/board/NUCLEO_STM32L496ZG/TOS_CONFIG/tos_config.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef _TOS_CONFIG_H_ -#define _TOS_CONFIG_H_ - -#include "stm32l4xx.h" - -#define TOS_CFG_TASK_PRIO_MAX 10u - -#define TOS_CFG_ROUND_ROBIN_EN 1u - -#define TOS_CFG_OBJECT_VERIFY_EN 0u - -#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u - -#define TOS_CFG_EVENT_EN 1u - -#define TOS_CFG_MMBLK_EN 1u - -#define TOS_CFG_MMHEAP_EN 1u - -#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x100 - -#define TOS_CFG_MUTEX_EN 1u - -#define TOS_CFG_TIMER_EN 1u - -#define TOS_CFG_SEM_EN 1u - -#define TOS_CFG_IDLE_TASK_STK_SIZE 80u - -#define TOS_CFG_CPU_TICK_PER_SECOND 1000u - -#define TOS_CFG_CPU_CLOCK (SystemCoreClock) - -#define TOS_CFG_TIMER_AS_PROC 1u - -#endif -