add support for Microchip SmartFusion2 family FPGA
This commit is contained in:
whik
24
board/Microchip_M2S010/BSP/Inc/config.h
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24
board/Microchip_M2S010/BSP/Inc/config.h
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@@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-06 whik first version
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*/
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#ifndef __CONFIG_H__
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#define __CONFIG_H__
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#include "mss_gpio.h"
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#include "mss_uart.h"
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#include <rthw.h>
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#include <rtthread.h>
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void sw0_isr(void *args);
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void sw1_isr(void *args);
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void boardInit(void);
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void sayHello(void);
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#endif
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7
board/Microchip_M2S010/BSP/Inc/main.h
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7
board/Microchip_M2S010/BSP/Inc/main.h
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@@ -0,0 +1,7 @@
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#ifndef _MAIN_H_
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#define _MAIN_H_
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#include "mcu_init.h"
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#include "cmsis_os.h"
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#endif /* _MAIN_H_ */
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19
board/Microchip_M2S010/BSP/Inc/mcu_init.h
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19
board/Microchip_M2S010/BSP/Inc/mcu_init.h
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@@ -0,0 +1,19 @@
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#ifndef _MCU_INIT_H_
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#define _MCU_INIT_H_
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#include "m2sxxx.h"
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#include "system_m2sxxx.h"
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#include "mss_uart.h"
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#include "mss_gpio.h"
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#include "tos_k.h"
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#include "tos_sys.h"
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _MCU_INIT_H_ */
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86
board/Microchip_M2S010/BSP/Src/board.c
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86
board/Microchip_M2S010/BSP/Src/board.c
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@@ -0,0 +1,86 @@
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-06 whik first version
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*/
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#include <stdint.h>
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#include <rthw.h>
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#include <rtthread.h>
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#define _SCB_BASE (0xE000E010UL)
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#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0))
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#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4))
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#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8))
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#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC))
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#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL))
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extern void SystemCoreClockUpdate(void);
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extern uint32_t SystemCoreClock;
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static uint32_t _SysTick_Config(rt_uint32_t ticks)
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{
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if ((ticks - 1) > 0xFFFFFF)
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{
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return 1;
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}
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_SYSTICK_LOAD = ticks - 1;
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_SYSTICK_PRI = 0xFF;
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_SYSTICK_VAL = 0;
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_SYSTICK_CTRL = 0x07;
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return 0;
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}
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#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
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#define RT_HEAP_SIZE 1024
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static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4)
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RT_WEAK void *rt_heap_begin_get(void)
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{
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return rt_heap;
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}
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RT_WEAK void *rt_heap_end_get(void)
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{
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return rt_heap + RT_HEAP_SIZE;
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}
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#endif
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/* This function will initial your board. */
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void rt_hw_board_init()
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{
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/* System Clock Update */
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SystemCoreClockUpdate();
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/* System Tick Configuration */
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_SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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/* Call components board initial (use INIT_BOARD_EXPORT()) */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
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rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
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#endif
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}
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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26
board/Microchip_M2S010/BSP/Src/main.c
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26
board/Microchip_M2S010/BSP/Src/main.c
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@@ -0,0 +1,26 @@
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#include "main.h"
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#define APPLICATION_TASK_STK_SIZE 1024
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extern void application_entry(void *arg);
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osThreadDef(application_entry, osPriorityNormal, 1, APPLICATION_TASK_STK_SIZE);
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__weak void application_entry(void *arg)
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{
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while (1) {
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printf("This is a demo task,please use your task entry!\r\n");
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tos_task_delay(1000);
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}
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}
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int main(void)
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{
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/* peripheral initial*/
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board_init();
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printf("Hello TencentOS-tiny! By Microchip SmartFusion2 Family FPGA<47><41><EFBFBD><EFBFBD>M2S010.\r\n");
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osKernelInitialize(); // TOS Tiny kernel initialize
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osThreadCreate(osThread(application_entry), NULL); // Create TOS Tiny task
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osKernelStart(); // Start TOS Tiny
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}
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38
board/Microchip_M2S010/BSP/Src/mcu_init.c
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38
board/Microchip_M2S010/BSP/Src/mcu_init.c
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@@ -0,0 +1,38 @@
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#include "mcu_init.h"
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mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;
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void board_init(void)
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{
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/* disable watchdog */
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SYSREG->WDOG_CR = 0;
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/* update system core clock */
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SystemCoreClockUpdate();
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/* mss gpio config */
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MSS_GPIO_init();
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MSS_GPIO_config(MSS_GPIO_0, MSS_GPIO_OUTPUT_MODE);
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MSS_GPIO_config(MSS_GPIO_1, MSS_GPIO_OUTPUT_MODE);
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/* set gpio output */
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MSS_GPIO_set_output(MSS_GPIO_0, 1);
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MSS_GPIO_set_output(MSS_GPIO_1, 0);
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/* mss uart initial: 115200, 8, no, 1 */
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MSS_UART_init(gp_my_uart,
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MSS_UART_115200_BAUD,
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MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
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printf("SystemCoreClock Frequency: %.2f MHz\r\n", SystemCoreClock/1000000.0);
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}
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void SysTick_Handler(void)
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{
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if (tos_knl_is_running())
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{
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tos_knl_irq_enter();
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tos_tick_handler();
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tos_knl_irq_leave();
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}
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}
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385
board/Microchip_M2S010/BSP/sys_config/sys_config.c
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385
board/Microchip_M2S010/BSP/sys_config/sys_config.c
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@@ -0,0 +1,385 @@
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/*******************************************************************************
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* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
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*
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* Smartfusion2 system configuration. This file is automatically generated
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* by the Libero tools. It contains the Smartfusion2 system configuration that
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* was selected during the hardware configuration flow.
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*
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*/
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#include "../../CMSIS/m2sxxx.h"
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#include "../../CMSIS/sys_init_cfg_types.h"
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#include "sys_config.h"
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/*==============================================================================
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* !!! WARNING !!!
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*==============================================================================
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* The project including this file must be linked so that the content of this
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* file is located in internal eNVM at run time. The content of this file is
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* used to configure the system prior to RAM content initialization. This means
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* that the content of the data structures below will be used before the copy
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* from LMA to VMA takes place. The LMA and VMA locations of the content of this
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* file must be identical for the system to be seamlessly configured as part of
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* the CMSIS boot process.
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*/
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/*==============================================================================
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* Clock configuration
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*/
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/* No configuration data structure required. */
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/*==============================================================================
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* Memory remapping configuration
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*/
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/* TBD. */
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/*==============================================================================
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* MDDR configuration
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*/
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#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
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#include "sys_config_mddr_define.h"
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MDDR_TypeDef * const g_m2s_mddr_addr = (MDDR_TypeDef *)0x40020800;
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const ddr_subsys_cfg_t g_m2s_mddr_subsys_config =
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{
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/*---------------------------------------------------------------------
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* DDR Controller registers.
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* All registers are 16-bit wide unless mentioned beside the definition.
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*/
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{
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MDDR_DDRC_DYN_SOFT_RESET_CR,
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MDDR_DDRC_RESERVED0,
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MDDR_DDRC_DYN_REFRESH_1_CR,
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MDDR_DDRC_DYN_REFRESH_2_CR,
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MDDR_DDRC_DYN_POWERDOWN_CR,
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MDDR_DDRC_DYN_DEBUG_CR,
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MDDR_DDRC_MODE_CR,
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MDDR_DDRC_ADDR_MAP_BANK_CR,
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MDDR_DDRC_ECC_DATA_MASK_CR,
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MDDR_DDRC_ADDR_MAP_COL_1_CR,
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MDDR_DDRC_ADDR_MAP_COL_2_CR,
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MDDR_DDRC_ADDR_MAP_ROW_1_CR,
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MDDR_DDRC_ADDR_MAP_ROW_2_CR,
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MDDR_DDRC_INIT_1_CR,
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MDDR_DDRC_CKE_RSTN_CYCLES_1_CR,
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MDDR_DDRC_CKE_RSTN_CYCLES_2_CR,
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MDDR_DDRC_INIT_MR_CR,
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MDDR_DDRC_INIT_EMR_CR,
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MDDR_DDRC_INIT_EMR2_CR,
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MDDR_DDRC_INIT_EMR3_CR,
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MDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,
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MDDR_DDRC_DRAM_RD_WR_LATENCY_CR,
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MDDR_DDRC_DRAM_RD_WR_PRE_CR,
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MDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,
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MDDR_DDRC_DRAM_RAS_TIMING_CR,
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MDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,
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MDDR_DDRC_DRAM_T_PD_CR,
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MDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,
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MDDR_DDRC_ODT_PARAM_1_CR,
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MDDR_DDRC_ODT_PARAM_2_CR,
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MDDR_DDRC_ADDR_MAP_COL_3_CR,
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MDDR_DDRC_MODE_REG_RD_WR_CR,
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MDDR_DDRC_MODE_REG_DATA_CR,
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MDDR_DDRC_PWR_SAVE_1_CR,
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MDDR_DDRC_PWR_SAVE_2_CR,
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MDDR_DDRC_ZQ_LONG_TIME_CR,
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MDDR_DDRC_ZQ_SHORT_TIME_CR,
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MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,
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MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,
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MDDR_DDRC_PERF_PARAM_1_CR,
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MDDR_DDRC_HPR_QUEUE_PARAM_1_CR,
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MDDR_DDRC_HPR_QUEUE_PARAM_2_CR,
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MDDR_DDRC_LPR_QUEUE_PARAM_1_CR,
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MDDR_DDRC_LPR_QUEUE_PARAM_2_CR,
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MDDR_DDRC_WR_QUEUE_PARAM_CR,
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MDDR_DDRC_PERF_PARAM_2_CR,
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MDDR_DDRC_PERF_PARAM_3_CR,
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MDDR_DDRC_DFI_RDDATA_EN_CR,
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MDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,
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MDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,
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MDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,
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MDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,
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MDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,
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MDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,
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MDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,
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MDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,
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MDDR_DDRC_AXI_FABRIC_PRI_ID_CR,
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},
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/*---------------------------------------------------------------------
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* DDR PHY configuration registers
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*/
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{
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MDDR_PHY_LOOPBACK_TEST_CR,
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MDDR_PHY_BOARD_LOOPBACK_CR,
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MDDR_PHY_CTRL_SLAVE_RATIO_CR,
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MDDR_PHY_CTRL_SLAVE_FORCE_CR,
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MDDR_PHY_CTRL_SLAVE_DELAY_CR,
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MDDR_PHY_DATA_SLICE_IN_USE_CR,
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MDDR_PHY_LVL_NUM_OF_DQ0_CR,
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MDDR_PHY_DQ_OFFSET_1_CR,
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MDDR_PHY_DQ_OFFSET_2_CR,
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MDDR_PHY_DQ_OFFSET_3_CR,
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MDDR_PHY_DIS_CALIB_RST_CR,
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MDDR_PHY_DLL_LOCK_DIFF_CR,
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MDDR_PHY_FIFO_WE_IN_DELAY_1_CR,
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MDDR_PHY_FIFO_WE_IN_DELAY_2_CR,
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MDDR_PHY_FIFO_WE_IN_DELAY_3_CR,
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MDDR_PHY_FIFO_WE_IN_FORCE_CR,
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MDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,
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MDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,
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MDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,
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MDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,
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MDDR_PHY_GATELVL_INIT_MODE_CR,
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MDDR_PHY_GATELVL_INIT_RATIO_1_CR,
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MDDR_PHY_GATELVL_INIT_RATIO_2_CR,
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MDDR_PHY_GATELVL_INIT_RATIO_3_CR,
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MDDR_PHY_GATELVL_INIT_RATIO_4_CR,
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MDDR_PHY_LOCAL_ODT_CR,
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MDDR_PHY_INVERT_CLKOUT_CR,
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MDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,
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MDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,
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MDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,
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MDDR_PHY_RD_DQS_SLAVE_FORCE_CR,
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MDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,
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MDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,
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MDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,
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MDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,
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MDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,
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MDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,
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MDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,
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MDDR_PHY_WR_DQS_SLAVE_FORCE_CR,
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MDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,
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MDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,
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MDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,
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MDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,
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MDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,
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MDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,
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MDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,
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MDDR_PHY_WR_DATA_SLAVE_FORCE_CR,
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MDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,
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MDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,
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MDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,
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||||
MDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,
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||||
MDDR_PHY_WRLVL_INIT_MODE_CR,
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||||
MDDR_PHY_WRLVL_INIT_RATIO_1_CR,
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||||
MDDR_PHY_WRLVL_INIT_RATIO_2_CR,
|
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MDDR_PHY_WRLVL_INIT_RATIO_3_CR,
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MDDR_PHY_WRLVL_INIT_RATIO_4_CR,
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MDDR_PHY_WR_RD_RL_CR,
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||||
MDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,
|
||||
MDDR_PHY_RDC_WE_TO_RE_DELAY_CR,
|
||||
MDDR_PHY_USE_FIXED_RE_CR,
|
||||
MDDR_PHY_USE_RANK0_DELAYS_CR,
|
||||
MDDR_PHY_USE_LVL_TRNG_LEVEL_CR,
|
||||
MDDR_PHY_DYN_CONFIG_CR,
|
||||
MDDR_PHY_RD_WR_GATE_LVL_CR,
|
||||
MDDR_PHY_DYN_RESET_CR
|
||||
},
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||||
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/*---------------------------------------------------------------------
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||||
* FIC-64 registers
|
||||
* These registers are 16-bit wide and 32-bit aligned.
|
||||
*/
|
||||
{
|
||||
MDDR_DDR_FIC_NB_ADDR_CR,
|
||||
MDDR_DDR_FIC_NBRWB_SIZE_CR,
|
||||
MDDR_DDR_FIC_WB_TIMEOUT_CR,
|
||||
MDDR_DDR_FIC_HPD_SW_RW_EN_CR,
|
||||
MDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,
|
||||
MDDR_DDR_FIC_SW_WR_ERCLR_CR,
|
||||
MDDR_DDR_FIC_ERR_INT_ENABLE_CR,
|
||||
MDDR_DDR_FIC_NUM_AHB_MASTERS_CR,
|
||||
MDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,
|
||||
MDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,
|
||||
MDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/*==============================================================================
|
||||
* FDDR configuration
|
||||
*/
|
||||
#if MSS_SYS_FDDR_CONFIG_BY_CORTEX
|
||||
|
||||
#include "sys_config_fddr_define.h"
|
||||
|
||||
FDDR_TypeDef * const g_m2s_fddr_addr = (FDDR_TypeDef *)0x40021000;
|
||||
|
||||
const fddr_sysreg_t g_m2s_fddr_sysreg_subsys_config =
|
||||
{
|
||||
0x0001u, /* PLL_CONFIG_LOW_1 */
|
||||
0x0002u, /* PLL_CONFIG_LOW_2 */
|
||||
0x0003u, /* PLL_CONFIG_HIGH */
|
||||
0x0004u, /* FACC_CLK_EN */
|
||||
0x0005u, /* FACC_MUX_CONFIG */
|
||||
0x0006u, /* FACC_DIVISOR_RATIO */
|
||||
0x0007u, /* PLL_DELAY_LINE_SEL */
|
||||
0x0008u, /* SOFT_RESET */
|
||||
0x0009u, /* IO_CALIB */
|
||||
0x000Au, /* INTERRUPT_ENABLE */
|
||||
0x000Bu, /* AXI_AHB_MODE_SEL */
|
||||
0x000Cu /* PHY_SELF_REF_EN */
|
||||
};
|
||||
|
||||
const ddr_subsys_cfg_t g_m2s_fddr_subsys_config =
|
||||
{
|
||||
/*---------------------------------------------------------------------
|
||||
* DDR Controller registers.
|
||||
* All registers are 16-bit wide unless mentioned beside the definition.
|
||||
*/
|
||||
{
|
||||
FDDR_DDRC_DYN_SOFT_RESET_CR,
|
||||
FDDR_DDRC_RESERVED0,
|
||||
FDDR_DDRC_DYN_REFRESH_1_CR,
|
||||
FDDR_DDRC_DYN_REFRESH_2_CR,
|
||||
FDDR_DDRC_DYN_POWERDOWN_CR,
|
||||
FDDR_DDRC_DYN_DEBUG_CR,
|
||||
FDDR_DDRC_MODE_CR,
|
||||
FDDR_DDRC_ADDR_MAP_BANK_CR,
|
||||
FDDR_DDRC_ECC_DATA_MASK_CR,
|
||||
FDDR_DDRC_ADDR_MAP_COL_1_CR,
|
||||
FDDR_DDRC_ADDR_MAP_COL_2_CR,
|
||||
FDDR_DDRC_ADDR_MAP_ROW_1_CR,
|
||||
FDDR_DDRC_ADDR_MAP_ROW_2_CR,
|
||||
FDDR_DDRC_INIT_1_CR,
|
||||
FDDR_DDRC_CKE_RSTN_CYCLES_1_CR,
|
||||
FDDR_DDRC_CKE_RSTN_CYCLES_2_CR,
|
||||
FDDR_DDRC_INIT_MR_CR,
|
||||
FDDR_DDRC_INIT_EMR_CR,
|
||||
FDDR_DDRC_INIT_EMR2_CR,
|
||||
FDDR_DDRC_INIT_EMR3_CR,
|
||||
FDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,
|
||||
FDDR_DDRC_DRAM_RD_WR_LATENCY_CR,
|
||||
FDDR_DDRC_DRAM_RD_WR_PRE_CR,
|
||||
FDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,
|
||||
FDDR_DDRC_DRAM_RAS_TIMING_CR,
|
||||
FDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,
|
||||
FDDR_DDRC_DRAM_T_PD_CR,
|
||||
FDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,
|
||||
FDDR_DDRC_ODT_PARAM_1_CR,
|
||||
FDDR_DDRC_ODT_PARAM_2_CR,
|
||||
FDDR_DDRC_ADDR_MAP_COL_3_CR,
|
||||
FDDR_DDRC_MODE_REG_RD_WR_CR,
|
||||
FDDR_DDRC_MODE_REG_DATA_CR,
|
||||
FDDR_DDRC_PWR_SAVE_1_CR,
|
||||
FDDR_DDRC_PWR_SAVE_2_CR,
|
||||
FDDR_DDRC_ZQ_LONG_TIME_CR,
|
||||
FDDR_DDRC_ZQ_SHORT_TIME_CR,
|
||||
FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,
|
||||
FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,
|
||||
FDDR_DDRC_PERF_PARAM_1_CR,
|
||||
FDDR_DDRC_HPR_QUEUE_PARAM_1_CR,
|
||||
FDDR_DDRC_HPR_QUEUE_PARAM_2_CR,
|
||||
FDDR_DDRC_LPR_QUEUE_PARAM_1_CR,
|
||||
FDDR_DDRC_LPR_QUEUE_PARAM_2_CR,
|
||||
FDDR_DDRC_WR_QUEUE_PARAM_CR,
|
||||
FDDR_DDRC_PERF_PARAM_2_CR,
|
||||
FDDR_DDRC_PERF_PARAM_3_CR,
|
||||
FDDR_DDRC_DFI_RDDATA_EN_CR,
|
||||
FDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,
|
||||
FDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,
|
||||
FDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,
|
||||
FDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,
|
||||
FDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,
|
||||
FDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,
|
||||
FDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,
|
||||
FDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,
|
||||
FDDR_DDRC_AXI_FABRIC_PRI_ID_CR
|
||||
},
|
||||
|
||||
/*---------------------------------------------------------------------
|
||||
* DDR PHY configuration registers
|
||||
*/
|
||||
{
|
||||
FDDR_PHY_LOOPBACK_TEST_CR,
|
||||
FDDR_PHY_BOARD_LOOPBACK_CR,
|
||||
FDDR_PHY_CTRL_SLAVE_RATIO_CR,
|
||||
FDDR_PHY_CTRL_SLAVE_FORCE_CR,
|
||||
FDDR_PHY_CTRL_SLAVE_DELAY_CR,
|
||||
FDDR_PHY_DATA_SLICE_IN_USE_CR,
|
||||
FDDR_PHY_LVL_NUM_OF_DQ0_CR,
|
||||
FDDR_PHY_DQ_OFFSET_1_CR,
|
||||
FDDR_PHY_DQ_OFFSET_2_CR,
|
||||
FDDR_PHY_DQ_OFFSET_3_CR,
|
||||
FDDR_PHY_DIS_CALIB_RST_CR,
|
||||
FDDR_PHY_DLL_LOCK_DIFF_CR,
|
||||
FDDR_PHY_FIFO_WE_IN_DELAY_1_CR,
|
||||
FDDR_PHY_FIFO_WE_IN_DELAY_2_CR,
|
||||
FDDR_PHY_FIFO_WE_IN_DELAY_3_CR,
|
||||
FDDR_PHY_FIFO_WE_IN_FORCE_CR,
|
||||
FDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,
|
||||
FDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,
|
||||
FDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,
|
||||
FDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,
|
||||
FDDR_PHY_GATELVL_INIT_MODE_CR,
|
||||
FDDR_PHY_GATELVL_INIT_RATIO_1_CR,
|
||||
FDDR_PHY_GATELVL_INIT_RATIO_2_CR,
|
||||
FDDR_PHY_GATELVL_INIT_RATIO_3_CR,
|
||||
FDDR_PHY_GATELVL_INIT_RATIO_4_CR,
|
||||
FDDR_PHY_LOCAL_ODT_CR,
|
||||
FDDR_PHY_INVERT_CLKOUT_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_FORCE_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,
|
||||
FDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_FORCE_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,
|
||||
FDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_FORCE_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,
|
||||
FDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,
|
||||
FDDR_PHY_WRLVL_INIT_MODE_CR,
|
||||
FDDR_PHY_WRLVL_INIT_RATIO_1_CR,
|
||||
FDDR_PHY_WRLVL_INIT_RATIO_2_CR,
|
||||
FDDR_PHY_WRLVL_INIT_RATIO_3_CR,
|
||||
FDDR_PHY_WRLVL_INIT_RATIO_4_CR,
|
||||
FDDR_PHY_WR_RD_RL_CR,
|
||||
FDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,
|
||||
FDDR_PHY_RDC_WE_TO_RE_DELAY_CR,
|
||||
FDDR_PHY_USE_FIXED_RE_CR,
|
||||
FDDR_PHY_USE_RANK0_DELAYS_CR,
|
||||
FDDR_PHY_USE_LVL_TRNG_LEVEL_CR,
|
||||
FDDR_PHY_DYN_CONFIG_CR,
|
||||
FDDR_PHY_RD_WR_GATE_LVL_CR,
|
||||
FDDR_PHY_DYN_RESET_CR,
|
||||
},
|
||||
|
||||
/*---------------------------------------------------------------------
|
||||
* FIC-64 registers
|
||||
* These registers are 16-bit wide and 32-bit aligned.
|
||||
*/
|
||||
{
|
||||
FDDR_DDR_FIC_NB_ADDR_CR,
|
||||
FDDR_DDR_FIC_NBRWB_SIZE_CR,
|
||||
FDDR_DDR_FIC_WB_TIMEOUT_CR,
|
||||
FDDR_DDR_FIC_HPD_SW_RW_EN_CR,
|
||||
FDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,
|
||||
FDDR_DDR_FIC_SW_WR_ERCLR_CR,
|
||||
FDDR_DDR_FIC_ERR_INT_ENABLE_CR,
|
||||
FDDR_DDR_FIC_NUM_AHB_MASTERS_CR,
|
||||
FDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,
|
||||
FDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,
|
||||
FDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
66
board/Microchip_M2S010/BSP/sys_config/sys_config.h
Normal file
66
board/Microchip_M2S010/BSP/sys_config/sys_config.h
Normal file
@@ -0,0 +1,66 @@
|
||||
/*******************************************************************************
|
||||
* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
|
||||
*
|
||||
* Smartfusion2 system configuration. This file is automatically generated
|
||||
* by the Libero tools.
|
||||
*
|
||||
*/
|
||||
#ifndef MSS_SYSTEM_CONFIGURATION
|
||||
#define MSS_SYSTEM_CONFIGURATION
|
||||
|
||||
/*==============================================================================
|
||||
* Clock configuration
|
||||
*/
|
||||
#include "sys_config_mss_clocks.h"
|
||||
|
||||
/*==============================================================================
|
||||
* Memory remapping configuration
|
||||
*/
|
||||
/* TBD */
|
||||
|
||||
/*==============================================================================
|
||||
* FACC_INIT (Cortex-M3 runs the FACC INIT procedure)
|
||||
* Only set to 1 for design targeting the M2S050T_ES device
|
||||
*/
|
||||
#define MSS_SYS_FACC_INIT_BY_CORTEX 0
|
||||
|
||||
/*==============================================================================
|
||||
* MDDR configuration
|
||||
*/
|
||||
#define MSS_SYS_MDDR_CONFIG_BY_CORTEX 0
|
||||
|
||||
/*==============================================================================
|
||||
* FDDR configuration
|
||||
*/
|
||||
#define MSS_SYS_FDDR_CONFIG_BY_CORTEX 0
|
||||
|
||||
/*==============================================================================
|
||||
* SERDES Interface configuration
|
||||
*/
|
||||
#define MSS_SYS_SERDES_0_CONFIG_BY_CORTEX 0
|
||||
#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX
|
||||
#include "sys_config_SERDESIF_0.h"
|
||||
#endif
|
||||
|
||||
#define MSS_SYS_SERDES_1_CONFIG_BY_CORTEX 0
|
||||
#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX
|
||||
#include "sys_config_SERDESIF_1.h"
|
||||
#endif
|
||||
|
||||
#define MSS_SYS_SERDES_2_CONFIG_BY_CORTEX 0
|
||||
#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX
|
||||
#include "sys_config_SERDESIF_2.h"
|
||||
#endif
|
||||
|
||||
#define MSS_SYS_SERDES_3_CONFIG_BY_CORTEX 0
|
||||
#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX
|
||||
#include "sys_config_SERDESIF_3.h"
|
||||
#endif
|
||||
|
||||
/*==============================================================================
|
||||
* Cache configuration
|
||||
*/
|
||||
#define MSS_SYS_CACHE_CONFIG_BY_CORTEX 0
|
||||
|
||||
#endif /* MSS_SYSTEM_CONFIGURATION */
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
/*=============================================================*/
|
||||
/* Created by Microsemi SmartDesign Fri May 22 15:04:18 2020 */
|
||||
/* */
|
||||
/* Warning: Do not modify this file, it may lead to unexpected */
|
||||
/* functional failures in your design. */
|
||||
/* */
|
||||
/*=============================================================*/
|
||||
|
||||
#ifndef SYS_CONFIG_MSS_CLOCKS
|
||||
#define SYS_CONFIG_MSS_CLOCKS
|
||||
|
||||
#define MSS_SYS_M3_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_MDDR_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_APB_0_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_APB_1_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_APB_2_CLK_FREQ 25000000u
|
||||
#define MSS_SYS_FIC_0_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_FIC_1_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_FIC64_CLK_FREQ 100000000u
|
||||
|
||||
#endif /* SYS_CONFIG_MSS_CLOCKS */
|
||||
BIN
board/Microchip_M2S010/IMAGE/connect_core.jpg
Normal file
BIN
board/Microchip_M2S010/IMAGE/connect_core.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 152 KiB |
BIN
board/Microchip_M2S010/IMAGE/download_complete.jpg
Normal file
BIN
board/Microchip_M2S010/IMAGE/download_complete.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 158 KiB |
BIN
board/Microchip_M2S010/IMAGE/file_structure.jpg
Normal file
BIN
board/Microchip_M2S010/IMAGE/file_structure.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 193 KiB |
BIN
board/Microchip_M2S010/IMAGE/flash_algorithm.jpg
Normal file
BIN
board/Microchip_M2S010/IMAGE/flash_algorithm.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 154 KiB |
BIN
board/Microchip_M2S010/IMAGE/microchip_logo.png
Normal file
BIN
board/Microchip_M2S010/IMAGE/microchip_logo.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 28 KiB |
BIN
board/Microchip_M2S010/IMAGE/smartfusion_block_diagram.jpg
Normal file
BIN
board/Microchip_M2S010/IMAGE/smartfusion_block_diagram.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 1007 KiB |
BIN
board/Microchip_M2S010/IMAGE/top_sd.jpg
Normal file
BIN
board/Microchip_M2S010/IMAGE/top_sd.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 120 KiB |
BIN
board/Microchip_M2S010/IMAGE/uart_printf.jpg
Normal file
BIN
board/Microchip_M2S010/IMAGE/uart_printf.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 26 KiB |
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
|
||||
|
||||
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
|
||||
<events>
|
||||
</events>
|
||||
|
||||
</component_viewer>
|
||||
39
board/Microchip_M2S010/KEIL/hello_world/JLinkSettings.ini
Normal file
39
board/Microchip_M2S010/KEIL/hello_world/JLinkSettings.ini
Normal file
@@ -0,0 +1,39 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
MonModeVTableAddr = 0xFFFFFFFF
|
||||
MonModeDebug = 0
|
||||
MaxNumAPs = 0
|
||||
LowPowerHandlingMode = 0
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 0
|
||||
Device="ARM7"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
26
board/Microchip_M2S010/KEIL/hello_world/M2Sxxx_esram.ini
Normal file
26
board/Microchip_M2S010/KEIL/hello_world/M2Sxxx_esram.ini
Normal file
@@ -0,0 +1,26 @@
|
||||
FUNC void Setup (void) {
|
||||
_WDWORD(0x4003806C, 0x00000000); // Watchdog disable
|
||||
_WDWORD(0xE000ED08, 0x20000000); // Relocate vector table to start of eSRAM (0x20000000)
|
||||
}
|
||||
|
||||
FUNC void SetupPC_SP (void) {
|
||||
SP = _RDWORD(0x20000000); // Setup Stack Pointer
|
||||
PC = _RDWORD(0x20000004); // Setup Program Counter
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
** Invoke the function at debugger startup
|
||||
**-----------------------------------------------------------------*/
|
||||
|
||||
Setup();
|
||||
SetupPC_SP();
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
** Execute upon software RESET
|
||||
**-----------------------------------------------------------------*/
|
||||
FUNC void OnResetExec(void) {
|
||||
Setup();
|
||||
SetupPC_SP();
|
||||
}
|
||||
|
||||
|
||||
821
board/Microchip_M2S010/KEIL/hello_world/Microchip_M2S010.uvoptx
Normal file
821
board/Microchip_M2S010/KEIL/hello_world/Microchip_M2S010.uvoptx
Normal file
@@ -0,0 +1,821 @@
|
||||
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|
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|
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|
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?<
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667
board/Microchip_M2S010/KEIL/hello_world/Microchip_M2S010.uvprojx
Normal file
667
board/Microchip_M2S010/KEIL/hello_world/Microchip_M2S010.uvprojx
Normal file
@@ -0,0 +1,667 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
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<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
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|
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<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
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<Targets>
|
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<Target>
|
||||
<TargetName>Microchip_M2S010</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>M2S010</Device>
|
||||
<Vendor>Microsemi</Vendor>
|
||||
<PackID>Microsemi.M2Sxxx.1.0.64</PackID>
|
||||
<PackURL>http://cores.actel-ip.com/CMSIS-Pack</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x10000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M2Sxxx_256 -FS00 -FL040000 -FP0($$Device:M2S010$Flash\M2Sxxx_256.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:M2S010$CMSIS\m2sxxx.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:M2S010$SVD\M2Sxxx.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Obj\</OutputDirectory>
|
||||
<OutputName>Microchip_M2S010</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Obj\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M3"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>1</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>MICROSEMI_STDIO_THRU_MMUART0</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\BSP\Inc;..\..\BSP\sys_config;..\..\..\..\platform\hal\Microchip;..\..\..\..\platform\hal\Microchip\CortexM3;..\..\..\..\platform\hal\Microchip\CortexM3\Keil;..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\Inc;..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\CMSIS;..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\CMSIS\startup_arm;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m3\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\TOS_CONFIG</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\CMSIS\startup_arm\smartfusion2_execute_in_place.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Application/MDK-ARM</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_m2sxxx.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\startup_m2sxxx.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Application/User</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>main.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\..\BSP\Inc\main.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>mcu_init.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\mcu_init.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>mcu_init.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\..\BSP\Inc\mcu_init.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>sys_config.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\sys_config\sys_config.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>sys_config_mss_clocks.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\..\BSP\sys_config\sys_config_mss_clocks.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Drivers/SmartFusion2_HAL_Driver</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>mss_uart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\Src\mss_uart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>mss_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\Src\mss_gpio.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Drivers/CMSIS</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_m2sxxx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\CMSIS\system_m2sxxx.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>retarget.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\CMSIS\startup_arm\retarget.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>low_level_init.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\Microchip\SmartFusion2\CMSIS\startup_arm\low_level_init.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/arch</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_cpu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\cortex-m3\armcc\port_c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_s.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\cortex-m3\armcc\port_s.S</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/kernel</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_barrier.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_barrier.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_binary_heap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_binary_heap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_bitmap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_bitmap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_char_fifo.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_char_fifo.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_completion.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_completion.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_countdownlatch.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_event.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_event.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_global.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_global.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmblk.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mmblk.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmheap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mutex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mutex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_pend.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_pend.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_ring_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_robin.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_robin.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_rwlock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_rwlock.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sched.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sched.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_stopwatch.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_stopwatch.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sys.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sys.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_task.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_task.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_tick.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_tick.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_time.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_time.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_timer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/cmsis</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>cmsis_os.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\osal\cmsis_os\cmsis_os.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/config</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_config.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\..\TOS_CONFIG\tos_config.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>examples</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>hello_world.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\examples\hello_world\hello_world.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,20 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'Microchip_M2S010'
|
||||
* Target: 'Microchip_M2S010'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "m2sxxx.h"
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
586
board/Microchip_M2S010/KEIL/hello_world/startup_m2sxxx.s
Normal file
586
board/Microchip_M2S010/KEIL/hello_world/startup_m2sxxx.s
Normal file
@@ -0,0 +1,586 @@
|
||||
;*******************************************************************************
|
||||
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
|
||||
; SmartFusion2 startup code for Keil-MDK.
|
||||
;
|
||||
; SmartFusion2 vector table and startup code for ARM tool chain.
|
||||
;
|
||||
; SVN $Revision: 7419 $
|
||||
; SVN $Date: 2015-05-15 21:20:21 +0530 (Fri, 15 May 2015) $
|
||||
;
|
||||
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00001000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
stack_start
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
stack_end
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
;===============================================================================
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WdogWakeup_IRQHandler
|
||||
DCD RTC_Wakeup_IRQHandler
|
||||
DCD SPI0_IRQHandler
|
||||
DCD SPI1_IRQHandler
|
||||
DCD I2C0_IRQHandler
|
||||
DCD I2C0_SMBAlert_IRQHandler
|
||||
DCD I2C0_SMBus_IRQHandler
|
||||
DCD I2C1_IRQHandler
|
||||
DCD I2C1_SMBAlert_IRQHandler
|
||||
DCD I2C1_SMBus_IRQHandler
|
||||
DCD UART0_IRQHandler
|
||||
DCD UART1_IRQHandler
|
||||
DCD EthernetMAC_IRQHandler
|
||||
DCD DMA_IRQHandler
|
||||
DCD Timer1_IRQHandler
|
||||
DCD Timer2_IRQHandler
|
||||
DCD CAN_IRQHandler
|
||||
DCD ENVM0_IRQHandler
|
||||
DCD ENVM1_IRQHandler
|
||||
DCD ComBlk_IRQHandler
|
||||
DCD USB_IRQHandler
|
||||
DCD USB_DMA_IRQHandler
|
||||
DCD PLL_Lock_IRQHandler
|
||||
DCD PLL_LockLost_IRQHandler
|
||||
DCD CommSwitchError_IRQHandler
|
||||
DCD CacheError_IRQHandler
|
||||
DCD DDR_IRQHandler
|
||||
DCD HPDMA_Complete_IRQHandler
|
||||
DCD HPDMA_Error_IRQHandler
|
||||
DCD ECC_Error_IRQHandler
|
||||
DCD MDDR_IOCalib_IRQHandler
|
||||
DCD FAB_PLL_Lock_IRQHandler
|
||||
DCD FAB_PLL_LockLost_IRQHandler
|
||||
DCD FIC64_IRQHandler
|
||||
DCD FabricIrq0_IRQHandler
|
||||
DCD FabricIrq1_IRQHandler
|
||||
DCD FabricIrq2_IRQHandler
|
||||
DCD FabricIrq3_IRQHandler
|
||||
DCD FabricIrq4_IRQHandler
|
||||
DCD FabricIrq5_IRQHandler
|
||||
DCD FabricIrq6_IRQHandler
|
||||
DCD FabricIrq7_IRQHandler
|
||||
DCD FabricIrq8_IRQHandler
|
||||
DCD FabricIrq9_IRQHandler
|
||||
DCD FabricIrq10_IRQHandler
|
||||
DCD FabricIrq11_IRQHandler
|
||||
DCD FabricIrq12_IRQHandler
|
||||
DCD FabricIrq13_IRQHandler
|
||||
DCD FabricIrq14_IRQHandler
|
||||
DCD FabricIrq15_IRQHandler
|
||||
DCD GPIO0_IRQHandler
|
||||
DCD GPIO1_IRQHandler
|
||||
DCD GPIO2_IRQHandler
|
||||
DCD GPIO3_IRQHandler
|
||||
DCD GPIO4_IRQHandler
|
||||
DCD GPIO5_IRQHandler
|
||||
DCD GPIO6_IRQHandler
|
||||
DCD GPIO7_IRQHandler
|
||||
DCD GPIO8_IRQHandler
|
||||
DCD GPIO9_IRQHandler
|
||||
DCD GPIO10_IRQHandler
|
||||
DCD GPIO11_IRQHandler
|
||||
DCD GPIO12_IRQHandler
|
||||
DCD GPIO13_IRQHandler
|
||||
DCD GPIO14_IRQHandler
|
||||
DCD GPIO15_IRQHandler
|
||||
DCD GPIO16_IRQHandler
|
||||
DCD GPIO17_IRQHandler
|
||||
DCD GPIO18_IRQHandler
|
||||
DCD GPIO19_IRQHandler
|
||||
DCD GPIO20_IRQHandler
|
||||
DCD GPIO21_IRQHandler
|
||||
DCD GPIO22_IRQHandler
|
||||
DCD GPIO23_IRQHandler
|
||||
DCD GPIO24_IRQHandler
|
||||
DCD GPIO25_IRQHandler
|
||||
DCD GPIO26_IRQHandler
|
||||
DCD GPIO27_IRQHandler
|
||||
DCD GPIO28_IRQHandler
|
||||
DCD GPIO29_IRQHandler
|
||||
DCD GPIO30_IRQHandler
|
||||
DCD GPIO31_IRQHandler
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;===============================================================================
|
||||
; Reset Handler
|
||||
;
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT low_level_init
|
||||
IMPORT __main
|
||||
|
||||
;---------------------------------------------------------------
|
||||
; Initialize stack RAM content to initialize the error detection
|
||||
; and correction (EDAC). This is done if EDAC is enabled for the
|
||||
; eSRAM blocks or the ECC/SECDED is enabled for the MDDR.
|
||||
; Register R11 is used to keep track of the RAM intialization
|
||||
; decision outcome for later use for heap RAM initialization at
|
||||
; the end of the startup code.
|
||||
; Please note that the stack has to be located in eSRAM at this
|
||||
; point and cannot be located in MDDR since MDDR is not available
|
||||
; at this point.
|
||||
; The bits of the content of register R11 have the foolwing
|
||||
; meaning:
|
||||
; reg11[0]: eSRAM EDAC enabled
|
||||
; reg11[1]: MDDR ECC/SECDED enabled
|
||||
;
|
||||
MOV R11, #0
|
||||
LDR R0, SF2_MDDR_MODE_CR
|
||||
LDR R0, [R0]
|
||||
LDR R1, SF2_EDAC_CR
|
||||
LDR R1, [R1]
|
||||
AND R1, R1, #3
|
||||
AND R0, R0, #0x1C
|
||||
CMP R0, #0x14
|
||||
BNE check_esram_edac
|
||||
ORR R11, R11, #2
|
||||
check_esram_edac
|
||||
CMP R1, #0
|
||||
BEQ check_stack_init
|
||||
ORR R11, R11, #1
|
||||
check_stack_init
|
||||
CMP R11, #0
|
||||
BEQ call_system_init
|
||||
clear_stack
|
||||
LDR R0, =stack_start
|
||||
LDR R1, =stack_end
|
||||
LDR R2, RAM_INIT_PATTERN
|
||||
BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */
|
||||
|
||||
;---------------------------------------------------------------
|
||||
; Call SystemInit() to perform Libero specified configuration.
|
||||
;
|
||||
call_system_init
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =low_level_init
|
||||
BLX R0
|
||||
|
||||
;---------------------------------------------------------------
|
||||
; Modify MDDR configuration if ECC/SECDED is enabled for MDDR.
|
||||
; Enable write combining on MDDR bridge, disable non-bufferable
|
||||
; regions.
|
||||
;
|
||||
adjust_mddr_cfg
|
||||
AND R10, R11, #0x2
|
||||
CMP R10, #0
|
||||
BEQ branch_to_main
|
||||
LDR R0, SF2_DDRB_NB_SIZE
|
||||
LDR R1, SF2_DDRB_CR
|
||||
LDR R2, [R0]
|
||||
LDR R3, [R1]
|
||||
push {R0, R1, R2, R3}
|
||||
MOV R2, #0
|
||||
MOV R3, #0xFF
|
||||
STR R2, [R0]
|
||||
STR R3, [R1]
|
||||
|
||||
; --------------------------------------------------------------
|
||||
; Initialize heap RAM content to initialize the error detection
|
||||
; and correction (EDAC). We use the decision made earlier in the
|
||||
; startup code of whether or not the stack RAM should be
|
||||
; initialized. This decision is held in register R11. A non-zero
|
||||
; value indicates that the RAM content should be initialized.
|
||||
;
|
||||
clear_heap
|
||||
CMP R11, #0
|
||||
BEQ branch_to_main
|
||||
LDR R0, =__heap_base
|
||||
LDR R1, =__heap_limit
|
||||
LDR R2, HEAP_INIT_PATTERN
|
||||
BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */
|
||||
|
||||
;---------------------------------------------------------------
|
||||
; Branch to __main
|
||||
;
|
||||
branch_to_main
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
SF2_EDAC_CR DCD 0x40038038
|
||||
SF2_DDRB_NB_SIZE DCD 0x40038030
|
||||
SF2_DDRB_CR DCD 0x40038034
|
||||
SF2_MDDR_MODE_CR DCD 0x40020818
|
||||
RAM_INIT_PATTERN DCD 0x00000000
|
||||
HEAP_INIT_PATTERN DCD 0x00000000
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
; * fill_memory.
|
||||
; * @brief Fills memory with Pattern contained in r2
|
||||
; * This routine uses the stmne instruction to copy 4 words at a time which is very efficient
|
||||
; * The instruction can only write to word aligned memory, hence the code at the start and end of this routine
|
||||
; * to handle possible unaligned bytes at start and end.
|
||||
; *
|
||||
; * @param param1 r0: start address
|
||||
; * @param param2 r1: end address
|
||||
; * @param param3 r2: FILL PATTETN
|
||||
; *
|
||||
; * @note note: Most efficient if memory aligned. Linker ALIGN(4) command
|
||||
; * should be used as per example linker scripts
|
||||
; * Stack is not used in this routine
|
||||
; * register contents r4, r5, r6, r7, r8, r9, will are used and will be returned undefined
|
||||
; * @return none - Used Registers are not preserved
|
||||
; */
|
||||
|
||||
fill_memory PROC
|
||||
;push {r4, r5, r6, r7, r8, r9, lr} We will not use stack as may be not available */
|
||||
cmp r0, r1
|
||||
beq fill_memory_exit ; Exit early if source and destination the same */
|
||||
; copy non-aligned bytes at the start */
|
||||
and.w r6, r0, #3 ; see if non-alaigned bytes at the start */
|
||||
cmp r6, #0
|
||||
beq fill_memory_end_start ; no spare bytes at start, continue */
|
||||
mov r5, #4
|
||||
sub.w r4, r5, r6 ; now have number of non-aligned bytes in r4 */
|
||||
mov r7, #8
|
||||
mul r8, r7, r6 ; calculate number of shifts required to initalise pattern for non-aligned bytes */
|
||||
mov r9, r2 ; copy pattern */
|
||||
ror r9, r9, r8 ; Rotate right to keep pattern consistent */
|
||||
fill_memory_spare_bytes_start ; From above, R0 contains source address, R1 contains destination address */
|
||||
cmp r4, #0 ; no spare bytes at end- end now */
|
||||
beq fill_memory_end_start
|
||||
strb r9, [r0] ; fill byte */
|
||||
ror.w r9, r9, r7 ; Rotate right by one byte for the next time, to keep pattern consistent */
|
||||
add r0, r0, #1 ; add one to address */
|
||||
subs r4, r4, #1 ; subtract one from byte count 1 */
|
||||
b fill_memory_spare_bytes_start
|
||||
fill_memory_end_start
|
||||
mov r6, #0
|
||||
mov r7, r1 ; save end address */
|
||||
subs r1, r1, r0 ; Calculate number of bytes to fill */
|
||||
mov r8,r1 ; Save copy of byte count */
|
||||
asrs r1,r1, #4 ; Div by 16 to get number of chunks to move */
|
||||
mov r9, r2 ; copy pattern */
|
||||
mov r4, r2 ; copy pattern */
|
||||
mov r5, r2 ; copy pattern */
|
||||
cmp r1, r6 ; compare to see if all chunks copied */
|
||||
beq fill_memory_spare_bytes_end
|
||||
fill_memory_loop
|
||||
it ne
|
||||
stmne r0!, {r2, r4, r5, r9} ; copy pattern- note: stmne instruction must me word aligned (address in r0) */
|
||||
add.w r6, r6, #1 ; use Thumb2- make sure condition code reg. not updated */
|
||||
cmp r1, r6 ; compare to see if all chunks copied */
|
||||
bne fill_memory_loop
|
||||
fill_memory_spare_bytes_end ; copy spare bytes at the end if any */
|
||||
and.w r8, r8, #15 ; get spare bytes --check can you do an ands? */
|
||||
fill_memory_spare_end_loop ; From above, R0 contains source address, R1 contains destination address */
|
||||
cmp r8, #0 ; no spare bytes at end- end now */
|
||||
beq fill_memory_exit
|
||||
strb r2, [r0]
|
||||
ror.w r2, r2, #8 ; Rotate right by one byte for the next time, to keep pattern consistent */
|
||||
add r0, r0, #1 ; add one to address */
|
||||
subs r8, r8, #1 ; subtract one from byte count 1 */
|
||||
b fill_memory_spare_end_loop
|
||||
fill_memory_exit
|
||||
bx lr ; We will not use pop as stack may be not available */
|
||||
ENDP
|
||||
|
||||
|
||||
|
||||
;===============================================================================
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WdogWakeup_IRQHandler [WEAK]
|
||||
EXPORT RTC_Wakeup_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_SMBAlert_IRQHandler [WEAK]
|
||||
EXPORT I2C0_SMBus_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT I2C1_SMBAlert_IRQHandler [WEAK]
|
||||
EXPORT I2C1_SMBus_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT EthernetMAC_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT Timer1_IRQHandler [WEAK]
|
||||
EXPORT Timer2_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT ENVM0_IRQHandler [WEAK]
|
||||
EXPORT ENVM1_IRQHandler [WEAK]
|
||||
EXPORT ComBlk_IRQHandler [WEAK]
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_DMA_IRQHandler [WEAK]
|
||||
EXPORT PLL_Lock_IRQHandler [WEAK]
|
||||
EXPORT PLL_LockLost_IRQHandler [WEAK]
|
||||
EXPORT CommSwitchError_IRQHandler [WEAK]
|
||||
EXPORT CacheError_IRQHandler [WEAK]
|
||||
EXPORT DDR_IRQHandler [WEAK]
|
||||
EXPORT HPDMA_Complete_IRQHandler [WEAK]
|
||||
EXPORT HPDMA_Error_IRQHandler [WEAK]
|
||||
EXPORT ECC_Error_IRQHandler [WEAK]
|
||||
EXPORT MDDR_IOCalib_IRQHandler [WEAK]
|
||||
EXPORT FAB_PLL_Lock_IRQHandler [WEAK]
|
||||
EXPORT FAB_PLL_LockLost_IRQHandler [WEAK]
|
||||
EXPORT FIC64_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq0_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq1_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq2_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq3_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq4_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq5_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq6_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq7_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq8_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq9_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq10_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq11_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq12_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq13_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq14_IRQHandler [WEAK]
|
||||
EXPORT FabricIrq15_IRQHandler [WEAK]
|
||||
EXPORT GPIO0_IRQHandler [WEAK]
|
||||
EXPORT GPIO1_IRQHandler [WEAK]
|
||||
EXPORT GPIO2_IRQHandler [WEAK]
|
||||
EXPORT GPIO3_IRQHandler [WEAK]
|
||||
EXPORT GPIO4_IRQHandler [WEAK]
|
||||
EXPORT GPIO5_IRQHandler [WEAK]
|
||||
EXPORT GPIO6_IRQHandler [WEAK]
|
||||
EXPORT GPIO7_IRQHandler [WEAK]
|
||||
EXPORT GPIO8_IRQHandler [WEAK]
|
||||
EXPORT GPIO9_IRQHandler [WEAK]
|
||||
EXPORT GPIO10_IRQHandler [WEAK]
|
||||
EXPORT GPIO11_IRQHandler [WEAK]
|
||||
EXPORT GPIO12_IRQHandler [WEAK]
|
||||
EXPORT GPIO13_IRQHandler [WEAK]
|
||||
EXPORT GPIO14_IRQHandler [WEAK]
|
||||
EXPORT GPIO15_IRQHandler [WEAK]
|
||||
EXPORT GPIO16_IRQHandler [WEAK]
|
||||
EXPORT GPIO17_IRQHandler [WEAK]
|
||||
EXPORT GPIO18_IRQHandler [WEAK]
|
||||
EXPORT GPIO19_IRQHandler [WEAK]
|
||||
EXPORT GPIO20_IRQHandler [WEAK]
|
||||
EXPORT GPIO21_IRQHandler [WEAK]
|
||||
EXPORT GPIO22_IRQHandler [WEAK]
|
||||
EXPORT GPIO23_IRQHandler [WEAK]
|
||||
EXPORT GPIO24_IRQHandler [WEAK]
|
||||
EXPORT GPIO25_IRQHandler [WEAK]
|
||||
EXPORT GPIO26_IRQHandler [WEAK]
|
||||
EXPORT GPIO27_IRQHandler [WEAK]
|
||||
EXPORT GPIO28_IRQHandler [WEAK]
|
||||
EXPORT GPIO29_IRQHandler [WEAK]
|
||||
EXPORT GPIO30_IRQHandler [WEAK]
|
||||
EXPORT GPIO31_IRQHandler [WEAK]
|
||||
|
||||
|
||||
WdogWakeup_IRQHandler
|
||||
RTC_Wakeup_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C0_SMBAlert_IRQHandler
|
||||
I2C0_SMBus_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
I2C1_SMBAlert_IRQHandler
|
||||
I2C1_SMBus_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
EthernetMAC_IRQHandler
|
||||
DMA_IRQHandler
|
||||
Timer1_IRQHandler
|
||||
Timer2_IRQHandler
|
||||
CAN_IRQHandler
|
||||
ENVM0_IRQHandler
|
||||
ENVM1_IRQHandler
|
||||
ComBlk_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_DMA_IRQHandler
|
||||
PLL_Lock_IRQHandler
|
||||
PLL_LockLost_IRQHandler
|
||||
CommSwitchError_IRQHandler
|
||||
CacheError_IRQHandler
|
||||
DDR_IRQHandler
|
||||
HPDMA_Complete_IRQHandler
|
||||
HPDMA_Error_IRQHandler
|
||||
ECC_Error_IRQHandler
|
||||
MDDR_IOCalib_IRQHandler
|
||||
FAB_PLL_Lock_IRQHandler
|
||||
FAB_PLL_LockLost_IRQHandler
|
||||
FIC64_IRQHandler
|
||||
FabricIrq0_IRQHandler
|
||||
FabricIrq1_IRQHandler
|
||||
FabricIrq2_IRQHandler
|
||||
FabricIrq3_IRQHandler
|
||||
FabricIrq4_IRQHandler
|
||||
FabricIrq5_IRQHandler
|
||||
FabricIrq6_IRQHandler
|
||||
FabricIrq7_IRQHandler
|
||||
FabricIrq8_IRQHandler
|
||||
FabricIrq9_IRQHandler
|
||||
FabricIrq10_IRQHandler
|
||||
FabricIrq11_IRQHandler
|
||||
FabricIrq12_IRQHandler
|
||||
FabricIrq13_IRQHandler
|
||||
FabricIrq14_IRQHandler
|
||||
FabricIrq15_IRQHandler
|
||||
GPIO0_IRQHandler
|
||||
GPIO1_IRQHandler
|
||||
GPIO2_IRQHandler
|
||||
GPIO3_IRQHandler
|
||||
GPIO4_IRQHandler
|
||||
GPIO5_IRQHandler
|
||||
GPIO6_IRQHandler
|
||||
GPIO7_IRQHandler
|
||||
GPIO8_IRQHandler
|
||||
GPIO9_IRQHandler
|
||||
GPIO10_IRQHandler
|
||||
GPIO11_IRQHandler
|
||||
GPIO12_IRQHandler
|
||||
GPIO13_IRQHandler
|
||||
GPIO14_IRQHandler
|
||||
GPIO15_IRQHandler
|
||||
GPIO16_IRQHandler
|
||||
GPIO17_IRQHandler
|
||||
GPIO18_IRQHandler
|
||||
GPIO19_IRQHandler
|
||||
GPIO20_IRQHandler
|
||||
GPIO21_IRQHandler
|
||||
GPIO22_IRQHandler
|
||||
GPIO23_IRQHandler
|
||||
GPIO24_IRQHandler
|
||||
GPIO25_IRQHandler
|
||||
GPIO26_IRQHandler
|
||||
GPIO27_IRQHandler
|
||||
GPIO28_IRQHandler
|
||||
GPIO29_IRQHandler
|
||||
GPIO30_IRQHandler
|
||||
GPIO31_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
mscc_post_hw_cfg_init PROC
|
||||
EXPORT mscc_post_hw_cfg_init [WEAK]
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
;===============================================================================
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
80
board/Microchip_M2S010/README.md
Normal file
80
board/Microchip_M2S010/README.md
Normal file
@@ -0,0 +1,80 @@
|
||||
## 移植TencentOS-tiny到Microchip SmartFusion2系列FPGA芯片上
|
||||
|
||||
### 1. BSP简介
|
||||
|
||||
移植 [TencentOS-tiny](https://cloud.tencent.com/product/tos-tiny) 实时操作系统到一款 **FPGA 芯片——M2S010** ，运行hello_world示例程序。该芯片属于 Microchip（原Microsemi）公司SmartFusion2系列，是一款**智能混合型FPGA**，片上除了 FPGA Fabric 逻辑部分，还包括一个 **ARM® Cortex™-M3 内核的 MCU**，主频最高 166MHz ，256KB eNVM，64KB eSRAM，集成GPIO、UART、I2C、SPI、CAN、USB等基本外设。
|
||||
|
||||
|
||||
|
||||
SmartFusion2 内部框图
|
||||
|
||||
|
||||
|
||||
### 2. 使用说明
|
||||
|
||||
#### 2.1 FPGA 工程设计
|
||||
|
||||
FPGA 部分使用 SmartDesign 图形化设计，只使用到了内部ARM处理器，不需要写 HDL 代码，时钟采用内部50M RC晶振输入，PLL 倍频 100M 提供给 MCU 使用，顶层配置如下图所示：
|
||||
|
||||
|
||||
|
||||
MSS 部分仅使用到了GPIO 和UART，GPIO_0和GPIO_1配置成输出输出模式用于驱动LED。
|
||||
|
||||
配置完成的 FPGA 工程下载：[fpga_prj.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/TencentOS-tiny/fpga_prj.rar)
|
||||
|
||||
管脚分配说明：
|
||||
|
||||
| 管脚名称 | 方向 | 管脚 |
|
||||
| -------- | ---- | ---- |
|
||||
| UART0_RX | 输入 | 1 |
|
||||
| UART0_TX | 输出 | 2 |
|
||||
| LED0 | 输出 | 129 |
|
||||
| LED1 | 输出 | 128 |
|
||||
| DEVRST_N | 输入 | 72 |
|
||||
|
||||
#### 2.2 ARM 程序设计
|
||||
|
||||
ARM 程序使用 Keil MDK 5.26 开发，需要安装 M2S 系列芯片支持包：[Microsemi.M2Sxxx.1.0.64.pack](http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack)
|
||||
|
||||
如果官网下载失败，可以到以下地址下载：[Microsemi.M2Sxxx.1.0.64.pack](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/TencentOS-tiny/Microsemi.M2Sxxx.1.0.64.pack)
|
||||
|
||||
在官方生成的示例工程目录下，添加 TencentOS-tiny 内核文件，并实现一些对接函数，最终的文件结构：
|
||||
|
||||
|
||||
|
||||
#### 2.3. 下载和运行
|
||||
|
||||
为了能让 J-Link 调试器连接到 ARM 内核，需要把 JTAG_SEL 引脚置为低电平，如果连接正常，可以检测到 ARM 芯片，如下图所示：
|
||||
|
||||
|
||||
|
||||
配置对应的 Flash 编程算法：
|
||||
|
||||
|
||||
|
||||
下载完成：
|
||||
|
||||
|
||||
|
||||
如果编译 & 烧写无误，下载完成之后，会在串口上看到 TencentOS-tiny 的运行信息：
|
||||
|
||||
|
||||
|
||||
### 3. 注意事项
|
||||
|
||||
- FPGA 开发环境基于 Libero V11.8.2.4，向上兼容，不支持低版本 Libero SoC。
|
||||
- ARM 开发环境基于 Keil MDK 5.26，使用 MDK5 需要安装对应器件支持包，MDK4 不用。
|
||||
- 调试器连接内部 ARM 核时，需要把 JTAG_SEL 拉低，否则调试器连接不上。
|
||||
- 内核时钟需要和 FPGA 中 MSS 配置的对应，Libero 自动生成的时钟文件，可以直接替换`TencentOS-tiny\board\Microchip_M2S010\BSP\sys_config`文件夹 。
|
||||
|
||||
### 4. 参考资料
|
||||
|
||||
- [TencentOS Tiny 简介-贡献代码](https://github.com/Tencent/TencentOS-tiny/blob/master/README.md)
|
||||
- [TencentOS Tiny 内核移植参考指南（Keil版）](https://github.com/Tencent/TencentOS-tiny/blob/master/doc/10.Porting_Manual_for_KEIL.md)
|
||||
- [Microsemi Libero系列中文教程](https://blog.csdn.net/whik1194/article/details/102901710)
|
||||
- [SmartFusion从FPGA到ARM系列教程](https://blog.csdn.net/whik1194/article/details/107104960)
|
||||
|
||||
### 5. 联系我
|
||||
|
||||
- Github：[whik](https://github.com/whik)
|
||||
- E-Mail：wangchao149@foxmail.com
|
||||
38
board/Microchip_M2S010/TOS_CONFIG/tos_config.h
Normal file
38
board/Microchip_M2S010/TOS_CONFIG/tos_config.h
Normal file
@@ -0,0 +1,38 @@
|
||||
#ifndef _TOS_CONFIG_H_
|
||||
#define _TOS_CONFIG_H_
|
||||
|
||||
#include "m2sxxx.h"
|
||||
#include "system_m2sxxx.h"
|
||||
|
||||
#define TOS_CFG_TASK_PRIO_MAX 10u
|
||||
|
||||
#define TOS_CFG_ROUND_ROBIN_EN 1u
|
||||
|
||||
#define TOS_CFG_OBJECT_VERIFY_EN 0u
|
||||
|
||||
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
|
||||
|
||||
#define TOS_CFG_EVENT_EN 1u
|
||||
|
||||
#define TOS_CFG_MMBLK_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x100
|
||||
|
||||
#define TOS_CFG_MUTEX_EN 1u
|
||||
|
||||
#define TOS_CFG_TIMER_EN 1u
|
||||
|
||||
#define TOS_CFG_SEM_EN 1u
|
||||
|
||||
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
|
||||
|
||||
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
|
||||
|
||||
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
|
||||
|
||||
#define TOS_CFG_TIMER_AS_PROC 1u
|
||||
|
||||
#endif /* _TOS_CONFIG_H_ */
|
||||
|
||||
Reference in New Issue
Block a user