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add support for Microchip SmartFusion2 family FPGA

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whik
2021-01-25 23:09:24 +08:00
parent 6e7e8e3d39
commit 9f76f7d35a
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30
platform/hal/Microchip/CortexM3/Keil/cpu_types.h Normal file
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef __CPU_TYPES_H
#define __CPU_TYPES_H 1
#include <stdint.h>
/*------------------------------------------------------------------------------
*/
typedef unsigned int size_t;
/*------------------------------------------------------------------------------
* addr_t: address type.
* Used to specify the address of peripherals present in the processor's memory
* map.
*/
typedef unsigned int addr_t;
/*------------------------------------------------------------------------------
* psr_t: processor state register.
* Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
* processor's state between disabling and restoring interrupts.
*/
typedef unsigned int psr_t;
#endif /* __CPU_TYPES_H */

32
platform/hal/Microchip/CortexM3/Keil/hal.s Normal file
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;-------------------------------------------------------------------------------
; (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
;
; Interrupt disabling/restoration for critical section protection.
;
; SVN $Revision: 5261 $
; SVN $Date: 2013-03-21 19:52:41 +0530 (Thu, 21 Mar 2013) $
;
AREA |.text|, CODE, READONLY
EXPORT HAL_disable_interrupts
EXPORT HAL_restore_interrupts
;-------------------------------------------------------------------------------
;
;
HAL_disable_interrupts \
PROC
mrs r0, PRIMASK
cpsid I
bx lr
ENDP
;-------------------------------------------------------------------------------
;
;
HAL_restore_interrupts \
PROC
msr PRIMASK, r0
bx lr
ENDP
END

96
platform/hal/Microchip/CortexM3/Keil/hw_macros.h Normal file
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Hardware registers access macros.
*
* THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW
* DEVELOPMENT.
*
* These macros are used to access peripheral's registers. They allow access to
* 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
* be done through these macros in order to ease porting accross different
* processors/bus architectures.
*
* Some of these macros also allow to access a specific register field.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef __HW_REGISTER_MACROS_H
#define __HW_REGISTER_MACROS_H 1
/*------------------------------------------------------------------------------
* 32 bits registers access:
*/
#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint32_t) \
( \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 32 bits memory access:
*/
#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
/*------------------------------------------------------------------------------
* 16 bits registers access:
*/
#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint16_t) \
( \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits registers access:
*/
#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint8_t) \
( \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits memory access:
*/
#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
#endif /* __HW_REGISTER_MACROS_H */

175
platform/hal/Microchip/CortexM3/Keil/hw_reg_access.s Normal file
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;******************************************************************************
; (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
;
; SVN $Revision: 5258 $
; SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
;
AREA |.text|, CODE, READONLY
EXPORT HW_set_32bit_reg
EXPORT HW_get_32bit_reg
EXPORT HW_set_32bit_reg_field
EXPORT HW_get_32bit_reg_field
EXPORT HW_set_16bit_reg
EXPORT HW_get_16bit_reg
EXPORT HW_set_16bit_reg_field
EXPORT HW_get_16bit_reg_field
EXPORT HW_set_8bit_reg
EXPORT HW_get_8bit_reg
EXPORT HW_set_8bit_reg_field
EXPORT HW_get_8bit_reg_field
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint32_t value
;
HW_set_32bit_reg \
PROC
STR R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_32bit_reg \
PROC
LDR R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint32_t mask
; R3: uint32_t value
;
HW_set_32bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDR R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STR R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint32_t mask
;
HW_get_32bit_reg_field \
PROC
LDR R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint_fast16_t value
;
HW_set_16bit_reg \
PROC
STRH R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_16bit_reg \
PROC
LDRH R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast16_t mask
; R3: uint_fast16_t value
;
HW_set_16bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDRH R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STRH R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast16_t mask
;
HW_get_16bit_reg_field \
PROC
LDRH R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint_fast8_t value
;
HW_set_8bit_reg \
PROC
STRB R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_8bit_reg \
PROC
LDRB R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr,
; R1: int_fast8_t shift
; R2: uint_fast8_t mask
; R3: uint_fast8_t value
;
HW_set_8bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDRB R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STRB R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast8_t mask
;
HW_get_8bit_reg_field \
PROC
LDRB R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
END

209
platform/hal/Microchip/CortexM3/cortex_nvic.c Normal file
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Legacy Actel HAL Cortex NVIC control functions.
* The use of these functions should be replaced by calls to the equivalent
* CMSIS function in your application code.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $
*/
#include "cortex_nvic.h"
#ifdef MSCC_NO_RELATIVE_PATHS
#include "mss_assert.h"
#else
#include "../../CMSIS/mss_assert.h"
#endif
/***************************************************************************//**
*
*/
void NVIC_init( void )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Simply remove the call to NVIC_init() from your application code.
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_set_handler
(
uint32_t interrupt_number,
hal_nvic_irq_handler_t handler
)
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please remove the call to NVIC_set_handler() from your application code
* and provide a function using one of the following function prototypes to
* handle interrupts from peripherals implemeted in the SmartFusion2 FPGA
* fabric:
* - void FabricIrq0_IRQHandler(void)
* - void FabricIrq1_IRQHandler(void)
* - void FabricIrq2_IRQHandler(void)
* - void FabricIrq3_IRQHandler(void)
* - void FabricIrq4_IRQHandler(void)
* - void FabricIrq5_IRQHandler(void)
* - void FabricIrq6_IRQHandler(void)
* - void FabricIrq7_IRQHandler(void)
* - void FabricIrq8_IRQHandler(void)
* - void FabricIrq9_IRQHandler(void)
* - void FabricIrq10_IRQHandler(void)
* - void FabricIrq11_IRQHandler(void)
* - void FabricIrq12_IRQHandler(void)
* - void FabricIrq13_IRQHandler(void)
* - void FabricIrq14_IRQHandler(void)
* - void FabricIrq15_IRQHandler(void)
* The function to implement depends on which MSS_INT_F2M[n] signal is used
* in your Libero design to connect the interrupt signal of the peripheral
* generating the interrupt.
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_set_priority
(
uint32_t interrupt_number,
uint8_t priority_level
)
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_set_priority() with a call to the CMSIS
* void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) function where
* IRQn is one of the following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_enable_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_enable_interrupt() with a call to the CMSIS
* void NVIC_EnableIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_disable_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_disable_interrupt() with a call to the CMSIS
* void NVIC_DisableIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_clear_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_clear_interrupt() with a call to the CMSIS
* void NVIC_ClearPendingIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}

56
platform/hal/Microchip/CortexM3/cortex_nvic.h Normal file
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Legacy Actel HAL Cortex NVIC control functions.
* The use of these functions should be replaced by calls to the equivalent
* CMSIS function in your application code.
*
* SVN $Revision: 5257 $
* SVN $Date: 2013-03-21 17:54:10 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef CORTEX_NVIC_H_
#define CORTEX_NVIC_H_
#include <stdint.h>
typedef void (*hal_nvic_irq_handler_t)(void);
/*------------------------------------------------------------------------------
*
*/
void NVIC_init( void );
/*------------------------------------------------------------------------------
*
*/
void NVIC_set_handler
(
uint32_t interrupt_number,
hal_nvic_irq_handler_t handler
);
/*------------------------------------------------------------------------------
*
*/
void NVIC_set_priority
(
uint32_t interrupt_number,
uint8_t priority_level
);
/*------------------------------------------------------------------------------
*
*/
void NVIC_enable_interrupt( uint32_t interrupt_number );
/*------------------------------------------------------------------------------
*
*/
void NVIC_disable_interrupt( uint32_t interrupt_number );
/*------------------------------------------------------------------------------
*
*/
void NVIC_clear_interrupt( uint32_t interrupt_number );
#endif /*CORTEX_NVIC_H_*/