add support for Microchip SmartFusion2 family FPGA
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whik
30
platform/hal/Microchip/CortexM3/Keil/cpu_types.h
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30
platform/hal/Microchip/CortexM3/Keil/cpu_types.h
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/*******************************************************************************
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* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
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*
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* SVN $Revision: 5258 $
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* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
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*/
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#ifndef __CPU_TYPES_H
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#define __CPU_TYPES_H 1
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#include <stdint.h>
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/*------------------------------------------------------------------------------
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*/
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typedef unsigned int size_t;
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/*------------------------------------------------------------------------------
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* addr_t: address type.
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* Used to specify the address of peripherals present in the processor's memory
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* map.
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*/
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typedef unsigned int addr_t;
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/*------------------------------------------------------------------------------
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* psr_t: processor state register.
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* Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
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* processor's state between disabling and restoring interrupts.
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*/
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typedef unsigned int psr_t;
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#endif /* __CPU_TYPES_H */
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32
platform/hal/Microchip/CortexM3/Keil/hal.s
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32
platform/hal/Microchip/CortexM3/Keil/hal.s
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;-------------------------------------------------------------------------------
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; (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
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;
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; Interrupt disabling/restoration for critical section protection.
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;
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; SVN $Revision: 5261 $
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; SVN $Date: 2013-03-21 19:52:41 +0530 (Thu, 21 Mar 2013) $
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;
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AREA |.text|, CODE, READONLY
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EXPORT HAL_disable_interrupts
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EXPORT HAL_restore_interrupts
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;-------------------------------------------------------------------------------
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;
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;
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HAL_disable_interrupts \
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PROC
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mrs r0, PRIMASK
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cpsid I
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bx lr
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ENDP
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;-------------------------------------------------------------------------------
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;
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;
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HAL_restore_interrupts \
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PROC
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msr PRIMASK, r0
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bx lr
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ENDP
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END
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96
platform/hal/Microchip/CortexM3/Keil/hw_macros.h
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96
platform/hal/Microchip/CortexM3/Keil/hw_macros.h
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@@ -0,0 +1,96 @@
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/*******************************************************************************
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* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
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*
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* Hardware registers access macros.
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*
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* THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW
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* DEVELOPMENT.
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*
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* These macros are used to access peripheral's registers. They allow access to
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* 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
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* be done through these macros in order to ease porting accross different
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* processors/bus architectures.
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*
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* Some of these macros also allow to access a specific register field.
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*
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* SVN $Revision: 5258 $
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* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
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*/
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#ifndef __HW_REGISTER_MACROS_H
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#define __HW_REGISTER_MACROS_H 1
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/*------------------------------------------------------------------------------
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* 32 bits registers access:
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*/
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#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint32_t) \
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( \
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(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 32 bits memory access:
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*/
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#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
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#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
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/*------------------------------------------------------------------------------
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* 16 bits registers access:
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*/
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#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint16_t) \
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( \
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(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 8 bits registers access:
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*/
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#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint8_t) \
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( \
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(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 8 bits memory access:
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*/
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#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
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#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
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#endif /* __HW_REGISTER_MACROS_H */
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175
platform/hal/Microchip/CortexM3/Keil/hw_reg_access.s
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175
platform/hal/Microchip/CortexM3/Keil/hw_reg_access.s
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@@ -0,0 +1,175 @@
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;******************************************************************************
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; (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
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;
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; SVN $Revision: 5258 $
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; SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
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;
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AREA |.text|, CODE, READONLY
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EXPORT HW_set_32bit_reg
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EXPORT HW_get_32bit_reg
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EXPORT HW_set_32bit_reg_field
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EXPORT HW_get_32bit_reg_field
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EXPORT HW_set_16bit_reg
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EXPORT HW_get_16bit_reg
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EXPORT HW_set_16bit_reg_field
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EXPORT HW_get_16bit_reg_field
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EXPORT HW_set_8bit_reg
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EXPORT HW_get_8bit_reg
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EXPORT HW_set_8bit_reg_field
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EXPORT HW_get_8bit_reg_field
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: uint32_t value
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;
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HW_set_32bit_reg \
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PROC
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STR R1, [R0]
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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;
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HW_get_32bit_reg \
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PROC
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LDR R0, [R0]
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: int_fast8_t shift
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; R2: uint32_t mask
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; R3: uint32_t value
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;
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HW_set_32bit_reg_field \
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PROC
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PUSH {R1,R2,R3,LR}
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LSL.W R3, R3, R1
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AND.W R3, R3, R2
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LDR R1, [R0]
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MVN.W R2, R2
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AND.W R1, R1, R2
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ORR.W R1, R1, R3
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STR R1, [R0]
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POP {R1,R2,R3,PC}
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: int_fast8_t shift
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; R2: uint32_t mask
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;
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HW_get_32bit_reg_field \
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PROC
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LDR R0, [R0]
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AND.W R0, R0, R2
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LSR.W R0, R0, R1
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: uint_fast16_t value
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;
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HW_set_16bit_reg \
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PROC
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STRH R1, [R0]
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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;
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HW_get_16bit_reg \
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PROC
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LDRH R0, [R0]
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: int_fast8_t shift
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; R2: uint_fast16_t mask
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; R3: uint_fast16_t value
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;
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HW_set_16bit_reg_field \
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PROC
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PUSH {R1,R2,R3,LR}
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LSL.W R3, R3, R1
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AND.W R3, R3, R2
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LDRH R1, [R0]
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MVN.W R2, R2
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AND.W R1, R1, R2
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ORR.W R1, R1, R3
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STRH R1, [R0]
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POP {R1,R2,R3,PC}
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: int_fast8_t shift
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; R2: uint_fast16_t mask
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;
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HW_get_16bit_reg_field \
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PROC
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LDRH R0, [R0]
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AND.W R0, R0, R2
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LSR.W R0, R0, R1
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: uint_fast8_t value
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;
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HW_set_8bit_reg \
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PROC
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STRB R1, [R0]
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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;
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HW_get_8bit_reg \
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PROC
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LDRB R0, [R0]
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BX LR
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr,
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; R1: int_fast8_t shift
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; R2: uint_fast8_t mask
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; R3: uint_fast8_t value
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;
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HW_set_8bit_reg_field \
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PROC
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PUSH {R1,R2,R3,LR}
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LSL.W R3, R3, R1
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AND.W R3, R3, R2
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LDRB R1, [R0]
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MVN.W R2, R2
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AND.W R1, R1, R2
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ORR.W R1, R1, R3
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STRB R1, [R0]
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POP {R1,R2,R3,PC}
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ENDP
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;------------------------------------------------------------------------------
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; R0: addr_t reg_addr
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; R1: int_fast8_t shift
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; R2: uint_fast8_t mask
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;
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HW_get_8bit_reg_field \
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PROC
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LDRB R0, [R0]
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AND.W R0, R0, R2
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LSR.W R0, R0, R1
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BX LR
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ENDP
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END
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