From 9fb07d7c2cd2aa61340a24a2316e7ce00e32ac77 Mon Sep 17 00:00:00 2001
From: mculover666 <2412828003@qq.com>
Date: Sat, 25 Dec 2021 14:18:16 +0800
Subject: [PATCH] add mqttclient_iot_explorer demo on tos_evb_aiot board
---
.../TOS-CONFIG/mqtt_config.h | 48 +
.../hello_world/KEIL/TencentOS-Tiny.uvoptx | 2 +-
.../hello_world/KEIL/TencentOS-Tiny.uvprojx | 7 +-
.../KEIL/MIMXRT1062xxxxx_flexspi_nor.scf | 111 +
.../KEIL/MIMXRT1062xxxxx_ram.scf | 77 +
.../KEIL/TencentOS-Tiny.uvoptx | 2306 ++++++++++++++++
.../KEIL/TencentOS-Tiny.uvprojx | 2449 +++++++++++++++++
.../KEIL/tosevbrt1062_flexspi_nor.ini | 89 +
.../KEIL/tosevbrt1062_ram.ini | 89 +
.../mqttclient_iot_explorer/board/board.c | 389 +++
.../mqttclient_iot_explorer/board/board.h | 220 ++
.../board/clock_config.c | 503 ++++
.../board/clock_config.h | 121 +
.../mqttclient_iot_explorer/board/dcd.c | 308 +++
.../mqttclient_iot_explorer/board/dcd.h | 25 +
.../mqttclient_iot_explorer/board/mcu_init.c | 54 +
.../mqttclient_iot_explorer/board/mcu_init.h | 20 +
.../mqttclient_iot_explorer/board/pin_mux.c | 69 +
.../mqttclient_iot_explorer/board/pin_mux.h | 87 +
.../xip/tosevbrt1062_flexspi_nor_config.c | 48 +
.../xip/tosevbrt1062_flexspi_nor_config.h | 268 ++
.../mqttclient_iot_explorer/main.c | 28 +
.../mqttclient_iot_explorer.c | 166 ++
.../KEIL/MIMXRT1062xxxxx_flexspi_nor.scf | 111 +
.../KEIL/MIMXRT1062xxxxx_ram.scf | 77 +
.../KEIL/TencentOS-Tiny.uvoptx | 1982 +++++++++++++
.../KEIL/TencentOS-Tiny.uvprojx | 2159 +++++++++++++++
.../KEIL/tosevbrt1062_flexspi_nor.ini | 89 +
.../KEIL/tosevbrt1062_ram.ini | 89 +
.../tcp_through_module/board/board.c | 389 +++
.../tcp_through_module/board/board.h | 220 ++
.../tcp_through_module/board/clock_config.c | 503 ++++
.../tcp_through_module/board/clock_config.h | 121 +
.../tcp_through_module/board/dcd.c | 308 +++
.../tcp_through_module/board/dcd.h | 25 +
.../tcp_through_module/board/mcu_init.c | 54 +
.../tcp_through_module/board/mcu_init.h | 20 +
.../tcp_through_module/board/pin_mux.c | 69 +
.../tcp_through_module/board/pin_mux.h | 87 +
.../xip/tosevbrt1062_flexspi_nor_config.c | 48 +
.../xip/tosevbrt1062_flexspi_nor_config.h | 268 ++
.../tcp_through_module/main.c | 28 +
devices/ec20_200_600/ec600s.c | 2 +
devices/esp8266/esp8266.c | 2 +
.../tcp_through_module/tcp_through_module.c | 42 +-
.../hal/nxp/mimxrt10xx/src/tos_hal_uart.c | 130 +
46 files changed, 14273 insertions(+), 34 deletions(-)
create mode 100644 board/TencentOS_tiny_EVB_AIoT/TOS-CONFIG/mqtt_config.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_ram.scf
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvoptx
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvprojx
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_flexspi_nor.ini
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_ram.ini
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/clock_config.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/clock_config.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/main.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/mqttclient_iot_explorer.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_ram.scf
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvoptx
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvprojx
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_flexspi_nor.ini
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_ram.ini
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/clock_config.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/clock_config.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.c
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.h
create mode 100644 board/TencentOS_tiny_EVB_AIoT/tcp_through_module/main.c
create mode 100644 platform/hal/nxp/mimxrt10xx/src/tos_hal_uart.c
diff --git a/board/TencentOS_tiny_EVB_AIoT/TOS-CONFIG/mqtt_config.h b/board/TencentOS_tiny_EVB_AIoT/TOS-CONFIG/mqtt_config.h
new file mode 100644
index 00000000..2e953d69
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/TOS-CONFIG/mqtt_config.h
@@ -0,0 +1,48 @@
+/*
+ * @Author: jiejie
+ * @Github: https://github.com/jiejieTop
+ * @LastEditTime: 2020-06-17 19:31:41
+ * @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
+ */
+#ifndef _MQTT_CONFIG_H_
+#define _MQTT_CONFIG_H_
+
+//#define MQTT_LOG_IS_SALOF
+
+#define MQTT_NETSOCKET_USING_AT
+
+#define MQTT_LOG_LEVEL MQTT_LOG_DEBUG_LEVEL //MQTT_LOG_WARN_LEVEL MQTT_LOG_DEBUG_LEVEL
+
+#ifdef MQTT_LOG_IS_SALOF
+ #define SALOF_USING_LOG (1U)
+ #define SALOF_USING_SALOF (1U)
+ #define SALOF_LOG_LEVEL MQTT_LOG_LEVEL
+ #define SALOF_OS SALOF_USING_TENCENTOS
+ #define SALOF_USING_IDLE_HOOK (0U)
+ #define SALOF_LOG_COLOR (1U)
+ #define SALOF_LOG_TS (0U)
+ #define SALOF_LOG_TAR (0U)
+ #define SALOF_BUFF_SIZE 512
+ #define SALOF_FIFO_SIZE 4096
+ #define SALOF_TASK_STACK_SIZE 1024
+ #define SALOF_TASK_TICK 50
+#endif
+
+#define MQTT_MAX_PACKET_ID (0xFFFF - 1)
+#define MQTT_TOPIC_LEN_MAX 64
+#define MQTT_ACK_HANDLER_NUM_MAX 64
+#define MQTT_DEFAULT_BUF_SIZE 1024
+#define MQTT_DEFAULT_CMD_TIMEOUT 5000
+#define MQTT_MAX_CMD_TIMEOUT 20000
+#define MQTT_MIN_CMD_TIMEOUT 1000
+#define MQTT_KEEP_ALIVE_INTERVAL 50 // unit: second
+#define MQTT_VERSION 4 // 4 is mqtt 3.1.1
+#define MQTT_RECONNECT_DEFAULT_DURATION 1000
+#define MQTT_THREAD_STACK_SIZE 2048
+#define MQTT_THREAD_PRIO 5
+#define MQTT_THREAD_TICK 50
+
+
+#define MQTT_NETWORK_TYPE_NO_TLS
+
+#endif /* _MQTT_CONFIG_H_ */
diff --git a/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvoptx b/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvoptx
index 4c907f8c..68f02b3c 100644
--- a/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvoptx
+++ b/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvoptx
@@ -10,7 +10,7 @@
*.s*; *.src; *.a*
*.obj
*.lib
- *.txt; *.h; *.inc
+ *.txt; *.h; *.inc; *.md
*.plm
*.cpp
0
diff --git a/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvprojx b/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvprojx
index 23c2dc24..694143c5 100644
--- a/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvprojx
+++ b/board/TencentOS_tiny_EVB_AIoT/hello_world/KEIL/TencentOS-Tiny.uvprojx
@@ -1031,7 +1031,7 @@
TencentOS-Tiny flexspi_nor_release
0x4
ARM-ADS
- 6140000::V6.14::ARMCLANG
+ 6160000::V6.16::ARMCLANG
1
@@ -2060,11 +2060,6 @@
<Project Info>
-
-
-
-
-
0
1
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf
new file mode 100644
index 00000000..70351918
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf
@@ -0,0 +1,111 @@
+#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
+/*
+** ###################################################################
+** Processors: MIMXRT1062CVJ5A
+** MIMXRT1062CVL5A
+** MIMXRT1062DVJ6A
+** MIMXRT1062DVL6A
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
+** Version: rev. 0.1, 2017-01-10
+** Build: b191015
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+#if (defined(__ram_vector_table__))
+ #define __ram_vector_table_size__ 0x00000400
+#else
+ #define __ram_vector_table_size__ 0x00000000
+#endif
+
+#define m_flash_config_start 0x60000000
+#define m_flash_config_size 0x00001000
+
+#define m_ivt_start 0x60001000
+#define m_ivt_size 0x00001000
+
+#define m_interrupts_start 0x60002000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x60002400
+#define m_text_size 0x007FDC00
+
+#define m_interrupts_ram_start 0x20000000
+#define m_interrupts_ram_size __ram_vector_table_size__
+
+#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size (0x00020000 - m_interrupts_ram_size)
+
+#define m_data2_start 0x20200000
+#define m_data2_size 0x000C0000
+
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
+ RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
+ * (.boot_hdr.conf, +FIRST)
+ }
+
+ RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
+ * (.boot_hdr.ivt, +FIRST)
+ * (.boot_hdr.boot_data)
+ * (.boot_hdr.dcd_data)
+ }
+#else
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+#endif
+ VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+#if (defined(__ram_vector_table__))
+ VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
+ }
+#else
+ VECTOR_RAM m_interrupts_start EMPTY 0 {
+ }
+#endif
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+ RW_m_ncache m_data2_start EMPTY 0 {
+ }
+ RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
+ }
+}
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_ram.scf b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_ram.scf
new file mode 100644
index 00000000..64effc60
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/MIMXRT1062xxxxx_ram.scf
@@ -0,0 +1,77 @@
+#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
+/*
+** ###################################################################
+** Processors: MIMXRT1062CVJ5A
+** MIMXRT1062CVL5A
+** MIMXRT1062DVJ6A
+** MIMXRT1062DVL6A
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
+** Version: rev. 0.1, 2017-01-10
+** Build: b191015
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_interrupts_start 0x00000000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x00000400
+#define m_text_size 0x0001FC00
+
+#define m_data_start 0x20000000
+#define m_data_size 0x00020000
+
+#define m_data2_start 0x20200000
+#define m_data2_size 0x000C0000
+
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+ VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+ VECTOR_RAM m_interrupts_start EMPTY 0 {
+ }
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+ RW_m_ncache m_data2_start EMPTY 0 {
+ }
+ RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
+ }
+}
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvoptx b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvoptx
new file mode 100644
index 00000000..e91bc57a
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvoptx
@@ -0,0 +1,2306 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc; *.md
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ TencentOS-Tiny_debug
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\output\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 0
+
+ 8
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+ .\tosevbrt1062_ram.ini
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ JL2CM3
+ -U-O14 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ CMSIS_AGDI
+ -X"" -O974 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MIMXRT106x_HYPER_256KB_SEC -FL04000000 -FS060000000 -FP0($$Device:MIMXRT1062DVL6A$Flash\MIMXRT106x_HYPER_256KB_SEC.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+ 1
+ 1
+ 0
+ 2
+ 10000000
+
+
+
+
+
+ TencentOS-Tiny flexspi_nor_release
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\output\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 8
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+ .\tosevbrt1062_flexspi_nor.ini
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ JL2CM3
+ -U-O14 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ CMSIS_AGDI
+ -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MIMXRT106x_HYPER_256KB_SEC -FL04000000 -FS060000000 -FP0($$Device:MIMXRT1062DVL6A$Flash\MIMXRT106x_HYPER_256KB_SEC.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+ 0
+ 1
+ 0
+ 2
+ 10000000
+
+
+
+
+
+ startup
+ 0
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 2
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\arm\startup_MIMXRT1062.s
+ startup_MIMXRT1062.s
+ 0
+ 0
+
+
+
+
+ source
+ 1
+ 0
+ 0
+ 0
+
+ 2
+ 2
+ 1
+ 0
+ 0
+ 0
+ ..\main.c
+ main.c
+ 0
+ 0
+
+
+
+
+ example
+ 1
+ 0
+ 0
+ 0
+
+ 3
+ 3
+ 1
+ 0
+ 0
+ 0
+ ..\mqttclient_iot_explorer.c
+ mqttclient_iot_explorer.c
+ 0
+ 0
+
+
+
+
+ board
+ 0
+ 0
+ 0
+ 0
+
+ 4
+ 4
+ 1
+ 0
+ 0
+ 0
+ ..\board\board.c
+ board.c
+ 0
+ 0
+
+
+ 4
+ 5
+ 1
+ 0
+ 0
+ 0
+ ..\board\clock_config.c
+ clock_config.c
+ 0
+ 0
+
+
+ 4
+ 6
+ 1
+ 0
+ 0
+ 0
+ ..\board\dcd.c
+ dcd.c
+ 0
+ 0
+
+
+ 4
+ 7
+ 1
+ 0
+ 0
+ 0
+ ..\board\pin_mux.c
+ pin_mux.c
+ 0
+ 0
+
+
+ 4
+ 8
+ 1
+ 0
+ 0
+ 0
+ ..\board\mcu_init.c
+ mcu_init.c
+ 0
+ 0
+
+
+
+
+ utilities
+ 0
+ 0
+ 0
+ 0
+
+ 5
+ 9
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_assert.c
+ fsl_assert.c
+ 0
+ 0
+
+
+ 5
+ 10
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_debug_console.c
+ fsl_debug_console.c
+ 0
+ 0
+
+
+
+
+ drivers
+ 0
+ 0
+ 0
+ 0
+
+ 6
+ 11
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc.c
+ fsl_adc.c
+ 0
+ 0
+
+
+ 6
+ 12
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc_etc.c
+ fsl_adc_etc.c
+ 0
+ 0
+
+
+ 6
+ 13
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aipstz.c
+ fsl_aipstz.c
+ 0
+ 0
+
+
+ 6
+ 14
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aoi.c
+ fsl_aoi.c
+ 0
+ 0
+
+
+ 6
+ 15
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_bee.c
+ fsl_bee.c
+ 0
+ 0
+
+
+ 6
+ 16
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cache.c
+ fsl_cache.c
+ 0
+ 0
+
+
+ 6
+ 17
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_clock.c
+ fsl_clock.c
+ 0
+ 0
+
+
+ 6
+ 18
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cmp.c
+ fsl_cmp.c
+ 0
+ 0
+
+
+ 6
+ 19
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_common.c
+ fsl_common.c
+ 0
+ 0
+
+
+ 6
+ 20
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_csi.c
+ fsl_csi.c
+ 0
+ 0
+
+
+ 6
+ 21
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcdc.c
+ fsl_dcdc.c
+ 0
+ 0
+
+
+ 6
+ 22
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcp.c
+ fsl_dcp.c
+ 0
+ 0
+
+
+ 6
+ 23
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dmamux.c
+ fsl_dmamux.c
+ 0
+ 0
+
+
+ 6
+ 24
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_edma.c
+ fsl_edma.c
+ 0
+ 0
+
+
+ 6
+ 25
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_elcdif.c
+ fsl_elcdif.c
+ 0
+ 0
+
+
+ 6
+ 26
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enc.c
+ fsl_enc.c
+ 0
+ 0
+
+
+ 6
+ 27
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enet.c
+ fsl_enet.c
+ 0
+ 0
+
+
+ 6
+ 28
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ewm.c
+ fsl_ewm.c
+ 0
+ 0
+
+
+ 6
+ 29
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan.c
+ fsl_flexcan.c
+ 0
+ 0
+
+
+ 6
+ 30
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan_edma.c
+ fsl_flexcan_edma.c
+ 0
+ 0
+
+
+ 6
+ 31
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio.c
+ fsl_flexio.c
+ 0
+ 0
+
+
+ 6
+ 32
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera.c
+ fsl_flexio_camera.c
+ 0
+ 0
+
+
+ 6
+ 33
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera_edma.c
+ fsl_flexio_camera_edma.c
+ 0
+ 0
+
+
+ 6
+ 34
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2c_master.c
+ fsl_flexio_i2c_master.c
+ 0
+ 0
+
+
+ 6
+ 35
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s.c
+ fsl_flexio_i2s.c
+ 0
+ 0
+
+
+ 6
+ 36
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s_edma.c
+ fsl_flexio_i2s_edma.c
+ 0
+ 0
+
+
+ 6
+ 37
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd.c
+ fsl_flexio_mculcd.c
+ 0
+ 0
+
+
+ 6
+ 38
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd_edma.c
+ fsl_flexio_mculcd_edma.c
+ 0
+ 0
+
+
+ 6
+ 39
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi.c
+ fsl_flexio_spi.c
+ 0
+ 0
+
+
+ 6
+ 40
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi_edma.c
+ fsl_flexio_spi_edma.c
+ 0
+ 0
+
+
+ 6
+ 41
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart.c
+ fsl_flexio_uart.c
+ 0
+ 0
+
+
+ 6
+ 42
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart_edma.c
+ fsl_flexio_uart_edma.c
+ 0
+ 0
+
+
+ 6
+ 43
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram.c
+ fsl_flexram.c
+ 0
+ 0
+
+
+ 6
+ 44
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram_allocate.c
+ fsl_flexram_allocate.c
+ 0
+ 0
+
+
+ 6
+ 45
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi.c
+ fsl_flexspi.c
+ 0
+ 0
+
+
+ 6
+ 46
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi_edma.c
+ fsl_flexspi_edma.c
+ 0
+ 0
+
+
+ 6
+ 47
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpc.c
+ fsl_gpc.c
+ 0
+ 0
+
+
+ 6
+ 48
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpio.c
+ fsl_gpio.c
+ 0
+ 0
+
+
+ 6
+ 49
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpt.c
+ fsl_gpt.c
+ 0
+ 0
+
+
+ 6
+ 50
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_kpp.c
+ fsl_kpp.c
+ 0
+ 0
+
+
+ 6
+ 51
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c.c
+ fsl_lpi2c.c
+ 0
+ 0
+
+
+ 6
+ 52
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c_edma.c
+ fsl_lpi2c_edma.c
+ 0
+ 0
+
+
+ 6
+ 53
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi.c
+ fsl_lpspi.c
+ 0
+ 0
+
+
+ 6
+ 54
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi_edma.c
+ fsl_lpspi_edma.c
+ 0
+ 0
+
+
+ 6
+ 55
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart.c
+ fsl_lpuart.c
+ 0
+ 0
+
+
+ 6
+ 56
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart_edma.c
+ fsl_lpuart_edma.c
+ 0
+ 0
+
+
+ 6
+ 57
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ocotp.c
+ fsl_ocotp.c
+ 0
+ 0
+
+
+ 6
+ 58
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pit.c
+ fsl_pit.c
+ 0
+ 0
+
+
+ 6
+ 59
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pmu.c
+ fsl_pmu.c
+ 0
+ 0
+
+
+ 6
+ 60
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pwm.c
+ fsl_pwm.c
+ 0
+ 0
+
+
+ 6
+ 61
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pxp.c
+ fsl_pxp.c
+ 0
+ 0
+
+
+ 6
+ 62
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_qtmr.c
+ fsl_qtmr.c
+ 0
+ 0
+
+
+ 6
+ 63
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_romapi.c
+ fsl_romapi.c
+ 0
+ 0
+
+
+ 6
+ 64
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_rtwdog.c
+ fsl_rtwdog.c
+ 0
+ 0
+
+
+ 6
+ 65
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai.c
+ fsl_sai.c
+ 0
+ 0
+
+
+ 6
+ 66
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai_edma.c
+ fsl_sai_edma.c
+ 0
+ 0
+
+
+ 6
+ 67
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_semc.c
+ fsl_semc.c
+ 0
+ 0
+
+
+ 6
+ 68
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_hp.c
+ fsl_snvs_hp.c
+ 0
+ 0
+
+
+ 6
+ 69
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_lp.c
+ fsl_snvs_lp.c
+ 0
+ 0
+
+
+ 6
+ 70
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif.c
+ fsl_spdif.c
+ 0
+ 0
+
+
+ 6
+ 71
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif_edma.c
+ fsl_spdif_edma.c
+ 0
+ 0
+
+
+ 6
+ 72
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_src.c
+ fsl_src.c
+ 0
+ 0
+
+
+ 6
+ 73
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tempmon.c
+ fsl_tempmon.c
+ 0
+ 0
+
+
+ 6
+ 74
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_trng.c
+ fsl_trng.c
+ 0
+ 0
+
+
+ 6
+ 75
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tsc.c
+ fsl_tsc.c
+ 0
+ 0
+
+
+ 6
+ 76
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_usdhc.c
+ fsl_usdhc.c
+ 0
+ 0
+
+
+ 6
+ 77
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_wdog.c
+ fsl_wdog.c
+ 0
+ 0
+
+
+ 6
+ 78
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbara.c
+ fsl_xbara.c
+ 0
+ 0
+
+
+ 6
+ 79
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbarb.c
+ fsl_xbarb.c
+ 0
+ 0
+
+
+
+
+ device
+ 0
+ 0
+ 0
+ 0
+
+ 7
+ 80
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\system_MIMXRT1062.c
+ system_MIMXRT1062.c
+ 0
+ 0
+
+
+
+
+ xip
+ 0
+ 0
+ 0
+ 0
+
+ 8
+ 81
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip\fsl_flexspi_nor_boot.c
+ fsl_flexspi_nor_boot.c
+ 0
+ 0
+
+
+ 8
+ 82
+ 1
+ 0
+ 0
+ 0
+ ..\board\xip\tosevbrt1062_flexspi_nor_config.c
+ tosevbrt1062_flexspi_nor_config.c
+ 0
+ 0
+
+
+
+
+ nxp/component/uart
+ 0
+ 0
+ 0
+ 0
+
+ 9
+ 83
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart\fsl_adapter_lpuart.c
+ fsl_adapter_lpuart.c
+ 0
+ 0
+
+
+
+
+ nxp/component/lists
+ 0
+ 0
+ 0
+ 0
+
+ 10
+ 84
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists\fsl_component_generic_list.c
+ fsl_component_generic_list.c
+ 0
+ 0
+
+
+
+
+ cpu
+ 0
+ 0
+ 0
+ 0
+
+ 11
+ 85
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+ tos_cpu.c
+ 0
+ 0
+
+
+ 11
+ 86
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c
+ port_c.c
+ 0
+ 0
+
+
+ 11
+ 87
+ 2
+ 0
+ 0
+ 0
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S
+ port_s.S
+ 0
+ 0
+
+
+
+
+ kernel
+ 0
+ 0
+ 0
+ 0
+
+ 12
+ 88
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_barrier.c
+ tos_barrier.c
+ 0
+ 0
+
+
+ 12
+ 89
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_binary_heap.c
+ tos_binary_heap.c
+ 0
+ 0
+
+
+ 12
+ 90
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_bitmap.c
+ tos_bitmap.c
+ 0
+ 0
+
+
+ 12
+ 91
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_char_fifo.c
+ tos_char_fifo.c
+ 0
+ 0
+
+
+ 12
+ 92
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_completion.c
+ tos_completion.c
+ 0
+ 0
+
+
+ 12
+ 93
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_countdownlatch.c
+ tos_countdownlatch.c
+ 0
+ 0
+
+
+ 12
+ 94
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_event.c
+ tos_event.c
+ 0
+ 0
+
+
+ 12
+ 95
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_global.c
+ tos_global.c
+ 0
+ 0
+
+
+ 12
+ 96
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mail_queue.c
+ tos_mail_queue.c
+ 0
+ 0
+
+
+ 12
+ 97
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_message_queue.c
+ tos_message_queue.c
+ 0
+ 0
+
+
+ 12
+ 98
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mmblk.c
+ tos_mmblk.c
+ 0
+ 0
+
+
+ 12
+ 99
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mmheap.c
+ tos_mmheap.c
+ 0
+ 0
+
+
+ 12
+ 100
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mutex.c
+ tos_mutex.c
+ 0
+ 0
+
+
+ 12
+ 101
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_pend.c
+ tos_pend.c
+ 0
+ 0
+
+
+ 12
+ 102
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_priority_mail_queue.c
+ tos_priority_mail_queue.c
+ 0
+ 0
+
+
+ 12
+ 103
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_priority_message_queue.c
+ tos_priority_message_queue.c
+ 0
+ 0
+
+
+ 12
+ 104
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_priority_queue.c
+ tos_priority_queue.c
+ 0
+ 0
+
+
+ 12
+ 105
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_ring_queue.c
+ tos_ring_queue.c
+ 0
+ 0
+
+
+ 12
+ 106
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_robin.c
+ tos_robin.c
+ 0
+ 0
+
+
+ 12
+ 107
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_rwlock.c
+ tos_rwlock.c
+ 0
+ 0
+
+
+ 12
+ 108
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_sched.c
+ tos_sched.c
+ 0
+ 0
+
+
+ 12
+ 109
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_sem.c
+ tos_sem.c
+ 0
+ 0
+
+
+ 12
+ 110
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_stopwatch.c
+ tos_stopwatch.c
+ 0
+ 0
+
+
+ 12
+ 111
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_sys.c
+ tos_sys.c
+ 0
+ 0
+
+
+ 12
+ 112
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_task.c
+ tos_task.c
+ 0
+ 0
+
+
+ 12
+ 113
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_tick.c
+ tos_tick.c
+ 0
+ 0
+
+
+ 12
+ 114
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_time.c
+ tos_time.c
+ 0
+ 0
+
+
+ 12
+ 115
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_timer.c
+ tos_timer.c
+ 0
+ 0
+
+
+
+
+ config
+ 0
+ 0
+ 0
+ 0
+
+ 13
+ 116
+ 5
+ 0
+ 0
+ 0
+ ..\..\TOS-CONFIG\tos_config.h
+ tos_config.h
+ 0
+ 0
+
+
+ 13
+ 117
+ 5
+ 0
+ 0
+ 0
+ ..\..\TOS-CONFIG\mqtt_config.h
+ mqtt_config.h
+ 0
+ 0
+
+
+
+
+ hal/uart
+ 0
+ 0
+ 0
+ 0
+
+ 14
+ 118
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\hal\nxp\mimxrt10xx\src\tos_hal_uart.c
+ tos_hal_uart.c
+ 0
+ 0
+
+
+
+
+ net/at
+ 0
+ 0
+ 0
+ 0
+
+ 15
+ 119
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\net\at\src\tos_at.c
+ tos_at.c
+ 0
+ 0
+
+
+
+
+ net/sal_module_wrapper
+ 0
+ 0
+ 0
+ 0
+
+ 16
+ 120
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c
+ sal_module_wrapper.c
+ 0
+ 0
+
+
+
+
+ devices
+ 0
+ 0
+ 0
+ 0
+
+ 17
+ 121
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\devices\esp8266\esp8266.c
+ esp8266.c
+ 0
+ 0
+
+
+ 17
+ 122
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\devices\ec20_200_600\ec600s.c
+ ec600s.c
+ 0
+ 0
+
+
+
+
+ mqttclient
+ 0
+ 0
+ 0
+ 0
+
+ 18
+ 123
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqttclient\mqttclient.c
+ mqttclient.c
+ 0
+ 0
+
+
+
+
+ mqttclient/mqtt
+ 0
+ 0
+ 0
+ 0
+
+ 19
+ 124
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectClient.c
+ MQTTConnectClient.c
+ 0
+ 0
+
+
+ 19
+ 125
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectServer.c
+ MQTTConnectServer.c
+ 0
+ 0
+
+
+ 19
+ 126
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTDeserializePublish.c
+ MQTTDeserializePublish.c
+ 0
+ 0
+
+
+ 19
+ 127
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTFormat.c
+ MQTTFormat.c
+ 0
+ 0
+
+
+ 19
+ 128
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTPacket.c
+ MQTTPacket.c
+ 0
+ 0
+
+
+ 19
+ 129
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSerializePublish.c
+ MQTTSerializePublish.c
+ 0
+ 0
+
+
+ 19
+ 130
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeClient.c
+ MQTTSubscribeClient.c
+ 0
+ 0
+
+
+ 19
+ 131
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeServer.c
+ MQTTSubscribeServer.c
+ 0
+ 0
+
+
+ 19
+ 132
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeClient.c
+ MQTTUnsubscribeClient.c
+ 0
+ 0
+
+
+ 19
+ 133
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeServer.c
+ MQTTUnsubscribeServer.c
+ 0
+ 0
+
+
+
+
+ mqttclient/common
+ 0
+ 0
+ 0
+ 0
+
+ 20
+ 134
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\common\random.c
+ random.c
+ 0
+ 0
+
+
+ 20
+ 135
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\common\mqtt_list.c
+ mqtt_list.c
+ 0
+ 0
+
+
+
+
+ mqttclient/network
+ 0
+ 0
+ 0
+ 0
+
+ 21
+ 136
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\network\nettype_tcp.c
+ nettype_tcp.c
+ 0
+ 0
+
+
+ 21
+ 137
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\network\nettype_tls.c
+ nettype_tls.c
+ 0
+ 0
+
+
+ 21
+ 138
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\network\network.c
+ network.c
+ 0
+ 0
+
+
+
+
+ mqttclient/platform
+ 0
+ 0
+ 0
+ 0
+
+ 22
+ 139
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_memory.c
+ platform_memory.c
+ 0
+ 0
+
+
+ 22
+ 140
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_mutex.c
+ platform_mutex.c
+ 0
+ 0
+
+
+ 22
+ 141
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_net_socket.c
+ platform_net_socket.c
+ 0
+ 0
+
+
+ 22
+ 142
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_thread.c
+ platform_thread.c
+ 0
+ 0
+
+
+ 22
+ 143
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_timer.c
+ platform_timer.c
+ 0
+ 0
+
+
+
+
+ cjson
+ 0
+ 0
+ 0
+ 0
+
+ 23
+ 144
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\components\utils\JSON\src\cJSON.c
+ cJSON.c
+ 0
+ 0
+
+
+
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvprojx b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvprojx
new file mode 100644
index 00000000..35f14c55
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/TencentOS-Tiny.uvprojx
@@ -0,0 +1,2449 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ TencentOS-Tiny_debug
+ 0x4
+ ARM-ADS
+ 6160000::V6.16::ARMCLANG
+ 1
+
+
+ MIMXRT1062DVL6A
+ NXP
+ NXP.MIMXRT1062_DFP.13.0.0
+ https://mcuxpresso.nxp.com/cmsis_pack/repo/
+ CPUTYPE("Cortex-M7") FPU3(DFPU)
+
+
+
+ 0
+ $$Device:MIMXRT1062DVL6A$Device\Include\fsl_device_registers.h
+
+
+
+
+
+
+
+
+
+ $$Device:MIMXRT1062DVL6A$SVD\MIMXRT1062.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\debug\
+ TencentOS-Tiny.out
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\output\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 1
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM7
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM7
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M7"
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 3
+ 4
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x20200000
+ 0x40000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20200000
+ 0x40000
+
+
+ 0
+ 0x80000000
+ 0x2000000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 0
+ 0x20000000
+ 0x20000
+
+
+
+
+
+ 0
+ 7
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 1
+ 1
+ 0
+ 0
+ 0
+
+ -fno-common -fdata-sections -ffreestanding -fno-builtin -mthumb
+ DEBUG, CPU_MIMXRT1062DVL6A, PRINTF_FLOAT_ENABLE=0, SCANF_FLOAT_ENABLE=0, PRINTF_ADVANCED_ENABLE=0, SCANF_ADVANCED_ENABLE=0,SDK_DEBUGCONSOLE_UART
+
+ ..;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\CMSIS\Include;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite;..\board;..\board\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc;..\..\..\..\kernel\core\include;..\..\TOS-CONFIG;..\..\..\..\kernel\hal\include;..\..\..\..\net\at\include;..\..\..\..\net\sal_module_wrapper;..\..\..\..\devices\esp8266;..\..\..\..\devices\ec20_200_600;..\..\..\..\components\utils\JSON\include;..\..\..\..\components\connectivity\mqttclient\common;..\..\..\..\components\connectivity\mqttclient\mqtt;..\..\..\..\components\connectivity\mqttclient\mqttclient;..\..\..\..\components\connectivity\mqttclient\network;..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ DEBUG, __STARTUP_INITIALIZE_NONCACHEDATA
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ MIMXRT1062xxxxx_ram.scf
+
+
+ --remove
+
+ 6314,6329
+
+
+
+
+
+ startup
+
+
+ startup_MIMXRT1062.s
+ 2
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\arm\startup_MIMXRT1062.s
+
+
+
+
+ source
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+
+
+ example
+
+
+ mqttclient_iot_explorer.c
+ 1
+ ..\mqttclient_iot_explorer.c
+
+
+
+
+ board
+
+
+ board.c
+ 1
+ ..\board\board.c
+
+
+ clock_config.c
+ 1
+ ..\board\clock_config.c
+
+
+ dcd.c
+ 1
+ ..\board\dcd.c
+
+
+ pin_mux.c
+ 1
+ ..\board\pin_mux.c
+
+
+ mcu_init.c
+ 1
+ ..\board\mcu_init.c
+
+
+
+
+ utilities
+
+
+ fsl_assert.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_assert.c
+
+
+ fsl_debug_console.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_debug_console.c
+
+
+
+
+ drivers
+
+
+ fsl_adc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc.c
+
+
+ fsl_adc_etc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc_etc.c
+
+
+ fsl_aipstz.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aipstz.c
+
+
+ fsl_aoi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aoi.c
+
+
+ fsl_bee.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_bee.c
+
+
+ fsl_cache.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cache.c
+
+
+ fsl_clock.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_clock.c
+
+
+ fsl_cmp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cmp.c
+
+
+ fsl_common.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_common.c
+
+
+ fsl_csi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_csi.c
+
+
+ fsl_dcdc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcdc.c
+
+
+ fsl_dcp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcp.c
+
+
+ fsl_dmamux.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dmamux.c
+
+
+ fsl_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_edma.c
+
+
+ fsl_elcdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_elcdif.c
+
+
+ fsl_enc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enc.c
+
+
+ fsl_enet.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enet.c
+
+
+ fsl_ewm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ewm.c
+
+
+ fsl_flexcan.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan.c
+
+
+ fsl_flexcan_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan_edma.c
+
+
+ fsl_flexio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio.c
+
+
+ fsl_flexio_camera.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera.c
+
+
+ fsl_flexio_camera_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera_edma.c
+
+
+ fsl_flexio_i2c_master.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2c_master.c
+
+
+ fsl_flexio_i2s.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s.c
+
+
+ fsl_flexio_i2s_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s_edma.c
+
+
+ fsl_flexio_mculcd.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd.c
+
+
+ fsl_flexio_mculcd_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd_edma.c
+
+
+ fsl_flexio_spi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi.c
+
+
+ fsl_flexio_spi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi_edma.c
+
+
+ fsl_flexio_uart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart.c
+
+
+ fsl_flexio_uart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart_edma.c
+
+
+ fsl_flexram.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram.c
+
+
+ fsl_flexram_allocate.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram_allocate.c
+
+
+ fsl_flexspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi.c
+
+
+ fsl_flexspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi_edma.c
+
+
+ fsl_gpc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpc.c
+
+
+ fsl_gpio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpio.c
+
+
+ fsl_gpt.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpt.c
+
+
+ fsl_kpp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_kpp.c
+
+
+ fsl_lpi2c.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c.c
+
+
+ fsl_lpi2c_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c_edma.c
+
+
+ fsl_lpspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi.c
+
+
+ fsl_lpspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi_edma.c
+
+
+ fsl_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart.c
+
+
+ fsl_lpuart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart_edma.c
+
+
+ fsl_ocotp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ocotp.c
+
+
+ fsl_pit.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pit.c
+
+
+ fsl_pmu.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pmu.c
+
+
+ fsl_pwm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pwm.c
+
+
+ fsl_pxp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pxp.c
+
+
+ fsl_qtmr.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_qtmr.c
+
+
+ fsl_romapi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_romapi.c
+
+
+ fsl_rtwdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_rtwdog.c
+
+
+ fsl_sai.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai.c
+
+
+ fsl_sai_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai_edma.c
+
+
+ fsl_semc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_semc.c
+
+
+ fsl_snvs_hp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_hp.c
+
+
+ fsl_snvs_lp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_lp.c
+
+
+ fsl_spdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif.c
+
+
+ fsl_spdif_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif_edma.c
+
+
+ fsl_src.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_src.c
+
+
+ fsl_tempmon.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tempmon.c
+
+
+ fsl_trng.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_trng.c
+
+
+ fsl_tsc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tsc.c
+
+
+ fsl_usdhc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_usdhc.c
+
+
+ fsl_wdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_wdog.c
+
+
+ fsl_xbara.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbara.c
+
+
+ fsl_xbarb.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbarb.c
+
+
+
+
+ device
+
+
+ system_MIMXRT1062.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\system_MIMXRT1062.c
+
+
+
+
+ xip
+
+
+ fsl_flexspi_nor_boot.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip\fsl_flexspi_nor_boot.c
+
+
+ tosevbrt1062_flexspi_nor_config.c
+ 1
+ ..\board\xip\tosevbrt1062_flexspi_nor_config.c
+
+
+
+
+ nxp/component/uart
+
+
+ fsl_adapter_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart\fsl_adapter_lpuart.c
+
+
+
+
+ nxp/component/lists
+
+
+ fsl_component_generic_list.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists\fsl_component_generic_list.c
+
+
+
+
+ cpu
+
+
+ tos_cpu.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+
+
+ port_c.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c
+
+
+ port_s.S
+ 2
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S
+
+
+
+
+ kernel
+
+
+ tos_barrier.c
+ 1
+ ..\..\..\..\kernel\core\tos_barrier.c
+
+
+ tos_binary_heap.c
+ 1
+ ..\..\..\..\kernel\core\tos_binary_heap.c
+
+
+ tos_bitmap.c
+ 1
+ ..\..\..\..\kernel\core\tos_bitmap.c
+
+
+ tos_char_fifo.c
+ 1
+ ..\..\..\..\kernel\core\tos_char_fifo.c
+
+
+ tos_completion.c
+ 1
+ ..\..\..\..\kernel\core\tos_completion.c
+
+
+ tos_countdownlatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_countdownlatch.c
+
+
+ tos_event.c
+ 1
+ ..\..\..\..\kernel\core\tos_event.c
+
+
+ tos_global.c
+ 1
+ ..\..\..\..\kernel\core\tos_global.c
+
+
+ tos_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_mail_queue.c
+
+
+ tos_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_message_queue.c
+
+
+ tos_mmblk.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmblk.c
+
+
+ tos_mmheap.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmheap.c
+
+
+ tos_mutex.c
+ 1
+ ..\..\..\..\kernel\core\tos_mutex.c
+
+
+ tos_pend.c
+ 1
+ ..\..\..\..\kernel\core\tos_pend.c
+
+
+ tos_priority_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_mail_queue.c
+
+
+ tos_priority_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_message_queue.c
+
+
+ tos_priority_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_queue.c
+
+
+ tos_ring_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_ring_queue.c
+
+
+ tos_robin.c
+ 1
+ ..\..\..\..\kernel\core\tos_robin.c
+
+
+ tos_rwlock.c
+ 1
+ ..\..\..\..\kernel\core\tos_rwlock.c
+
+
+ tos_sched.c
+ 1
+ ..\..\..\..\kernel\core\tos_sched.c
+
+
+ tos_sem.c
+ 1
+ ..\..\..\..\kernel\core\tos_sem.c
+
+
+ tos_stopwatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_stopwatch.c
+
+
+ tos_sys.c
+ 1
+ ..\..\..\..\kernel\core\tos_sys.c
+
+
+ tos_task.c
+ 1
+ ..\..\..\..\kernel\core\tos_task.c
+
+
+ tos_tick.c
+ 1
+ ..\..\..\..\kernel\core\tos_tick.c
+
+
+ tos_time.c
+ 1
+ ..\..\..\..\kernel\core\tos_time.c
+
+
+ tos_timer.c
+ 1
+ ..\..\..\..\kernel\core\tos_timer.c
+
+
+
+
+ config
+
+
+ tos_config.h
+ 5
+ ..\..\TOS-CONFIG\tos_config.h
+
+
+ mqtt_config.h
+ 5
+ ..\..\TOS-CONFIG\mqtt_config.h
+
+
+
+
+ hal/uart
+
+
+ tos_hal_uart.c
+ 1
+ ..\..\..\..\platform\hal\nxp\mimxrt10xx\src\tos_hal_uart.c
+
+
+
+
+ net/at
+
+
+ tos_at.c
+ 1
+ ..\..\..\..\net\at\src\tos_at.c
+
+
+
+
+ net/sal_module_wrapper
+
+
+ sal_module_wrapper.c
+ 1
+ ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c
+
+
+
+
+ devices
+
+
+ esp8266.c
+ 1
+ ..\..\..\..\devices\esp8266\esp8266.c
+
+
+ ec600s.c
+ 1
+ ..\..\..\..\devices\ec20_200_600\ec600s.c
+
+
+
+
+ mqttclient
+
+
+ mqttclient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqttclient\mqttclient.c
+
+
+
+
+ mqttclient/mqtt
+
+
+ MQTTConnectClient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectClient.c
+
+
+ MQTTConnectServer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectServer.c
+
+
+ MQTTDeserializePublish.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTDeserializePublish.c
+
+
+ MQTTFormat.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTFormat.c
+
+
+ MQTTPacket.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTPacket.c
+
+
+ MQTTSerializePublish.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSerializePublish.c
+
+
+ MQTTSubscribeClient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeClient.c
+
+
+ MQTTSubscribeServer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeServer.c
+
+
+ MQTTUnsubscribeClient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeClient.c
+
+
+ MQTTUnsubscribeServer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeServer.c
+
+
+
+
+ mqttclient/common
+
+
+ random.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\common\random.c
+
+
+ mqtt_list.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\common\mqtt_list.c
+
+
+
+
+ mqttclient/network
+
+
+ nettype_tcp.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\network\nettype_tcp.c
+
+
+ nettype_tls.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\network\nettype_tls.c
+
+
+ network.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\network\network.c
+
+
+
+
+ mqttclient/platform
+
+
+ platform_memory.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_memory.c
+
+
+ platform_mutex.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_mutex.c
+
+
+ platform_net_socket.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_net_socket.c
+
+
+ platform_thread.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_thread.c
+
+
+ platform_timer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_timer.c
+
+
+
+
+ cjson
+
+
+ cJSON.c
+ 1
+ ..\..\..\..\components\utils\JSON\src\cJSON.c
+
+
+
+
+
+
+ TencentOS-Tiny flexspi_nor_release
+ 0x4
+ ARM-ADS
+ 6160000::V6.16::ARMCLANG
+ 1
+
+
+ MIMXRT1062DVL6A
+ NXP
+ NXP.MIMXRT1062_DFP.13.0.0
+ https://mcuxpresso.nxp.com/cmsis_pack/repo/
+ CPUTYPE("Cortex-M7") FPU3(DFPU)
+
+
+
+ 0
+ $$Device:MIMXRT1062DVL6A$Device\Include\fsl_device_registers.h
+
+
+
+
+
+
+
+
+
+ $$Device:MIMXRT1062DVL6A$SVD\MIMXRT1062.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ flexspi_nor_release\
+ hello_world.out
+ 1
+ 0
+ 0
+ 0
+ 1
+ .\output\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 1
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM7
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM7
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M7"
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 3
+ 4
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x20200000
+ 0x40000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20200000
+ 0x40000
+
+
+ 0
+ 0x80000000
+ 0x2000000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 0
+ 0x20000000
+ 0x20000
+
+
+
+
+
+ 0
+ 7
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 1
+ 1
+ 0
+ 0
+ 0
+
+ -fno-common -fdata-sections -ffreestanding -fno-builtin -mthumb
+ XIP_EXTERNAL_FLASH=1, XIP_BOOT_HEADER_ENABLE=1, NDEBUG, CPU_MIMXRT1062DVL6A, PRINTF_FLOAT_ENABLE=0, SCANF_FLOAT_ENABLE=0, PRINTF_ADVANCED_ENABLE=0, SCANF_ADVANCED_ENABLE=0,SDK_DEBUGCONSOLE_UART
+
+ ..;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\CMSIS\Include;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite;..\board;..\board\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc;..\..\..\..\kernel\core\include;..\..\TOS-CONFIG;..\..\..\..\kernel\hal\include;..\..\..\..\net\at\include;..\..\..\..\net\sal_module_wrapper;..\..\..\..\devices\esp8266;..\..\..\..\devices\ec20_200_600;..\..\..\..\components\utils\JSON\include;..\..\..\..\components\connectivity\mqttclient\common;..\..\..\..\components\connectivity\mqttclient\mqtt;..\..\..\..\components\connectivity\mqttclient\mqttclient;..\..\..\..\components\connectivity\mqttclient\network;..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ NDEBUG, __STARTUP_INITIALIZE_NONCACHEDATA
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ MIMXRT1062xxxxx_flexspi_nor.scf
+
+
+ --remove --predefine="-DXIP_BOOT_HEADER_ENABLE=1"
+
+ 6314,6329
+
+
+
+
+
+ startup
+
+
+ startup_MIMXRT1062.s
+ 2
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\arm\startup_MIMXRT1062.s
+
+
+
+
+ source
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+
+
+ example
+
+
+ mqttclient_iot_explorer.c
+ 1
+ ..\mqttclient_iot_explorer.c
+
+
+
+
+ board
+
+
+ board.c
+ 1
+ ..\board\board.c
+
+
+ clock_config.c
+ 1
+ ..\board\clock_config.c
+
+
+ dcd.c
+ 1
+ ..\board\dcd.c
+
+
+ pin_mux.c
+ 1
+ ..\board\pin_mux.c
+
+
+ mcu_init.c
+ 1
+ ..\board\mcu_init.c
+
+
+
+
+ utilities
+
+
+ fsl_assert.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_assert.c
+
+
+ fsl_debug_console.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_debug_console.c
+
+
+
+
+ drivers
+
+
+ fsl_adc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc.c
+
+
+ fsl_adc_etc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc_etc.c
+
+
+ fsl_aipstz.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aipstz.c
+
+
+ fsl_aoi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aoi.c
+
+
+ fsl_bee.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_bee.c
+
+
+ fsl_cache.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cache.c
+
+
+ fsl_clock.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_clock.c
+
+
+ fsl_cmp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cmp.c
+
+
+ fsl_common.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_common.c
+
+
+ fsl_csi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_csi.c
+
+
+ fsl_dcdc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcdc.c
+
+
+ fsl_dcp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcp.c
+
+
+ fsl_dmamux.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dmamux.c
+
+
+ fsl_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_edma.c
+
+
+ fsl_elcdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_elcdif.c
+
+
+ fsl_enc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enc.c
+
+
+ fsl_enet.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enet.c
+
+
+ fsl_ewm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ewm.c
+
+
+ fsl_flexcan.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan.c
+
+
+ fsl_flexcan_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan_edma.c
+
+
+ fsl_flexio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio.c
+
+
+ fsl_flexio_camera.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera.c
+
+
+ fsl_flexio_camera_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera_edma.c
+
+
+ fsl_flexio_i2c_master.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2c_master.c
+
+
+ fsl_flexio_i2s.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s.c
+
+
+ fsl_flexio_i2s_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s_edma.c
+
+
+ fsl_flexio_mculcd.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd.c
+
+
+ fsl_flexio_mculcd_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd_edma.c
+
+
+ fsl_flexio_spi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi.c
+
+
+ fsl_flexio_spi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi_edma.c
+
+
+ fsl_flexio_uart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart.c
+
+
+ fsl_flexio_uart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart_edma.c
+
+
+ fsl_flexram.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram.c
+
+
+ fsl_flexram_allocate.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram_allocate.c
+
+
+ fsl_flexspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi.c
+
+
+ fsl_flexspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi_edma.c
+
+
+ fsl_gpc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpc.c
+
+
+ fsl_gpio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpio.c
+
+
+ fsl_gpt.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpt.c
+
+
+ fsl_kpp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_kpp.c
+
+
+ fsl_lpi2c.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c.c
+
+
+ fsl_lpi2c_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c_edma.c
+
+
+ fsl_lpspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi.c
+
+
+ fsl_lpspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi_edma.c
+
+
+ fsl_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart.c
+
+
+ fsl_lpuart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart_edma.c
+
+
+ fsl_ocotp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ocotp.c
+
+
+ fsl_pit.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pit.c
+
+
+ fsl_pmu.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pmu.c
+
+
+ fsl_pwm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pwm.c
+
+
+ fsl_pxp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pxp.c
+
+
+ fsl_qtmr.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_qtmr.c
+
+
+ fsl_romapi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_romapi.c
+
+
+ fsl_rtwdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_rtwdog.c
+
+
+ fsl_sai.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai.c
+
+
+ fsl_sai_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai_edma.c
+
+
+ fsl_semc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_semc.c
+
+
+ fsl_snvs_hp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_hp.c
+
+
+ fsl_snvs_lp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_lp.c
+
+
+ fsl_spdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif.c
+
+
+ fsl_spdif_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif_edma.c
+
+
+ fsl_src.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_src.c
+
+
+ fsl_tempmon.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tempmon.c
+
+
+ fsl_trng.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_trng.c
+
+
+ fsl_tsc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tsc.c
+
+
+ fsl_usdhc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_usdhc.c
+
+
+ fsl_wdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_wdog.c
+
+
+ fsl_xbara.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbara.c
+
+
+ fsl_xbarb.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbarb.c
+
+
+
+
+ device
+
+
+ system_MIMXRT1062.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\system_MIMXRT1062.c
+
+
+
+
+ xip
+
+
+ fsl_flexspi_nor_boot.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip\fsl_flexspi_nor_boot.c
+
+
+ tosevbrt1062_flexspi_nor_config.c
+ 1
+ ..\board\xip\tosevbrt1062_flexspi_nor_config.c
+
+
+
+
+ nxp/component/uart
+
+
+ fsl_adapter_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart\fsl_adapter_lpuart.c
+
+
+
+
+ nxp/component/lists
+
+
+ fsl_component_generic_list.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists\fsl_component_generic_list.c
+
+
+
+
+ cpu
+
+
+ tos_cpu.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+
+
+ port_c.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c
+
+
+ port_s.S
+ 2
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S
+
+
+
+
+ kernel
+
+
+ tos_barrier.c
+ 1
+ ..\..\..\..\kernel\core\tos_barrier.c
+
+
+ tos_binary_heap.c
+ 1
+ ..\..\..\..\kernel\core\tos_binary_heap.c
+
+
+ tos_bitmap.c
+ 1
+ ..\..\..\..\kernel\core\tos_bitmap.c
+
+
+ tos_char_fifo.c
+ 1
+ ..\..\..\..\kernel\core\tos_char_fifo.c
+
+
+ tos_completion.c
+ 1
+ ..\..\..\..\kernel\core\tos_completion.c
+
+
+ tos_countdownlatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_countdownlatch.c
+
+
+ tos_event.c
+ 1
+ ..\..\..\..\kernel\core\tos_event.c
+
+
+ tos_global.c
+ 1
+ ..\..\..\..\kernel\core\tos_global.c
+
+
+ tos_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_mail_queue.c
+
+
+ tos_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_message_queue.c
+
+
+ tos_mmblk.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmblk.c
+
+
+ tos_mmheap.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmheap.c
+
+
+ tos_mutex.c
+ 1
+ ..\..\..\..\kernel\core\tos_mutex.c
+
+
+ tos_pend.c
+ 1
+ ..\..\..\..\kernel\core\tos_pend.c
+
+
+ tos_priority_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_mail_queue.c
+
+
+ tos_priority_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_message_queue.c
+
+
+ tos_priority_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_queue.c
+
+
+ tos_ring_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_ring_queue.c
+
+
+ tos_robin.c
+ 1
+ ..\..\..\..\kernel\core\tos_robin.c
+
+
+ tos_rwlock.c
+ 1
+ ..\..\..\..\kernel\core\tos_rwlock.c
+
+
+ tos_sched.c
+ 1
+ ..\..\..\..\kernel\core\tos_sched.c
+
+
+ tos_sem.c
+ 1
+ ..\..\..\..\kernel\core\tos_sem.c
+
+
+ tos_stopwatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_stopwatch.c
+
+
+ tos_sys.c
+ 1
+ ..\..\..\..\kernel\core\tos_sys.c
+
+
+ tos_task.c
+ 1
+ ..\..\..\..\kernel\core\tos_task.c
+
+
+ tos_tick.c
+ 1
+ ..\..\..\..\kernel\core\tos_tick.c
+
+
+ tos_time.c
+ 1
+ ..\..\..\..\kernel\core\tos_time.c
+
+
+ tos_timer.c
+ 1
+ ..\..\..\..\kernel\core\tos_timer.c
+
+
+
+
+ config
+
+
+ tos_config.h
+ 5
+ ..\..\TOS-CONFIG\tos_config.h
+
+
+ mqtt_config.h
+ 5
+ ..\..\TOS-CONFIG\mqtt_config.h
+
+
+
+
+ hal/uart
+
+
+ tos_hal_uart.c
+ 1
+ ..\..\..\..\platform\hal\nxp\mimxrt10xx\src\tos_hal_uart.c
+
+
+
+
+ net/at
+
+
+ tos_at.c
+ 1
+ ..\..\..\..\net\at\src\tos_at.c
+
+
+
+
+ net/sal_module_wrapper
+
+
+ sal_module_wrapper.c
+ 1
+ ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c
+
+
+
+
+ devices
+
+
+ esp8266.c
+ 1
+ ..\..\..\..\devices\esp8266\esp8266.c
+
+
+ ec600s.c
+ 1
+ ..\..\..\..\devices\ec20_200_600\ec600s.c
+
+
+
+
+ mqttclient
+
+
+ mqttclient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqttclient\mqttclient.c
+
+
+
+
+ mqttclient/mqtt
+
+
+ MQTTConnectClient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectClient.c
+
+
+ MQTTConnectServer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectServer.c
+
+
+ MQTTDeserializePublish.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTDeserializePublish.c
+
+
+ MQTTFormat.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTFormat.c
+
+
+ MQTTPacket.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTPacket.c
+
+
+ MQTTSerializePublish.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSerializePublish.c
+
+
+ MQTTSubscribeClient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeClient.c
+
+
+ MQTTSubscribeServer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeServer.c
+
+
+ MQTTUnsubscribeClient.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeClient.c
+
+
+ MQTTUnsubscribeServer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeServer.c
+
+
+
+
+ mqttclient/common
+
+
+ random.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\common\random.c
+
+
+ mqtt_list.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\common\mqtt_list.c
+
+
+
+
+ mqttclient/network
+
+
+ nettype_tcp.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\network\nettype_tcp.c
+
+
+ nettype_tls.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\network\nettype_tls.c
+
+
+ network.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\network\network.c
+
+
+
+
+ mqttclient/platform
+
+
+ platform_memory.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_memory.c
+
+
+ platform_mutex.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_mutex.c
+
+
+ platform_net_socket.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_net_socket.c
+
+
+ platform_thread.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_thread.c
+
+
+ platform_timer.c
+ 1
+ ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_timer.c
+
+
+
+
+ cjson
+
+
+ cJSON.c
+ 1
+ ..\..\..\..\components\utils\JSON\src\cJSON.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ TencentOS-Tiny
+ 0
+ 1
+
+
+
+
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_flexspi_nor.ini b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_flexspi_nor.ini
new file mode 100644
index 00000000..4624147d
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_flexspi_nor.ini
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+FUNC void _loadDcdcTrim(void)
+{
+ unsigned int dcdc_trim_loaded;
+ unsigned long ocotp_base;
+ unsigned long ocotp_fuse_bank0_base;
+ unsigned long dcdc_base;
+ unsigned long reg;
+ unsigned long trim_value;
+ unsigned int index;
+
+ ocotp_base = 0x401F4000;
+ ocotp_fuse_bank0_base = ocotp_base + 0x400;
+ dcdc_base = 0x40080000;
+
+ dcdc_trim_loaded = 0;
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
+ if (reg & (1<<10))
+ {
+ // DCDC: REG0->VBG_TRM
+ trim_value = (reg & (0x1F << 11)) >> 11;
+ reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
+ _WDWORD(dcdc_base + 0x4, reg);
+ dcdc_trim_loaded = 1;
+ }
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
+ if (reg & (1<<30))
+ {
+ index = (reg & (3 << 28)) >> 28;
+ if (index < 4)
+ {
+ // DCDC: REG3->TRG
+ reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
+ _WDWORD(dcdc_base + 0xC, reg);
+ dcdc_trim_loaded = 1;
+ }
+ }
+
+ if (dcdc_trim_loaded)
+ {
+ // delay about 400us till dcdc is stable.
+ _Sleep_(1);
+ }
+}
+
+FUNC void restoreFlexRAM(void)
+{
+ unsigned int value;
+ unsigned int base;
+
+ base = 0x400AC000;
+
+ value = _RDWORD(base + 0x44);
+ value &= ~(0xFFFFFFFF);
+ value |= 0x55AFFA55;
+ _WDWORD(base + 0x44, value);
+
+ value = _RDWORD(base + 0x40);
+ value |= (1 << 2);
+ _WDWORD(base + 0x40, value);
+}
+
+FUNC void Setup (void) {
+ _loadDcdcTrim();
+ SP = _RDWORD(0x60002000); // Setup Stack Pointer
+ PC = _RDWORD(0x60002004); // Setup Program Counter
+ _WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
+}
+
+FUNC void OnResetExec (void) { // executes upon software RESET
+ restoreFlexRAM();
+ Setup(); // Setup for Running
+}
+
+restoreFlexRAM();
+
+LOAD %L INCREMENTAL // Download
+
+Setup(); // Setup for Running
+
+// g, main
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_ram.ini b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_ram.ini
new file mode 100644
index 00000000..7eccf483
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/KEIL/tosevbrt1062_ram.ini
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+FUNC void _loadDcdcTrim(void)
+{
+ unsigned int dcdc_trim_loaded;
+ unsigned long ocotp_base;
+ unsigned long ocotp_fuse_bank0_base;
+ unsigned long dcdc_base;
+ unsigned long reg;
+ unsigned long trim_value;
+ unsigned int index;
+
+ ocotp_base = 0x401F4000;
+ ocotp_fuse_bank0_base = ocotp_base + 0x400;
+ dcdc_base = 0x40080000;
+
+ dcdc_trim_loaded = 0;
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
+ if (reg & (1<<10))
+ {
+ // DCDC: REG0->VBG_TRM
+ trim_value = (reg & (0x1F << 11)) >> 11;
+ reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
+ _WDWORD(dcdc_base + 0x4, reg);
+ dcdc_trim_loaded = 1;
+ }
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
+ if (reg & (1<<30))
+ {
+ index = (reg & (3 << 28)) >> 28;
+ if (index < 4)
+ {
+ // DCDC: REG3->TRG
+ reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
+ _WDWORD(dcdc_base + 0xC, reg);
+ dcdc_trim_loaded = 1;
+ }
+ }
+
+ if (dcdc_trim_loaded)
+ {
+ // delay about 400us till dcdc is stable.
+ _Sleep_(1);
+ }
+}
+
+FUNC void restoreFlexRAM(void)
+{
+ unsigned int value;
+ unsigned int base;
+
+ base = 0x400AC000;
+
+ value = _RDWORD(base + 0x44);
+ value &= ~(0xFFFFFFFF);
+ value |= 0x55AFFA55;
+ _WDWORD(base + 0x44, value);
+
+ value = _RDWORD(base + 0x40);
+ value |= (1 << 2);
+ _WDWORD(base + 0x40, value);
+}
+
+FUNC void Setup (void) {
+ _loadDcdcTrim();
+ SP = _RDWORD(0x00000000); // Setup Stack Pointer
+ PC = _RDWORD(0x00000004); // Setup Program Counter
+ _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
+}
+
+FUNC void OnResetExec (void) { // executes upon software RESET
+ restoreFlexRAM();
+ Setup(); // Setup for Running
+}
+
+restoreFlexRAM();
+
+LOAD %L INCREMENTAL // Download
+
+Setup(); // Setup for Running
+
+// g, main
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.c b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.c
new file mode 100644
index 00000000..cd8708cb
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_lpi2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get debug console frequency. */
+uint32_t BOARD_DebugConsoleSrcFreq(void)
+{
+ uint32_t freq;
+
+ /* To make it simple, we assume default PLL and divider settings, and the only variable
+ from application is use PLL3 source or OSC source */
+ if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
+ {
+ freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+ else
+ {
+ freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+
+ return freq;
+}
+
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
+{
+ lpi2c_master_config_t lpi2cConfig = {0};
+
+ /*
+ * lpi2cConfig.debugEnable = false;
+ * lpi2cConfig.ignoreAck = false;
+ * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
+ * lpi2cConfig.baudRate_Hz = 100000U;
+ * lpi2cConfig.busIdleTimeout_ns = 0;
+ * lpi2cConfig.pinLowTimeout_ns = 0;
+ * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
+ * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
+ */
+ LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
+ LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_LPI2C_Send(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Write;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = txBuff;
+ xfer.dataSize = txBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Read;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = rxBuff;
+ xfer.dataSize = rxBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Write;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = txBuff;
+ xfer.dataSize = txBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ status_t status;
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Write;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = NULL;
+ xfer.dataSize = 0;
+
+ status = LPI2C_MasterTransferBlocking(base, &xfer);
+
+ if (kStatus_Success == status)
+ {
+ xfer.subaddressSize = 0;
+ xfer.direction = kLPI2C_Read;
+ xfer.data = rxBuff;
+ xfer.dataSize = rxBuffSize;
+
+ status = LPI2C_MasterTransferBlocking(base, &xfer);
+ }
+
+ return status;
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+ BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+ uint8_t data = (uint8_t)txBuff;
+
+ return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+ BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Camera_I2C_Init(void)
+{
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
+ BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Camera_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Camera_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
+ rxBuffSize);
+}
+
+status_t BOARD_Camera_I2C_SendSCCB(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Camera_I2C_ReceiveSCCB(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
+ rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/* MPU configuration. */
+void BOARD_ConfigMPU(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Image$$RW_m_ncache$$Base[];
+ /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
+ extern uint32_t Image$$RW_m_ncache_unused$$Base[];
+ extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
+ uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
+ uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
+ 0 :
+ ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
+#elif defined(__MCUXPRESSO)
+ extern uint32_t __base_NCACHE_REGION;
+ extern uint32_t __top_NCACHE_REGION;
+ uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
+ uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
+#elif defined(__ICCARM__) || defined(__GNUC__)
+ extern uint32_t __NCACHE_REGION_START[];
+ extern uint32_t __NCACHE_REGION_SIZE[];
+ uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
+ uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
+#endif
+ volatile uint32_t i = 0;
+
+ /* Disable I cache and D cache */
+ if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
+ {
+ SCB_DisableICache();
+ }
+ if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
+ {
+ SCB_DisableDCache();
+ }
+
+ /* Disable MPU */
+ ARM_MPU_Disable();
+
+ /* MPU configure:
+ * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
+ * SubRegionDisable, Size)
+ * API in mpu_armv7.h.
+ * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
+ * disabled.
+ * param AccessPermission Data access permissions, allows you to configure read/write access for User and
+ * Privileged mode.
+ * Use MACROS defined in mpu_armv7.h:
+ * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
+ * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
+ * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
+ * 0 x 0 0 Strongly Ordered shareable
+ * 0 x 0 1 Device shareable
+ * 0 0 1 0 Normal not shareable Outer and inner write
+ * through no write allocate
+ * 0 0 1 1 Normal not shareable Outer and inner write
+ * back no write allocate
+ * 0 1 1 0 Normal shareable Outer and inner write
+ * through no write allocate
+ * 0 1 1 1 Normal shareable Outer and inner write
+ * back no write allocate
+ * 1 0 0 0 Normal not shareable outer and inner
+ * noncache
+ * 1 1 0 0 Normal shareable outer and inner
+ * noncache
+ * 1 0 1 1 Normal not shareable outer and inner write
+ * back write/read acllocate
+ * 1 1 1 1 Normal shareable outer and inner write
+ * back write/read acllocate
+ * 2 x 0 0 Device not shareable
+ * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
+ * policy.
+ * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide
+ * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
+ * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
+ * mpu_armv7.h.
+ */
+
+ /*
+ * Add default region to deny access to whole address space to workaround speculative prefetch.
+ * Refer to Arm errata 1013783-B for more details.
+ *
+ */
+ /* Region 0 setting: Instruction access disabled, No data access permission. */
+ MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
+
+ /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+ /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
+ /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
+ MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
+#endif
+
+ /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+ /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+ /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+ /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
+
+ /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+ /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert(!(nonCacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
+ }
+
+ /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
+
+ /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
+
+ /* Enable MPU */
+ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+ /* Enable I cache and D cache */
+ SCB_EnableDCache();
+ SCB_EnableICache();
+}
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.h b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.h
new file mode 100644
index 00000000..af781e3d
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/board.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "MIMXRT1060-EVK"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
+#define BOARD_DEBUG_UART_INSTANCE 1U
+
+#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
+
+#define BOARD_UART_IRQ LPUART1_IRQn
+#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE (115200U)
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/*! @brief The USER_LED used for board */
+#define LOGIC_LED_ON (0U)
+#define LOGIC_LED_OFF (1U)
+#ifndef BOARD_USER_LED_GPIO
+#define BOARD_USER_LED_GPIO GPIO1
+#endif
+#ifndef BOARD_USER_LED_GPIO_PIN
+#define BOARD_USER_LED_GPIO_PIN (9U)
+#endif
+
+#define USER_LED_INIT(output) \
+ GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
+ BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
+#define USER_LED_ON() \
+ GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
+#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+ /* Disable Flexspi2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi2);
+ /* Set FLEXSPI2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+ /* Set Flexspi2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can3);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ CLOCK_DisableClock(kCLOCK_Can3S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+ /* Disable Usb1 PLL output for USBPHY1. */
+ CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+ {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+ /* DeInit Enet PLL. */
+ CLOCK_DeinitEnetPll();
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* Set Enet output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ /* Enable Enet output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+ /* Set Enet2 output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+ /* Enable Enet2 output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+ /* Enable Enet25M output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+ /* DeInit Usb2 PLL. */
+ CLOCK_DeinitUsb2Pll();
+ /* Bypass Usb2 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+ /* Enable Usb2 PLL output. */
+ CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+ /* Set ENET2 Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/clock_config.h b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/clock_config.h
new file mode 100644
index 00000000..663e6c6e
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/clock_config.h
@@ -0,0 +1,121 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.c b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.c
new file mode 100644
index 00000000..64a9db5b
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.c
@@ -0,0 +1,308 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#include "dcd.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.dcd_data"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.dcd_data"
+#endif
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: DCDx v3.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 10.0.0
+board: MIMXRT1060-EVK
+output_format: c_array
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
+const uint8_t dcd_data[] = {
+ /* HEADER */
+ /* Tag */
+ 0xD2,
+ /* Image Length */
+ 0x04, 0x10,
+ /* Version */
+ 0x41,
+
+ /* COMMANDS */
+
+ /* group: 'Imported Commands' */
+ /* #1.1-113, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x03, 0x8C, 0x04,
+ /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
+ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
+ /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
+ 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
+ /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
+ /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
+ /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
+ /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
+ /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
+ /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
+ /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
+ /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
+ /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
+ /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
+ /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
+ /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
+ /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
+ /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
+ /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
+ /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
+ /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
+ /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
+ /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
+ /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
+ /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
+ /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
+ /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
+ /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
+ /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
+ /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
+ /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
+ /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
+ /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
+ /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
+ /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
+ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
+ /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
+ 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
+ /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
+ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
+ /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
+ 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
+ /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
+ /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
+ /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
+ /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
+ /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
+ 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
+ /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
+ 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
+ /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
+ 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
+ /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
+ /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
+ 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
+ /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
+ 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
+ /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
+ 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
+ /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
+ 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
+ /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
+ 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
+ /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
+ 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
+ /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
+ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
+ /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
+ 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
+ /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
+ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
+ /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
+ 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
+ /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #3.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #5.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #7.1-3, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x1C, 0x04,
+ /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
+ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
+ /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
+ /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
+ 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
+ };
+/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
+
+#else
+const uint8_t dcd_data[] = {0x00};
+#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.h b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.h
new file mode 100644
index 00000000..3d8b7cd7
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/dcd.h
@@ -0,0 +1,25 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef __DCD__
+#define __DCD__
+
+#include
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*************************************
+ * DCD Data
+ *************************************/
+#define DCD_TAG_HEADER (0xD2)
+#define DCD_VERSION (0x41)
+#define DCD_TAG_HEADER_SHIFT (24)
+#define DCD_ARRAY_SIZE 1
+
+#endif /* __DCD__ */
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.c b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.c
new file mode 100644
index 00000000..8cb6bb70
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.c
@@ -0,0 +1,54 @@
+#include "mcu_init.h"
+#include "tos_at.h"
+
+void board_init(void)
+{
+ /* Init board hardware. */
+ BOARD_ConfigMPU();
+ BOARD_InitPins();
+ BOARD_InitBootClocks();
+
+ BOARD_InitDebugConsole();
+}
+
+void SysTick_Handler(void)
+{
+ if (tos_knl_is_running()) {
+ tos_knl_irq_enter();
+ tos_tick_handler();
+ tos_knl_irq_leave();
+ }
+}
+
+/* LPUART2_IRQn interrupt handler */
+void LPUART2_IRQHandler(void) {
+ uint8_t data;
+
+ tos_knl_irq_enter();
+
+ /* If new data arrived. */
+ if ((kLPUART_RxDataRegFullFlag)&LPUART_GetStatusFlags(LPUART2))
+ {
+ data = LPUART_ReadByte(LPUART2);
+ tos_at_uart_input_byte(data);
+ }
+
+ tos_knl_irq_leave();
+}
+
+/* LPUART4_IRQn interrupt handler */
+void LPUART4_IRQHandler(void) {
+ uint8_t data;
+
+ tos_knl_irq_enter();
+
+ /* If new data arrived. */
+ if ((kLPUART_RxDataRegFullFlag)&LPUART_GetStatusFlags(LPUART4))
+ {
+ data = LPUART_ReadByte(LPUART4);
+ tos_at_uart_input_byte(data);
+ }
+
+ tos_knl_irq_leave();
+}
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.h b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.h
new file mode 100644
index 00000000..9a2a04ba
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/mcu_init.h
@@ -0,0 +1,20 @@
+#ifndef __MCU_INIT_H
+#define __MCU_INIT_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "tos_k.h"
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_lpuart.h"
+
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ __MCU_INIT_H */
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.c b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.c
new file mode 100644
index 00000000..a901ef12
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.c
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v10.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 10.0.0
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+ pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+ pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ - {pin_num: M12, peripheral: LPUART2, signal: RX, pin_signal: GPIO_AD_B1_03}
+ - {pin_num: L11, peripheral: LPUART2, signal: TX, pin_signal: GPIO_AD_B1_02}
+ - {pin_num: M5, peripheral: LPUART4, signal: RX, pin_signal: GPIO_SD_B1_01}
+ - {pin_num: L5, peripheral: LPUART4, signal: TX, pin_signal: GPIO_SD_B1_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_LPUART4_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_LPUART4_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.h b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.h
new file mode 100644
index 00000000..08577cc1
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/pin_mux.h
@@ -0,0 +1,87 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type */
+typedef enum _pin_mux_direction
+{
+ kPIN_MUX_DirectionInput = 0U, /* Input direction */
+ kPIN_MUX_DirectionOutput = 1U, /* Output direction */
+ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
+
+/* GPIO_AD_B1_03 (coord M12), SPDIF_IN/J22[8] */
+/* Routed pin properties */
+#define BOARD_INITPINS_SPDIF_IN_PERIPHERAL LPUART2 /*!< Peripheral name */
+#define BOARD_INITPINS_SPDIF_IN_SIGNAL RX /*!< Signal name */
+
+/* GPIO_AD_B1_02 (coord L11), SPDIF_OUT/J22[7] */
+/* Routed pin properties */
+#define BOARD_INITPINS_SPDIF_OUT_PERIPHERAL LPUART2 /*!< Peripheral name */
+#define BOARD_INITPINS_SPDIF_OUT_SIGNAL TX /*!< Signal name */
+
+/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */
+/* Routed pin properties */
+#define BOARD_INITPINS_FlexSPI_D2_B_PERIPHERAL LPUART4 /*!< Peripheral name */
+#define BOARD_INITPINS_FlexSPI_D2_B_SIGNAL RX /*!< Signal name */
+
+/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */
+/* Routed pin properties */
+#define BOARD_INITPINS_FlexSPI_D3_B_PERIPHERAL LPUART4 /*!< Peripheral name */
+#define BOARD_INITPINS_FlexSPI_D3_B_SIGNAL TX /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.c b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.c
new file mode 100644
index 00000000..8e186ef2
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "tosevbrt1062_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+ .memConfig =
+ {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+ .sflashPadType = kSerialFlash_4Pads,
+ .serialClkFreq = kFlexSpiSerialClk_100MHz,
+ .sflashA1Size = 8u * 1024u * 1024u,
+ .lookupTable =
+ {
+ // Read LUTs
+ FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+ },
+ },
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .blockSize = 64u * 1024u,
+ .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.h b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.h
new file mode 100644
index 00000000..f416a822
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/board/xip/tosevbrt1062_flexspi_nor_config.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
+
+#include
+#include
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_100MHz = 6,
+ kFlexSpiSerialClk_120MHz = 7,
+ kFlexSpiSerialClk_133MHz = 8,
+ kFlexSpiSerialClk_166MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+ kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+ kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+ kFlexSPIReadSampleClk_LoopbackInternally = 0,
+ kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+ kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+ kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+ kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
+ kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
+ kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
+ kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
+ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
+ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+ kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+ kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
+ kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
+ kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
+ kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+ kSerialFlash_1Pad = 1,
+ kSerialFlash_2Pads = 2,
+ kSerialFlash_4Pads = 4,
+ kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+ uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+ uint8_t seqId; //!< Sequence Index, valid number: 0-15
+ uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+ kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
+ kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+ kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
+ kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
+ kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
+ kDeviceConfigCmdType_Reset, //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+ uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+ uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+ uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
+ uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+ uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
+ uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
+ uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+ //! Serial NAND, need to refer to datasheet
+ uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+ uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+ //! Generic configuration, etc.
+ uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+ //! DPI/QPI/OPI switch or reset command
+ flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+ //! sequence number, [31:16] Reserved
+ uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
+ uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+ uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+ flexspi_lut_seq_t
+ configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+ uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
+ uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+ uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
+ uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+ //! details
+ uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
+ uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+ uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+ //! Chapter for more details
+ uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+ //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+ uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
+ uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
+ uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
+ uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
+ uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
+ uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
+ uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+ uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+ uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
+ uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
+ uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
+ uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+ uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+ uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+ //! busy flag is 0 when flash device is busy
+ uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
+ flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+ uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/* */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
+#define NOR_CMD_INDEX_DUMMY 6 //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+ CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+ 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+ CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+ 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+ CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+ 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+ 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ * Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+ flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+ uint32_t pageSize; //!< Page size of Serial NOR
+ uint32_t sectorSize; //!< Sector size of Serial NOR
+ uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
+ uint8_t isUniformBlockSize; //!< Sector/Block size is the same
+ uint8_t reserved0[2]; //!< Reserved for future use
+ uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
+ uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
+ uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
+ uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
+ uint32_t blockSize; //!< Block size
+ uint32_t reserve2[11]; //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/main.c b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/main.c
new file mode 100644
index 00000000..a6d087a8
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/main.c
@@ -0,0 +1,28 @@
+#include "mcu_init.h"
+
+#define APPLICATION_TASK_STK_SIZE 4096
+k_task_t application_task;
+uint8_t application_task_stk[APPLICATION_TASK_STK_SIZE];
+
+extern void application_entry(void *arg);
+
+#pragma weak application_entry
+void application_entry(void *arg)
+{
+ while (1) {
+ printf("This is a demo task,please use your task entry!\r\n");
+ tos_task_delay(1000);
+ }
+}
+
+int main(void)
+{
+ board_init();
+ PRINTF("Welcome to TencentOS tiny(%s)\r\n", TOS_VERSION);
+ tos_knl_init(); // TencentOS Tiny kernel initialize
+ tos_task_create(&application_task, "application_task", application_entry, NULL, 4, application_task_stk, APPLICATION_TASK_STK_SIZE, 0);
+ tos_knl_start();
+
+ while (1);
+}
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/mqttclient_iot_explorer.c b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/mqttclient_iot_explorer.c
new file mode 100644
index 00000000..2fa37620
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/mqttclient_iot_explorer/mqttclient_iot_explorer.c
@@ -0,0 +1,166 @@
+#include "mcu_init.h"
+#include "tos_k.h"
+#include "mqttclient.h"
+#include "cjson.h"
+#include "sal_module_wrapper.h"
+
+#define USE_ESP8266
+//#define USE_EC600S
+
+#if defined(USE_ESP8266)
+#include "esp8266.h"
+
+#elif defined(USE_EC600S)
+#include "ec600s.h"
+#endif
+
+k_event_t report_result_event;
+k_event_flag_t report_success = 1<<0;
+k_event_flag_t report_fail = 1<<1;
+
+static void tos_topic_handler(void* client, message_data_t* msg)
+{
+ (void) client;
+ cJSON* cjson_root = NULL;
+ cJSON* cjson_status = NULL;
+ char* status = NULL;
+ k_event_flag_t event_flag = report_fail;
+
+ /* ´òÓ¡ÈÕÖ¾ */
+ MQTT_LOG_I("-----------------------------------------------------------------------------------");
+ MQTT_LOG_I("%s:%d %s()...\ntopic: %s, qos: %d. \nmessage:\n\t%s\n", __FILE__, __LINE__, __FUNCTION__,
+ msg->topic_name, msg->message->qos, (char*)msg->message->payload);
+ MQTT_LOG_I("-----------------------------------------------------------------------------------\n");
+
+ /* ʹÓÃcjson½âÎöÉϱ¨ÏìÓ¦Êý¾Ý */
+ cjson_root = cJSON_Parse((char*)msg->message->payload);
+ if (cjson_root == NULL) {
+ printf("report reply message parser fail\r\n");
+ event_flag = report_fail;
+ goto exit;
+ }
+
+ /* ÌáÈ¡status״̬ */
+ cjson_status = cJSON_GetObjectItem(cjson_root, "status");
+ status = cJSON_GetStringValue(cjson_status);
+ if (cjson_status == NULL || status == NULL) {
+ printf("report reply status parser fail\r\n");
+ event_flag = report_fail;
+ goto exit;
+ }
+
+ /* ÅжÏstatus״̬ */
+ if (strstr(status,"success")) {
+ event_flag = report_success;
+ }else {
+ event_flag = report_fail;
+ }
+
+exit:
+ cJSON_Delete(cjson_root);
+ cjson_root = NULL;
+ status = NULL;
+
+ tos_event_post(&report_result_event, event_flag);
+
+ return;
+}
+
+#define REPORT_DATA_TEMPLATE "{\"method\":\"report\",\"clientToken\":\"00000001\",\"params\":{\"brightness\":%d,\"name\":\"bedroom\"}}"
+
+char report_buf[200];
+
+void mqttclient_task(void)
+{
+ int error;
+
+ int lightness = 0;
+
+ mqtt_client_t *client = NULL;
+
+ mqtt_message_t msg;
+
+ k_event_flag_t match_flag;
+
+ char host_ip[20];
+
+ memset(&msg, 0, sizeof(msg));
+
+#ifdef USE_ESP8266
+ esp8266_sal_init(HAL_UART_PORT_2);
+ esp8266_join_ap("Mculover666", "mculover666");
+#endif
+
+
+#ifdef USE_EC600S
+ ec600s_sal_init(HAL_UART_PORT_4);
+#endif
+
+ mqtt_log_init();
+
+ client = mqtt_lease();
+
+ tos_event_create(&report_result_event, (k_event_flag_t)0u);
+
+ /* Domain Format: .iotcloud.tencentdevices.com */
+ tos_sal_module_parse_domain("FWR8PGACUS.iotcloud.tencentdevices.com",host_ip,sizeof(host_ip));
+
+ /*
+ These infomation is generated by mqtt_config_gen.py tool in "TencentOS-tiny\tools" directory.
+ */
+ mqtt_set_port(client, "1883");
+ mqtt_set_host(client, host_ip);
+ mqtt_set_client_id(client, "FWR8PGACUSdev001");
+ mqtt_set_user_name(client, "FWR8PGACUSdev001;21010406;12365;4294967295");
+ mqtt_set_password(client, "273f218b35f52900b8b85183d93c1fcc6b9c9444;hmacsha1");
+ mqtt_set_clean_session(client, 1);
+
+ error = mqtt_connect(client);
+
+ MQTT_LOG_D("mqtt connect error is %#0x", error);
+
+ error = mqtt_subscribe(client, "$thing/down/property/FWR8PGACUS/dev001", QOS0, tos_topic_handler);
+
+ MQTT_LOG_D("mqtt subscribe error is %#0x", error);
+
+ while (1) {
+ memset(&msg, 0, sizeof(msg));
+
+ snprintf(report_buf, sizeof(report_buf), REPORT_DATA_TEMPLATE, lightness++);
+
+ if (lightness > 100) {
+ lightness = 0;
+ }
+
+ msg.qos = QOS0;
+ msg.payload = (void *) report_buf;
+
+ error = mqtt_publish(client, "$thing/up/property/FWR8PGACUS/dev001", &msg);
+
+ MQTT_LOG_D("mqtt publish error is %#0x", error);
+
+ tos_event_pend(&report_result_event,
+ report_success|report_fail,
+ &match_flag,
+ TOS_TIME_FOREVER,
+ TOS_OPT_EVENT_PEND_ANY | TOS_OPT_EVENT_PEND_CLR);
+
+ if (match_flag == report_success) {
+ printf("report to Tencent IoT Explorer success\r\n");
+
+ }else if (match_flag == report_fail){
+ printf("report to Tencent IoT Explorer fail\r\n");
+ }
+
+ tos_task_delay(5000);
+ }
+}
+
+void application_entry(void *arg)
+{
+ mqttclient_task();
+ while (1) {
+ printf("This is a mqtt demo!\r\n");
+ tos_task_delay(1000);
+ }
+}
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf
new file mode 100644
index 00000000..70351918
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf
@@ -0,0 +1,111 @@
+#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
+/*
+** ###################################################################
+** Processors: MIMXRT1062CVJ5A
+** MIMXRT1062CVL5A
+** MIMXRT1062DVJ6A
+** MIMXRT1062DVL6A
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
+** Version: rev. 0.1, 2017-01-10
+** Build: b191015
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+#if (defined(__ram_vector_table__))
+ #define __ram_vector_table_size__ 0x00000400
+#else
+ #define __ram_vector_table_size__ 0x00000000
+#endif
+
+#define m_flash_config_start 0x60000000
+#define m_flash_config_size 0x00001000
+
+#define m_ivt_start 0x60001000
+#define m_ivt_size 0x00001000
+
+#define m_interrupts_start 0x60002000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x60002400
+#define m_text_size 0x007FDC00
+
+#define m_interrupts_ram_start 0x20000000
+#define m_interrupts_ram_size __ram_vector_table_size__
+
+#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size (0x00020000 - m_interrupts_ram_size)
+
+#define m_data2_start 0x20200000
+#define m_data2_size 0x000C0000
+
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
+ RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
+ * (.boot_hdr.conf, +FIRST)
+ }
+
+ RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
+ * (.boot_hdr.ivt, +FIRST)
+ * (.boot_hdr.boot_data)
+ * (.boot_hdr.dcd_data)
+ }
+#else
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+#endif
+ VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+#if (defined(__ram_vector_table__))
+ VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
+ }
+#else
+ VECTOR_RAM m_interrupts_start EMPTY 0 {
+ }
+#endif
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+ RW_m_ncache m_data2_start EMPTY 0 {
+ }
+ RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
+ }
+}
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_ram.scf b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_ram.scf
new file mode 100644
index 00000000..64effc60
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_ram.scf
@@ -0,0 +1,77 @@
+#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
+/*
+** ###################################################################
+** Processors: MIMXRT1062CVJ5A
+** MIMXRT1062CVL5A
+** MIMXRT1062DVJ6A
+** MIMXRT1062DVL6A
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
+** Version: rev. 0.1, 2017-01-10
+** Build: b191015
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_interrupts_start 0x00000000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x00000400
+#define m_text_size 0x0001FC00
+
+#define m_data_start 0x20000000
+#define m_data_size 0x00020000
+
+#define m_data2_start 0x20200000
+#define m_data2_size 0x000C0000
+
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+ VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+ VECTOR_RAM m_interrupts_start EMPTY 0 {
+ }
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+ RW_m_ncache m_data2_start EMPTY 0 {
+ }
+ RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
+ }
+}
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvoptx b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvoptx
new file mode 100644
index 00000000..42795842
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvoptx
@@ -0,0 +1,1982 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc; *.md
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ TencentOS-Tiny_debug
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\output\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 0
+
+ 8
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+ .\tosevbrt1062_ram.ini
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ JL2CM3
+ -U-O14 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ CMSIS_AGDI
+ -X"" -O974 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MIMXRT106x_HYPER_256KB_SEC -FL04000000 -FS060000000 -FP0($$Device:MIMXRT1062DVL6A$Flash\MIMXRT106x_HYPER_256KB_SEC.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+ 1
+ 1
+ 0
+ 2
+ 10000000
+
+
+
+
+
+ TencentOS-Tiny flexspi_nor_release
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\output\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 8
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+ .\tosevbrt1062_flexspi_nor.ini
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ JL2CM3
+ -U-O14 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ CMSIS_AGDI
+ -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MIMXRT106x_HYPER_256KB_SEC -FL04000000 -FS060000000 -FP0($$Device:MIMXRT1062DVL6A$Flash\MIMXRT106x_HYPER_256KB_SEC.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+ 0
+ 1
+ 0
+ 2
+ 10000000
+
+
+
+
+
+ startup
+ 0
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 2
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\arm\startup_MIMXRT1062.s
+ startup_MIMXRT1062.s
+ 0
+ 0
+
+
+
+
+ source
+ 1
+ 0
+ 0
+ 0
+
+ 2
+ 2
+ 1
+ 0
+ 0
+ 0
+ ..\main.c
+ main.c
+ 0
+ 0
+
+
+
+
+ example
+ 1
+ 0
+ 0
+ 0
+
+ 3
+ 3
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\examples\tcp_through_module\tcp_through_module.c
+ tcp_through_module.c
+ 0
+ 0
+
+
+
+
+ board
+ 0
+ 0
+ 0
+ 0
+
+ 4
+ 4
+ 1
+ 0
+ 0
+ 0
+ ..\board\board.c
+ board.c
+ 0
+ 0
+
+
+ 4
+ 5
+ 1
+ 0
+ 0
+ 0
+ ..\board\clock_config.c
+ clock_config.c
+ 0
+ 0
+
+
+ 4
+ 6
+ 1
+ 0
+ 0
+ 0
+ ..\board\dcd.c
+ dcd.c
+ 0
+ 0
+
+
+ 4
+ 7
+ 1
+ 0
+ 0
+ 0
+ ..\board\pin_mux.c
+ pin_mux.c
+ 0
+ 0
+
+
+ 4
+ 8
+ 1
+ 0
+ 0
+ 0
+ ..\board\mcu_init.c
+ mcu_init.c
+ 0
+ 0
+
+
+
+
+ utilities
+ 0
+ 0
+ 0
+ 0
+
+ 5
+ 9
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_assert.c
+ fsl_assert.c
+ 0
+ 0
+
+
+ 5
+ 10
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_debug_console.c
+ fsl_debug_console.c
+ 0
+ 0
+
+
+
+
+ drivers
+ 0
+ 0
+ 0
+ 0
+
+ 6
+ 11
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc.c
+ fsl_adc.c
+ 0
+ 0
+
+
+ 6
+ 12
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc_etc.c
+ fsl_adc_etc.c
+ 0
+ 0
+
+
+ 6
+ 13
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aipstz.c
+ fsl_aipstz.c
+ 0
+ 0
+
+
+ 6
+ 14
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aoi.c
+ fsl_aoi.c
+ 0
+ 0
+
+
+ 6
+ 15
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_bee.c
+ fsl_bee.c
+ 0
+ 0
+
+
+ 6
+ 16
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cache.c
+ fsl_cache.c
+ 0
+ 0
+
+
+ 6
+ 17
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_clock.c
+ fsl_clock.c
+ 0
+ 0
+
+
+ 6
+ 18
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cmp.c
+ fsl_cmp.c
+ 0
+ 0
+
+
+ 6
+ 19
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_common.c
+ fsl_common.c
+ 0
+ 0
+
+
+ 6
+ 20
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_csi.c
+ fsl_csi.c
+ 0
+ 0
+
+
+ 6
+ 21
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcdc.c
+ fsl_dcdc.c
+ 0
+ 0
+
+
+ 6
+ 22
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcp.c
+ fsl_dcp.c
+ 0
+ 0
+
+
+ 6
+ 23
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dmamux.c
+ fsl_dmamux.c
+ 0
+ 0
+
+
+ 6
+ 24
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_edma.c
+ fsl_edma.c
+ 0
+ 0
+
+
+ 6
+ 25
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_elcdif.c
+ fsl_elcdif.c
+ 0
+ 0
+
+
+ 6
+ 26
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enc.c
+ fsl_enc.c
+ 0
+ 0
+
+
+ 6
+ 27
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enet.c
+ fsl_enet.c
+ 0
+ 0
+
+
+ 6
+ 28
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ewm.c
+ fsl_ewm.c
+ 0
+ 0
+
+
+ 6
+ 29
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan.c
+ fsl_flexcan.c
+ 0
+ 0
+
+
+ 6
+ 30
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan_edma.c
+ fsl_flexcan_edma.c
+ 0
+ 0
+
+
+ 6
+ 31
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio.c
+ fsl_flexio.c
+ 0
+ 0
+
+
+ 6
+ 32
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera.c
+ fsl_flexio_camera.c
+ 0
+ 0
+
+
+ 6
+ 33
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera_edma.c
+ fsl_flexio_camera_edma.c
+ 0
+ 0
+
+
+ 6
+ 34
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2c_master.c
+ fsl_flexio_i2c_master.c
+ 0
+ 0
+
+
+ 6
+ 35
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s.c
+ fsl_flexio_i2s.c
+ 0
+ 0
+
+
+ 6
+ 36
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s_edma.c
+ fsl_flexio_i2s_edma.c
+ 0
+ 0
+
+
+ 6
+ 37
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd.c
+ fsl_flexio_mculcd.c
+ 0
+ 0
+
+
+ 6
+ 38
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd_edma.c
+ fsl_flexio_mculcd_edma.c
+ 0
+ 0
+
+
+ 6
+ 39
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi.c
+ fsl_flexio_spi.c
+ 0
+ 0
+
+
+ 6
+ 40
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi_edma.c
+ fsl_flexio_spi_edma.c
+ 0
+ 0
+
+
+ 6
+ 41
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart.c
+ fsl_flexio_uart.c
+ 0
+ 0
+
+
+ 6
+ 42
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart_edma.c
+ fsl_flexio_uart_edma.c
+ 0
+ 0
+
+
+ 6
+ 43
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram.c
+ fsl_flexram.c
+ 0
+ 0
+
+
+ 6
+ 44
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram_allocate.c
+ fsl_flexram_allocate.c
+ 0
+ 0
+
+
+ 6
+ 45
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi.c
+ fsl_flexspi.c
+ 0
+ 0
+
+
+ 6
+ 46
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi_edma.c
+ fsl_flexspi_edma.c
+ 0
+ 0
+
+
+ 6
+ 47
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpc.c
+ fsl_gpc.c
+ 0
+ 0
+
+
+ 6
+ 48
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpio.c
+ fsl_gpio.c
+ 0
+ 0
+
+
+ 6
+ 49
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpt.c
+ fsl_gpt.c
+ 0
+ 0
+
+
+ 6
+ 50
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_kpp.c
+ fsl_kpp.c
+ 0
+ 0
+
+
+ 6
+ 51
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c.c
+ fsl_lpi2c.c
+ 0
+ 0
+
+
+ 6
+ 52
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c_edma.c
+ fsl_lpi2c_edma.c
+ 0
+ 0
+
+
+ 6
+ 53
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi.c
+ fsl_lpspi.c
+ 0
+ 0
+
+
+ 6
+ 54
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi_edma.c
+ fsl_lpspi_edma.c
+ 0
+ 0
+
+
+ 6
+ 55
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart.c
+ fsl_lpuart.c
+ 0
+ 0
+
+
+ 6
+ 56
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart_edma.c
+ fsl_lpuart_edma.c
+ 0
+ 0
+
+
+ 6
+ 57
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ocotp.c
+ fsl_ocotp.c
+ 0
+ 0
+
+
+ 6
+ 58
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pit.c
+ fsl_pit.c
+ 0
+ 0
+
+
+ 6
+ 59
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pmu.c
+ fsl_pmu.c
+ 0
+ 0
+
+
+ 6
+ 60
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pwm.c
+ fsl_pwm.c
+ 0
+ 0
+
+
+ 6
+ 61
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pxp.c
+ fsl_pxp.c
+ 0
+ 0
+
+
+ 6
+ 62
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_qtmr.c
+ fsl_qtmr.c
+ 0
+ 0
+
+
+ 6
+ 63
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_romapi.c
+ fsl_romapi.c
+ 0
+ 0
+
+
+ 6
+ 64
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_rtwdog.c
+ fsl_rtwdog.c
+ 0
+ 0
+
+
+ 6
+ 65
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai.c
+ fsl_sai.c
+ 0
+ 0
+
+
+ 6
+ 66
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai_edma.c
+ fsl_sai_edma.c
+ 0
+ 0
+
+
+ 6
+ 67
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_semc.c
+ fsl_semc.c
+ 0
+ 0
+
+
+ 6
+ 68
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_hp.c
+ fsl_snvs_hp.c
+ 0
+ 0
+
+
+ 6
+ 69
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_lp.c
+ fsl_snvs_lp.c
+ 0
+ 0
+
+
+ 6
+ 70
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif.c
+ fsl_spdif.c
+ 0
+ 0
+
+
+ 6
+ 71
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif_edma.c
+ fsl_spdif_edma.c
+ 0
+ 0
+
+
+ 6
+ 72
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_src.c
+ fsl_src.c
+ 0
+ 0
+
+
+ 6
+ 73
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tempmon.c
+ fsl_tempmon.c
+ 0
+ 0
+
+
+ 6
+ 74
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_trng.c
+ fsl_trng.c
+ 0
+ 0
+
+
+ 6
+ 75
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tsc.c
+ fsl_tsc.c
+ 0
+ 0
+
+
+ 6
+ 76
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_usdhc.c
+ fsl_usdhc.c
+ 0
+ 0
+
+
+ 6
+ 77
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_wdog.c
+ fsl_wdog.c
+ 0
+ 0
+
+
+ 6
+ 78
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbara.c
+ fsl_xbara.c
+ 0
+ 0
+
+
+ 6
+ 79
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbarb.c
+ fsl_xbarb.c
+ 0
+ 0
+
+
+
+
+ device
+ 0
+ 0
+ 0
+ 0
+
+ 7
+ 80
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\system_MIMXRT1062.c
+ system_MIMXRT1062.c
+ 0
+ 0
+
+
+
+
+ xip
+ 0
+ 0
+ 0
+ 0
+
+ 8
+ 81
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip\fsl_flexspi_nor_boot.c
+ fsl_flexspi_nor_boot.c
+ 0
+ 0
+
+
+ 8
+ 82
+ 1
+ 0
+ 0
+ 0
+ ..\board\xip\tosevbrt1062_flexspi_nor_config.c
+ tosevbrt1062_flexspi_nor_config.c
+ 0
+ 0
+
+
+
+
+ nxp/component/uart
+ 0
+ 0
+ 0
+ 0
+
+ 9
+ 83
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart\fsl_adapter_lpuart.c
+ fsl_adapter_lpuart.c
+ 0
+ 0
+
+
+
+
+ nxp/component/lists
+ 0
+ 0
+ 0
+ 0
+
+ 10
+ 84
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists\fsl_component_generic_list.c
+ fsl_component_generic_list.c
+ 0
+ 0
+
+
+
+
+ cpu
+ 0
+ 0
+ 0
+ 0
+
+ 11
+ 85
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+ tos_cpu.c
+ 0
+ 0
+
+
+ 11
+ 86
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c
+ port_c.c
+ 0
+ 0
+
+
+ 11
+ 87
+ 2
+ 0
+ 0
+ 0
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S
+ port_s.S
+ 0
+ 0
+
+
+
+
+ kernel
+ 0
+ 0
+ 0
+ 0
+
+ 12
+ 88
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_barrier.c
+ tos_barrier.c
+ 0
+ 0
+
+
+ 12
+ 89
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_binary_heap.c
+ tos_binary_heap.c
+ 0
+ 0
+
+
+ 12
+ 90
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_bitmap.c
+ tos_bitmap.c
+ 0
+ 0
+
+
+ 12
+ 91
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_char_fifo.c
+ tos_char_fifo.c
+ 0
+ 0
+
+
+ 12
+ 92
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_completion.c
+ tos_completion.c
+ 0
+ 0
+
+
+ 12
+ 93
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_countdownlatch.c
+ tos_countdownlatch.c
+ 0
+ 0
+
+
+ 12
+ 94
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_event.c
+ tos_event.c
+ 0
+ 0
+
+
+ 12
+ 95
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_global.c
+ tos_global.c
+ 0
+ 0
+
+
+ 12
+ 96
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mail_queue.c
+ tos_mail_queue.c
+ 0
+ 0
+
+
+ 12
+ 97
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_message_queue.c
+ tos_message_queue.c
+ 0
+ 0
+
+
+ 12
+ 98
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mmblk.c
+ tos_mmblk.c
+ 0
+ 0
+
+
+ 12
+ 99
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mmheap.c
+ tos_mmheap.c
+ 0
+ 0
+
+
+ 12
+ 100
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_mutex.c
+ tos_mutex.c
+ 0
+ 0
+
+
+ 12
+ 101
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_pend.c
+ tos_pend.c
+ 0
+ 0
+
+
+ 12
+ 102
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_priority_mail_queue.c
+ tos_priority_mail_queue.c
+ 0
+ 0
+
+
+ 12
+ 103
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_priority_message_queue.c
+ tos_priority_message_queue.c
+ 0
+ 0
+
+
+ 12
+ 104
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_priority_queue.c
+ tos_priority_queue.c
+ 0
+ 0
+
+
+ 12
+ 105
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_ring_queue.c
+ tos_ring_queue.c
+ 0
+ 0
+
+
+ 12
+ 106
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_robin.c
+ tos_robin.c
+ 0
+ 0
+
+
+ 12
+ 107
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_rwlock.c
+ tos_rwlock.c
+ 0
+ 0
+
+
+ 12
+ 108
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_sched.c
+ tos_sched.c
+ 0
+ 0
+
+
+ 12
+ 109
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_sem.c
+ tos_sem.c
+ 0
+ 0
+
+
+ 12
+ 110
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_stopwatch.c
+ tos_stopwatch.c
+ 0
+ 0
+
+
+ 12
+ 111
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_sys.c
+ tos_sys.c
+ 0
+ 0
+
+
+ 12
+ 112
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_task.c
+ tos_task.c
+ 0
+ 0
+
+
+ 12
+ 113
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_tick.c
+ tos_tick.c
+ 0
+ 0
+
+
+ 12
+ 114
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_time.c
+ tos_time.c
+ 0
+ 0
+
+
+ 12
+ 115
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\kernel\core\tos_timer.c
+ tos_timer.c
+ 0
+ 0
+
+
+
+
+ config
+ 1
+ 0
+ 0
+ 0
+
+ 13
+ 116
+ 5
+ 0
+ 0
+ 0
+ ..\..\TOS-CONFIG\tos_config.h
+ tos_config.h
+ 0
+ 0
+
+
+
+
+ hal/uart
+ 1
+ 0
+ 0
+ 0
+
+ 14
+ 117
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\platform\hal\nxp\mimxrt10xx\src\tos_hal_uart.c
+ tos_hal_uart.c
+ 0
+ 0
+
+
+
+
+ net/at
+ 1
+ 0
+ 0
+ 0
+
+ 15
+ 118
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\net\at\src\tos_at.c
+ tos_at.c
+ 0
+ 0
+
+
+
+
+ net/sal_module_wrapper
+ 1
+ 0
+ 0
+ 0
+
+ 16
+ 119
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c
+ sal_module_wrapper.c
+ 0
+ 0
+
+
+
+
+ devices
+ 1
+ 0
+ 0
+ 0
+
+ 17
+ 120
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\devices\esp8266\esp8266.c
+ esp8266.c
+ 0
+ 0
+
+
+ 17
+ 121
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\..\devices\ec20_200_600\ec600s.c
+ ec600s.c
+ 0
+ 0
+
+
+
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvprojx b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvprojx
new file mode 100644
index 00000000..ed0c472c
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvprojx
@@ -0,0 +1,2159 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ TencentOS-Tiny_debug
+ 0x4
+ ARM-ADS
+ 6160000::V6.16::ARMCLANG
+ 1
+
+
+ MIMXRT1062DVL6A
+ NXP
+ NXP.MIMXRT1062_DFP.13.0.0
+ https://mcuxpresso.nxp.com/cmsis_pack/repo/
+ CPUTYPE("Cortex-M7") FPU3(DFPU)
+
+
+
+ 0
+ $$Device:MIMXRT1062DVL6A$Device\Include\fsl_device_registers.h
+
+
+
+
+
+
+
+
+
+ $$Device:MIMXRT1062DVL6A$SVD\MIMXRT1062.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\debug\
+ TencentOS-Tiny.out
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\output\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 1
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM7
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM7
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M7"
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 3
+ 4
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x20200000
+ 0x40000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20200000
+ 0x40000
+
+
+ 0
+ 0x80000000
+ 0x2000000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 0
+ 0x20000000
+ 0x20000
+
+
+
+
+
+ 0
+ 7
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 1
+ 1
+ 0
+ 0
+ 0
+
+ -fno-common -fdata-sections -ffreestanding -fno-builtin -mthumb
+ DEBUG, CPU_MIMXRT1062DVL6A, PRINTF_FLOAT_ENABLE=0, SCANF_FLOAT_ENABLE=0, PRINTF_ADVANCED_ENABLE=0, SCANF_ADVANCED_ENABLE=0,SDK_DEBUGCONSOLE_UART
+
+ ..;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\CMSIS\Include;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite;..\board;..\board\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc;..\..\..\..\kernel\core\include;..\..\TOS-CONFIG;..\..\..\..\kernel\hal\include;..\..\..\..\..\..\..\TencentOS-tiny\net\at\include;..\..\..\..\net\sal_module_wrapper;..\..\..\..\devices\esp8266;..\..\..\..\devices\ec20_200_600
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ DEBUG, __STARTUP_INITIALIZE_NONCACHEDATA
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ MIMXRT1062xxxxx_ram.scf
+
+
+ --remove
+
+ 6314,6329
+
+
+
+
+
+ startup
+
+
+ startup_MIMXRT1062.s
+ 2
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\arm\startup_MIMXRT1062.s
+
+
+
+
+ source
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+
+
+ example
+
+
+ tcp_through_module.c
+ 1
+ ..\..\..\..\examples\tcp_through_module\tcp_through_module.c
+
+
+
+
+ board
+
+
+ board.c
+ 1
+ ..\board\board.c
+
+
+ clock_config.c
+ 1
+ ..\board\clock_config.c
+
+
+ dcd.c
+ 1
+ ..\board\dcd.c
+
+
+ pin_mux.c
+ 1
+ ..\board\pin_mux.c
+
+
+ mcu_init.c
+ 1
+ ..\board\mcu_init.c
+
+
+
+
+ utilities
+
+
+ fsl_assert.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_assert.c
+
+
+ fsl_debug_console.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_debug_console.c
+
+
+
+
+ drivers
+
+
+ fsl_adc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc.c
+
+
+ fsl_adc_etc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc_etc.c
+
+
+ fsl_aipstz.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aipstz.c
+
+
+ fsl_aoi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aoi.c
+
+
+ fsl_bee.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_bee.c
+
+
+ fsl_cache.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cache.c
+
+
+ fsl_clock.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_clock.c
+
+
+ fsl_cmp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cmp.c
+
+
+ fsl_common.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_common.c
+
+
+ fsl_csi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_csi.c
+
+
+ fsl_dcdc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcdc.c
+
+
+ fsl_dcp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcp.c
+
+
+ fsl_dmamux.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dmamux.c
+
+
+ fsl_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_edma.c
+
+
+ fsl_elcdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_elcdif.c
+
+
+ fsl_enc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enc.c
+
+
+ fsl_enet.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enet.c
+
+
+ fsl_ewm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ewm.c
+
+
+ fsl_flexcan.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan.c
+
+
+ fsl_flexcan_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan_edma.c
+
+
+ fsl_flexio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio.c
+
+
+ fsl_flexio_camera.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera.c
+
+
+ fsl_flexio_camera_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera_edma.c
+
+
+ fsl_flexio_i2c_master.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2c_master.c
+
+
+ fsl_flexio_i2s.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s.c
+
+
+ fsl_flexio_i2s_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s_edma.c
+
+
+ fsl_flexio_mculcd.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd.c
+
+
+ fsl_flexio_mculcd_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd_edma.c
+
+
+ fsl_flexio_spi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi.c
+
+
+ fsl_flexio_spi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi_edma.c
+
+
+ fsl_flexio_uart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart.c
+
+
+ fsl_flexio_uart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart_edma.c
+
+
+ fsl_flexram.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram.c
+
+
+ fsl_flexram_allocate.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram_allocate.c
+
+
+ fsl_flexspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi.c
+
+
+ fsl_flexspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi_edma.c
+
+
+ fsl_gpc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpc.c
+
+
+ fsl_gpio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpio.c
+
+
+ fsl_gpt.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpt.c
+
+
+ fsl_kpp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_kpp.c
+
+
+ fsl_lpi2c.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c.c
+
+
+ fsl_lpi2c_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c_edma.c
+
+
+ fsl_lpspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi.c
+
+
+ fsl_lpspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi_edma.c
+
+
+ fsl_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart.c
+
+
+ fsl_lpuart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart_edma.c
+
+
+ fsl_ocotp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ocotp.c
+
+
+ fsl_pit.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pit.c
+
+
+ fsl_pmu.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pmu.c
+
+
+ fsl_pwm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pwm.c
+
+
+ fsl_pxp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pxp.c
+
+
+ fsl_qtmr.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_qtmr.c
+
+
+ fsl_romapi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_romapi.c
+
+
+ fsl_rtwdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_rtwdog.c
+
+
+ fsl_sai.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai.c
+
+
+ fsl_sai_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai_edma.c
+
+
+ fsl_semc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_semc.c
+
+
+ fsl_snvs_hp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_hp.c
+
+
+ fsl_snvs_lp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_lp.c
+
+
+ fsl_spdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif.c
+
+
+ fsl_spdif_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif_edma.c
+
+
+ fsl_src.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_src.c
+
+
+ fsl_tempmon.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tempmon.c
+
+
+ fsl_trng.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_trng.c
+
+
+ fsl_tsc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tsc.c
+
+
+ fsl_usdhc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_usdhc.c
+
+
+ fsl_wdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_wdog.c
+
+
+ fsl_xbara.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbara.c
+
+
+ fsl_xbarb.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbarb.c
+
+
+
+
+ device
+
+
+ system_MIMXRT1062.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\system_MIMXRT1062.c
+
+
+
+
+ xip
+
+
+ fsl_flexspi_nor_boot.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip\fsl_flexspi_nor_boot.c
+
+
+ tosevbrt1062_flexspi_nor_config.c
+ 1
+ ..\board\xip\tosevbrt1062_flexspi_nor_config.c
+
+
+
+
+ nxp/component/uart
+
+
+ fsl_adapter_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart\fsl_adapter_lpuart.c
+
+
+
+
+ nxp/component/lists
+
+
+ fsl_component_generic_list.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists\fsl_component_generic_list.c
+
+
+
+
+ cpu
+
+
+ tos_cpu.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+
+
+ port_c.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c
+
+
+ port_s.S
+ 2
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S
+
+
+
+
+ kernel
+
+
+ tos_barrier.c
+ 1
+ ..\..\..\..\kernel\core\tos_barrier.c
+
+
+ tos_binary_heap.c
+ 1
+ ..\..\..\..\kernel\core\tos_binary_heap.c
+
+
+ tos_bitmap.c
+ 1
+ ..\..\..\..\kernel\core\tos_bitmap.c
+
+
+ tos_char_fifo.c
+ 1
+ ..\..\..\..\kernel\core\tos_char_fifo.c
+
+
+ tos_completion.c
+ 1
+ ..\..\..\..\kernel\core\tos_completion.c
+
+
+ tos_countdownlatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_countdownlatch.c
+
+
+ tos_event.c
+ 1
+ ..\..\..\..\kernel\core\tos_event.c
+
+
+ tos_global.c
+ 1
+ ..\..\..\..\kernel\core\tos_global.c
+
+
+ tos_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_mail_queue.c
+
+
+ tos_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_message_queue.c
+
+
+ tos_mmblk.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmblk.c
+
+
+ tos_mmheap.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmheap.c
+
+
+ tos_mutex.c
+ 1
+ ..\..\..\..\kernel\core\tos_mutex.c
+
+
+ tos_pend.c
+ 1
+ ..\..\..\..\kernel\core\tos_pend.c
+
+
+ tos_priority_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_mail_queue.c
+
+
+ tos_priority_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_message_queue.c
+
+
+ tos_priority_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_queue.c
+
+
+ tos_ring_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_ring_queue.c
+
+
+ tos_robin.c
+ 1
+ ..\..\..\..\kernel\core\tos_robin.c
+
+
+ tos_rwlock.c
+ 1
+ ..\..\..\..\kernel\core\tos_rwlock.c
+
+
+ tos_sched.c
+ 1
+ ..\..\..\..\kernel\core\tos_sched.c
+
+
+ tos_sem.c
+ 1
+ ..\..\..\..\kernel\core\tos_sem.c
+
+
+ tos_stopwatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_stopwatch.c
+
+
+ tos_sys.c
+ 1
+ ..\..\..\..\kernel\core\tos_sys.c
+
+
+ tos_task.c
+ 1
+ ..\..\..\..\kernel\core\tos_task.c
+
+
+ tos_tick.c
+ 1
+ ..\..\..\..\kernel\core\tos_tick.c
+
+
+ tos_time.c
+ 1
+ ..\..\..\..\kernel\core\tos_time.c
+
+
+ tos_timer.c
+ 1
+ ..\..\..\..\kernel\core\tos_timer.c
+
+
+
+
+ config
+
+
+ tos_config.h
+ 5
+ ..\..\TOS-CONFIG\tos_config.h
+
+
+
+
+ hal/uart
+
+
+ tos_hal_uart.c
+ 1
+ ..\..\..\..\platform\hal\nxp\mimxrt10xx\src\tos_hal_uart.c
+
+
+
+
+ net/at
+
+
+ tos_at.c
+ 1
+ ..\..\..\..\net\at\src\tos_at.c
+
+
+
+
+ net/sal_module_wrapper
+
+
+ sal_module_wrapper.c
+ 1
+ ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c
+
+
+
+
+ devices
+
+
+ esp8266.c
+ 1
+ ..\..\..\..\devices\esp8266\esp8266.c
+
+
+ ec600s.c
+ 1
+ ..\..\..\..\devices\ec20_200_600\ec600s.c
+
+
+
+
+
+
+ TencentOS-Tiny flexspi_nor_release
+ 0x4
+ ARM-ADS
+ 6160000::V6.16::ARMCLANG
+ 1
+
+
+ MIMXRT1062DVL6A
+ NXP
+ NXP.MIMXRT1062_DFP.13.0.0
+ https://mcuxpresso.nxp.com/cmsis_pack/repo/
+ CPUTYPE("Cortex-M7") FPU3(DFPU)
+
+
+
+ 0
+ $$Device:MIMXRT1062DVL6A$Device\Include\fsl_device_registers.h
+
+
+
+
+
+
+
+
+
+ $$Device:MIMXRT1062DVL6A$SVD\MIMXRT1062.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ flexspi_nor_release\
+ hello_world.out
+ 1
+ 0
+ 0
+ 0
+ 1
+ .\output\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 1
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM7
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM7
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M7"
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 3
+ 4
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x20200000
+ 0x40000
+
+
+ 1
+ 0x60000000
+ 0x4000000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20200000
+ 0x40000
+
+
+ 0
+ 0x80000000
+ 0x2000000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x20000
+
+
+ 0
+ 0x20000000
+ 0x20000
+
+
+
+
+
+ 0
+ 7
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 1
+ 1
+ 0
+ 0
+ 0
+
+ -fno-common -fdata-sections -ffreestanding -fno-builtin -mthumb
+ XIP_EXTERNAL_FLASH=1, XIP_BOOT_HEADER_ENABLE=1, NDEBUG, CPU_MIMXRT1062DVL6A, PRINTF_FLOAT_ENABLE=0, SCANF_FLOAT_ENABLE=0, PRINTF_ADVANCED_ENABLE=0, SCANF_ADVANCED_ENABLE=0,SDK_DEBUGCONSOLE_UART
+
+ ..;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\CMSIS\Include;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite;..\board;..\board\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc;..\..\..\..\kernel\core\include;..\..\TOS-CONFIG;..\..\..\..\kernel\hal\include;..\..\..\..\net\at\include;..\..\..\..\net\sal_module_wrapper;..\..\..\..\devices\esp8266;..\..\..\..\devices\ec20_200_600
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ NDEBUG, __STARTUP_INITIALIZE_NONCACHEDATA
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ MIMXRT1062xxxxx_flexspi_nor.scf
+
+
+ --remove --predefine="-DXIP_BOOT_HEADER_ENABLE=1"
+
+ 6314,6329
+
+
+
+
+
+ startup
+
+
+ startup_MIMXRT1062.s
+ 2
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\arm\startup_MIMXRT1062.s
+
+
+
+
+ source
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+
+
+ example
+
+
+ tcp_through_module.c
+ 1
+ ..\..\..\..\examples\tcp_through_module\tcp_through_module.c
+
+
+
+
+ board
+
+
+ board.c
+ 1
+ ..\board\board.c
+
+
+ clock_config.c
+ 1
+ ..\board\clock_config.c
+
+
+ dcd.c
+ 1
+ ..\board\dcd.c
+
+
+ pin_mux.c
+ 1
+ ..\board\pin_mux.c
+
+
+ mcu_init.c
+ 1
+ ..\board\mcu_init.c
+
+
+
+
+ utilities
+
+
+ fsl_assert.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_assert.c
+
+
+ fsl_debug_console.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\utilities\debug_console_lite\fsl_debug_console.c
+
+
+
+
+ drivers
+
+
+ fsl_adc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc.c
+
+
+ fsl_adc_etc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_adc_etc.c
+
+
+ fsl_aipstz.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aipstz.c
+
+
+ fsl_aoi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_aoi.c
+
+
+ fsl_bee.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_bee.c
+
+
+ fsl_cache.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cache.c
+
+
+ fsl_clock.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_clock.c
+
+
+ fsl_cmp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_cmp.c
+
+
+ fsl_common.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_common.c
+
+
+ fsl_csi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_csi.c
+
+
+ fsl_dcdc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcdc.c
+
+
+ fsl_dcp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dcp.c
+
+
+ fsl_dmamux.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_dmamux.c
+
+
+ fsl_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_edma.c
+
+
+ fsl_elcdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_elcdif.c
+
+
+ fsl_enc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enc.c
+
+
+ fsl_enet.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_enet.c
+
+
+ fsl_ewm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ewm.c
+
+
+ fsl_flexcan.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan.c
+
+
+ fsl_flexcan_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexcan_edma.c
+
+
+ fsl_flexio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio.c
+
+
+ fsl_flexio_camera.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera.c
+
+
+ fsl_flexio_camera_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_camera_edma.c
+
+
+ fsl_flexio_i2c_master.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2c_master.c
+
+
+ fsl_flexio_i2s.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s.c
+
+
+ fsl_flexio_i2s_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_i2s_edma.c
+
+
+ fsl_flexio_mculcd.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd.c
+
+
+ fsl_flexio_mculcd_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_mculcd_edma.c
+
+
+ fsl_flexio_spi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi.c
+
+
+ fsl_flexio_spi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_spi_edma.c
+
+
+ fsl_flexio_uart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart.c
+
+
+ fsl_flexio_uart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexio_uart_edma.c
+
+
+ fsl_flexram.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram.c
+
+
+ fsl_flexram_allocate.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexram_allocate.c
+
+
+ fsl_flexspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi.c
+
+
+ fsl_flexspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_flexspi_edma.c
+
+
+ fsl_gpc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpc.c
+
+
+ fsl_gpio.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpio.c
+
+
+ fsl_gpt.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_gpt.c
+
+
+ fsl_kpp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_kpp.c
+
+
+ fsl_lpi2c.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c.c
+
+
+ fsl_lpi2c_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpi2c_edma.c
+
+
+ fsl_lpspi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi.c
+
+
+ fsl_lpspi_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpspi_edma.c
+
+
+ fsl_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart.c
+
+
+ fsl_lpuart_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_lpuart_edma.c
+
+
+ fsl_ocotp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_ocotp.c
+
+
+ fsl_pit.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pit.c
+
+
+ fsl_pmu.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pmu.c
+
+
+ fsl_pwm.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pwm.c
+
+
+ fsl_pxp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_pxp.c
+
+
+ fsl_qtmr.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_qtmr.c
+
+
+ fsl_romapi.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_romapi.c
+
+
+ fsl_rtwdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_rtwdog.c
+
+
+ fsl_sai.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai.c
+
+
+ fsl_sai_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_sai_edma.c
+
+
+ fsl_semc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_semc.c
+
+
+ fsl_snvs_hp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_hp.c
+
+
+ fsl_snvs_lp.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_snvs_lp.c
+
+
+ fsl_spdif.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif.c
+
+
+ fsl_spdif_edma.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_spdif_edma.c
+
+
+ fsl_src.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_src.c
+
+
+ fsl_tempmon.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tempmon.c
+
+
+ fsl_trng.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_trng.c
+
+
+ fsl_tsc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_tsc.c
+
+
+ fsl_usdhc.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_usdhc.c
+
+
+ fsl_wdog.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_wdog.c
+
+
+ fsl_xbara.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbara.c
+
+
+ fsl_xbarb.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\drivers\fsl_xbarb.c
+
+
+
+
+ device
+
+
+ system_MIMXRT1062.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\system_MIMXRT1062.c
+
+
+
+
+ xip
+
+
+ fsl_flexspi_nor_boot.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\xip\fsl_flexspi_nor_boot.c
+
+
+ tosevbrt1062_flexspi_nor_config.c
+ 1
+ ..\board\xip\tosevbrt1062_flexspi_nor_config.c
+
+
+
+
+ nxp/component/uart
+
+
+ fsl_adapter_lpuart.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\uart\fsl_adapter_lpuart.c
+
+
+
+
+ nxp/component/lists
+
+
+ fsl_component_generic_list.c
+ 1
+ ..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1062\components\lists\fsl_component_generic_list.c
+
+
+
+
+ cpu
+
+
+ tos_cpu.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+
+
+ port_c.c
+ 1
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c
+
+
+ port_s.S
+ 2
+ ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S
+
+
+
+
+ kernel
+
+
+ tos_barrier.c
+ 1
+ ..\..\..\..\kernel\core\tos_barrier.c
+
+
+ tos_binary_heap.c
+ 1
+ ..\..\..\..\kernel\core\tos_binary_heap.c
+
+
+ tos_bitmap.c
+ 1
+ ..\..\..\..\kernel\core\tos_bitmap.c
+
+
+ tos_char_fifo.c
+ 1
+ ..\..\..\..\kernel\core\tos_char_fifo.c
+
+
+ tos_completion.c
+ 1
+ ..\..\..\..\kernel\core\tos_completion.c
+
+
+ tos_countdownlatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_countdownlatch.c
+
+
+ tos_event.c
+ 1
+ ..\..\..\..\kernel\core\tos_event.c
+
+
+ tos_global.c
+ 1
+ ..\..\..\..\kernel\core\tos_global.c
+
+
+ tos_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_mail_queue.c
+
+
+ tos_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_message_queue.c
+
+
+ tos_mmblk.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmblk.c
+
+
+ tos_mmheap.c
+ 1
+ ..\..\..\..\kernel\core\tos_mmheap.c
+
+
+ tos_mutex.c
+ 1
+ ..\..\..\..\kernel\core\tos_mutex.c
+
+
+ tos_pend.c
+ 1
+ ..\..\..\..\kernel\core\tos_pend.c
+
+
+ tos_priority_mail_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_mail_queue.c
+
+
+ tos_priority_message_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_message_queue.c
+
+
+ tos_priority_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_priority_queue.c
+
+
+ tos_ring_queue.c
+ 1
+ ..\..\..\..\kernel\core\tos_ring_queue.c
+
+
+ tos_robin.c
+ 1
+ ..\..\..\..\kernel\core\tos_robin.c
+
+
+ tos_rwlock.c
+ 1
+ ..\..\..\..\kernel\core\tos_rwlock.c
+
+
+ tos_sched.c
+ 1
+ ..\..\..\..\kernel\core\tos_sched.c
+
+
+ tos_sem.c
+ 1
+ ..\..\..\..\kernel\core\tos_sem.c
+
+
+ tos_stopwatch.c
+ 1
+ ..\..\..\..\kernel\core\tos_stopwatch.c
+
+
+ tos_sys.c
+ 1
+ ..\..\..\..\kernel\core\tos_sys.c
+
+
+ tos_task.c
+ 1
+ ..\..\..\..\kernel\core\tos_task.c
+
+
+ tos_tick.c
+ 1
+ ..\..\..\..\kernel\core\tos_tick.c
+
+
+ tos_time.c
+ 1
+ ..\..\..\..\kernel\core\tos_time.c
+
+
+ tos_timer.c
+ 1
+ ..\..\..\..\kernel\core\tos_timer.c
+
+
+
+
+ config
+
+
+ tos_config.h
+ 5
+ ..\..\TOS-CONFIG\tos_config.h
+
+
+
+
+ hal/uart
+
+
+ tos_hal_uart.c
+ 1
+ ..\..\..\..\platform\hal\nxp\mimxrt10xx\src\tos_hal_uart.c
+
+
+
+
+ net/at
+
+
+ tos_at.c
+ 1
+ ..\..\..\..\net\at\src\tos_at.c
+
+
+
+
+ net/sal_module_wrapper
+
+
+ sal_module_wrapper.c
+ 1
+ ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c
+
+
+
+
+ devices
+
+
+ esp8266.c
+ 1
+ ..\..\..\..\devices\esp8266\esp8266.c
+
+
+ ec600s.c
+ 1
+ ..\..\..\..\devices\ec20_200_600\ec600s.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ TencentOS-Tiny
+ 0
+ 1
+
+
+
+
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_flexspi_nor.ini b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_flexspi_nor.ini
new file mode 100644
index 00000000..4624147d
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_flexspi_nor.ini
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+FUNC void _loadDcdcTrim(void)
+{
+ unsigned int dcdc_trim_loaded;
+ unsigned long ocotp_base;
+ unsigned long ocotp_fuse_bank0_base;
+ unsigned long dcdc_base;
+ unsigned long reg;
+ unsigned long trim_value;
+ unsigned int index;
+
+ ocotp_base = 0x401F4000;
+ ocotp_fuse_bank0_base = ocotp_base + 0x400;
+ dcdc_base = 0x40080000;
+
+ dcdc_trim_loaded = 0;
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
+ if (reg & (1<<10))
+ {
+ // DCDC: REG0->VBG_TRM
+ trim_value = (reg & (0x1F << 11)) >> 11;
+ reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
+ _WDWORD(dcdc_base + 0x4, reg);
+ dcdc_trim_loaded = 1;
+ }
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
+ if (reg & (1<<30))
+ {
+ index = (reg & (3 << 28)) >> 28;
+ if (index < 4)
+ {
+ // DCDC: REG3->TRG
+ reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
+ _WDWORD(dcdc_base + 0xC, reg);
+ dcdc_trim_loaded = 1;
+ }
+ }
+
+ if (dcdc_trim_loaded)
+ {
+ // delay about 400us till dcdc is stable.
+ _Sleep_(1);
+ }
+}
+
+FUNC void restoreFlexRAM(void)
+{
+ unsigned int value;
+ unsigned int base;
+
+ base = 0x400AC000;
+
+ value = _RDWORD(base + 0x44);
+ value &= ~(0xFFFFFFFF);
+ value |= 0x55AFFA55;
+ _WDWORD(base + 0x44, value);
+
+ value = _RDWORD(base + 0x40);
+ value |= (1 << 2);
+ _WDWORD(base + 0x40, value);
+}
+
+FUNC void Setup (void) {
+ _loadDcdcTrim();
+ SP = _RDWORD(0x60002000); // Setup Stack Pointer
+ PC = _RDWORD(0x60002004); // Setup Program Counter
+ _WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
+}
+
+FUNC void OnResetExec (void) { // executes upon software RESET
+ restoreFlexRAM();
+ Setup(); // Setup for Running
+}
+
+restoreFlexRAM();
+
+LOAD %L INCREMENTAL // Download
+
+Setup(); // Setup for Running
+
+// g, main
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_ram.ini b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_ram.ini
new file mode 100644
index 00000000..7eccf483
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_ram.ini
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+FUNC void _loadDcdcTrim(void)
+{
+ unsigned int dcdc_trim_loaded;
+ unsigned long ocotp_base;
+ unsigned long ocotp_fuse_bank0_base;
+ unsigned long dcdc_base;
+ unsigned long reg;
+ unsigned long trim_value;
+ unsigned int index;
+
+ ocotp_base = 0x401F4000;
+ ocotp_fuse_bank0_base = ocotp_base + 0x400;
+ dcdc_base = 0x40080000;
+
+ dcdc_trim_loaded = 0;
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
+ if (reg & (1<<10))
+ {
+ // DCDC: REG0->VBG_TRM
+ trim_value = (reg & (0x1F << 11)) >> 11;
+ reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
+ _WDWORD(dcdc_base + 0x4, reg);
+ dcdc_trim_loaded = 1;
+ }
+
+ reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
+ if (reg & (1<<30))
+ {
+ index = (reg & (3 << 28)) >> 28;
+ if (index < 4)
+ {
+ // DCDC: REG3->TRG
+ reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
+ _WDWORD(dcdc_base + 0xC, reg);
+ dcdc_trim_loaded = 1;
+ }
+ }
+
+ if (dcdc_trim_loaded)
+ {
+ // delay about 400us till dcdc is stable.
+ _Sleep_(1);
+ }
+}
+
+FUNC void restoreFlexRAM(void)
+{
+ unsigned int value;
+ unsigned int base;
+
+ base = 0x400AC000;
+
+ value = _RDWORD(base + 0x44);
+ value &= ~(0xFFFFFFFF);
+ value |= 0x55AFFA55;
+ _WDWORD(base + 0x44, value);
+
+ value = _RDWORD(base + 0x40);
+ value |= (1 << 2);
+ _WDWORD(base + 0x40, value);
+}
+
+FUNC void Setup (void) {
+ _loadDcdcTrim();
+ SP = _RDWORD(0x00000000); // Setup Stack Pointer
+ PC = _RDWORD(0x00000004); // Setup Program Counter
+ _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
+}
+
+FUNC void OnResetExec (void) { // executes upon software RESET
+ restoreFlexRAM();
+ Setup(); // Setup for Running
+}
+
+restoreFlexRAM();
+
+LOAD %L INCREMENTAL // Download
+
+Setup(); // Setup for Running
+
+// g, main
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.c b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.c
new file mode 100644
index 00000000..cd8708cb
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_lpi2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get debug console frequency. */
+uint32_t BOARD_DebugConsoleSrcFreq(void)
+{
+ uint32_t freq;
+
+ /* To make it simple, we assume default PLL and divider settings, and the only variable
+ from application is use PLL3 source or OSC source */
+ if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
+ {
+ freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+ else
+ {
+ freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+
+ return freq;
+}
+
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
+{
+ lpi2c_master_config_t lpi2cConfig = {0};
+
+ /*
+ * lpi2cConfig.debugEnable = false;
+ * lpi2cConfig.ignoreAck = false;
+ * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
+ * lpi2cConfig.baudRate_Hz = 100000U;
+ * lpi2cConfig.busIdleTimeout_ns = 0;
+ * lpi2cConfig.pinLowTimeout_ns = 0;
+ * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
+ * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
+ */
+ LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
+ LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_LPI2C_Send(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Write;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = txBuff;
+ xfer.dataSize = txBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Read;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = rxBuff;
+ xfer.dataSize = rxBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Write;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = txBuff;
+ xfer.dataSize = txBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ status_t status;
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Write;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = NULL;
+ xfer.dataSize = 0;
+
+ status = LPI2C_MasterTransferBlocking(base, &xfer);
+
+ if (kStatus_Success == status)
+ {
+ xfer.subaddressSize = 0;
+ xfer.direction = kLPI2C_Read;
+ xfer.data = rxBuff;
+ xfer.dataSize = rxBuffSize;
+
+ status = LPI2C_MasterTransferBlocking(base, &xfer);
+ }
+
+ return status;
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+ BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+ uint8_t data = (uint8_t)txBuff;
+
+ return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+ BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Camera_I2C_Init(void)
+{
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
+ BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Camera_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Camera_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
+ rxBuffSize);
+}
+
+status_t BOARD_Camera_I2C_SendSCCB(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Camera_I2C_ReceiveSCCB(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
+ rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/* MPU configuration. */
+void BOARD_ConfigMPU(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Image$$RW_m_ncache$$Base[];
+ /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
+ extern uint32_t Image$$RW_m_ncache_unused$$Base[];
+ extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
+ uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
+ uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
+ 0 :
+ ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
+#elif defined(__MCUXPRESSO)
+ extern uint32_t __base_NCACHE_REGION;
+ extern uint32_t __top_NCACHE_REGION;
+ uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
+ uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
+#elif defined(__ICCARM__) || defined(__GNUC__)
+ extern uint32_t __NCACHE_REGION_START[];
+ extern uint32_t __NCACHE_REGION_SIZE[];
+ uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
+ uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
+#endif
+ volatile uint32_t i = 0;
+
+ /* Disable I cache and D cache */
+ if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
+ {
+ SCB_DisableICache();
+ }
+ if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
+ {
+ SCB_DisableDCache();
+ }
+
+ /* Disable MPU */
+ ARM_MPU_Disable();
+
+ /* MPU configure:
+ * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
+ * SubRegionDisable, Size)
+ * API in mpu_armv7.h.
+ * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
+ * disabled.
+ * param AccessPermission Data access permissions, allows you to configure read/write access for User and
+ * Privileged mode.
+ * Use MACROS defined in mpu_armv7.h:
+ * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
+ * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
+ * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
+ * 0 x 0 0 Strongly Ordered shareable
+ * 0 x 0 1 Device shareable
+ * 0 0 1 0 Normal not shareable Outer and inner write
+ * through no write allocate
+ * 0 0 1 1 Normal not shareable Outer and inner write
+ * back no write allocate
+ * 0 1 1 0 Normal shareable Outer and inner write
+ * through no write allocate
+ * 0 1 1 1 Normal shareable Outer and inner write
+ * back no write allocate
+ * 1 0 0 0 Normal not shareable outer and inner
+ * noncache
+ * 1 1 0 0 Normal shareable outer and inner
+ * noncache
+ * 1 0 1 1 Normal not shareable outer and inner write
+ * back write/read acllocate
+ * 1 1 1 1 Normal shareable outer and inner write
+ * back write/read acllocate
+ * 2 x 0 0 Device not shareable
+ * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
+ * policy.
+ * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide
+ * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
+ * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
+ * mpu_armv7.h.
+ */
+
+ /*
+ * Add default region to deny access to whole address space to workaround speculative prefetch.
+ * Refer to Arm errata 1013783-B for more details.
+ *
+ */
+ /* Region 0 setting: Instruction access disabled, No data access permission. */
+ MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
+
+ /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+ /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
+ /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
+ MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
+#endif
+
+ /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+ /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+ /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+ /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
+
+ /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+ /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert(!(nonCacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
+ }
+
+ /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
+
+ /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
+
+ /* Enable MPU */
+ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+ /* Enable I cache and D cache */
+ SCB_EnableDCache();
+ SCB_EnableICache();
+}
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.h b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.h
new file mode 100644
index 00000000..af781e3d
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/board.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "MIMXRT1060-EVK"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
+#define BOARD_DEBUG_UART_INSTANCE 1U
+
+#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
+
+#define BOARD_UART_IRQ LPUART1_IRQn
+#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE (115200U)
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/*! @brief The USER_LED used for board */
+#define LOGIC_LED_ON (0U)
+#define LOGIC_LED_OFF (1U)
+#ifndef BOARD_USER_LED_GPIO
+#define BOARD_USER_LED_GPIO GPIO1
+#endif
+#ifndef BOARD_USER_LED_GPIO_PIN
+#define BOARD_USER_LED_GPIO_PIN (9U)
+#endif
+
+#define USER_LED_INIT(output) \
+ GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
+ BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
+#define USER_LED_ON() \
+ GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
+#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+ /* Disable Flexspi2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi2);
+ /* Set FLEXSPI2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+ /* Set Flexspi2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can3);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ CLOCK_DisableClock(kCLOCK_Can3S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+ /* Disable Usb1 PLL output for USBPHY1. */
+ CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+ {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+ /* DeInit Enet PLL. */
+ CLOCK_DeinitEnetPll();
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* Set Enet output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ /* Enable Enet output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+ /* Set Enet2 output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+ /* Enable Enet2 output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+ /* Enable Enet25M output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+ /* DeInit Usb2 PLL. */
+ CLOCK_DeinitUsb2Pll();
+ /* Bypass Usb2 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+ /* Enable Usb2 PLL output. */
+ CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+ /* Set ENET2 Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/clock_config.h b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/clock_config.h
new file mode 100644
index 00000000..663e6c6e
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/clock_config.h
@@ -0,0 +1,121 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.c b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.c
new file mode 100644
index 00000000..64a9db5b
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.c
@@ -0,0 +1,308 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#include "dcd.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.dcd_data"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.dcd_data"
+#endif
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: DCDx v3.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 10.0.0
+board: MIMXRT1060-EVK
+output_format: c_array
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
+const uint8_t dcd_data[] = {
+ /* HEADER */
+ /* Tag */
+ 0xD2,
+ /* Image Length */
+ 0x04, 0x10,
+ /* Version */
+ 0x41,
+
+ /* COMMANDS */
+
+ /* group: 'Imported Commands' */
+ /* #1.1-113, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x03, 0x8C, 0x04,
+ /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
+ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
+ /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
+ 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
+ /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
+ /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
+ /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
+ /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
+ /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
+ /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
+ /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
+ /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
+ /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
+ /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
+ /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
+ /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
+ /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
+ /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
+ /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
+ /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
+ /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
+ /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
+ /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
+ /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
+ /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
+ /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
+ /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
+ /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
+ /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
+ /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
+ /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
+ /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
+ /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
+ /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
+ /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
+ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
+ /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
+ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
+ /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
+ 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
+ /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
+ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
+ /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
+ 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
+ /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
+ /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
+ /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
+ /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
+ /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
+ 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
+ /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
+ 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
+ /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
+ 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
+ /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
+ /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
+ 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
+ /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
+ 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
+ /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
+ 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
+ /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
+ 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
+ /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
+ 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
+ /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
+ 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
+ /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
+ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
+ /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
+ 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
+ /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
+ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
+ /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
+ 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
+ /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #3.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #5.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #7.1-3, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x1C, 0x04,
+ /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
+ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
+ /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
+ /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
+ 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
+ };
+/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
+
+#else
+const uint8_t dcd_data[] = {0x00};
+#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.h b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.h
new file mode 100644
index 00000000..3d8b7cd7
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/dcd.h
@@ -0,0 +1,25 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef __DCD__
+#define __DCD__
+
+#include
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*************************************
+ * DCD Data
+ *************************************/
+#define DCD_TAG_HEADER (0xD2)
+#define DCD_VERSION (0x41)
+#define DCD_TAG_HEADER_SHIFT (24)
+#define DCD_ARRAY_SIZE 1
+
+#endif /* __DCD__ */
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.c b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.c
new file mode 100644
index 00000000..8cb6bb70
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.c
@@ -0,0 +1,54 @@
+#include "mcu_init.h"
+#include "tos_at.h"
+
+void board_init(void)
+{
+ /* Init board hardware. */
+ BOARD_ConfigMPU();
+ BOARD_InitPins();
+ BOARD_InitBootClocks();
+
+ BOARD_InitDebugConsole();
+}
+
+void SysTick_Handler(void)
+{
+ if (tos_knl_is_running()) {
+ tos_knl_irq_enter();
+ tos_tick_handler();
+ tos_knl_irq_leave();
+ }
+}
+
+/* LPUART2_IRQn interrupt handler */
+void LPUART2_IRQHandler(void) {
+ uint8_t data;
+
+ tos_knl_irq_enter();
+
+ /* If new data arrived. */
+ if ((kLPUART_RxDataRegFullFlag)&LPUART_GetStatusFlags(LPUART2))
+ {
+ data = LPUART_ReadByte(LPUART2);
+ tos_at_uart_input_byte(data);
+ }
+
+ tos_knl_irq_leave();
+}
+
+/* LPUART4_IRQn interrupt handler */
+void LPUART4_IRQHandler(void) {
+ uint8_t data;
+
+ tos_knl_irq_enter();
+
+ /* If new data arrived. */
+ if ((kLPUART_RxDataRegFullFlag)&LPUART_GetStatusFlags(LPUART4))
+ {
+ data = LPUART_ReadByte(LPUART4);
+ tos_at_uart_input_byte(data);
+ }
+
+ tos_knl_irq_leave();
+}
+
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.h b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.h
new file mode 100644
index 00000000..9a2a04ba
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/mcu_init.h
@@ -0,0 +1,20 @@
+#ifndef __MCU_INIT_H
+#define __MCU_INIT_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "tos_k.h"
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_lpuart.h"
+
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ __MCU_INIT_H */
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.c b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.c
new file mode 100644
index 00000000..a901ef12
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.c
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v10.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 10.0.0
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+ pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+ pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ - {pin_num: M12, peripheral: LPUART2, signal: RX, pin_signal: GPIO_AD_B1_03}
+ - {pin_num: L11, peripheral: LPUART2, signal: TX, pin_signal: GPIO_AD_B1_02}
+ - {pin_num: M5, peripheral: LPUART4, signal: RX, pin_signal: GPIO_SD_B1_01}
+ - {pin_num: L5, peripheral: LPUART4, signal: TX, pin_signal: GPIO_SD_B1_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_LPUART4_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_LPUART4_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.h b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.h
new file mode 100644
index 00000000..08577cc1
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/pin_mux.h
@@ -0,0 +1,87 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type */
+typedef enum _pin_mux_direction
+{
+ kPIN_MUX_DirectionInput = 0U, /* Input direction */
+ kPIN_MUX_DirectionOutput = 1U, /* Output direction */
+ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
+
+/* GPIO_AD_B1_03 (coord M12), SPDIF_IN/J22[8] */
+/* Routed pin properties */
+#define BOARD_INITPINS_SPDIF_IN_PERIPHERAL LPUART2 /*!< Peripheral name */
+#define BOARD_INITPINS_SPDIF_IN_SIGNAL RX /*!< Signal name */
+
+/* GPIO_AD_B1_02 (coord L11), SPDIF_OUT/J22[7] */
+/* Routed pin properties */
+#define BOARD_INITPINS_SPDIF_OUT_PERIPHERAL LPUART2 /*!< Peripheral name */
+#define BOARD_INITPINS_SPDIF_OUT_SIGNAL TX /*!< Signal name */
+
+/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */
+/* Routed pin properties */
+#define BOARD_INITPINS_FlexSPI_D2_B_PERIPHERAL LPUART4 /*!< Peripheral name */
+#define BOARD_INITPINS_FlexSPI_D2_B_SIGNAL RX /*!< Signal name */
+
+/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */
+/* Routed pin properties */
+#define BOARD_INITPINS_FlexSPI_D3_B_PERIPHERAL LPUART4 /*!< Peripheral name */
+#define BOARD_INITPINS_FlexSPI_D3_B_SIGNAL TX /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.c b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.c
new file mode 100644
index 00000000..8e186ef2
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "tosevbrt1062_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+ .memConfig =
+ {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+ .sflashPadType = kSerialFlash_4Pads,
+ .serialClkFreq = kFlexSpiSerialClk_100MHz,
+ .sflashA1Size = 8u * 1024u * 1024u,
+ .lookupTable =
+ {
+ // Read LUTs
+ FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+ },
+ },
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .blockSize = 64u * 1024u,
+ .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.h b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.h
new file mode 100644
index 00000000..f416a822
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/board/xip/tosevbrt1062_flexspi_nor_config.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
+
+#include
+#include
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_100MHz = 6,
+ kFlexSpiSerialClk_120MHz = 7,
+ kFlexSpiSerialClk_133MHz = 8,
+ kFlexSpiSerialClk_166MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+ kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+ kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+ kFlexSPIReadSampleClk_LoopbackInternally = 0,
+ kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+ kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+ kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+ kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
+ kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
+ kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
+ kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
+ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
+ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+ kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+ kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
+ kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
+ kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
+ kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+ kSerialFlash_1Pad = 1,
+ kSerialFlash_2Pads = 2,
+ kSerialFlash_4Pads = 4,
+ kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+ uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+ uint8_t seqId; //!< Sequence Index, valid number: 0-15
+ uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+ kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
+ kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+ kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
+ kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
+ kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
+ kDeviceConfigCmdType_Reset, //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+ uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+ uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+ uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
+ uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+ uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
+ uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
+ uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+ //! Serial NAND, need to refer to datasheet
+ uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+ uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+ //! Generic configuration, etc.
+ uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+ //! DPI/QPI/OPI switch or reset command
+ flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+ //! sequence number, [31:16] Reserved
+ uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
+ uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+ uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+ flexspi_lut_seq_t
+ configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+ uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
+ uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+ uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
+ uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+ //! details
+ uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
+ uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+ uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+ //! Chapter for more details
+ uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+ //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+ uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
+ uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
+ uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
+ uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
+ uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
+ uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
+ uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+ uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+ uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
+ uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
+ uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
+ uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+ uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+ uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+ //! busy flag is 0 when flash device is busy
+ uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
+ flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+ uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/* */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
+#define NOR_CMD_INDEX_DUMMY 6 //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+ CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+ 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+ CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+ 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+ CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+ 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+ 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ * Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+ flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+ uint32_t pageSize; //!< Page size of Serial NOR
+ uint32_t sectorSize; //!< Sector size of Serial NOR
+ uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
+ uint8_t isUniformBlockSize; //!< Sector/Block size is the same
+ uint8_t reserved0[2]; //!< Reserved for future use
+ uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
+ uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
+ uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
+ uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
+ uint32_t blockSize; //!< Block size
+ uint32_t reserve2[11]; //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
diff --git a/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/main.c b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/main.c
new file mode 100644
index 00000000..a6d087a8
--- /dev/null
+++ b/board/TencentOS_tiny_EVB_AIoT/tcp_through_module/main.c
@@ -0,0 +1,28 @@
+#include "mcu_init.h"
+
+#define APPLICATION_TASK_STK_SIZE 4096
+k_task_t application_task;
+uint8_t application_task_stk[APPLICATION_TASK_STK_SIZE];
+
+extern void application_entry(void *arg);
+
+#pragma weak application_entry
+void application_entry(void *arg)
+{
+ while (1) {
+ printf("This is a demo task,please use your task entry!\r\n");
+ tos_task_delay(1000);
+ }
+}
+
+int main(void)
+{
+ board_init();
+ PRINTF("Welcome to TencentOS tiny(%s)\r\n", TOS_VERSION);
+ tos_knl_init(); // TencentOS Tiny kernel initialize
+ tos_task_create(&application_task, "application_task", application_entry, NULL, 4, application_task_stk, APPLICATION_TASK_STK_SIZE, 0);
+ tos_knl_start();
+
+ while (1);
+}
+
diff --git a/devices/ec20_200_600/ec600s.c b/devices/ec20_200_600/ec600s.c
index e471f75c..361db6fe 100644
--- a/devices/ec20_200_600/ec600s.c
+++ b/devices/ec20_200_600/ec600s.c
@@ -491,7 +491,9 @@ __STATIC__ void ec600s_incoming_data_process(void)
}
do {
+#if !defined(MIN)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
read_len = MIN(data_len, sizeof(buffer));
if (tos_at_uart_read(buffer, read_len) != read_len) {
return;
diff --git a/devices/esp8266/esp8266.c b/devices/esp8266/esp8266.c
index 5cfd7cff..88d1e5d9 100644
--- a/devices/esp8266/esp8266.c
+++ b/devices/esp8266/esp8266.c
@@ -430,7 +430,9 @@ __STATIC__ void esp8266_incoming_data_process(void)
}
do {
+#if !defined(MIN)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
read_len = MIN(data_len, sizeof(buffer));
if (tos_at_uart_read(buffer, read_len) != read_len) {
return;
diff --git a/examples/tcp_through_module/tcp_through_module.c b/examples/tcp_through_module/tcp_through_module.c
index 19df6797..9ad9fc6f 100644
--- a/examples/tcp_through_module/tcp_through_module.c
+++ b/examples/tcp_through_module/tcp_through_module.c
@@ -1,34 +1,24 @@
#include "mcu_init.h"
#include "sal_module_wrapper.h"
-#include "cmsis_os.h"
#define USE_ESP8266
-
-//#define USE_AIR724
-
-//#define USE_EC600S
+//#define USE_EC20_200_600
#ifdef USE_ESP8266
#include "esp8266.h"
#endif
-
-#ifdef USE_AIR724
-#include "air724.h"
-#endif
-
-
-#ifdef USE_EC600S
+#ifdef USE_EC20_200_600
#include "ec600s.h"
#endif
-#define TCP_TEST_TASK0_STK_SIZE 4096
-void tcp_test0(void);
-osThreadDef(tcp_test0, osPriorityNormal, 1, TCP_TEST_TASK0_STK_SIZE);
+#define TCP_TEST0_TASK_STK_SIZE 4096
+k_task_t tcp_test0_task;
+uint8_t tcp_test0_task_stk[TCP_TEST0_TASK_STK_SIZE];
-#define TCP_TEST_TASK1_STK_SIZE 4096
-void tcp_test1(void);
-osThreadDef(tcp_test1, osPriorityNormal, 1, TCP_TEST_TASK1_STK_SIZE);
+#define TCP_TEST1_TASK_STK_SIZE 4096
+k_task_t tcp_test1_task;
+uint8_t tcp_test1_task_stk[TCP_TEST1_TASK_STK_SIZE];
int socket_id_0 = -1;
int socket_id_1 = -1;
@@ -37,7 +27,7 @@ int socket_id_1 = -1;
uint8_t recv_data_0[RECV_LEN];
uint8_t recv_data_1[RECV_LEN];
-void tcp_test0(void)
+void tcp_test0(void *args)
{
int recv_len = -1;
@@ -58,7 +48,7 @@ void tcp_test0(void)
}
}
-void tcp_test1(void)
+void tcp_test1(void *args)
{
int recv_len = -1;
@@ -83,12 +73,10 @@ void tcp_test1(void)
void application_entry(void *arg)
{
#if defined(USE_ESP8266)
- esp8266_sal_init(HAL_UART_PORT_0);
+ esp8266_sal_init(HAL_UART_PORT_2);
esp8266_join_ap("Mculover666", "mculover666");
-#elif defined(USE_AIR724)
- air724_sal_init(HAL_UART_PORT_0);
-#elif defined(USE_EC600S)
- ec600s_sal_init(HAL_UART_PORT_0);
+#elif defined(USE_EC20_200_600)
+ ec600s_sal_init(HAL_UART_PORT_4);
#endif
socket_id_0 = tos_sal_module_connect("117.50.111.72", "8080", TOS_SAL_PROTO_TCP);
@@ -105,7 +93,7 @@ void application_entry(void *arg)
printf("TCP1 connect success! fd: %d\n", socket_id_1);
}
- osThreadCreate(osThread(tcp_test0), NULL);
- osThreadCreate(osThread(tcp_test1), NULL);
+ tos_task_create(&tcp_test0_task, "task1", tcp_test0, NULL, 3, tcp_test0_task_stk, TCP_TEST0_TASK_STK_SIZE, 0);
+ tos_task_create(&tcp_test1_task, "task2", tcp_test1, NULL, 3, tcp_test1_task_stk, TCP_TEST1_TASK_STK_SIZE, 0);
}
diff --git a/platform/hal/nxp/mimxrt10xx/src/tos_hal_uart.c b/platform/hal/nxp/mimxrt10xx/src/tos_hal_uart.c
new file mode 100644
index 00000000..63e9094e
--- /dev/null
+++ b/platform/hal/nxp/mimxrt10xx/src/tos_hal_uart.c
@@ -0,0 +1,130 @@
+#include "tos_k.h"
+#include "tos_hal.h"
+#include "fsl_lpuart.h"
+
+/* Definition of the clock source frequency */
+#define LPUART_CLOCK_SOURCE 80000000UL
+
+__API__ int tos_hal_uart_init(hal_uart_t *uart, hal_uart_port_t port)
+{
+ status_t status;
+ lpuart_config_t config;
+
+ if (!uart) {
+ return -1;
+ }
+
+ if (port == HAL_UART_PORT_0) {
+ // not support.
+ return -1;
+ } else if (port == HAL_UART_PORT_1) {
+ uart->private_uart = LPUART1;
+
+ LPUART_GetDefaultConfig(&config);
+ config.baudRate_Bps = 115200;
+ config.enableTx = true;
+ config.enableRx = true;
+ status = LPUART_Init(LPUART1, &config, LPUART_CLOCK_SOURCE);
+ if (status != kStatus_Success) {
+ return -1;
+ }
+
+ /* Enable RX interrupt. */
+ LPUART_EnableInterrupts(LPUART1, kLPUART_RxDataRegFullInterruptEnable);
+ EnableIRQ(LPUART1_IRQn);
+ } else if (port == HAL_UART_PORT_2) {
+ uart->private_uart = LPUART2;
+
+ LPUART_GetDefaultConfig(&config);
+ config.baudRate_Bps = 115200;
+ config.enableTx = true;
+ config.enableRx = true;
+ status = LPUART_Init(LPUART2, &config, LPUART_CLOCK_SOURCE);
+ if (status != kStatus_Success) {
+ return -1;
+ }
+
+ /* Enable RX interrupt. */
+ LPUART_EnableInterrupts(LPUART2, kLPUART_RxDataRegFullInterruptEnable);
+ EnableIRQ(LPUART2_IRQn);
+ } else if (port == HAL_UART_PORT_3) {
+ uart->private_uart = LPUART3;
+
+ LPUART_GetDefaultConfig(&config);
+ config.baudRate_Bps = 115200;
+ config.enableTx = true;
+ config.enableRx = true;
+ status = LPUART_Init(LPUART3, &config, LPUART_CLOCK_SOURCE);
+ if (status != kStatus_Success) {
+ return -1;
+ }
+
+ /* Enable RX interrupt. */
+ LPUART_EnableInterrupts(LPUART3, kLPUART_RxDataRegFullInterruptEnable);
+ EnableIRQ(LPUART3_IRQn);
+ } else if (port == HAL_UART_PORT_4) {
+ uart->private_uart = LPUART4;
+
+ LPUART_GetDefaultConfig(&config);
+ config.baudRate_Bps = 115200;
+ config.enableTx = true;
+ config.enableRx = true;
+ status = LPUART_Init(LPUART4, &config, LPUART_CLOCK_SOURCE);
+ if (status != kStatus_Success) {
+ return -1;
+ }
+
+ /* Enable RX interrupt. */
+ LPUART_EnableInterrupts(LPUART4, kLPUART_RxDataRegFullInterruptEnable);
+ EnableIRQ(LPUART4_IRQn);
+ }
+
+ return 0;
+}
+
+__API__ int tos_hal_uart_write(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout)
+{
+ status_t status;
+ LPUART_Type *base;
+
+ if (!uart || !buf) {
+ return -1;
+ }
+
+ if (!uart->private_uart) {
+ return -1;
+ }
+
+ base = (LPUART_Type *)uart->private_uart;
+
+ status = LPUART_WriteBlocking(base, (uint8_t *)buf, size);
+ if (status != kStatus_Success) {
+ return -1;
+ }
+ return 0;
+}
+
+__API__ int tos_hal_uart_read(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout)
+{
+ return 0;
+}
+
+__API__ int tos_hal_uart_deinit(hal_uart_t *uart)
+{
+ LPUART_Type *base;
+
+ if (!uart) {
+ return -1;
+ }
+
+ if (!uart->private_uart) {
+ return -1;
+ }
+
+ base = (LPUART_Type *)uart->private_uart;
+
+ LPUART_Deinit(base);
+
+ return 0;
+}
+