From af245f2e5bf7fbce5c6378d5ad0398972d3fbbb1 Mon Sep 17 00:00:00 2001 From: acezhao Date: Fri, 13 Sep 2019 00:45:38 +0800 Subject: [PATCH 1/5] port TencentOS tiny to RISC-V --- arch/risc-v/common/riscv_encoding.h | 1368 +++++++++++++++++ arch/risc-v/common/tos_cpu.c | 190 +++ arch/risc-v/common/tos_cpu.h | 118 ++ arch/risc-v/common/tos_cpu_def.h | 23 + arch/risc-v/common/tos_cpu_types.h | 46 + arch/risc-v/common/tos_fault.h | 10 + arch/risc-v/rv32i/port.h | 72 + arch/risc-v/rv32i/port_c.c | 148 ++ arch/risc-v/rv32i/port_config.h | 27 + arch/risc-v/rv32i/port_s.S | 407 +++++ arch/risc-v/rv32i/start.S | 209 +++ .../QEMU_Spike/eclipse/hello_world/.cproject | 436 ++++++ .../QEMU_Spike/eclipse/hello_world/.gitignore | 1 + board/QEMU_Spike/eclipse/hello_world/.project | 53 + .../.settings/language.settings.xml | 48 + .../org.eclipse.cdt.codan.core.prefs | 75 + .../org.eclipse.ltk.core.refactoring.prefs | 2 + .../eclipse/hello_world/Inc/tos_config.h | 55 + .../QEMU_Spike/eclipse/hello_world/Src/main.c | 97 ++ board/QEMU_Spike/eclipse/hello_world/link.ld | 52 + 20 files changed, 3437 insertions(+) create mode 100644 arch/risc-v/common/riscv_encoding.h create mode 100644 arch/risc-v/common/tos_cpu.c create mode 100644 arch/risc-v/common/tos_cpu.h create mode 100644 arch/risc-v/common/tos_cpu_def.h create mode 100644 arch/risc-v/common/tos_cpu_types.h create mode 100644 arch/risc-v/common/tos_fault.h create mode 100644 arch/risc-v/rv32i/port.h create mode 100644 arch/risc-v/rv32i/port_c.c create mode 100644 arch/risc-v/rv32i/port_config.h create mode 100644 arch/risc-v/rv32i/port_s.S create mode 100644 arch/risc-v/rv32i/start.S create mode 100644 board/QEMU_Spike/eclipse/hello_world/.cproject create mode 100644 board/QEMU_Spike/eclipse/hello_world/.gitignore create mode 100644 board/QEMU_Spike/eclipse/hello_world/.project create mode 100644 board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml create mode 100644 board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.ltk.core.refactoring.prefs create mode 100644 board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h create mode 100644 board/QEMU_Spike/eclipse/hello_world/Src/main.c create mode 100644 board/QEMU_Spike/eclipse/hello_world/link.ld diff --git a/arch/risc-v/common/riscv_encoding.h b/arch/risc-v/common/riscv_encoding.h new file mode 100644 index 00000000..07049e68 --- /dev/null +++ b/arch/risc-v/common/riscv_encoding.h @@ -0,0 +1,1368 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define MIE_SSIE MIP_SSIP +#define MIE_HSIE MIP_HSIP +#define MIE_MSIE MIP_MSIP +#define MIE_STIE MIP_STIP +#define MIE_HTIE MIP_HTIP +#define MIE_MTIE MIP_MTIP +#define MIE_SEIE MIP_SEIP +#define MIE_HEIE MIP_HEIP +#define MIE_MEIE MIP_MEIP + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_fpu(reg) ({ unsigned long __tmp; \ + asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_fpu(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) + + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + + + + + + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + + +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 + +#define CSR_MCOUNTINHIBIT 0x320 + +#define CSR_MNVEC 0x7C3 + +#define CSR_MTVT2 0x7EC +#define CSR_JALMNXTI 0x7ED +#define CSR_PUSHMCAUSE 0x7EE +#define CSR_PUSHMEPC 0x7EF +#define CSR_PUSHMSUBM 0x7EB + +#define CSR_WFE 0x810 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 + +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MSUBM 0x7c4 + + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, +MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, +MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, +MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, +MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif + diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c new file mode 100644 index 00000000..5ad1656c --- /dev/null +++ b/arch/risc-v/common/tos_cpu.c @@ -0,0 +1,190 @@ +/* + * tos_cpu.c + * + * Created on: Sep 8, 2019 + * Author: ace + */ +#include +#include + +// soc code shoud not put here +#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; + +__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +{ + port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); + port_systick_config(cycle_per_tick); +} + +__KERNEL__ void cpu_init(void) { + k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; + cpu_systick_init(k_cpu_cycle_per_tick); + //TODO +} + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void) +{ + return port_cpsr_save(); +} + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) +{ + port_cpsr_restore(cpsr); +} + + +__KERNEL__ void cpu_context_switch(void) +{ + port_context_switch(); +} + +__KERNEL__ void cpu_irq_context_switch(void) +{ + port_irq_context_switch(); +} + +__KERNEL__ void cpu_sched_start(void) +{ + port_sched_start(); +} + +/* + +Inx Offset Register +31 124 x31 t6 +32 120 x30 t5 +29 116 x29 t4 +28 112 x28 t3 +27 108 x27 s11 +26 104 x26 s10 +25 100 x25 s9 +24 096 x24 s8 +23 092 x23 s7 +22 088 x22 s6 +21 084 x21 s5 +20 080 x20 s4 +19 076 x19 s3 +18 072 x18 s2 +17 068 x17 a7 +16 064 x16 a6 +15 060 x15 a5 +14 056 x14 a4 +13 052 x13 a3 +12 048 x12 a2 +11 044 x11 a1 +10 040 x10 a0 +09 036 x9 s1 +08 032 x8 s0/fp +07 028 x7 t2 +06 024 x6 t1 +05 020 x5 t0 +04 016 x4 tp +03 012 x3 gp +02 008 x1 ra +01 004 mstatus +00 000 epc + +*/ + +__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size) +{ + cpu_data_t *sp = 0; + cpu_context_t *regs = 0; + + sp = (cpu_data_t *)&stk_base[stk_size]; + sp = (cpu_data_t *)((cpu_addr_t)(sp) & 0xFFFFFFF8); + + sp -= (sizeof(cpu_context_t)/sizeof(cpu_data_t)); + + regs = (cpu_context_t*) sp; + +#if 1 + for(int i=0; i<(sizeof(cpu_context_t)/sizeof(cpu_data_t)); i++) { + #define _V(v) ((unsigned int)((v/10) << 4 | (v % 10))) + *(sp + i) = (_V(i) << 24) | (_V(i) << 16) | (_V(i) << 8) | _V(i); + #undef _V + } +#endif + + regs->a0 = (cpu_data_t)arg; // a0: argument + regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address + regs->mstatus = (cpu_data_t)(MSTATUS_MPP | MSTATUS_MPIE); // return to machine mode and enable interrupt + regs->epc = (cpu_data_t)entry; + + + return (k_stack_t*)sp; +} + +void cpu_trap_entry(cpu_data_t cause, cpu_context_t *regs) +{ + int ddd = cause; + while(1) { + ddd++; + } +} + +void SysTick_IRQHandler() { + //asm("csrs mip, %0"::"r"(MIP_MTIP)); + + port_systick_config(k_cpu_cycle_per_tick); +#if 1 + if(tos_knl_is_running()) { + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); + } +#endif +} + +void cpu_irq_entry(cpu_data_t irq, cpu_context_t *regs) +{ + void (*irq_handler)(); + extern void (*handler_vector_table[])(); + + irq_handler = handler_vector_table[irq]; + if((*irq_handler) == 0) { + return; + } + + (*irq_handler)(); +} + +__API__ uint32_t tos_cpu_clz(uint32_t val) +{ + uint32_t nbr_lead_zeros = 0; + + if (!(val & 0XFFFF0000)) { + val <<= 16; + nbr_lead_zeros += 16; + } + + if (!(val & 0XFF000000)) { + val <<= 8; + nbr_lead_zeros += 8; + } + + if (!(val & 0XF0000000)) { + val <<= 4; + nbr_lead_zeros += 4; + } + + if (!(val & 0XC0000000)) { + val <<= 2; + nbr_lead_zeros += 2; + } + + if (!(val & 0X80000000)) { + nbr_lead_zeros += 1; + } + + if (!val) { + nbr_lead_zeros += 1; + } + + return (nbr_lead_zeros); +} diff --git a/arch/risc-v/common/tos_cpu.h b/arch/risc-v/common/tos_cpu.h new file mode 100644 index 00000000..ee39a3a4 --- /dev/null +++ b/arch/risc-v/common/tos_cpu.h @@ -0,0 +1,118 @@ +#ifndef _TOS_CPU_H_ +#define _TOS_CPU_H_ + + +typedef struct cpu_context_st { + cpu_data_t epc; + cpu_data_t mstatus; + union { cpu_data_t x1, ra; }; + union { cpu_data_t x3, gp; }; + union { cpu_data_t x4, tp; }; + union { cpu_data_t x5, t0; }; + union { cpu_data_t x6, t1; }; + union { cpu_data_t x7, t2; }; + union { cpu_data_t x8, s0, fp; }; + union { cpu_data_t x9, s1; }; + union { cpu_data_t x10, a0; }; + union { cpu_data_t x11, a1; }; + union { cpu_data_t x12, a2; }; + union { cpu_data_t x13, a3; }; + union { cpu_data_t x14, a4; }; + union { cpu_data_t x15, a5; }; + union { cpu_data_t x16, a6; }; + union { cpu_data_t x17, a7; }; + union { cpu_data_t x18, s2; }; + union { cpu_data_t x19, s3; }; + union { cpu_data_t x20, s4; }; + union { cpu_data_t x21, s5; }; + union { cpu_data_t x22, s6; }; + union { cpu_data_t x23, s7; }; + union { cpu_data_t x24, s8; }; + union { cpu_data_t x25, s9; }; + union { cpu_data_t x26, s10; }; + union { cpu_data_t x27, s11; }; + union { cpu_data_t x28, t3; }; + union { cpu_data_t x29, t4; }; + union { cpu_data_t x30, t5; }; + union { cpu_data_t x31, t6; }; +} cpu_context_t; + +__API__ uint32_t tos_cpu_clz(uint32_t val); + +__API__ void tos_cpu_int_disable(void); + +__API__ void tos_cpu_int_enable(void); + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void); + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr); + + +__KERNEL__ void cpu_init(void); + +__KERNEL__ void cpu_reset(void); + +__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); + +__KERNEL__ void cpu_sched_start(void); + +__KERNEL__ void cpu_context_switch(void); + +__KERNEL__ void cpu_irq_context_switch(void); + +__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size); + +#if TOS_CFG_TICKLESS_EN > 0u + +__KERNEL__ void cpu_systick_resume(void); + +__KERNEL__ void cpu_systick_suspend(void); + +__KERNEL__ void cpu_systick_reload_reset(void); + +__KERNEL__ void cpu_systick_pending_reset(void); + +__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); + +__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); + +__KERNEL__ void cpu_systick_reset(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__KERNEL__ void cpu_sleep_mode_enter(void); + +__KERNEL__ void cpu_stop_mode_enter(void); + +__KERNEL__ void cpu_standby_mode_enter(void); + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +#error "unsupport now" + +#endif + +/* Allocates CPU status register word. */ +#define TOS_CPU_CPSR_ALLOC() cpu_cpsr_t cpu_cpsr = (cpu_cpsr_t)0u + +/* Save CPU status word & disable interrupts.*/ +#define TOS_CPU_INT_DISABLE() \ + do { \ + cpu_cpsr = tos_cpu_cpsr_save(); \ + } while (0) + +/* Restore CPU status word. */ +#define TOS_CPU_INT_ENABLE() \ + do { \ + tos_cpu_cpsr_restore(cpu_cpsr); \ + } while (0) + +#endif /* _TOS_CPU_H_ */ diff --git a/arch/risc-v/common/tos_cpu_def.h b/arch/risc-v/common/tos_cpu_def.h new file mode 100644 index 00000000..c603da9b --- /dev/null +++ b/arch/risc-v/common/tos_cpu_def.h @@ -0,0 +1,23 @@ +/* + * tos_cpu_def.h + * + * Created on: Sep 7, 2019 + * Author: ace + */ + +#ifndef _TOS_CPU_DEF_H_ +#define _TOS_CPU_DEF_H_ + +enum CPU_WORD_SIZE { + CPU_WORD_SIZE_08, + CPU_WORD_SIZE_16, + CPU_WORD_SIZE_32, + CPU_WORD_SIZE_64, +}; + +enum CPU_STK_GROWTH { + CPU_STK_GROWTH_ASCENDING, + CPU_STK_GROWTH_DESCENDING, +}; + +#endif /* _TOS_CPU_DEF_H_ */ diff --git a/arch/risc-v/common/tos_cpu_types.h b/arch/risc-v/common/tos_cpu_types.h new file mode 100644 index 00000000..a3f9285d --- /dev/null +++ b/arch/risc-v/common/tos_cpu_types.h @@ -0,0 +1,46 @@ +/* + * tos_cpu_types.h + * + * Created on: Sep 7, 2019 + * Author: ace + */ + +#ifndef _TOS_CPU_TYPES_H_ +#define _TOS_CPU_TYPES_H_ + +/* CPU address type based on address bus size. */ +#if (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_addr_t; +#elif (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_addr_t; +#else +typedef uint8_t cpu_addr_t; +#endif + +/* CPU data type based on data bus size. */ +#if (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_data_t; +#elif (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_data_t; +#else +typedef uint8_t cpu_data_t; +#endif + +#if (TOS_CFG_CPU_HRTIMER_EN > 0) +#if (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_08) +typedef uint8_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_64) +typedef uint64_t cpu_hrtimer_t; +#else +typedef uint32_t cpu_hrtimer_t; +#endif +#else +typedef uint32_t cpu_hrtimer_t; +#endif + +//typedef cpu_addr_t size_t; +typedef cpu_addr_t cpu_cpsr_t; + +#endif diff --git a/arch/risc-v/common/tos_fault.h b/arch/risc-v/common/tos_fault.h new file mode 100644 index 00000000..5b9d34b2 --- /dev/null +++ b/arch/risc-v/common/tos_fault.h @@ -0,0 +1,10 @@ +#ifndef _TOS_FAULT_H_ +#define _TOS_FAULT_H_ + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +#error "unsupport now" + +#endif + +#endif /* _TOS_FAULT_H_ */ diff --git a/arch/risc-v/rv32i/port.h b/arch/risc-v/rv32i/port.h new file mode 100644 index 00000000..a3da86ea --- /dev/null +++ b/arch/risc-v/rv32i/port.h @@ -0,0 +1,72 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_H_ +#define _PORT_H_ + +__PORT__ void port_int_disable(void); + +__PORT__ void port_int_enable(void); + +__PORT__ cpu_cpsr_t port_cpsr_save(void); + +__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); + +__PORT__ void port_cpu_reset(void); + +__PORT__ void port_sched_start(void) __NO_RETURN__; + +__PORT__ void port_context_switch(void); + +__PORT__ void port_irq_context_switch(void); + +__PORT__ void port_systick_config(uint32_t cycle_per_tick); + +__PORT__ void port_systick_priority_set(uint32_t prio); + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ void port_systick_resume(void); + +__PORT__ void port_systick_suspend(void); + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick); + +__PORT__ void port_systick_pending_reset(void); + +__PORT__ k_time_t port_systick_max_delay_millisecond(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void); + +__PORT__ void port_stop_mode_enter(void); + +__PORT__ void port_standby_mode_enter(void); + +#endif + + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +__PORT__ void HardFault_Handler(void); + +__PORT__ void port_fault_diagnosis(void); +#endif + +#endif /* _PORT_H_ */ diff --git a/arch/risc-v/rv32i/port_c.c b/arch/risc-v/rv32i/port_c.c new file mode 100644 index 00000000..7de9ed61 --- /dev/null +++ b/arch/risc-v/rv32i/port_c.c @@ -0,0 +1,148 @@ +/* + * port_c.c + * + * Created on: Sep 9, 2019 + * Author: ace + */ +#include "riscv_encoding.h" +#include +#define CLINT_CTRL_ADDR 0x2000000 +#define CLINT_MSIP 0x0000 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIME 0xBFF8 + + +static uint32_t mtime_lo(void) +{ + return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME); +} + + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_mtime_val() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + uint32_t nhi = mtime_hi(); + if (hi == nhi) { + return (((uint64_t)hi) << 32) | lo; + } { + uint32_t a = hi; + uint32_t b = nhi; + } + } +} + +void set_mtimecmp_lo(uint32_t v) +{ + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP) = v; +} + +void set_mtimecmp_hi(uint32_t v) +{ + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = v; +} + +void set_mtimecmp_val(uint64_t v) +{ + uint32_t hi = (v >> 32) & 0xFFFFFFFF; + uint32_t lo = (v >> 0) & 0xFFFFFFFF; + set_mtimecmp_lo(0xFFFFFFFF); // No smaller than old value. + set_mtimecmp_hi(hi); // No smaller than new value. + set_mtimecmp_lo(lo); // New value. +} + + + +__PORT__ void port_systick_config(uint32_t cycle_per_tick) +{ +#if 0 + asm("csrc mie, %0"::"r"(MIP_MTIP)); + +#if 1 + uint64_t mtime = get_mtime_val(); +#else + static uint64_t last_mtime = 0; + if(last_mtime == 0) { + last_mtime = get_mtime_val(); + } + uint64_t mtime = get_mtime_val(); + if((mtime - last_mtime)/cycle_per_tick >= 4) { + mtime = last_mtime+2*cycle_per_tick; + } + last_mtime = mtime; +#endif + uint64_t mtimecmp; + do { + tick_inc(); + mtimecmp = ((uint64_t)tos_get_tick())* cycle_per_tick; + } while(mtimecmp <= mtime); + + set_mtimecmp_val(mtimecmp); + + asm("csrs mie, %0"::"r"(MIP_MTIP)); +#endif +#if 0 + clear_csr(mie, MIP_MTIP); + static uint64_t then = 0; + + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + if(then != 0) { + //next timer irq is 1 second from previous + then += 1*cycle_per_tick; + } else{ //first time setting the timer + uint64_t now = *mtime; + then = now + 1*cycle_per_tick; + } + *mtimecmp = then; + + set_csr(mie, MIP_MTIP); +#endif + //asm("csrc mie, %0"::"r"(MIP_MTIP)); +#if 0 + uint64_t next_tick = get_mtime_val(); + next_tick += cycle_per_tick; + set_mtimecmp_val(next_tick); +#endif + +#if 0 + uint64_t new_tick = get_mtime_val() + cycle_per_tick; + uint64_t tick = 0; + if(new_tick - next_tick > 50000) { + tick = get_mtime_val() + cycle_per_tick; + } + next_tick = new_tick; + set_mtimecmp_val(next_tick); +#endif + +#if 1 + // this is illegal in ricsv-32 + // it cost cpu read two times, first mtime_lo and then mtime_hi + // if mtime_lo == 0xFFFFFFFF and mtime_hi = 0 at first read + // then mtime_lo == 0 and mtime_hi = 1 at next read + // the result will be 0x1FFFFFFFF, not 0x100000000 + //*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF; + //*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF; + + uint64_t mtime = *(volatile uint64_t *)(CLINT_CTRL_ADDR + CLINT_MTIME); + + mtime += cycle_per_tick; + + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = (mtime >> 32) & 0xFFFFFFFF; + asm("csrc mip, %0"::"r"(MIP_MTIP)); + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = (mtime >> 0) & 0xFFFFFFFF; + //asm("csrc mip, %0"::"r"(MIP_MTIP)); +#endif + //asm("csrs mie, %0"::"r"(MIP_MTIP)); +} + +__PORT__ void port_systick_priority_set(uint32_t prio) +{ + //NVIC_SetPriority(SysTick_IRQn, prio); +} diff --git a/arch/risc-v/rv32i/port_config.h b/arch/risc-v/rv32i/port_config.h new file mode 100644 index 00000000..9a8a5e2b --- /dev/null +++ b/arch/risc-v/rv32i/port_config.h @@ -0,0 +1,27 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_CONFIG_H_ +#define _PORT_CONFIG_H_ + +#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING +#define TOS_CFG_CPU_HRTIMER_EN 0u +#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u + +#endif /* _PORT_CONFIG_H_ */ diff --git a/arch/risc-v/rv32i/port_s.S b/arch/risc-v/rv32i/port_s.S new file mode 100644 index 00000000..f29c0e9b --- /dev/null +++ b/arch/risc-v/rv32i/port_s.S @@ -0,0 +1,407 @@ +.global port_int_disable +.global port_int_enable + +.global port_cpsr_save +.global port_cpsr_restore + +.global port_sched_start +.global port_context_switch +.global port_irq_context_switch + +#include "riscv_encoding.h" + +.text +.align 2 + +.type port_int_disable, %function +port_int_disable: + csrci mstatus, MSTATUS_MIE + ret + +.type port_int_enable, %function +port_int_enable: + csrsi mstatus, MSTATUS_MIE + ret + +.type port_cpsr_save, %function +port_cpsr_save: + csrrci a0, mstatus, MSTATUS_MIE + #csrrci a0, mstatus, MSTATUS_MPIE + ret + +.type port_cpsr_restore, %function +port_cpsr_restore: + csrw mstatus, a0 + ret + + +#define REGBYTES 4 +#define LOAD lw +#define STORE sw +.extern k_curr_task +.type port_sched_start, %function +port_sched_start: + // enable timer interrupt + li t0, MIE_MTIE + csrs mie, t0 + + la t0, k_curr_task // t0 = &k_curr_task + LOAD t0, (t0) // t0 = &(k_curr_task->sp) + LOAD sp, (t0) // k_curr_task->sp = sp + + // save sp + addi t1, sp, 32*REGBYTES + STORE t1, (t0) + + LOAD t0, 0*REGBYTES(sp) + csrw mepc, t0 + + LOAD t0, 1*REGBYTES(sp) + csrw mstatus, t0 + + LOAD x1, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + + mret + +.align 2 +.global machine_trap_entry +machine_trap_entry: + addi sp, sp, -32*REGBYTES + STORE x1, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + +#if 1 + //li t0, MSTATUS_MPP | MSTATUS_MPIE // acutally MPIE is not need + csrr t0, mstatus + STORE t0, 1*REGBYTES(sp) + + csrr t0, mepc // just save information for handler + STORE t0, 0*REGBYTES(sp) + + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + LOAD t1, (t0) + STORE sp, (t1) + + csrr a0, mcause + mv a1, sp + bltz a0, irq + call cpu_trap_entry + j restore +irq: + slli a0, a0, 1 + srli a0, a0, 1 + call cpu_irq_entry +restore: + LOAD t0, 0*REGBYTES(sp) + csrw mepc, t0 + + LOAD t0, 1*REGBYTES(sp) + csrw mstatus, t0 +#else + // for debug timer interrupt only + csrr a0, mcause + slli a0, a0, 1 + srli a0, a0, 1 + call cpu_irq_entry +#endif + LOAD x1, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + + mret + + +.align 2 +.type port_context_switch, %function +port_context_switch: + nop + nop + addi sp, sp, -32*REGBYTES + STORE x1, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + + li t0, MSTATUS_MPP // force use machine mode + csrr t1, mstatus + and t1, t1, MSTATUS_MIE + beqz t1, save_mstatus + or t0, t0, MSTATUS_MPIE +save_mstatus: + STORE t0, 1*REGBYTES(sp) + la t0, port_context_switch_return // just save information for handler + STORE t0, 0*REGBYTES(sp) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + LOAD t1, (t0) + STORE sp, (t1) + + // k_curr_task = k_next_task + la t1, k_next_task // t1 = &k_next_task + LOAD t1, (t1) // t1 = k_next_task + STORE t1, (t0) + + // load sp from k_next_task.sp + LOAD sp, (t1) + + LOAD t0, 0*REGBYTES(sp) + csrw mepc, t0 + + LOAD t0, 1*REGBYTES(sp) + csrw mstatus, t0 + + LOAD x1, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + + mret + +.align 2 +port_context_switch_return: + ret + + +.align 2 +.type port_irq_context_switch, %function +port_irq_context_switch: + addi sp, sp, -32*REGBYTES + STORE x1, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + + li t0, MSTATUS_MPP + STORE t0, 1*REGBYTES(sp) + la t0, irq_context_return + STORE t0, 0*REGBYTES(sp) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + LOAD t1, (t0) + STORE sp, (t1) + + // k_curr_task = k_next_task + la t1, k_next_task // t1 = &k_next_task + LOAD t1, (t1) // t1 = k_next_task + STORE t1, (t0) + + // load sp from k_next_task.sp + LOAD sp, (t1) + + LOAD t0, 1*REGBYTES(sp) + csrw mstatus, t0 + + LOAD t0, 0*REGBYTES(sp) + csrw mepc, t0 + + LOAD x1, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + + addi sp, sp, 32*REGBYTES + + mret + + +irq_context_return: + ret diff --git a/arch/risc-v/rv32i/start.S b/arch/risc-v/rv32i/start.S new file mode 100644 index 00000000..556b8333 --- /dev/null +++ b/arch/risc-v/rv32i/start.S @@ -0,0 +1,209 @@ +// See LICENSE for license details. + +#include "riscv_encoding.h" + +.section .text.entry + .globl _start + .type _start,@function +_start: + csrc mstatus, MSTATUS_MIE + csrw mie, 0 + + la t0, machine_trap_entry + csrw mtvec, t0 +#if 1 + // before kernel run, the stack is unused + // so just borrow to use + la t0, k_idle_task_stk_addr + lw t1, k_idle_task_stk_size + add sp, t0, t1 +#else + // uncomment in link.ld + la sp, _stack_top +#endif + + /* Load data section */ + la a0, _load_data + la a1, _data + la a2, _edata + bgeu a1, a2, begin_clear_bss +clear_data: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, clear_data + +begin_clear_bss: + // clear bss section + la a0, _bss + la a1, _ebss + bgeu a0, a1, init_finish +clear_bss: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, clear_bss +init_finish: + call main +__die: + j __die + + + +.section .text + .weak eclic_msip_handler + .weak eclic_mtip_handler + .weak SysTick_IRQHandler + .weak eclic_bwei_handler + .weak eclic_pmovi_handler + .weak WWDGT_IRQHandler + .weak LVD_IRQHandler + .weak TAMPER_IRQHandler + .weak RTC_IRQHandler + .weak FMC_IRQHandler + .weak RCU_IRQHandler + .weak EXTI0_IRQHandler + .weak EXTI1_IRQHandler + .weak EXTI2_IRQHandler + .weak EXTI3_IRQHandler + .weak EXTI4_IRQHandler + .weak DMA0_Channel0_IRQHandler + .weak DMA0_Channel1_IRQHandler + .weak DMA0_Channel2_IRQHandler + .weak DMA0_Channel3_IRQHandler + .weak DMA0_Channel4_IRQHandler + .weak DMA0_Channel5_IRQHandler + .weak DMA0_Channel6_IRQHandler + .weak ADC0_1_IRQHandler + .weak CAN0_TX_IRQHandler + .weak CAN0_RX0_IRQHandler + .weak CAN0_RX1_IRQHandler + .weak CAN0_EWMC_IRQHandler + .weak EXTI5_9_IRQHandler + .weak TIMER0_BRK_IRQHandler + .weak TIMER0_UP_IRQHandler + .weak TIMER0_TRG_CMT_IRQHandler + .weak TIMER0_Channel_IRQHandler + .weak TIMER1_IRQHandler + .weak TIMER2_IRQHandler + .weak TIMER3_IRQHandler + .weak I2C0_EV_IRQHandler + .weak I2C0_ER_IRQHandler + .weak I2C1_EV_IRQHandler + .weak I2C1_ER_IRQHandler + .weak SPI0_IRQHandler + .weak SPI1_IRQHandler + .weak USART0_IRQHandler + .weak USART1_IRQHandler + .weak USART2_IRQHandler + .weak EXTI10_15_IRQHandler + .weak RTC_Alarm_IRQHandler + .weak USBFS_WKUP_IRQHandler + .weak EXMC_IRQHandler + .weak TIMER4_IRQHandler + .weak SPI2_IRQHandler + .weak UART3_IRQHandler + .weak UART4_IRQHandler + .weak TIMER5_IRQHandler + .weak TIMER6_IRQHandler + .weak DMA1_Channel0_IRQHandler + .weak DMA1_Channel1_IRQHandler + .weak DMA1_Channel2_IRQHandler + .weak DMA1_Channel3_IRQHandler + .weak DMA1_Channel4_IRQHandler + .weak CAN1_TX_IRQHandler + .weak CAN1_RX0_IRQHandler + .weak CAN1_RX1_IRQHandler + .weak CAN1_EWMC_IRQHandler + .weak USBFS_IRQHandler + +.global handler_vector_table +.align 2 +handler_vector_table: + .word 0 + .word 0 + .word 0 + .word eclic_msip_handler + .word 0 + .word 0 + .word 0 + .word SysTick_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word eclic_bwei_handler + .word eclic_pmovi_handler + .word WWDGT_IRQHandler + .word LVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FMC_IRQHandler + .word RCU_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA0_Channel0_IRQHandler + .word DMA0_Channel1_IRQHandler + .word DMA0_Channel2_IRQHandler + .word DMA0_Channel3_IRQHandler + .word DMA0_Channel4_IRQHandler + .word DMA0_Channel5_IRQHandler + .word DMA0_Channel6_IRQHandler + .word ADC0_1_IRQHandler + .word CAN0_TX_IRQHandler + .word CAN0_RX0_IRQHandler + .word CAN0_RX1_IRQHandler + .word CAN0_EWMC_IRQHandler + .word EXTI5_9_IRQHandler + .word TIMER0_BRK_IRQHandler + .word TIMER0_UP_IRQHandler + .word TIMER0_TRG_CMT_IRQHandler + .word TIMER0_Channel_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word TIMER3_IRQHandler + .word I2C0_EV_IRQHandler + .word I2C0_ER_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word SPI0_IRQHandler + .word SPI1_IRQHandler + .word USART0_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word EXTI10_15_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBFS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word EXMC_IRQHandler + .word 0 + .word TIMER4_IRQHandler + .word SPI2_IRQHandler + .word UART3_IRQHandler + .word UART4_IRQHandler + .word TIMER5_IRQHandler + .word TIMER6_IRQHandler + .word DMA1_Channel0_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word 0 + .word 0 + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_EWMC_IRQHandler + .word USBFS_IRQHandler diff --git a/board/QEMU_Spike/eclipse/hello_world/.cproject b/board/QEMU_Spike/eclipse/hello_world/.cproject new file mode 100644 index 00000000..061d67bc --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/.cproject @@ -0,0 +1,436 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/board/QEMU_Spike/eclipse/hello_world/.gitignore b/board/QEMU_Spike/eclipse/hello_world/.gitignore new file mode 100644 index 00000000..3df573fe --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/board/QEMU_Spike/eclipse/hello_world/.project b/board/QEMU_Spike/eclipse/hello_world/.project new file mode 100644 index 00000000..94798340 --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/.project @@ -0,0 +1,53 @@ + + + hello_world + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + TencentOS_tiny + 2 + virtual:/virtual + + + TencentOS_tiny/arch + 2 + virtual:/virtual + + + TencentOS_tiny/kernel + 2 + $%7BPARENT-4-PROJECT_LOC%7D/kernel + + + TencentOS_tiny/osal + 2 + $%7BPARENT-4-PROJECT_LOC%7D/osal + + + TencentOS_tiny/arch/risc-v + 2 + $%7BPARENT-4-PROJECT_LOC%7D/arch/risc-v + + + diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml new file mode 100644 index 00000000..e33f632e --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.cdt.codan.core.prefs b/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..77496f55 --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,75 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No 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+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.qt.core.qtproblem=Warning +org.eclipse.cdt.qt.core.qtproblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>true,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>null} diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.ltk.core.refactoring.prefs b/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.ltk.core.refactoring.prefs new file mode 100644 index 00000000..b196c64a --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.ltk.core.refactoring.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h b/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h new file mode 100644 index 00000000..243b3594 --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h @@ -0,0 +1,55 @@ +/* + * tos_config.h + * + * Created on: Sep 7, 2019 + * Author: ace + */ + +#ifndef INC_TOS_CONFIG_H_ +#define INC_TOS_CONFIG_H_ + +#include "stddef.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u // 配置TencentOS tiny默认支持的最大优先级数量 + +#define TOS_CFG_ROUND_ROBIN_EN 0u // 配置TencentOS tiny的内核是否开启时间片轮转 + +#define TOS_CFG_OBJECT_VERIFY 0u // 配置TencentOS tiny是否校验指针合法 + +#define TOS_CFG_EVENT_EN 1u // TencentOS tiny 事件模块功能宏 + +#define TOS_CFG_MMHEAP_EN 1u // 配置TencentOS tiny是否开启动态内存模块 + +#define TOS_CFG_MMHEAP_POOL_SIZE 8192 // 配置TencentOS tiny动态内存池大小 + +#define TOS_CFG_MUTEX_EN 1u // 配置TencentOS tiny是否开启互斥锁模块 + +#define TOS_CFG_QUEUE_EN 1u // 配置TencentOS tiny是否开启队列模块 + +#define TOS_CFG_TIMER_EN 0u // 配置TencentOS tiny是否开启软件定时器模块 + +#define TOS_CFG_SEM_EN 1u // 配置TencentOS tiny是否开启信号量模块 + +#if (TOS_CFG_QUEUE_EN > 0u) +#define TOS_CFG_MSG_EN 1u +#else +#define TOS_CFG_MSG_EN 0u +#endif + +#define TOS_CFG_MSG_POOL_SIZE 10u // 配置TencentOS tiny消息队列大小 + +#define TOS_CFG_IDLE_TASK_STK_SIZE 512u // 配置TencentOS tiny空闲任务栈大小 + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u // 配置TencentOS tiny的tick频率 + +extern uint32_t SystemCoreClock; +#define TOS_CFG_CPU_CLOCK (SystemCoreClock) // 配置TencentOS tiny CPU频率 + +#define TOS_CFG_TIMER_AS_PROC 1u // 配置是否将TIMER配置成函数模式 + +#define TOS_CFG_VFS_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + + +#endif /* INC_TOS_CONFIG_H_ */ diff --git a/board/QEMU_Spike/eclipse/hello_world/Src/main.c b/board/QEMU_Spike/eclipse/hello_world/Src/main.c new file mode 100644 index 00000000..24497aa8 --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/Src/main.c @@ -0,0 +1,97 @@ +/* + * main.c + * + * Created on: Sep 13, 2019 + * Author: ace + */ + +#include "tos.h" +#include "riscv_encoding.h" + +#define RISCV_MSTATUS_MIE (1<<3) /*machine-level interrupt bit*/ +#define RISCV_MSTATUS_MPIE (1<<7) /*machine-level pre interrupt bit*/ +#define RISCV_MSTATUS_MPP (0x3<<10) /*machine-level MPP bit*/ + +#define RISCV_MSTATUS_MPP_MPIE (RISCV_MSTATUS_MPIE | RISCV_MSTATUS_MPP) +void port_sched_start(); +#define STACK_SIZE 512 +char stack[STACK_SIZE]; +void debug_task() { + int idle = 0; + int cnt = 0; + while(1) { + idle++; + cnt++; + } +} + +#include "cmsis_os.h" + +//task1 +#define TASK1_STK_SIZE 512 +void task1(void *pdata); +k_task_t k_task_task1; +uint8_t k_task1_stk[TASK1_STK_SIZE]; +int shit = 123; +void task1(void *pdata) +{ + int c = 0; + while(1) + { + c++; + shit++; + //k_tick_t delay = tos_millisec2tick(10); + //tos_task_delay(delay); + tos_task_yield(); + //osDelay(10); + //asm("wfi;"); + } +} + +void task2(void *pdata); +k_task_t k_task_task2; +uint8_t k_task2_stk[TASK1_STK_SIZE]; +void task2(void *pdata) +{ + int c = 0; + while(1) + { + c--; + shit--; + //osDelay(10); + tos_task_yield(); + asm("wfi;"); + } +} + +uint32_t *stack_sp; + +int main(void) +{ + osKernelInitialize(); +#if 0 + while(1) { + asm("csrs mie, %0"::"r"(MIE_MTIE)); + asm("csrs mstatus, %0"::"r"(MSTATUS_MIE)); + asm("wfi;"); + } +#endif + tos_task_create(&k_task_task1, "task1", task1, NULL, 3, k_task1_stk, TASK1_STK_SIZE, 0); + tos_task_create(&k_task_task2, "task2", task2, NULL, 3, k_task2_stk, TASK1_STK_SIZE, 0); + osKernelStart(); + uint32_t *sp = stack+STACK_SIZE - 4; + sp = (uint32_t*)(((uint32_t)sp) & 0xFFFFFFF0); + + *(sp - 22) = 0x0ACE0ACE; // Reg R0: argument + *(sp - 30) = 0x1234ABCD; // ra + *(sp - 31) = debug_task; + *(sp - 32) = RISCV_MSTATUS_MPIE | RISCV_MSTATUS_MPP; + sp -= 32; + stack_sp = sp; + port_sched_start(); + int c = 0; + while(1) { + c++; + } + +} diff --git a/board/QEMU_Spike/eclipse/hello_world/link.ld b/board/QEMU_Spike/eclipse/hello_world/link.ld new file mode 100644 index 00000000..63201721 --- /dev/null +++ b/board/QEMU_Spike/eclipse/hello_world/link.ld @@ -0,0 +1,52 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY( _start ) + +MEMORY +{ + ROM (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K + RAM (wxa!ri) : ORIGIN = 0x84000000, LENGTH = 128K +} + +SECTIONS +{ + .text : { + PROVIDE( _text = . ); + *(.text.entry) + *(.text) + *(.rodata) + PROVIDE( _etext = . ); + } >ROM AT>ROM + + . = ALIGN(4); + _load_data = LOADADDR(.data); + + . = ALIGN(4); + .data : { + PROVIDE( _data = . ); + *(.data) + . = ALIGN(4); + } >RAM AT>ROM + . = ALIGN(4); + PROVIDE( _edata = . ); + + . = ALIGN(0x1000); + PROVIDE( _bss = . ); + .bss : { + *(.bss) + } >RAM AT>RAM + . = ALIGN(4); + PROVIDE( _ebss = . ); + + + . = ALIGN(8); + PROVIDE( end = . ); + + /* + _stack_size = 256; + .stack ORIGIN(RAM) + LENGTH(RAM) - _stack_size : + { + . = _stack_size; + PROVIDE( _stack_top = . ); + } >RAM AT>RAM + */ +} \ No newline at end of file From ad72fb73d281efab6c27e7b9ea466c9483fc45a5 Mon Sep 17 00:00:00 2001 From: acezhao Date: Fri, 13 Sep 2019 22:22:49 +0800 Subject: [PATCH 2/5] fix port_systick_config bug --- arch/risc-v/common/riscv_encoding.h | 1226 +---------------- arch/risc-v/common/tos_cpu.c | 19 +- arch/risc-v/rv32i/port_c.c | 139 +- arch/risc-v/rv32i/port_s.S | 26 +- arch/risc-v/rv32i/start.S | 170 +-- .../QEMU_Spike/eclipse/hello_world/.cproject | 2 - board/QEMU_Spike/eclipse/hello_world/.project | 5 - .../.settings/language.settings.xml | 2 +- .../eclipse/hello_world/Inc/tos_config.h | 3 +- .../QEMU_Spike/eclipse/hello_world/Src/main.c | 81 +- board/QEMU_Spike/eclipse/hello_world/link.ld | 4 +- 11 files changed, 83 insertions(+), 1594 deletions(-) diff --git a/arch/risc-v/common/riscv_encoding.h b/arch/risc-v/common/riscv_encoding.h index 07049e68..63644419 100644 --- a/arch/risc-v/common/riscv_encoding.h +++ b/arch/risc-v/common/riscv_encoding.h @@ -1,7 +1,5 @@ -// See LICENSE for license details. - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H +#ifndef _RISCV_CSR_ENCODING_H +#define _RISCV_CSR_ENCODING_H #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -143,1226 +141,6 @@ #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Accessed -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#ifdef __riscv64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_fpu(reg) ({ unsigned long __tmp; \ - asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_fpu(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) - - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - - - - - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse-opcodes */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_HRET 0x20200073 -#define MASK_HRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VM 0x10400073 -#define MASK_SFENCE_VM 0xfff07fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 -#define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 -#define CSR_MIP 0x344 -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f - - -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 - -#define CSR_MCOUNTINHIBIT 0x320 - -#define CSR_MNVEC 0x7C3 - -#define CSR_MTVT2 0x7EC -#define CSR_JALMNXTI 0x7ED -#define CSR_PUSHMCAUSE 0x7EE -#define CSR_PUSHMEPC 0x7EF -#define CSR_PUSHMSUBM 0x7EB - -#define CSR_WFE 0x810 -#define CSR_SLEEPVALUE 0x811 -#define CSR_TXEVT 0x812 - -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MSUBM 0x7c4 - - -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, -MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, -MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, -MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, -MASK_CUSTOM3_RD_RS1_RS2) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) #endif diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c index 5ad1656c..9680fbba 100644 --- a/arch/risc-v/common/tos_cpu.c +++ b/arch/risc-v/common/tos_cpu.c @@ -7,9 +7,6 @@ #include #include -// soc code shoud not put here -#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; __KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { @@ -20,7 +17,6 @@ __KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) __KERNEL__ void cpu_init(void) { k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; cpu_systick_init(k_cpu_cycle_per_tick); - //TODO } __API__ cpu_cpsr_t tos_cpu_cpsr_save(void) @@ -122,27 +118,29 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, void cpu_trap_entry(cpu_data_t cause, cpu_context_t *regs) { - int ddd = cause; while(1) { - ddd++; + // TODO } } void SysTick_IRQHandler() { - //asm("csrs mip, %0"::"r"(MIP_MTIP)); - port_systick_config(k_cpu_cycle_per_tick); -#if 1 if(tos_knl_is_running()) { tos_knl_irq_enter(); tos_tick_handler(); tos_knl_irq_leave(); } -#endif } void cpu_irq_entry(cpu_data_t irq, cpu_context_t *regs) { +#if 1 + if(irq != 7) { + return; + } + + SysTick_IRQHandler(); +#else void (*irq_handler)(); extern void (*handler_vector_table[])(); @@ -152,6 +150,7 @@ void cpu_irq_entry(cpu_data_t irq, cpu_context_t *regs) } (*irq_handler)(); +#endif } __API__ uint32_t tos_cpu_clz(uint32_t val) diff --git a/arch/risc-v/rv32i/port_c.c b/arch/risc-v/rv32i/port_c.c index 7de9ed61..a3d2096d 100644 --- a/arch/risc-v/rv32i/port_c.c +++ b/arch/risc-v/rv32i/port_c.c @@ -6,140 +6,41 @@ */ #include "riscv_encoding.h" #include + #define CLINT_CTRL_ADDR 0x2000000 #define CLINT_MSIP 0x0000 #define CLINT_MTIMECMP 0x4000 #define CLINT_MTIME 0xBFF8 - -static uint32_t mtime_lo(void) -{ - return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME); -} - - -static uint32_t mtime_hi(void) -{ - return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); -} - -uint64_t get_mtime_val() -{ - while (1) { - uint32_t hi = mtime_hi(); - uint32_t lo = mtime_lo(); - uint32_t nhi = mtime_hi(); - if (hi == nhi) { - return (((uint64_t)hi) << 32) | lo; - } { - uint32_t a = hi; - uint32_t b = nhi; - } - } -} - -void set_mtimecmp_lo(uint32_t v) -{ - *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP) = v; -} - -void set_mtimecmp_hi(uint32_t v) -{ - *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = v; -} - -void set_mtimecmp_val(uint64_t v) -{ - uint32_t hi = (v >> 32) & 0xFFFFFFFF; - uint32_t lo = (v >> 0) & 0xFFFFFFFF; - set_mtimecmp_lo(0xFFFFFFFF); // No smaller than old value. - set_mtimecmp_hi(hi); // No smaller than new value. - set_mtimecmp_lo(lo); // New value. -} - - - __PORT__ void port_systick_config(uint32_t cycle_per_tick) { -#if 0 - asm("csrc mie, %0"::"r"(MIP_MTIP)); -#if 1 - uint64_t mtime = get_mtime_val(); -#else - static uint64_t last_mtime = 0; - if(last_mtime == 0) { - last_mtime = get_mtime_val(); - } - uint64_t mtime = get_mtime_val(); - if((mtime - last_mtime)/cycle_per_tick >= 4) { - mtime = last_mtime+2*cycle_per_tick; - } - last_mtime = mtime; -#endif - uint64_t mtimecmp; - do { - tick_inc(); - mtimecmp = ((uint64_t)tos_get_tick())* cycle_per_tick; - } while(mtimecmp <= mtime); - - set_mtimecmp_val(mtimecmp); - - asm("csrs mie, %0"::"r"(MIP_MTIP)); -#endif -#if 0 - clear_csr(mie, MIP_MTIP); - static uint64_t then = 0; - - volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); - volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); - if(then != 0) { - //next timer irq is 1 second from previous - then += 1*cycle_per_tick; - } else{ //first time setting the timer - uint64_t now = *mtime; - then = now + 1*cycle_per_tick; - } - *mtimecmp = then; - - set_csr(mie, MIP_MTIP); -#endif - //asm("csrc mie, %0"::"r"(MIP_MTIP)); -#if 0 - uint64_t next_tick = get_mtime_val(); - next_tick += cycle_per_tick; - set_mtimecmp_val(next_tick); -#endif - -#if 0 - uint64_t new_tick = get_mtime_val() + cycle_per_tick; - uint64_t tick = 0; - if(new_tick - next_tick > 50000) { - tick = get_mtime_val() + cycle_per_tick; - } - next_tick = new_tick; - set_mtimecmp_val(next_tick); -#endif - -#if 1 - // this is illegal in ricsv-32 // it cost cpu read two times, first mtime_lo and then mtime_hi // if mtime_lo == 0xFFFFFFFF and mtime_hi = 0 at first read // then mtime_lo == 0 and mtime_hi = 1 at next read // the result will be 0x1FFFFFFFF, not 0x100000000 - //*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF; - //*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF; + uint64_t mtime = 0; + while(1) { + uint32_t mtime_hi = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); + uint32_t mtime_lo = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 0); + uint32_t mtime_hn = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); + if(mtime_hi == mtime_hn) { + mtime += ((uint64_t)mtime_hi << 32) | mtime_lo; + break; + } + } - uint64_t mtime = *(volatile uint64_t *)(CLINT_CTRL_ADDR + CLINT_MTIME); + // just set mtime to mtimecmp does not accurately reflect the passage of time + // cause some time cost on the path to deal with the interrupt + // so, we need to to fix the value with a multiple of cycle_per_tick + uint64_t tick = mtime / cycle_per_tick; + uint64_t mtimecmp = (tick + 1) * cycle_per_tick; - mtime += cycle_per_tick; - *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = (mtime >> 32) & 0xFFFFFFFF; - asm("csrc mip, %0"::"r"(MIP_MTIP)); - *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = (mtime >> 0) & 0xFFFFFFFF; - //asm("csrc mip, %0"::"r"(MIP_MTIP)); -#endif - //asm("csrs mie, %0"::"r"(MIP_MTIP)); + // write to mtimecmp register + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF; + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF & (mtimecmp >> 32); + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF & (mtimecmp >> 0); } __PORT__ void port_systick_priority_set(uint32_t prio) diff --git a/arch/risc-v/rv32i/port_s.S b/arch/risc-v/rv32i/port_s.S index f29c0e9b..507af6b0 100644 --- a/arch/risc-v/rv32i/port_s.S +++ b/arch/risc-v/rv32i/port_s.S @@ -4,6 +4,10 @@ .global port_cpsr_save .global port_cpsr_restore +.global port_systick_resume +.global port_systick_suspend +.global port_systick_pending_reset + .global port_sched_start .global port_context_switch .global port_irq_context_switch @@ -26,7 +30,6 @@ port_int_enable: .type port_cpsr_save, %function port_cpsr_save: csrrci a0, mstatus, MSTATUS_MIE - #csrrci a0, mstatus, MSTATUS_MPIE ret .type port_cpsr_restore, %function @@ -34,6 +37,25 @@ port_cpsr_restore: csrw mstatus, a0 ret +.type port_systick_resume, %function +port_systick_resume: + li t0, MIE_MTIE + csrs mie, t0 + ret + +.type port_systick_suspend, %function +port_systick_suspend: + li t0, MIE_MTIE + csrc mie, t0 + ret + +.type port_systick_pending_reset, %function +port_systick_pending_reset: + li t0, MIP_MTIP + csrc mip, t0 + ret + + #define REGBYTES 4 #define LOAD lw @@ -405,3 +427,5 @@ port_irq_context_switch: irq_context_return: ret + + diff --git a/arch/risc-v/rv32i/start.S b/arch/risc-v/rv32i/start.S index 556b8333..87d48427 100644 --- a/arch/risc-v/rv32i/start.S +++ b/arch/risc-v/rv32i/start.S @@ -11,16 +11,8 @@ _start: la t0, machine_trap_entry csrw mtvec, t0 -#if 1 - // before kernel run, the stack is unused - // so just borrow to use - la t0, k_idle_task_stk_addr - lw t1, k_idle_task_stk_size - add sp, t0, t1 -#else - // uncomment in link.ld + la sp, _stack_top -#endif /* Load data section */ la a0, _load_data @@ -47,163 +39,3 @@ init_finish: call main __die: j __die - - - -.section .text - .weak eclic_msip_handler - .weak eclic_mtip_handler - .weak SysTick_IRQHandler - .weak eclic_bwei_handler - .weak eclic_pmovi_handler - .weak WWDGT_IRQHandler - .weak LVD_IRQHandler - .weak TAMPER_IRQHandler - .weak RTC_IRQHandler - .weak FMC_IRQHandler - .weak RCU_IRQHandler - .weak EXTI0_IRQHandler - .weak EXTI1_IRQHandler - .weak EXTI2_IRQHandler - .weak EXTI3_IRQHandler - .weak EXTI4_IRQHandler - .weak DMA0_Channel0_IRQHandler - .weak DMA0_Channel1_IRQHandler - .weak DMA0_Channel2_IRQHandler - .weak DMA0_Channel3_IRQHandler - .weak DMA0_Channel4_IRQHandler - .weak DMA0_Channel5_IRQHandler - .weak DMA0_Channel6_IRQHandler - .weak ADC0_1_IRQHandler - .weak CAN0_TX_IRQHandler - .weak CAN0_RX0_IRQHandler - .weak CAN0_RX1_IRQHandler - .weak CAN0_EWMC_IRQHandler - .weak EXTI5_9_IRQHandler - .weak TIMER0_BRK_IRQHandler - .weak TIMER0_UP_IRQHandler - .weak TIMER0_TRG_CMT_IRQHandler - .weak TIMER0_Channel_IRQHandler - .weak TIMER1_IRQHandler - .weak TIMER2_IRQHandler - .weak TIMER3_IRQHandler - .weak I2C0_EV_IRQHandler - .weak I2C0_ER_IRQHandler - .weak I2C1_EV_IRQHandler - .weak I2C1_ER_IRQHandler - .weak SPI0_IRQHandler - .weak SPI1_IRQHandler - .weak USART0_IRQHandler - .weak USART1_IRQHandler - .weak USART2_IRQHandler - .weak EXTI10_15_IRQHandler - .weak RTC_Alarm_IRQHandler - .weak USBFS_WKUP_IRQHandler - .weak EXMC_IRQHandler - .weak TIMER4_IRQHandler - .weak SPI2_IRQHandler - .weak UART3_IRQHandler - .weak UART4_IRQHandler - .weak TIMER5_IRQHandler - .weak TIMER6_IRQHandler - .weak DMA1_Channel0_IRQHandler - .weak DMA1_Channel1_IRQHandler - .weak DMA1_Channel2_IRQHandler - .weak DMA1_Channel3_IRQHandler - .weak DMA1_Channel4_IRQHandler - .weak CAN1_TX_IRQHandler - .weak CAN1_RX0_IRQHandler - .weak CAN1_RX1_IRQHandler - .weak CAN1_EWMC_IRQHandler - .weak USBFS_IRQHandler - -.global handler_vector_table -.align 2 -handler_vector_table: - .word 0 - .word 0 - .word 0 - .word eclic_msip_handler - .word 0 - .word 0 - .word 0 - .word SysTick_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word eclic_bwei_handler - .word eclic_pmovi_handler - .word WWDGT_IRQHandler - .word LVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FMC_IRQHandler - .word RCU_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA0_Channel0_IRQHandler - .word DMA0_Channel1_IRQHandler - .word DMA0_Channel2_IRQHandler - .word DMA0_Channel3_IRQHandler - .word DMA0_Channel4_IRQHandler - .word DMA0_Channel5_IRQHandler - .word DMA0_Channel6_IRQHandler - .word ADC0_1_IRQHandler - .word CAN0_TX_IRQHandler - .word CAN0_RX0_IRQHandler - .word CAN0_RX1_IRQHandler - .word CAN0_EWMC_IRQHandler - .word EXTI5_9_IRQHandler - .word TIMER0_BRK_IRQHandler - .word TIMER0_UP_IRQHandler - .word TIMER0_TRG_CMT_IRQHandler - .word TIMER0_Channel_IRQHandler - .word TIMER1_IRQHandler - .word TIMER2_IRQHandler - .word TIMER3_IRQHandler - .word I2C0_EV_IRQHandler - .word I2C0_ER_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word SPI0_IRQHandler - .word SPI1_IRQHandler - .word USART0_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word EXTI10_15_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBFS_WKUP_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word EXMC_IRQHandler - .word 0 - .word TIMER4_IRQHandler - .word SPI2_IRQHandler - .word UART3_IRQHandler - .word UART4_IRQHandler - .word TIMER5_IRQHandler - .word TIMER6_IRQHandler - .word DMA1_Channel0_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word 0 - .word 0 - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_EWMC_IRQHandler - .word USBFS_IRQHandler diff --git a/board/QEMU_Spike/eclipse/hello_world/.cproject b/board/QEMU_Spike/eclipse/hello_world/.cproject index 061d67bc..5f72b9a4 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.cproject +++ b/board/QEMU_Spike/eclipse/hello_world/.cproject @@ -134,8 +134,6 @@ - - diff --git a/board/QEMU_Spike/eclipse/hello_world/.project b/board/QEMU_Spike/eclipse/hello_world/.project index 94798340..684db511 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.project +++ b/board/QEMU_Spike/eclipse/hello_world/.project @@ -39,11 +39,6 @@ 2 $%7BPARENT-4-PROJECT_LOC%7D/kernel - - TencentOS_tiny/osal - 2 - $%7BPARENT-4-PROJECT_LOC%7D/osal - TencentOS_tiny/arch/risc-v 2 diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml index e33f632e..9bd2bb79 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml +++ b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml @@ -11,7 +11,7 @@ - + diff --git a/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h b/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h index 243b3594..501ec378 100644 --- a/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h +++ b/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h @@ -42,8 +42,7 @@ #define TOS_CFG_CPU_TICK_PER_SECOND 1000u // 配置TencentOS tiny的tick频率 -extern uint32_t SystemCoreClock; -#define TOS_CFG_CPU_CLOCK (SystemCoreClock) // 配置TencentOS tiny CPU频率 +#define TOS_CFG_CPU_CLOCK 108000000 // 配置TencentOS tiny CPU频率 #define TOS_CFG_TIMER_AS_PROC 1u // 配置是否将TIMER配置成函数模式 diff --git a/board/QEMU_Spike/eclipse/hello_world/Src/main.c b/board/QEMU_Spike/eclipse/hello_world/Src/main.c index 24497aa8..406c6e84 100644 --- a/board/QEMU_Spike/eclipse/hello_world/Src/main.c +++ b/board/QEMU_Spike/eclipse/hello_world/Src/main.c @@ -6,40 +6,21 @@ */ #include "tos.h" -#include "riscv_encoding.h" -#define RISCV_MSTATUS_MIE (1<<3) /*machine-level interrupt bit*/ -#define RISCV_MSTATUS_MPIE (1<<7) /*machine-level pre interrupt bit*/ -#define RISCV_MSTATUS_MPP (0x3<<10) /*machine-level MPP bit*/ - -#define RISCV_MSTATUS_MPP_MPIE (RISCV_MSTATUS_MPIE | RISCV_MSTATUS_MPP) -void port_sched_start(); -#define STACK_SIZE 512 -char stack[STACK_SIZE]; -void debug_task() { - int idle = 0; - int cnt = 0; - while(1) { - idle++; - cnt++; - } -} - -#include "cmsis_os.h" - -//task1 -#define TASK1_STK_SIZE 512 -void task1(void *pdata); +#define TASK_SIZE 512 k_task_t k_task_task1; -uint8_t k_task1_stk[TASK1_STK_SIZE]; -int shit = 123; +k_task_t k_task_task2; +uint8_t k_task1_stk[TASK_SIZE]; +uint8_t k_task2_stk[TASK_SIZE]; + +int share = 123; void task1(void *pdata) { - int c = 0; + int t1 = 0; while(1) { - c++; - shit++; + t1++; + share++; //k_tick_t delay = tos_millisec2tick(10); //tos_task_delay(delay); tos_task_yield(); @@ -48,50 +29,34 @@ void task1(void *pdata) } } -void task2(void *pdata); -k_task_t k_task_task2; -uint8_t k_task2_stk[TASK1_STK_SIZE]; void task2(void *pdata) { - int c = 0; + int t2 = 0; while(1) { - c--; - shit--; - //osDelay(10); + t2--; + share--; + //tos_task_delay(10); tos_task_yield(); asm("wfi;"); } } -uint32_t *stack_sp; - int main(void) { - osKernelInitialize(); -#if 0 - while(1) { - asm("csrs mie, %0"::"r"(MIE_MTIE)); - asm("csrs mstatus, %0"::"r"(MSTATUS_MIE)); - asm("wfi;"); - } -#endif - tos_task_create(&k_task_task1, "task1", task1, NULL, 3, k_task1_stk, TASK1_STK_SIZE, 0); - tos_task_create(&k_task_task2, "task2", task2, NULL, 3, k_task2_stk, TASK1_STK_SIZE, 0); - osKernelStart(); - uint32_t *sp = stack+STACK_SIZE - 4; - sp = (uint32_t*)(((uint32_t)sp) & 0xFFFFFFF0); + tos_knl_init(); + + tos_task_create(&k_task_task1, "task1", task1, NULL, 3, k_task1_stk, TASK_SIZE, 0); + tos_task_create(&k_task_task2, "task2", task2, NULL, 3, k_task2_stk, TASK_SIZE, 0); + + tos_knl_start(); + - *(sp - 22) = 0x0ACE0ACE; // Reg R0: argument - *(sp - 30) = 0x1234ABCD; // ra - *(sp - 31) = debug_task; - *(sp - 32) = RISCV_MSTATUS_MPIE | RISCV_MSTATUS_MPP; - sp -= 32; - stack_sp = sp; - port_sched_start(); int c = 0; - while(1) { + while(1) + { c++; + asm("wfi;"); } } diff --git a/board/QEMU_Spike/eclipse/hello_world/link.ld b/board/QEMU_Spike/eclipse/hello_world/link.ld index 63201721..a4e704dd 100644 --- a/board/QEMU_Spike/eclipse/hello_world/link.ld +++ b/board/QEMU_Spike/eclipse/hello_world/link.ld @@ -41,12 +41,10 @@ SECTIONS . = ALIGN(8); PROVIDE( end = . ); - /* - _stack_size = 256; + _stack_size = 128; .stack ORIGIN(RAM) + LENGTH(RAM) - _stack_size : { . = _stack_size; PROVIDE( _stack_top = . ); } >RAM AT>RAM - */ } \ No newline at end of file From de43d4ef0ed48ce522c5af2ed8c300cfdb0b7c1a Mon Sep 17 00:00:00 2001 From: acezhao Date: Sat, 14 Sep 2019 22:15:09 +0800 Subject: [PATCH 3/5] replace multiple instructions with macro SAVE_CONTEXT and RESTORE_CONTEXT --- arch/risc-v/common/tos_cpu.c | 122 ++-- arch/risc-v/common/tos_cpu.h | 64 +-- arch/risc-v/rv32i/port_c.c | 52 +- arch/risc-v/rv32i/port_s.S | 519 ++++++------------ arch/risc-v/rv32i/start.S | 52 +- .../{eclipse/hello_world => }/Src/main.c | 0 .../Inc => TOS-CONFIG}/tos_config.h | 0 .../QEMU_Spike/eclipse/hello_world/.cproject | 18 +- board/QEMU_Spike/eclipse/hello_world/.project | 15 + .../.settings/language.settings.xml | 2 +- 10 files changed, 342 insertions(+), 502 deletions(-) rename board/QEMU_Spike/{eclipse/hello_world => }/Src/main.c (100%) rename board/QEMU_Spike/{eclipse/hello_world/Inc => TOS-CONFIG}/tos_config.h (100%) diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c index 9680fbba..ec7a7ebf 100644 --- a/arch/risc-v/common/tos_cpu.c +++ b/arch/risc-v/common/tos_cpu.c @@ -10,7 +10,7 @@ __KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) { - port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); + port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); port_systick_config(cycle_per_tick); } @@ -48,38 +48,38 @@ __KERNEL__ void cpu_sched_start(void) /* Inx Offset Register -31 124 x31 t6 -32 120 x30 t5 -29 116 x29 t4 -28 112 x28 t3 -27 108 x27 s11 -26 104 x26 s10 -25 100 x25 s9 -24 096 x24 s8 -23 092 x23 s7 -22 088 x22 s6 -21 084 x21 s5 -20 080 x20 s4 -19 076 x19 s3 -18 072 x18 s2 -17 068 x17 a7 -16 064 x16 a6 -15 060 x15 a5 -14 056 x14 a4 -13 052 x13 a3 -12 048 x12 a2 -11 044 x11 a1 -10 040 x10 a0 -09 036 x9 s1 -08 032 x8 s0/fp -07 028 x7 t2 -06 024 x6 t1 -05 020 x5 t0 -04 016 x4 tp -03 012 x3 gp -02 008 x1 ra -01 004 mstatus -00 000 epc +31 124 x31 t6 +32 120 x30 t5 +29 116 x29 t4 +28 112 x28 t3 +27 108 x27 s11 +26 104 x26 s10 +25 100 x25 s9 +24 096 x24 s8 +23 092 x23 s7 +22 088 x22 s6 +21 084 x21 s5 +20 080 x20 s4 +19 076 x19 s3 +18 072 x18 s2 +17 068 x17 a7 +16 064 x16 a6 +15 060 x15 a5 +14 056 x14 a4 +13 052 x13 a3 +12 048 x12 a2 +11 044 x11 a1 +10 040 x10 a0 +09 036 x9 s1 +08 032 x8 s0/fp +07 028 x7 t2 +06 024 x6 t1 +05 020 x5 t0 +04 016 x4 tp +03 012 x3 gp +02 008 x1 ra +01 004 mstatus +00 000 epc */ @@ -89,7 +89,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, k_stack_t *stk_base, size_t stk_size) { - cpu_data_t *sp = 0; + cpu_data_t *sp = 0; cpu_context_t *regs = 0; sp = (cpu_data_t *)&stk_base[stk_size]; @@ -101,16 +101,16 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, #if 1 for(int i=0; i<(sizeof(cpu_context_t)/sizeof(cpu_data_t)); i++) { - #define _V(v) ((unsigned int)((v/10) << 4 | (v % 10))) - *(sp + i) = (_V(i) << 24) | (_V(i) << 16) | (_V(i) << 8) | _V(i); - #undef _V + #define _V(v) ((unsigned int)((v/10) << 4 | (v % 10))) + *(sp + i) = (_V(i) << 24) | (_V(i) << 16) | (_V(i) << 8) | _V(i); + #undef _V } #endif - regs->a0 = (cpu_data_t)arg; // a0: argument - regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address - regs->mstatus = (cpu_data_t)(MSTATUS_MPP | MSTATUS_MPIE); // return to machine mode and enable interrupt - regs->epc = (cpu_data_t)entry; + regs->a0 = (cpu_data_t)arg; // a0: argument + regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address + regs->mstatus = (cpu_data_t)(MSTATUS_MPP | MSTATUS_MPIE); // return to machine mode and enable interrupt + regs->epc = (cpu_data_t)entry; return (k_stack_t*)sp; @@ -118,38 +118,38 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, void cpu_trap_entry(cpu_data_t cause, cpu_context_t *regs) { - while(1) { - // TODO - } + while(1) { + // TODO + } } void SysTick_IRQHandler() { - port_systick_config(k_cpu_cycle_per_tick); - if(tos_knl_is_running()) { - tos_knl_irq_enter(); - tos_tick_handler(); - tos_knl_irq_leave(); - } + port_systick_config(k_cpu_cycle_per_tick); + if(tos_knl_is_running()) { + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); + } } void cpu_irq_entry(cpu_data_t irq, cpu_context_t *regs) { #if 1 - if(irq != 7) { - return; - } + if(irq != 7) { + return; + } - SysTick_IRQHandler(); + SysTick_IRQHandler(); #else - void (*irq_handler)(); - extern void (*handler_vector_table[])(); + void (*irq_handler)(); + extern void (*handler_vector_table[])(); - irq_handler = handler_vector_table[irq]; - if((*irq_handler) == 0) { - return; - } + irq_handler = handler_vector_table[irq]; + if((*irq_handler) == 0) { + return; + } - (*irq_handler)(); + (*irq_handler)(); #endif } diff --git a/arch/risc-v/common/tos_cpu.h b/arch/risc-v/common/tos_cpu.h index ee39a3a4..75695178 100644 --- a/arch/risc-v/common/tos_cpu.h +++ b/arch/risc-v/common/tos_cpu.h @@ -3,38 +3,38 @@ typedef struct cpu_context_st { - cpu_data_t epc; - cpu_data_t mstatus; - union { cpu_data_t x1, ra; }; - union { cpu_data_t x3, gp; }; - union { cpu_data_t x4, tp; }; - union { cpu_data_t x5, t0; }; - union { cpu_data_t x6, t1; }; - union { cpu_data_t x7, t2; }; - union { cpu_data_t x8, s0, fp; }; - union { cpu_data_t x9, s1; }; - union { cpu_data_t x10, a0; }; - union { cpu_data_t x11, a1; }; - union { cpu_data_t x12, a2; }; - union { cpu_data_t x13, a3; }; - union { cpu_data_t x14, a4; }; - union { cpu_data_t x15, a5; }; - union { cpu_data_t x16, a6; }; - union { cpu_data_t x17, a7; }; - union { cpu_data_t x18, s2; }; - union { cpu_data_t x19, s3; }; - union { cpu_data_t x20, s4; }; - union { cpu_data_t x21, s5; }; - union { cpu_data_t x22, s6; }; - union { cpu_data_t x23, s7; }; - union { cpu_data_t x24, s8; }; - union { cpu_data_t x25, s9; }; - union { cpu_data_t x26, s10; }; - union { cpu_data_t x27, s11; }; - union { cpu_data_t x28, t3; }; - union { cpu_data_t x29, t4; }; - union { cpu_data_t x30, t5; }; - union { cpu_data_t x31, t6; }; + cpu_data_t epc; + cpu_data_t mstatus; + union { cpu_data_t x1, ra; }; + union { cpu_data_t x3, gp; }; + union { cpu_data_t x4, tp; }; + union { cpu_data_t x5, t0; }; + union { cpu_data_t x6, t1; }; + union { cpu_data_t x7, t2; }; + union { cpu_data_t x8, s0, fp; }; + union { cpu_data_t x9, s1; }; + union { cpu_data_t x10, a0; }; + union { cpu_data_t x11, a1; }; + union { cpu_data_t x12, a2; }; + union { cpu_data_t x13, a3; }; + union { cpu_data_t x14, a4; }; + union { cpu_data_t x15, a5; }; + union { cpu_data_t x16, a6; }; + union { cpu_data_t x17, a7; }; + union { cpu_data_t x18, s2; }; + union { cpu_data_t x19, s3; }; + union { cpu_data_t x20, s4; }; + union { cpu_data_t x21, s5; }; + union { cpu_data_t x22, s6; }; + union { cpu_data_t x23, s7; }; + union { cpu_data_t x24, s8; }; + union { cpu_data_t x25, s9; }; + union { cpu_data_t x26, s10; }; + union { cpu_data_t x27, s11; }; + union { cpu_data_t x28, t3; }; + union { cpu_data_t x29, t4; }; + union { cpu_data_t x30, t5; }; + union { cpu_data_t x31, t6; }; } cpu_context_t; __API__ uint32_t tos_cpu_clz(uint32_t val); diff --git a/arch/risc-v/rv32i/port_c.c b/arch/risc-v/rv32i/port_c.c index a3d2096d..fcb9958d 100644 --- a/arch/risc-v/rv32i/port_c.c +++ b/arch/risc-v/rv32i/port_c.c @@ -8,39 +8,39 @@ #include #define CLINT_CTRL_ADDR 0x2000000 -#define CLINT_MSIP 0x0000 -#define CLINT_MTIMECMP 0x4000 -#define CLINT_MTIME 0xBFF8 +#define CLINT_MSIP 0x0000 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIME 0xBFF8 __PORT__ void port_systick_config(uint32_t cycle_per_tick) { - // it cost cpu read two times, first mtime_lo and then mtime_hi - // if mtime_lo == 0xFFFFFFFF and mtime_hi = 0 at first read - // then mtime_lo == 0 and mtime_hi = 1 at next read - // the result will be 0x1FFFFFFFF, not 0x100000000 - uint64_t mtime = 0; - while(1) { - uint32_t mtime_hi = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); - uint32_t mtime_lo = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 0); - uint32_t mtime_hn = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); - if(mtime_hi == mtime_hn) { - mtime += ((uint64_t)mtime_hi << 32) | mtime_lo; - break; - } - } + // it cost cpu read two times, first mtime_lo and then mtime_hi + // if mtime_lo == 0xFFFFFFFF and mtime_hi = 0 at first read + // then mtime_lo == 0 and mtime_hi = 1 at next read + // the result will be 0x1FFFFFFFF, not 0x100000000 + uint64_t mtime = 0; + while(1) { + uint32_t mtime_hi = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); + uint32_t mtime_lo = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 0); + uint32_t mtime_hn = *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); + if(mtime_hi == mtime_hn) { + mtime += ((uint64_t)mtime_hi << 32) | mtime_lo; + break; + } + } - // just set mtime to mtimecmp does not accurately reflect the passage of time - // cause some time cost on the path to deal with the interrupt - // so, we need to to fix the value with a multiple of cycle_per_tick - uint64_t tick = mtime / cycle_per_tick; - uint64_t mtimecmp = (tick + 1) * cycle_per_tick; + // just set mtime to mtimecmp does not accurately reflect the passage of time + // cause some time cost on the path to deal with the interrupt + // so, we need to to fix the value with a multiple of cycle_per_tick + uint64_t tick = mtime / cycle_per_tick; + uint64_t mtimecmp = (tick + 1) * cycle_per_tick; - // write to mtimecmp register - *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF; - *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF & (mtimecmp >> 32); - *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF & (mtimecmp >> 0); + // write to mtimecmp register + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF; + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF & (mtimecmp >> 32); + *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF & (mtimecmp >> 0); } __PORT__ void port_systick_priority_set(uint32_t prio) diff --git a/arch/risc-v/rv32i/port_s.S b/arch/risc-v/rv32i/port_s.S index 507af6b0..a7153dc0 100644 --- a/arch/risc-v/rv32i/port_s.S +++ b/arch/risc-v/rv32i/port_s.S @@ -12,6 +12,10 @@ .global port_context_switch .global port_irq_context_switch +.extern k_curr_task +.extern k_next_task + + #include "riscv_encoding.h" .text @@ -19,23 +23,23 @@ .type port_int_disable, %function port_int_disable: - csrci mstatus, MSTATUS_MIE - ret + csrci mstatus, MSTATUS_MIE + ret .type port_int_enable, %function port_int_enable: - csrsi mstatus, MSTATUS_MIE - ret + csrsi mstatus, MSTATUS_MIE + ret .type port_cpsr_save, %function port_cpsr_save: - csrrci a0, mstatus, MSTATUS_MIE - ret + csrrci a0, mstatus, MSTATUS_MIE + ret .type port_cpsr_restore, %function port_cpsr_restore: - csrw mstatus, a0 - ret + csrw mstatus, a0 + ret .type port_systick_resume, %function port_systick_resume: @@ -55,377 +59,200 @@ port_systick_pending_reset: csrc mip, t0 ret +#define REGBYTES 4 +.macro SAVE_CONTEXT + addi sp, sp, -32*REGBYTES + sw x1, 2*REGBYTES(sp) + sw x3, 3*REGBYTES(sp) + sw x4, 4*REGBYTES(sp) + sw x5, 5*REGBYTES(sp) + sw x6, 6*REGBYTES(sp) + sw x7, 7*REGBYTES(sp) + sw x8, 8*REGBYTES(sp) + sw x9, 9*REGBYTES(sp) + sw x10, 10*REGBYTES(sp) + sw x11, 11*REGBYTES(sp) + sw x12, 12*REGBYTES(sp) + sw x13, 13*REGBYTES(sp) + sw x14, 14*REGBYTES(sp) + sw x15, 15*REGBYTES(sp) + sw x16, 16*REGBYTES(sp) + sw x17, 17*REGBYTES(sp) + sw x18, 18*REGBYTES(sp) + sw x19, 19*REGBYTES(sp) + sw x20, 20*REGBYTES(sp) + sw x21, 21*REGBYTES(sp) + sw x22, 22*REGBYTES(sp) + sw x23, 23*REGBYTES(sp) + sw x24, 24*REGBYTES(sp) + sw x25, 25*REGBYTES(sp) + sw x26, 26*REGBYTES(sp) + sw x27, 27*REGBYTES(sp) + sw x28, 28*REGBYTES(sp) + sw x29, 29*REGBYTES(sp) + sw x30, 30*REGBYTES(sp) + sw x31, 31*REGBYTES(sp) +.endm -#define REGBYTES 4 -#define LOAD lw -#define STORE sw -.extern k_curr_task -.type port_sched_start, %function -port_sched_start: - // enable timer interrupt - li t0, MIE_MTIE - csrs mie, t0 +.macro RESTORE_CONTEXT + lw t0, 0*REGBYTES(sp) + csrw mepc, t0 - la t0, k_curr_task // t0 = &k_curr_task - LOAD t0, (t0) // t0 = &(k_curr_task->sp) - LOAD sp, (t0) // k_curr_task->sp = sp + lw t0, 1*REGBYTES(sp) + csrw mstatus, t0 - // save sp - addi t1, sp, 32*REGBYTES - STORE t1, (t0) + lw x1, 2*REGBYTES(sp) + lw x3, 3*REGBYTES(sp) + lw x4, 4*REGBYTES(sp) + lw x5, 5*REGBYTES(sp) + lw x6, 6*REGBYTES(sp) + lw x7, 7*REGBYTES(sp) + lw x8, 8*REGBYTES(sp) + lw x9, 9*REGBYTES(sp) + lw x10, 10*REGBYTES(sp) + lw x11, 11*REGBYTES(sp) + lw x12, 12*REGBYTES(sp) + lw x13, 13*REGBYTES(sp) + lw x14, 14*REGBYTES(sp) + lw x15, 15*REGBYTES(sp) + lw x16, 16*REGBYTES(sp) + lw x17, 17*REGBYTES(sp) + lw x18, 18*REGBYTES(sp) + lw x19, 19*REGBYTES(sp) + lw x20, 20*REGBYTES(sp) + lw x21, 21*REGBYTES(sp) + lw x22, 22*REGBYTES(sp) + lw x23, 23*REGBYTES(sp) + lw x24, 24*REGBYTES(sp) + lw x25, 25*REGBYTES(sp) + lw x26, 26*REGBYTES(sp) + lw x27, 27*REGBYTES(sp) + lw x28, 28*REGBYTES(sp) + lw x29, 29*REGBYTES(sp) + lw x30, 30*REGBYTES(sp) + lw x31, 31*REGBYTES(sp) - LOAD t0, 0*REGBYTES(sp) - csrw mepc, t0 - - LOAD t0, 1*REGBYTES(sp) - csrw mstatus, t0 - - LOAD x1, 2*REGBYTES(sp) - LOAD x3, 3*REGBYTES(sp) - LOAD x4, 4*REGBYTES(sp) - LOAD x5, 5*REGBYTES(sp) - LOAD x6, 6*REGBYTES(sp) - LOAD x7, 7*REGBYTES(sp) - LOAD x8, 8*REGBYTES(sp) - LOAD x9, 9*REGBYTES(sp) - LOAD x10, 10*REGBYTES(sp) - LOAD x11, 11*REGBYTES(sp) - LOAD x12, 12*REGBYTES(sp) - LOAD x13, 13*REGBYTES(sp) - LOAD x14, 14*REGBYTES(sp) - LOAD x15, 15*REGBYTES(sp) - LOAD x16, 16*REGBYTES(sp) - LOAD x17, 17*REGBYTES(sp) - LOAD x18, 18*REGBYTES(sp) - LOAD x19, 19*REGBYTES(sp) - LOAD x20, 20*REGBYTES(sp) - LOAD x21, 21*REGBYTES(sp) - LOAD x22, 22*REGBYTES(sp) - LOAD x23, 23*REGBYTES(sp) - LOAD x24, 24*REGBYTES(sp) - LOAD x25, 25*REGBYTES(sp) - LOAD x26, 26*REGBYTES(sp) - LOAD x27, 27*REGBYTES(sp) - LOAD x28, 28*REGBYTES(sp) - LOAD x29, 29*REGBYTES(sp) - LOAD x30, 30*REGBYTES(sp) - LOAD x31, 31*REGBYTES(sp) - - addi sp, sp, 32*REGBYTES - - mret + addi sp, sp, 32*REGBYTES +.endm .align 2 -.global machine_trap_entry -machine_trap_entry: - addi sp, sp, -32*REGBYTES - STORE x1, 2*REGBYTES(sp) - STORE x3, 3*REGBYTES(sp) - STORE x4, 4*REGBYTES(sp) - STORE x5, 5*REGBYTES(sp) - STORE x6, 6*REGBYTES(sp) - STORE x7, 7*REGBYTES(sp) - STORE x8, 8*REGBYTES(sp) - STORE x9, 9*REGBYTES(sp) - STORE x10, 10*REGBYTES(sp) - STORE x11, 11*REGBYTES(sp) - STORE x12, 12*REGBYTES(sp) - STORE x13, 13*REGBYTES(sp) - STORE x14, 14*REGBYTES(sp) - STORE x15, 15*REGBYTES(sp) - STORE x16, 16*REGBYTES(sp) - STORE x17, 17*REGBYTES(sp) - STORE x18, 18*REGBYTES(sp) - STORE x19, 19*REGBYTES(sp) - STORE x20, 20*REGBYTES(sp) - STORE x21, 21*REGBYTES(sp) - STORE x22, 22*REGBYTES(sp) - STORE x23, 23*REGBYTES(sp) - STORE x24, 24*REGBYTES(sp) - STORE x25, 25*REGBYTES(sp) - STORE x26, 26*REGBYTES(sp) - STORE x27, 27*REGBYTES(sp) - STORE x28, 28*REGBYTES(sp) - STORE x29, 29*REGBYTES(sp) - STORE x30, 30*REGBYTES(sp) - STORE x31, 31*REGBYTES(sp) +context_switch_return: +irq_context_return: + ret -#if 1 - //li t0, MSTATUS_MPP | MSTATUS_MPIE // acutally MPIE is not need - csrr t0, mstatus - STORE t0, 1*REGBYTES(sp) +.align 2 +.type port_sched_start, %function +port_sched_start: + // enable timer interrupt + li t0, MIE_MTIE + csrs mie, t0 - csrr t0, mepc // just save information for handler - STORE t0, 0*REGBYTES(sp) + // load sp from k_curr_task->sp + la t0, k_curr_task // t0 = &k_curr_task + lw t0, (t0) // t0 = &(k_curr_task->sp) + lw sp, (t0) // sp = k_curr_task->sp + // save sp to stack + addi t1, sp, 32*REGBYTES + sw t1, (t0) - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - LOAD t1, (t0) - STORE sp, (t1) + RESTORE_CONTEXT - csrr a0, mcause - mv a1, sp - bltz a0, irq - call cpu_trap_entry - j restore -irq: - slli a0, a0, 1 - srli a0, a0, 1 - call cpu_irq_entry -restore: - LOAD t0, 0*REGBYTES(sp) - csrw mepc, t0 - - LOAD t0, 1*REGBYTES(sp) - csrw mstatus, t0 -#else - // for debug timer interrupt only - csrr a0, mcause - slli a0, a0, 1 - srli a0, a0, 1 - call cpu_irq_entry -#endif - LOAD x1, 2*REGBYTES(sp) - LOAD x3, 3*REGBYTES(sp) - LOAD x4, 4*REGBYTES(sp) - LOAD x5, 5*REGBYTES(sp) - LOAD x6, 6*REGBYTES(sp) - LOAD x7, 7*REGBYTES(sp) - LOAD x8, 8*REGBYTES(sp) - LOAD x9, 9*REGBYTES(sp) - LOAD x10, 10*REGBYTES(sp) - LOAD x11, 11*REGBYTES(sp) - LOAD x12, 12*REGBYTES(sp) - LOAD x13, 13*REGBYTES(sp) - LOAD x14, 14*REGBYTES(sp) - LOAD x15, 15*REGBYTES(sp) - LOAD x16, 16*REGBYTES(sp) - LOAD x17, 17*REGBYTES(sp) - LOAD x18, 18*REGBYTES(sp) - LOAD x19, 19*REGBYTES(sp) - LOAD x20, 20*REGBYTES(sp) - LOAD x21, 21*REGBYTES(sp) - LOAD x22, 22*REGBYTES(sp) - LOAD x23, 23*REGBYTES(sp) - LOAD x24, 24*REGBYTES(sp) - LOAD x25, 25*REGBYTES(sp) - LOAD x26, 26*REGBYTES(sp) - LOAD x27, 27*REGBYTES(sp) - LOAD x28, 28*REGBYTES(sp) - LOAD x29, 29*REGBYTES(sp) - LOAD x30, 30*REGBYTES(sp) - LOAD x31, 31*REGBYTES(sp) - - addi sp, sp, 32*REGBYTES - - mret + mret .align 2 .type port_context_switch, %function port_context_switch: - nop - nop - addi sp, sp, -32*REGBYTES - STORE x1, 2*REGBYTES(sp) - STORE x3, 3*REGBYTES(sp) - STORE x4, 4*REGBYTES(sp) - STORE x5, 5*REGBYTES(sp) - STORE x6, 6*REGBYTES(sp) - STORE x7, 7*REGBYTES(sp) - STORE x8, 8*REGBYTES(sp) - STORE x9, 9*REGBYTES(sp) - STORE x10, 10*REGBYTES(sp) - STORE x11, 11*REGBYTES(sp) - STORE x12, 12*REGBYTES(sp) - STORE x13, 13*REGBYTES(sp) - STORE x14, 14*REGBYTES(sp) - STORE x15, 15*REGBYTES(sp) - STORE x16, 16*REGBYTES(sp) - STORE x17, 17*REGBYTES(sp) - STORE x18, 18*REGBYTES(sp) - STORE x19, 19*REGBYTES(sp) - STORE x20, 20*REGBYTES(sp) - STORE x21, 21*REGBYTES(sp) - STORE x22, 22*REGBYTES(sp) - STORE x23, 23*REGBYTES(sp) - STORE x24, 24*REGBYTES(sp) - STORE x25, 25*REGBYTES(sp) - STORE x26, 26*REGBYTES(sp) - STORE x27, 27*REGBYTES(sp) - STORE x28, 28*REGBYTES(sp) - STORE x29, 29*REGBYTES(sp) - STORE x30, 30*REGBYTES(sp) - STORE x31, 31*REGBYTES(sp) + SAVE_CONTEXT - li t0, MSTATUS_MPP // force use machine mode - csrr t1, mstatus - and t1, t1, MSTATUS_MIE - beqz t1, save_mstatus - or t0, t0, MSTATUS_MPIE -save_mstatus: - STORE t0, 1*REGBYTES(sp) - la t0, port_context_switch_return // just save information for handler - STORE t0, 0*REGBYTES(sp) + // return from port_context_switch as return from a function + la t0, context_switch_return + sw t0, 0*REGBYTES(sp) - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - LOAD t1, (t0) - STORE sp, (t1) + csrr t0, mstatus + li t1, MSTATUS_MPP + or t0, t0, t1 + sw t0, 1*REGBYTES(sp) - // k_curr_task = k_next_task - la t1, k_next_task // t1 = &k_next_task - LOAD t1, (t1) // t1 = k_next_task - STORE t1, (t0) + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) - // load sp from k_next_task.sp - LOAD sp, (t1) + // switch task + // k_curr_task = k_next_task + la t1, k_next_task // t1 = &k_next_task + lw t1, (t1) // t1 = k_next_task + sw t1, (t0) - LOAD t0, 0*REGBYTES(sp) - csrw mepc, t0 + // load new task sp + lw sp, (t1) - LOAD t0, 1*REGBYTES(sp) - csrw mstatus, t0 + RESTORE_CONTEXT - LOAD x1, 2*REGBYTES(sp) - LOAD x3, 3*REGBYTES(sp) - LOAD x4, 4*REGBYTES(sp) - LOAD x5, 5*REGBYTES(sp) - LOAD x6, 6*REGBYTES(sp) - LOAD x7, 7*REGBYTES(sp) - LOAD x8, 8*REGBYTES(sp) - LOAD x9, 9*REGBYTES(sp) - LOAD x10, 10*REGBYTES(sp) - LOAD x11, 11*REGBYTES(sp) - LOAD x12, 12*REGBYTES(sp) - LOAD x13, 13*REGBYTES(sp) - LOAD x14, 14*REGBYTES(sp) - LOAD x15, 15*REGBYTES(sp) - LOAD x16, 16*REGBYTES(sp) - LOAD x17, 17*REGBYTES(sp) - LOAD x18, 18*REGBYTES(sp) - LOAD x19, 19*REGBYTES(sp) - LOAD x20, 20*REGBYTES(sp) - LOAD x21, 21*REGBYTES(sp) - LOAD x22, 22*REGBYTES(sp) - LOAD x23, 23*REGBYTES(sp) - LOAD x24, 24*REGBYTES(sp) - LOAD x25, 25*REGBYTES(sp) - LOAD x26, 26*REGBYTES(sp) - LOAD x27, 27*REGBYTES(sp) - LOAD x28, 28*REGBYTES(sp) - LOAD x29, 29*REGBYTES(sp) - LOAD x30, 30*REGBYTES(sp) - LOAD x31, 31*REGBYTES(sp) - - addi sp, sp, 32*REGBYTES - - mret - -.align 2 -port_context_switch_return: - ret + mret .align 2 .type port_irq_context_switch, %function port_irq_context_switch: - addi sp, sp, -32*REGBYTES - STORE x1, 2*REGBYTES(sp) - STORE x3, 3*REGBYTES(sp) - STORE x4, 4*REGBYTES(sp) - STORE x5, 5*REGBYTES(sp) - STORE x6, 6*REGBYTES(sp) - STORE x7, 7*REGBYTES(sp) - STORE x8, 8*REGBYTES(sp) - STORE x9, 9*REGBYTES(sp) - STORE x10, 10*REGBYTES(sp) - STORE x11, 11*REGBYTES(sp) - STORE x12, 12*REGBYTES(sp) - STORE x13, 13*REGBYTES(sp) - STORE x14, 14*REGBYTES(sp) - STORE x15, 15*REGBYTES(sp) - STORE x16, 16*REGBYTES(sp) - STORE x17, 17*REGBYTES(sp) - STORE x18, 18*REGBYTES(sp) - STORE x19, 19*REGBYTES(sp) - STORE x20, 20*REGBYTES(sp) - STORE x21, 21*REGBYTES(sp) - STORE x22, 22*REGBYTES(sp) - STORE x23, 23*REGBYTES(sp) - STORE x24, 24*REGBYTES(sp) - STORE x25, 25*REGBYTES(sp) - STORE x26, 26*REGBYTES(sp) - STORE x27, 27*REGBYTES(sp) - STORE x28, 28*REGBYTES(sp) - STORE x29, 29*REGBYTES(sp) - STORE x30, 30*REGBYTES(sp) - STORE x31, 31*REGBYTES(sp) - - li t0, MSTATUS_MPP - STORE t0, 1*REGBYTES(sp) - la t0, irq_context_return - STORE t0, 0*REGBYTES(sp) - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - LOAD t1, (t0) - STORE sp, (t1) - - // k_curr_task = k_next_task - la t1, k_next_task // t1 = &k_next_task - LOAD t1, (t1) // t1 = k_next_task - STORE t1, (t0) - - // load sp from k_next_task.sp - LOAD sp, (t1) - - LOAD t0, 1*REGBYTES(sp) - csrw mstatus, t0 - - LOAD t0, 0*REGBYTES(sp) - csrw mepc, t0 - - LOAD x1, 2*REGBYTES(sp) - LOAD x3, 3*REGBYTES(sp) - LOAD x4, 4*REGBYTES(sp) - LOAD x5, 5*REGBYTES(sp) - LOAD x6, 6*REGBYTES(sp) - LOAD x7, 7*REGBYTES(sp) - LOAD x8, 8*REGBYTES(sp) - LOAD x9, 9*REGBYTES(sp) - LOAD x10, 10*REGBYTES(sp) - LOAD x11, 11*REGBYTES(sp) - LOAD x12, 12*REGBYTES(sp) - LOAD x13, 13*REGBYTES(sp) - LOAD x14, 14*REGBYTES(sp) - LOAD x15, 15*REGBYTES(sp) - LOAD x16, 16*REGBYTES(sp) - LOAD x17, 17*REGBYTES(sp) - LOAD x18, 18*REGBYTES(sp) - LOAD x19, 19*REGBYTES(sp) - LOAD x20, 20*REGBYTES(sp) - LOAD x21, 21*REGBYTES(sp) - LOAD x22, 22*REGBYTES(sp) - LOAD x23, 23*REGBYTES(sp) - LOAD x24, 24*REGBYTES(sp) - LOAD x25, 25*REGBYTES(sp) - LOAD x26, 26*REGBYTES(sp) - LOAD x27, 27*REGBYTES(sp) - LOAD x28, 28*REGBYTES(sp) - LOAD x29, 29*REGBYTES(sp) - LOAD x30, 30*REGBYTES(sp) - LOAD x31, 31*REGBYTES(sp) + SAVE_CONTEXT - addi sp, sp, 32*REGBYTES + la t0, irq_context_return + sw t0, 0*REGBYTES(sp) - mret + li t0, MSTATUS_MPP + sw t0, 1*REGBYTES(sp) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) + + // switch task + // k_curr_task = k_next_task + la t1, k_next_task // t1 = &k_next_task + lw t1, (t1) // t1 = k_next_task + sw t1, (t0) + + // load new task sp + lw sp, (t1) + + RESTORE_CONTEXT + + mret -irq_context_return: - ret +.align 2 +.global machine_trap_entry +machine_trap_entry: + SAVE_CONTEXT + csrr t0, mepc + sw t0, 0*REGBYTES(sp) + + csrr t0, mstatus + sw t0, 1*REGBYTES(sp) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) + + csrr a0, mcause + mv a1, sp + bltz a0, irq + call cpu_trap_entry + j restore +irq: + slli a0, a0, 1 + srli a0, a0, 1 + call cpu_irq_entry +restore: + RESTORE_CONTEXT + + mret diff --git a/arch/risc-v/rv32i/start.S b/arch/risc-v/rv32i/start.S index 87d48427..30b04422 100644 --- a/arch/risc-v/rv32i/start.S +++ b/arch/risc-v/rv32i/start.S @@ -3,39 +3,39 @@ #include "riscv_encoding.h" .section .text.entry - .globl _start - .type _start,@function + .globl _start + .type _start,@function _start: - csrc mstatus, MSTATUS_MIE - csrw mie, 0 + csrc mstatus, MSTATUS_MIE + csrw mie, 0 - la t0, machine_trap_entry - csrw mtvec, t0 + la t0, machine_trap_entry + csrw mtvec, t0 - la sp, _stack_top + la sp, _stack_top - /* Load data section */ - la a0, _load_data - la a1, _data - la a2, _edata - bgeu a1, a2, begin_clear_bss + /* Load data section */ + la a0, _load_data + la a1, _data + la a2, _edata + bgeu a1, a2, begin_clear_bss clear_data: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, clear_data + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, clear_data begin_clear_bss: - // clear bss section - la a0, _bss - la a1, _ebss - bgeu a0, a1, init_finish + // clear bss section + la a0, _bss + la a1, _ebss + bgeu a0, a1, init_finish clear_bss: - sw zero, (a0) - addi a0, a0, 4 - bltu a0, a1, clear_bss + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, clear_bss init_finish: - call main + call main __die: - j __die + j __die diff --git a/board/QEMU_Spike/eclipse/hello_world/Src/main.c b/board/QEMU_Spike/Src/main.c similarity index 100% rename from board/QEMU_Spike/eclipse/hello_world/Src/main.c rename to board/QEMU_Spike/Src/main.c diff --git a/board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h b/board/QEMU_Spike/TOS-CONFIG/tos_config.h similarity index 100% rename from board/QEMU_Spike/eclipse/hello_world/Inc/tos_config.h rename to board/QEMU_Spike/TOS-CONFIG/tos_config.h diff --git a/board/QEMU_Spike/eclipse/hello_world/.cproject b/board/QEMU_Spike/eclipse/hello_world/.cproject index 5f72b9a4..ad0ee72b 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.cproject +++ b/board/QEMU_Spike/eclipse/hello_world/.cproject @@ -125,15 +125,17 @@ @@ -211,9 +213,7 @@ - - - + @@ -369,9 +369,7 @@ - - - + diff --git a/board/QEMU_Spike/eclipse/hello_world/.project b/board/QEMU_Spike/eclipse/hello_world/.project index 684db511..1730710c 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.project +++ b/board/QEMU_Spike/eclipse/hello_world/.project @@ -24,6 +24,21 @@ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + Inc + 2 + $%7BPARENT-2-PROJECT_LOC%7D/Inc + + + Src + 2 + $%7BPARENT-2-PROJECT_LOC%7D/Src + + + TOS-CONFIG + 2 + $%7BPARENT-2-PROJECT_LOC%7D/TOS-CONFIG + TencentOS_tiny 2 diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml index 9bd2bb79..96b0cb0d 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml +++ b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml @@ -11,7 +11,7 @@ - + From 262dbe0b56d7db04f27e91f2957dbf329fe58dbe Mon Sep 17 00:00:00 2001 From: acezhao Date: Tue, 17 Sep 2019 22:41:48 +0800 Subject: [PATCH 4/5] move rv32i port code under gcc --- arch/risc-v/rv32i/{ => gcc}/port.h | 0 arch/risc-v/rv32i/{ => gcc}/port_c.c | 0 arch/risc-v/rv32i/{ => gcc}/port_config.h | 0 arch/risc-v/rv32i/{ => gcc}/port_s.S | 0 arch/risc-v/rv32i/{ => gcc}/start.S | 0 board/QEMU_Spike/eclipse/hello_world/.cproject | 4 ++-- .../eclipse/hello_world/.settings/language.settings.xml | 2 +- 7 files changed, 3 insertions(+), 3 deletions(-) rename arch/risc-v/rv32i/{ => gcc}/port.h (100%) rename arch/risc-v/rv32i/{ => gcc}/port_c.c (100%) rename arch/risc-v/rv32i/{ => gcc}/port_config.h (100%) rename arch/risc-v/rv32i/{ => gcc}/port_s.S (100%) rename arch/risc-v/rv32i/{ => gcc}/start.S (100%) diff --git a/arch/risc-v/rv32i/port.h b/arch/risc-v/rv32i/gcc/port.h similarity index 100% rename from arch/risc-v/rv32i/port.h rename to arch/risc-v/rv32i/gcc/port.h diff --git a/arch/risc-v/rv32i/port_c.c b/arch/risc-v/rv32i/gcc/port_c.c similarity index 100% rename from arch/risc-v/rv32i/port_c.c rename to arch/risc-v/rv32i/gcc/port_c.c diff --git a/arch/risc-v/rv32i/port_config.h b/arch/risc-v/rv32i/gcc/port_config.h similarity index 100% rename from arch/risc-v/rv32i/port_config.h rename to arch/risc-v/rv32i/gcc/port_config.h diff --git a/arch/risc-v/rv32i/port_s.S b/arch/risc-v/rv32i/gcc/port_s.S similarity index 100% rename from arch/risc-v/rv32i/port_s.S rename to arch/risc-v/rv32i/gcc/port_s.S diff --git a/arch/risc-v/rv32i/start.S b/arch/risc-v/rv32i/gcc/start.S similarity index 100% rename from arch/risc-v/rv32i/start.S rename to arch/risc-v/rv32i/gcc/start.S diff --git a/board/QEMU_Spike/eclipse/hello_world/.cproject b/board/QEMU_Spike/eclipse/hello_world/.cproject index ad0ee72b..10343617 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.cproject +++ b/board/QEMU_Spike/eclipse/hello_world/.cproject @@ -109,7 +109,7 @@ - + @@ -131,7 +131,7 @@ - + diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml index 96b0cb0d..c13aaae5 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml +++ b/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml @@ -11,7 +11,7 @@ - + From f3212cc924dba07acbcf6a7c628b806b976ab528 Mon Sep 17 00:00:00 2001 From: acezhao Date: Tue, 17 Sep 2019 23:22:28 +0800 Subject: [PATCH 5/5] add gcc demo --- .../common/{ => include}/riscv_encoding.h | 0 arch/risc-v/common/{ => include}/tos_cpu.h | 0 .../risc-v/common/{ => include}/tos_cpu_def.h | 0 .../common/{ => include}/tos_cpu_types.h | 0 arch/risc-v/common/{ => include}/tos_fault.h | 0 board/QEMU_Spike/GCC/demo/Makefile | 193 ++++++++++++++++++ board/QEMU_Spike/GCC/demo/link.ld | 51 +++++ .../gcc => board/QEMU_Spike/GCC/demo}/start.S | 0 .../eclipse/{hello_world => demo}/.cproject | 26 +-- .../eclipse/{hello_world => demo}/.gitignore | 0 .../eclipse/{hello_world => demo}/.project | 2 +- .../.settings/language.settings.xml | 2 +- .../org.eclipse.cdt.codan.core.prefs | 0 .../org.eclipse.ltk.core.refactoring.prefs | 0 .../eclipse/{hello_world => demo}/link.ld | 0 board/QEMU_Spike/eclipse/demo/start.S | 41 ++++ 16 files changed, 300 insertions(+), 15 deletions(-) rename arch/risc-v/common/{ => include}/riscv_encoding.h (100%) rename arch/risc-v/common/{ => include}/tos_cpu.h (100%) rename arch/risc-v/common/{ => include}/tos_cpu_def.h (100%) rename arch/risc-v/common/{ => include}/tos_cpu_types.h (100%) rename arch/risc-v/common/{ => include}/tos_fault.h (100%) create mode 100644 board/QEMU_Spike/GCC/demo/Makefile create mode 100644 board/QEMU_Spike/GCC/demo/link.ld rename {arch/risc-v/rv32i/gcc => board/QEMU_Spike/GCC/demo}/start.S (100%) rename board/QEMU_Spike/eclipse/{hello_world => demo}/.cproject (96%) rename board/QEMU_Spike/eclipse/{hello_world => demo}/.gitignore (100%) rename board/QEMU_Spike/eclipse/{hello_world => demo}/.project (98%) rename board/QEMU_Spike/eclipse/{hello_world => demo}/.settings/language.settings.xml (97%) rename board/QEMU_Spike/eclipse/{hello_world => demo}/.settings/org.eclipse.cdt.codan.core.prefs (100%) rename board/QEMU_Spike/eclipse/{hello_world => demo}/.settings/org.eclipse.ltk.core.refactoring.prefs (100%) rename board/QEMU_Spike/eclipse/{hello_world => demo}/link.ld (100%) create mode 100644 board/QEMU_Spike/eclipse/demo/start.S diff --git a/arch/risc-v/common/riscv_encoding.h b/arch/risc-v/common/include/riscv_encoding.h similarity index 100% rename from arch/risc-v/common/riscv_encoding.h rename to arch/risc-v/common/include/riscv_encoding.h diff --git a/arch/risc-v/common/tos_cpu.h b/arch/risc-v/common/include/tos_cpu.h similarity index 100% rename from arch/risc-v/common/tos_cpu.h rename to arch/risc-v/common/include/tos_cpu.h diff --git a/arch/risc-v/common/tos_cpu_def.h b/arch/risc-v/common/include/tos_cpu_def.h similarity index 100% rename from arch/risc-v/common/tos_cpu_def.h rename to arch/risc-v/common/include/tos_cpu_def.h diff --git a/arch/risc-v/common/tos_cpu_types.h b/arch/risc-v/common/include/tos_cpu_types.h similarity index 100% rename from arch/risc-v/common/tos_cpu_types.h rename to arch/risc-v/common/include/tos_cpu_types.h diff --git a/arch/risc-v/common/tos_fault.h b/arch/risc-v/common/include/tos_fault.h similarity index 100% rename from arch/risc-v/common/tos_fault.h rename to arch/risc-v/common/include/tos_fault.h diff --git a/board/QEMU_Spike/GCC/demo/Makefile b/board/QEMU_Spike/GCC/demo/Makefile new file mode 100644 index 00000000..8b6a96e6 --- /dev/null +++ b/board/QEMU_Spike/GCC/demo/Makefile @@ -0,0 +1,193 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.3.0] date: [Mon Aug 05 10:29:11 CST 2019] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = demo + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -O0 + +TOP_DIR = ../../../.. +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +KERNEL_SRC = \ + ${wildcard $(TOP_DIR)/kernel/core/*.c} + C_SOURCES += $(KERNEL_SRC) + +ARCH_SRC = \ + ${wildcard $(TOP_DIR)/arch/risc-v/rv32i/gcc/*.c} \ + ${wildcard $(TOP_DIR)/arch/risc-v/common/*.c} + C_SOURCES += $(ARCH_SRC) + +HAL_DRIVER_SRC = \ + $(TOP_DIR)/board/QEMU_Spike/Src/main.c + C_SOURCES += $(HAL_DRIVER_SRC) + +# ASM sources +ASM_SOURCES = + +ASM_SOURCES_S = \ +$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \ +start.S + + +####################################### +# binaries +####################################### +PREFIX = riscv-none-embed- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -march=rv32imac + +# fpu +FPU = + +# float-abi +FLOAT-ABI = + +# mcu +MCU = $(CPU) $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = + +# AS includes +AS_INCLUDES = + +# C includes +KERNEL_INC = \ + -I $(TOP_DIR)/kernel/core/include \ + -I $(TOP_DIR)/kernel/pm/include \ + -I $(TOP_DIR)/kernel/hal/include \ + -I $(TOP_DIR)/arch/risc-v/common/include \ + -I $(TOP_DIR)/arch/risc-v/rv32i/gcc \ + -I $(TOP_DIR)/board/QEMU_Spike/TOS-CONFIG + C_INCLUDES += $(KERNEL_INC) +CMSIS_INC = + +HAL_DRIVER_INC = \ + -I $(TOP_DIR)/board/QEMU_Spike/Inc \ + C_INCLUDES += $(HAL_DRIVER_INC) + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections -mabi=ilp32 -msmall-data-limit=8 -mno-save-restore + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections -mabi=ilp32 -msmall-data-limit=8 -mno-save-restore -std=gnu11 --specs=nosys.specs -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = link.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -nostartfiles + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES_S:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES_S))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/board/QEMU_Spike/GCC/demo/link.ld b/board/QEMU_Spike/GCC/demo/link.ld new file mode 100644 index 00000000..bc3eb43f --- /dev/null +++ b/board/QEMU_Spike/GCC/demo/link.ld @@ -0,0 +1,51 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY( _start ) + +MEMORY +{ + ROM (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K + RAM (wxa!ri) : ORIGIN = 0x84000000, LENGTH = 128K +} + +SECTIONS +{ + .text : { + PROVIDE( _text = . ); + *(.text.entry) + *(.text) + *(.rodata) + PROVIDE( _etext = . ); + } >ROM AT>ROM + + . = ALIGN(4); + _load_data = LOADADDR(.data); + + . = ALIGN(4); + .data : { + PROVIDE( _data = . ); + *(.data) + . = ALIGN(4); + } >RAM AT>ROM + . = ALIGN(4); + PROVIDE( _edata = . ); + + . = ALIGN(0x1000); + PROVIDE( _bss = . ); + .bss : { + *(.bss) + } >RAM AT>RAM + . = ALIGN(4); + PROVIDE( _ebss = . ); + + + . = ALIGN(8); + PROVIDE( end = . ); + + _stack_size = 128; + .stack ORIGIN(RAM) + LENGTH(RAM) - _stack_size : + { + . = _stack_size; + PROVIDE( _stack_top = . ); + } >RAM AT>RAM + _end = .; +} diff --git a/arch/risc-v/rv32i/gcc/start.S b/board/QEMU_Spike/GCC/demo/start.S similarity index 100% rename from arch/risc-v/rv32i/gcc/start.S rename to board/QEMU_Spike/GCC/demo/start.S diff --git a/board/QEMU_Spike/eclipse/hello_world/.cproject b/board/QEMU_Spike/eclipse/demo/.cproject similarity index 96% rename from board/QEMU_Spike/eclipse/hello_world/.cproject rename to board/QEMU_Spike/eclipse/demo/.cproject index 10343617..895eea06 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.cproject +++ b/board/QEMU_Spike/eclipse/demo/.cproject @@ -97,7 +97,7 @@ - + @@ -107,9 +107,9 @@ @@ -125,17 +125,17 @@ @@ -301,7 +301,7 @@ - + @@ -385,7 +385,7 @@ - + @@ -417,13 +417,13 @@ - + - + diff --git a/board/QEMU_Spike/eclipse/hello_world/.gitignore b/board/QEMU_Spike/eclipse/demo/.gitignore similarity index 100% rename from board/QEMU_Spike/eclipse/hello_world/.gitignore rename to board/QEMU_Spike/eclipse/demo/.gitignore diff --git a/board/QEMU_Spike/eclipse/hello_world/.project b/board/QEMU_Spike/eclipse/demo/.project similarity index 98% rename from board/QEMU_Spike/eclipse/hello_world/.project rename to board/QEMU_Spike/eclipse/demo/.project index 1730710c..dd81e27f 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.project +++ b/board/QEMU_Spike/eclipse/demo/.project @@ -1,6 +1,6 @@ - hello_world + demo diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml b/board/QEMU_Spike/eclipse/demo/.settings/language.settings.xml similarity index 97% rename from board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml rename to board/QEMU_Spike/eclipse/demo/.settings/language.settings.xml index c13aaae5..975049f4 100644 --- a/board/QEMU_Spike/eclipse/hello_world/.settings/language.settings.xml +++ b/board/QEMU_Spike/eclipse/demo/.settings/language.settings.xml @@ -11,7 +11,7 @@ - + diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.cdt.codan.core.prefs b/board/QEMU_Spike/eclipse/demo/.settings/org.eclipse.cdt.codan.core.prefs similarity index 100% rename from board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.cdt.codan.core.prefs rename to board/QEMU_Spike/eclipse/demo/.settings/org.eclipse.cdt.codan.core.prefs diff --git a/board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.ltk.core.refactoring.prefs b/board/QEMU_Spike/eclipse/demo/.settings/org.eclipse.ltk.core.refactoring.prefs similarity index 100% rename from board/QEMU_Spike/eclipse/hello_world/.settings/org.eclipse.ltk.core.refactoring.prefs rename to board/QEMU_Spike/eclipse/demo/.settings/org.eclipse.ltk.core.refactoring.prefs diff --git a/board/QEMU_Spike/eclipse/hello_world/link.ld b/board/QEMU_Spike/eclipse/demo/link.ld similarity index 100% rename from board/QEMU_Spike/eclipse/hello_world/link.ld rename to board/QEMU_Spike/eclipse/demo/link.ld diff --git a/board/QEMU_Spike/eclipse/demo/start.S b/board/QEMU_Spike/eclipse/demo/start.S new file mode 100644 index 00000000..30b04422 --- /dev/null +++ b/board/QEMU_Spike/eclipse/demo/start.S @@ -0,0 +1,41 @@ +// See LICENSE for license details. + +#include "riscv_encoding.h" + +.section .text.entry + .globl _start + .type _start,@function +_start: + csrc mstatus, MSTATUS_MIE + csrw mie, 0 + + la t0, machine_trap_entry + csrw mtvec, t0 + + la sp, _stack_top + + /* Load data section */ + la a0, _load_data + la a1, _data + la a2, _edata + bgeu a1, a2, begin_clear_bss +clear_data: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, clear_data + +begin_clear_bss: + // clear bss section + la a0, _bss + la a1, _ebss + bgeu a0, a1, init_finish +clear_bss: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, clear_bss +init_finish: + call main +__die: + j __die