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iysheng
2022-08-17 16:25:22 +08:00
parent a1fff99aea
commit aaa8e01bdb
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311
arch/arm/arm-v8m/star-mc1/gcc/port.h Normal file
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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _PORT_H_
#define _PORT_H_
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
typedef struct port_fault_regs {
union {
/* System Handler Control and State Register (0xE000ED24) */
uint32_t value;
struct {
/* Read as 1 if memory management fault is active */
uint32_t MEMFAULTACT : 1;
/* Read as 1 if bus fault exception is active */
uint32_t BUSFAULTACT : 1;
uint32_t UnusedBits1 : 1;
/* Read as 1 if usage fault exception is active */
uint32_t USGFAULTACT : 1;
uint32_t UnusedBits2 : 3;
/* Read as 1 if SVC exception is active */
uint32_t SVCALLACT : 1;
/* Read as 1 if debug monitor exception is active */
uint32_t MONITORACT : 1;
uint32_t UnusedBits3 : 1;
/* Read as 1 if PendSV exception is active */
uint32_t PENDSVACT : 1;
/* Read as 1 if SYSTICK exception is active */
uint32_t SYSTICKACT : 1;
/* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
uint32_t USGFAULTPENDED : 1;
/* Memory management fault pended; memory management fault started but was replaced by a
higher-priority exception */
uint32_t MEMFAULTPENDED : 1;
/* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
exception */
uint32_t BUSFAULTPENDED : 1;
/* SVC pended; SVC was started but was replaced by a higher-priority exception */
uint32_t SVCALLPENDED : 1;
/* Memory management fault handler enable */
uint32_t MEMFAULTENA : 1;
/* Bus fault handler enable */
uint32_t BUSFAULTENA : 1;
/* Usage fault handler enable */
uint32_t USGFAULTENA : 1;
} bits;
} syshndctrl;
union {
uint32_t value;
struct {
union {
/* Memory Management Fault Status Register (0xE000ED28) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IACCVIOL : 1;
/* Data access violation */
uint8_t DACCVIOL : 1;
uint8_t UnusedBits : 1;
/* Unstacking error */
uint8_t MUNSTKERR : 1;
/* Stacking error */
uint8_t MSTKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t MLSPERR : 1;
uint8_t UnusedBits2 : 1;
/* Indicates the MMAR is valid */
uint8_t MMARVALID : 1;
} bits;
} mfsr;
union {
/* Bus Fault Status Register (0xE000ED29) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IBUSERR : 1;
/* Precise data access violation */
uint8_t PRECISERR : 1;
/* Imprecise data access violation */
uint8_t IMPREISERR : 1;
/* Unstacking error */
uint8_t UNSTKERR : 1;
/* Stacking error */
uint8_t STKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t LSPERR : 1;
uint8_t UnusedBits : 1;
/* Indicates BFAR is valid */
uint8_t BFARVALID : 1;
} bits;
} bfsr;
union {
/* Usage Fault Status Register (0xE000ED2A) */
uint16_t value;
struct {
/* Attempts to execute an undefined instruction */
uint16_t UNDEFINSTR : 1;
/* Attempts to switch to an invalid state (e.g., ARM) */
uint16_t INVSTATE : 1;
/* Attempts to do an exception with a bad value in the EXC_RETURN number */
uint16_t INVPC : 1;
/* Attempts to execute a coprocessor instruction */
uint16_t NOCP : 1;
uint16_t UnusedBits : 4;
/* Indicates that an unaligned access fault has taken place */
uint16_t UNALIGNED : 1;
/* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
uint16_t DIVBYZERO0 : 1;
} bits;
} ufsr;
} part;
} cfsr;
/* Memory Management Fault Address Register (0xE000ED34) */
uint32_t mmar;
/* Bus Fault Manage Address Register (0xE000ED38) */
uint32_t bfar;
union {
/* Hard Fault Status Register (0xE000ED2C) */
uint32_t value;
struct {
uint32_t UnusedBits : 1;
/* Indicates hard fault is caused by failed vector fetch */
uint32_t VECTBL : 1;
uint32_t UnusedBits2 : 28;
/* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
uint32_t FORCED : 1;
/* Indicates hard fault is triggered by debug event */
uint32_t DEBUGEVT : 1;
} bits;
} hfsr;
union {
/* Debug Fault Status Register (0xE000ED30) */
uint32_t value;
struct {
/* Halt requested in NVIC */
uint32_t HALTED : 1;
/* BKPT instruction executed */
uint32_t BKPT : 1;
/* DWT match occurred */
uint32_t DWTTRAP : 1;
/* Vector fetch occurred */
uint32_t VCATCH : 1;
/* EDBGRQ signal asserted */
uint32_t EXTERNAL : 1;
} bits;
} dfsr;
/* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
uint32_t afsr;
} port_fault_regs_t;
enum fault_info {
FAULT_INFO_ASSERT_ON_THREAD,
FAULT_INFO_HFSR_VECTBL,
FAULT_INFO_MFSR_IACCVIOL,
FAULT_INFO_MFSR_DACCVIOL,
FAULT_INFO_MFSR_MUNSTKERR,
FAULT_INFO_MFSR_MSTKERR,
FAULT_INFO_MFSR_MLSPERR,
FAULT_INFO_BFSR_IBUSERR,
FAULT_INFO_BFSR_PRECISERR,
FAULT_INFO_BFSR_IMPREISERR,
FAULT_INFO_BFSR_UNSTKERR,
FAULT_INFO_BFSR_STKERR,
FAULT_INFO_BFSR_LSPERR,
FAULT_INFO_UFSR_UNDEFINSTR,
FAULT_INFO_UFSR_INVSTATE,
FAULT_INFO_UFSR_INVPC,
FAULT_INFO_UFSR_NOCP,
FAULT_INFO_UFSR_UNALIGNED,
FAULT_INFO_UFSR_DIVBYZERO0,
FAULT_INFO_DFSR_HALTED,
FAULT_INFO_DFSR_BKPT,
FAULT_INFO_DFSR_DWTTRAP,
FAULT_INFO_DFSR_VCATCH,
FAULT_INFO_DFSR_EXTERNAL,
FAULT_INFO_MMAR,
FAULT_INFO_BFAR,
};
static const char *const fault_msg[] = {
[FAULT_INFO_ASSERT_ON_THREAD] = "Assert on thread %s\n",
[FAULT_INFO_HFSR_VECTBL] = "Hard fault is caused by failed vector fetch\n",
[FAULT_INFO_MFSR_IACCVIOL] = "Memory management fault: instruction access violation\n",
[FAULT_INFO_MFSR_DACCVIOL] = "Memory management fault: data access violation\n",
[FAULT_INFO_MFSR_MUNSTKERR] = "Memory management fault: unstacking error\n",
[FAULT_INFO_MFSR_MSTKERR] = "Memory management fault: stacking error\n",
[FAULT_INFO_MFSR_MLSPERR] = "Memory management fault: floating-point lazy state preservation\n",
[FAULT_INFO_BFSR_IBUSERR] = "Bus fault: instruction access violation\n",
[FAULT_INFO_BFSR_PRECISERR] = "Bus fault: precise data access violation\n",
[FAULT_INFO_BFSR_IMPREISERR] = "Bus fault: imprecise data access violation\n",
[FAULT_INFO_BFSR_UNSTKERR] = "Bus fault: unstacking error\n",
[FAULT_INFO_BFSR_STKERR] = "Bus fault: stacking error\n",
[FAULT_INFO_BFSR_LSPERR] = "Bus fault: floating-point lazy state preservation\n",
[FAULT_INFO_UFSR_UNDEFINSTR] = "Usage fault: undefined instruction\n",
[FAULT_INFO_UFSR_INVSTATE] = "Usage fault: invalid state (e.g., ARM)\n",
[FAULT_INFO_UFSR_INVPC] = "Usage fault: invalid EXC_RETURN\n",
[FAULT_INFO_UFSR_NOCP] = "Usage fault: coprocessor instruction\n",
[FAULT_INFO_UFSR_UNALIGNED] = "Usage fault: unaligned access\n",
[FAULT_INFO_UFSR_DIVBYZERO0] = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
[FAULT_INFO_DFSR_HALTED] = "Debug fault: halt requested in NVIC\n",
[FAULT_INFO_DFSR_BKPT] = "Debug fault: BKPT instruction executed\n",
[FAULT_INFO_DFSR_DWTTRAP] = "Debug fault: DWT match occurred\n",
[FAULT_INFO_DFSR_VCATCH] = "Debug fault: Vector fetch occurred\n",
[FAULT_INFO_DFSR_EXTERNAL] = "Debug fault: EDBGRQ signal asserted\n",
[FAULT_INFO_MMAR] = "The memory management fault occurred address is %08x\n",
[FAULT_INFO_BFAR] = "The bus fault occurred address is %08x\n",
};
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
__PORT__ uint32_t port_clz(uint32_t val);
#endif
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#endif /* _PORT_H_ */

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arch/arm/arm-v8m/star-mc1/gcc/port_c.c Normal file
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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "tos_k.h"
#include "core_star.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
(void)SysTick_Config(cycle_per_tick);
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTick_IRQn, prio);
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
port_systick_config(cycle_per_tick);
}
__PORT__ void port_systick_pending_reset(void)
{
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
#if 1
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#endif
}
__PORT__ void port_stop_mode_enter(void)
{
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
HAL_PWR_EnterSTANDBYMode();
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
{
k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
if (regs->hfsr.bits.VECTBL) {
k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
}
if (regs->hfsr.bits.FORCED) {
/* Memory Management Fault */
if (regs->cfsr.part.mfsr.value) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MLSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
}
if (regs->cfsr.part.mfsr.bits.MMARVALID) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
}
}
}
/* Bus Fault */
if (regs->cfsr.part.bfsr.value) {
if (regs->cfsr.part.bfsr.bits.IBUSERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
}
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
}
if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
}
if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
}
if (regs->cfsr.part.bfsr.bits.STKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
}
if (regs->cfsr.part.bfsr.bits.LSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
}
if (regs->cfsr.part.bfsr.bits.BFARVALID) {
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
}
}
}
/* Usage Fault */
if (regs->cfsr.part.ufsr.value) {
if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
}
if (regs->cfsr.part.ufsr.bits.INVSTATE) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
}
if (regs->cfsr.part.ufsr.bits.INVPC) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
}
if (regs->cfsr.part.ufsr.bits.NOCP) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
}
if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
}
if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
}
}
}
/* Debug Fault */
if (regs->hfsr.bits.DEBUGEVT) {
if (regs->dfsr.value) {
if (regs->dfsr.bits.HALTED) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
}
if (regs->dfsr.bits.BKPT) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
}
if (regs->dfsr.bits.DWTTRAP) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
}
if (regs->dfsr.bits.VCATCH) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
}
if (regs->dfsr.bits.EXTERNAL) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
}
}
}
}
__PORT__ void port_fault_diagnosis(void)
{
port_fault_regs_t regs;
regs.syshndctrl.value = SCB->SHCSR;
regs.cfsr.value = SCB->CFSR;
regs.mmar = SCB->MMFAR;
regs.bfar = SCB->BFAR;
regs.hfsr.value = SCB->HFSR;
regs.dfsr.value = SCB->DFSR;
regs.afsr = SCB->AFSR;
port_fault_do_diagnosis(&regs);
}
__PORT__ void __NAKED__ HardFault_Handler(void)
{
__ASM__ __VOLATILE__ (
"MOV r0, lr\n\t"
"TST lr, #0x04\n\t"
"ITE EQ\n\t"
"MRSEQ r1, MSP\n\t"
"MRSNE r1, PSP\n\t"
"BL fault_backtrace\n\t"
);
}
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

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arch/arm/arm-v8m/star-mc1/gcc/port_config.h Normal file
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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 1u
#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
#define TOS_CFG_CPU_ARM_FPU_EN 1u
#else
#define TOS_CFG_CPU_ARM_FPU_EN 0u
#endif
#endif /* _PORT_CONFIG_H_ */

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arch/arm/arm-v8m/star-mc1/gcc/port_s.S Normal file
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.global port_int_disable
.global port_int_enable
.global port_cpsr_save
.global port_cpsr_restore
.global port_sched_start
.global port_context_switch
.global port_irq_context_switch
.global port_clz
.global PendSV_Handler
.extern k_curr_task
.extern k_next_task
.equ SCB_VTOR, 0xE000ED08
.equ NVIC_INT_CTRL, 0xE000ED04
.equ NVIC_SYSPRI14, 0xE000ED22
.equ NVIC_PENDSV_PRI, 0xFF
.equ NVIC_PENDSVSET, 0x10000000
.text
.align 2
.thumb
.syntax unified
.type port_int_disable, %function
port_int_disable:
CPSID I
BX LR
.type port_int_enable, %function
port_int_enable:
CPSIE I
BX LR
.type port_cpsr_save, %function
port_cpsr_save:
MRS R0, PRIMASK
CPSID I
BX LR
.type port_cpsr_restore, %function
port_cpsr_restore:
MSR PRIMASK, R0
BX LR
.type port_clz, %function
port_clz:
CLZ R0, R0
BX LR
.thumb_func
.type port_sched_start, %function
port_sched_start:
CPSID I
@ set pendsv priority lowest
@ otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
@ that would be a disaster
MOVW R0, #:lower16:NVIC_SYSPRI14
MOVT R0, #:upper16:NVIC_SYSPRI14
MOVW R1, #:lower16:NVIC_PENDSV_PRI
MOVT R1, #:upper16:NVIC_PENDSV_PRI
STRB R1, [R0]
MOVW R0, #:lower16:SCB_VTOR
MOVT R0, #:upper16:SCB_VTOR
LDR R0, [R0]
LDR R0, [R0]
MSR MSP, R0
MOVW R0, #:lower16:k_curr_task
MOVT R0, #:upper16:k_curr_task
@ k_curr_task = k_next_task;
MOVW R1, #:lower16:k_next_task
MOVT R1, #:upper16:k_next_task
LDR R2, [R1]
STR R2, [R0]
@ sp = k_next_task->sp
LDR R0, [R2]
@ PSP = sp
MSR PSP, R0
MRS R0, CONTROL
ORR R0, R0, #2
MSR CONTROL, R0
ISB
@ restore r4-11 from new process stack
LDMFD SP!, {R4 - R11}
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@ ignore EXC_RETURN the first switch
LDMFD SP!, {R0}
#endif
@ restore r0, r3
LDMFD SP!, {R0 - R3}
@ load R12 and LR
LDMFD SP!, {R12, LR}
@ load PC and discard xPSR
LDMFD SP!, {R1, R2}
CPSIE I
BX R1
.thumb_func
.type port_context_switch, %function
port_context_switch:
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
.thumb_func
.type port_irq_context_switch, %function
port_irq_context_switch:
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
.thumb_func
.type PendSV_Handler, %function
PendSV_Handler:
CPSID I
MRS R0, PSP
_context_save:
@ R0-R3, R12, LR, PC, xPSR is saved automatically here
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@ is it extended frame?
TST LR, #0x10
IT EQ
VSTMDBEQ R0!, {S16 - S31}
@ S0 - S16, FPSCR saved automatically here
@ save EXC_RETURN
STMFD R0!, {LR}
#endif
@ save remaining regs r4 - 11 on process stack
STMFD R0!, {R4 - R11}
@ k_curr_task->sp = PSP;
MOVW R5, #:lower16:k_curr_task
MOVT R5, #:upper16:k_curr_task
LDR R6, [R5]
@ R0 is SP of process being switched out
STR R0, [R6]
_context_restore:
@ k_curr_task = k_next_task;
MOVW R1, #:lower16:k_next_task
MOVT R1, #:upper16:k_next_task
LDR R2, [R1]
STR R2, [R5]
@ R0 = k_next_task->sp
LDR R0, [R2]
@ restore R4 - R11
LDMFD R0!, {R4 - R11}
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@ restore EXC_RETURN
LDMFD R0!, {LR}
@ is it extended frame?
TST LR, #0x10
IT EQ
VLDMIAEQ R0!, {S16 - S31}
#endif
@ Load PSP with new process SP
MSR PSP, R0
CPSIE I
@ R0-R3, R12, LR, PC, xPSR restored automatically here
@ S0 - S16, FPSCR restored automatically here if FPCA = 1
BX LR
.end

30
board/MM32F5270/BSP/Inc/board_init.h Normal file
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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __BOARD_INIT_H__
#define __BOARD_INIT_H__
#include <stdio.h>
#include <stdint.h>
#include "hal_common.h"
#include "hal_rcc.h"
#include "hal_uart.h"
#include "clock_init.h"
#include "pin_init.h"
/* DEBUG UART. */
#define BOARD_DEBUG_UART_PORT UART1
#define BOARD_DEBUG_UART_IRQ UART1_IRQn
#define BOARD_DEBUG_UART_BAUDRATE 115200u
#define BOARD_DEBUG_UART_FREQ CLOCK_APB2_FREQ
void BOARD_Init(void);
#endif /* __BOARD_INIT_H__ */

21
board/MM32F5270/BSP/Inc/clock_init.h Normal file
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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CLOCK_INIT_H__
#define __CLOCK_INIT_H__
#include "hal_common.h"
#define CLOCK_SYS_FREQ 120000000u
#define CLOCK_SYSTICK_FREQ (CLOCK_SYS_FREQ/8u)
#define CLOCK_AHB1_FREQ 120000000u
#define CLOCK_APB1_FREQ 60000000u
#define CLOCK_APB2_FREQ 60000000u
void BOARD_InitBootClocks(void);

14
board/MM32F5270/BSP/Inc/pin_init.h Normal file
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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PIN_INIT_H__
#define __PIN_INIT_H__
void BOARD_InitPins(void);
#endif /* __PIN_INIT_H__ */

179
board/MM32F5270/BSP/Src/board_init.c Normal file
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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "board_init.h"
#include "hal_gpio.h"
#include "tos_shell.h"
/*
* Definitions.
*/
/*
* Declerations.
*/
void BOARD_InitDebugConsole(void);
/*
* Functions.
*/
void BOARD_Init(void)
{
BOARD_InitBootClocks();
BOARD_InitPins();
BOARD_InitDebugConsole();
}
void BOARD_InitDebugConsole(void)
{
UART_Init_Type uart_init;
uart_init.ClockFreqHz = BOARD_DEBUG_UART_FREQ;
uart_init.BaudRate = BOARD_DEBUG_UART_BAUDRATE;
uart_init.WordLength = UART_WordLength_8b;
uart_init.StopBits = UART_StopBits_1;
uart_init.Parity = UART_Parity_None;
uart_init.XferMode = UART_XferMode_RxTx;
uart_init.HwFlowControl = UART_HwFlowControl_None;
UART_Init(BOARD_DEBUG_UART_PORT, &uart_init);
UART_EnableInterrupts(BOARD_DEBUG_UART_PORT, UART_ISR_RXINTF_MASK, true);
UART_Enable(BOARD_DEBUG_UART_PORT, true);
NVIC_SetPriority(BOARD_DEBUG_UART_IRQ, (1UL << __NVIC_PRIO_BITS) - 2UL);
}
#if defined(__ARMCC_VERSION)
int fputc(int c, FILE *f)
{
(void)(f);
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(c));
return c;
}
int fgetc(FILE *f)
{
(void)(f);
while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
return UART_GetData(BOARD_DEBUG_UART_PORT);
}
#elif defined(__GNUC__)
/*
* Called by libc stdio fwrite functions
*/
int _write(int fd, char *ptr, int len)
{
int i = 0;
/*
* write "len" of char from "ptr" to file id "fd"
* Return number of char written.
*
* Only work for STDOUT, STDIN, and STDERR
*/
if (fd > 2)
{
return -1;
}
while (*ptr && (i < len))
{
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(*ptr));
i++;
ptr++;
}
return i;
}
/*
* Called by the libc stdio fread fucntions
*
* Implements a buffered read with line editing.
*/
int _read(int fd, char *ptr, int len)
{
int my_len;
if (fd > 2)
{
return -1;
}
my_len = 0;
while (len > 0)
{
while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
*ptr = UART_GetData(BOARD_DEBUG_UART_PORT);
len--;
my_len++;
if ( (*ptr == '\r') || (*ptr == '\n') || (*ptr == '\0') )
{
break;
}
ptr++;
}
return my_len; /* return the length we got */
}
int putchar(int c)
{
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(c));
return c;
}
int getchar(void)
{
while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
return UART_GetData(BOARD_DEBUG_UART_PORT);
}
#elif (defined(__ICCARM__))
/* These function __write and __read is used to support IAR toolchain to printf and scanf. */
int fputc(int ch, FILE *f)
{
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(ch));
return ch;
}
int fgetc(FILE *f)
{
while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
return UART_GetData(BOARD_DEBUG_UART_PORT);
}
#endif
void UART1_IRQHandler(void)
{
uint8_t data = 0;
if (UART_ISR_RXINTF_MASK & UART_GetInterruptStatus(BOARD_DEBUG_UART_PORT))
{
data = UART_GetData(BOARD_DEBUG_UART_PORT);
tos_shell_input_byte(data);
}
}
/* EOF. */

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board/MM32F5270/BSP/Src/clock_init.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_common.h"
#include "clock_init.h"
#include "tos_k.h"
#include "tos_shell.h"
#include "hal_rcc.h"
void CLOCK_ResetToDefault(void);
void CLOCK_BootToHSI96MHz(void);
void CLOCK_BootToHSE96MHz(void);
void CLOCK_BootToHSE120MHz(void);
void BOARD_InitBootClocks(void)
{
CLOCK_ResetToDefault();
CLOCK_BootToHSE120MHz();
/* UART1. */
RCC_EnableAPB2Periphs(RCC_APB2_PERIPH_UART1, true);
RCC_ResetAPB2Periphs(RCC_APB2_PERIPH_UART1);
/* GPIOB. */
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOB, true);
RCC_ResetAHB1Periphs(RCC_AHB1_PERIPH_GPIOB);
/* GPIOI. */
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOI, true);
RCC_ResetAHB1Periphs(RCC_AHB1_PERIPH_GPIOI);
}
/* Switch to HSI. */
void CLOCK_ResetToDefault(void)
{
/* Switch to HSI. */
RCC->CR |= RCC_CR_HSION_MASK; /* Make sure the HSI is enabled. */
while ( RCC_CR_HSIRDY_MASK != (RCC->CR & RCC_CR_HSIRDY_MASK) )
{
}
RCC->CFGR = RCC_CFGR_SW(0u); /* Reset other clock sources and switch to HSI. */
while ( RCC_CFGR_SWS(0u) != (RCC->CFGR & RCC_CFGR_SWS_MASK) ) /* Wait while the SYSCLK is switch to the HSI. */
{
}
/* Reset all other clock sources. */
RCC->CR = RCC_CR_HSION_MASK;
/* Disable all interrupts and clear pending bits. */
RCC->CIR = RCC->CIR; /* clear flags. */
RCC->CIR = 0u; /* disable interrupts. */
}
/* Enable the PLL1 and use the HSE as input clock source. */
void CLOCK_BootToHSE120MHz(void)
{
RCC->APB1ENR |= (1u << 28u); /* enable PWR/DBG. */
PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS_MASK) | PWR_CR1_VOS(3u); /* 1.7V. */
/* enable HSE. */
RCC->CR |= RCC_CR_HSEON_MASK;
while ( RCC_CR_HSERDY_MASK != (RCC->CR & RCC_CR_HSERDY_MASK) )
{
}
RCC->PLL1CFGR = RCC_PLL1CFGR_PLL1SRC(1) /* (pllsrc == 1) ? HSE : HSI. */
| RCC_PLL1CFGR_PLL1MUL(19) /* (12 * (19 + 1)) / 2 = 120. */
| RCC_PLL1CFGR_PLL1DIV(1)
| RCC_PLL1CFGR_PLL1LDS(1)
| RCC_PLL1CFGR_PLL1ICTRL(3)
;
/* Enable PLL1. */
RCC->CR |= RCC_CR_PLL1ON_MASK;
while((RCC->CR & RCC_CR_PLL1RDY_MASK) == 0)
{
}
/* Enable the FLASH prefetch. */
RCC->AHB1ENR |= (1u << 13u); /* enable the access to FLASH. */
FLASH->ACR = FLASH_ACR_LATENCY(4u) /* setup divider. */
| FLASH_ACR_PRFTBE_MASK /* enable flash prefetch. */
;
/* Setup the dividers for each bus. */
RCC->CFGR = RCC_CFGR_HPRE(0) /* div=1 for AHB freq. */
| RCC_CFGR_PPRE1(0x4) /* div=2 for APB1 freq. */
| RCC_CFGR_PPRE2(0x4) /* div=2 for APB2 freq. */
| RCC_CFGR_MCO(7) /* use PLL1 as output. */
;
/* Switch the system clock source to PLL. */
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW(2); /* use PLL as SYSCLK */
/* Wait till PLL is used as system clock source. */
while ( (RCC->CFGR & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS(2) )
{
}
}
void SysTick_Handler(void)
{
if (tos_knl_is_running())
{
tos_knl_irq_enter();
tos_tick_handler();
tos_knl_irq_leave();
}
}
/* EOF. */

37
board/MM32F5270/BSP/Src/pin_init.c Normal file
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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "pin_init.h"
#include "hal_rcc.h"
#include "hal_gpio.h"
void BOARD_InitPins(void)
{
/* PB7 - UART1_TX. */
GPIO_Init_Type gpio_init;
gpio_init.Pins = GPIO_PIN_6;
gpio_init.PinMode = GPIO_PinMode_AF_PushPull; //GPIO_PinMode_AF_PushPull
gpio_init.Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOB, &gpio_init);
GPIO_PinAFConf(GPIOB, gpio_init.Pins, GPIO_AF_7);
/* PB6 - UART1_RX. */
gpio_init.Pins = GPIO_PIN_7;
gpio_init.PinMode = GPIO_PinMode_In_Floating; //GPIO_PinMode_In_Floating
gpio_init.Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOB, &gpio_init);
GPIO_PinAFConf(GPIOB, gpio_init.Pins, GPIO_AF_7);
/* PI0 - GPIO. */
gpio_init.Pins = GPIO_PIN_0;
gpio_init.PinMode = GPIO_PinMode_Out_PushPull;
gpio_init.Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOI, &gpio_init);
GPIO_WriteBit(GPIOI, GPIO_PIN_0, 1);
}

184
board/MM32F5270/BSP/Src/syscalls.c Normal file
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/**
*****************************************************************************
**
** File : syscalls.c
**
** Author : Auto-generated by STM32CubeIDE
**
** Abstract : STM32CubeIDE Minimal System calls file
**
** For more information about which c-functions
** need which of these lowlevel functions
** please consult the Newlib libc-manual
**
** Environment : STM32CubeIDE MCU
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
*****************************************************************************
**
** <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
**
*****************************************************************************
*/
/* Includes */
#include <sys/stat.h>
#include <stdlib.h>
#include <errno.h>
#include <stdio.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <sys/times.h>
/* Variables */
//#undef errno
extern int errno;
extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak));
register char * stack_ptr asm("sp");
char *__env[1] = { 0 };
char **environ = __env;
/* Functions */
void initialise_monitor_handles()
{
}
int _getpid(void)
{
return 1;
}
int _kill(int pid, int sig)
{
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
}
int _close(int file)
{
return -1;
}
int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
return 1;
}
int _lseek(int file, int ptr, int dir)
{
return 0;
}
int _open(char *path, int flags, ...)
{
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
return -1;
}
int _stat(char *file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
errno = ENOMEM;
return -1;
}

234
board/MM32F5270/GCC/hello_world/Makefile Normal file
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##########################################################################################################################
# File automatically-generated by tool: [projectgenerator] version: [3.3.0] date: [Mon Aug 05 10:29:11 CST 2019]
##########################################################################################################################
# ------------------------------------------------
# Generic Makefile (based on gcc)
#
# ChangeLog :
# 2022-08-17 - Port to MM32F250
# 2022-04-13 - Port to GD32F310-START
# 2017-02-10 - Several enhancements + project update mode
# 2015-07-22 - first version
# ------------------------------------------------
######################################
# target
######################################
TARGET = TencentOS_tiny
######################################
# building variables
######################################
# debug build?
DEBUG = 1
# optimization
OPT = -O0
TOP_DIR = ../../../..
#######################################
# paths
#######################################
# Build path
BUILD_DIR = build
######################################
# source
######################################
# C sources
KERNEL_SRC = \
${wildcard $(TOP_DIR)/kernel/core/*.c}
C_SOURCES += $(KERNEL_SRC)
ARCH_SRC = \
${wildcard $(TOP_DIR)/arch/arm/arm-v8m/star-mc1/gcc/*.c} \
${wildcard $(TOP_DIR)/arch/arm/arm-v8m/common/*.c}
C_SOURCES += $(ARCH_SRC)
BOARD_SRC = \
${wildcard $(TOP_DIR)/board/MM32F5270/BSP/Src/*.c} \
${wildcard $(TOP_DIR)/board/MM32F5270/GCC/hello_world/main.c}
HAL_DRIVER_SRC = $(BOARD_SRC) \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.c \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.c
C_SOURCES += $(HAL_DRIVER_SRC)
# ASM sources
ASM_SOURCES_S = \
$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/armgcc/startup_mm32f5277e.S
ASM_SOURCES_S += \
$(TOP_DIR)/arch/arm/arm-v8m/star-mc1/gcc/port_s.S
COMPONENTS_SRC = \
$(TOP_DIR)/components/shell/tos_shell.c \
$(TOP_DIR)/components/shell/tos_shell_commands.c
C_SOURCES += $(COMPONENTS_SRC)
#######################################
# binaries
#######################################
PREFIX = arm-none-eabi-
# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
# either it can be added to the PATH environment variable.
ifdef GCC_PATH
CC = $(GCC_PATH)/$(PREFIX)gcc
AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
CP = $(GCC_PATH)/$(PREFIX)objcopy
SZ = $(GCC_PATH)/$(PREFIX)size
else
CC = $(PREFIX)gcc
AS = $(PREFIX)gcc -x assembler-with-cpp
CP = $(PREFIX)objcopy
SZ = $(PREFIX)size
endif
HEX = $(CP) -O ihex
BIN = $(CP) -O binary -S
#######################################
# CFLAGS
#######################################
# cpu
CPU = -mcpu=cortex-m33
# fpu
FPU = -mfpu=fpv4-sp-d16
# float-abi
FLOAT-ABI = -mfloat-abi=hard
# asm extra flags
ASM_EXTRA_FLAGS = -DDEBUG -D__STARTUP_CLEAR_BSS -D__STARTUP_INITIALIZE_NONCACHEDATA -g -fno-common -ffreestanding -fno-builtin -mapcs -std=gnu99
# C extra flags
C_EXTRA_FLAGS = -MMD -MP -fno-common -ffreestanding -fno-builtin -mapcs -std=gnu99
# C++ extra flags
CXX_EXTRA_FLAGS = -MMD -MP -fno-common -ffreestanding -fno-builtin -mapcs -fno-rtti -fno-exceptions
# mcu
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
# macros for gcc
# AS defines
AS_DEFS =
# C defines
C_DEFS = \
-DMM32F5270
# AS includes
AS_INCLUDES =
# C includes
KERNEL_INC = \
-I $(TOP_DIR)/kernel/core/include \
-I $(TOP_DIR)/kernel/pm/include \
-I $(TOP_DIR)/kernel/hal/include \
-I $(TOP_DIR)/arch/arm/arm-v8m/common/include \
-I $(TOP_DIR)/arch/arm/arm-v8m/star-mc1/gcc \
-I $(TOP_DIR)/board/MM32F5270/TOS-CONFIG
C_INCLUDES += $(KERNEL_INC)
CMSIS_INC = \
-I $(TOP_DIR)/osal/cmsis_os \
-I $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527 \
-I $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include
C_INCLUDES += $(CMSIS_INC)
HAL_DRIVER_INC = \
-I $(TOP_DIR)/board/MM32F5270/BSP/Inc \
-I $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers
C_INCLUDES += $(HAL_DRIVER_INC)
COMPONENTS_INC = \
-I $(TOP_DIR)/components/shell/include
C_INCLUDES += $(COMPONENTS_INC)
# compile gcc flags
ASFLAGS = $(MCU) $(ASM_EXTRA_FLAGS) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
CFLAGS = $(MCU) $(C_EXTRA_FLAGS) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
ifeq ($(DEBUG), 1)
CFLAGS += -g -gdwarf-2
endif
# Generate dependency information
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
#######################################
# LDFLAGS
#######################################
# link script
LDSCRIPT = $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/armgcc/linker/mm32f5277e_flash.ld
# libraries
LIBS = -lc -lm -lnosys
LIBDIR =
LDFLAGS = $(MCU) -specs=nosys.specs -specs=nano.specs -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mthumb -mapcs -Xlinker --gc-sections -Xlinker -static -Xlinker -z -Xlinker muldefs -Xlinker -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
# default action: build all
all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
#######################################
# build the application
#######################################
# list of objects
OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
vpath %.c $(sort $(dir $(C_SOURCES)))
# list of ASM program objects
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
vpath %.s $(sort $(dir $(ASM_SOURCES)))
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES_S:.S=.o)))
vpath %.S $(sort $(dir $(ASM_SOURCES_S)))
$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
$(AS) -c $(CFLAGS) $< -o $@
$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR)
$(AS) -c $(CFLAGS) $< -o $@
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
$(CC) $(OBJECTS) $(LDFLAGS) -o $@
$(SZ) $@
$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
$(HEX) $< $@
$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
$(BIN) $< $@
@cp $@ ./$(notdir $@)
$(BUILD_DIR):
mkdir $@
#######################################
# clean up
#######################################
clean:
-rm -fR $(BUILD_DIR)
#######################################
# dependencies
#######################################
-include $(wildcard $(BUILD_DIR)/*.d)
# *** EOF ***

57
board/MM32F5270/GCC/hello_world/main.c Normal file
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@@ -0,0 +1,57 @@
/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "board_init.h"
#include "tos_shell.h"
#include "hal_gpio.h"
#define APPLICATION_TASK_STK_SIZE 0x1000
k_task_t application_task;
uint8_t application_task_stk[APPLICATION_TASK_STK_SIZE];
static char gs_cmd_buffer[32];
__attribute__ ((__weak__)) void application_entry(void *arg)
{
NVIC_EnableIRQ(BOARD_DEBUG_UART_IRQ);
while (1) {
GPIO_WriteBit(GPIOI, GPIO_PIN_0, 0);
tos_task_delay(1000);
GPIO_WriteBit(GPIOI, GPIO_PIN_0, 1);
tos_task_delay(1000);
}
}
static void board_shell_output_t(const char ch)
{
if (ch == '\n')
{
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
UART_PutData(BOARD_DEBUG_UART_PORT, '\r');
}
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) )
{}
UART_PutData(BOARD_DEBUG_UART_PORT, ch);
}
/*
* Functions.
*/
int main(void)
{
BOARD_Init();
tos_knl_init();
tos_task_create(&application_task, "main_task", application_entry, NULL, 1, application_task_stk, APPLICATION_TASK_STK_SIZE, 0);
tos_shell_init(gs_cmd_buffer, sizeof(gs_cmd_buffer), board_shell_output_t, NULL);
tos_knl_start();
return 0;
}
/* EOF. */

12
board/MM32F5270/GCC/hello_world/readme.md Normal file
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@@ -0,0 +1,12 @@
# hello_world
## 实验过程
+ 打印“tshell>”
+ 用户通过串口向设备发送任意字符，设备通过串口返回用户发送的字符。
## 实验结果
tshell>ps
LED4 以周期 1s 闪烁

41
board/MM32F5270/TOS-CONFIG/tickless/tos_config.h Normal file
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@@ -0,0 +1,41 @@
#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
#include "stm32l4xx.h"
#define TOS_CFG_TASK_PRIO_MAX 10u
#define TOS_CFG_ROUND_ROBIN_EN 1u
#define TOS_CFG_OBJECT_VERIFY_EN 1u
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
#define TOS_CFG_EVENT_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#define TOS_CFG_MMHEAP_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x6000
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 1u
#define TOS_CFG_TICKLESS_EN 1u
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_IDLE_TASK_STK_SIZE 512u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
#define TOS_CFG_TIMER_AS_PROC 1u
#endif

47
board/MM32F5270/TOS-CONFIG/tos_config.h Normal file
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@@ -0,0 +1,47 @@
#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
#include "mm32f5277e.h"
#define TOS_CFG_TASK_PRIO_MAX 10u
#define TOS_CFG_ROUND_ROBIN_EN 1u
#define TOS_CFG_OBJECT_VERIFY_EN 1u
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
#define TOS_CFG_EVENT_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#define TOS_CFG_MMHEAP_EN 0u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x400
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 0u
#define TOS_CFG_TICKLESS_EN 0u
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u
#define TOS_CFG_FAULT_BACKTRACE_EN 1u
#define TOS_CFG_IDLE_TASK_STK_SIZE 1024u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (120000000)
#define TOS_CFG_TIMER_AS_PROC 1u
#define TOS_CFG_MAIL_QUEUE_EN 1u
#endif

378
platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_common_tables.h Normal file
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@@ -0,0 +1,378 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
extern const uint16_t armBitRevTable[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
extern const float32_t twiddleCoef_16[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
extern const float32_t twiddleCoef_32[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
extern const float32_t twiddleCoef_64[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
extern const float32_t twiddleCoef_128[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
extern const float32_t twiddleCoef_256[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
extern const float32_t twiddleCoef_512[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
extern const float32_t twiddleCoef_1024[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
extern const float32_t twiddleCoef_2048[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
extern const q31_t twiddleCoef_16_q31[24];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
extern const q31_t twiddleCoef_32_q31[48];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
extern const q31_t twiddleCoef_64_q31[96];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
extern const q31_t twiddleCoef_128_q31[192];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
extern const q31_t twiddleCoef_256_q31[384];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
extern const q31_t twiddleCoef_512_q31[768];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
extern const q31_t twiddleCoef_1024_q31[1536];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
extern const q31_t twiddleCoef_2048_q31[3072];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
extern const q31_t twiddleCoef_4096_q31[6144];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
extern const q15_t twiddleCoef_16_q15[24];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
extern const q15_t twiddleCoef_32_q15[48];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
extern const q15_t twiddleCoef_64_q15[96];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
extern const q15_t twiddleCoef_128_q15[192];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
extern const q15_t twiddleCoef_256_q15[384];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
extern const q15_t twiddleCoef_512_q15[768];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
extern const q15_t twiddleCoef_1024_q15[1536];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
extern const q15_t twiddleCoef_2048_q15[3072];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
extern const q15_t twiddleCoef_4096_q15[6144];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
extern const float32_t twiddleCoef_rfft_32[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
extern const float32_t twiddleCoef_rfft_64[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
extern const float32_t twiddleCoef_rfft_128[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
extern const float32_t twiddleCoef_rfft_256[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
extern const float32_t twiddleCoef_rfft_512[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
extern const float32_t twiddleCoef_rfft_1024[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
extern const float32_t twiddleCoef_rfft_2048[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
extern const float32_t twiddleCoef_rfft_4096[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* floating-point bit reversal tables */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* fixed-point bit reversal tables */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
extern const float32_t realCoefA[8192];
extern const float32_t realCoefB[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
extern const q31_t realCoefAQ31[8192];
extern const q31_t realCoefBQ31[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
extern const q15_t realCoefAQ15[8192];
extern const q15_t realCoefBQ15[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
extern const float32_t Weights_128[256];
extern const float32_t cos_factors_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
extern const float32_t Weights_512[1024];
extern const float32_t cos_factors_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
extern const float32_t Weights_2048[4096];
extern const float32_t cos_factors_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
extern const float32_t Weights_8192[16384];
extern const float32_t cos_factors_8192[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
extern const q15_t WeightsQ15_128[256];
extern const q15_t cos_factorsQ15_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
extern const q15_t WeightsQ15_512[1024];
extern const q15_t cos_factorsQ15_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
extern const q15_t WeightsQ15_2048[4096];
extern const q15_t cos_factorsQ15_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
extern const q15_t WeightsQ15_8192[16384];
extern const q15_t cos_factorsQ15_8192[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
extern const q31_t WeightsQ31_128[256];
extern const q31_t cos_factorsQ31_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
extern const q31_t WeightsQ31_512[1024];
extern const q31_t cos_factorsQ31_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
extern const q31_t WeightsQ31_2048[4096];
extern const q31_t cos_factorsQ31_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
extern const q31_t WeightsQ31_8192[16384];
extern const q31_t cos_factorsQ31_8192[8192];
#endif
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
extern const q15_t armRecipTableQ15[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
extern const q31_t armRecipTableQ31[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
/* Tables for Fast Math Sine and Cosine */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file cmsis_xcc.h
* @brief CMSIS DSP Core Peripheral Access Layer Header File
* @version V1.0
* @date 20. January 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CORE_DSP_H_GENERIC
#define __CORE_DSP_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __STATIC_INLINE static inline
#define __BKPT(value) do {} while(0)
#define __NOP() do {} while(0)
#define NVIC_SetPriorityGrouping(value) do {} while(0)
#define NVIC_GetPriorityGrouping() do {} while(0)
#define NVIC_EnableIRQ(value) do {} while(0)
#define NVIC_GetEnableIRQ(value) do {} while(0)
#define NVIC_DisableIRQ(value) do {} while(0)
#define NVIC_GetPendingIRQ(value) do {} while(0)
#define NVIC_SetPendingIRQ(value) do {} while(0)
#define NVIC_ClearPendingIRQ(value) do {} while(0)
#define NVIC_GetActive(value) do {} while(0)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_DSP_H_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

70
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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

298
platform/vendor_bsp/MindMotion/MM32F527/armgcc/linker/mm32f5277e_flash.ld Normal file
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/*
*-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*---------------------- Flash Configuration ----------------------------------
<h> Flash Configuration
<o0> Flash Base Address <0x0-0xFFFFFFFF:8>
<o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
-----------------------------------------------------------------------------*/
__ROM_BASE = 0x08000000;
__ROM_SIZE = 0x00040000;
/*--------------------- Embedded RAM Configuration ----------------------------
<h> RAM Configuration
<o0> RAM Base Address <0x0-0xFFFFFFFF:8>
<o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
-----------------------------------------------------------------------------*/
__RAM_BASE = 0x30000000;
__RAM_SIZE = 0x0001C000;
/*--------------------- Stack / Heap Configuration ----------------------------
<h> Stack / Heap Configuration
<o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
-----------------------------------------------------------------------------*/
__STACK_SIZE = 0x00001000;
__HEAP_SIZE = 0x00001000;
/*
*-------------------- <<< end of configuration section >>> -------------------
*/
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
*/
__STACKSEAL_SIZE = 0;
MEMORY
{
FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __StackSeal (only if ARMv8-M stack sealing is used)
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
_stext = .;
KEEP(*(.vectors))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
/*
* SG veneers:
* All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
* must be set, either with the command line option <20><>--section-start<72><74> or in a linker script,
* to indicate where to place these veneers in memory.
*/
/*
.gnu.sgstubs :
{
. = ALIGN(32);
} > FLASH
*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG ((__data_end__ - __data_start__) / 4)
/* Add each additional data section here */
/*
LONG (__etext2)
LONG (__data2_start__)
LONG ((__data2_end__ - __data2_start__) / 4)
*/
__copy_table_end__ = .;
} > FLASH
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
/* Add each additional bss section here */
/*
LONG (__bss2_start__)
LONG ((__bss2_end__ - __bss2_start__) / 4)
*/
__zero_table_end__ = .;
} > FLASH
/**
* Location counter can end up 2byte aligned with narrow Thumb code but
* __etext is assumed by startup code to be the LMA of a section in RAM
* which must be 4byte aligned
*/
__etext = ALIGN (4);
_etext = ALIGN (4);
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
/*
* Secondary data section, optional
*
* Remember to add each additional data section
* to the .copy.table above to asure proper
* initialization during startup.
*/
/*
__etext2 = ALIGN (4);
.data2 : AT (__etext2)
{
. = ALIGN(4);
__data2_start__ = .;
*(.data2)
*(.data2.*)
. = ALIGN(4);
__data2_end__ = .;
} > RAM2
*/
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM AT > RAM
/*
* Secondary bss section, optional
*
* Remember to add each additional bss section
* to the .zero.table above to asure proper
* initialization during startup.
*/
/*
.bss2 :
{
. = ALIGN(4);
__bss2_start__ = .;
*(.bss2)
*(.bss2.*)
. = ALIGN(4);
__bss2_end__ = .;
} > RAM2 AT > RAM2
*/
.heap (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
} > RAM
.stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
_sstack = .;
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
_estack = .;
} > RAM
PROVIDE(__stack = __StackTop);
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing uncomment '.stackseal' section
*/
/*
.stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackSeal = .;
. = . + 8;
. = ALIGN(8);
} > RAM
*/
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

348
platform/vendor_bsp/MindMotion/MM32F527/armgcc/startup_mm32f5277e.S Normal file
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/* ------------------------------------------------------------------------- */
/* @file: startup_MM32F5277.S */
/* @purpose: CMSIS Star-MC1 Core Device Startup File */
/* */
/* @version: 1.0 */
/* @date: 2022-07-01 */
/* @build: b220701 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 2022 MindMotion */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: ICC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv8-m.main
#define __INITIAL_SP __StackTop
#define __STACK_LIMIT __StackLimit
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACK_SEAL __StackSeal
#endif
.section .vectors
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __INITIAL_SP /* Initial Stack Pointer */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
.long WWDG_IWDG_IRQHandler /* 0 Watchdog interrupt (IWDG is EXTI21) */
.long PVD_IRQHandler /* 1 Supply Voltage Detect (PVD) Interrupt (EXTI16) */
.long BKP_TAMPER_IRQHandler /* 2 BKP intrusion detection interrupted */
.long RTC_IRQHandler /* 3 RTC global interrupt */
.long FLASH_IRQHandler /* 4 Flash Global Interrupt */
.long RCC_CRS_IRQHandler /* 5 RCC and CRS global interrupt */
.long EXTI0_IRQHandler /* 6 EXTI line 0 interrupt */
.long EXTI1_IRQHandler /* 7 EXTI line 1 interrupt */
.long EXTI2_IRQHandler /* 8 EXTI line 2 interrupt */
.long EXTI3_IRQHandler /* 9 EXTI line 3 interrupt */
.long EXTI4_IRQHandler /* 10 EXTI line 4 interrupt */
.long DMA1_CH1_IRQHandler /* 11 DMA1 channel 1 global interrupt */
.long DMA1_CH2_IRQHandler /* 12 DMA1 channel 2 global interrupt */
.long DMA1_CH3_IRQHandler /* 13 DMA1 channel 3 global interrupt */
.long DMA1_CH4_IRQHandler /* 14 DMA1 channel 4 global interrupt */
.long DMA1_CH5_IRQHandler /* 15 DMA1 channel 5 global interrupt */
.long DMA1_CH6_IRQHandler /* 16 DMA1 channel 6 global interrupt */
.long DMA1_CH7_IRQHandler /* 17 DMA1 channel 7 global interrupt */
.long ADC1_2_IRQHandler /* 18 ADC1/2 global interrupt */
.long 0 /* 19 Reserved */
.long DMA1_CH8_IRQHandler /* 20 DMA1 channel 8 global interrupt */
.long FlexCAN1_IRQHandler /* 21 FlexCAN1 global interrupt */
.long 0 /* 22 Reserved */
.long EXTI9_5_IRQHandler /* 23 EXTI line[9:5] interrupt */
.long TIM1_BRK_IRQHandler /* 24 TIM1 brake interrupt */
.long TIM1_UP_IRQHandler /* 25 TIM1 update interrupted */
.long TIM1_TRG_COM_IRQHandler /* 26 TIM1 trigger/COM interrupt */
.long TIM1_CC_IRQHandler /* 27 TIM1 capture compare interrupt */
.long TIM2_IRQHandler /* 28 TIM2 global interrupt */
.long TIM3_IRQHandler /* 29 TIM3 global interrupt */
.long TIM4_IRQHandler /* 30 TIM4 global interrupt */
.long I2C1_IRQHandler /* 31 I2C1 global interrupt */
.long 0 /* 32 Reserved */
.long I2C2_IRQHandler /* 33 I2C2 global interrupt */
.long 0 /* 34 Reserved */
.long SPI1_IRQHandler /* 35 SPI1 global interrupt */
.long SPI2_IRQHandler /* 36 SPI2 global interrupt */
.long UART1_IRQHandler /* 37 UART1 global interrupt */
.long UART2_IRQHandler /* 38 UART2 global interrupt */
.long UART3_IRQHandler /* 39 UART3 global interrupt */
.long EXTI15_10_IRQHandler /* 40 Interrupt on EXTI line[15:10] */
.long RTC_ALR_IRQHandler /* 41 RTC Alarm Interrupt (EXTI17) */
.long USB_WKUP_IRQHandler /* 42 USB Wakeup Interrupt (EXTI18) */
.long TIM8_BRK_IRQHandler /* 43 TIM8 brake interrupt */
.long TIM8_UP_IRQHandler /* 44 TIM8 update interrupted */
.long TIM8_TRG_COM_IRQHandler /* 45 TIM8 trigger/COM interrupt */
.long TIM8_CC_IRQHandler /* 46 TIM8 capture compare interrupt */
.long 0 /* 47 Reserved */
.long 0 /* 48 Reserved */
.long 0 /* 49 Reserved */
.long TIM5_IRQHandler /* 50 TIM5 global interrupt */
.long SPI3_IRQHandler /* 51 SPI3 global interrupt */
.long UART4_IRQHandler /* 52 UART4 global interrupt */
.long UART5_IRQHandler /* 53 UART5 global interrupt */
.long TIM6_IRQHandler /* 54 TIM6 global interrupt */
.long TIM7_IRQHandler /* 55 TIM7 global interrupt */
.long DMA2_CH1_IRQHandler /* 56 DMA2 channel 1 global interrupt */
.long DMA2_CH2_IRQHandler /* 57 DMA2 channel 2 global interrupt */
.long DMA2_CH3_IRQHandler /* 58 DMA2 channel 3 global interrupt */
.long DMA2_CH4_IRQHandler /* 59 DMA2 channel 4 global interrupt */
.long DMA2_CH5_IRQHandler /* 60 DMA2 channel 5 global interrupt */
.long ENET_IRQHandler /* 61 ENET global interrupt */
.long ENET_WKUP_IRQHandler /* 62 ENET wake-up interrupt (EXTI25) */
.long 0 /* 63 Reserved */
.long COMP_IRQHandler /* 64 Comparator 1/2/3 Global Interrupts (EXTI19/20/24) */
.long FlexCAN2_IRQHandler /* 65 FLexCAN2 global interrupt */
.long 0 /* 66 Reserved */
.long USB_FS_IRQHandler /* 67 USB OTG global interrupt */
.long DMA2_CH6_IRQHandler /* 68 DMA2 channel 6 global interrupt */
.long DMA2_CH7_IRQHandler /* 69 DMA2 channel 7 global interrupt */
.long DMA2_CH8_IRQHandler /* 70 DMA2 channel 8 global interrupt */
.long UART6_IRQHandler /* 71 UART6 global interrupt */
.long 0 /* 72 Reserved */
.long 0 /* 73 Reserved */
.long 0 /* 74 Reserved */
.long 0 /* 75 Reserved */
.long 0 /* 76 Reserved */
.long 0 /* 77 Reserved */
.long 0 /* 78 Reserved */
.long 0 /* 79 Reserved */
.long 0 /* 80 Reserved */
.long 0 /* 81 Reserved */
.long UART7_IRQHandler /* 82 UART7 global interrupt */
.long 0 /* 83 Reserved */
.long 0 /* 84 Reserved */
.long 0 /* 85 Reserved */
.long 0 /* 86 Reserved */
.long 0 /* 87 Reserved */
.long 0 /* 88 Reserved */
.long 0 /* 89 Reserved */
.long 0 /* 90 Reserved */
.long 0 /* 91 Reserved */
.long 0 /* 92 Reserved */
.long 0 /* 93 Reserved */
.long 0 /* 94 Reserved */
.long QSPI_IRQHandler /* 95 QSPI global interrupt */
.long 0 /* 96 Reserved */
.long 0 /* 97 Reserved */
.long 0 /* 98 Reserved */
.long 0 /* 99 Reserved */
.long 0 /* 100 Reserved */
.long 0 /* 101 Reserved */
.long LPTIM_IRQHandler /* 102 LPTIM global interrupt (EXTI22) */
.long 0 /* 103 Reserved */
.long LPUART_IRQHandler /* 104 LPUART global interrupt (EXTI23) */
.space (470 * 4) /* Interrupts 10 .. 480 are left out */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
.thumb
.section .text
.align 2
.thumb_func
.type Reset_Handler, %function
.globl Reset_Handler
.fnstart
Reset_Handler:
ldr r0, =__INITIAL_SP
msr psp, r0
#ifdef STACK_LIMIT_CHECK
ldr r0, =__STACK_LIMIT
msr msplim, r0
msr psplim, r0
#else
ldr r0, =0xE000ED14
ldr r1, [r0]
orr r1, #0x400
str r1, [r0]
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ldr r0, =__STACK_SEAL
ldr r1, =0xFEF5EDA5U
strd r1,r1,[r0,#0]
#endif
bl SystemInit
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4] /* source address */
ldr r2, [r4, #4] /* destination address */
ldr r3, [r4, #8] /* word count */
lsls r3, r3, #2 /* byte count */
.L_loop0_0:
subs r3, #4 /* decrement byte count */
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3] /* destination address */
ldr r2, [r3, #4] /* word count */
lsls r2, r2, #2 /* byte count */
movs r0, 0
.L_loop2_0:
subs r2, #4 /* decrement byte count */
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
bl _start
.fnend
.size Reset_Handler, . - Reset_Handler
/* The default macro is not used for HardFault_Handler
* because this results in a poor debug illusion.
*/
.thumb_func
.type HardFault_Handler, %function
.weak HardFault_Handler
.fnstart
HardFault_Handler:
b .
.fnend
.size HardFault_Handler, . - HardFault_Handler
.thumb_func
.type Default_Handler, %function
.weak Default_Handler
.fnstart
Default_Handler:
b .
.fnend
.size Default_Handler, . - Default_Handler
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Set_Default_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* Exception Handlers */
Set_Default_Handler NMI_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler WWDG_IWDG_IRQHandler
Set_Default_Handler PVD_IRQHandler
Set_Default_Handler BKP_TAMPER_IRQHandler
Set_Default_Handler RTC_IRQHandler
Set_Default_Handler FLASH_IRQHandler
Set_Default_Handler RCC_CRS_IRQHandler
Set_Default_Handler EXTI0_IRQHandler
Set_Default_Handler EXTI1_IRQHandler
Set_Default_Handler EXTI2_IRQHandler
Set_Default_Handler EXTI3_IRQHandler
Set_Default_Handler EXTI4_IRQHandler
Set_Default_Handler DMA1_CH1_IRQHandler
Set_Default_Handler DMA1_CH2_IRQHandler
Set_Default_Handler DMA1_CH3_IRQHandler
Set_Default_Handler DMA1_CH4_IRQHandler
Set_Default_Handler DMA1_CH5_IRQHandler
Set_Default_Handler DMA1_CH6_IRQHandler
Set_Default_Handler DMA1_CH7_IRQHandler
Set_Default_Handler ADC1_2_IRQHandler
Set_Default_Handler DMA1_CH8_IRQHandler
Set_Default_Handler FlexCAN1_IRQHandler
Set_Default_Handler EXTI9_5_IRQHandler
Set_Default_Handler TIM1_BRK_IRQHandler
Set_Default_Handler TIM1_UP_IRQHandler
Set_Default_Handler TIM1_TRG_COM_IRQHandler
Set_Default_Handler TIM1_CC_IRQHandler
Set_Default_Handler TIM2_IRQHandler
Set_Default_Handler TIM3_IRQHandler
Set_Default_Handler TIM4_IRQHandler
Set_Default_Handler I2C1_IRQHandler
Set_Default_Handler I2C2_IRQHandler
Set_Default_Handler SPI1_IRQHandler
Set_Default_Handler SPI2_IRQHandler
Set_Default_Handler UART1_IRQHandler
Set_Default_Handler UART2_IRQHandler
Set_Default_Handler UART3_IRQHandler
Set_Default_Handler EXTI15_10_IRQHandler
Set_Default_Handler RTC_ALR_IRQHandler
Set_Default_Handler USB_WKUP_IRQHandler
Set_Default_Handler TIM8_BRK_IRQHandler
Set_Default_Handler TIM8_UP_IRQHandler
Set_Default_Handler TIM8_TRG_COM_IRQHandler
Set_Default_Handler TIM8_CC_IRQHandler
Set_Default_Handler TIM5_IRQHandler
Set_Default_Handler SPI3_IRQHandler
Set_Default_Handler UART4_IRQHandler
Set_Default_Handler UART5_IRQHandler
Set_Default_Handler TIM6_IRQHandler
Set_Default_Handler TIM7_IRQHandler
Set_Default_Handler DMA2_CH1_IRQHandler
Set_Default_Handler DMA2_CH2_IRQHandler
Set_Default_Handler DMA2_CH3_IRQHandler
Set_Default_Handler DMA2_CH4_IRQHandler
Set_Default_Handler DMA2_CH5_IRQHandler
Set_Default_Handler ENET_IRQHandler
Set_Default_Handler ENET_WKUP_IRQHandler
Set_Default_Handler COMP_IRQHandler
Set_Default_Handler FlexCAN2_IRQHandler
Set_Default_Handler USB_FS_IRQHandler
Set_Default_Handler DMA2_CH6_IRQHandler
Set_Default_Handler DMA2_CH7_IRQHandler
Set_Default_Handler DMA2_CH8_IRQHandler
Set_Default_Handler UART6_IRQHandler
Set_Default_Handler UART7_IRQHandler
Set_Default_Handler QSPI_IRQHandler
Set_Default_Handler LPTIM_IRQHandler
Set_Default_Handler LPUART_IRQHandler
.end

505
platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_adc.c Normal file
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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_adc.h"
void ADC_Init(ADC_Type * ADCx, ADC_Init_Type * init)
{
if (!init)
{
return;
}
ADCx->ADCFG = (ADCx->ADCFG & ~ADC_ADCFG_RSLTCTL_MASK)| ADC_ADCFG_RSLTCTL(init->Resolution);
/* ADC conversion mode and conversion data result align. */
ADCx->ADCR = (ADCx->ADCR & ~( ADC_ADCR_ADMD_MASK | ADC_ADCR_ALIGN_MASK) )
| ADC_ADCR_ADMD(init->ConvMode)
| ADC_ADCR_ALIGN(init->Align)
;
/* Set the single-end or diff conversion mode. */
ADCx->ADCFG2 = ADCx->ADCFG2 & ~(ADC_ADCFG2_ADCSREF_MASK | ADC_ADCFG2_DC_MASK | ADC_ADCFG2_PSDC_MASK);
if (ADC_SingleDiffConvMode_SingleEnd == init->SingleDiffMode)
{
ADCx->ADCFG2 |= ADC_ADCFG2_ADCSREF(init->SingleVolt);
}
else if (ADC_SingleDiffConvMode_Diff == init->SingleDiffMode)
{
ADCx->ADCFG2 |= ADC_ADCFG2_DC(init->DiffPair);
}
else if (ADC_SingleDiffConvMode_PseudoDiff == init->SingleDiffMode)
{
ADCx->ADCFG2 = ADCx->ADCFG2 | ( ADC_ADCFG2_DC(init->DiffPair) | ADC_ADCFG2_PSDC(init->DiffPair) );
}
}
void ADC_Enable(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCFG |= ADC_ADCFG_ADEN_MASK;
}
else
{
ADCx->ADCFG &= ~ADC_ADCFG_ADEN_MASK;
}
}
void ADC_EnableTempSensor(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCFG |= ADC_ADCFG_TSEN_MASK;
}
else
{
ADCx->ADCFG &= ~ADC_ADCFG_TSEN_MASK;
}
}
/* Use VBG 1.2V as default voltage sensor. */
void ADC_EnableVoltSensor(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx ->ADCFG |= ADC_ADCFG_VSEN_MASK;
}
else
{
ADCx->ADCFG &= ~ADC_ADCFG_VSEN_MASK;
}
}
void ADC_EnableDMA(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCR |= ADC_ADCR_DMAEN_MASK;
}
else
{
ADCx->ADCR &= ~ADC_ADCR_DMAEN_MASK;
}
}
void ADC_EnableInterrupts(ADC_Type * ADCx, uint32_t interrupts, bool enable)
{
if (enable)
{
if ( 0u != (ADC_INT_CONV_SLOT_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_EOCIE_MASK;
}
if ( 0u != (ADC_INT_CONV_SAMPLE_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_EOSMPIE_MASK;
}
if ( 0u != (ADC_INT_CONV_SEQ_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_EOSIE_MASK;
}
if ( 0u != (ADC_INT_CONV_COMPARE_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_AWDIE_MASK;
}
if ( 0u != (ADC_INT_CONV_CALIB_DONE & interrupts) )
{
ADCx->ANYCR |= ADC_ANYCR_EOCALIE_MASK;
}
if ( 0u != (ADC_INT_JCONV_SLOT_DONE & interrupts) )
{
ADCx->ANYCR |= ADC_ANYCR_JEOCIE_MASK;
}
if ( 0u != (ADC_INT_JCONV_SAMPLE_DONE & interrupts) )
{
ADCx->ANYCR |= ADC_ANYCR_JEOSMPIE_MASK;
}
if ( 0u != (ADC_INT_JCONV_SEQ_DONE & interrupts) )
{
ADCx->ANYCR |= ADC_ANYCR_JEOSIE_MASK;
}
}
else
{
if ( 0u != (ADC_INT_CONV_SLOT_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_EOCIE_MASK;
}
if ( 0u != (ADC_INT_CONV_SAMPLE_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_EOSMPIE_MASK;
}
if ( 0u != (ADC_INT_CONV_SEQ_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_EOSIE_MASK;
}
if ( 0u != (ADC_INT_CONV_COMPARE_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_AWDIE_MASK;
}
if ( 0u != (ADC_INT_CONV_CALIB_DONE & interrupts) )
{
ADCx->ANYCR &= ~ ADC_ANYCR_EOCALIE_MASK;
}
if ( 0u != (ADC_INT_JCONV_SLOT_DONE & interrupts) )
{
ADCx->ANYCR &= ~ ADC_ANYCR_JEOCIE_MASK;
}
if ( 0u != (ADC_INT_JCONV_SAMPLE_DONE & interrupts) )
{
ADCx->ANYCR &= ~ ADC_ANYCR_JEOSMPIE_MASK;
}
if ( 0u != (ADC_INT_JCONV_SEQ_DONE & interrupts) )
{
ADCx->ANYCR &= ~ ADC_ANYCR_JEOSIE_MASK;
}
}
}
uint32_t ADC_GetStatus(ADC_Type * ADCx)
{
uint32_t flags = 0u;
if ( 0u != (ADC_ADSTAEXT_EOCALIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_CONV_CALIB_DONE;
}
if ( 0u != (ADC_ADSTAEXT_JEOCIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_JCONV_SLOT_DONE;
}
if ( 0u != (ADC_ADSTAEXT_JEOSMPIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_JCONV_SAMPLE_DONE;
}
if ( 0u != (ADC_ADSTAEXT_JEOSIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_JCONV_SEQ_DONE;
}
if ( 0u != (ADC_ADSTAEXT_EOCIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_CONV_SLOT_DONE;
}
if ( 0u != (ADC_ADSTAEXT_EOSMPIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_CONV_SAMPLE_DONE;
}
if ( 0u != (ADC_ADSTA_EOSIF_MASK & ADCx->ADSTA) )
{
flags |= ADC_STATUS_CONV_SEQ_DONE;
}
if ( 0u != (ADC_ADSTA_AWDIF_MASK & ADCx->ADSTA) )
{
flags |= ADC_STATUS_CONV_COMPARE_DONE;
}
return flags;
}
void ADC_ClearStatus(ADC_Type * ADCx, uint32_t flags)
{
if ( 0u != (ADC_STATUS_CONV_CALIB_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCALIF_MASK;
}
if ( 0u != (ADC_STATUS_JCONV_SLOT_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOCIF_MASK;
}
if ( 0u != (ADC_STATUS_JCONV_SAMPLE_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOSMPIF_MASK;
}
if ( 0u != ( ADC_STATUS_JCONV_SEQ_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOSIF_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SLOT_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCIF_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SAMPLE_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_EOSMPIF_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SEQ_DONE & flags) )
{
ADCx->ADSTA = ADC_ADSTA_EOSIF_MASK;
}
if ( 0u != (ADC_STATUS_CONV_COMPARE_DONE & flags) )
{
ADCx->ADSTA = ADC_ADSTA_AWDIF_MASK;
}
}
uint32_t ADC_GetChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags)
{
uint32_t tmp32 = ADCx->ADDATA;
*channel = (tmp32 & (ADC_ADDATA_CHANNELSEL_MASK | ADC_ADDATA_CHANNELSELH_MASK) ) >> ADC_ADDATA_CHANNELSEL_SHIFT;
if (flags)
{
*flags = (tmp32 & (ADC_ADDATA_OVERRUN_MASK | ADC_ADDATA_VALID_MASK) ) >> ADC_ADDATA_OVERRUN_SHIFT;
}
return (tmp32 & ADC_ADDATA_DATA_MASK ) >> ADC_ADDATA_DATA_SHIFT;
}
uint32_t ADC_GetSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags)
{
uint32_t tmp32 = ADCx ->ADDR[slot];
if (flags)
{
*flags = (tmp32 & (ADC_ADDR_OVERRUN_MASK | ADC_ADDR_VALID_MASK) ) >> ADC_ADDR_OVERRUN_SHIFT;
}
return (tmp32 & ADC_ADDR_DATA_MASK ) >> ADC_ADDR_DATA_SHIFT;
}
uint32_t ADC_GetExtChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags)
{
uint32_t tmp32 = ADCx->JADDATA;
*channel = (tmp32 & ADC_JADDATA_JCHANNELSEL_MASK) >> ADC_JADDATA_JCHANNELSEL_SHIFT;
if (flags)
{
*flags = (tmp32 & (ADC_JADDATA_JOVERRUN_MASK | ADC_JADDATA_JVALID_MASK) ) >> ADC_JADDATA_JOVERRUN_SHIFT;
}
return (tmp32 & ADC_JADDATA_JDATA_MASK ) >> ADC_JADDATA_JDATA_SHIFT;
}
uint32_t ADC_GetExtSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags)
{
uint32_t tmp32 = ADCx ->JDR[slot];
if (flags)
{
*flags = (tmp32 & (ADC_JDR_JOVERRUN_MASK | ADC_JDR_JVALID_MASK) ) >> ADC_JDR_JOVERRUN_SHIFT;
}
return (tmp32 & ADC_JDR_JDATA_MASK ) >> ADC_JDR_JDATA_SHIFT;
}
void ADC_SetChnSampleTime(ADC_Type * ADCx, uint32_t channel, ADC_SampleTime_Type sample_time)
{
if (channel < 8u)
{
ADCx->SMPR1 = (ADCx->SMPR1 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
}
else if (channel-8 < 8u)
{
channel-= 8u;
ADCx->SMPR2 = (ADCx->SMPR2 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
}
else
{
channel-= 16u;
ADCx->SMPR3 = (ADCx->SMPR3 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
}
}
void ADC_EnableHwTrigger(ADC_Type * ADCx, ADC_HwTriggerConf_Type * conf)
{
if ( !conf )
{
ADCx->ADCR &= ~ADC_ADCR_TRGEN_MASK;
return;
}
/* Enable the hardware trigger. */
ADCx->ADCR = ( ADCx->ADCR & ~( ADC_ADCR_TRGSHIFT_MASK | ADC_ADCR_TRGEDGE_MASK) )
| ADC_ADCR_TRGEN_MASK
| ADC_ADCR_TRGSHIFT(conf->DelayCycle)
| ADC_ADCR_TRGEDGE(conf->Edge)
;
}
void ADC_EnableSeqSlotFixed(ADC_Type * ADCx, uint32_t seq_slot, ADC_SeqFixedDirection_Type dir)
{
ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK;
/* enable fixed channel. */
ADCx->ADCHS = seq_slot;
/* configure the scan direction. */
ADCx->ADCR = (ADCx->ADCR & ~ADC_ADCR_SCANDIR_MASK)
| ADC_ADCR_SCANDIR(dir)
;
}
void ADC_EnableSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel)
{
if (slot_idx > 16u)
{
return; /* the available range of seq length is within 16u. */
}
/* enable any channel sequence mode. */
ADCx->ANYCR |= ADC_ANYCR_CHANYMDEN_MASK;
/* select the any slots number. */
ADCx->ANYCFG = ADC_ANYCFG_CHANYNUM(slot_idx);
uint32_t offset = slot_idx;
/* fill the channel into each slot. */
if (slot_idx < 8u)
{
ADCx->CHANY0 = (ADCx->CHANY0 & ~( 0xFF << (offset * 4u) )) | ( (channel & 0xF) << (offset * 4u) );
}
else
{
ADCx->CHANY1 = (ADCx->CHANY1 & ~( 0xFF << ((offset - 8u) * 4u) )) | ( (channel & 0xF) << ((offset - 8u) * 4u) );
}
ADCx->ANYCFG = (ADCx->ANYCFG & ~( 0x01 << (offset + 8u) )) | ( (channel & 0x10) << (offset + 8u) );
}
void ADC_EnableExtSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel)
{
if (slot_idx > 4u)
{
return; /* the available range of seq length is within 4u. */
}
/* enable the inject channel sequence mode. */
ADCx->ANYCR |= ADC_ANYCR_JCEN_MASK;
/* select the inject slot number. */
ADCx->JSQR = ADC_JSQR_JNUM(slot_idx);
/* fill the channels into each slot of inject sequence. */
uint32_t offset = slot_idx;
ADCx->JSQR = (ADCx->JSQR &~(0x1F << (5u * offset)))| (channel & 0x1F) << (5u * offset);
}
void ADC_EnableAutoExtSeqSlot(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ANYCR |= ADC_ANYCR_JAUTO_MASK;
}
else
{
ADCx->ANYCR &= ~ADC_ANYCR_JAUTO_MASK;
}
}
void ADC_DoExtSeqSlotSwTrigger(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ANYCR |= ADC_ANYCR_JADST_MASK;
}
else
{
ADCx->ANYCR &= ~ADC_ANYCR_JADST_MASK;
}
}
void ADC_SetExtSlotCalibParam(ADC_Type * ADCx, uint32_t slot, uint32_t value)
{
ADCx->JOFR[slot] = ADC_JOFR_JOFFSET(value);
}
void ADC_DoSwTrigger(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCR |= ADC_ADCR_ADST_MASK;
}
else
{
ADCx->ADCR &= ~ADC_ADCR_ADST_MASK;
}
}
void ADC_EnableHwComp(ADC_Type * ADCx, ADC_HwCompConf_Type * conf)
{
if ( !conf )
{
/* disable the hardware compare feature for both regular & any seq. */
ADCx->ADCFG &= ~ADC_ADCFG_AWDEN_MASK;
return;
}
/* enable the hardware compare feature. */
ADCx->ADCFG |= ADC_ADCFG_AWDEN_MASK;
/* setup the compare channel. */
ADCx->ADCR = (ADCx->ADCR & ~(ADC_ADCR_CMPCHL_MASK | ADC_ADCR_CMPCHH_MASK))
| ADC_ADCR_CMPCHL(0xf & conf->ChnNum)
| ADC_ADCR_CMPCHH(conf->ChnNum >> 4)
;
/* setup the compare boundary. */
ADCx->ADCMPR = ADC_ADCMPR_CMPLDATA(conf->LowLimit)
| ADC_ADCMPR_CMPHDATA(conf->HighLimit)
;
}
void ADC_DoAutoCalib(ADC_Type * ADCx)
{
ADCx->ANYCR |= ADC_ANYCR_ADCAL_MASK;
while(0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_EOCALIF_MASK));
/* clear the status. */
ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCALIF_MASK;
}
uint32_t ADC_GetCalibFactor(ADC_Type * ADCx, uint32_t * factor)
{
for (uint32_t i = 0; i < 17; i++)
{
ADCx->ADDATA = ADC_ADDATA_DATA((i + 1) << 9);
factor[i]= ADCx->ADDATA & 0x1FF;
while ( 0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_FREOCIF_MASK))
{}
ADCx->ADSTAEXT |= ADC_ADSTAEXT_FREOCIF_MASK;
}
return 1;
}
void ADC_SetCalibFactor(ADC_Type * ADCx, uint32_t * factor)
{
for (uint32_t i = 0; i < 17; i++)
{
ADCx->ADDATA = factor[i] | ( (i + 1) << 9);
while ( 0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_FREOCIF_MASK))
{}
ADCx->ADSTAEXT |= ADC_ADSTAEXT_FREOCIF_MASK;
}
}
void ADC_SetOverSample(ADC_Type * ADCx, ADC_OverSampleConf_Type *conf)
{
if (!conf)
{
return;
}
ADCx->ADCFG2 = ( ADCx->ADCFG2 & ~ (ADC_ADCFG2_ROVSE_MASK |ADC_ADCFG2_JOVSE_MASK | ADC_ADCFG2_OVSR_MASK | ADC_ADCFG2_OVSS_MASK | ADC_ADCFG2_TROVS_MASK) )
| ADC_ADCFG2_OVSR(conf->Ratio)
| ADC_ADCFG2_OVSS(conf->Div)
| ADC_ADCFG2_TROVS(conf->Mode)
| ADC_ADCFG2_JOVSE(conf->injectOverSampleMode)
;
}
void ADC_ResetAllSlot(ADC_Type * ADCx)
{
/* wait for the latest conversion done. */
while( (0u != (ADCx->ADSTA & ADC_ADSTA_BUSY_MASK)) | (0u != (ADCx->ADSTAEXT & ADC_ADSTAEXT_JBUSY_MASK)) )
{}
/* disable the regular channel. */
ADCx->ADCHS = 0x00;
/* disable the any sequence. */
ADCx->CHANY0 = 0x00;
ADCx->CHANY1 = 0x00;
/* reset the inject slot . */
ADCx->JSQR = 0x00;
/* disable inject conversion. */
ADCx->ANYCR &= ~ADC_ANYCR_JCEN_MASK;
/* disable sequence conversion. */
ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK;
/* stop adc conversion. */
ADCx->ADCR |= ADC_ADCR_ADST_MASK;
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_ADC_H__
#define __HAL_ADC_H__
#include "hal_common.h"
/*!
* @addtogroup ADC
* @{
*/
/*!
* @brief ADC driver version number.
*/
#define ADC_DRIVER_VERSION 1u /*!< adc_1. */
/*!
* @addtogroup ADC_STATUS
* Define ADC status.
* @{
*/
#define ADC_STATUS_CONV_SLOT_DONE (1u << 0u) /*!< Status flag when ADC slot conversion done. */
#define ADC_STATUS_CONV_SAMPLE_DONE (1u << 1u) /*!< Status flag when ADC sample done. */
#define ADC_STATUS_CONV_SEQ_DONE (1u << 2u) /*!< Status flag when ADC sequence conversion done. */
#define ADC_STATUS_CONV_COMPARE_DONE (1u << 3u) /*!< Status flag when ADC compare done. */
#define ADC_STATUS_CONV_CALIB_DONE (1u << 4u) /*!< Status flag when ADC calibration done */
#define ADC_STATUS_JCONV_SLOT_DONE (1u << 5u) /*!< Status flag when ADC inject slot conversion done. */
#define ADC_STATUS_JCONV_SAMPLE_DONE (1u << 6u) /*!< Status flag when ADC inject sample done. */
#define ADC_STATUS_JCONV_SEQ_DONE (1u << 7u) /*!< Status flag when ADC inject sequence conversion done. */
/*!
* @}
*/
/*!
* @addtogroup ADC_INT
* ADC interrupt define.
* @{
*/
#define ADC_INT_CONV_SLOT_DONE (1u << 0u) /*!< Interrupt when ADC slot conversion done. */
#define ADC_INT_CONV_SAMPLE_DONE (1u << 1u) /*!< Interrupt enable when ADC sample done. */
#define ADC_INT_CONV_SEQ_DONE (1u << 2u) /*!< Interrupt enable when ADC sequence conversion done. */
#define ADC_INT_CONV_COMPARE_DONE (1u << 3u) /*!< Interrupt enable when ADC compare done. */
#define ADC_INT_CONV_CALIB_DONE (1u << 4u) /*!< Interrupt enable when ADC calibration done */
#define ADC_INT_JCONV_SLOT_DONE (1u << 5u) /*!< Interrupt enable when ADC inject slot conversion done. */
#define ADC_INT_JCONV_SAMPLE_DONE (1u << 6u) /*!< Interrupt enable when ADC inject sample done. */
#define ADC_INT_JCONV_SEQ_DONE (1u << 7u) /*!< Interrupt enable when ADC inject sequence conversion done. */
/*!
* @}
*/
/*!
* @addtogroup ADC_RESULT_FLAGS
* Define ADC Convert result flags.
* @{
*/
#define ADC_CONV_RESULT_FLAG_OVERRUN (1u << 0u) /*!< Result flag when adc conversion result is overrun. */
#define ADC_CONV_RESULT_FLAG_VALID (1u << 1u) /*!< Result flag when adc conversion result valid. */
/*!
* @}
*/
/*!
* @brief ADC Resolution type.
*
* Select ADC conversion data resolution.
*/
typedef enum
{
ADC_Resolution_Alt0 = 0u, /*!< source 0 as a resolution source for ADC. */
ADC_Resolution_Alt1 = 1u, /*!< source 1 as a resolution source for ADC. */
ADC_Resolution_Alt2 = 2u, /*!< source 2 as a resolution source for ADC. */
ADC_Resolution_Alt3 = 3u, /*!< source 3 as a resolution source for ADC. */
ADC_Resolution_Alt4 = 4u, /*!< source 4 as a resolution source for ADC. */
} ADC_Resolution_Type;
/*!
* @brief ADC HwTriggerEdge type.
*
* Use hardware trigger in ADC, this trigger edge must be rising edge.
*/
typedef enum
{
ADC_HwTriggerEdge_RisingEdge = 2u, /*!< Rising edge trigger. */
} ADC_HwTriggerEdge_Type;
/*!
* @brief ADC HwTriggerDelayCycle type.
*
* After the hardware trigger signal is generated, delay N PCLK2 clock cycles before starting the first sample.
*/
typedef enum
{
ADC_HwTriggerDelayCycle_0 = 0u, /*!< Delay 0 cycle. */
ADC_HwTriggerDelayCycle_4 = 1u, /*!< Delay 4 cycle. */
ADC_HwTriggerDelayCycle_16 = 2u, /*!< Delay 16 cycle. */
ADC_HwTriggerDelayCycle_32 = 3u, /*!< Delay 32 cycle. */
ADC_HwTriggerDelayCycle_64 = 4u, /*!< Delay 64 cycle. */
ADC_HwTriggerDelayCycle_128 = 5u, /*!< Delay 128 cycle. */
ADC_HwTriggerDelayCycle_256 = 6u, /*!< Delay 256 cycle. */
ADC_HwTriggerDelayCycle_512 = 7u, /*!< Delay 512 cycle. */
} ADC_HwTriggerDelayCycle_Type;
/*!
* @brief ADC Align type.
*
* Choose to store the converted data as left-aligned or right-aligned.
*/
typedef enum
{
ADC_Align_Right = 0u, /*!< Data right align. */
ADC_Align_Left = 1u, /*!< Data left align. */
} ADC_Align_Type;
/*!
* @brief ADC SeqFixedDirection type.
*
* In single-cycle scan or continuous scan mode, set the order of scan channels.
*/
typedef enum
{
ADC_SeqFixedDirection_LowFirst = 0u, /*!< ADC scan direction from low channel to high channel. */
ADC_SeqFixedDirection_HighFirst = 1u, /*!< ADC scan direction from high channel to low channel. */
} ADC_SeqFixedDirection_Type;
/*!
* @brief ADC ConvMode type.
*
* Select the adc channel or sequence convert mode.
*/
typedef enum
{
ADC_ConvMode_SingleSlot = 0u, /*!< Run the conversion by channel. */
ADC_ConvMode_SeqOneTime = 1u, /*!< Run the conversion by sequence once. */
ADC_ConvMode_SeqContinues = 2u, /*!< Run the conversion by sequence again and again. */
} ADC_ConvMode_Type;
/*!
* @brief ADC SampleTime type.
*
* Select channel sample time.
*/
typedef enum
{
ADC_SampleTime_Alt0 = 0u, /*!< Channel sample time mode 0 . */
ADC_SampleTime_Alt1 = 1u, /*!< Channel sample time mode 1 . */
ADC_SampleTime_Alt2 = 2u, /*!< Channel sample time mode 2 . */
ADC_SampleTime_Alt3 = 3u, /*!< Channel sample time mode 3 . */
ADC_SampleTime_Alt4 = 4u, /*!< Channel sample time mode 4 . */
ADC_SampleTime_Alt5 = 5u, /*!< Channel sample time mode 5 . */
ADC_SampleTime_Alt6 = 6u, /*!< Channel sample time mode 6 . */
ADC_SampleTime_Alt7 = 7u, /*!< Channel sample time mode 7 . */
ADC_SampleTime_Alt8 = 8u, /*!< Channel sample time mode 8 . */
ADC_SampleTime_Alt9 = 9u, /*!< Channel sample time mode 9 . */
ADC_SampleTime_Alt10 = 10u, /*!< Channel sample time mode 10. */
ADC_SampleTime_Alt11 = 11u, /*!< Channel sample time mode 11. */
ADC_SampleTime_Alt12 = 12u, /*!< Channel sample time mode 12. */
ADC_SampleTime_Alt13 = 13u, /*!< Channel sample time mode 13. */
ADC_SampleTime_Alt14 = 14u, /*!< Channel sample time mode 14. */
ADC_SampleTime_Alt15 = 15u, /*!< Channel sample time mode 15. */
} ADC_SampleTime_Type;
/*!
* @brief ADC SingDiffConvMode type.
*
* Select ADC channel single-ended or difference conversion mode.
*/
typedef enum
{
ADC_SingleDiffConvMode_SingleEnd = 1u, /*!< Channel conversion mode is single-ended conversion. */
ADC_SingleDiffConvMode_Diff = 2u, /*!< Channel conversion mode is differential conversion. */
ADC_SingleDiffConvMode_PseudoDiff = 3u, /*!< Channel conversion mode is pseudo-difference conversion. */
}ADC_SingleDiffConvMode_Type;
/*!
* @brief ADC SingleConvVref type.
*
* Select the reference voltage for single-ended conversion mode.
*/
typedef enum
{
ADC_SingleConvVref_Internal = 1u, /*!< Select the internal reference voltage as the reference voltage for single-ended conversion. */
ADC_SingleConvVref_External = 0u, /*!< Select the external reference voltage as the reference voltage for single-ended conversion. */
}ADC_SingleConvVref_Type;
/*!
* @brief ADC DiffPair type.
*
* Select channel source as ADC differential or pseudo-difference conversion channels.
*/
typedef enum
{
ADC_DiffChnPair_0_1 = 1u, /*!< Select channel 0 and 1 for a group of differential or pseudo-difference channels. */
ADC_DiffChnPair_2_3 = 2u, /*!< Select channel 2 and 3 for a group of differential or pseudo-difference channels */
ADC_DiffChnPair_4_5 = 4u, /*!< Select channel 4 and 5 for a group of differential or pseudo-difference channels. */
ADC_DiffChnPair_6_7 = 8u, /*!< Select channel 6 and 7 for a group of differential or pseudo-difference channels. */
}ADC_DiffPair_Type;
/*!
* @brief ADC OverSampleRatio type.
*
* Select ADC oversampling rate, to confirm the number of conversions performed by ADC, the sum of these conversion data is calculated as ADC oversampling conversion data (before potential shift).
*/
typedef enum
{
ADC_OverSampleRatio_2 = 0u, /*!< Select the oversample ratio of 2, 2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
ADC_OverSampleRatio_4 = 1u, /*!< Select the oversample ratio of 4, 4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
ADC_OverSampleRatio_8 = 2u, /*!< Select the oversample ratio of 8, 8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
ADC_OverSampleRatio_16 = 3u, /*!< Select the oversample ratio of 16, 16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
ADC_OverSampleRatio_32 = 4u, /*!< Select the oversample ratio of 32, 32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
ADC_OverSampleRatio_64 = 5u, /*!< Select the oversample ratio of 64, 64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
ADC_OverSampleRatio_128 = 6u, /*!< Select the oversample ratio of 128,128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
ADC_OverSampleRatio_256 = 7u, /*!< Select the oversample ratio of 256, 256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */
}ADC_OverSampleRatio_Type;
/*!
* @brief ADC OverSampleDataDiv type.
*
* Select ADC oversampling rate, to confirm the number of conversions performed by ADC, the sum of these conversion data is calculated as ADC oversampling conversion data (before potential shift).
*/
typedef enum
{
ADC_OverSampleDataDiv_0 = 0u, /*!< Select ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_1 = 1u, /*!< Select ADC oversampling 1 shift (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_2 = 2u, /*!< Select ADC oversampling 2 shift (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_3 = 3u, /*!< Select ADC oversampling 3 shift (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_4 = 4u, /*!< Select ADC oversampling 4 shift (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_5 = 5u, /*!< Select ADC oversampling 5 shift (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_6 = 6u, /*!< Select ADC oversampling 6 shift (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_7 = 7u, /*!< Select ADC oversampling 7 shift (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data). */
ADC_OverSampleDataDiv_8 = 8u, /*!< Select ADC oversampling 8 shift (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data). */
}ADC_OverSampleDataDiv_Type;
/*!
* @brief ADC ADC_OverSampleTrigMode type.
*
* Select ADC oversampling continuous or discontinuous mode
*/
typedef enum
{
ADC_OverSampleTriggerMode_Multi = 0u, /*!< All conversions of oversampling ratio are done from 1 trigger. */
ADC_OverSampleTriggerMode_Single = 1u, /*!< Each conversion of oversampling ratio needs a trigger. */
}ADC_OverSampleTriggerMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_Init() to initialize the ADC module.
*/
typedef struct
{
ADC_Resolution_Type Resolution; /*!< Specify the available bits for the conversion result data. */
ADC_Align_Type Align; /*!< Specify the data alignment. */
ADC_ConvMode_Type ConvMode; /*!< Specify the adc conversion mode. */
ADC_SingleDiffConvMode_Type SingleDiffMode; /*!< Select ADC channel single-ended or difference conversion mode.*/
ADC_DiffPair_Type DiffPair; /*!< Select channel source as ADC differential or pseudo-difference conversion channels. */
ADC_SingleConvVref_Type SingleVolt; /*!< Select the single-ended conversion vref source. */
} ADC_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_EnableHwTrigger() to initialize the ADC hardware trigger module.
*/
typedef struct
{
ADC_HwTriggerEdge_Type Edge; /*!< Select the trigger edge. */
ADC_HwTriggerDelayCycle_Type DelayCycle; /*!< Select the hardware trigger shift sample. */
} ADC_HwTriggerConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_EnableHwComp() to enable the ADC windows compare mode.
*/
typedef struct
{
uint32_t ChnNum; /*!< Select the channel number binding to the compare. */
uint32_t HighLimit; /*!< The comparator high limit. */
uint32_t LowLimit; /*!< The comparator low limit. */
} ADC_HwCompConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* This function just only used in any channel or inject channel.
* when calling the @ref ADC_SetOverSample() to initialize the ADC oversample module.
*/
typedef struct
{
ADC_OverSampleRatio_Type Ratio; /*!< Configures the oversampling ratio. */
ADC_OverSampleDataDiv_Type Div; /*!< Configures the division coefficient for the Oversampler. */
ADC_OverSampleTriggerMode_Type Mode; /*!< Select the oversample trigger mode. */
bool injectOverSampleMode; /*!< Whether injection channel oversampling is enable, ture is enable, false is disable. */
}ADC_OverSampleConf_Type;
/*!
* @brief Initialize the ADC module.
*
* @param ADCx ADC instance.
* @param init Pointer to the initialization structure. See to @ref ADC_Init_Type.
* @return None.
*/
void ADC_Init(ADC_Type * ADCx, ADC_Init_Type * init);
/*!
* @brief Enable the ADC module.
*
* The ADC module should be enabled before conversion data.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void ADC_Enable(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable Temperature sensor from the ADC module.
*
* The module should be enabled when Using the built-in temperature sensor to
* detect temperature changes inside the device.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void ADC_EnableTempSensor(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable Voltage sensor from the ADC module.
*
* The module should be enabled when using internal reference voltage .
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void ADC_EnableVoltSensor(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable the DMA from the ADC module.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the DMA, 'false' to disable the DMA.
* @return None.
*/
void ADC_EnableDMA(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable interrupts of the ADC module.
*
* @param ADCx ADC instance.
* @param interrupts Interrupt code masks.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void ADC_EnableInterrupts(ADC_Type * ADCx, uint32_t interrupts, bool enable);
/*!
* @brief Get the current status flags of the ADC module.
*
* @param ADCx ADC instance.
* @return Status flags.
*/
uint32_t ADC_GetStatus(ADC_Type * ADCx);
/*!
* @brief Clear the status flags of the ADC module.
*
* @param ADCx ADC instance.
* @param flags The mask codes of the indicated interrupt flags to be cleared.
* @return None.
*/
void ADC_ClearStatus(ADC_Type * ADCx, uint32_t flags);
/*!
* @brief Get the channel convert data from the ADC module.
*
* @param ADCx ADC instance.
* @param channel The convert channel.
* @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS.
* @return The data value.
*/
uint32_t ADC_GetChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags);
/*!
* @brief Get the indication slot conversion data from the ADC module.
*
* @param ADCx ADC instance.
* @param slot the adc conversion slot.
* @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS.
* @return The data value.
*/
uint32_t ADC_GetSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags);
/*!
* @brief Get the inject channel convert data from the ADC module.
*
* @param ADCx ADC instance.
* @param channel The convert channel.
* @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS.
* @return The data value.
*/
uint32_t ADC_GetExtChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags);
/*!
* @brief Get the indication external slot convert data from the ADC module.
*
* @param ADCx ADC instance.
* @param slot the adc external slot.
* @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS.
* @return The data value.
*/
uint32_t ADC_GetExtSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags);
/*!
* @brief Configuration channel sample time of the ADC module.
*
* @param ADCx ADC instance.
* @param channel the adc convert channel.
* @param sampletime the adc channel sample time
* @return None.
*/
void ADC_SetChnSampleTime(ADC_Type * ADCx, uint32_t channel, ADC_SampleTime_Type sample_time);
/*!
* @brief Enable hardware trigger from the ADC module.
*
* The ADC module should be enabled before using hardware trrigger function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param conf Select the hardware trigger source. See to @ref ADC_HwTrgConf_Type.
* @return None.
*/
void ADC_EnableHwTrigger(ADC_Type * ADCx, ADC_HwTriggerConf_Type * conf);
/*!
* @brief Enable fixed slot sequence conversion from the ADC module.
*
* The ADC module should be enabled before regular sequence function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param seq_slot the fixed channel, it can be ascending or descending.
* @param seq_direction the sequence fixed scan direction.
* @return None.
*/
void ADC_EnableSeqSlotFixed(ADC_Type * ADCx, uint32_t seq_slot, ADC_SeqFixedDirection_Type dir);
/*!
* @brief Enable sequence conversion from the ADC module.
*
* The ADC module should be enabled before Any sequence function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param slot_idx the sequence slot index.
* @param channel the conversion channel, it will be placed in each slot.
* @return None.
*/
void ADC_EnableSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel);
/*!
* @brief Enable external sequence conversion from the ADC module.
*
* The ADC module should be enabled before sequence conversion function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param slot_idx the sequence slot index.
* @param channel the conversion channel, it will be placed in each slot.
* @return None.
*/
void ADC_EnableExtSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel);
/*!
* @brief Enable Inject sequence auto conversion from the ADC module.
* the sequence conversion done, the inject sequence start conversion.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the ADC start inject sequence convert, 'false' to disable.
* @return None.
*/
void ADC_EnableAutoExtSeqSlot(ADC_Type * ADCx, bool enable);
/*!
* @brief Do external chanenel sequence conversion software trigger.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the ADC start inject channel convert, 'false' to disable.
* @return None.
*/
void ADC_DoExtSeqSlotSwTrigger(ADC_Type * ADCx, bool enable);
/*!
* @brief Set inject chanenel data offset compensation.
*
* @param ADCx ADC instance.
* @param value difference between actual input value and converted value.
* @param slot the inject slot.
* @return None.
*/
void ADC_SetExtSlotCalibParam(ADC_Type * ADCx, uint32_t slot, uint32_t value);
/*!
* @brief Enable window comparison from the ADC module.
*
* The ADC module should be enabled before using analog watchdog function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param conf Pointer to the initialization structure. See to @ref ADC_HwCompConf_Type.
* @return None.
*/
void ADC_EnableHwComp(ADC_Type * ADCx, ADC_HwCompConf_Type * conf);
/*!
* @brief Do soft trigger.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the ADC start convert, 'false' to disable.
* @return None.
*/
void ADC_DoSwTrigger(ADC_Type * ADCx, bool enable);
/*!
* @brief Do auto self-calibration.
*
* @param ADCx ADC instance.
* @return None.
*/
void ADC_DoAutoCalib(ADC_Type * ADCx);
/*!
* @brief Get Calibration factor through auto calibration.
*
* when you use the use this api to get the calibration factor when you write the calibration through the register.
* @param ADCx ADC instance.
* @param factor from self-calibration,the calibration parameter consists of 17 9-digit numbers.
* @param return 1;
*/
uint32_t ADC_GetCalibFactor(ADC_Type * ADCx, uint32_t * factor);
/*!
* @brief Set Calibration factor through register.
*
* when you use the use this api to write the calibration factor when you write the calibration through the register.
* @param ADCx ADC instance.
* @param factor the calibration parameters from ADC_GetCalibFactor().
* @return None.
*/
void ADC_SetCalibFactor(ADC_Type * ADCx, uint32_t * factor);
/*!
* @brief Set Set OverSample mode.
*
* Average value of converted data using hardware implementation.
* @param ADCx ADC instance.
* @param conf Pointer to the initialization structure. See to @ref ADC_OverSampleConf_Type.
* @return None.
*/
void ADC_SetOverSample(ADC_Type * ADCx, ADC_OverSampleConf_Type *conf);
/*!
* @brief Reset all the slot conversion.
*
* @param ADCx ADC instance.
* @return None.
*/
void ADC_ResetAllSlot(ADC_Type * ADCx);
/*!
*@}
*/
#endif /*__HAL_ADC_H__. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_COMMON_H__
#define __HAL_COMMON_H__
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hal_device_registers.h"
#endif /* __HAL_COMMON_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_comp.h"
static __IO uint32_t * COMP_GetCSR(COMP_Type * COMPx, uint32_t channel)
{
__IO uint32_t * csr[] =
{
&COMPx->CSR[0],
&COMPx->CSR[1],
&COMPx->CSR3,
};
return csr[channel];
}
/* init comp. */
void COMP_Init(COMP_Type * COMPx, uint32_t channel, COMP_Init_Type * init)
{
if ( channel < COMP_CHANNEL_NUM )
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
*csr = (*csr & ~(COMP_CSR_HYST_MASK | COMP_CSR_OUTSEL_MASK | COMP_CSR_INPSEL_MASK | COMP_CSR_INMSEL_MASK | COMP_CSR_MODE_MASK) )
| COMP_CSR_HYST(init->Hysteresis)
| COMP_CSR_OUTSEL(init->OutMux)
| COMP_CSR_INPSEL(init->PosInMux)
| COMP_CSR_INMSEL(init->InvInMux)
| COMP_CSR_MODE(init->Speed)
;
}
}
/* enable comp. */
void COMP_Enable(COMP_Type * COMPx, uint32_t channel, bool enable)
{
if ( channel < COMP_CHANNEL_NUM )
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
if ( true == enable )
{
*csr |= COMP_CSR_EN_MASK;
}
else
{
*csr &= ~COMP_CSR_EN_MASK;
}
}
}
/* lock. */
void COMP_Lock(COMP_Type * COMPx, uint32_t channel)
{
if ( channel < COMP_CHANNEL_NUM )
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
*csr |= COMP_CSR_LOCK_MASK;
}
}
/* get output status. */
bool COMP_GetOutputStatus(COMP_Type * COMPx, uint32_t channel)
{
if ( channel < COMP_CHANNEL_NUM )
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
if ( 0u != ( COMP_CSR_OUT_MASK & (*csr) ) )
{
return true;
}
else
{
return false; /* normal input voltage lower than inverting input. */
}
}
else
{
return false;
}
}
/* enable external vref. */
void COMP_EnableExtVrefConf(COMP_Type * COMPx, COMP_ExtVrefConf_Type * conf)
{
if ( NULL == conf) /* disable the ext vref. */
{
COMPx->CRV &= ~COMP_CRV_CRVEN_MASK;
}
else /* init & enable ext vref. */
{
COMPx->CRV = (COMPx->CRV & ~(COMP_CRV_CRVSRC_MASK | COMP_CRV_CRVSEL_MASK | COMP_CRV_CRVEN_MASK) )
| COMP_CRV_CRVSRC(conf->VrefSource)
| COMP_CRV_CRVSEL(conf->Volt)
| COMP_CRV_CRVEN_MASK
;
}
}
/* enable round robin (poll compare). */
void COMP_EnableRoundRobinConf(COMP_Type * COMPx, uint32_t channel, COMP_RoundRobinConf_Type * conf)
{
if ( channel < COMP_CHANNEL_NUM )
{
if ( NULL == conf )
{
COMPx->POLL[channel] &= ~COMP_POLL_POLLEN_MASK;
}
else
{
COMPx->POLL[channel] = (COMPx->POLL[channel] & ~(COMP_POLL_PERIOD_MASK | COMP_POLL_FIXN_MASK | COMP_POLL_POLLCH_MASK | COMP_POLL_POLLEN_MASK) )
| COMP_POLL_PERIOD(conf->Period)
| COMP_POLL_FIXN(conf->EnableInvInFix)
| COMP_POLL_POLLCH(conf->ChnGroup)
| COMP_POLL_POLLEN_MASK;
;
}
}
}
/* get round robin (poll compare) status. */
bool COMP_GetRoundRobinOutStatus(COMP_Type * COMPx, uint32_t channel, COMP_InMux_Type pos_in)
{
if ( channel < COMP_CHANNEL_NUM )
{
uint32_t mask = COMP_POLL_POUT(1u << ( (uint32_t)pos_in - 1u ) );
if ( 0u != (COMPx->POLL[channel] & mask) )
{
return true;
}
else
{
return false;
}
}
else
{
return false;
}
}
/* set output filter. */
void COMP_SetOutFilter(COMP_Type * COMPx, uint32_t channel, COMP_OutFilter_Type filter)
{
if (channel < COMP_CHANNEL_NUM)
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
*csr = (*csr & ~COMP_CSR_OFLT_MASK) | COMP_CSR_OFLT(filter);
}
}
/* enable output invert. */
void COMP_EnableOutInvert(COMP_Type * COMPx, uint32_t channel, bool invert)
{
if (channel < COMP_CHANNEL_NUM)
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
if(true == invert)
{
*csr = (*csr & ~COMP_CSR_POL_MASK) | COMP_CSR_POL(1u);
}
else
{
*csr = (*csr & ~COMP_CSR_POL_MASK) | COMP_CSR_POL(0u);
}
}
}
/* enable bypass output. */
void COMP_EnableBypassOutput(COMP_Type * COMPx, uint32_t channel, bool enable)
{
if (channel < COMP_CHANNEL_NUM)
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
if (enable)
{
*csr |= COMP_CSR_OUTANASEL_MASK;
}
else
{
*csr &= ~COMP_CSR_OUTANASEL_MASK;
}
}
}
void COMP_EnableWindow(COMP_Type * COMPx, uint32_t channel, bool enable)
{
if (channel < COMP_CHANNEL_NUM)
{
__IO uint32_t * csr = COMP_GetCSR(COMPx, channel);
if (enable)
{
*csr |= COMP_CSR_WE_MASK;
}
else
{
*csr &= ~COMP_CSR_WE_MASK;
}
}
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_COMP_H__
#define __HAL_COMP_H__
#include "hal_common.h"
/*!
* @addtogroup COMP
* @{
*/
/*!
* @brief COMP driver version number.
*/
#define COMP_DRIVER_VERSION 1u /*!< COMP_1. */
/*!
* @brief COMP number.
*/
#define COMP_CHANNEL_NUM 3u
/*!
* @brief COMP output filter type.
*
* If the compare result keeps n APB Clocks unchanged, the output is valid.
*/
typedef enum
{
COMP_OutFilter_1 = 0x00, /*!< 1 PCLK filter. */
COMP_OutFilter_2 = 0x01, /*!< 2 PCLK filter. */
COMP_OutFilter_4 = 0x02, /*!< 4 PCLK filter. */
COMP_OutFilter_8 = 0x03, /*!< 8 PCLK filter. */
COMP_OutFilter_16 = 0x04, /*!< 16 PCLK filter. */
COMP_OutFilter_32 = 0x05, /*!< 32 PCLK filter. */
COMP_OutFilter_64 = 0x06, /*!< 64 PCLK filter. */
COMP_OutFilter_128 = 0x07, /*!< 128 PCLK filter. */
} COMP_OutFilter_Type;
/*!
* @brief COMP hysteresis type.
*
* If V(InvInput) > V(PosInput), the compare result is high, if V(InvInput) < (V(PosInput) - hysteresis), the compare result is low.
*/
typedef enum
{
COMP_Hysteresis_Alt0 = 0x00, /*!< Hysteresis alt 0. */
COMP_Hysteresis_Alt1 = 0x01, /*!< Hysteresis alt 1. */
COMP_Hysteresis_Alt2 = 0x02, /*!< Hysteresis alt 2. */
COMP_Hysteresis_Alt3 = 0x03, /*!< Hysteresis alt 3. */
} COMP_Hysteresis_Type;
/*!
* @brief COMP output mux type.
*/
typedef enum
{
COMP_OutMux_Alt0 = 0x00, /*!< Output mux alt 0. */
COMP_OutMux_Alt1 = 0x01, /*!< Output mux alt 1. */
COMP_OutMux_Alt2 = 0x02, /*!< Output mux alt 2. */
COMP_OutMux_Alt3 = 0x03, /*!< Output mux alt 3. */
COMP_OutMux_Alt4 = 0x04, /*!< Output mux alt 4. */
COMP_OutMux_Alt5 = 0x05, /*!< Output mux alt 5. */
COMP_OutMux_Alt6 = 0x06, /*!< Output mux alt 6. */
COMP_OutMux_Alt7 = 0x07, /*!< Output mux alt 7. */
COMP_OutMux_Alt8 = 0x08, /*!< Output mux alt 8. */
COMP_OutMux_Alt9 = 0x09, /*!< Output mux alt 0. */
COMP_OutMux_Alt11 = 0x0A, /*!< Output mux alt 1. */
COMP_OutMux_Alt12 = 0x0B, /*!< Output mux alt 2. */
COMP_OutMux_Alt13 = 0x0C, /*!< Output mux alt 3. */
COMP_OutMux_Alt14 = 0x0D, /*!< Output mux alt 4. */
COMP_OutMux_Alt15 = 0x0E, /*!< Output mux alt 5. */
} COMP_OutMux_Type;
/*!
* @brief COMP input Mux type.
*/
typedef enum
{
COMP_InMux_Alt0 = 0x00, /*!< Input mux 0. */
COMP_InMux_Alt1 = 0x01, /*!< Input mux 1. */
COMP_InMux_Alt2 = 0x02, /*!< Input mux 2. */
COMP_InMux_Alt3 = 0x03, /*!< Input mux 3. */
COMP_InMux_Alt4 = 0x04, /*!< Input mux 4. */
COMP_InMux_Alt5 = 0x05, /*!< Input mux 5. */
} COMP_InMux_Type;
/*!
* @brief COMP speed type.
*/
typedef enum
{
COMP_Speed_High = 0x00, /*!< High speed. */
COMP_Speed_Middle = 0x01, /*!< Middle speed. */
COMP_Speed_Low = 0x02, /*!< Low speed. */
COMP_Speed_DeepLow = 0x03, /*!< Deep low speed. */
} COMP_Speed_Type;
/*!
* @brief COMP external reference voltage source type.
*/
typedef enum
{
COMP_ExtVrefSource_VREFINT = 0x00, /*!< Internal reference voltage. */
COMP_ExtVrefSource_VDDA = 0x01, /*!< VDDA voltage. */
} COMP_ExtVrefSource_Type;
/*!
* @brief COMP external reference voltage type.
*/
typedef enum
{
COMP_ExtVrefVolt_Alt0 = 0x00, /*!< External reference voltage alt 0. */
COMP_ExtVrefVolt_Alt1 = 0x01, /*!< External reference voltage alt 1. */
COMP_ExtVrefVolt_Alt2 = 0x02, /*!< External reference voltage alt 2. */
COMP_ExtVrefVolt_Alt3 = 0x03, /*!< External reference voltage alt 3. */
COMP_ExtVrefVolt_Alt4 = 0x04, /*!< External reference voltage alt 4. */
COMP_ExtVrefVolt_Alt5 = 0x05, /*!< External reference voltage alt 5. */
COMP_ExtVrefVolt_Alt6 = 0x06, /*!< External reference voltage alt 6. */
COMP_ExtVrefVolt_Alt7 = 0x07, /*!< External reference voltage alt 7. */
COMP_ExtVrefVolt_Alt8 = 0x08, /*!< External reference voltage alt 8. */
COMP_ExtVrefVolt_Alt9 = 0x09, /*!< External reference voltage alt 9. */
COMP_ExtVrefVolt_Alt10 = 0x0A, /*!< External reference voltage alt 10. */
COMP_ExtVrefVolt_Alt11 = 0x0B, /*!< External reference voltage alt 11. */
COMP_ExtVrefVolt_Alt12 = 0x0C, /*!< External reference voltage alt 12. */
COMP_ExtVrefVolt_Alt13 = 0x0D, /*!< External reference voltage alt 13. */
COMP_ExtVrefVolt_Alt14 = 0x0E, /*!< External reference voltage alt 14. */
COMP_ExtVrefVolt_Alt15 = 0x0F, /*!< External reference voltage alt 15. */
} COMP_ExtVrefVolt_Type;
/*!
* @brief COMP round robin period type.
*
* wait n APB clock to compare next channel.
*/
typedef enum
{
COMP_RoundRobinPeriod_1 = 0x00, /*!< Wait 1 PCLK to compare next channel. */
COMP_RoundRobinPeriod_2 = 0x01, /*!< Wait 2 PCLK to compare next channel. */
COMP_RoundRobinPeriod_4 = 0x02, /*!< Wait 4 PCLK to compare next channel. */
COMP_RoundRobinPeriod_8 = 0x03, /*!< Wait 8 PCLK to compare next channel. */
COMP_RoundRobinPeriod_16 = 0x04, /*!< Wait 16 PCLK to compare next channel. */
COMP_RoundRobinPeriod_32 = 0x05, /*!< Wait 32 PCLK to compare next channel. */
COMP_RoundRobinPeriod_64 = 0x06, /*!< Wait 64 PCLK to compare next channel. */
COMP_RoundRobinPeriod_128 = 0x07, /*!< Wait 128 PCLK to compare next channel. */
} COMP_RoundRobinPeriod_Type;
/*!
* @brief COMP round robin channel Type.
*/
typedef enum
{
COMP_RoundRobinChnGroup_Alt0 = 0x00, /*!< Compare the positive input 1 & 2. */
COMP_RoundRobinChnGroup_Alt1 = 0x01, /*!< Compare the positive input 1, 2 & 3. */
} COMP_RoundRobinChnGroup_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref COMP_Init() to initialize the COMP module.
*/
typedef struct
{
COMP_Hysteresis_Type Hysteresis; /*!< Specify the hysteresis. */
COMP_OutMux_Type OutMux; /*!< Specify the output. */
COMP_InMux_Type PosInMux; /*!< Specify the positive input. */
COMP_InMux_Type InvInMux; /*!< Specify the nagetive input. */
COMP_Speed_Type Speed; /*!< Specify the compare speed. */
} COMP_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref COMP_EnableExtVrefConf() to enable the COMP ext vref.
*/
typedef struct
{
COMP_ExtVrefSource_Type VrefSource; /*!< Specify the Vref source. */
COMP_ExtVrefVolt_Type Volt; /*!< Specify the Vref voltage. */
} COMP_ExtVrefConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref COMP_EnableRoundRobinConf() to enable the COMP round robin.
*/
typedef struct
{
COMP_RoundRobinPeriod_Type Period; /*!< Specify the round robin period. */
bool EnableInvInFix; /*!< Specify the nagetive input fix. */
COMP_RoundRobinChnGroup_Type ChnGroup; /*!< Specify the round robin channel. */
} COMP_RoundRobinConf_Type;
/*!
* @brief Initialize the COMP module.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param init Pointer to the initialization structure. See to @ref COMP_Init_Type.
* @return None.
*/
void COMP_Init(COMP_Type * COMPx, uint32_t channel, COMP_Init_Type * init);
/*!
* @brief Enable the COMP module.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void COMP_Enable(COMP_Type * COMPx, uint32_t channel, bool enable);
/*!
* @brief Keep the COMP settings not changed.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @return None.
*/
void COMP_Lock(COMP_Type * COMPx, uint32_t channel);
/*!
* @brief Get comp output status.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @return output status.
*/
bool COMP_GetOutputStatus(COMP_Type * COMPx, uint32_t channel);
/*!
* @brief Enable the COMP ext Vref.
*
* @param COMPx COMP instance.
* @param init Pointer to the initialization structure. See to @ref COMP_ExtVrefConf_Type, if null, disable ext Vref.
* @return None.
*/
void COMP_EnableExtVrefConf(COMP_Type * COMPx, COMP_ExtVrefConf_Type * conf);
/*!
* @brief Enable polling function.
*
* Enable round robin function, the comp channel can get positive input 1, 2 & 3 status.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param init Pointer to the initialization structure. See to @ref COMP_RoundRobinConf_Type, if null, disable round robin.
* @return None.
*/
void COMP_EnableRoundRobinConf(COMP_Type * COMPx, uint32_t channel, COMP_RoundRobinConf_Type * conf);
/*!
* @brief Get round robin output status.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param pos_in Positive input Mux.
* @return Status of comp channel output level.
*/
bool COMP_GetRoundRobinOutStatus(COMP_Type * COMPx, uint32_t channel, COMP_InMux_Type pos_in);
/*!
* @brief Enable COMP window control.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param enable 'true' to enable window control, 'false' to disable window control.
* @return None.
*/
void COMP_EnableWindow(COMP_Type * COMPx, uint32_t channel, bool enable);
/*!
* @brief Set the output filter.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param filter Output filter, See to @ref COMP_OutFilter_Type.
* @return None.
*/
void COMP_SetOutFilter(COMP_Type * COMPx, uint32_t channel, COMP_OutFilter_Type filter);
/*!
* @brief Enable the out invert.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param enable 'true' to enable the out invert, 'false' to disable the out invert.
* @return None.
*/
void COMP_EnableOutInvert(COMP_Type * COMPx, uint32_t channel, bool enable);
/*!
* @brief Enable the bypass output.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param enable 'true' to enable the bypass output, 'false' to disable the bypass output.
* @return None.
*/
void COMP_EnableBypassOutput(COMP_Type * COMPx, uint32_t channel, bool enable);
/*!
*@}
*/
#endif /* __HAL_COMP_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_crc.h"
/* CRC initialization. */
void CRC_Init(CRC_Type * CRCx, CRC_Init_Type * init)
{
CRCx->CR &= ~(CRC_PR_PR_MASK | CRC_CR_RO_MASK | CRC_CR_RI_MASK | CRC_CR_BEO_MASK | CRC_CR_BEI_MASK);
CRCx->PR &= ~CRC_PR_PR_MASK;
CRCx->CR |= CRC_CR_PWIDTH(init->PolynomialWidth) | CRC_CR_RO(init->OutRev)
| CRC_CR_RI(init->InRev) | CRC_CR_BEO(init->OutEndian) | CRC_CR_BEI(init->InEndian);
CRCx->PR = CRC_PR_PR(init->Polynomial);
}
/* Set the value in CRC calculation unit as the initial value. */
void CRC_SetSeed(CRC_Type * CRCx, uint32_t val)
{
CRCx->IVR = CRC_IVR_IVR(val);
CRCx->CR |= CRC_CR_RST_MASK;
}
/* Set data for CRC calculation. */
void CRC_SetData(CRC_Type * CRCx, uint32_t val)
{
CRCx->DR = val;
}
/* Get CRC calculation result. */
uint32_t CRC_GetResult(CRC_Type * CRCx)
{
return CRCx->DR;
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_CRC_H__
#define __HAL_CRC_H__
#include "hal_common.h"
/*!
* @addtogroup CRC
* @{
*/
/*!
* @brief CRC polynomail width type.
*/
typedef enum
{
CRC_PolynomialWidth_32b = 0, /*!< Polynomial Width 32 bits. */
CRC_PolynomialWidth_16b = 1, /*!< Polynomial Width 16 bits. */
CRC_PolynomialWidth_8b = 2, /*!< Polynomial Width 8 bits. */
} CRC_PolynomialWidth_Type;
/*!
* @brief Whether the data in reverse order.
*/
typedef enum
{
CRC_Rev_Normal = 0, /*!< Transfer data in normal order. */
CRC_Rev_Rev = 1, /*!< Transfer data in reverse order. */
} CRC_Rev_Type;
/*!
* @brief The data endian is little-endian or big-endian.
*/
typedef enum
{
CRC_DataEndian_LittleEndian = 0, /*!< Specofy the data endian is little-endian. */
CRC_DataEndian_BigEndian = 1, /*!< Specofy the data endian is big-endian. */
} CRC_DataEndian_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref CRC_Init() to initialize the CRC module.
*/
typedef struct
{
uint32_t Polynomial; /*!< Configure arbitrary polynomial. */
CRC_PolynomialWidth_Type PolynomialWidth; /*!< Specify the CRC polynomial width. */
CRC_DataEndian_Type InEndian; /*!< Specify input endian is little-endian or big-endian. */
CRC_DataEndian_Type OutEndian; /*!< Specify output endian is little-endian or big-ndian. */
CRC_Rev_Type InRev; /*!< Specify whether the input data in reverse order. */
CRC_Rev_Type OutRev; /*!< Specify whether the output data in reverse order. */
} CRC_Init_Type;
/*!
* @brief Initialize the CRC module.
*
* Initialize polynomial width, polynomial and input/output configuration
* The highest power of polynomial is determined by polynomial width.
*
* @param CRCx CRC instance.
* @param init Pointer to the initialization structure. See to @ref CRC_Init_Type.
* @return None.
*/
void CRC_Init(CRC_Type * CRCx, CRC_Init_Type * init);
/*!
* @brief Set the first data for CRC calculation.
*
* @param CRCx CRC instance.
* @param val The first data of CRC calculation.
* @return None.
*/
void CRC_SetSeed(CRC_Type * CRCx, uint32_t val);
/*!
* @brief Set data for CRC calculation.
*
* @param CRCx CRC instance.
* @param val The value used for CRC calculation.
* @return None.
*/
void CRC_SetData(CRC_Type * CRCx, uint32_t val);
/*!
* @brief Get the most recent result of CRC calculation.
*
* @param CRCx CRC instance.
* @return Return the most recent result of CRC calculation.
*/
uint32_t CRC_GetResult(CRC_Type * CRCx);
/*!
*@}
*/
#endif /*__HAL_CRC_H__. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_dac.h"
void DAC_Init(DAC_Type * DACx, uint32_t channel, DAC_Init_Type * init)
{
uint32_t cr = 0u;
cr = DACx->CR & ~(( DAC_CR_BOFF1_MASK
| DAC_CR_TEN1_MASK
) << (channel<<4u)); /* Calculate the shift and clear the indicated bit. */
/* Enable Output Buffer. */
if (init->EnableOutBuf == false)
{
cr |= (DAC_CR_BOFF1_MASK << (channel<<4u));
}
/* Trigger Source. */
if (init->EnableTrigger)
{
cr |= ((DAC_CR_TEN1_MASK) << (channel<<4u));
}
DAC->CR = cr;
}
void DAC_Enable(DAC_Type * DACx, uint32_t channel, bool enable)
{
if (enable)
{
DACx->CR |= (DAC_CR_EN1_MASK << (channel << 4u));
}
else
{
DACx->CR &= ~(DAC_CR_EN1_MASK << (channel << 4u));
}
}
void DAC_EnableChannelOutput(DAC_Type * DACx, uint32_t channel, bool enable)
{
if (enable)
{
DACx->CR |= (DAC_CR_OEEN1_MASK << (channel << 4u));
}
else
{
DACx->CR &= ~(DAC_CR_OEEN1_MASK << (channel << 4u));
}
}
uint32_t DAC_GetData(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0u;
if(channel == DAC_CHN_1)
{
ret = (DACx->DOR1 & DAC_DOR1_DACC1DOR_MASK);
}
else if (channel == DAC_CHN_2)
{
ret = (DACx->DOR2 & DAC_DOR2_DACC2DOR_MASK);
}
return ret;
}
uint32_t DAC_PutData(DAC_Type * DACx, uint32_t channel, uint32_t value, DAC_Align_Type align)
{
uint32_t ret = 0u;
switch (align)
{
case DAC_Align_8b_Dual:
{
DAC_PutDualChannelData8bRightAlign(DACx, value);
ret = DAC_GetData(DACx, DAC_CHN_1) | ( DAC_GetData(DACx, DAC_CHN_2) << 16u);
break;
}
case DAC_Align_8b_Right:
{
DAC_PutData8bRightAlign(DACx, channel, value);
ret = DAC_GetData(DACx, channel);
break;
}
case DAC_Align_12b_Left:
{
DAC_PutData12bLeftAlign(DACx, channel, value);
ret = DAC_GetData(DACx, channel);
break;
}
case DAC_Align_12b_Right:
{
DAC_PutData12bRightAlign(DACx, channel, value);
ret = DAC_GetData(DACx, channel);
break;
}
case DAC_Align_12b_Dual_Left:
{
DAC_PutDualChannelData12bLeftAlign(DACx, value);
ret = DAC_GetData(DACx, DAC_CHN_1)
| ( DAC_GetData(DACx, DAC_CHN_2) << 16u);
break;
}
case DAC_Align_12b_Dual_Right:
{
DAC_PutDualChannelData12bRightAlign(DACx, value);
ret = DAC_GetData(DACx, DAC_CHN_1)
| ( DAC_GetData(DACx, DAC_CHN_2) << 16u);
break;
}
default:
break;
}
return ret;
}
void DAC_EnableAddNoise(DAC_Type * DACx, uint32_t channel, DAC_AddNoise_Init_Type * init)
{
if (init == NULL)
{
DAC->CR &= ~(DAC_CR_WAVE1_MASK << (channel << 4u));
}
else
{
DAC->CR |= (( DAC_CR_WAVE1(1u) /* Noise wave need to set WAVEx = 01. */
| DAC_CR_MAMP1(init->AddNoise)
) << (channel << 4u));
}
}
void DAC_EnableAddTriangle(DAC_Type * DACx, uint32_t channel, DAC_AddTriangle_Init_Type * init)
{
if (init == NULL)
{
DAC->CR &= ~(DAC_CR_WAVE1_MASK << (channel << 4u));
}
else
{
DAC->CR |= (( DAC_CR_WAVE1(2u) /* Noise wave need to set WAVEx = 1x. */
| DAC_CR_MAMP1(init->AddTriangle)
) << (channel << 4u));
}
}
void DAC_EnableDMA(DAC_Type * DACx, uint32_t channel, bool enable)
{
if (enable)
{
DACx->CR |= (DAC_CR_DMAEN1_MASK << (channel<<4u));
}
else
{
DACx->CR &= ~(DAC_CR_DMAEN1_MASK << (channel<<4u));
}
}
void DAC_DoSwTrigger(DAC_Type * DACx, uint32_t channel)
{
DACx->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1_MASK << channel);
}
void DAC_DoDualChannelSwTrigger(DAC_Type * DACx)
{
DACx->SWTRIGR |= DAC_SWTRIGR_SWTRIG1_MASK
| DAC_SWTRIGR_SWTRIG2_MASK
;
}
uint32_t DAC_GetDataRegAddr(DAC_Type * DACx, uint32_t channel, DAC_Align_Type align)
{
uint32_t ret = 0u;
switch (align)
{
case DAC_Align_8b_Dual:
{
ret = DAC_GetDualChannelData8bRegAddr(DACx);
break;
}
case DAC_Align_8b_Right:
{
ret = DAC_GetData8bRegAddr(DACx, channel);
break;
}
case DAC_Align_12b_Left:
{
ret = DAC_GetData12bLeftRegAddr(DACx, channel);
break;
}
case DAC_Align_12b_Right:
{
ret = DAC_GetData12bRightRegAddr(DACx, channel);
break;
}
case DAC_Align_12b_Dual_Left:
{
ret = DAC_GetDualChannelData12bLeftRegAddr(DACx);
break;
}
case DAC_Align_12b_Dual_Right:
{
ret = DAC_GetDualChannelData12bRightRegAddr(DACx);
break;
}
default:
break;
}
return ret;
}
/* input value bit[7:0]. 12b output: xxxxxxxx0000. */
void DAC_PutData8bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value)
{
if (channel == DAC_CHN_1)
{
DACx->DHR8R1 = value;
}
else if (channel == DAC_CHN_2)
{
DACx->DHR8R2 = value;
}
}
/* input value bit[15:4]. 12b output: xxxxxxxxxxxx. */
void DAC_PutData12bLeftAlign(DAC_Type * DACx, uint32_t channel, uint32_t value)
{
if (channel == DAC_CHN_1)
{
DACx->DHR12L1 = value;
}
else if (channel == DAC_CHN_2)
{
DACx->DHR12L2 = value;
}
}
/* input value bit[11:0], 12b output: xxxxxxxxxxxx. */
void DAC_PutData12bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value)
{
if (channel == DAC_CHN_1)
{
DACx->DHR12R1 = value;
}
else if (channel == DAC_CHN_2)
{
DACx->DHR12R2 = value;
}
}
/* bit[15:8] for channel 2, bit[7:0] for channel 1. */
void DAC_PutDualChannelData8bRightAlign(DAC_Type * DACx, uint32_t value)
{
DACx->DHR8RD = value;
}
/* bit[31:16] for channel 2, bit[15:0] for channel 1. */
void DAC_PutDualChannelData12bLeftAlign(DAC_Type * DACx, uint32_t value)
{
DACx->DHR12LD = value;
}
/* bit[31:16] for channel 2, bit[15:0] for channel 1. */
void DAC_PutDualChannelData12bRightAlign(DAC_Type * DACx, uint32_t value)
{
DACx->DHR12RD = value;
}
uint32_t DAC_GetData8bRegAddr(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0u;
if (channel == DAC_CHN_1)
{
ret = (uint32_t)(&(DACx->DHR8R1));
}
else if (channel == DAC_CHN_2)
{
ret = (uint32_t)(&(DACx->DHR8R2));
}
return ret;
}
uint32_t DAC_GetData12bLeftRegAddr(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0u;
if (channel == DAC_CHN_1)
{
ret = (uint32_t)(&(DACx->DHR12L1));
}
else if (channel == DAC_CHN_2)
{
ret = (uint32_t)(&(DACx->DHR12L2));
}
return ret;
}
uint32_t DAC_GetData12bRightRegAddr(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0;
if (channel == DAC_CHN_1)
{
ret = (uint32_t)(&(DACx->DHR12R1));
}
else if (channel == DAC_CHN_2)
{
ret = (uint32_t)(&(DACx->DHR12R2));
}
return ret;
}
uint32_t DAC_GetDualChannelData8bRegAddr(DAC_Type * DACx)
{
return (uint32_t)(&(DACx->DHR8RD));
}
uint32_t DAC_GetDualChannelData12bLeftRegAddr(DAC_Type * DACx)
{
return (uint32_t)(&(DACx->DHR12LD));
}
uint32_t DAC_GetDualChannelData12bRightRegAddr(DAC_Type * DACx)
{
return (uint32_t)(&(DACx->DHR12RD));
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_DAC_H__
#define __HAL_DAC_H__
#include "hal_common.h"
/*!
* @addtogroup DAC
* @{
*/
/*!
* @brief DAC driver version number.
*/
#define DAC_DRIVER_VERSION 0u /*!< dac_0. */
/*!
* @addtogroup DAC_CHANNEL_SELECTION
* @{
*/
#define DAC_CHN_NUM (2u) /*!< The total number of DAC channel. */
#define DAC_CHN_1 (0u) /*!< The selection of DAC Channel 1. */
#define DAC_CHN_2 (1u) /*!< The selection of DAC Channel 2. */
/*!
*@}
*/
/*!
* @brief DAC align type.
*/
typedef enum
{
DAC_Align_8b_Dual = 0u, /*!< The selection of dual channel data alignment of 8b right. */
DAC_Align_8b_Right = 1u, /*!< The selection of single channel data alignment of 8b right. */
DAC_Align_12b_Left = 2u, /*!< The selection of single channel data alignment of 12b left. */
DAC_Align_12b_Right = 3u, /*!< The selection of single channel data alignment of 12b right. */
DAC_Align_12b_Dual_Left = 4u, /*!< The selection of dual channel data alignment of 12b left. */
DAC_Align_12b_Dual_Right = 5u, /*!< The selection of dual channel data alignment of 12b right. */
} DAC_Align_Type;
/*!
* @brief DAC LFSR unmask bit selector type for adding noise wave.
*/
typedef enum
{
DAC_AddNoise_LFSRUnMask_0 = 0u, /*!< Unmask DAC channel LFSR bit0. */
DAC_AddNoise_LFSRUnMask_1 = 1u, /*!< Unmask DAC channel LFSR bit[1:0]. */
DAC_AddNoise_LFSRUnMask_2 = 2u, /*!< Unmask DAC channel LFSR bit[2:0]. */
DAC_AddNoise_LFSRUnMask_3 = 3u, /*!< Unmask DAC channel LFSR bit[3:0]. */
DAC_AddNoise_LFSRUnMask_4 = 4u, /*!< Unmask DAC channel LFSR bit[4:0]. */
DAC_AddNoise_LFSRUnMask_5 = 5u, /*!< Unmask DAC channel LFSR bit[5:0]. */
DAC_AddNoise_LFSRUnMask_6 = 6u, /*!< Unmask DAC channel LFSR bit[6:0]. */
DAC_AddNoise_LFSRUnMask_7 = 7u, /*!< Unmask DAC channel LFSR bit[7:0]. */
DAC_AddNoise_LFSRUnMask_8 = 8u, /*!< Unmask DAC channel LFSR bit[8:0]. */
DAC_AddNoise_LFSRUnMask_9 = 9u, /*!< Unmask DAC channel LFSR bit[9:0]. */
DAC_AddNoise_LFSRUnMask_10 = 10u, /*!< Unmask DAC channel LFSR bit[10:0]. */
DAC_AddNoise_LFSRUnMask_11 = 11u, /*!< Unmask DAC channel LFSR bit[11:0]. */
} DAC_AddNoise_Type;
/*!
* @brief DAC triangle amplitude selector type for adding triangle wave.
*/
typedef enum
{
DAC_AddTriangle_LFSRAmplitude_1 = 0u, /*!< Max triangle amplitude of 1. */
DAC_AddTriangle_LFSRAmplitude_3 = 1u, /*!< Max triangle amplitude of 3. */
DAC_AddTriangle_LFSRAmplitude_7 = 2u, /*!< Max triangle amplitude of 7. */
DAC_AddTriangle_LFSRAmplitude_15 = 3u, /*!< Max triangle amplitude of 15. */
DAC_AddTriangle_LFSRAmplitude_31 = 4u, /*!< Max triangle amplitude of 31. */
DAC_AddTriangle_LFSRAmplitude_63 = 5u, /*!< Max triangle amplitude of 63. */
DAC_AddTriangle_LFSRAmplitude_127 = 6u, /*!< Max triangle amplitude of 127. */
DAC_AddTriangle_LFSRAmplitude_255 = 7u, /*!< Max triangle amplitude of 255. */
DAC_AddTriangle_LFSRAmplitude_511 = 8u, /*!< Max triangle amplitude of 511. */
DAC_AddTriangle_LFSRAmplitude_1023 = 9u, /*!< Max triangle amplitude of 1023. */
DAC_AddTriangle_LFSRAmplitude_2047 = 10u, /*!< Max triangle amplitude of 2047. */
DAC_AddTriangle_LFSRAmplitude_4095 = 11u, /*!< Max triangle amplitude of 4095. */
} DAC_AddTriangle_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DAC_EnableAddNoise() to initialize the DAC noise wave generation.
*/
typedef struct
{
DAC_AddNoise_Type AddNoise; /*!< Specify the noise wave pattern. */
} DAC_AddNoise_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DAC_EnableAddTriangle() to initialize the DAC triangle wave generation.
*/
typedef struct
{
DAC_AddTriangle_Type AddTriangle; /*!< Specify the triangle wave pattern. */
} DAC_AddTriangle_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DAC_Init() to initialize the DAC module.
*/
typedef struct
{
bool EnableTrigger; /*!< Specify whether to use the trigger and the trigger type. */
bool EnableOutBuf; /*!< Specify whether output buffer is enabled. */
} DAC_Init_Type;
/*!
* @brief Initialize the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param init Pointer to the initialization structure. See to @ref DAC_Init_Type.
* @return None.
*/
void DAC_Init(DAC_Type * DACx, uint32_t channel, DAC_Init_Type * init);
/*!
* @brief Enable the DAC module.
*
* The DAC module should be enabled before outputting voltage.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void DAC_Enable(DAC_Type * DACx, uint32_t channel, bool enable);
/*!
* @brief Enable the DAC channel output.
*
* The DAC output channel should be enabled before outputting voltage.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param enable 'true' to enable the DAC channel output, 'false' to disable the DAC channel output.
* @return None.
*/
void DAC_EnableChannelOutput(DAC_Type * DACx, uint32_t channel, bool enable);
/*!
* @brief Get the echo data from the output of the indicated DAC channel.
*
* The value in DAC_DORx register takes effect on the actual output of DAC.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The indicated DAC channel data output value.
*/
uint32_t DAC_GetData(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Put the value into the indicated channel of the DAC module with the alignment.
*
* The value in DAC_DORx register takes effect on the actual output of DAC.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @param align Alignment the value expected to be put into the conversion. See to @ref DAC_Align_Type.
* @return The current converted value of the indicated DAC channel.
*/
uint32_t DAC_PutData(DAC_Type * DACx, uint32_t channel, uint32_t value, DAC_Align_Type align);
/*!
* @brief Enable the feature of generating noise wave from the DAC module.
*
* If enable additional noise wave, the output value will depend on the the unmask LFSR bit and input of the indicated channel.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param init Pointer to the initialization structure. See to @ref DAC_AddNoise_Init_Type. If null, disable the wave generation.
* @return None.
*/
void DAC_EnableAddNoise(DAC_Type * DACx, uint32_t channel, DAC_AddNoise_Init_Type * init);
/*!
* @brief Enable the feature of generating triangle wave from the DAC module.
*
* Defaultedly, DAC does not generate any wave.
* If enable additional triangle wave, the output value will depend on the the indicated amplitude and input of the indicated channel.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param init Pointer to the initialization structure. See to @ref DAC_AddTriangle_Init_Type. If null, disable the wave generation.
* @return None.
*/
void DAC_EnableAddTriangle(DAC_Type * DACx, uint32_t channel, DAC_AddTriangle_Init_Type * init);
/*!
* @brief Enable the DMA trigger from the DAC module.
*
* The DMA trigger events are the same as the intertupts.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void DAC_EnableDMA(DAC_Type * DACx, uint32_t channel, bool enable);
/*!
* @brief Do trigger the indicated DAC channel with software trigger.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return None.
*/
void DAC_DoSwTrigger(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Do trigger the dual DAC channels with software trigger simultaneously.
*
* @param DACx DAC instance.
* @return None.
*/
void DAC_DoDualChannelSwTrigger(DAC_Type * DACx);
/*!
* @brief Get the indicated register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param align Alignment that the data expects to br transferred. See to @ref DAC_Align_Type.
* @return The value of the address for indicated align type of the DAC channel.
*/
uint32_t DAC_GetDataRegAddr(DAC_Type * DACx, uint32_t channel, DAC_Align_Type align);
/*!
* @brief Put 8-bit value into the indicated channel of the DAC module.
*
* The low 8-bit of the setting value here will be output with 4-bit left shift.
* If the value is 0x1f, the output will be 0x1f0.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @return None.
*/
void DAC_PutData8bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value);
/*!
* @brief Put the 12-bit value into indicated channel of the DAC module.
*
* The low 12-bit of the setting value here will be output after 4-bit right shift.
* If the value is 0x1ff, the output will be 0x1f.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @return None.
*/
void DAC_PutData12bLeftAlign(DAC_Type * DACx, uint32_t channel, uint32_t value);
/*!
* @brief Put the current data into indicated channel of the DAC module.
*
* The low 12-bit of the setting value here will output with the original value.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @return None.
*/
void DAC_PutData12bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value);
/*!
* @brief Respectively put the value into the dual channels of the DAC module 8b right aligned.
*
* Simultaneously output the low 8-bit of the low 16-bit and high 16-bit of the 32-bit value seperately with a 4-bit left shift.
* If value is 0x011f01ff, the output of each channel will be 0xff0 ( channel 1 ) and 0x1f0 ( channel 2 ).
*
* @param DACx DAC instance.
* @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion.
* @return None.
*/
void DAC_PutDualChannelData8bRightAlign(DAC_Type * DACx, uint32_t value);
/*!
* @brief Put the data into the dual channel of the DAC module 12b left aligned.
*
* Simultaneously output the high 12-bit of the low 16-bit and high 16-bit of the 32-bit value seperately after 4-bit right shift.
* If value is 0x011f01ff, the output of each channel will be 0x01f ( channel 1 ) and 0x011 ( channel 2 ).
*
* @param DACx DAC instance.
* @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion.
* @return None.
*/
void DAC_PutDualChannelData12bLeftAlign(DAC_Type * DACx, uint32_t value);
/*!
* @brief Put the data into the dual channel of the DAC module 12b right aligned.
*
* Simultaneously output the low 12-bit of the low 16-bit and high 16-bit of the 32-bit value seperately.
*
* @param DACx DAC instance.
* @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion.
* @return None.
*/
void DAC_PutDualChannelData12bRightAlign(DAC_Type * DACx, uint32_t value);
/*!
* @brief Get the 8-bit data register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The value of the address for DAC module's 8-bit data register .
*/
uint32_t DAC_GetData8bRegAddr(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Get the 12-bit left-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The value of the address for DAC module's 12-bit left-aligned data register .
*/
uint32_t DAC_GetData12bLeftRegAddr(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Get the 12-bit right-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The value of the address for DAC module's 12-bit right-aligned data register .
*/
uint32_t DAC_GetData12bRightRegAddr(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Get the dual channel 8-bit data register address of the DAC module.
*
* @param DACx DAC instance.
* @return The value of the address for DAC module's dual channel 8-bit data register .
*/
uint32_t DAC_GetDualChannelData8bRegAddr(DAC_Type * DACx);
/*!
* @brief Get the dual channel 12-bit left-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @return The value of the address for DAC module's 12-bit dual channel left-aligned data register .
*/
uint32_t DAC_GetDualChannelData12bLeftRegAddr(DAC_Type * DACx);
/*!
* @brief Get the dual channel 12-bit right-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @return The value of the address for DAC module's 12-bit dual channel right-aligned data register .
*/
uint32_t DAC_GetDualChannelData12bRightRegAddr(DAC_Type * DACx);
/*!
*@}
*/
#endif /* __HAL_DAC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_dma.h"
/* clear all the interrupt enables and disable the dma channel. */
uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init)
{
uint32_t ccr = 0u;
if ( (init->XferMode == DMA_XferMode_MemoryToPeriph)
|| (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
{
ccr |= DMA_CCR_DIR_MASK;
}
if ( (init->XferMode == DMA_XferMode_PeriphToMemoryBurst)
|| (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
{
ccr |= DMA_CCR_MEM2MEM_MASK;
}
if (init->ReloadMode == DMA_ReloadMode_AutoReload)
{
ccr |= DMA_CCR_ARE_MASK;
}
else if (init->ReloadMode == DMA_ReloadMode_AutoReloadContinuous)
{
ccr |= (DMA_CCR_ARE_MASK | DMA_CCR_CIRC_MASK);
}
ccr |= DMA_CCR_PINC(init->PeriphAddrIncMode)
| DMA_CCR_MINC(init->MemAddrIncMode)
| DMA_CCR_PSIZE(init->XferWidth)
| DMA_CCR_MSIZE(init->XferWidth)
| DMA_CCR_PL(init->Priority)
;
DMAx->CH[channel].CCR = ccr;
DMAx->CH[channel].CNDTR = init->XferCount;
DMAx->CH[channel].CPAR = init->PeriphAddr;
DMAx->CH[channel].CMAR = init->MemAddr;
return 0u;
}
void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable)
{
if (enable)
{
DMAx->CH[channel].CCR |= (interrupts & 0xEu);
}
else
{
DMAx->CH[channel].CCR &= ~(interrupts & 0xEu);
}
}
uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel)
{
return (DMAx->ISR >> (channel * 4u)) & 0xFu;
}
void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts)
{
DMAx->IFCR = ( (interrupts & 0xFu) << (channel * 4u) );
}
void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable)
{
if (enable)
{
DMAx->CH[channel].CCR |= DMA_CCR_EN_MASK;
}
else
{
DMAx->CH[channel].CCR &= ~DMA_CCR_EN_MASK;
}
}
void DMA_EnableBurstMode(DMA_Type * DMAx, uint32_t channel, bool enable)
{
if (enable)
{
DMAx->CH[channel].CCR |= DMA_CCR_BURSTEN_MASK;
}
else
{
DMAx->CH[channel].CCR &= ~DMA_CCR_BURSTEN_MASK;
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_DMA_H__
#define __HAL_DMA_H__
#include "hal_common.h"
/*!
* @addtogroup DMA
* @{
*/
/*!
* @addtogroup DMA_CHANNEL_INT
* @{
*/
#define DMA_CHN_INT_XFER_GLOBAL (0x1u << 0u) /*!< DMA global interrupt channel. */
#define DMA_CHN_INT_XFER_DONE (0x1u << 1u) /*!< DMA end of transfer interrupt channel. */
#define DMA_CHN_INT_XFER_HALF_DONE (0x1u << 2u) /*!< DMA half transfer interrupt channel. */
#define DMA_CHN_INT_XFER_ERR (0x1u << 3u) /*!< DMA transfer error interrupt channel. */
/*!
* @}
*/
/*!
* @brief Define the enum type of DMA_XferMode_Type.
*/
typedef enum
{
DMA_XferMode_PeriphToMemory = 0u, /*!< memory to memory mode, from periph addr to memory addr. */
DMA_XferMode_MemoryToPeriph = 1u, /*!< memory to memory mode, from periph addr to memory addr. */
DMA_XferMode_PeriphToMemoryBurst = 2u, /*!< memory to memory mode, from periph addr to memory addr. */
DMA_XferMode_MemoryToPeriphBurst = 3u, /*!< memory to memory mode, from memory addr to periph addr. */
} DMA_XferMode_Type;
/*!
* @brief Define the enum type of DMA_ReloadMode_Type.
*/
typedef enum
{
DMA_ReloadMode_OneTime = 0u, /*!< the count is exhausted after the xfer is done. */
DMA_ReloadMode_AutoReload = 1u, /*!< auto reload the count for the new xfer. */
DMA_ReloadMode_AutoReloadContinuous = 2u, /*!< auto reload the count for the next xfer, and always run. */
} DMA_ReloadMode_Type;
/*!
* @brief Incremental mode of peripherals and memories.
*/
typedef enum
{
DMA_AddrIncMode_StayAfterXfer = 0u, /*!< Peripheral access address accumulation. */
DMA_AddrIncMode_IncAfterXfer = 1u, /*!< Memory access address accumulation. */
} DMA_AddrIncMode_Type;
/*!
* @brief Define the enum type of DMA xfer width type.
*/
typedef enum
{
DMA_XferWidth_8b = 0u, /*!< Xfer width 8 bits. */
DMA_XferWidth_16b = 1u, /*!< Xfer width 16 bits. */
DMA_XferWidth_32b = 2u, /*!< Xfer width 32 bits. */
} DMA_XferWidth_Type;
/*!
* @brief Configure DMA Priority.
*/
typedef enum
{
DMA_Priority_Low = 0u, /*!< Low Priority. */
DMA_Priority_Middle = 1u, /*!< Middle Priority. */
DMA_Priority_High = 2u, /*!< High Priority. */
DMA_Priority_Highest = 3u, /*!< Highest Priority. */
} DMA_Priority_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DMA_InitChannel() to initialize the DMA module.
*/
typedef struct
{
DMA_XferMode_Type XferMode; /*!< Specify whether the Receive or Transmit mode is enabled or not. */
DMA_ReloadMode_Type ReloadMode; /*!< Specify whether to automatically reload the next transfer count when the count is exhausted. */
DMA_AddrIncMode_Type PeriphAddrIncMode; /*!< Specify peripheral Address Inc Mode. */
DMA_AddrIncMode_Type MemAddrIncMode; /*!< Specify Memory Address Inc Mode. */
DMA_XferWidth_Type XferWidth; /*!< Specify the transmission data width. */
DMA_Priority_Type Priority; /*!< Specify priority mode. */
uint32_t XferCount; /*!< Specify CircularMode's count. */
uint32_t MemAddr; /*!< Specify Memory Address. */
uint32_t PeriphAddr; /*!< Specify Periph Address. */
} DMA_Channel_Init_Type;
/*!
* @brief Initialize the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller.
* @param init Pointer to the initialization structure. See to @ref DMA_Channel_Init_Type.
* @return None.
*/
uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init);
/*!
* @brief enable the DMA channel interrupts of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller.
* @param interrupts Interrupt code masks. See to @ref DMA_CHANNEL_INT.
* @param enable 'true' to enable the DMA channel interrupts, 'false' to disable the DMA channel interrupts.
* @return None.
*/
void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable);
/*!
* @brief Get the channel interrupts status flags of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller in DMA. See to @ref DMA_CHANNEL_INT.
* @return Interrupt status flags.
*/
uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel);
/*!
* @brief Clear the channel interrupts status flags of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller. See to @ref DMA_CHANNEL_INT.
* @param interrupts Interrupt code masks.
* @return None.
*/
void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts);
/*!
* @brief Enable the channel of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller.
* @param enable 'true' to enable the DMA controller sends a reply signal to the peripheral, 'false' to disable the DMA controller sends a reply signal to the peripheral.
* @return None.
*/
void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable);
/*!
* @brief Enable the burst mode of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller.
* @param enable 'true' to enable the DMA controller sends a reply signal to the peripheral, 'false' to disable the DMA controller sends a reply signal to the peripheral.
* @return None.
*/
void DMA_EnableBurstMode(DMA_Type * DMAx, uint32_t channel, bool enable);
/*!
*@}
*/
#endif /* __HAL_DMA_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_DMA_REQUESET_H__
#define __HAL_DMA_REQUESET_H__
/* DMA1 Requests Remap. */
/* ADC1. */
#define DMA_REQ_DMA1_ADC1 0u
/* ADC2. */
#define DMA_REQ_DMA1_ADC2 1u
/* SPI1. */
#define DMA_REQ_DMA1_SPI1_RX 1u
#define DMA_REQ_DMA1_SPI1_TX 2u
/* SPI2. */
#define DMA_REQ_DMA1_SPI2_RX 3u
#define DMA_REQ_DMA1_SPI2_TX 4u
/* UART1. */
#define DMA_REQ_DMA1_UART1_TX 3u
#define DMA_REQ_DMA1_UART1_RX 4u
/* UART2. */
#define DMA_REQ_DMA1_UART2_TX 5u
#define DMA_REQ_DMA1_UART2_RX 6u
/* UART3. */
#define DMA_REQ_DMA1_UART3_TX 1u
#define DMA_REQ_DMA1_UART3_RX 2u
/* UART4. */
/* UART5. */
/* UART6. */
#define DMA_REQ_DMA1_UART6_RX 0u
#define DMA_REQ_DMA1_UART6_TX 7u
/* UART7. */
/* I2C1. */
#define DMA_REQ_DMA1_I2C1_TX 5u
#define DMA_REQ_DMA1_I2C1_RX 6u
/* I2C2. */
#define DMA_REQ_DMA1_I2C2_TX 3u
#define DMA_REQ_DMA1_I2C2_RX 4u
/* TIM1. */
#define DMA_REQ_DMA1_TIM1_CC1 1u
#define DMA_REQ_DMA1_TIM1_CC2 2u
#define DMA_REQ_DMA1_TIM1_CC4 3u
#define DMA_REQ_DMA1_TIM1_UP 4u
#define DMA_REQ_DMA1_TIM1_CC3 5u
#define DMA_REQ_DMA1_TIM1_TRIG_2 6u
#define DMA_REQ_DMA1_TIM1_COM_2 7u
#define DMA_REQ_DMA1_TIM1_TRIG_1 3u
#define DMA_REQ_DMA1_TIM1_COM_1 3u
/* TIM2. */
#define DMA_REQ_DMA1_TIM2_CC3_1 0u
#define DMA_REQ_DMA1_TIM2_UP_1 1u
#define DMA_REQ_DMA1_TIM2_UP_2 2u
#define DMA_REQ_DMA1_TIM2_CC1 4u
#define DMA_REQ_DMA1_TIM2_CC2 6u
#define DMA_REQ_DMA1_TIM2_UP_3 7u
#define DMA_REQ_DMA1_TIM2_CC3_2 2u
#define DMA_REQ_DMA1_TIM2_CC4_1 6u
#define DMA_REQ_DMA1_TIM2_CC4_2 7u
/* TIM3. */
#define DMA_REQ_DMA1_TIM3_CC3 1u
#define DMA_REQ_DMA1_TIM3_CC4 2u
#define DMA_REQ_DMA1_TIM3_CC1 5u
#define DMA_REQ_DMA1_TIM3_CC2 7u
#define DMA_REQ_DMA1_TIM3_UP 2u
#define DMA_REQ_DMA1_TIM3_TRIG 5u
/* TIM4. */
#define DMA_REQ_DMA1_TIM4_CC1 0u
#define DMA_REQ_DMA1_TIM4_CC2 3u
#define DMA_REQ_DMA1_TIM4_CC3 4u
#define DMA_REQ_DMA1_TIM4_UP 6u
#define DMA_REQ_DMA1_TIM4_CC4 7u
/* TIM5. */
/* TIM6. */
/* TIM7. */
/* TIM8. */
/* FELXCAN1. */
#define DMA_REQ_DMA1_FLEXCAN1_RX 7u
/* QSPI. */
/* DMA2 Requests Remap. */
/* ADC. */
/* DAC. */
#define DMA_REQ_DMA2_DAC_CH1_1 2u
#define DMA_REQ_DMA2_DAC_CH2_1 3u
#define DMA_REQ_DMA2_DAC_CH1_2 6u
#define DMA_REQ_DMA2_DAC_CH2_2 6u
/* SPI3. */
#define DMA_REQ_DMA2_SPI3_RX 0u
#define DMA_REQ_DMA2_SPI3_TX 1u
/* UART4. */
#define DMA_REQ_DMA2_UART4_RX_1 2u
#define DMA_REQ_DMA2_UART4_TX_1 4u
#define DMA_REQ_DMA2_UART4_RX_2 6u
#define DMA_REQ_DMA2_UART4_TX_2 7u
/* UART5. */
#define DMA_REQ_DMA2_UART5_RX 0u
#define DMA_REQ_DMA2_UART5_TX 1u
/* UART6. */
#define DMA_REQ_DMA2_UART6_TX 3u
#define DMA_REQ_DMA2_UART6_RX 5u
/* UART7. */
#define DMA_REQ_DMA2_UART7_RX_1 0u
#define DMA_REQ_DMA2_UART7_TX_1 1u
#define DMA_REQ_DMA2_UART7_RX_2 6u
#define DMA_REQ_DMA2_UART7_TX_2 7u
/* LPUART. */
#define DMA_REQ_DMA2_LPUART_TX 3u
#define DMA_REQ_DMA2_LPUART_RX 5u
/* I2C. */
/* TIM1. */
/* TIM2. */
/* TIM3. */
/* TIM4. */
/* TIM5. */
#define DMA_REQ_DMA2_TIM5_CC4 0u
#define DMA_REQ_DMA2_TIM5_CC3 1u
#define DMA_REQ_DMA2_TIM5_CC2 3u
#define DMA_REQ_DMA2_TIM5_CC1 4u
#define DMA_REQ_DMA2_TIM5_UP_2 5u
#define DMA_REQ_DMA2_TIM5_TRIG 0u
#define DMA_REQ_DMA2_TIM5_UP_1 1u
/* TIM6. */
#define DMA_REQ_DMA2_TIM6_UP_1 2u
#define DMA_REQ_DMA2_TIM6_UP_2 5u
/* TIM7. */
#define DMA_REQ_DMA2_TIM7_UP_1 3u
#define DMA_REQ_DMA2_TIM7_UP_2 5u
/* TIM8. */
#define DMA_REQ_DMA2_TIM8_CC3 0u
#define DMA_REQ_DMA2_TIM8_CC4 1u
#define DMA_REQ_DMA2_TIM8_CC1 2u
#define DMA_REQ_DMA2_TIM8_CC2 4u
#define DMA_REQ_DMA2_TIM8_UP_2 5u
#define DMA_REQ_DMA2_TIM8_TRIG_2 6u
#define DMA_REQ_DMA2_TIM8_COM_2 7u
#define DMA_REQ_DMA2_TIM8_UP_1 0u
#define DMA_REQ_DMA2_TIM8_TRIG_1 1u
#define DMA_REQ_DMA2_TIM8_COM_1 1u
/* FELXCAN2. */
#define DMA_REQ_DMA2_FLEXCAN2_RX 5u
/* QSPI. */
#define DMA_REQ_DMA2_QSPI 7u

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_exti.h"
void EXTI_EnableLineInterrupt(EXTI_Type * EXTIx, uint32_t lines, bool enable)
{
if (enable)
{
EXTIx->IMR |= lines;
}
else
{
EXTIx->IMR &= ~ lines;
}
}
void EXTI_EnableLineEvent(EXTI_Type * EXTIx, uint32_t lines, bool enable)
{
if (enable)
{
EXTIx->EMR |= lines;
}
else
{
EXTIx->EMR &= ~ lines;
}
}
void EXTI_SetTriggerIn(EXTI_Type * EXTIx, uint32_t lines, EXTI_TriggerIn_Type trgin)
{
switch (trgin)
{
case EXTI_TriggerIn_Disable:
EXTIx->RTSR &= ~ lines;
EXTIx->FTSR &= ~ lines;
break;
case EXTI_TriggerIn_RisingEdge:
EXTI->RTSR |= lines;
EXTIx->FTSR &= ~ lines;
break;
case EXTI_TriggerIn_FallingEdge:
EXTI->RTSR &= ~ lines;
EXTI->FTSR |= lines;
break;
case EXTI_TriggerIn_BothEdges:
EXTI->RTSR |= lines;
EXTI->FTSR |= lines;
break;
default:
break;
}
}
void EXTI_DoSwTrigger(EXTI_Type * EXTIx, uint32_t lines)
{
EXTIx->SWIER = lines;
}
uint32_t EXTI_GetLineStatus(EXTI_Type * EXTIx)
{
return EXTIx->PR;
}
void EXTI_ClearLineStatus(EXTI_Type * EXTIx, uint32_t lines)
{
EXTIx->PR |= lines;
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_EXTI_H__
#define __HAL_EXTI_H__
#include "hal_common.h"
/*!
* @addtogroup EXTI
* @{
*/
/*!
* @brief EXTI driver version number.
*/
#define EXTI_DRIVER_VERSION 0u /*!< exti_0. */
/*!
* @addtogroup EXTI_LINE
* @{
*/
#define EXTI_LINE_0 (1u << 0u) /*!<External Interrupt Line 0 switcher. */
#define EXTI_LINE_1 (1u << 1u) /*!<External Interrupt Line 1 switcher. */
#define EXTI_LINE_2 (1u << 2u) /*!<External Interrupt Line 2 switcher. */
#define EXTI_LINE_3 (1u << 3u) /*!<External Interrupt Line 3 switcher. */
#define EXTI_LINE_4 (1u << 4u) /*!<External Interrupt Line 4 switcher. */
#define EXTI_LINE_5 (1u << 5u) /*!<External Interrupt Line 5 switcher. */
#define EXTI_LINE_6 (1u << 6u) /*!<External Interrupt Line 6 switcher. */
#define EXTI_LINE_7 (1u << 7u) /*!<External Interrupt Line 7 switcher. */
#define EXTI_LINE_8 (1u << 8u) /*!<External Interrupt Line 8 switcher. */
#define EXTI_LINE_9 (1u << 9u) /*!<External Interrupt Line 9 switcher. */
#define EXTI_LINE_10 (1u << 10u) /*!<External Interrupt Line 10 switcher. */
#define EXTI_LINE_11 (1u << 11u) /*!<External Interrupt Line 11 switcher. */
#define EXTI_LINE_12 (1u << 12u) /*!<External Interrupt Line 12 switcher. */
#define EXTI_LINE_13 (1u << 13u) /*!<External Interrupt Line 13 switcher. */
#define EXTI_LINE_14 (1u << 14u) /*!<External Interrupt Line 14 switcher. */
#define EXTI_LINE_15 (1u << 15u) /*!<External Interrupt Line 15 switcher. */
#define EXTI_LINE_16 (1u << 16u) /*!<External Interrupt Line 16 switcher. */
#define EXTI_LINE_17 (1u << 17u) /*!<External Interrupt Line 17 switcher. */
#define EXTI_LINE_18 (1u << 18u) /*!<External Interrupt Line 18 switcher. */
#define EXTI_LINE_19 (1u << 19u) /*!<External Interrupt Line 19 switcher. */
#define EXTI_LINE_20 (1u << 20u) /*!<External Interrupt Line 20 switcher. */
#define EXTI_LINE_21 (1u << 21u) /*!<External Interrupt Line 21 switcher. */
#define EXTI_LINE_22 (1u << 22u) /*!<External Interrupt Line 22 switcher. */
#define EXTI_LINE_23 (1u << 23u) /*!<External Interrupt Line 23 switcher. */
#define EXTI_LINE_24 (1u << 24u) /*!<External Interrupt Line 24 switcher. */
/*!
* @}
*/
/*!
* @brief EXTI trigger input detection edge alt.
*/
typedef enum
{
EXTI_TriggerIn_Disable = 0u, /*!< Disable the trigger input interrupt. */
EXTI_TriggerIn_RisingEdge = 1u, /*!< Trigger input rising edge interrupt.*/
EXTI_TriggerIn_FallingEdge = 2u, /*!< Trigger input falling edge interrupt.*/
EXTI_TriggerIn_BothEdges = 3u, /*!< Both trigger input rising and falling edge interrupt.*/
} EXTI_TriggerIn_Type;
/*!
* @brief Enable the external interrupt line's interrupts.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @param enable 'true' to unmask the external interrupt lines' interrupt, 'false' to mask the external interrupt lines' interrupt.
* @return None.
*/
void EXTI_EnableLineInterrupt(EXTI_Type * EXTIx, uint32_t lines, bool enable);
/*!
* @brief Enable the external interrupt line's events.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @param enable 'true' to unmask the external interrupt lines' event, 'false' to disable the external interrupt lines' event.
* @return None.
*/
void EXTI_EnableLineEvent(EXTI_Type * EXTIx, uint32_t lines, bool enable);
/*!
* @brief Set the line input for triggering interrupts.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @param trgin The active signal for triggering interrupts. See to @ref EXTI_TriggerIn_Type;
* @return None.
*/
void EXTI_SetTriggerIn(EXTI_Type * EXTIx, uint32_t lines, EXTI_TriggerIn_Type trgin);
/*!
* @brief Do software trigger to trigger interrupts of the indicated lines.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @return None.
*/
void EXTI_DoSwTrigger(EXTI_Type * EXTIx, uint32_t lines);
/*!
* @brief Get the interrupt status of the indicated EXTI module.
*
* @param EXTIx EXTI instance.
* @return Line status flags. See to @ref EXTI_LINE.
*/
uint32_t EXTI_GetLineStatus(EXTI_Type * EXTIx);
/*!
* @brief Clear the interrupt status of the indicated EXTI module.
*
* @param EXTIx EXTI instance.
* @param lines Interrupt status flags. See to @ref EXTI_LINE.
* @return None.
*/
void EXTI_ClearLineStatus(EXTI_Type * EXTIx, uint32_t lines);
/*!
* @}
*/
#endif /* __HAL_EXTI_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_flexcan.h"
void FLEXCAN_Enable(FLEXCAN_Type * FLEXCANx, bool enable)
{
if (enable)
{
FLEXCANx->MCR &= ~ FLEXCAN_MCR_MDIS_MASK; /* Unmask the module disable. */
}
else
{
FLEXCANx->MCR |= FLEXCAN_MCR_MDIS_MASK;
}
}
void FLEXCAN_DoSoftReset(FLEXCAN_Type * FLEXCANx)
{
/* Wait for exiting from low power mode. */
while ( 0u != (FLEXCANx->MCR & FLEXCAN_MCR_LPMACK_MASK) )
{
}
FLEXCANx->MCR |= FLEXCAN_MCR_SOFTRST_MASK;
while ( 0u != (FLEXCANx->MCR & FLEXCAN_MCR_SOFTRST_MASK) )
{
}
/* Enable overall warning interrupt. Detailed tx warning and rx warning will be setup by detailed func.*/
FLEXCANx->MCR |= (FLEXCAN_MCR_WRNEN_MASK | FLEXCAN_MCR_LPRIOEN_MASK);
/* Set sampling mode, using three sampling points. */
FLEXCANx->CTRL1 |= FLEXCAN_CTRL1_SMP_MASK;
/* No response automatically generated after receiving remote frame. */
FLEXCANx->CTRL2 |= ( FLEXCAN_CTRL2_RRS_MASK
| FLEXCAN_CTRL2_EACEN_MASK
);
/* Get the defaulted max message buffer number. */
uint32_t mb_num = ( (FLEXCANx->MCR & FLEXCAN_MCR_MAXMB_MASK) >> FLEXCAN_MCR_MAXMB_SHIFT );
/* Clear the individual mask and CS for all message buffers. */
for (uint32_t i = 0u; i <= mb_num; i++)
{
FLEXCANx->RXIMRN[i] = 0x3FFFFFFFu; /* Defaultedly, this mask value is for standard data frame. */
FLEXCAN_ResetMb(FLEXCANx, i);
}
/* Clear the global mask. */
FLEXCANx->RXMGMASK = 0x3FFFFFFFu;
FLEXCANx->RX14MASK = 0x3FFFFFFFu;
FLEXCANx->RX15MASK = 0x3FFFFFFFu;
FLEXCANx->RXFGMASK = 0x3FFFFFFFu;
}
bool FLEXCAN_Init(FLEXCAN_Type * FLEXCANx, FLEXCAN_Init_Type * init)
{
/* Just enable the module shortly for soft reset. */
FLEXCAN_Enable(FLEXCANx, true);
/* softreset the module to enter freezemode and do some default setup. */
FLEXCAN_DoSoftReset(FLEXCANx);
/* Clear register setting bit and save other settings. */
uint32_t mcr = FLEXCANx->MCR & ~ ( FLEXCAN_MCR_SLFWAK_MASK
| FLEXCAN_MCR_WAKSRC_MASK
| FLEXCAN_MCR_MAXMB_MASK
| FLEXCAN_MCR_SRXDIS_MASK
| FLEXCAN_MCR_IRMQ_MASK
);
uint32_t ctrl1 = FLEXCANx->CTRL1 & ~ ( FLEXCAN_CTRL1_LOM_MASK
| FLEXCAN_CTRL1_LPB_MASK
| FLEXCAN_CTRL1_CLKSRC_MASK
| FLEXCAN_CTRL1_BOFFREC_MASK
| FLEXCAN_CTRL1_TSYN_MASK
);
uint32_t ctrl2 = FLEXCANx->CTRL2 & ~ ( FLEXCAN_CTRL2_RRS_MASK
| FLEXCAN_CTRL2_EACEN_MASK
);
/* Select the work mode. */
switch (init->WorkMode)
{
case FLEXCAN_WorkMode_LoopBack:
ctrl1 |= FLEXCAN_CTRL1_LPB_MASK;
break;
case FLEXCAN_WorkMode_ListenOnly:
ctrl1 |= FLEXCAN_CTRL1_LOM_MASK;
break;
case FLEXCAN_WorkMode_Normal:
break;
}
/* Set the self wake up mechanism. */
switch (init->SelfWakeUp)
{
case FLEXCAN_SelfWakeUp_BypassFilter:
mcr |= FLEXCAN_MCR_SLFWAK_MASK;
break;
case FLEXCAN_SelfWakeUp_WithFilter:
mcr |= ( FLEXCAN_MCR_SLFWAK_MASK
| FLEXCAN_MCR_WAKSRC_MASK
);
break;
case FLEXCAN_SelfWakeUp_Disabled:
break;
default:
break;
}
/* Set the max number of message buffer to be used during xferring. */
mcr |= FLEXCAN_MCR_MAXMB(init->MaxXferNum);
/* If enable timer synchronization. */
if ( init->EnableTimerSync )
{
ctrl1 |= FLEXCAN_CTRL1_TSYN_MASK;
}
/* Set the global mask or individual mask. */
if (init->Mask == FLEXCAN_Mask_Individual)
{
mcr |= FLEXCAN_MCR_IRMQ_MASK;
}
/* Enable the self reception for self rx frame. */
if (!init->EnableSelfReception)
{
mcr |= FLEXCAN_MCR_SRXDIS_MASK;
}
/* Set the clock source of protocol engine. */
ctrl1 |= FLEXCAN_CTRL1_CLKSRC(init->ClockSource);
/* Store the remote request but not automatically generate a response. */
ctrl2 |= ( FLEXCAN_CTRL2_RRS_MASK
| FLEXCAN_CTRL2_EACEN_MASK /* Enable comparison of IDE and RTR. */
);
/* Write back to the register. */
FLEXCANx->MCR = mcr;
FLEXCANx->CTRL1 = ctrl1;
FLEXCANx->CTRL2 = ctrl2;
/* Calculate divider and set timing. */
/* Calculate the time quantum for resynchronization. */
uint32_t quantum = ( 1u
+ ( init->TimConf->PropSegLen + 1u )
+ ( init->TimConf->PhaSegLen1 + 1u )
+ ( init->TimConf->PhaSegLen2 + 1u )
);
/* Check validity. */
if ( (quantum * init->BaudRate > init->ClockFreqHz) || (init->BaudRate == 0u) )
{
return false;
}
/* Calculate the prescaler value. */
init->TimConf->PreDiv = init->ClockFreqHz / ( quantum * init->BaudRate ) - 1u;
FLEXCAN_SetTimingConf(FLEXCANx, init->TimConf);
return true;
}
void FLEXCAN_SetTimingConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_TimConf_Type * conf)
{
/* Enter freeze mode before setting timing parameters. */
FLEXCAN_EnableFreezeMode(FLEXCANx, true);
/* If use extended then set up the CBT reg. */
if ( conf->EnableExtendedTime )
{
/* clear extended timing conf. */
uint32_t cbt = FLEXCANx->CBT & ~ ( FLEXCAN_CBT_BTF_MASK
| FLEXCAN_CBT_EPRESDIV_MASK
| FLEXCAN_CBT_ERJW_MASK
| FLEXCAN_CBT_EPROPSEG_MASK
| FLEXCAN_CBT_EPSEG1_MASK
| FLEXCAN_CBT_EPSEG2_MASK
);
cbt = FLEXCAN_CBT_BTF_MASK
| FLEXCAN_CBT_EPRESDIV(conf->PreDiv)
| FLEXCAN_CBT_EPSEG1(conf->PhaSegLen1)
| FLEXCAN_CBT_EPSEG2(conf->PhaSegLen2)
| FLEXCAN_CBT_EPROPSEG(conf->PropSegLen)
| FLEXCAN_CBT_ERJW(conf->JumpWidth);
FLEXCANx->CBT = cbt;
}
else
{
/* Clear registers for writing. */
uint32_t ctrl1 = FLEXCANx->CTRL1 & ~ ( FLEXCAN_CTRL1_PRESDIV_MASK
| FLEXCAN_CTRL1_PSEG1_MASK
| FLEXCAN_CTRL1_PSEG2_MASK
| FLEXCAN_CTRL1_PROPSEG_MASK
| FLEXCAN_CTRL1_RJW_MASK
);
ctrl1 |= FLEXCAN_CTRL1_PRESDIV(conf->PreDiv)
| FLEXCAN_CTRL1_PSEG1(conf->PhaSegLen1)
| FLEXCAN_CTRL1_PSEG2(conf->PhaSegLen2)
| FLEXCAN_CTRL1_PROPSEG(conf->PropSegLen)
| FLEXCAN_CTRL1_RJW(conf->JumpWidth);
FLEXCANx->CTRL1 = ctrl1;
}
/* Exit the freeze mode after setting timing parameters. */
FLEXCAN_EnableFreezeMode(FLEXCANx, false);
}
void FLEXCAN_EnableFreezeMode(FLEXCAN_Type * FLEXCANx, bool enable)
{
if (enable)
{
FLEXCANx->MCR |= ( FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK );
/* Wait a period of time for entering. */
while (0u == (FLEXCANx->MCR & FLEXCAN_MCR_FRZACK_MASK))
{
}
}
else
{
FLEXCANx->MCR &= ~( FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK );
/* Wait a period of time for entirely exiting. */
while (0u != (FLEXCANx->MCR & FLEXCAN_MCR_FRZACK_MASK))
{
}
}
}
/* RXMGMASK register macro. */
#define FLEXCAN_RXMGMASK_RTR_SHIFT (31u)
#define FLEXCAN_RXMGMASK_RTR_MASK (0x1u << FLEXCAN_RXMGMASK_RTR_SHIFT)
#define FLEXCAN_RXMGMASK_RTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_RTR_SHIFT)) & FLEXCAN_RXMGMASK_RTR_MASK)
#define FLEXCAN_RXMGMASK_IDE_SHIFT (30u)
#define FLEXCAN_RXMGMASK_IDE_MASK (0x1u << FLEXCAN_RXMGMASK_IDE_SHIFT)
#define FLEXCAN_RXMGMASK_IDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_IDE_SHIFT)) & FLEXCAN_RXMGMASK_IDE_MASK)
#define FLEXCAN_RXMGMASK_STD_SHIFT (18u)
#define FLEXCAN_RXMGMASK_STD_MASK (0x7FFU << FLEXCAN_RXMGMASK_STD_SHIFT)
#define FLEXCAN_RXMGMASK_STD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_STD_SHIFT)) & FLEXCAN_RXMGMASK_STD_MASK)
#define FLEXCAN_RXMGMASK_EXT_SHIFT (0u)
#define FLEXCAN_RXMGMASK_EXT_MASK (0x1FFFFFFFu << FLEXCAN_RXMGMASK_EXT_SHIFT)
#define FLEXCAN_RXMGMASK_EXT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_EXT_SHIFT)) & FLEXCAN_RXMGMASK_EXT_MASK)
void FLEXCAN_SetGlobalMbMaskConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxMbMaskConf_Type * conf)
{
/* Calculate the mask value. */
uint32_t mask = ( FLEXCAN_RXMGMASK_RTR(conf->MbType)
| FLEXCAN_RXMGMASK_IDE(conf->MbFormat)
| ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? (FLEXCAN_RXMGMASK_EXT(conf->IdMask)) : (FLEXCAN_RXMGMASK_STD(conf->IdMask)) )
);
FLEXCANx->RXMGMASK = mask;
FLEXCANx->RX14MASK = mask;
FLEXCANx->RX15MASK = mask;
}
/* RXFGMASK register macro. */
#define FLEXCAN_RXFGMASK_RXIDA_RTR_SHIFT (31u)
#define FLEXCAN_RXFGMASK_RXIDA_RTR_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDA_RTR_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDA_RTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_RTR_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_RTR_MASK)
#define FLEXCAN_RXFGMASK_RXIDA_IDE_SHIFT (30u)
#define FLEXCAN_RXFGMASK_RXIDA_IDE_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDA_IDE_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDA_IDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_IDE_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_IDE_MASK)
#define FLEXCAN_RXFGMASK_RXIDA_STD_SHIFT (19u)
#define FLEXCAN_RXFGMASK_RXIDA_STD_MASK (0x7FFu << FLEXCAN_RXFGMASK_RXIDA_STD_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDA_STD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_STD_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_STD_MASK)
#define FLEXCAN_RXFGMASK_RXIDA_EXT_SHIFT (1u)
#define FLEXCAN_RXFGMASK_RXIDA_EXT_MASK (0x1FFFFFFFu << FLEXCAN_RXFGMASK_RXIDA_EXT_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDA_EXT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_EXT_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_EXT_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_SHIFT (31u)
#define FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_SHIFT (30u)
#define FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_SHIFT (19u)
#define FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_MASK (0x7FFu << FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_STD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_SHIFT (16u)
#define FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_MASK (0x3FFFu << FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_SHIFT (15u)
#define FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_RTR_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_SHIFT (14u)
#define FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_IDE_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_STD_LOW_SHIFT (3u)
#define FLEXCAN_RXFGMASK_RXIDB_STD_LOW_MASK (0x7FFu << FLEXCAN_RXFGMASK_RXIDB_STD_LOW_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_STD_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_STD_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_STD_LOW_MASK)
#define FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_SHIFT (0u)
#define FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_MASK (0x3FFFu << FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDB_EXT_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_MASK)
#define FLEXCAN_RXFGMASK_RXIDC_HIGH_SHIFT (24u)
#define FLEXCAN_RXFGMASK_RXIDC_HIGH_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_HIGH_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDC_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_HIGH_MASK)
#define FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_SHIFT (16u)
#define FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDC_MIDHIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_MASK)
#define FLEXCAN_RXFGMASK_RXIDC_MIDLOW_SHIFT (8u)
#define FLEXCAN_RXFGMASK_RXIDC_MIDLOW_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_MIDLOW_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDC_MIDLOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_MIDLOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_MIDLOW_MASK)
#define FLEXCAN_RXFGMASK_RXIDC_LOW_SHIFT (0u)
#define FLEXCAN_RXFGMASK_RXIDC_LOW_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_LOW_SHIFT)
#define FLEXCAN_RXFGMASK_RXIDC_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_LOW_MASK)
void FLEXCAN_SetRxFifoGlobalMaskConf(FLEXCAN_Type *FLEXCANx, FLEXCAN_RxFifoMaskConf_Type * conf)
{
uint32_t mask = 0u;
/* Select filter format. */
switch(conf->FilterFormat)
{
case FLEXCAN_FifoIdFilterFormat_A:
mask = ( FLEXCAN_RXFGMASK_RXIDA_RTR(conf->MbType)
| FLEXCAN_RXFGMASK_RXIDA_IDE(conf->MbFormat)
| ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? FLEXCAN_RXFGMASK_RXIDA_EXT(conf->RxIdA) : FLEXCAN_RXFGMASK_RXIDA_STD(conf->RxIdA) )
);
break;
case FLEXCAN_FifoIdFilterFormat_B:
mask = ( FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH(conf->MbType)
| FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH(conf->MbFormat)
| ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH(conf->RxIdB[0]) : FLEXCAN_RXFGMASK_RXIDB_STD_HIGH(conf->RxIdB[0]) )
| FLEXCAN_RXFGMASK_RXIDB_RTR_LOW(conf->MbType)
| FLEXCAN_RXFGMASK_RXIDB_IDE_LOW(conf->MbFormat)
| ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? FLEXCAN_RXFGMASK_RXIDB_EXT_LOW(conf->RxIdB[1]) : FLEXCAN_RXFGMASK_RXIDB_STD_LOW(conf->RxIdB[1]) )
);
break;
case FLEXCAN_FifoIdFilterFormat_C:
mask = ( FLEXCAN_RXFGMASK_RXIDC_HIGH(conf->RxIdC[0])
| FLEXCAN_RXFGMASK_RXIDC_MIDHIGH(conf->RxIdC[1])
| FLEXCAN_RXFGMASK_RXIDC_MIDLOW(conf->RxIdC[2])
| FLEXCAN_RXFGMASK_RXIDC_LOW(conf->RxIdC[3])
);
break;
default:
break;
}
FLEXCANx->RXFGMASK = mask;
}
void FLEXCAN_SetRxMbIndividualMaskConf(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbMaskConf_Type * conf)
{
/* Calculate the mask value. */
uint32_t mask = ( FLEXCAN_RXMGMASK_RTR(conf->MbType)
| FLEXCAN_RXMGMASK_IDE(conf->MbFormat)
| ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? (FLEXCAN_RXMGMASK_EXT(conf->IdMask)) : (FLEXCAN_RXMGMASK_STD(conf->IdMask)) )
);
FLEXCANx->RXIMRN[channel] = mask;
}
void FLEXCAN_ResetMb(FLEXCAN_Type * FLEXCANx, uint32_t channel)
{
FLEXCANx->MB[channel].CS = 0u;
FLEXCANx->MB[channel].ID = 0u;
FLEXCANx->MB[channel].WORD0 = 0u;
FLEXCANx->MB[channel].WORD1 = 0u;
}
void FLEXCAN_SetMbCode(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_MbCode_Type code)
{
FLEXCANx->MB[channel].CS = (FLEXCANx->MB[channel].CS & ~FLEXCAN_CS_CODE_MASK) | FLEXCAN_CS_CODE(code);
}
void FLEXCAN_SetRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbConf_Type * conf)
{
if (NULL != conf)
{
uint32_t cs = 0u;
/* Select the mb format type for seting ID area with different format. */
if (conf->MbFormat == FLEXCAN_MbFormat_Extended)
{
cs |= FLEXCAN_CS_IDE_MASK; /* Set extended frame flag bit. */
FLEXCANx->MB[channel].ID = ( (conf->Id) << FLEXCAN_ID_EXT_SHIFT ) & ( FLEXCAN_ID_EXT_MASK | FLEXCAN_ID_STD_MASK);
}
else
{
FLEXCANx->MB[channel].ID = FLEXCAN_ID_STD(conf->Id);
}
/* Set RTR area for remote frame. */
if (conf->MbType == FLEXCAN_MbType_Remote)
{
cs |= FLEXCAN_CS_RTR_MASK;
}
FLEXCANx->MB[channel].CS = cs;
/* FLEXCAN_SetMbCode(FLEXCANx, channel, FLEXCAN_MbCode_RxEmpty); */
}
else
{
/* If not use Rx Mb anymore, just reset for neither Tx nor Rx. */
FLEXCAN_ResetMb(FLEXCANx, channel);
}
}
bool FLEXCAN_EnableRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxFifoConf_Type * conf)
{
if ( NULL == conf )
{
/* Disable the fifo. */
FLEXCANx->MCR &= ~ FLEXCAN_MCR_RFEN_MASK;
/* Clear rffn value. */
uint32_t rffn = ( (FLEXCANx->CTRL2 & FLEXCAN_CTRL2_RFFN_MASK) >> FLEXCAN_CTRL2_RFFN_SHIFT );
uint32_t max_channel = 8u + rffn * 2u;
/* Clear the mb used for fifo and fifo filters. */
for (uint32_t i = 0u; i < max_channel; i++)
{
FLEXCAN_ResetMb(FLEXCANx, i);
}
}
else
{
/* Clear registers for setting. */
uint32_t mcr = FLEXCANx->MCR & ~ ( FLEXCAN_MCR_RFEN_MASK
| FLEXCAN_MCR_IDAM_MASK
);
uint32_t ctrl2 = FLEXCANx->CTRL2 & ~ ( FLEXCAN_CTRL2_RFFN_MASK
| FLEXCAN_CTRL2_MRP_MASK
);
/* Set FLEXCAN fifo filter format. */
mcr |= FLEXCAN_MCR_IDAM(conf->FilterFormat);
/* Calculate the mb to be used for fifo. */
uint32_t max_mb = ( (FLEXCANx->MCR & FLEXCAN_MCR_MAXMB_MASK) >> FLEXCAN_MCR_MAXMB_SHIFT );
max_mb = max_mb < 0xFu ? 0xFu : max_mb;
/* Calculate the rffn setting value from the Id filter number to be used. */
uint32_t rffn = 0u;
for (uint32_t i = 0u; i < 0xFu; i++)
{
if ( ( ( i + 1u ) * 8u) >= (conf->IdFilterNum) )
{
if ( max_mb < (6u + ( i + 1u ) * 2u) )
{
return false;
}
rffn = i;
break;
}
}
ctrl2 |= FLEXCAN_CTRL2_RFFN(rffn);
/* Set the filter value, for left Mb space, just set it all 1. */
uint32_t idx = 0u;
for (uint32_t i = 6u; i < 6u + ( rffn + 1u ) * 2u; i++)
{
volatile uint32_t * mb = &(FLEXCANx->MB[i].CS);
for (uint32_t k = 0u; k < 4u; k++)
{
/* Fill all valid filter in the mail box occupied by filter.
* Disable unused Rx FIFO Filter, the other rest of register in the last Mail box occupied by fiter set
* as 0xffffffff.
*/
mb[k] = (idx < conf->IdFilterNum) ? (conf->IdFilterTable[idx]) : 0xFFFFFFFFU;
/* Try to fill next filter in current Mail Box. */
idx++;
}
}
/* Set Rx priority between Mb and fifo. */
if (FLEXCAN_FifoPriority_FifoFirst == conf->priority)
{
ctrl2 |= FLEXCAN_CTRL2_MRP_MASK;
}
/* Enable the fifo. */
mcr |= FLEXCAN_MCR_RFEN_MASK;
FLEXCANx->MCR = mcr;
FLEXCANx->CTRL2 = ctrl2;
return true;
}
return false;
}
void FLEXCAN_EnableInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable)
{
uint32_t ctrl1 = FLEXCANx->CTRL1;
/* Enable interrupts. */
if (enable)
{
ctrl1 |= interrupts;
}
else
{
ctrl1 &= ~interrupts;
}
FLEXCANx->CTRL1 = ctrl1;
}
uint32_t FLEXCAN_GetStatus(FLEXCAN_Type * FLEXCANx)
{
return FLEXCANx->ESR1;
}
void FLEXCAN_ClearStatus(FLEXCAN_Type * FLEXCANx, uint32_t flags)
{
FLEXCANx->ESR1 = flags;
}
void FLEXCAN_EnableMbInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable)
{
if (enable)
{
FLEXCANx->IMASK1 |= interrupts;
}
else
{
FLEXCANx->IMASK1 &= ~ interrupts;
}
}
uint32_t FLEXCAN_GetMbStatus(FLEXCAN_Type * FLEXCANx)
{
return FLEXCANx->IFLAG1;
}
void FLEXCAN_ClearMbStatus(FLEXCAN_Type * FLEXCANx, uint32_t interrupts)
{
FLEXCANx->IFLAG1 = interrupts;
}
void FLEXCAN_EnableFifoDMA(FLEXCAN_Type * FLEXCANx, bool enable)
{
if (enable)
{
FLEXCANx->MCR |= FLEXCAN_MCR_DMA_MASK;
}
else
{
FLEXCANx->MCR &= ~ FLEXCAN_MCR_DMA_MASK;
}
}
uint32_t FLEXCAN_GetTxError(FLEXCAN_Type * FLEXCANx)
{
return ( (FLEXCANx->ECR & FLEXCAN_ECR_TXERRCNT_MASK) >> FLEXCAN_ECR_TXERRCNT_SHIFT );
}
uint32_t FLEXCAN_GetRxError(FLEXCAN_Type * FLEXCANx)
{
return ( (FLEXCANx->ECR & FLEXCAN_ECR_RXERRCNT_MASK) >> FLEXCAN_ECR_RXERRCNT_SHIFT );
}
uint32_t FLEXCAN_GetFifoAddr(FLEXCAN_Type * FLEXCANx)
{
return (uint32_t)(&(FLEXCANx->MB[0].CS));
}
bool FLEXCAN_WriteTxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb)
{
if ( FLEXCAN_MbCode_TxDataOrRemote != ( (FLEXCANx->MB[channel].CS & FLEXCAN_CS_CODE_MASK) >> FLEXCAN_CS_CODE_SHIFT ) )
{
/* Reset the CODE for transfer. */
uint32_t cs = (FLEXCANx->MB[channel].CS & ~ FLEXCAN_CS_CODE_MASK) | FLEXCAN_CS_CODE(FLEXCAN_MbCode_TxInactive);
/* Switch mb format. */
if (mb->FORMAT == FLEXCAN_MbFormat_Extended)
{
/* Extended Mb frame with longer ID. */
FLEXCANx->MB[channel].ID = ( ( ( mb->ID ) & ( FLEXCAN_ID_STD_MASK | FLEXCAN_ID_EXT_MASK ) )
| FLEXCAN_ID_PRIO(mb->PRIORITY)
);
cs |= FLEXCAN_CS_SRR_MASK | FLEXCAN_CS_IDE_MASK;
}
else
{
FLEXCANx->MB[channel].ID = ( FLEXCAN_ID_STD(mb->ID)
| FLEXCAN_ID_PRIO(mb->PRIORITY)
);
cs &= ~ (FLEXCAN_CS_SRR_MASK | FLEXCAN_CS_IDE_MASK);
}
/* Switch Mb type. */
if (mb->TYPE == FLEXCAN_MbType_Remote)
{
cs |= FLEXCAN_CS_RTR_MASK;
}
else
{
cs &= ~ FLEXCAN_CS_RTR_MASK;
}
/* Set Mb length for Tx. */
cs |= FLEXCAN_CS_DLC(mb->LENGTH);
FLEXCANx->MB[channel].WORD0 = mb->WORD0;
FLEXCANx->MB[channel].WORD1 = mb->WORD1;
FLEXCANx->MB[channel].CS = cs; /* Always set the CS area at last. */
/* FLEXCAN_SetMbCode(FLEXCANx, channel, FLEXCAN_MbCode_TxDataOrRemote); */
return true;
}
return false;
}
bool FLEXCAN_ReadRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb)
{
uint32_t cs = FLEXCANx->MB[channel].CS;
/* Switch the Mb format to get the ID. */
if ( 0u != (cs & FLEXCAN_CS_IDE_MASK) )
{
mb->ID = FLEXCANx->MB[channel].ID;
mb->FORMAT = FLEXCAN_MbFormat_Extended;
}
else
{
mb->ID = ( (FLEXCANx->MB[channel].ID & FLEXCAN_ID_STD_MASK) >> FLEXCAN_ID_STD_SHIFT);
mb->FORMAT = FLEXCAN_MbFormat_Standard;
}
/* Swith the Mb type. */
if ( 0u != (cs & FLEXCAN_CS_RTR_MASK) )
{
mb->TYPE = FLEXCAN_MbType_Remote;
}
else
{
mb->TYPE = FLEXCAN_MbType_Data;
}
/* Get the valid data length. */
mb->LENGTH = ( (cs & FLEXCAN_CS_DLC_MASK) >> FLEXCAN_CS_DLC_SHIFT );
/* Get the Rx Mb frame timestamp. */
mb->TIMESTAMP = ( (cs & FLEXCAN_CS_TIMESTAMP_MASK) >> FLEXCAN_CS_TIMESTAMP_SHIFT);
/* Read the data. */
mb->WORD0 = FLEXCANx->MB[channel].WORD0;
mb->WORD1 = FLEXCANx->MB[channel].WORD1;
/* Unlock the Mb. */
(void)FLEXCANx->TIMER;
return true;
}
bool FLEXCAN_ReadRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_Mb_Type * mb)
{
if ( 0u != ( FLEXCANx->MCR & FLEXCAN_MCR_RFEN_MASK ) ) /* If fifo is enabled, MB0 will be the only output of fifo. */
{
/* Mb 0 is the fifo output. */
FLEXCAN_ReadRxMb(FLEXCANx, 0u, mb);
/* Get the id filter hit number. */
mb->IDHIT = (FLEXCANx->RXFIR & FLEXCAN_RXFIR_IDHIT_MASK); /* Get the fifo output idhit number. */
return true;
}
else
{
(void)FLEXCANx->TIMER; /* Unlock the Mb. */
return false;
}
}
uint32_t FLEXCAN_GetMatchCrcValue(FLEXCAN_Type * FLEXCANx, uint32_t * channel)
{
if (channel)
{
*channel = ( FLEXCANx->CRCR & FLEXCAN_CRCR_MBCRC_MASK) >> FLEXCAN_CRCR_MBCRC_SHIFT; /* Get the number of the Mb who has succeeded in arbitration for Tx. */
}
return FLEXCANx->CRCR & FLEXCAN_CRCR_TXCRC_MASK;/* Get the CRC value of the last Tx frame. */
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_FLEXCAN_H__
#define __HAL_FLEXCAN_H__
#include "hal_common.h"
/*!
* @addtogroup FLEXCAN
* @{
*/
/*!
* @brief FLEXCAN driver version number.
*/
#define FLEXCAN_DRIVER_VERSION 0u /*!< FLEXCAN_0. */
/*!
* @addtogroup FLEXCAN_GLOBAL_INT
* @{
*/
#define FLEXCAN_INT_RWRN FLEXCAN_CTRL1_RWRNMSK_MASK /*!< Tx warning interrupt switchers. */
#define FLEXCAN_INT_TWRN FLEXCAN_CTRL1_TWRNMSK_MASK /*!< Rx warning interrupt switchers. */
#define FLEXCAN_INT_ERR FLEXCAN_CTRL1_ERRMSK_MASK /*!< Error interrupt switchers. */
#define FLEXCAN_INT_BOFF FLEXCAN_CTRL1_BOFFMSK_MASK /*!< Bus off interrupt switchers. */
/*!
* @}
*/
/*!
* @addtogroup FLEXCAN_STATUS
* @{
*/
#define FLEXCAN_STATUS_WAK (1 << 0u) /*!< Wake up interrupt flag. */
#define FLEXCAN_STATUS_ERR (1 << 1u) /*!< Error interrupt flag. */
#define FLEXCAN_STATUS_BOFF (1 << 2u) /*!< Bus off interrupt flag. */
#define FLEXCAN_STATUS_RX (1 << 3u) /*!< Reception state flag. */
#define FLEXCAN_STATUS_FLTCONF (0 << 4u) /*!< Fault confinement state flag. */
#define FLEXCAN_STATUS_TX (1 << 6u) /*!< Transmission state flag. */
#define FLEXCAN_STATUS_IDLE (1 << 7u) /*!< Idele state flag. */
#define FLEXCAN_STATUS_RXWRN (1 << 8u) /*!< Rx error warning flag. */
#define FLEXCAN_STATUS_TXWRN (1 << 9u) /*!< Tx error warning flag. */
#define FLEXCAN_STATUS_STFERR (1 << 10u) /*!< Stuffing error flag. */
#define FLEXCAN_STATUS_FMRERR (1 << 11u) /*!< Form error flag. */
#define FLEXCAN_STATUS_CRCERR (1 << 12u) /*!< CRC error flag. */
#define FLEXCAN_STATUS_ACKERR (1 << 13u) /*!< ACK error flag. */
#define FLEXCAN_STATUS_BIT0ERR (1 << 14u) /*!< Bit 0 error flag. */
#define FLEXCAN_STATUS_BIT1ERR (1 << 15u) /*!< Bit 1 error flag. */
#define FLEXCAN_STATUS_RWRN (1 << 16u) /*!< Rx warning interrupt flag. */
#define FLEXCAN_STATUS_TWRN (1 << 17u) /*!< Tx warning interrupt flag. */
#define FLEXCAN_STATUS_SYNCH (1 << 18u) /*!< Synchronization status flag. */
#define FLEXCAN_STATUS_BOFFDONE (1 << 19u) /*!< Bus off done interrupt flag. */
#define FLEXCAN_STATUS_ERROVR (1 << 21u) /*!< Error Overrun interrupt flag. */
/*!
* @}
*/
/*!
* @addtogroup FLEXCAN_CHANNEL_SELECTION
* @{
*/
#define FLEXCAN_CHN_NUM (16u) /*!< The total number of FLEXCAN channel. */
#define FLEXCAN_CHN_0 (0u) /*!< The selection of FLEXCAN MB Channel 0. */
#define FLEXCAN_CHN_1 (1u) /*!< The selection of FLEXCAN MB Channel 1. */
#define FLEXCAN_CHN_2 (2u) /*!< The selection of FLEXCAN MB Channel 2. */
#define FLEXCAN_CHN_3 (3u) /*!< The selection of FLEXCAN MB Channel 3. */
#define FLEXCAN_CHN_4 (4u) /*!< The selection of FLEXCAN MB Channel 4. */
#define FLEXCAN_CHN_5 (5u) /*!< The selection of FLEXCAN MB Channel 5. */
#define FLEXCAN_CHN_6 (6u) /*!< The selection of FLEXCAN MB Channel 6. */
#define FLEXCAN_CHN_7 (7u) /*!< The selection of FLEXCAN MB Channel 7. */
#define FLEXCAN_CHN_8 (8u) /*!< The selection of FLEXCAN MB Channel 8. */
#define FLEXCAN_CHN_9 (9u) /*!< The selection of FLEXCAN MB Channel 9. */
#define FLEXCAN_CHN_10 (10u) /*!< The selection of FLEXCAN MB Channel 10. */
#define FLEXCAN_CHN_11 (11u) /*!< The selection of FLEXCAN MB Channel 11. */
#define FLEXCAN_CHN_12 (12u) /*!< The selection of FLEXCAN MB Channel 12. */
#define FLEXCAN_CHN_13 (13u) /*!< The selection of FLEXCAN MB Channel 13. */
#define FLEXCAN_CHN_14 (14u) /*!< The selection of FLEXCAN MB Channel 14. */
#define FLEXCAN_CHN_15 (15u) /*!< The selection of FLEXCAN MB Channel 15. */
/*!
*@}
*/
/*!
* @addtogroup FLEXCAN_MB_INT
* @{
*/
#define FLEXCAN_INT_MB_0 (1u << 0u) /*!< Individual Mb 0 interrupt and clear fifo switcher. */
#define FLEXCAN_INT_MB_1 (1u << 1u) /*!< Individual Mb 1 interrupt switcher. */
#define FLEXCAN_INT_MB_2 (1u << 2u) /*!< Individual Mb 2 interrupt switcher. */
#define FLEXCAN_INT_MB_3 (1u << 3u) /*!< Individual Mb 3 interrupt switcher. */
#define FLEXCAN_INT_MB_4 (1u << 4u) /*!< Individual Mb 4 interrupt switcher. */
#define FLEXCAN_INT_MB_5 (1u << 5u) /*!< Individual Mb 5 interrupt and Rx fifo frame available switcher. */
#define FLEXCAN_INT_MB_6 (1u << 6u) /*!< Individual Mb 6 interrupt and Rx fifo warning interrupt switcher. */
#define FLEXCAN_INT_MB_7 (1u << 7u) /*!< Individual Mb 7 interrupt and Rx fifo overflow interrupt switcher. */
#define FLEXCAN_INT_MB_8 (1u << 8u) /*!< Individual Mb 8 interrupt switcher. */
#define FLEXCAN_INT_MB_9 (1u << 9u) /*!< Individual Mb 9 interrupt switcher. */
#define FLEXCAN_INT_MB_10 (1u << 10u) /*!< Individual Mb 10 interrupt switcher. */
#define FLEXCAN_INT_MB_11 (1u << 11u) /*!< Individual Mb 11 interrupt switcher. */
#define FLEXCAN_INT_MB_12 (1u << 12u) /*!< Individual Mb 12 interrupt switcher. */
#define FLEXCAN_INT_MB_13 (1u << 13u) /*!< Individual Mb 13 interrupt switcher. */
#define FLEXCAN_INT_MB_14 (1u << 14u) /*!< Individual Mb 14 interrupt switcher. */
#define FLEXCAN_INT_MB_15 (1u << 15u) /*!< Individual Mb 15 interrupt switcher. */
/*!
* @}
*/
/*!
* @addtogroup FLEXCAN_MB_STATUS
* @{
*/
#define FLEXCAN_STATUS_MB_0 (1u << 0u) /*!< Individual Mb 0 interrupt and clear fifo switcher. */
#define FLEXCAN_STATUS_MB_1 (1u << 1u) /*!< Individual Mb 1 interrupt switcher. */
#define FLEXCAN_STATUS_MB_2 (1u << 2u) /*!< Individual Mb 2 interrupt switcher. */
#define FLEXCAN_STATUS_MB_3 (1u << 3u) /*!< Individual Mb 3 interrupt switcher. */
#define FLEXCAN_STATUS_MB_4 (1u << 4u) /*!< Individual Mb 4 interrupt switcher. */
#define FLEXCAN_STATUS_MB_5 (1u << 5u) /*!< Individual Mb 5 interrupt and Rx fifo frame available switcher. */
#define FLEXCAN_STATUS_MB_6 (1u << 6u) /*!< Individual Mb 6 interrupt and Rx fifo warning interrupt switcher. */
#define FLEXCAN_STATUS_MB_7 (1u << 7u) /*!< Individual Mb 7 interrupt and Rx fifo overflow interrupt switcher. */
#define FLEXCAN_STATUS_MB_8 (1u << 8u) /*!< Individual Mb 8 interrupt switcher. */
#define FLEXCAN_STATUS_MB_9 (1u << 9u) /*!< Individual Mb 9 interrupt switcher. */
#define FLEXCAN_STATUS_MB_10 (1u << 10u) /*!< Individual Mb 10 interrupt switcher. */
#define FLEXCAN_STATUS_MB_11 (1u << 11u) /*!< Individual Mb 11 interrupt switcher. */
#define FLEXCAN_STATUS_MB_12 (1u << 12u) /*!< Individual Mb 12 interrupt switcher. */
#define FLEXCAN_STATUS_MB_13 (1u << 13u) /*!< Individual Mb 13 interrupt switcher. */
#define FLEXCAN_STATUS_MB_14 (1u << 14u) /*!< Individual Mb 14 interrupt switcher. */
#define FLEXCAN_STATUS_MB_15 (1u << 15u) /*!< Individual Mb 15 interrupt switcher. */
/*!
* @}
*/
/*!
* @brief FLEXCAN clock source type.
*/
typedef enum
{
FLEXCAN_ClockSource_Osc = 0u, /*!< CAN Protocol Engine will use the Oscillator clock. */
FLEXCAN_ClockSource_Periph = 1u, /*!< CAN Protocol Engine will use the Peripheral clock.*/
} FLEXCAN_ClockSource_Type;
/*!
* @brief FLEXCAN self wake up from bus off source.
*/
typedef enum
{
FLEXCAN_SelfWakeUp_Disabled = 0u, /*!< Disable self wake up, FLEXCAN can only back from Stop mode when its request is cleared. */
FLEXCAN_SelfWakeUp_BypassFilter = 1u, /*!< FLEXCAN can use the unfiltered Rx input to detect events on CAN bus then back from Stop mode. */
FLEXCAN_SelfWakeUp_WithFilter = 2u, /*!< FLEXCAN can use the filtered Rx input to detect events on CAN bus then back from Stop mode. */
} FLEXCAN_SelfWakeUp_Type;
/*!
* @brief FLEXCAN function mode.
*/
typedef enum
{
FLEXCAN_WorkMode_Normal = 0u, /*!< Normal work mode. */
FLEXCAN_WorkMode_LoopBack = 1u, /*!< Loop-back working mode, transfer and receive its own frame. */
FLEXCAN_WorkMode_ListenOnly = 2u, /*!< Listen-only mode, no transfer. */
} FLEXCAN_WorkMode_Type;
/*!
* @brief FLEXCAN Rx message buffer filter type.
*/
typedef enum
{
FLEXCAN_Mask_Global = 0u, /*!< Use global mask to filter all the received frame. */
FLEXCAN_Mask_Individual = 1u, /*!< Use individual mask to filter the received frame. */
} FLEXCAN_Mask_Type;
/*!
* @brief FLEXCAN Xfer Mb frame type switcher.
*/
typedef enum
{
FLEXCAN_MbType_Data = 0u, /*!< Data frames can be accepted and remote frames are rejected. */
FLEXCAN_MbType_Remote = 1u, /*!< Data frames can be rejected and remote frames are accepted. */
} FLEXCAN_MbType_Type;
/*!
* @brief FLEXCAN Xfer Mb frame format switcher.
*/
typedef enum
{
FLEXCAN_MbFormat_Standard = 0u, /*!< Only Standard format frames can be accepted. */
FLEXCAN_MbFormat_Extended = 1u, /*!< Only Extended format frames can be accepted. */
} FLEXCAN_MbFormat_Type;
/*!
* @brief FLEXCAN Rx fifo ID filter type.
*/
typedef enum
{
FLEXCAN_FifoIdFilterFormat_A = 0u, /*!< Format A: One full ID (standard and extended) per ID Filter Table element. */
FLEXCAN_FifoIdFilterFormat_B = 1u, /*!< Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.*/
FLEXCAN_FifoIdFilterFormat_C = 2u, /*!< Format C: Four partial 8-bit Standard IDs per ID Filter Table element. */
FLEXCAN_FifoIdFilterFormat_D = 3u, /*!< Format D: All frames rejected. */
} FLEXCAN_FifoIdFilterFormat_Type;
/*!
* @brief FLEXCAN fifo priority type.
*/
typedef enum
{
FLEXCAN_FifoPriority_MbFirst = 0u, /*!< Mactching process start with message buffer. */
FLEXCAN_FifoPriority_FifoFirst = 1u, /*!< Mactching process start with fifo. */
}FLEXCAN_FifoPriority_Type;
/*!
* @brief FLEXCAN Xfer MB frame code switcher.
*/
typedef enum
{
FLEXCAN_MbCode_RxInactive = 0u, /*!< Code for MB being not active. */
FLEXCAN_MbCode_RxFull = 2u, /*!< Code for MB being full. */
FLEXCAN_MbCode_RxEmpty = 4u, /*!< Code for MB being active and empty. */
FLEXCAN_MbCode_RxOverrun = 6u, /*!< Code for MB being over written without accessing the received frame. */
FLEXCAN_MbCode_TxInactive = 8u, /*!< Code for data response for Tx inactive. */
FLEXCAN_MbCode_TxAbort = 9u, /*!< Code for Tx abort after transmission. */
FLEXCAN_MbCode_RxRanswer = 10u, /*!< Code for Rx waiting for remote frame. */
FLEXCAN_MbCode_TxDataOrRemote = 12u, /*!< Code for data frame or remote frame transmission. */
FLEXCAN_MbCode_TxTanswer = 14u, /*!< Code for data response for remote frame. */
FLEXCAN_MbCode_RxBusy = 15u, /*!< Code for Rx updating MB. */
} FLEXCAN_MbCode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetTimingConf() to initialize the time configuration.
*/
typedef struct
{
bool EnableExtendedTime; /*!< If enable, the setting time range can be broader. */
uint32_t PhaSegLen1; /*!< Phase segment 1. Compensate for edge phase errors and may be lengthened during resynchronization.*/
uint32_t PhaSegLen2; /*!< Phase segment 2. Compensate for edge phase errors and may be lengthened during resynchronization.*/
uint32_t PropSegLen; /*!< Propagation segment. Compensate for signal delays across the network.*/
uint32_t JumpWidth; /*!< Resynchronize jump width. */
uint32_t PreDiv; /*!< The divider for FLEXCAN clock source. */
} FLEXCAN_TimConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_Init() to initialize the general setting of FLEXCAN.
*/
typedef struct
{
uint8_t MaxXferNum; /*!< Max number of message buffer to be used. */
uint32_t BaudRate; /*!< Data bit per second when using FLEXCAN for transmision and reception. */
uint32_t ClockFreqHz; /*!< Clock source frequency. */
FLEXCAN_ClockSource_Type ClockSource; /*!< Clock source selection. */
FLEXCAN_SelfWakeUp_Type SelfWakeUp; /*!< Stop mode self wake up source. */
FLEXCAN_WorkMode_Type WorkMode; /*!< FLEXCAN function mode. */
FLEXCAN_Mask_Type Mask; /*!< Filter work range for filtering the received frames. */
FLEXCAN_TimConf_Type * TimConf; /*!< FLEXCAN timer and time synchronization setup. */
bool EnableSelfReception; /*!< Whether to receive frames sent by FLEXCAN itself. */
bool EnableTimerSync; /*!< Refresh the timer every frame reception. */
} FLEXCAN_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetGlobalMbMaskConf() to set the mask for buffer.
*/
typedef struct
{
FLEXCAN_MbType_Type MbType; /*!< Data frame or Remote frame switcher. */
FLEXCAN_MbFormat_Type MbFormat; /*!< Extended or standard id switcher. */
uint32_t IdMask; /*!< Id mask. */
} FLEXCAN_RxMbMaskConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetRxFifoGlobalMaskConf() to set the conf for fifo mask filter.
*/
typedef struct
{
FLEXCAN_MbType_Type MbType; /*!< Data frame or Remote frame switcher. */
FLEXCAN_MbFormat_Type MbFormat; /*!< Extended or standard id switcher. */
FLEXCAN_FifoIdFilterFormat_Type FilterFormat; /*!< fifo filter format. */
union
{
uint32_t RxIdA; /*!< The fifo Id setting for filter format A. */
uint16_t RxIdB[2]; /*!< The fifo Id setting for filter format B. */
uint8_t RxIdC[4]; /*!< The fifo Id setting for filter format C. */
};
} FLEXCAN_RxFifoMaskConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetRxMb() to set the mask for buffer.
*/
typedef struct
{
FLEXCAN_MbType_Type MbType; /*!< Data frame or Remote frame switcher. */
FLEXCAN_MbFormat_Type MbFormat; /*!< Extended or standard id switcher. */
uint32_t Id; /*!< Id value. */
} FLEXCAN_RxMbConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_EnableRxFifo() to initialize the fifo setting.
*/
typedef struct
{
FLEXCAN_FifoIdFilterFormat_Type FilterFormat; /*!< fifo filter format which will decide how to filter the fifo reception. */
uint32_t IdFilterNum; /*!< The fifo filter element num. */
uint32_t * IdFilterTable; /*!< Filter array to be set for Rx fifo. */
FLEXCAN_FifoPriority_Type priority; /*!< Enable matching process start with fifo. */
} FLEXCAN_RxFifoConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_WriteTxMb() to set the mask for buffer.
*/
typedef struct
{
struct
{
uint32_t TIMESTAMP : 16; /*!< Free-running counter time stamp. */
uint32_t LENGTH : 4; /*!< Length of Data in Bytes. */
uint32_t TYPE : 1; /*!< Frame data type or remote type. */
uint32_t FORMAT : 1; /*!< Frame extended format or standard format. */
uint32_t RESERVED_0 : 1; /*!< Reservation. */
uint32_t IDHIT : 9; /*!< Id filter number hit by fifo. */
};
struct
{
uint32_t ID :29; /*!< Frame Identifier. */
uint32_t PRIORITY: 3; /*!< Local priority. */
};
union
{
struct
{
uint32_t WORD0; /*!< CAN Frame payload word0. */
uint32_t WORD1; /*!< CAN Frame payload word1. */
};
struct
{
/* The sequence refers to the little-endian-storage and big-endian transfer. */
uint8_t BYTE3; /*!< CAN Frame payload byte3. */
uint8_t BYTE2; /*!< CAN Frame payload byte2. */
uint8_t BYTE1; /*!< CAN Frame payload byte1. */
uint8_t BYTE0; /*!< CAN Frame payload byte0. */
uint8_t BYTE7; /*!< CAN Frame payload byte7. */
uint8_t BYTE6; /*!< CAN Frame payload byte6. */
uint8_t BYTE5; /*!< CAN Frame payload byte5. */
uint8_t BYTE4; /*!< CAN Frame payload byte4. */
};
};
} FLEXCAN_Mb_Type;
/*!
* @brief Enable the FLEXCAN module.
*
* @param FLEXCANx FLEXCAN instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void FLEXCAN_Enable(FLEXCAN_Type * FLEXCANx, bool enable);
/*!
* @brief Enable soft reset of FLEXCAN registers.
*
* This will reset most part of the FLEXCAN registers.
*
* @param FLEXCANx FLEXCAN instance.
* @return None.
*/
void FLEXCAN_DoSoftReset(FLEXCAN_Type * FLEXCANx);
/*!
* @brief Set up the FLEXCAN module with the indicated setting.
*
* @param FLEXCANx FLEXCAN instance.
* @param init Pointer to the initialization structure. See to @ref FLEXCAN_Init_Type.
* @return 'true' to setup the FLEXCAN module successfully, false to fail to set the baudrate wrongly.
*/
bool FLEXCAN_Init(FLEXCAN_Type * FLEXCANx, FLEXCAN_Init_Type * init);
/*!
* @brief Set up the FLEXCAN timing module with the indicated setting.
*
* This would work when people want to change the boadrate after setting up the module.
*
* @param FLEXCANx FLEXCAN instance.
* @param conf Pointer to the initialization structure. See to @ref FLEXCAN_TimConf_Type.
* @return None.
*/
void FLEXCAN_SetTimingConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_TimConf_Type * conf);
/*!
* @brief Enter freeze mode for configuration.
*
* @param FLEXCANx FLEXCAN instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void FLEXCAN_EnableFreezeMode(FLEXCAN_Type * FLEXCANx, bool enable);
/*!
* @brief Set the Rx message buffer mask globally.
*
* Setting should be done after entering Freeze Mode.
*
* @param FLEXCANx FLEXCAN instance.
* @param conf Indicated mask and Mb frame type and format to be set for 16 message buffer globally. See to @ref FLEXCAN_RxMbMaskConf_Type.
* @return None.
*/
void FLEXCAN_SetGlobalMbMaskConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxMbMaskConf_Type * conf);
/*!
* @brief Set the Rx fifo mask globally.
*
* Setting should be done after entering Freeze Mode.
*
* @param FLEXCANx FLEXCAN instance.
* @param mask Indicated mask to be set for 16 message buffer globally. See to @ref FLEXCAN_RxFifoMaskConf_Type.
* @return None.
*/
void FLEXCAN_SetRxFifoGlobalMaskConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxFifoMaskConf_Type * mask);
/*!
* @brief Set Rx message buffer mask individually.
*
* Setting should be done after entering Freeze Mode.
*
* @param FLEXCANx FLEXCAN instance.
* @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION.
* @param mask Indicated mask to be set for 16 message buffer globally. See to @ref FLEXCAN_RxMbMaskConf_Type.
* @return None.
*/
void FLEXCAN_SetRxMbIndividualMaskConf(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbMaskConf_Type * mask);
/*!
* @brief Clear the indicated MB.
*
* Clear the previous information in the buffer.
*
* @param FLEXCANx FLEXCAN instance.
* @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION.
* @return None.
*/
void FLEXCAN_ResetMb(FLEXCAN_Type * FLEXCANx, uint32_t channel);
/*!
* @brief Clear message buffer with value 0.
*
* Clear the previous information in the buffer.
*
* @param FLEXCANx FLEXCAN instance.
* @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION.
* @param code The code to be set in Mb channel. See to @ref FLEXCAN_MbCode_Type.
* @return None.
*/
void FLEXCAN_SetMbCode(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_MbCode_Type code);
/*!
* @brief Set Rx message buffer before reception.
*
* Prepare the type, format and id for Rx receiving.
*
* @param FLEXCANx FLEXCAN instance.
* @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION.
* @param conf Configuration for Rx Mb receiving. See to @ref FLEXCAN_RxMbConf_Type.
* @return None.
*/
void FLEXCAN_SetRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbConf_Type * conf);
/*!
* @brief Setup the Rx fifo setting.
*
* Need to be done under freeze mode.
*
* @param FLEXCANx FLEXCAN instance.
* @param conf Pointer to the configuration structure. See to @ref FLEXCAN_RxFifoConf_Type.
* @return 'true' to enbale the Rx fifo successfully, 'false' to fail for setting the filter number wrongly.
*/
bool FLEXCAN_EnableRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxFifoConf_Type * conf);
/*!
* @brief Enable global FLEXCAN interrupts.
*
* @param FLEXCANx FLEXCAN instance.
* @param interrupts Global interrupts to be set simultaneously. See to @ref FLEXCAN_GLOBAL_INT.
* @param enable 'true' to enable the interrupts, 'false' to disable the interrupts.
* @return None.
*/
void FLEXCAN_EnableInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable);
/*!
* @brief Get the error status and global status of FLEXCAN.
*
* @param FLEXCANx FLEXCAN instance.
* @return FLEXCAN status. See to @ref FLEXCAN_STATUS.
*/
uint32_t FLEXCAN_GetStatus(FLEXCAN_Type * FLEXCANx);
/*!
* @brief Get the error status and global status of FLEXCAN.
*
* @param FLEXCANx FLEXCAN instance.
* @param flags Flags to be cleared. See to @ref FLEXCAN_STATUS.
* @return None.
*/
void FLEXCAN_ClearStatus(FLEXCAN_Type * FLEXCANx, uint32_t flags);
/*!
* @brief Enable FLEXCAN individual message buffer interrupts.
*
* @param FLEXCANx FLEXCAN instance.
* @param interrupts Global interrupts to be set simultaneously. See to @ref FLEXCAN_MB_INT.
* @param enable 'true' to enable the interrupts, 'false' to disable the interrupts.
* @return None.
*/
void FLEXCAN_EnableMbInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable);
/*!
* @brief Get the buffer status or fifo status of FLEXCAN.
*
* @param FLEXCANx FLEXCAN instance.
* @return FLEXCAN buffer status. See to @ref FLEXCAN_MB_STATUS.
*/
uint32_t FLEXCAN_GetMbStatus(FLEXCAN_Type * FLEXCANx);
/*!
* @brief Get the buffer status or fifo status of FLEXCAN.
*
* @param FLEXCANx FLEXCAN instance.
* @param mbs FLEXCAN buffer status to be cleared. See to @ref FLEXCAN_MB_STATUS.
* @return None.
*/
void FLEXCAN_ClearMbStatus(FLEXCAN_Type * FLEXCANx, uint32_t mbs);
/*!
* @brief Enable Fifo DMA of FLEXCAN fifo.
*
* Should be done under freeze mode.
*
* @param FLEXCANx FLEXCAN instance.
* @param enable 'true' to enable the DMA, 'false' to disable the DMA.
* @return None.
*/
void FLEXCAN_EnableFifoDMA(FLEXCAN_Type * FLEXCANx, bool enable);
/*!
* @brief Get the Tx error counter value.
*
* @param FLEXCANx FLEXCAN instance.
* @return Tx error counter value.
*/
uint32_t FLEXCAN_GetTxError(FLEXCAN_Type * FLEXCANx);
/*!
* @brief Get the Rx error counter value.
*
* @param FLEXCANx FLEXCAN instance.
* @return Rx error counter value.
*/
uint32_t FLEXCAN_GetRxError(FLEXCAN_Type * FLEXCANx);
/*!
* @brief Get the fifo address.
*
* @param FLEXCANx FLEXCAN instance.
* @return fifo address of the FLEXCAN.
*/
uint32_t FLEXCAN_GetFifoAddr(FLEXCAN_Type * FLEXCANx);
/*!
* @brief Write the Mb frame into the indicated Mb channel.
*
* @param FLEXCANx FLEXCAN instance.
* @param channel The indicated FLEXCAN Mb channel.
* @param mb The prepared Mb for Tx. See to @ref FLEXCAN_Mb_Type.
* @return 'true' to put the Mb frame successfully, 'false' to fail.
*/
bool FLEXCAN_WriteTxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb);
/*!
* @brief Read the Mb frame from the indicated Mb channel.
*
* @param FLEXCANx FLEXCAN instance.
* @param channel The indicated FLEXCAN Mb channel.
* @param mb The Mb for Rx. See to @ref FLEXCAN_Mb_Type.
* @return 'true' to get the Mb frame successfully, 'false' to fail.
*/
bool FLEXCAN_ReadRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb);
/*!
* @brief Read the fifo Mb frame from fifo.
*
* @param FLEXCANx FLEXCAN instance.
* @param mb Pointer to the Mb structure. See to @ref FLEXCAN_Mb_Type.
* @return 'true' to get the Mb frame successfully, 'false' to fail.
*/
bool FLEXCAN_ReadRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_Mb_Type * mb);
/*!
* @brief Get the number of buffer corresponding to the latest transmitted crc.
*
* @param FLEXCANx FLEXCAN instance.
* @param channel Channel match the latest transmission crc value.
* @return Latest transmission crc value.
*/
uint32_t FLEXCAN_GetMatchCrcValue(FLEXCAN_Type * FLEXCANx, uint32_t * channel);
/*!
*@}
*/
#endif /* __HAL_FLEXCAN_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_fsmc.h"
const uint32_t FSMC_BankBases[] =
{
FSMC_BANK0_BASE,
FSMC_BANK1_BASE,
FSMC_BANK2_BASE,
FSMC_BANK3_BASE
};
void FSMC_Init(FSMC_Type * FSMCx, uint32_t bankn, FSMC_Init_Type * init)
{
FSMCx->SMSKR[bankn] = ( (FSMCx->SMSKR[bankn] & ~(FSMC_SMSKR_MEMSIZE_MASK | FSMC_SMSKR_MEMTYPE_MASK) )
| FSMC_SMSKR_MEMSIZE(init->MemSize)
| FSMC_SMSKR_MEMTYPE(init->MemType) )
;
}
void FSMC_SetConf(FSMC_Type * FSMCx, uint32_t index, FSMC_Conf_Type * init)
{
if (index >= FSMC_SMTMGR_REG_NUM)
{
return;
}
FSMCx->SMTMGRSET[index] = FSMC_SMTMGRSET_TRC(init->ReadPeriod)
| FSMC_SMTMGRSET_TAS(init->AddrSetTime)
| FSMC_SMTMGRSET_TWR(init->WriteHoldTime)
| FSMC_SMTMGRSET_TWP(init->WritePeriod)
| FSMC_SMTMGRSET_READYMODE(init->ReadySignal)
| FSMC_SMTMGRSET_SMREADPIPE(init->SMReadPipe)
;
switch (index)
{
case 0u:
FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDW_MASK)
| FSMC_SMCTLR_SMDW(init->BusWidth) )
;
break;
case 1u:
FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDW1_MASK)
| FSMC_SMCTLR_SMDW1(init->BusWidth) )
;
break;
case 2u:
FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDW2_MASK)
| FSMC_SMCTLR_SMDW2(init->BusWidth) )
;
break;
default:
break;
}
}
/* only last enabled bankn is available. */
void FSMC_EnableConf(FSMC_Type * FSMCx, uint32_t bankn, uint32_t index)
{
if (index >= FSMC_SMTMGR_REG_NUM)
{
return;
}
FSMCx->SMSKR[bankn] = ( (FSMCx->SMSKR[bankn] & ~FSMC_SMSKR_REGSELECT_MASK)
| FSMC_SMSKR_REGSELECT(index) )
;
}
void FSMC_PutData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint32_t data)
{
(void)FSMCx;
*( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) = data;
}
uint32_t FSMC_GetData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (*( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) );
}
uint32_t FSMC_GetXferDataRegAddr(FSMC_Type *FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (FSMC_BankBases[bankn] + offset);
}
void FSMC_PutData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint16_t data)
{
(void)FSMCx;
*( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) = data;
}
uint16_t FSMC_GetData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (*( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) );
}
void FSMC_PutData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint8_t data)
{
(void)FSMCx;
*( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) = data;
}
uint8_t FSMC_GetData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (*( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) );
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_FSMC_H__
#define __HAL_FSMC_H__
#include "hal_common.h"
/*
* There are still some configurations in SYSCFG_CFGR1:
* - switch between 8080 mode and NOR FLASH mode.
* - disable the reuse of data pins as address pins.
* - enable the fsmc sync.
*/
/*!
* @addtogroup FSMC
* @{
*/
/*!
* @brief FSMC driver version number.
*/
#define FSMC_DRIVER_VERSION 0u /*!< fsmc_0. */
/*!
* @brief FSMC memory type.
*/
typedef enum
{
FSMC_MemType_SRAM = 1u, /*!< Mem type: SRAM. */
FSMC_MemType_NorFlash = 2u, /*!< Mem type: NorFlash. */
FSMC_MemType_PSRAM = 3u, /*!< Mem type: PSRAM. */
} FSMC_MemType_Type;
/*!
* @brief FSMC memory size type.
*/
typedef enum
{
FSMC_MemSize_NoDevice = 0u, /*!< Mem Size type: NoDevice. */
FSMC_MemSize_64KB = 1u, /*!< Mem Size type: 64KB. */
FSMC_MemSize_128KB = 2u, /*!< Mem Size type: 128KB. */
FSMC_MemSize_256KB = 3u, /*!< Mem Size type: 256KB. */
FSMC_MemSize_512KB = 4u, /*!< Mem Size type: 512KB. */
FSMC_MemSize_1MB = 5u, /*!< Mem Size type: 1MB. */
FSMC_MemSize_2MB = 6u, /*!< Mem Size type: 2MB. */
FSMC_MemSize_4MB = 7u, /*!< Mem Size type: 4MB. */
FSMC_MemSize_8MB = 8u, /*!< Mem Size type: 8MB. */
FSMC_MemSize_16MB = 9u, /*!< Mem Size type: 16MB. */
FSMC_MemSize_32MB = 10u, /*!< Mem Size type: 32MB. */
FSMC_MemSize_64MB = 11u, /*!< Mem Size type: 64MB. */
FSMC_MemSize_128MB = 12u, /*!< Mem Size type: 128MB. */
FSMC_MemSize_256MB = 13u, /*!< Mem Size type: 256MB. */
FSMC_MemSize_512MB = 14u, /*!< Mem Size type: 512MB. */
FSMC_MemSize_1GB = 15u, /*!< Mem Size type: 1GB. */
FSMC_MemSize_2GB = 16u, /*!< Mem Size type: 2GB. */
FSMC_MemSize_4GB = 17u, /*!< Mem Size type: 4GB. */
} FSMC_MemSize_Type;
/*!
* @brief FSMC ready signal type.
*/
typedef enum
{
FSMC_ReadySignal_Internal = 0u, /*!< The ready signal is inside the FSMC, do not need the external ready signal. */
FSMC_ReadySignal_External = 1u, /*!< The ready signal is from external device. */
} FSMC_ReadySignal_Type;
/*!
* @brief FSMC bus width type.
*/
typedef enum
{
FSMC_BusWidth_8b = 4u, /*!< Bus width: 8bit. */
FSMC_BusWidth_16b = 0u, /*!< Bus width: 16bit. */
FSMC_BusWidth_32b = 1u, /*!< Bus width: 32bit. */
} FSMC_BusWidth_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FSMC_Init() to initialize the FSMC module.
*/
typedef struct
{
FSMC_MemType_Type MemType; /*!< Specify the memory type. */
FSMC_MemSize_Type MemSize; /*!< Specify the memory size. */
} FSMC_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FSMC_SetConf() to initialize the FSMC config.
*/
typedef struct
{
uint32_t ReadPeriod; /*!< the cycles for 'reading data', NOE available period. */
uint32_t AddrSetTime; /*!< the cycles for 'setup' when writing. */
uint32_t WriteHoldTime; /*!< the cycles between the master write action and slave capture done. */
uint32_t WritePeriod; /*!< the cycles for 'keep data' in writing operation, NWE available period. */
FSMC_ReadySignal_Type ReadySignal; /*!< select if capture the external ready signal. */
uint32_t SMReadPipe; /*!< the cycles between the read action and release the bus.*/
FSMC_BusWidth_Type BusWidth; /*!< Specify the bus width. */
} FSMC_Conf_Type;
/*!
* @brief Initialize the FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param init Pointer to the initialization structure. See to @ref FSMC_Init_Type.
* @return None.
*/
void FSMC_Init(FSMC_Type * FSMCx, uint32_t bankn, FSMC_Init_Type * init);
/*!
* @brief Set the FSMC config.
*
* @param FSMCx FSMC instance.
* @param index Config index.
* @param conf Pointer to the config structure. See to @ref FSMC_Conf_Type.
* @return None.
*/
void FSMC_SetConf(FSMC_Type * FSMCx, uint32_t index, FSMC_Conf_Type * conf);
/*!
* @brief Enable the FSMC config.
*
* Only last enabled config is available.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param index Config index.
* @return None.
*/
void FSMC_EnableConf(FSMC_Type * FSMCx, uint32_t bankn, uint32_t index);
/*!
* @brief Get the Xfer data reg addr.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The addr value of Xfer data reg.
*/
uint32_t FSMC_GetXferDataRegAddr(FSMC_Type *FSMCx, uint32_t bankn, uint32_t offset);
/*!
* @brief Put the 32bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void FSMC_PutData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint32_t data);
/*!
* @brief Get the 32bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The data value received from FSMC.
*/
uint32_t FSMC_GetData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset);
/*!
* @brief Put the 16bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void FSMC_PutData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint16_t data);
/*!
* @brief Get the 16bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The data value received from FSMC.
*/
uint16_t FSMC_GetData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset);
/*!
* @brief Put the 8bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void FSMC_PutData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint8_t data);
/*!
* @brief Get the 8bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The data value received from FSMC.
*/
uint8_t FSMC_GetData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset);
/*!
*@}
*/
#endif /* __HAL_FSMC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_gpio.h"
void GPIO_Init(GPIO_Type * GPIOx, GPIO_Init_Type * init)
{
uint8_t idx;
uint8_t i;
uint32_t pin;
__IO uint32_t * addr;
/* 1x. */
uint32_t dat = init->PinMode & 0xFu;
if (init->PinMode & 0x10u)
{
dat |= init->Speed;
}
/* 0x. */
addr = &(GPIOx->CRL);
for (i = 0u; i < 8u; i++)
{
idx = i * 4u;
if ( (init->Pins) & (1u << i) )
{
*addr = ( *addr & ~(0xFu << idx) ) | (dat << idx);
}
}
addr = &(GPIOx->CRH);
pin = init->Pins >> 8u;
for (i = 0u; i < 8u; i++)
{
idx = i * 4u;
if ( pin & (1u << i) )
{
*addr = ( *addr & ~(0xFu << idx) ) | (dat << idx);
}
}
/* 2x,4x. */
if (init->PinMode == GPIO_PinMode_In_PullDown)
{
GPIOx->BRR |= init->Pins;
}
else if (init->PinMode == GPIO_PinMode_In_PullUp)
{
GPIOx->BSRR |= init->Pins;
}
}
bool GPIO_ReadInDataBit(GPIO_Type * GPIOx, uint16_t pin)
{
return (GPIOx->IDR & pin);
}
uint16_t GPIO_ReadInData(GPIO_Type * GPIOx)
{
return (uint16_t)(GPIOx->IDR);
}
bool GPIO_ReadOutDataBit(GPIO_Type * GPIOx, uint16_t pins)
{
return (GPIOx->ODR & pins);
}
uint16_t GPIO_ReadOutData(GPIO_Type * GPIOx)
{
return (uint16_t)GPIOx->ODR;
}
void GPIO_SetBits(GPIO_Type * GPIOx, uint16_t pins)
{
GPIOx->BSRR = pins;
}
void GPIO_ClearBits(GPIO_Type * GPIOx, uint16_t pins)
{
GPIOx->BRR = pins;
}
void GPIO_WriteBit(GPIO_Type * GPIOx, uint16_t pins, uint16_t val)
{
(val != 0u) ? (GPIOx->BSRR = pins) : (GPIOx->BRR = pins);
}
void GPIO_WriteBits(GPIO_Type * GPIOx, uint16_t val)
{
GPIOx->ODR = val;
}
void GPIO_PinLock(GPIO_Type * GPIOx, uint16_t pins, bool enable_lock)
{
(enable_lock) ? (GPIOx->LCKR |= pins) : (GPIOx->LCKR &= ~pins);
}
void GPIO_PinLockConf(GPIO_Type * GPIOx, uint16_t pins)
{
GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins);
GPIOx->LCKR = pins;
GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins);
GPIOx->LCKR;
GPIOx->LCKR;
}
void GPIO_PinAFConf(GPIO_Type * GPIOx, uint16_t pins, uint8_t af)
{
uint32_t shift = 0u;
uint32_t idx = 0u;
uint32_t val = GPIOx->AFRL;
while (idx < 8u)
{
if ( ( (1u << idx) & pins) != 0u )
{
shift = idx * 4u;
val &= ~(0xFu << shift);
val |= (uint32_t)af << shift;
}
idx++;
}
GPIOx->AFRL = val;
val = GPIOx->AFRH;
while (idx < 16u)
{
if ( ( (1u << idx) & pins) != 0u )
{
shift = (idx - 8u) * 4u;
val &= ~(0xFu << shift);
val |= (uint32_t)af << shift;
}
idx++;
}
GPIOx->AFRH = val;
}
void GPIO_PortAFConfig(GPIO_Type * GPIOx, uint32_t af_high, uint32_t af_low)
{
GPIOx->AFRL = af_low;
GPIOx->AFRH = af_high;
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_GPIO_H__
#define __HAL_GPIO_H__
#include "hal_common.h"
/*!
* @addtogroup GPIO
* @{
*/
/*!
* @addtogroup GPIO_PIN
* @brief GPIO pin mask codes.
* @{
*/
#define GPIO_PIN_0 (0x0001u) /*!< Pin 0 selected. */
#define GPIO_PIN_1 (0x0002u) /*!< Pin 1 selected. */
#define GPIO_PIN_2 (0x0004u) /*!< Pin 2 selected. */
#define GPIO_PIN_3 (0x0008u) /*!< Pin 3 selected. */
#define GPIO_PIN_4 (0x0010u) /*!< Pin 4 selected. */
#define GPIO_PIN_5 (0x0020u) /*!< Pin 5 selected. */
#define GPIO_PIN_6 (0x0040u) /*!< Pin 6 selected. */
#define GPIO_PIN_7 (0x0080u) /*!< Pin 7 selected. */
#define GPIO_PIN_8 (0x0100u) /*!< Pin 8 selected. */
#define GPIO_PIN_9 (0x0200u) /*!< Pin 9 selected. */
#define GPIO_PIN_10 (0x0400u) /*!< Pin 10 selected. */
#define GPIO_PIN_11 (0x0800u) /*!< Pin 11 selected. */
#define GPIO_PIN_12 (0x1000u) /*!< Pin 12 selected. */
#define GPIO_PIN_13 (0x2000u) /*!< Pin 13 selected. */
#define GPIO_PIN_14 (0x4000u) /*!< Pin 14 selected. */
#define GPIO_PIN_15 (0x8000u) /*!< Pin 15 selected. */
#define GPIO_PINS_ALL (0xFFFFu) /*!< All pins selected. */
/*!
* @}
*/
/*!
* @addtogroup GPIO_AF
* @brief GPIO pin alternative function.
* @{
*/
#define GPIO_AF_0 (0x00u) /*!< Alternative function 0. */
#define GPIO_AF_1 (0x01u) /*!< Alternative function 1. */
#define GPIO_AF_2 (0x02u) /*!< Alternative function 2. */
#define GPIO_AF_3 (0x03u) /*!< Alternative function 3. */
#define GPIO_AF_4 (0x04u) /*!< Alternative function 4. */
#define GPIO_AF_5 (0x05u) /*!< Alternative function 5. */
#define GPIO_AF_6 (0x06u) /*!< Alternative function 6. */
#define GPIO_AF_7 (0x07u) /*!< Alternative function 7. */
#define GPIO_AF_8 (0x08u) /*!< Alternative function 8. */
#define GPIO_AF_9 (0x09u) /*!< Alternative function 9. */
#define GPIO_AF_10 (0x0Au) /*!< Alternative function 10. */
#define GPIO_AF_11 (0x0Bu) /*!< Alternative function 11. */
#define GPIO_AF_12 (0x0Cu) /*!< Alternative function 12. */
#define GPIO_AF_13 (0x0Du) /*!< Alternative function 13. */
#define GPIO_AF_14 (0x0Eu) /*!< Alternative function 14. */
#define GPIO_AF_15 (0x0Fu) /*!< Alternative function 15. */
/*!
* @}
*/
/*!
* @brief GPIO maximum speed type.
*/
typedef enum
{
GPIO_Speed_10MHz = 1u, /*!< Maximum speed is 10MHz. */
GPIO_Speed_20MHz = 2u, /*!< Maximum speed is 20MHz. */
GPIO_Speed_50MHz = 3u, /*!< Maximum speed is 50MHz. */
} GPIO_Speed_Type;
/*!
* @brief Port input / output mode.
*/
typedef enum
{
GPIO_PinMode_In_Analog = 0x00u, /*!< Analog input. */
GPIO_PinMode_In_Floating = 0x04u, /*!< Floating input. */
GPIO_PinMode_In_PullDown = 0x28u, /*!< Pull down input. */
GPIO_PinMode_In_PullUp = 0x48u, /*!< Pull up input. */
GPIO_PinMode_Out_OpenDrain = 0x14u, /*!< Universal open drain output. */
GPIO_PinMode_Out_PushPull = 0x10u, /*!< Universal push-pull output. */
GPIO_PinMode_AF_OpenDrain = 0x1Cu, /*!< Multiplex open drain output. */
GPIO_PinMode_AF_PushPull = 0x18u, /*!< Multiplexed push-pull output. */
} GPIO_PinMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref GPIO_Init() to initialize the GPIO module.
*/
typedef struct
{
uint16_t Pins; /*!< GPIO operating pins. */
GPIO_Speed_Type Speed; /*!< GPIO pin speed mode. */
GPIO_PinMode_Type PinMode; /*!< GPIO pin input / output functional mode. */
} GPIO_Init_Type;
/*!
* @brief Initialize the GPIO module.
*
* @param GPIOx GPIO instance.
* @param init Pointer to the initialization structure. See to @ref GPIO_Init_Type.
* @return None.
*/
void GPIO_Init(GPIO_Type * GPIOx, GPIO_Init_Type * init);
/*!
* @brief Set the specified data port bit.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return None.
*/
void GPIO_SetBits(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Clear the specified data port bit.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return None.
*/
void GPIO_ClearBits(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Writes 0 or 1 to the specified bit.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @param val Decide whether to set or clear.
* @return None.
*/
void GPIO_WriteBit(GPIO_Type * GPIOx, uint16_t pins, uint16_t val);
/*!
* @brief Write 0 or 1 for multiple I/O ports.
*
* @param GPIOx GPIO instance.
* @param val Decide whether to set or clear.
* @return None.
*/
void GPIO_WriteBits(GPIO_Type * GPIOx, uint16_t val);
/*!
* @brief Keep the set I/O configuration can not be changed.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @param enable_lock enable 'true' to enable the lock, 'false' to disable the lock.
* @return None.
*/
void GPIO_PinLock(GPIO_Type * GPIOx, uint16_t pins, bool enable_lock);
/*!
* @brief Lock the corresponding bit of the select port configuration register.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return None.
*/
void GPIO_PinLockConf(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Read the value once entered before by the specified pin.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return Status of a pin's logic level, 0 for low level or 1 for high level.
*/
bool GPIO_ReadInDataBit(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Read the value previously output by the specified pin.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return Status of a pin's logic level, 0 for low level or 1 for high level.
*/
bool GPIO_ReadOutDataBit(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Read the specified GPIO port input.
*
* @param GPIOx GPIO instance.
* @return A hexadecimal number.
*/
uint16_t GPIO_ReadInData(GPIO_Type * GPIOx);
/*!
* @brief Read the specified GPIO port output.
*
* @param GPIOx GPIO instance.
* @return A hexadecimal number.
*/
uint16_t GPIO_ReadOutData(GPIO_Type * GPIOx);
/*!
* @brief Pin alternate function configuration of GPIO.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @param alternate_function Reuse the unified I/O port, but the function is different.
* @return None.
*/
void GPIO_PinAFConf(GPIO_Type* GPIOx, uint16_t pins, uint8_t alternate_function);
/*!
* @}
*/
#endif /* __HAL_GPIO_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_i2c.h"
/* Configure I2C speed to ordinary speed. */
static bool I2C_CalcBandrate(I2C_Type * I2Cx, uint32_t clk, uint32_t bandrate)
{
/*
* SCLH = (xSHR + 12) * I2C_CLK + tSYNC1;
* SCLL = (xSLR + 1) * I2C_CLK + tSYNC2;
* tSYNC1 & tSYNC2 equal 0 ~ 1 clk.
*/
if ( (clk / 24u) < bandrate ) /* the system clock cannot meet the baud rate requirement. */
{
return false;
}
else
{
uint32_t tmp = clk / bandrate;
I2Cx->SSHR = tmp / 2u - 12u; /* Configure high level count in normal speed. */
I2Cx->SSLR = tmp / 2u - 1u; /* Configure low level count in normal speed. */
I2Cx->FSHR = tmp / 2u - 14u; /* Configure high level count in fast speed. */
I2Cx->FSLR = tmp / 2u - 3u; /* Configure low level count in fast speed. */
return true;
}
}
/* Initialize I2C, Initialization failure return false, Initialization success return true. */
bool I2C_InitMaster(I2C_Type * I2Cx, I2C_Master_Init_Type * init)
{
I2Cx->ENR &= ~I2C_ENR_ENABLE_MASK; /* Disable I2C. */
if ( !I2C_CalcBandrate(I2Cx, init->ClockFreqHz, init->BaudRate) ) /* The system clock cannot meet the baud rate requirement. */
{
return false;
}
I2Cx->CR = I2C_CR_SPEED(1u);
/* Setup I2C. */
I2Cx->CR &= ~I2C_CR_MASTER10_MASK; /* Address format. */
I2Cx->CR |= I2C_CR_RESTART_MASK /* Generate restart signal. */
| I2C_CR_DISSLAVE_MASK /* Disable slave module. */
| I2C_CR_REPEN_MASK /* Enable sending restart condition. */
| I2C_CR_EMPINT_MASK /* Control tx_empty interrupt generation. */
| I2C_CR_MASTER_MASK; /* Enable master module. */
I2Cx->IMR = 0u; /* Close all interrupts. */
I2Cx->RXTLR = 0u; /* Configure the sending receive value. */
I2Cx->TXTLR = 0u; /* Configure the sending threshold value. */
return true; /* Initialize I2C succeeded, return true. */
}
/* Enable I2C. */
void I2C_Enable(I2C_Type * I2Cx, bool enable)
{
if (enable)
{
I2Cx->ENR |= I2C_ENR_ENABLE_MASK;
}
else
{
I2Cx->ENR &= ~I2C_ENR_ENABLE_MASK;
}
}
/* Configuration the target device address. */
void I2C_SetTargetAddr(I2C_Type * I2Cx, uint8_t addr)
{
I2Cx->TAR = I2C_TAR_ADDR(addr);
}
/* Get I2C target device address. */
uint16_t I2C_GetTargetAddr(I2C_Type * I2Cx)
{
return (I2Cx->TAR & I2C_TAR_ADDR_MASK);
}
/* Put data to target device. */
void I2C_PutData(I2C_Type * I2Cx, uint8_t val)
{
I2Cx->DR = I2C_DR_DAT(val);
}
/* Control read-write bit to prepare to read data. */
void I2C_PrepareToGetData(I2C_Type * I2Cx)
{
I2Cx->DR = I2C_DR_CMD_MASK;
}
/* Get the data received by target device. */
uint8_t I2C_GetData(I2C_Type * I2Cx)
{
return ( (uint8_t)I2Cx->DR );
}
/* Get the current status flags of the I2C module. */
uint32_t I2C_GetStatus(I2C_Type * I2Cx)
{
return I2Cx->SR;
}
/* Prepare for the stop, when transfer finish. */
void I2C_Stop(I2C_Type * I2Cx)
{
I2Cx->ENR |= I2C_ENR_ABORT_MASK; /* Prepare for the stop. */
I2Cx->TXABRT; /* Read register to release tx fifo. */
}
/* Enable I2C interrupt. */
void I2C_EnableInterrupts(I2C_Type * I2Cx, uint32_t interrupts, bool enable)
{
if (enable)
{
I2Cx->IMR |= interrupts;
}
else
{
I2Cx->IMR &= ~interrupts;
}
}
/* Get the current enabled interrupts the I2C module. */
uint32_t I2C_GetEnabledInterrupts(I2C_Type * I2Cx)
{
return I2Cx->IMR;
}
/* Get the I2C interrupt status flags of the I2C module. */
uint32_t I2C_GetInterruptStatus(I2C_Type * I2Cx)
{
return (I2Cx->RAWISR & I2Cx->IMR); /* To ensure that the acquired interrupt is an enabled interrupt. */
}
/* Clear I2C interrupt status. */
void I2C_ClearInterruptStatus(I2C_Type * I2Cx, uint32_t interrupts)
{
if ( (I2C_INT_RX_UNDER & interrupts) != 0u ) /* Clear receive buffer under status. */
{
I2Cx->RXUNDER;
}
if ( (I2C_INT_TX_ABORT & interrupts) != 0u ) /* Clear I2C transmit abort status. */
{
I2Cx->TXABRT;
}
if ( (I2C_INT_ACTIVE & interrupts) != 0u ) /* Clear I2C interface activation status. */
{
I2Cx->ACTIV;
}
if ( (I2C_INT_STOP & interrupts) != 0u ) /* Clear I2C stop condition detection status. */
{
I2Cx->STOP;
}
if ( (I2C_INT_START & interrupts) != 0u ) /* Clear I2C start condition detection status. */
{
I2Cx->START;
}
}
/* Performs polling tx. */
bool I2C_MasterWriteBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer)
{
/* Put register address. */
I2C_PutData(I2Cx, xfer->TxBuf[0u]);
uint32_t waittime1 = xfer->WaitTimes;
/* Wait to tx fifo empty. */
while ( (0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime1) )
{
waittime1--;
}
if (0u == waittime1) /* I2C write register address timeout. */
{
return false;
}
uint32_t waittime2 = xfer->WaitTimes;
/* Write data to target device. */
for (uint32_t i = 1u; i < xfer->TxLen; i++)
{
I2C_PutData(I2Cx, xfer->TxBuf[i]);
while ( ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime2) ) /* Wait to tx fifo empty. */
{
waittime2--;
}
if (0u == waittime2) /* I2C write timeout. */
{
return false;
}
}
I2C_Stop(I2Cx); /* Prepare to stop send data. */
uint32_t waittime3 = xfer->WaitTimes;
/* Wait to I2C not active, which means stop is taking effect. */
while ( (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) && (0u != waittime3) )
{
waittime3--;
}
if (0u == waittime3) /* The wait operation is timeout. */
{
return false;
}
/* Clear fifo and flags. */
I2C1->ICR;
I2C1->TXABRT;
return true;
}
/* Performs polling rx. */
bool I2C_MasterReadBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer)
{
I2C_PutData(I2Cx, xfer->TxBuf[0u]); /* Put device register address. */
uint32_t waittime1 = xfer->WaitTimes;
while ( ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime1) ) /* Wait to tx fifo empty. */
{
waittime1--;
}
if (0u == waittime1)
{
return false;
}
/* read data from target device. */
for (uint32_t i = 0u; i < xfer->RxLen; i++)
{
I2C_PrepareToGetData(I2Cx); /* Swich read-write bit, prepare to get data. */
while ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_RX_NOTEMPTY) ) /* Wait to rx fifo not empty. */
{
if ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) ) /* Receive is active. */
{
return false;
}
}
xfer->RxBuf[i] = I2C_GetData(I2Cx);
}
I2C_Stop(I2Cx); /* Prepare to stop I2C. */
uint32_t waittime2 = xfer->WaitTimes;
while ( (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) && (0u != waittime2) ) /* Wait I2C not active, which means stop being effective. */
{
waittime2--;
}
if (0u == waittime2)
{
return false;
}
/* Clear fifo and flags. */
I2C1->ICR;
I2C1->TXABRT;
return true;
}
/* I2C master interrupt transfer of the I2C module. */
void I2C_MasterXfer(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer)
{
I2C_PutData(I2Cx, (uint8_t)xfer->TxBuf[0u]); /* Put target register address. */
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT | I2C_INT_STOP, true); /* Enable tx required interrupt. */
xfer->TxIdx = 1u; /* One data has been sent. */
xfer->RxIdx = 0u;
xfer->TxLen--;
}
/* I2C Master handler. */
void I2C_MasterXferHandler(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer, uint32_t interrupts)
{
if ( 0u != (interrupts & I2C_INT_TX_ABORT) ) /* Early termination of program. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT | I2C_INT_STOP, false); /* Clear the interrupt used for tx. */
if (NULL != xfer->AbortCallback)
{
xfer->AbortCallback(xfer); /* Use abort call back. */
}
}
else if ( 0u != (interrupts & I2C_INT_TX_EMPTY) ) /* Tx fifo is empty, can send data. */
{
if (I2C_Direction_Rx == xfer->Direction) /* The current operation is receive, the register address has been sent. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT, false); /* Clear tx interrupt. */
I2C_EnableInterrupts(I2Cx, I2C_INT_RX_NOTEMPTY, true); /* Enable receive required interrupt. */
if (0u != xfer->RxLen) /* The data to be received is not 0. */
{
I2C_PrepareToGetData(I2Cx); /* Prepare to get data. */
xfer->RxLen--;
}
else
{
I2C_Stop(I2Cx); /* No more transmition, prepare to stop. */
}
}
else
{
if (0u == xfer->TxLen) /* Tx finish. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT, false); /* Clear Tx interrupt. */
I2C_Stop(I2Cx); /* Prepare to stop. */
}
else
{
xfer->TxLen--;
I2C_PutData(I2Cx, xfer->TxBuf[xfer->TxIdx++]); /* Tx is not over, continue to put data. */
}
}
}
else if ( 0u != (interrupts & I2C_INT_RX_NOTEMPTY) ) /* Receive interrupt. */
{
if (0u == xfer->RxLen) /* Receive finish. */
{
xfer->RxBuf[xfer->RxIdx++] = I2C_GetData(I2Cx); /* Get last data from I2C bus. */
I2C_EnableInterrupts(I2Cx, I2C_INT_RX_NOTEMPTY, false); /* Clear receive interrupt. */
I2C_Stop(I2Cx); /* Prepare to stop. */
}
else
{
xfer->RxLen--; /* Current count length count -1. */
xfer->RxBuf[xfer->RxIdx++] = I2C_GetData(I2Cx); /* Receive is not over, continue to get data. */
I2C_PrepareToGetData(I2Cx); /* Prepare to get data. */
}
}
else if ( 0u != (interrupts & I2C_INT_STOP) ) /* Xfer stop. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_STOP, false); /* Clear stop interrupt. */
if ( (0u != xfer->TxLen) || (0u != xfer->RxLen) ) /* The transmission was not completed but terminated. */
{
if (NULL != xfer->AbortCallback)
{
xfer->AbortCallback(xfer); /* Early termination of program, abort callback. */
I2C1->ICR;
I2C1->TXABRT; /* Clear FIFO. */
}
}
else
{
if (NULL != xfer->DoneCallback)
{
xfer->DoneCallback(xfer); /* Transmission finish and stop, xfer done callback. */
I2C1->ICR;
I2C1->TXABRT; /* Clear FIFO. */
}
}
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_I2C_H__
#define __HAL_I2C_H__
#include "hal_common.h"
/*!
* @addtogroup I2C
* @{
*/
/*!
* @addtogroup I2C_INT
* @{
*/
#define I2C_INT_RX_UNDER I2C_RAWISR_RXUNDER_MASK /*!< Assert when attempting to read the RX fifo, even it is empty. */
#define I2C_INT_RX_NOTEMPTY I2C_RAWISR_RXFULL_MASK /*!< Assert when the data in RX fifo is available. */
#define I2C_INT_TX_EMPTY I2C_RAWISR_TXEMPTY_MASK /*!< When working as master, this bit asserts if the data count is under or equal to the tx threshold. */
#define I2C_INT_TX_ABORT I2C_RAWISR_TXABRT_MASK /*!< Assert when transmit abort. */
#define I2C_INT_ACTIVE I2C_RAWISR_ACTIV_MASK /*!< Assert when the i2c bus is active, while the clocks are transfered. */
#define I2C_INT_STOP I2C_RAWISR_STOP_MASK /*!< Assert when detecting a STOP on the i2c bus, no mater working as master or slave. */
#define I2C_INT_START I2C_RAWISR_START_MASK /*!< Assert when detecting a START on the i2c bus, no matter working as master or slave. */
/*!
* @}
*/
/*!
* @addtogroup I2C_STATUS
* @{
*/
#define I2C_STATUS_ACTIVE I2C_SR_ACTIV_MASK /*!< I2C bus is active. */
#define I2C_STATUS_TX_EMPTY I2C_SR_TFE_MASK /*!< I2C tx fifo is empty. */
#define I2C_STATUS_RX_NOTEMPTY I2C_SR_RFNE_MASK /*!< I2C rx fifo is not empty. */
/*!
* @}
*/
/*!
* @brief I2C baudrate type.
*/
typedef enum
{
I2C_BaudRate_50K = 50000u, /*!< Specify operate at the speed of 50K. */
I2C_BaudRate_100K = 100000u, /*!< Specify operate at the speed of 100K. */
} I2C_BaudRate_Type;
/*!
* @brief I2C transmission direction type.
*/
typedef enum
{
I2C_Direction_Tx = 0u, /*!< Specify I2C transmission direction as tx. */
I2C_Direction_Rx = 1u, /*!< Specify I2C transmission direction as rx. */
} I2C_Direction_Type;
/*!
* @brief Define the callback function called when the I2C master transfer is abort.
*/
typedef void (*I2C_Callback_1_Type)(void *param);
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref I2C_MasterXfer() to transfer the I2C address and data.
*/
typedef struct
{
uint16_t TargetAddr; /*!< Specify I2C target device address. */
I2C_Direction_Type Direction; /*!< specify transmission direction. */
uint8_t *TxBuf; /*!< Specify the tx buffer array. */
uint32_t TxIdx; /*!< Specify the number of data currently sent. */
uint8_t TxLen; /*!< Specify the tx data len. */
uint8_t *RxBuf; /*!< Specify the rx buffer array. */
uint32_t RxIdx; /*!< Specify the number of data currently receive. */
uint8_t RxLen; /*!< Specify the rx data len. */
uint32_t WaitTimes; /*!< Specify the time limit for wait to the flag to be generated. If the required flag is not generated after this time, considered as timeout. */
I2C_Callback_1_Type DoneCallback; /*!< Callback function, called when the i2c transmit is done. */
I2C_Callback_1_Type AbortCallback; /*!< Callback function, called when the i2c transmit is abort. */
} I2C_MasterXfer_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref I2C_InitMaster() to initialize the I2C master module.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Specify bus clock frequency. */
I2C_BaudRate_Type BaudRate; /*!< Specify the I2C communication baud rate. */
} I2C_Master_Init_Type;
/*!
* @brief Initialize the I2C master module.
*
* @param I2Cx I2C instance.
* @param init Pointer to the master initialization structure. See to @ref I2C_Master_Init_Type.
* @return The initialize succeed return true, the misconfiguration of speed or baud rate return false.
*/
bool I2C_InitMaster(I2C_Type * I2Cx, I2C_Master_Init_Type * init);
/*!
* @brief Enabel the I2C module.
*
* @param I2Cx I2C instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void I2C_Enable(I2C_Type *I2Cx, bool enable);
/*!
* @brief Set the I2C target device address that matches the slave device.
*
* @param I2Cx I2C instance.
* @param addr I2C target device address.
* @return None.
*/
void I2C_SetTargetAddr(I2C_Type * I2Cx, uint8_t addr);
/*!
* @brief Get I2C target device address.
*
* @param I2Cx I2C instance.
* @return I2C target device addr.
*/
uint16_t I2C_GetTargetAddr(I2C_Type * I2Cx);
/*!
* @brief Put the data into transmiter buffer of the I2C module.
*
* @param I2Cx I2C instance.
* @param val Data value to be send through the transmiter.
* @return None.
*/
void I2C_PutData(I2C_Type * I2Cx, uint8_t val);
/*!
* @brief Control read-write bit to prepare for data acquisition.
*
* @param I2Cx I2C instance.
* @return None.
*/
void I2C_PrepareToGetData(I2C_Type * I2Cx);
/*!
* @brief Get the data from receiver buffer of the I2C module.
*
* @param I2Cx I2C instance.
* @return Data received by I2C bus.
*/
uint8_t I2C_GetData(I2C_Type * I2Cx);
/*!
* @brief Get the current status flags of the I2C module.
*
* @param I2Cx I2C instance.
* @return Status flags. See to @ref I2C_STATUS.
*/
uint32_t I2C_GetStatus(I2C_Type * I2Cx);
/*!
* @brief Prepare for the stop, when transfer finish.
*
* @param I2Cx I2C instance.
* @return None.
*/
void I2C_Stop(I2C_Type * I2Cx);
/*!
* @brief Enable interrupts of I2C module.
*
* @param I2Cx I2C instance.
* @param interrupts Interrupt code masks. See to @ref I2C_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void I2C_EnableInterrupts(I2C_Type * I2Cx, uint32_t interrupts, bool enable);
/*!
* @brief Read the current enabled interrupts the I2C module.
*
* @param I2Cx I2C instance.
* @return The mask codes enabled interrupts. See to @ref I2C_INT.
*/
uint32_t I2C_GetEnabledInterrupts(I2C_Type * I2Cx);
/*!
* @brief Get the I2C interrupt status flags of the I2C module.
*
* @param I2Cx I2C instance.
* @return Interrupt status flags. See to @ref I2C_INT.
*/
uint32_t I2C_GetInterruptStatus(I2C_Type * I2Cx);
/*!
* @brief Clear the I2C interrupt status flags of the I2C module.
*
* @param I2Cx I2C instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return None.
*/
void I2C_ClearInterruptStatus(I2C_Type * I2Cx, uint32_t interrupts);
/*!
* @brief I2C master interrupt transfer of the I2C module.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @return None.
*/
void I2C_MasterXfer(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer);
/*!
* @brief I2C master transfer interrupt handler.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @param interrupts Interrupt status flags. See to @ref I2C_INT.
* @return None.
*/
void I2C_MasterXferHandler(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer, uint32_t interrupts);
/*!
* @brief I2C master write polling.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @return 'true' to I2C write polling succeed, 'false' to I2C write polling failed.
*/
bool I2C_MasterWriteBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer);
/*!
* @brief I2C master read polling.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @return 'true' to I2C read polling succeed, 'false' to I2C read polling failed.
*/
bool I2C_MasterReadBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer);
/*!
*@}
*/
#endif /* __HAL_I2C_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_i2s.h"
/* init i2s in master mode. */
void I2S_InitMaster(I2S_Type * I2Sx, I2S_Master_Init_Type * init)
{
if (NULL == init ||
0u == init->SampleRate)
{
return;
}
/* get I2Sx->GCTL value & clear the field to be configured. */
uint32_t gctl = I2Sx->GCTL & ~(SPI_I2S_GCTL_RXEN_MASK
| SPI_I2S_GCTL_TXEN_MASK
| SPI_I2S_GCTL_MODE_MASK
| SPI_I2S_GCTL_INTEN_MASK);
/* get I2Sx->CCTL value & clear the field to be configured. */
uint32_t cctl = I2Sx->CCTL & ~(SPI_I2S_CCTL_RXEDGE_MASK
| SPI_I2S_CCTL_CPOL_MASK);
/* get I2Sx->I2SCFGR value & clear the field to be configured. */
uint32_t cfgr = I2Sx->I2SCFGR & ~(SPI_I2S_I2SCFGR_I2SDIV_MASK
| SPI_I2S_I2SCFGR_HFDSEL_MASK
| SPI_I2S_I2SCFGR_MCKOE_MASK
| SPI_I2S_I2SCFGR_SPII2S_MASK
| SPI_I2S_I2SCFGR_I2SSTD_MASK
| SPI_I2S_I2SCFGR_DATLEN_MASK
| SPI_I2S_I2SCFGR_CHLEN_MASK);
/* set the xfer mode. */
switch (init->XferMode)
{
case I2S_XferMode_TxOnly:
gctl |= SPI_I2S_GCTL_TXEN_MASK;
gctl &= ~SPI_I2S_GCTL_RXEN_MASK;
cfgr |= SPI_I2S_I2SCFGR_HFDSEL_MASK;
break;
case I2S_XferMode_RxOnly:
gctl |= SPI_I2S_GCTL_RXEN_MASK;
gctl &= ~SPI_I2S_GCTL_TXEN_MASK;
cfgr |= SPI_I2S_I2SCFGR_HFDSEL_MASK;
break;
case I2S_XferMode_TxRx:
gctl |= SPI_I2S_GCTL_TXEN_MASK | SPI_I2S_GCTL_RXEN_MASK;
cfgr &= ~SPI_I2S_I2SCFGR_HFDSEL_MASK;
break;
default:
break;
}
/* master mode. */
gctl |= SPI_I2S_GCTL_MODE_MASK /* master mode, disable i2s, and reset the other bits in CCTL. */
| SPI_I2S_GCTL_INTEN_MASK; /* always enable the global interrupt. the specific events are controlled by each bits in INTEN register. */
/* set CPOL. */
cctl |= SPI_I2S_CCTL_RXEDGE_MASK
| SPI_I2S_CCTL_CPOL(init->Polarity);
uint32_t div = 0u;
/* calc the i2s_div value. */
if (!(init->EnableMCLK) )
{
if (I2S_DataWidth_16b == init->DataWidth)
{
div = (init->ClockFreqHz) / (32u * (init->SampleRate) );
}
else
{
div = (init->ClockFreqHz) / (64u * (init->SampleRate) );
cfgr |= SPI_I2S_I2SCFGR_CHLEN_MASK;
}
}
else
{
div = (init->ClockFreqHz) / (256u * (init->SampleRate) );
if (I2S_DataWidth_16b != init->DataWidth)
{
cfgr |= SPI_I2S_I2SCFGR_CHLEN_MASK;
}
}
cfgr |= SPI_I2S_I2SCFGR_I2SDIV(div)
| SPI_I2S_I2SCFGR_MCKOE(1u)
| SPI_I2S_I2SCFGR_SPII2S_MASK
| SPI_I2S_I2SCFGR_I2SSTD(init->Protocol)
| SPI_I2S_I2SCFGR_DATLEN(init->DataWidth);
I2Sx->GCTL = gctl; /* set I2Sx->GCTL. */
I2Sx->CCTL = cctl; /* set I2Sx->CCTL. */
I2Sx->I2SCFGR = cfgr; /* set I2Sx->I2SCFGR. */
}
/* enable i2s. */
void I2S_Enable(I2S_Type * I2Sx, bool enable)
{
if (enable)
{
I2Sx->GCTL |= SPI_I2S_GCTL_SPIEN_MASK;
}
else
{
I2Sx->GCTL &= ~SPI_I2S_GCTL_SPIEN_MASK;
}
}
/* get i2s status. */
uint32_t I2S_GetStatus(I2S_Type * I2Sx)
{
return I2Sx->CSTAT;
}
/* enable interrupt. */
void I2S_EnableInterrupts(I2S_Type * I2Sx, uint32_t interrupts, bool enable)
{
if (enable)
{
I2Sx->INTEN |= interrupts;
}
else
{
I2Sx->INTEN &= ~interrupts;
}
}
/* get interrupt status. */
uint32_t I2S_GetInterruptStatus(I2S_Type * I2Sx)
{
return I2Sx->INTSTAT;
}
/* clear interrupt status. */
void I2S_ClearInterruptStatus(I2S_Type * I2Sx, uint32_t interrupts)
{
I2Sx->INTCLR = interrupts;
}
/* put data to tx buffer. */
void I2S_PutData(I2S_Type * I2Sx, uint32_t data)
{
I2Sx->TXREG = data;
}
/* get data in rx buffer. */
uint32_t I2S_GetData(I2S_Type * I2Sx)
{
return I2Sx->RXREG;
}
I2S_Channel_Type I2S_GetXferChannel(I2S_Type * I2Sx)
{
if (0u != (I2Sx->CSTAT & SPI_I2S_CSTAT_CHSIDE_MASK) )
{
return I2S_Channel_Right;
}
else
{
return I2S_Channel_Left;
}
}
/* enable dma. */
void I2S_EnableDMA(I2S_Type * I2Sx, bool enable)
{
if (enable)
{
I2Sx->GCTL |= SPI_I2S_GCTL_DMAMODE_MASK;
}
else
{
I2Sx->GCTL &= ~SPI_I2S_GCTL_DMAMODE_MASK;
}
}
/* get rx buffer reg addr. */
uint32_t I2S_GetRxDataRegAddr(I2S_Type * I2Sx)
{
return (uint32_t)(&(I2Sx->RXREG) );
}
/* get tx buffer reg addr. */
uint32_t I2S_GetTxDataRegAddr(I2S_Type * I2Sx)
{
return (uint32_t)(&(I2Sx->TXREG) );
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_I2S_H__
#define __HAL_I2S_H__
#include "hal_common.h"
/*!
* @addtogroup I2S
* @{
*/
/*!
* @brief I2S driver version number.
*/
#define I2S_DRIVER_VERSION 0u /*!< i2s_0. */
/*!
* @addtogroup I2S_STATUS
* @{
*/
#define I2S_STATUS_BUSY SPI_I2S_CSTAT_BUSY_MASK /*!< Status flag when I2S is transmitting or receiving. */
#define I2S_STATUS_TX_FULL SPI_I2S_CSTAT_TXFULL_MASK /*!< Status flag when I2S transmiter buffer is full. */
#define I2S_STATUS_TX_DONE SPI_I2S_CSTAT_TXEPT_MASK /*!< Status flag when I2S transmiter buffer & transmiter are empty. */
#define I2S_STATUS_RX_DONE SPI_I2S_CSTAT_RXAVL_MASK /*!< Status flag when I2S receiving buffer is with available data. */
/*!
* @}
*/
/*!
* @addtogroup I2S_INT
* @{
*/
#define I2S_INT_TX_EMPTY SPI_I2S_INTEN_TXIEN_MASK /*!< Interrupt flag when I2S transmiter buffer is empty. */
#define I2S_INT_TX_DONE SPI_I2S_INTSTAT_TXEPTINTF_MASK /*!< Interrupt flag when I2S transmiter buffer & transmiter are empty. */
#define I2S_INT_RX_DONE SPI_I2S_INTEN_RXIEN_MASK /*!< Interrupt flag when I2S receiving buffer is with available data. */
#define I2S_INT_XFER_ERROR SPI_I2S_INTEN_FREIEN_MASK /*!< Interrupt flag when I2S xfer data error. */
/*!
* @}
*/
/*!
* @brief I2S polarity type.
*/
typedef enum
{
I2S_Polarity_0 = 0u, /*!< CPOL = 0, Clock line is low when idle. */
I2S_Polarity_1 = 1u, /*!< CPOL = 1, Clock line is high when idle. */
} I2S_Polarity_Type;
/*!
* @brief I2S data width type.
*/
typedef enum
{
I2S_DataWidth_16b = 0u, /*!< Data width is 16 bit. */
I2S_DataWidth_24b = 1u, /*!< Data width is 24 bit. */
I2S_DataWidth_32b = 2u, /*!< Data width is 32 bit. */
} I2S_DataWidth_Type;
/*!
* @brief I2S protocol type.
*/
typedef enum
{
I2S_Protocol_PHILIPS = 0u, /*!< Philips xfer protocol. */
I2S_Protocol_MSB = 1u, /*!< MSB xfer protocol. */
I2S_Protocol_LSB = 2u, /*!< LSB xfer protocol. */
I2S_Protocol_PCM = 3u, /*!< PCM xfer protocol. */
} I2S_Protocol_Type;
/*!
* @brief I2S xfer mode type.
*/
typedef enum
{
I2S_XferMode_TxOnly = 0u, /*!< Enable Tx only. */
I2S_XferMode_RxOnly = 1u, /*!< Enable Rx only. */
I2S_XferMode_TxRx = 2u, /*!< Enable both Tx and Rx. */
} I2S_XferMode_Type;
/*!
* @brief I2S xfer channel type.
*/
typedef enum
{
I2S_Channel_Left = 0u, /*!< Left Xfer channel. */
I2S_Channel_Right = 1u, /*!< Right Xfer channel. */
} I2S_Channel_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref I2S_InitMaster() to initialize the I2S module.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Bus Clock Freq. */
uint32_t SampleRate; /*!< This member configures the I2S sample rate. */
I2S_DataWidth_Type DataWidth; /*!< Specifies the number of bits of data to be transmitted. */
I2S_Polarity_Type Polarity; /*!< Specifies the polarity of clock. */
I2S_Protocol_Type Protocol; /*!< Specifies different communication protocols. */
I2S_XferMode_Type XferMode; /*!< Specifies different communication transmit modes. */
bool EnableMCLK; /*!< Specifies whether enable MCLK. */
} I2S_Master_Init_Type;
/*!
* @brief Initialize the I2S Master module.
*
* @param I2Sx I2S instance.
* @param init Pointer to the initialization structure. See to @ref I2S_Master_Init_Type.
* @return None.
*/
void I2S_InitMaster(I2S_Type * I2Sx, I2S_Master_Init_Type * init);
/*!
* @brief Enable the I2S module.
*
* The I2S module should be enabled before sending or receiving data.
*
* @param I2Sx I2S instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void I2S_Enable(I2S_Type * I2Sx, bool enable);
/*!
* @brief Get the current status flags of the I2S module.
*
* @param I2Sx I2S instance.
* @return Status flags. See to @ref I2S_STATUS.
*/
uint32_t I2S_GetStatus(I2S_Type * I2Sx);
/*!
* @brief Enable interrupts of the I2S module.
*
* @param I2Sx I2S instance.
* @param interrupts Interrupt code masks. See to @ref I2S_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void I2S_EnableInterrupts(I2S_Type * I2Sx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the I2S module.
*
* @param I2Sx I2S instance.
* @return Interrupt status flags. See to @ref I2S_INT.
*/
uint32_t I2S_GetInterruptStatus(I2S_Type * I2Sx);
/*!
* @brief Clear the interrupt status flags of the I2S module.
*
* @param I2Sx I2S instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return None.
*/
void I2S_ClearInterruptStatus(I2S_Type * I2Sx, uint32_t interrupts);
/*!
* @brief Put the data into transmiter buffer of the I2S module.
*
* @param I2Sx I2S instance.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void I2S_PutData(I2S_Type * I2Sx, uint32_t dat);
/*!
* @brief Get the data from receiver buffer of the I2S module.
*
* @param I2Sx I2S instance.
* @return The data value received from the receiver.
* @return data Data value to be received from the transmiter.
*/
uint32_t I2S_GetData(I2S_Type * I2Sx);
/*!
* @brief Enable the DMA trigger from the I2S module.
*
* The DMA trigger events are the same as the interrupts.
*
* @param I2Sx I2S instance.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void I2S_EnableDMA(I2S_Type * I2Sx, bool enable);
/*!
* @brief Get the hardware Rx data buffer's address the I2S module.
*
* The return value of the address is most used with DMA module.
*
* @param I2Sx I2S instance.
* @return The value of the address for I2S module's hardware Rx data buffer.
*/
uint32_t I2S_GetRxDataRegAddr(I2S_Type * I2Sx);
/*!
* @brief Get the hardware Tx data buffer's address the I2S module.
*
* The return value of the address is most used with DMA module.
*
* @param I2Sx I2S instance.
* @return The value of the address for I2S module's hardware Tx data buffer.
*/
uint32_t I2S_GetTxDataRegAddr(I2S_Type * I2Sx);
/*!
* @brief Get the transmitting channel of the I2S module.
*
* @param I2Sx I2S instance.
* @return The current transmitting channel.
*/
I2S_Channel_Type I2S_GetXferChannel(I2S_Type * I2Sx);
/*!
*@}
*/
#endif /* __HAL_I2S_H__ */
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_iwdg.h"
void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init)
{
if ( NULL != init )
{
IWDGx->KR = IWDG_KEY_UNLOCK;
IWDGx->PR = init->Prescaler;
IWDGx->KR = IWDG_KEY_UNLOCK;
IWDGx->RLR = init->Relaod;
IWDG_DoReload(IWDGx);
}
}
void IWDG_Start(IWDG_Type * IWDGx)
{
IWDGx->KR = IWDG_KEY_ENABLE;
}
uint32_t IWDG_GetStatus(IWDG_Type * IWDGx)
{
return IWDGx->SR;
}
void IWDG_DoReload(IWDG_Type * IWDGx)
{
IWDGx->KR = IWDG_KEY_RELOAD;
}
void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable)
{
if( (true == enable ) && (IWDG_INT_ALMOST_TIMEOUT == interrupts) )
{
IWDGx->CR |= IWDG_CR_IRQSEL_MASK;
}
else
{
/* if IWDG_EnableInterrupts interrupt was enabled, only MCU reset can close it. */
}
}
void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status)
{
if( 0u != ( status & IWDG_CR_IRQCLR_MASK ) )
{
IWDGx->CR |= IWDG_CR_IRQCLR_MASK;
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_IWDG_H__
#define __HAL_IWDG_H__
#include "hal_common.h"
/*!
* @addtogroup IWDG
* @{
*/
/*!
* @brief IWDG driver version number.
*/
#define IWDG_DRIVER_VERSION 0u /*!< IWDG_0. */
/*!
* @brief IWDG key values
*/
#define IWDG_KEY_ENABLE 0xCCCC /*!< IWDG Peripheral Enable . */
#define IWDG_KEY_RELOAD 0xAAAA /*!< IWDG Reload Counter Enable. */
#define IWDG_KEY_UNLOCK 0x5555 /*!< IWDG KR Write Access Enable*/
/*!
* @addtogroup IWDG_STATUS
* @{
*/
#define IWDG_STATUS_RELOAD_UPDATE IWDG_SR_RVU_MASK /*!< Status flag when IWDG counter reload value update, can not be cleared. */
#define IWDG_STATUS_PRESCALER_UPDATE IWDG_SR_PVU_MASK /*!< Status flag when IWDG prescaler value update, can not be cleared. */
#define IWDG_STATUS_ALMOST_TIMEOUT IWDG_SR_IVU_MASK /*!< Status flag when IWDG almost timeout. */
/*!
* @}
*/
/*!
* @addtogroup IWDG_INT
* @{
*/
#define IWDG_INT_ALMOST_TIMEOUT IWDG_CR_IRQSEL_MASK /*!< IWDG Interrupt: Select IWDG interrupt method */
/*!
* @}
*/
/*!
* @brief IWDG prescaler type.
*
* Select the prescaler of time base as the IWDG counter clock.
*/
typedef enum
{
IWDG_Prescaler_4 = 0u, /*!< IWDG prescaler 4. */
IWDG_Prescaler_8 = 1u, /*!< IWDG prescaler 8. */
IWDG_Prescaler_16 = 2u, /*!< IWDG prescaler 16. */
IWDG_Prescaler_32 = 3u, /*!< IWDG prescaler 32. */
IWDG_Prescaler_64 = 4u, /*!< IWDG prescaler 64. */
IWDG_Prescaler_128 = 5u, /*!< IWDG prescaler 128. */
IWDG_Prescaler_256 = 6u, /*!< IWDG prescaler 256. */
} IWDG_Prescaler_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref IWDG_Init() to initialize the IWDG module.
*/
typedef struct
{
IWDG_Prescaler_Type Prescaler; /*!< Specify the IWDG counter time base division value. */
uint32_t Relaod; /*!< Specify the IWDG counter reload value. */
} IWDG_Init_Type;
/*!
* @brief Initialize the IWDG module.
*
* @param IWDGx IWDG instance.
* @param init Pointer to the initialization structure. See to @ref IWDG_Init_Type.
* @return None.
*/
void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init);
/*!
* @brief Start the IWDG counter.
*
* Once IWDG counter is started, it cannot be stopped unless reset MCU.
*
* @param IWDGx IWDG instance.
* @return None.
*/
void IWDG_Start(IWDG_Type * IWDGx);
/*!
* @brief Get the current status flags of the IWDG module.
*
* @param IWDGx IWDG instance.
* @return Status flags. See to @ref IWDG_STATUS.
*/
uint32_t IWDG_GetStatus(IWDG_Type * IWDGx);
/*!
* @brief Clear the status flags of the IWDG module.
*
* @param IWDGx IWDG instance.
* @param status Status flags. See to @ref IWDG_STATUS.
* @return None.
*/
void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status);
/*!
* @brief Do reload IWDG counter (i.e. "feed dog").
*
* @param IWDGx IWDG instance.
* @return None.
*/
void IWDG_DoReload(IWDG_Type * IWDGx);
/*!
* @brief Enable interrupts of the IWDG module.
*
* @param IWDGx IWDG instance.
* @param interrupts Interrupt code masks. See to @ref IWDG_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' has no effect.
* @return None.
*/
void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable);
/*!
*@}
*/
#endif /* __HAL_IWDG_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_lptim.h"
void LPTIM_Init(LPTIM_Type * LPTIMx, LPTIM_Init_Type * init)
{
LPTIMx->CFG = (LPTIMx->CFG & ~( LPTIM_CFG_TMODE_MASK | LPTIM_CFG_DIVSEL_MASK | LPTIM_CFG_MODE_MASK) )
| LPTIM_CFG_TMODE(init->WorkMode) /* Setup the work mode. */
| LPTIM_CFG_DIVSEL(init->Prescaler) /* Setup the prescaler. */
| LPTIM_CFG_MODE(init->PeriodMode); /* Setup the period mode. */
/* Setup the period value. */
LPTIMx->TARGET = LPTIM_TARGET_TARGETREG(init->Period);
}
void LPTIM_Start(LPTIM_Type * LPTIMx)
{
LPTIMx->CTRL |= LPTIM_CTRL_LPTEN_MASK; /* Start the counter. */
}
void LPTIM_Stop(LPTIM_Type * LPTIMx)
{
LPTIMx->CTRL &= ~LPTIM_CTRL_LPTEN_MASK; /* Stop the counter. */
}
void LPTIM_EnableInterrupts(LPTIM_Type * LPTIMx, uint32_t interrupts, bool enable)
{
if (enable)
{
LPTIMx->IE |= interrupts;
}
else
{
LPTIMx->IE &= ~interrupts;
}
}
uint32_t LPTIM_GetInterruptStatus(LPTIM_Type * LPTIMx)
{
return LPTIMx->IF; /* return flags */
}
void LPTIM_ClearInterruptStatus(LPTIM_Type * LPTIMx, uint32_t status)
{
LPTIMx->IF = status;
}
void LPTIM_EnableTriggerIn(LPTIM_Type * LPTIMx, LPTIM_TriggerInConf_Type * conf)
{
LPTIMx->CFG = (LPTIMx->CFG & ~(LPTIM_CFG_TRIGSEL_MASK | LPTIM_CFG_FLTEN_MASK | LPTIM_CFG_TRIGCFG_MASK) )
| LPTIM_CFG_TRIGSEL(conf->Channel) /* Setup trigger input channel. */
| LPTIM_CFG_FLTEN(conf->EnableFilter) /* Setup the external trigger input filter. */
| LPTIM_CFG_TRIGCFG(conf->TriggerInPolarity); /* Setup the trigger input polarity. */
}
void LPTIM_EnableOutWave(LPTIM_Type * LPTIMx, LPTIM_OutWaveConf_Type * conf)
{
LPTIMx->CFG = (LPTIMx->CFG & ~ (LPTIM_CFG_PWM_MASK | LPTIM_CFG_POLARITY_MASK) )
| LPTIM_CFG_PWM(conf->Wave) /* Setup the output waveform. */
| LPTIM_CFG_POLARITY(conf->OutPolarity); /* Setup the output waveform polarity. */
}
void LPTIM_SetCompareValue(LPTIM_Type * LPTIMx, uint32_t value)
{
LPTIMx->CMP = LPTIM_CMP_COMPAREREG(value);
}
uint32_t LPTIM_GetCounterValue(LPTIM_Type * LPTIMx)
{
return LPTIMx->CNT; /* return current counter value. */
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_LPTIM_H__
#define __HAL_LPTIM_H__
#include "hal_common.h"
/*!
* @addtogroup LPTIM
* @{
*/
/*!
* @brief LPTIM driver version number.
*/
#define LPTIM_DRIVER_VERSION 0u /*!< LPTIM_0. */
/*!
* @addtogroup LPTIM_STATUS
* @{
*/
#define LPTIM_STATUS_COUNTER_OVERFLOW (1u << 0u) /*!< Status flag when LPTIM counter overflow. */
#define LPTIM_STATUS_TRIGGER_INPUT (1u << 2u) /*!< Status flag when LPTIM trigger input. */
#define LPTIM_STATUS_COMPARE_MATCH (1u << 1u) /*!< Status flag when LPTIM compare match. */
/*!
* @}
*/
/*!
* @addtogroup LPTIM_INT
* @{
*/
#define LPTIM_INT_COUNTER_OVERFLOW (1u << 0u) /*!< Interrupt enable when LPTIM counter overflow. */
#define LPTIM_INT_TRIGGER_INPUT (1u << 1u) /*!< Interrupt enable when LPTIM trigger input. */
#define LPTIM_INT_COMPARE_MATCH (1u << 2u) /*!< Interrupt enable when LPTIM compare match. */
/*!
* @}
*/
/*!
* @brief LPTIM counter period working mode.
*/
typedef enum
{
LPTIM_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */
LPTIM_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */
} LPTIM_PeriodMode_Type;
/*!
* @brief LPTIM work mode type.
*/
typedef enum
{
LPTIM_WorkMode_Timer = 0u, /*!< Normal timer mode with output waveform feature. */
LPTIM_WorkMode_Trigger = 1u, /*!< Pulse trigger counting mode. */
LPTIM_WorkMode_WakeUpLowPower =3, /*!< Counter time out wake up MCU from low power mode. */
} LPTIM_WorkMode_Type;
/*!
* @brief LPTIM trigger input channel type.
*/
typedef enum
{
LPTIM_TriggerInChannel_Pin = 0u, /*!< Select trigger pin as trigger input channel. */
LPTIM_TriggerInChannel_Comp = 1u, /*!< Select Comparator output as trigger input channel. */
} LPTIM_TriggerInChannel_Type;
/*!
* @brief LPTIM trigger input polarity type.
*/
typedef enum
{
LPTIM_TriggerInPolarity_Rising = 0u, /*!< Select rising edge as external trigger signal. */
LPTIM_TriggerInPolarity_Falling = 1u, /*!< Select falling edge as external trigger signal. */
LPTIM_TriggerInPolarity_RisingOrFalling = 2u, /*!< Select both the rising and falling edge as external trigger signal. */
}LPTIM_TriggerInPolarity_Type;
/*!
* @brief LPTIM output waveform type.
*/
typedef enum
{
LPTIM_OutWave_Square = 0u, /*!< Select Square wave to output. */
LPTIM_OutWave_PWM = 1u, /*!< Select PWM wave to output. */
} LPTIM_OutWave_Type;
/*!
* @brief LPTIM output polarity type.
*/
typedef enum
{
LPTIM_OutPolarity_Rising = 0u, /*!< Output rising edge when the count value is equal to the compare value. */
LPTIM_OutPolarity_Falling = 1u, /*!< Output falling edge when the count value is equal to the compare value. */
} LPTIM_OutPolarity_Type;
/*!
* @brief LPTIM prescaler type.
*
* Select the prescaler of time base as the LPTIM counter clock.
*/
typedef enum
{
LPTIM_Prescaler_1 = 0u, /*!< LPTIM prescaler 1. */
LPTIM_Prescaler_2 = 1u, /*!< LPTIM prescaler 2. */
LPTIM_Prescaler_4 = 2u, /*!< LPTIM prescaler 4. */
LPTIM_Prescaler_8 = 3u, /*!< LPTIM prescaler 8. */
LPTIM_Prescaler_16 = 4u, /*!< LPTIM prescaler 16. */
LPTIM_Prescaler_32 = 5u, /*!< LPTIM prescaler 32. */
LPTIM_Prescaler_64 = 6u, /*!< LPTIM prescaler 64. */
LPTIM_Prescaler_128 = 7u, /*!< LPTIM prescaler 128. */
} LPTIM_Prescaler_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref LPTIM_Init() to initialize the LPTIM module.
*/
typedef struct
{
uint32_t Period; /*!< Counter counting length, from 0 to period value, the value range: 0 ~ 65535.*/
LPTIM_PeriodMode_Type PeriodMode; /*!< Specify the counter period mode. */
LPTIM_WorkMode_Type WorkMode; /*!< Specify the LPTIM worke mode. */
LPTIM_Prescaler_Type Prescaler; /*!< Specify the LPTIM counter time base division value. */
} LPTIM_Init_Type;
/*!
* @brief Setup the external trigger input configuration when calling the @ref LPTIM_EnableTriggerIn().
*/
typedef struct
{
LPTIM_TriggerInChannel_Type Channel; /*!< Specify the trigger input channel. */
bool EnableFilter; /*!< 'true' to enable the external tirgger pin filter, 'false' to disable the filer. */
LPTIM_TriggerInPolarity_Type TriggerInPolarity; /*!< Specify the trigger input polarity. */
} LPTIM_TriggerInConf_Type;
/*!
* @brief Setup the output waveform configuration when calling the @ref LPTIM_OutWaveConf_Type().
*/
typedef struct
{
LPTIM_OutWave_Type Wave; /*!< Specify output waveform. */
LPTIM_OutPolarity_Type OutPolarity; /*!< Specify the waveform output pin polarity. */
} LPTIM_OutWaveConf_Type;
/*!
* @brief Initialize the LPTIM module.
*
* @param LPTIMx LPTIM instance.
* @param init Pointer to the initialization structure. See to @ref LPTIM_Init_Type.
* @return None.
*/
void LPTIM_Init(LPTIM_Type * LPTIMx, LPTIM_Init_Type * init);
/*!
* @brief Start counting.
*
* @param LPTIMx LPTIM instance.
* @return None.
*/
void LPTIM_Start(LPTIM_Type * LPTIMx);
/*!
* @brief Stop counting immediately.
*
* @param LPTIMx LPTIM instance.
* @return None.
*/
void LPTIM_Stop(LPTIM_Type * LPTIMx);
/*!
* @brief Enable interrupts of the LPTIM module.
*
* @param LPTIMx LPTIM_Type instance.
* @param interrupts Interrupt code masks. See to @ref LPTIM_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void LPTIM_EnableInterrupts(LPTIM_Type * LPTIMx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the LPTIM module.
*
* @param LPTIMx LPTIM_Type instance.
* @return Interrupt status flags. See to @ref LPTIM_STATUS.
*/
uint32_t LPTIM_GetInterruptStatus(LPTIM_Type * LPTIMx);
/*!
* @brief Clear the interrupts status flags of the LPTIM module.
*
* @param LPTIMx LPTIM_Type instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return None.
*/
void LPTIM_ClearInterruptStatus(LPTIM_Type * LPTIMx, uint32_t interrupts);
/*!
* @brief Enable the external trigger input of the indicated counter.
*
* External trigger signal will trigger counter do addition.
*
* @param LPTIMx LPTIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref LPTIM_TriggerInConf_Type.
* @return None.
*/
void LPTIM_EnableTriggerIn(LPTIM_Type * LPTIMx, LPTIM_TriggerInConf_Type * conf);
/*!
* @brief Enable output waveform.
*
* The output waveform could be PWM wave or suqare wave.
*
* @param LPTIMx LPTIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref LPTIM_OutWaveConf_Type.
* @return None.
*/
void LPTIM_EnableOutWave(LPTIM_Type * LPTIMx, LPTIM_OutWaveConf_Type * conf);
/*!
* @brief Set the compare value.
*
* The compare value would be compared with counter value.
*
* @param LPTIMx LPTIM_Type instance.
* @param value The compare value to be set, the value range: 0 ~ 65535.
* @return none.
*/
void LPTIM_SetCompareValue(LPTIM_Type * LPTIMx, uint32_t value);
/*!
* @brief Get the current counter value.
*
* @param LPTIMx LPTIM_Type instance.
* @return The current counter value.
*/
uint32_t LPTIM_GetCounterValue(LPTIM_Type * LPTIMx);
/*!
*@}
*/
#endif /* __HAL_TIM_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_lpuart.h"
void LPUART_SetBaudrate2(LPUART_Type * LPUARTx, uint32_t freq, uint32_t baudrate)
{
LPUARTx->LPUBAUD |= LPUART_LPUBAUD_BREN_MASK;
uint32_t base_cycles = freq / baudrate;
uint32_t current_cycles = 0;
uint32_t ideal_K;
uint32_t K;
K = 0xFFFFFFFF / freq / 4 * 2;
LPUARTx->LPUBAUD |= LPUART_LPUBAUD_BR(base_cycles);
LPUARTx->MODU = 0;
for (uint8_t bit_idx = 0; bit_idx < 12; bit_idx++)
{
ideal_K = (uint32_t)( (base_cycles * K + 0.5) * (bit_idx + 1) );
current_cycles += base_cycles;
if (current_cycles * K >= ideal_K)
{
continue;
}
else if ( (ideal_K - current_cycles * K) >= (K / 2) )
{
LPUARTx->MODU |= 1 << bit_idx;
current_cycles += 1;
}
}
}
/* LPUART initialization use LSE(32.768KHz) clock source. */
void LPUART_Init(LPUART_Type * LPUARTx, LPUART_Init_Type * init)
{
uint32_t lpuart_mctl[6] = {0x952, 0xefb, 0x6db, 0x482,0x6d6, 0x842};
if (init->ClockSource == LPUART_ClockSource_LSE)
{
LPUARTx->LPUBAUD &= ~LPUART_LPUBAUD_BREN_MASK; /* BREN = 0, only 32.768KHz clock is supported as clock source. */
LPUARTx->LPUBAUD = LPUART_LPUBAUD_BAUD(init->BaudRate);
LPUARTx->MODU = lpuart_mctl[init->BaudRate];
}
/* WordLength. */
LPUARTx->LPUCON |= LPUART_LPUCON_DL(init->WordLength);
/* StopBits. */
LPUARTx->LPUCON |= LPUART_LPUCON_SL(init->StopBits);
/* Parity. */
if (init->Parity == LPUART_Parity_Even)
{
LPUARTx->LPUCON |= LPUART_LPUCON_PAREN_MASK;
LPUARTx->LPUCON &= ~LPUART_LPUCON_PTYP_MASK;
}
if (init->Parity == LPUART_Parity_Odd)
{
LPUARTx->LPUCON |= (LPUART_LPUCON_PAREN_MASK | LPUART_LPUCON_PTYP_MASK);
}
}
/* LPUART enable tx. */
void LPUART_EnableTx(LPUART_Type * LPUARTx, bool enable)
{
if (enable)
{
LPUARTx->LPUEN |= LPUART_LPUEN_TXEN_MASK;
}
else
{
LPUARTx->LPUEN &= ~LPUART_LPUEN_TXEN_MASK;
}
}
/* LPUART enable rx. */
void LPUART_EnableRx(LPUART_Type * LPUARTx, bool enable)
{
if (enable)
{
LPUARTx->LPUEN |= LPUART_LPUEN_RXEN_MASK;
}
else
{
LPUARTx->LPUEN &= ~LPUART_LPUEN_RXEN_MASK;
}
}
/* LPUART get status. */
uint32_t LPUART_GetStatus(LPUART_Type * LPUARTx)
{
return LPUARTx->LPUSTA;
}
/* LPUART put data. */
void LPUART_PutData(LPUART_Type * LPUARTx, uint8_t value)
{
LPUARTx->LPUTXD = value;
}
/* LPAURT put data. */
uint8_t LPUART_GetData(LPUART_Type * LPUARTx)
{
return (uint8_t)(LPUARTx->LPURXD & 0xff);
}
/* LPUART enable interrupt. */
void LPUART_EnableInterrupts(LPUART_Type * LPUARTx, uint32_t interrupts, bool enable)
{
switch (interrupts)
{
case LPUART_INT_RX_FULL:
if (enable)
{
LPUARTx->LPUCON |= LPUART_LPUCON_RXIE_MASK;
}
else
{
LPUARTx->LPUCON &= ~LPUART_LPUCON_TCIE_MASK;
}
break;
case LPUART_INT_TX_EMPTY:
if (enable)
{
LPUARTx->LPUCON |= LPUART_LPUCON_TXIE_MASK;
}
else
{
LPUARTx->LPUCON &= ~LPUART_LPUCON_TXIE_MASK;
}
break;
case LPUART_INT_TX_DONE:
if (enable)
{
LPUARTx->LPUCON |= LPUART_LPUCON_TCIE_MASK;
}
else
{
LPUARTx->LPUCON &= ~LPUART_LPUCON_TCIE_MASK;
}
break;
default:
break;
}
}
/* Get LPUART interrupt status. */
uint32_t LPUART_GetInterruptStatus(LPUART_Type * LPUARTx)
{
return LPUARTx->LPUIF;
}
/* Get LPUART interrupt enable status. */
uint32_t LPUART_GetEnabledInterrupts(LPUART_Type * LPUARTx)
{
uint32_t flags = 0u;
if ( 0u != (LPUART_LPUCON_RXIE_MASK & LPUARTx->LPUCON) )
{
flags |= LPUART_INT_RX_FULL;
}
if ( 0u != (LPUART_LPUCON_TXIE_MASK & LPUARTx->LPUCON) )
{
flags |= LPUART_INT_TX_EMPTY;
}
if ( 0u != (LPUART_LPUCON_TCIE_MASK & LPUARTx->LPUCON) )
{
flags |= LPUART_INT_TX_DONE;
}
return flags;
}
/* Clear LPUART interrupt status. */
void LPUART_ClearInterruptStatus(LPUART_Type * LPUARTx, uint32_t interrupts)
{
LPUARTx->LPUIF |= interrupts;
}
/* LPUART enable DMA. */
void LPUART_EnableDMA(LPUART_Type * LPUARTx, uint32_t dma, bool enable)
{
if (enable)
{
LPUARTx->LPUEN |= dma;
}
else
{
LPUARTx->LPUEN &= ~dma;
}
}
/* LPUART get tx data register address. */
uint32_t LPUART_GetTxDataRegAddr(LPUART_Type * LPUARTx)
{
return (uint32_t)(&(LPUARTx->LPUTXD));
}
/* LPUART get rx data register address. */
uint32_t LPUART_GetRxDataRegAddr(LPUART_Type * LPUARTx)
{
return (uint32_t)(&(LPUARTx->LPURXD));
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_LPUART_H__
#define __HAL_LPUART_H__
#include "hal_common.h"
/*!
* @addtogroup LPUART
* @{
*/
/*!
* @addtogroup LPUART_STATUS
* @{
*/
#define LPUART_STATUS_RX_FULL LPUART_LPUSTA_RXF_MASK /*!< Status flag when LPUART receiving buffer is full. */
#define LPUART_STATUS_TX_EMPTY LPUART_LPUSTA_TXE_MASK /*!< Status flag when LPUART transmiter buffer is empty. */
#define LPUART_STATUS_TX_DONE LPUART_LPUSTA_TC_MASK /*!< Status flag when LPUART transmiter shifter is empty after the transfer is done. */
/*!
* @}
*/
/*!
* @addtogroup LPUART_INT
* @{
*/
#define LPUART_INT_RX_FULL (1u << 0u) /*!< Interrupt enable when LPUART receiving buffer is full. */
#define LPUART_INT_TX_EMPTY (1u << 1u) /*!< Interrupt enable when LPUART transmiter buffer is empty. */
#define LPUART_INT_TX_DONE (1u << 3u) /*!< Interrupt enable when LPUART transmiter is done. */
/*!
* @}
*/
/*!
* @addtogroup LPUART_DMA
* @{
*/
#define LPUART_DMA_TX LPUART_LPUEN_DMAT_MASK /*!< Enable LPUART DMA tx only. */
#define LPUART_DMA_RX LPUART_LPUEN_DMAR_MASK /*!< Enable LPUART DMA rx only. */
#define LPUART_DMA_TXRX (LPUART_LPUEN_DMAT_MASK | LPUART_LPUEN_DMAR_MASK) /*!< Enable LPUART DMA tx and rx. */
/*!
* @}
*/
/*!
* @brief LPUART clock source select.
*/
typedef enum
{
LPUART_ClockSource_LSE = 0u, /*!< Clock soucre is LSE. */
} LPUART_ClockSource_Type;
/*!
* @brief LPUART use LSE as clock source's baudrate type.
*/
typedef enum
{
LPUART_Baudrate_9600 = 0x000, /*!< Baudrate is 9600 when clock source is LSE. */
LPUART_Baudrate_4800 = 0x001, /*!< Baudrate is 4800 when clock source is LSE. */
LPUART_Baudrate_2400 = 0x010, /*!< Baudrate is 2400 when clock source is LSE. */
LPUART_Baudrate_1200 = 0x011, /*!< Baudrate is 1200 when clock source is LSE. */
LPUART_Baudrate_600 = 0x100, /*!< Baudrate is 600 when clock source is LSE. */
LPUART_Baudrate_300 = 0x101, /*!< Baudrate is 300 when clock source is LSE. */
} LPUART_Baudrate_Type;
/*!
* @brief LPUART word length type.
*/
typedef enum
{
LPUART_WordLength_8 = 0u, /*!< Word length 8 bits. */
LPUART_WordLength_7 = 1u, /*!< Word length 7 bits. */
} LPUART_WordLength_Type;
/*!
* @brief LPUART stop bits type.
*/
typedef enum
{
LPUART_StopBits_1 = 0u, /* stop bit is 1 bit */
LPUART_StopBits_2 = 1u, /* stop bit is 2 bit */
} LPUART_StopBits_Type;
/*!
* @brief LPUART parity type.
*/
typedef enum
{
LPUART_Parity_None = 0u, /*!< No parity. */
LPUART_Parity_Even = 1u, /*!< Even parity. */
LPUART_Parity_Odd = 2u, /*!< Odd parity. */
} LPUART_Parity_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref LPUART_Init() to initialize the LPUART module.
*/
typedef struct
{
LPUART_ClockSource_Type ClockSource; /*!< LPUART clock source. */
LPUART_Baudrate_Type BaudRate; /*!< Specify the LPUART LSE specific baud rate. */
LPUART_WordLength_Type WordLength; /*!< Specify the number of data bits transmitted or received in a frame. */
LPUART_StopBits_Type StopBits; /*!< Specify the number of stop bits transmitted. */
LPUART_Parity_Type Parity; /*!< Specify the parity mode. */
} LPUART_Init_Type;
/*!
* @brief Initialize the LPUART module.
*
* @param LPUARTx LPUART instance.
* @param init Pointer to the initialization structure. See to @ref LPUART_Init_Type.
* @return None.
*/
void LPUART_Init(LPUART_Type * LPUARTx, LPUART_Init_Type * init);
/*!
* @brief Enable the LPUART tx module.
*
* The LPUART Tx module should be enabled before sending data.
*
* @param LPUARTx LPUART instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void LPUART_EnableTx(LPUART_Type * LPUARTx, bool enable);
/*!
* @brief Enable the LPUART rx module.
*
* The LPUART module should be enabled before receiving data.
*
* @param LPUARTx LPUART instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void LPUART_EnableRx(LPUART_Type * LPUARTx, bool enable);
/*!
* @brief Get the current status flags of the LPUART module.
*
* @param LPUARTx LPUART instance.
* @return Status flags. See to @ref LPUART_STATUS.
*/
uint32_t LPUART_GetStatus(LPUART_Type * LPUARTx);
/*!
* @brief Put the data into transmiter buffer of the LPUART module.
*
* @param LPUARTx LPUART instance.
* @param value Data value to be send through the transmiter.
* @return None.
*/
void LPUART_PutData(LPUART_Type * LPUARTx, uint8_t value);
/*!
* @brief Get the data from receiver buffer of the LPUART module.
*
* @param LPUARTx LPUART instance.
* @return The data value received from the receiver.
*/
uint8_t LPUART_GetData(LPUART_Type * LPUARTx);
/*!
* @brief Enable interrupts of the LPUART module.
*
* @param LPUARTx LPUART instance.
* @param interrupts Interrupt code masks. See to @ref LPUART_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void LPUART_EnableInterrupts(LPUART_Type * LPUARTx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the LPUART module.
*
* @param LPUARTx LPUART instance.
* @return Interrupt status flags. See to @ref LPUART_INT.
*/
uint32_t LPUART_GetInterruptStatus(LPUART_Type * LPUARTx);
/*!
* @brief Read the current enabled interrupts the LPUART module.
*
* @param LPUARTx LPUART instance.
* @return The mask codes enabled interrupts. See to @ref LPUART_INT
*/
uint32_t LPUART_GetEnabledInterrupts(LPUART_Type * LPUARTx);
/*!
* @brief Clear the interrupts status flags of the LPUART module.
*
* @param LPUARTx LPUART instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return Interrupt status flags. See to @ref LPUART_INT.
*/
void LPUART_ClearInterruptStatus(LPUART_Type * LPUARTx, uint32_t interrupts);
/*!
* @brief Enable the DMA trigger from the LPUART module.
*
* The DMA trigger events are the same as the interrupts.
*
* @param LPUARTx LPUART instance.
* @param dma DMA xfer direction.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void LPUART_EnableDMA(LPUART_Type * LPUARTx, uint32_t dma, bool enable);
/*!
* @brief Get the hardware Tx data buffer's address the LPUART module.
*
* The return value of the address is most used with DMA module.
*
* @param LPUARTx LPUART instance.
* @return The value of the address for LPUART module's hardware Tx data buffer.
*/
uint32_t LPUART_GetTxDataRegAddr(LPUART_Type * LPUARTx);
/*!
* @brief Get the hardware Rx data buffer's address the LPUART module.
*
* The return value of the address is most used with DMA module.
*
* @param LPUARTx LPUART instance.
* @return The value of the address for LPUART module's hardware Rx data buffer.
*/
uint32_t LPUART_GetRxDataRegAddr(LPUART_Type * LPUARTx);
/*!
*@}
*/
#endif /* __HAL_UART_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_mds.h"
/* Configure the trigger mode, not using clu out as the trigger in. */
void MDS_EnableTrigger(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_TriggerInMode_Type trigger_mode)
{
MDSx->TRIGXCR[out] =( MDSx->TRIGXCR[out] & ~(MDS_TRIGXCR_CLUEN_MASK | MDS_TRIGXCR_TRGSEL_MASK | MDS_TRIGXCR_EDGESEL_MASK) )
| MDS_TRIGXCR_TRGSEL(trigger_mode)
| MDS_TRIGXCR_TRGSEL(in)
;
}
/* enable the software trigger as the trigger source. */
void MDS_DoSwTrigger(MDS_Type * MDSx)
{
MDSx->SWTRIG = MDS_SWTRIG_SWTRIG_MASK;
}
/* Configure the connection mode, not using clu out as the connection in. */
void MDS_EnableConn(MDS_Type * MDSx, uint32_t out, uint32_t in)
{
MDSx->CONNXCR[out] =( MDSx->CONNXCR[out] & ~(MDS_CONNXCR_CLUEN_MASK | MDS_CONNXCR_TRGSEL_MASK ) )
| MDS_CONNXCR_TRGSEL(in)
;
}
/* Configure the trigger mode, using clu out as the trigger in. */
void MDS_EnableTriggerClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf)
{
if (!conf)
{
return;
}
MDSx->TRIGXCR[out] =( MDSx->TRIGXCR[out] & ~(MDS_TRIGXCR_CLUEN_MASK | MDS_TRIGXCR_TRGSEL_MASK | MDS_TRIGXCR_EDGESEL_MASK) )
| MDS_TRIGXCR_CLUSEL(in)
;
/* configure the trigger in for one clu in. */
for (uint32_t i = 0; i<MDS_CLU_IN_LEN; i++)
{
MDSx->TRIGCLUXSEL[in] |= conf->CluInSource[i] << (i * 8u);
}
/* configure the each trigger detection edge mode. */
MDSx->TRIGCLUXCFG[in] = conf->CluInSourceTriggerEdgeMask;
/* configure the each trigger in inverter and the clu operation logic. */
MDSx->CONNCLUXCFG[in] = conf->CluInSourceInvertMask | conf->CluLogic;
/* enable the clu mode. */
MDSx->TRIGXCR[out] |= MDS_TRIGXCR_CLUEN_MASK;
}
/* Configure the clu out as the trigger source mode . */
void MDS_EnableConnClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf)
{
if (!conf)
{
return;
}
MDSx->CONNXCR[out] = ( MDSx->CONNXCR[out] & ~ (MDS_CONNXCR_CLUEN_MASK | MDS_CONNXCR_CLUSEL_MASK))
| MDS_CONNXCR_CLUSEL(in)
;
/* configure the connection in for one clu in. */
for (uint32_t i = 0; i<MDS_CLU_IN_LEN; i++)
{
MDSx->CONNCLUXSEL[in] |= conf->CluInSource[i] << (i * 8u);
}
/* configure the each trigger in inverter and the clu operation logic. */
MDSx->CONNCLUXCFG[in] = conf->CluInSourceInvertMask | conf->CluLogic;
/* enable the clu mode. */
MDSx->CONNXCR[out] |= MDS_CONNXCR_CLUEN_MASK;
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_MDS_H__
#define __HAL_MDS_H__
#include "hal_common.h"
#include "hal_mds_remap.h"
/*!
* @addtogroup MDS
* @{
*/
/*!
* @brief MDS driver version number.
*/
#define MDS_DRIVER_VERSION 0u /*!< mds_0. */
/*!
* @brief MDS TriggerInMode type.
*
* Use the Trigger in mode, selecting the edge detection mode for the trigger source.
*/
typedef enum
{
MDS_TriggerInMode_RisingEdge = 0u, /*!< Select Rising edge detection. */
MDS_TriggerInMode_FallingEdge = 1u, /*!< Select Falling edge detection. */
MDS_TriggerInMode_BothEdges = 2u, /*!< Select Rising and Falling edge detection. */
}MDS_TriggerInMode_Type;
/*!
* @brief MDS CluLogic type.
*
* Select the operation logic of the Clu.
*/
typedef enum
{
MDS_CluLogic_OR_OR = 0u, /*!< The operation logic selects the OR-OR logic, and the four input logics are in0|in1|in2|in3. */
MDS_CluLogic_AND_OR = 1u, /*!< The operation logic selects the AND-OR logic, and the four input logics are (in0&in1)|(in2&in3). */
MDS_CluLogic_OR_XOR = 2u, /*!< The operation logic selects the OR-XOR logic, and the four input logics are (in0|in1)^(in2|in3). */
MDS_CluLogic_AND_AND = 3u, /*!< The operation logic selects the OR-OR logic, and the four input logics are in0&in1&in2&in3. */
}MDS_CluLogic_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref MDS_EnableTriggerClu() or @ref MDS_EnableConnClu() to configure using the Clu out as the trigger source.
*/
typedef struct
{
uint32_t CluInSource[MDS_CLU_IN_LEN]; /*!< Select the trigger and connection source for each of Clu in, TRIGGER_IN_SOURCE_LEN is the max input length. */
uint32_t CluInSourceInvertMask; /*!< Select trigger or connect the source after taking the inverse as input to the clu. */
uint32_t CluInSourceTriggerEdgeMask; /*!< Select the clu in source trigger edge detection mode. */
MDS_CluLogic_Type CluLogic; /*!< Select the Clu operation logic. */
} MDS_CluConf_Type;
/*!
* @brief Enable the trigger mode without clu output as connection source in.
* the hal_mds_remap.h define the mds(mindswitch) in or out, the trigger in correspond to trigger out.
*
* @param MDSx MDS instance.
* @param out the trigger source, see to hal_mds_remap.h.
* @param in the trigger target, see to hal_mds_remap.h.
* @param trigger_mode select the trigger in edge detection mode.
* @return None.
*/
void MDS_EnableTrigger(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_TriggerInMode_Type trigger_mode);
/*!
* @brief Enable software trigger as the trigger source in.
* when using the software trigger as the trigger source, enable it and it can only finish once trigger.
*
* @param MDSx MDS instance.
* @param enable true is enable the software trigger as the trigger source, false is not enable.
* @return None.
*/
void MDS_DoSwTrigger(MDS_Type * MDSx);
/*!
* @brief Enable the connection mode without clu output as connection source in.
* the hal_mds_remap.h define the mds(mindswitch) in or out, the connection in correspond to conntion out.
*
* @param MDSx MDS instance.
* @param out the connection target, see to hal_mds_remap.h.
* @param in the input of connection, see to hal_mds_remap.h.
* @return None.
*/
void MDS_EnableConn(MDS_Type * MDSx, uint32_t out, uint32_t in);
/*!
* @brief Enable the clu output as the trigger source in.
* the hal_mds_remap.h define the mds(mindswitch) in or out, the connection in correspond to conntion out.
*
* @param MDSx MDS instance.
* @param conf configure the clu parameter, @ref MDS_CluConf_Type.
* @param out select the trigger out, see to hal_mds_remap.h.
* @param in select which clu in, see to hal_mds_remap.h.
* @return None.
*/
void MDS_EnableTriggerClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf);
/*!
* @brief Enable the clu output as the connection source in.
* the hal_mds_remap.h define the mds(mindswitch) in or out, the connection in correspond to conntion out.
*
* @param MDSx MDS instance.
* @param conf configure the clu parameter, @ref MDS_CluConf_Type.
* @param out select the connection out, see to hal_mds_remap.h.
* @param in select which clu in, see to hal_mds_remap.h.
* @return None.
*/
void MDS_EnableConnClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf);
/*!
*@}
*/
#endif /*__HAL_MDS_H__. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* define the mds(mindswitch) in and out, the trigger in only from trigger out. the connection in only for connection out. */
#ifndef __HAL_MDS_REMAP_H__
#define __HAL_MDS_REMAP_H__
#define MDS_CLU_IN_LEN 4u /* one clu input max length. */
#define CONN_TRIGGER_IN_MASK 19u /* define the connection trigger source mask. */
/* Trigger In. */
#define MDS_TRIGGER_IN_LOGIC_0 0u
#define MDS_TRIGGER_IN_LOGIC_1 1u
#define MDS_TRIGGER_IN_SW 2u
#define MDS_TRIGGER_IN_TIM1_CC1 3u
#define MDS_TRIGGER_IN_TIM1_CC2 4u
#define MDS_TRIGGER_IN_TIM1_CC3 5u
#define MDS_TRIGGER_IN_TIM1_CC4 6u
#define MDS_TRIGGER_IN_TIM1_CC5 7u
#define MDS_TRIGGER_IN_TIM2_CC1 8u
#define MDS_TRIGGER_IN_TIM2_CC2 9u
#define MDS_TRIGGER_IN_TIM2_CC3 10u
#define MDS_TRIGGER_IN_TIM2_CC4 11u
#define MDS_TRIGGER_IN_TIM3_CC1 12u
#define MDS_TRIGGER_IN_TIM3_CC2 13u
#define MDS_TRIGGER_IN_TIM3_CC3 14u
#define MDS_TRIGGER_IN_TIM3_CC4 15u
#define MDS_TRIGGER_IN_TIM4_CC1 16u
#define MDS_TRIGGER_IN_TIM4_CC2 17u
#define MDS_TRIGGER_IN_TIM4_CC3 18u
#define MDS_TRIGGER_IN_TIM4_CC4 19u
#define MDS_TRIGGER_IN_TIM5_CC1 20u
#define MDS_TRIGGER_IN_TIM5_CC2 21u
#define MDS_TRIGGER_IN_TIM5_CC3 22u
#define MDS_TRIGGER_IN_TIM5_CC4 23u
#define MDS_TRIGGER_IN_TIM8_CC1 24u
#define MDS_TRIGGER_IN_TIM8_CC2 25u
#define MDS_TRIGGER_IN_TIM8_CC3 26u
#define MDS_TRIGGER_IN_TIM8_CC4 27u
#define MDS_TRIGGER_IN_TIM8_CC5 28u
#define MDS_TRIGGER_IN_TIM1_OUT 29u
#define MDS_TRIGGER_IN_TIM2_OUT 30u
#define MDS_TRIGGER_IN_TIM3_OUT 31u
#define MDS_TRIGGER_IN_TIM4_OUT 32u
#define MDS_TRIGGER_IN_TIM5_OUT 33u
#define MDS_TRIGGER_IN_TIM8_OUT 36u
#define MDS_TRIGGER_IN_EXTI0 37u
#define MDS_TRIGGER_IN_EXTI1 38u
#define MDS_TRIGGER_IN_EXTI2 39u
#define MDS_TRIGGER_IN_EXTI3 40u
#define MDS_TRIGGER_IN_EXTI4 41u
#define MDS_TRIGGER_IN_EXTI5 42u
#define MDS_TRIGGER_IN_EXTI6 43u
#define MDS_TRIGGER_IN_EXTI7 44u
#define MDS_TRIGGER_IN_EXTI8 45u
#define MDS_TRIGGER_IN_EXTI9 46u
#define MDS_TRIGGER_IN_EXTI10 47u
#define MDS_TRIGGER_IN_EXTI11 48u
#define MDS_TRIGGER_IN_EXTI12 49u
#define MDS_TRIGGER_IN_EXTI13 50u
#define MDS_TRIGGER_IN_EXTI14 51u
#define MDS_TRIGGER_IN_EXTI15 52u
#define MDS_TRIGGER_IN_CLU0 (0u << 17u)
#define MDS_TRIGGER_IN_CLU1 (1u << 17u)
#define MDS_TRIGGER_IN_CLU2 (2u << 17u)
#define MDS_TRIGGER_IN_CLU3 (3u << 17u)
/* Trigger Out. */
#define MDS_TRIGGER_OUT_ADC1_EXT_TRIGGER 0u
#define MDS_TRIGGER_OUT_ADC1_INJECT_EXT_TRIGGER 1u
#define MDS_TRIGGER_OUT_ADC2_EXT_TRIGGER 2u
#define MDS_TRIGGER_OUT_ADC2_INJECT_EXT_TRIGGER 3u
#define MDS_TRIGGER_OUT_DAC1_EXT_TRIGGER 6u
#define MDS_TRIGGER_OUT_DAC2_EXT_TRIGGER 7u
/* Connection In. */
#define MDS_CONN_IN_LOGIC_0 0u
#define MDS_CONN_IN_LOGIC_1 1u
#define MDS_CONN_IN_TIM1_CH1_OUT 2u
#define MDS_CONN_IN_TIM1_CH1N_OUT 3u
#define MDS_CONN_IN_TIM1_CH2_OUT 4u
#define MDS_CONN_IN_TIM1_CH2N_OUT 5u
#define MDS_CONN_IN_TIM1_CH3_OUT 6u
#define MDS_CONN_IN_TIM1_CH3N_OUT 7u
#define MDS_CONN_IN_TIM1_CH4_OUT 8u
#define MDS_CONN_IN_TIM1_CH4N_OUT 9u
#define MDS_CONN_IN_TIM2_CH1_OUT 10u
#define MDS_CONN_IN_TIM2_CH2_OUT 11u
#define MDS_CONN_IN_TIM2_CH3_OUT 12u
#define MDS_CONN_IN_TIM2_CH4_OUT 13u
#define MDS_CONN_IN_TIM3_CH4_OUT 14u
#define MDS_CONN_IN_TIM4_CH4_OUT 15u
#define MDS_CONN_IN_TIM5_CH4_OUT 16u
#define MDS_CONN_IN_TIM8_CH4_OUT 17u
#define MDS_CONN_IN_MDS_IN0 18u
#define MDS_CONN_IN_MDS_IN1 19u
#define MDS_CONN_IN_MDS_IN2 20u
#define MDS_CONN_IN_MDS_IN3 21u
#define MDS_CONN_IN_CLU0 (0u << 17u)
#define MDS_CONN_IN_CLU1 (1u << 17u)
#define MDS_CONN_IN_CLU2 (2u << 17u)
#define MDS_CONN_IN_CLU3 (3u << 17u)
/*Connection Out. */
#define MDS_CONN_OUT_COMP1_BLANK 0u
#define MDS_CONN_OUT_COMP2_BLANK 1u
#define MDS_CONN_OUT_COMP3_BLANK 2u
#define MDS_CONN_OUT_MDS_OUT0 3u
#define MDS_CONN_OUT_MDS_OUT1 4u
#define MDS_CONN_OUT_MDS_OUT2 5u
#define MDS_CONN_OUT_MDS_OUT3 6u
#endif /*__HAL_MDS_REMAP_H__. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_power.h"
void CORE_EnterSleepMode(bool sleep_on_exit, bool sleep_deep, POWER_WakeUp_Type mode)
{
if (sleep_on_exit)
{
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
}
else
{
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
}
if (sleep_deep)
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
}
else
{
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
}
if (mode == POWER_WakeUp_Interrupt)
{
__WFI();
}
if (mode == POWER_WakeUp_Event)
{
__WFE();
}
}
void POWER_EnterRunMode(void)
{
PWR_EnableLowPowerRunMode(PWR, false);
}
void POWER_EnableLowPowerRunMode(void)
{
PWR_EnableLowPowerRunMode(PWR, true);
}
void POWER_EnterSleepMode(POWER_SleepConf_Type * conf)
{
CORE_EnterSleepMode(conf->SleepOnExit, false, conf->WakeUpMode);
}
void POWER_EnterStopMode(POWER_StopConf_Type * conf)
{
PWR_EnterStopMode(PWR, conf->DeepStop);
CORE_EnterSleepMode(false, true, conf->WakeUpMode);
}
void POWER_EnableStandbyWakeUpPin(PWR_StandbyWakeUpPinConf_Type * conf)
{
PWR_EnableStandbyWakeUpPin(PWR, conf);
}
void POWER_EnterStandbyMode(POWER_StandbyConf_Type * conf)
{
PWR_EnterStandbyMode(PWR, conf->Delay);
CORE_EnterSleepMode(false, true, conf->WakeUpMode);
}
void POWER_SelectMode(POWER_Mode_Type mode, void * conf)
{
switch (mode)
{
case POWER_Mode_Run:
POWER_EnterRunMode();
break;
case POWER_Mode_LowPowerRun:
POWER_EnableLowPowerRunMode();
break;
case POWER_Mode_Sleep:
POWER_EnterSleepMode( (POWER_SleepConf_Type *) conf);
break;
case POWER_Mode_LowPowerSleep:
POWER_EnableLowPowerRunMode();
POWER_EnterSleepMode( (POWER_SleepConf_Type *) conf);
break;
case POWER_Mode_Stop:
POWER_EnterStopMode( (POWER_StopConf_Type *) conf);
break;
case POWER_Mode_DeepStop:
POWER_EnterStopMode( (POWER_StopConf_Type *) conf);
break;
case POWER_Mode_Standby:
POWER_EnterStandbyMode( (POWER_StandbyConf_Type *) conf);
break;
default:
break;
}
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_POWER_H__
#define __HAL_POWER_H__
#include "hal_common.h"
#include "hal_pwr.h"
/*!
* @brief POWER mode type.
*/
typedef enum
{
POWER_Mode_Run = 0u, /*!< Run mode selected. */
POWER_Mode_LowPowerRun = 1u, /*!< Low power run mode selected. */
POWER_Mode_Sleep = 2u, /*!< Sleep mode selected. */
POWER_Mode_LowPowerSleep = 3u, /*!< Low power sleep mode selected. */
POWER_Mode_Stop = 4u, /*!< Stop mode selected. */
POWER_Mode_DeepStop = 5u, /*!< Deep stop mode selected. */
POWER_Mode_Standby = 6u, /*!< Standby mode selected. */
} POWER_Mode_Type;
/*!
* @brief POWER wake up type.
*/
typedef enum
{
POWER_WakeUp_Interrupt = 0u, /*!< Select the interrupt wake up. */
POWER_WakeUp_Event = 1u, /*!< Select the event wake up. */
} POWER_WakeUp_Type;
/*!
* @brief POWER sleep mode parameter type.
*/
typedef struct
{
bool SleepOnExit; /*!< 'true' to sleep after exit from ISR, 'false' to sleep immediately. */
POWER_WakeUp_Type WakeUpMode; /*!< Specify wake up mode. See to @ref POWER_WakeUp_Type. */
} POWER_SleepConf_Type;
/*!
* @brief POWER stop mode parameter type.
*/
typedef struct
{
bool DeepStop; /*!< 'true' to enable the deep stop mode, 'false' to disable the deep stop mode. */
POWER_WakeUp_Type WakeUpMode; /*!< Specify wake up mode. See to @ref POWER_WakeUp_Type. */
} POWER_StopConf_Type;
/*!
* @brief POWER standby mode parameter type.
*/
typedef struct
{
PWR_StandbyWakeUpDelay_Type Delay; /*!< Specify standby mode wake up delay value. See to @ref PWR_StandbyWakeUpDelay_Type. */
POWER_WakeUp_Type WakeUpMode; /*!< Specify wake up mode. See to @ref POWER_WakeUp_Type. */
} POWER_StandbyConf_Type;
/*!
* @brief Select power mode.
*
* @param mode power mode. See to @ref POWER_Mode_Type.
* @param param Pointer to the initialization structure.
* @return None.
*/
void POWER_SelectMode(POWER_Mode_Type mode, void * conf);
/*!
* @brief Enter run mode.
*
* @return None.
*/
void POWER_EnterRunMode(void);
/*!
* @brief Enable low power run mode.
*
* @return None.
*/
void POWER_EnableLowPowerRunMode(void);
/*!
* @brief Enter sleep mode.
*
* @param param Pointer to the initialization structure. See to @ref POWER_SleepConf_Type.
* @return None.
*/
void POWER_EnterSleepMode(POWER_SleepConf_Type * conf);
/*!
* @brief Enter stop mode.
*
* @param param Pointer to the initialization structure. See to @ref POWER_StopConf_Type.
* @return None.
*/
void POWER_EnterStopMode(POWER_StopConf_Type * conf);
/*!
* @brief Enable standby wake up pin.
*
* @param PWRx PWR instance.
* @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinConf_Type.
* @return None.
*/
void POWER_EnableStandbyWakeUpPin(PWR_StandbyWakeUpPinConf_Type * conf);
/*!
* @brief Enter standby mode.
*
* @param param Pointer to the initialization structure. See to @ref POWER_StandbyConf_Type.
* @return None.
*/
void POWER_EnterStandbyMode(POWER_StandbyConf_Type * conf);
#endif /* __HAL_POWER_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_pwr.h"
void PWR_EnableLowPowerRunMode(PWR_Type * PWRx, bool enable)
{
if (enable)
{
PWRx->CR1 |= PWR_CR1_LPR_MASK;
}
else
{
PWRx->CR1 &= ~PWR_CR1_LPR_MASK;
}
}
void PWR_EnterStopMode(PWR_Type * PWRx, bool deep_stop)
{
PWRx->CR1 &= ~PWR_CR1_PDDS_MASK;
if (deep_stop)
{
PWRx->CR1 |= PWR_CR1_LPDS_MASK;
}
else
{
PWRx->CR1 &= ~PWR_CR1_LPDS_MASK;
}
}
void PWR_EnableStandbyWakeUpPin(PWR_Type * PWRx, PWR_StandbyWakeUpPinConf_Type * conf)
{
if (NULL != conf)
{
PWRx->CR2 |= PWR_CR2_EWUP(conf->Pins);
if (conf->TrgIn == PWR_StandbyWakeUpPinTriggerIn_FallingEdge)
{
PWRx->CR3 |= PWR_CR3_WP(conf->Pins);
}
if (conf->TrgIn == PWR_StandbyWakeUpPinTriggerIn_RisingEdge)
{
PWRx->CR3 &= ~PWR_CR3_WP(conf->Pins);
}
}
else
{
PWRx->CR2 &= ~PWR_CR2_EWUP_MASK;
}
}
void PWR_EnableStandbyWakeUpPinFilter0(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter0Conf_Type * conf)
{
if (NULL != conf)
{
if (conf->Pin == PWR_WAKEUP_PIN_0)
{
PWRx->CR4 |= PWR_CR4_FILTSEL0(0u);
}
if (conf->Pin == PWR_WAKEUP_PIN_1)
{
PWRx->CR4 |= PWR_CR4_FILTSEL0(1u);
}
if (conf->Pin == PWR_WAKEUP_PIN_2)
{
PWRx->CR4 |= PWR_CR4_FILTSEL0(2u);
}
if ( (conf->Pin == PWR_WAKEUP_PIN_0) || (conf->Pin == PWR_WAKEUP_PIN_1) || (conf->Pin == PWR_WAKEUP_PIN_2) )
{
PWRx->CR4 |= PWR_CR4_FILTE0(conf->TrgIn);
PWRx->CR4 |= PWR_CR4_FILTCNT0(conf->CountValue);
PWRx->CR4 |= PWR_CR4_FILTF0(1u);
}
else
{
PWRx->CR4 |= PWR_CR4_FILTF0(0u);
}
}
else
{
PWRx->CR4 |= PWR_CR4_FILTF0(0u);
}
}
void PWR_EnableStandbyWakeUpPinFilter1(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter1Conf_Type * conf)
{
if (NULL != conf)
{
if (conf->Pin == PWR_WAKEUP_PIN_3)
{
PWRx->CR5 |= PWR_CR5_FILTSEL1(0u);
}
if (conf->Pin == PWR_WAKEUP_PIN_4)
{
PWRx->CR5 |= PWR_CR5_FILTSEL1(1u);
}
if (conf->Pin == PWR_WAKEUP_PIN_5)
{
PWRx->CR5 |= PWR_CR5_FILTSEL1(2u);
}
if ( (conf->Pin == PWR_WAKEUP_PIN_3) || (conf->Pin == PWR_WAKEUP_PIN_4) || (conf->Pin == PWR_WAKEUP_PIN_5) )
{
PWRx->CR5 |= PWR_CR5_FILTE1(conf->TrgIn);
PWRx->CR5 |= PWR_CR5_FILTCNT1(conf->CountValue);
PWRx->CR5 |= PWR_CR5_FILTF1(1u);
}
else
{
PWRx->CR5 |= PWR_CR5_FILTF1(0u);
}
}
else
{
PWRx->CR5 |= PWR_CR5_FILTF1(0u);
}
}
void PWR_EnterStandbyMode(PWR_Type * PWRx, PWR_StandbyWakeUpDelay_Type delay)
{
PWRx->CR1 |= PWR_CR1_PDDS_MASK;
PWRx->SCR |= ( PWR_WAKEUP_PIN_0
| PWR_WAKEUP_PIN_1
| PWR_WAKEUP_PIN_2
| PWR_WAKEUP_PIN_3
| PWR_WAKEUP_PIN_4
| PWR_WAKEUP_PIN_5
);
PWRx->CR6 |= PWR_CR6_STDBYFSWK(delay);
}
uint32_t PWR_GetStatus(PWR_Type * PWRx)
{
uint32_t flags = 0u;
if ( 0u != (PWR_CR1_LPR_MASK & PWRx->CR1) )
{
flags |= PWR_STATUS_LOWPOWERRUN;
}
if ( 0u != (PWR_CSR_SBF_MASK & PWRx->CSR) )
{
flags |= PWR_STATUS_STANDBYRESET;
}
return flags;
}
void PWR_ClearStatus(PWR_Type * PWRx, uint32_t flags)
{
if ( 0u != (PWR_STATUS_LOWPOWERRUN & flags) )
{
PWRx->CR1 &= ~PWR_CR1_LPR_MASK;
}
if ( 0u != (PWR_STATUS_STANDBYRESET & flags) )
{
PWRx->CR1 |= PWR_CR1_CSBF_MASK;
}
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_PWR_H__
#define __HAL_PWR_H__
#include "hal_common.h"
/*!
* @addtogroup PWR
* @{
*/
/*!
* @brief PWR driver version number.
*/
#define PWR_DRIVER_VERSION 0u /*!< PWR_0. */
/*!
* @addtogroup PWR_WAKEUP_PIN
* @{
*/
#define PWR_WAKEUP_PIN_0 (1u << 0u) /*!< Wake up pin 0 selected. */
#define PWR_WAKEUP_PIN_1 (1u << 1u) /*!< Wake up pin 1 selected. */
#define PWR_WAKEUP_PIN_2 (1u << 2u) /*!< Wake up pin 2 selected. */
#define PWR_WAKEUP_PIN_3 (1u << 3u) /*!< Wake up pin 3 selected. */
#define PWR_WAKEUP_PIN_4 (1u << 4u) /*!< Wake up pin 4 selected. */
#define PWR_WAKEUP_PIN_5 (1u << 5u) /*!< Wake up pin 5 selected. */
/*!
* @}
*/
/*!
* @addtogroup PWR_STATUS
* @{
*/
#define PWR_STATUS_LOWPOWERRUN (1u << 0u) /*!< Low power run mode flag. */
#define PWR_STATUS_STANDBYRESET (1u << 1u) /*!< Standby reset flag. */
/*!
* @}
*/
/*!
* @brief PWR standby wake up delay type.
*/
typedef enum
{
PWR_StandbyWakeUpDelay_2 = 1u, /*!< 2 LSI period selected. */
PWR_StandbyWakeUpDelay_3 = 2u, /*!< 3 LSI period selected. */
PWR_StandbyWakeUpDelay_4 = 3u, /*!< 4 LSI period selected. */
PWR_StandbyWakeUpDelay_5 = 4u, /*!< 5 LSI period selected. */
PWR_StandbyWakeUpDelay_6 = 5u, /*!< 6 LSI period selected. */
PWR_StandbyWakeUpDelay_7 = 6u, /*!< 7 LSI period selected. */
PWR_StandbyWakeUpDelay_8 = 7u, /*!< 8 LSI period selected. */
} PWR_StandbyWakeUpDelay_Type;
/*!
* @brief PWR standby mode wake up pin trigger input type.
*/
typedef enum
{
PWR_StandbyWakeUpPinTriggerIn_RisingEdge = 0u, /*!< Enable the wake up pin rising edge trigger. */
PWR_StandbyWakeUpPinTriggerIn_FallingEdge = 1u, /*!< Enable the wake up pin falling edge trigger. */
} PWR_StandbyWakeUpPinTriggerIn_Type;
/*!
* @brief This type of structure instance is used to keep setting when calling.
*/
typedef struct
{
uint32_t Pins; /*!< Specify wake up pins. See to @ref PWR_WAKEUP_PIN. */
PWR_StandbyWakeUpPinTriggerIn_Type TrgIn; /*!< @ref Specify wake up pin trigger input type. See to @ref PWR_StandbyWakeUpPinTriggerIn_Type. */
} PWR_StandbyWakeUpPinConf_Type;
/*!
* @brief This type of structure instance is used to keep setting when calling.
*/
typedef struct
{
uint32_t Pin; /*!< Specify one of the PWR_WAKEUP_PIN_0, PWR_WAKEUP_PIN_1, and PWR_WAKEUP_PIN_2 for filtering. */
PWR_StandbyWakeUpPinTriggerIn_Type TrgIn; /*!< @ref Specify wake up pin trigger input type. See to @ref PWR_StandbyWakeUpPinTriggerIn_Type. */
uint32_t CountValue; /*!< Specify filter count value. */
} PWR_StandbyWakeUpPinFilter0Conf_Type;
/*!
* @brief This type of structure instance is used to keep setting when calling.
*/
typedef struct
{
uint32_t Pin; /*!< Specify one of PWR_WAKEUP_PIN_3, PWR_WAKEUP_PIN_4, and PWR_WAKEUP_PIN_5 for filtering. */
PWR_StandbyWakeUpPinTriggerIn_Type TrgIn; /*!< @ref Specify wake up pin trigger input type. See to @ref PWR_StandbyWakeUpPinTriggerIn_Type. */
uint32_t CountValue; /*!< Specify filter count value. */
} PWR_StandbyWakeUpPinFilter1Conf_Type;
/*!
* @brief Enable low power run mode.
*
* @param PWRx PWR instance.
* @param enable 'true' to enable the mode, 'false' to disable the mode.
* @return None.
*/
void PWR_EnableLowPowerRunMode(PWR_Type * PWRx, bool enable);
/*!
* @brief Enter stop mode.
*
* @param PWRx PWR instance.
* @param deep_stop 'true' to enable the deep stop mode, 'false' to disable the deep stop mode.
* @return None.
*/
void PWR_EnterStopMode(PWR_Type * PWRx, bool deep_stop);
/*!
* @brief Enable standby mode wake up pin.
*
* @param PWRx PWR instance.
* @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinConf_Type.
* @return None.
*/
void PWR_EnableStandbyWakeUpPin(PWR_Type * PWRx, PWR_StandbyWakeUpPinConf_Type * conf);
/*!
* @brief Enable standby mode wake up pin filter 0.
*
* @param PWRx PWR instance.
* @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinFilter0Conf_Type.
* @return None.
*/
void PWR_EnableStandbyWakeUpPinFilter0(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter0Conf_Type * conf);
/*!
* @brief Enable standby mode wake up pin filter 1.
*
* @param PWRx PWR instance.
* @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinFilter1Conf_Type.
* @return None.
*/
void PWR_EnableStandbyWakeUpPinFilter1(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter1Conf_Type * conf);
/*!
* @brief Enter standby mode.
*
* @param PWRx PWR instance.
* @param Delay Specify standby mode wake up delay value. See to @ref PWR_StandbyWakeUpDelay_Type.
* @return None.
*/
void PWR_EnterStandbyMode(PWR_Type * PWRx, PWR_StandbyWakeUpDelay_Type delay);
/*!
* @brief Get the current status flags of PWR module.
*
* @param PWRx PWR instance.
* @return PWR status flags. See to @ref PWR_STATUS.
*/
uint32_t PWR_GetStatus(PWR_Type * PWRx);
/*!
* @brief Clear PWR status flags.
*
* @param PWRx PWR instance.
* @param flags PWR status flags. See to @ref PWR_STATUS.
* @return None.
*/
void PWR_ClearStatus(PWR_Type * PWRx, uint32_t flags);
/*!
*@}
*/
#endif /* __HAL_PWR_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_qspi.h"
void QSPI_Init(QSPI_Type * QSPIx, QSPI_Init_Type * init)
{
if (NULL == init /* if the init pointer is null, quit init. */
|| init->SckDiv < 2u || init->SckDiv > 9u || init->SckDiv % 2u != 0u /* The available value must be even & the range would be 2 ~ 128. */
|| init->CsHighLevelCycles < 2u || init->CsHighLevelCycles > 9u) /* available range would be 2 ~ 9. */
{
return;
}
QSPIx->CR = (QSPIx->CR & ~(QSPI_CR_SCKDIV_MASK | QSPI_CR_CSRHT_MASK | QSPI_CR_SCKMODE_MASK | QSPI_CR_OPMODE_MASK) )
| QSPI_CR_SCKDIV(init->SckDiv / 2u - 1u) /* set the baudrate. */
| QSPI_CR_CSRHT(init->CsHighLevelCycles - 2u) /* set the CS high level cycle. */
| QSPI_CR_SCKMODE(init->SpiMode) /* set the SPI mode. */
| QSPI_CR_OPMODE(QSPI_OpMode_Idle); /* set the operation mode, idle by default. */
}
void QSPI_EnableDirectRead(QSPI_Type * QSPIx, QSPI_DirectXferConf_Type * conf)
{
if (NULL == conf) /* disabled. */
{
QSPIx->CR = (QSPIx->CR & ~QSPI_CR_OPMODE_MASK) | QSPI_CR_OPMODE(QSPI_OpMode_Idle);
return;
}
/* calculate the optimal value of rxdly, the value is SCK / 4. */
uint32_t rxdly = ( ( (QSPIx->CR & QSPI_CR_SCKDIV_MASK) >> QSPI_CR_SCKDIV_SHIFT) + 1u ) >> 1u;
if (rxdly > 3)
{
rxdly = 3; /* available range would be 0 ~ 3. */
}
QSPIx->DMCR = (QSPIx->DMCR & ~(QSPI_DMCR_RXDLY_MASK | QSPI_DMCR_NUMDC_MASK | QSPI_DMCR_DMODE_MASK
| QSPI_DMCR_ABMODE_MASK | QSPI_DMCR_ABSIZE_MASK | QSPI_DMCR_ADSIZE_MASK
| QSPI_DMCR_ADMODE_MASK | QSPI_DMCR_IMODE_MASK | QSPI_DMCR_INST_MASK) )
| QSPI_DMCR_RXDLY(rxdly)
| QSPI_DMCR_NUMDC(conf->DummyCycles)
| QSPI_DMCR_DMODE(conf->DataBusWidth)
| QSPI_DMCR_ABSIZE(conf->AltWordWidth)
| QSPI_DMCR_ABMODE(conf->AltBusWidth)
| QSPI_DMCR_ADSIZE(conf->AddrWordWidth)
| QSPI_DMCR_ADMODE(conf->AddrBusWidth)
| QSPI_DMCR_IMODE(conf->CmdBusWidth)
| QSPI_DMCR_INST(conf->CmdValue);
QSPIx->DABR = QSPI_DABR_DALT(conf->AltValue);
QSPIx->CR = ( QSPIx->CR & ~( QSPI_CR_OPMODE_MASK) ) | QSPI_CR_OPMODE(QSPI_OpMode_Direct);
}
uint8_t QSPI_GetDirectData8b(QSPI_Type * QSPIx, uint32_t offset)
{
(void)QSPIx;
return (*( (uint8_t *)(QSPI_M_BASE + offset) ) );
}
uint16_t QSPI_GetDirectData16b(QSPI_Type * QSPIx, uint32_t offset)
{
(void)QSPIx;
return (*( (uint16_t *)(QSPI_M_BASE + offset) ) );
}
uint32_t QSPI_GetDirectData32b(QSPI_Type * QSPIx, uint32_t offset)
{
(void)QSPIx;
return (*( (uint32_t *)(QSPI_M_BASE + offset) ) );
}
void QSPI_SetIndirectReadConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf)
{
if(NULL == conf)
{
return;
}
/* calculate the optimal value of rxdly, the value is SCK / 4. */
uint32_t rxdly = ( ( (QSPIx->CR & QSPI_CR_SCKDIV_MASK) >> QSPI_CR_SCKDIV_SHIFT) + 1u ) >> 1u;
if (rxdly > 3)
{
rxdly = 3; /* available range would be 0 ~ 3. */
}
QSPIx->IMCR = ( QSPIx->IMCR & ~(QSPI_IMCR_IDMODE_MASK | QSPI_IMCR_NUMDC_MASK | QSPI_IMCR_DSIZE_MASK
| QSPI_IMCR_DMODE_MASK | QSPI_IMCR_ABSIZE_MASK | QSPI_IMCR_ABMODE_MASK
| QSPI_IMCR_ADSIZE_MASK | QSPI_IMCR_ADMODE_MASK | QSPI_IMCR_IMODE_MASK
| QSPI_IMCR_INST_MASK | QSPI_IMCR_RXDLY_MASK) )
| QSPI_IMCR_RXDLY(rxdly)
| QSPI_IMCR_IDMODE(0u) /* read. */
| QSPI_IMCR_NUMDC(conf->DummyCycles)
| QSPI_IMCR_DSIZE(conf->DataWordWidth)
| QSPI_IMCR_DMODE(conf->DataBusWidth)
| QSPI_IMCR_ABSIZE(conf->AltWordWidth)
| QSPI_IMCR_ABMODE(conf->AltBusWidth)
| QSPI_IMCR_ADSIZE(conf->AddrWordWidth)
| QSPI_IMCR_ADMODE(conf->AddrBusWidth)
| QSPI_IMCR_IMODE(conf->CmdBusWidth)
| QSPI_IMCR_INST(conf->CmdValue);
QSPIx->IABR = QSPI_IABR_IALT(conf->AltValue);
QSPIx->IADR = QSPI_IADR_IADDR(conf->AddrValue);
QSPIx->IWCR = QSPI_IWCR_IWCNT(0u); /* wait 7 AHB_CLK to quit inrect mode. */
QSPIx->IDLR = QSPI_IDLR_IDLEN(conf->DataLen - 1u);
QSPIx->CR = (QSPIx->CR & ~QSPI_CR_OPMODE_MASK) | QSPI_CR_OPMODE(QSPI_OpMode_Indirect);
}
uint32_t QSPI_GetIndirectData(QSPI_Type * QSPIx)
{
return QSPIx->IDFR;
}
void QSPI_SetIndirectWriteConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf)
{
if(NULL == conf)
{
return;
}
/* calculate the optimal value of rxdly, the value is SCK / 4. */
uint32_t rxdly = ( ( (QSPIx->CR & QSPI_CR_SCKDIV_MASK) >> QSPI_CR_SCKDIV_SHIFT) + 1u ) >> 1u;
if (rxdly > 3)
{
rxdly = 3; /* available range would be 0 ~ 3. */
}
QSPIx->IMCR = ( QSPIx->IMCR & ~(QSPI_IMCR_IDMODE_MASK | QSPI_IMCR_NUMDC_MASK | QSPI_IMCR_DSIZE_MASK
| QSPI_IMCR_DMODE_MASK | QSPI_IMCR_ABSIZE_MASK | QSPI_IMCR_ABMODE_MASK
| QSPI_IMCR_ADSIZE_MASK | QSPI_IMCR_ADMODE_MASK | QSPI_IMCR_IMODE_MASK
| QSPI_IMCR_INST_MASK | QSPI_IMCR_RXDLY_MASK) )
| QSPI_IMCR_RXDLY(rxdly)
| QSPI_IMCR_IDMODE(1u) /* write. */
| QSPI_IMCR_NUMDC(conf->DummyCycles)
| QSPI_IMCR_DSIZE(conf->DataWordWidth)
| QSPI_IMCR_DMODE(conf->DataBusWidth)
| QSPI_IMCR_ABSIZE(conf->AltWordWidth)
| QSPI_IMCR_ABMODE(conf->AltBusWidth)
| QSPI_IMCR_ADSIZE(conf->AddrWordWidth)
| QSPI_IMCR_ADMODE(conf->AddrBusWidth)
| QSPI_IMCR_IMODE(conf->CmdBusWidth)
| QSPI_IMCR_INST(conf->CmdValue);
QSPIx->IABR = QSPI_IABR_IALT(conf->AltValue);
QSPIx->IADR = QSPI_IADR_IADDR(conf->AddrValue);
QSPIx->IWCR = QSPI_IWCR_IWCNT(0u); /* wait 7 AHB_CLK to quit inrect mode. */
QSPIx->IDLR = QSPI_IDLR_IDLEN(conf->DataLen - 1u);
QSPIx->CR = (QSPIx->CR & ~QSPI_CR_OPMODE_MASK) | QSPI_CR_OPMODE(QSPI_OpMode_Indirect);
}
void QSPI_PutIndirectData(QSPI_Type * QSPIx, uint32_t value)
{
QSPIx->IDFR = value;
}
void QSPI_EnableXIP(QSPI_Type * QSPIx, bool enable)
{
if (true == enable)
{
QSPIx->CR = QSPIx->CR | QSPI_CR_XIPMODE_MASK;
}
else
{
QSPIx->CR = QSPIx->CR & ~QSPI_CR_XIPMODE_MASK;
}
}
void QSPI_SetIndirectAutoXIP(QSPI_Type * QSPIx, bool enable)
{
if (true == enable)
{
QSPIx->IMCR |= QSPI_IMCR_XIPIM_MASK;
}
else
{
QSPIx->IMCR &= ~QSPI_IMCR_XIPIM_MASK;
}
}
uint32_t QSPI_GetStatus(QSPI_Type * QSPIx)
{
return QSPIx->SR;
}
void QSPI_ClearStatus(QSPI_Type * QSPIx, uint32_t status)
{
QSPIx->SR &= status; /* write 1 to clear status. */
}
uint32_t QSPI_GetOpMode(QSPI_Type * QSPIx)
{
return (QSPIx->SR & QSPI_SR_OPCRCF_MASK) >> QSPI_SR_OPCRCF_SHIFT;
}
void QSPI_EnableInterrupts(QSPI_Type * QSPIx, uint32_t interrupts, bool enable)
{
if(true == enable)
{
QSPIx->IDER |= interrupts;
}
else
{
QSPIx->IDER &= ~interrupts;
}
}
void QSPI_EnableDMARequest(QSPI_Type * QSPIx, uint32_t request, bool enable)
{
if(true == enable)
{
QSPIx->IDER |= request;
}
else
{
QSPIx->IDER &= ~request;
}
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_QSPI_H__
#define __HAL_QSPI_H__
#include "hal_common.h"
/*!
* @addtogroup QSPI
* @{
*/
/*!
* @brief QSPI driver version number.
*/
#define QSPI_DRIVER_VERSION 0u /*!< QSPI_0. */
/*!
* @addtogroup QSPI_STATUS
* @{
*/
#define QSPI_STATUS_XIP_ENABLE QSPI_SR_XIPST_MASK /*!< Status flag when QSPI XIP enabled. */
#define QSPI_STATUS_FIFO_FULL QSPI_SR_FULL_MASK /*!< Status flag when QSPI FIFO full. */
#define QSPI_STATUS_FIFO_EMPTY QSPI_SR_EMPTY_MASK /*!< Status flag when QSPI FIFO empty. */
#define QSPI_STATUS_BUSY QSPI_SR_BUSY_MASK /*!< Status flag when QSPI xfer data. */
#define QSPI_STATUS_XFER_DONE QSPI_SR_TCF_MASK /*!< Status flag when QSPI xfer done. */
#define QSPI_STATUS_OPMODE_CHANGE_DONE QSPI_SR_OPCRCF_MASK /*!< Status flag when QSPI change the operation mode done. */
/*!
* @}
*/
/*!
* @addtogroup QSPI_INT
* @{
*/
#define QSPI_INT_FIFO_FULL QSPI_IDER_FULLINTEN_MASK /*!< Interrupt enable when QSPI FIFO is full. */
#define QSPI_INT_FIFO_EMPTY QSPI_IDER_EMPTYINTEN_MASK /*!< Interrupt enable when QSPI FIFO is empty. */
#define QSPI_INT_XFER_DONE QSPI_IDER_TCFINTEN_MASK /*!< Interrupt enable when QSPI xfer done. */
/*!
* @}
*/
/*!
* @addtogroup QSPI_DMA
* @{
*/
#define QSPI_DMA_FIFO_FULL QSPI_IDER_FULLDMAEN_MASK /*!< DMA request enable when QSPI FIFO is full. */
#define QSPI_DMA_FIFO_EMPTY QSPI_IDER_EMPTYDMAEN_MASK /*!< DMA request enable when QSPI FIFO is empty. */
#define QSPI_DMA_XFER_DONE QSPI_IDER_TCFDMAEN_MASK /*!< DMA request enable when QSPI xfer done. */
/*!
* @}
*/
/*!
* @brief SPI mode, set the clock polarity(CPOL) & clock phase(CPHA).
*/
typedef enum
{
QSPI_SpiMode_0 = 0x00, /*!< SPI mode 0, CPOL = 0, CPHA = 0. */
QSPI_SpiMode_3 = 0x01, /*!< SPI mode 0, CPOL = 1, CPHA = 1. */
} QSPI_SpiMode_Type;
/*!
* @brief Operation mode, defines the QSPI operation status.
*/
typedef enum
{
QSPI_OpMode_Direct = 0x00, /*!< Direct mode, read data by mapped addr. */
QSPI_OpMode_Indirect = 0x02, /*!< Indirect mode, read & write data by QSPI peripheral. */
QSPI_OpMode_Idle = 0x03, /*!< Idle mode, cannot read data by direct mode. */
} QSPI_OpMode_Type;
/*!
* @brief Word width, defines the word width when xfer content.
*/
typedef enum
{
QSPI_WordWidth_8b = 0x00, /*!< The word wide is 8 bit. */
QSPI_WordWidth_16b = 0x01, /*!< The word wide is 16 bit. */
QSPI_WordWidth_24b = 0x02, /*!< The word wide is 24 bit. */
QSPI_WordWidth_32b = 0x03, /*!< The word wide is 32 bit. */
} QSPI_WordWidth_Type;
/*!
* @brief Bus width or line mode, defines the bus width when xfer content.
*/
typedef enum
{
QSPI_BusWidth_None = 0x00, /*!< No more content in this phase. */
QSPI_BusWidth_1b = 0x01, /*!< Xfer content by signal line. (using MOSI or MISO xfer content). */
QSPI_BusWidth_2b = 0x02, /*!< Xfer content by dual lines. (using DA0 & DA1 xfer content). */
QSPI_BusWidth_4b = 0x03, /*!< Xfer content by quad lines. (using DA0, DA1, DA2 & DA3 xfer content). */
} QSPI_BusWidth_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref QSPI_Init() to initialize the QSPI module.
*/
typedef struct
{
uint32_t SckDiv; /*!< Specify the QSPI SCK Prescaler.
The SCK output clock = AHB_CLK / SckDiv.
The available value must be even & the range would be 2 ~ 128. */
uint32_t CsHighLevelCycles; /*!< Specify the QSPI CS High Level Cycles.
The minimum duration for CS output high level (invalid level) is AHB_CLK * CsHighLevelCycles.
The available range would be 2 ~ 9. */
QSPI_SpiMode_Type SpiMode; /*!< Specify the SPI mode. */
} QSPI_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref QSPI_EnableDirectRead() to enable direct mode.
*/
typedef struct
{
/* instruction phase. */
QSPI_BusWidth_Type CmdBusWidth; /*!< Specify the QSPI instruction bus width. */
uint32_t CmdValue; /*!< Specify the QSPI instruction value. */
/* addr phase. */
/* the addr value will be determined when accessing QSPI device by direct operation mode. */
QSPI_BusWidth_Type AddrBusWidth; /*!< Specify the QSPI addr bus width. */
QSPI_WordWidth_Type AddrWordWidth; /*!< Specify the QSPI addr bit width. */
/* alt phase. */
QSPI_BusWidth_Type AltBusWidth; /*!< Specify the QSPI alt bus width. */
QSPI_WordWidth_Type AltWordWidth; /*!< Specify the QSPI alt bit width. */
uint32_t AltValue; /*!< Specify the QSPI alt value. */
/* dummy phase. */
uint32_t DummyCycles; /*!< Specify the QSPI dummy cycles, available range would be 0 ~ 31. */
/* data phase. */
QSPI_BusWidth_Type DataBusWidth; /*!< Specify the QSPI data bus width. */
} QSPI_DirectXferConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref QSPI_SetIndirectReadConf() or @ref QSPI_SetIndirectWriteConf() to set xfer configure.
*/
typedef struct
{
/* instruction phase. */
QSPI_BusWidth_Type CmdBusWidth; /*!< Specify the QSPI instruction bus width. */
uint32_t CmdValue; /*!< Specify the QSPI instruction value. */
/* addr phase. */
QSPI_BusWidth_Type AddrBusWidth; /*!< Specify the QSPI addr bus width. */
QSPI_WordWidth_Type AddrWordWidth; /*!< Specify the QSPI addr bit width. */
uint32_t AddrValue; /*!< Specify the QSPI addr value. */
/* alt phase. */
QSPI_BusWidth_Type AltBusWidth; /*!< Specify the QSPI alt bus width. */
QSPI_WordWidth_Type AltWordWidth; /*!< Specify the QSPI alt bit width. */
uint32_t AltValue; /*!< Specify the QSPI alt value. */
/* dummy phase. */
uint32_t DummyCycles; /*!< Specify the QSPI dummy cycles, available range would be 0 ~ 31. */
/* data phase. */
QSPI_BusWidth_Type DataBusWidth; /*!< Specify the QSPI data bus width. */
QSPI_WordWidth_Type DataWordWidth; /*!< Specify the QSPI data bit width. */
uint32_t DataLen; /*!< Specify the QSPI data length. */
} QSPI_IndirectXferConf_Type;
/*!
* @brief Initialize the QSPI module.
*
* @param QSPIx QSPI instance.
* @param init Pointer to the initialization structure. See to @ref QSPI_Init_Type.
* @return None.
*/
void QSPI_Init(QSPI_Type * QSPIx, QSPI_Init_Type * init);
/*!
* @brief Enable the QSPI direct read configure.
*
* @param QSPIx QSPI instance.
* @param conf Pointer to the initialization structure. See to @ref QSPI_DirectXferConf_Type.
* @return None.
*/
void QSPI_EnableDirectRead(QSPI_Type * QSPIx, QSPI_DirectXferConf_Type * conf);
/*!
* @brief Get the data from mapped addr as 8 bit.
*
* @param QSPIx QSPI instance.
* @param offset offset of data in QSPI Device.
* @return The data value received from the mapped addr.
*/
uint8_t QSPI_GetDirectData8b(QSPI_Type * QSPIx, uint32_t offset);
/*!
* @brief Get the data from mapped addr as 16 bit.
*
* @param QSPIx QSPI instance.
* @param offset offset of data in QSPI Device.
* @return The data value received from the mapped addr.
*/
uint16_t QSPI_GetDirectData16b(QSPI_Type * QSPIx, uint32_t addr);
/*!
* @brief Get the data from mapped addr as 32 bit.
*
* @param QSPIx QSPI instance.
* @param offset offset of data in QSPI Device.
* @return The data value received from the mapped addr.
*/
uint32_t QSPI_GetDirectData32b(QSPI_Type * QSPIx, uint32_t addr);
/*!
* @brief Set the QSPI indirect read configure.
*
* After configuration, the indirect read process will start.
*
* @param QSPIx QSPI instance.
* @param conf Pointer to the config structure. See to @ref QSPI_IndirectXferConf_Type.
* @return None.
*/
void QSPI_SetIndirectReadConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf);
/*!
* @brief Get the data from FIFO in indirect mode of the QSPI module.
*
* @param QSPIx QSPI instance.
* @return The data value received from the FIFO.
*/
uint32_t QSPI_GetIndirectData(QSPI_Type * QSPIx);
/*!
* @brief Set the QSPI indirect write configure.
*
* After configuration, the indirect write process will start.
*
* @param QSPIx QSPI instance.
* @param conf Pointer to the config structure. See to @ref QSPI_IndirectXferConf_Type.
* @return None.
*/
void QSPI_SetIndirectWriteConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf);
/*!
* @brief Put the data into FIFO of the QSPI module.
*
* @param QSPIx QSPI instance.
* @param value Data value to be send through the FIFO.
* @return None.
*/
void QSPI_PutIndirectData(QSPI_Type * QSPIx, uint32_t value);
/*!
* @brief Enable the QSPI XIP mode.
*
* @param QSPIx QSPI instance.
* @param enable 'true' to enable XIP, 'false' to disable XIP.
* @return None.
*/
void QSPI_EnableXIP(QSPI_Type * QSPIx, bool enable);
/*!
* @brief Set the QSPI enbale XIP mode after quit indirect mode.
*
* @param QSPIx QSPI instance.
* @param enable 'true' to enable XIP, 'false' to disable XIP.
* @return None.
*/
void QSPI_SetIndirectAutoXIP(QSPI_Type * QSPIx, bool enable);
/*!
* @brief Get the current status flags of the QSPI module.
*
* @param QSPIx QSPI instance.
* @return Status flags. See to @ref QSPI_STATUS.
*/
uint32_t QSPI_GetStatus(QSPI_Type * QSPIx);
/*!
* @brief Clear the interrupts status flags of the QSPI module.
*
* @param QSPIx QSPI instance.
* @param status The mask codes of the indicated status flags to be cleared.
* @return Status flags. See to @ref QSPI_INT.
*/
void QSPI_ClearStatus(QSPI_Type * QSPIx, uint32_t status);
/*!
* @brief Gets the current operating mode.
*
* @param QSPIx QSPI instance.
* @return Operation, See to @ref QSPI_OpMode_Type.
*/
uint32_t QSPI_GetOpMode(QSPI_Type * QSPIx);
/*!
* @brief Enable interrupts of the QSPI module.
*
* @param QSPIx QSPI instance.
* @param interrupts Interrupt code masks. See to @ref QSPI_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void QSPI_EnableInterrupts(QSPI_Type * QSPIx, uint32_t interrupts, bool enable);
/*!
* @brief Enable DMA request of the QSPI module.
*
* @param QSPIx QSPI instance.
* @param dmas dma request code masks. See to @ref QSPI_DMA.
* @param enable 'true' to enable the indicated request, 'false' to disable the indicated request.
* @return None.
*/
void QSPI_EnableDMA(QSPI_Type * QSPIx, uint32_t dmas, bool enable);
/*!
*@}
*/
#endif /* __HAL_QSPI_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_common.h"
#include "hal_rcc.h"
void RCC_EnableAHB1Periphs(uint32_t ahb1_periphs, bool enable)
{
(enable) ? (RCC->AHB1ENR |= ahb1_periphs) : (RCC->AHB1ENR &= ~ahb1_periphs);
}
void RCC_EnableAPB1Periphs(uint32_t apb1_periphs, bool enable)
{
(enable) ? (RCC->APB1ENR |= apb1_periphs) : (RCC->APB1ENR &= ~apb1_periphs);
}
void RCC_EnableAPB2Periphs(uint32_t apb2_periphs, bool enable)
{
(enable) ? (RCC->APB2ENR |= apb2_periphs) : (RCC->APB2ENR &= ~apb2_periphs);
}
void RCC_ResetAHB1Periphs(uint32_t ahb1_periphs)
{
RCC->AHB1RSTR |= ahb1_periphs;
RCC->AHB1RSTR &= ~ahb1_periphs;
}
void RCC_ResetAPB1Periphs(uint32_t apb1_periphs)
{
RCC->APB1RSTR |= apb1_periphs;
RCC->APB1RSTR &= ~apb1_periphs;
}
void RCC_ResetAPB2Periphs(uint32_t apb2_periphs)
{
RCC->APB2RSTR |= apb2_periphs;
RCC->APB2RSTR &= ~apb2_periphs;
}
void RCC_SetMCOConf(RCC_MCO_Type source)
{
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCO_MASK) | RCC_CFGR_MCO(source);
}
void RCC_SetADCClockDiv(ADC_Type * ADCx, uint32_t div)
{
if (ADCx == ADC1)
{
RCC->ADC1CFGR = (RCC->ADC1CFGR & ~RCC_ADC1CFGR_PRE_MASK) | RCC_ADC1CFGR_PRE(div);
}
else if (ADCx == ADC2)
{
RCC->ADC2CFGR = (RCC->ADC2CFGR & ~RCC_ADC2CFGR_PRE_MASK) | RCC_ADC2CFGR_PRE(div);
}
}
void RCC_SetADCCalibClockDiv(ADC_Type * ADCx, uint32_t div)
{
if (ADCx == ADC1)
{
RCC->ADC1CFGR = (RCC->ADC1CFGR & ~RCC_ADC1CFGR_PRECAL_MASK) | RCC_ADC1CFGR_PRECAL(div);
}
else if (ADCx == ADC2)
{
RCC->ADC2CFGR = (RCC->ADC2CFGR & ~RCC_ADC2CFGR_PRECAL_MASK) | RCC_ADC1CFGR_PRECAL(div);
}
}
void RCC_SetDACClockDiv(uint32_t div)
{
RCC->DACCFGR = (RCC->DACCFGR & ~RCC_DACCFGR_PRE_MASK) | RCC_DACCFGR_PRE(div);
}
void RCC_EnableFSMCSyncMode(bool enable)
{
(enable) ? (RCC->FSMCCFGR |= RCC_FSMCCFGR_FSMCSYNCEN_MASK) : (RCC->FSMCCFGR &= ~RCC_FSMCCFGR_FSMCSYNCEN_MASK);
}
void RCC_SetFSMCClockDiv(uint32_t div)
{
RCC->FSMCCFGR = (RCC->FSMCCFGR & ~RCC_FSMCCFGR_FSMCPRE_MASK) | RCC_FSMCCFGR_FSMCPRE(div);
}
void RCC_SetTPIUClockDiv(uint32_t div)
{
RCC->TPIUCFGR = (RCC->TPIUCFGR & ~RCC_TPIUCFGR_PRE_MASK) | RCC_TPIUCFGR_PRE(div);
}
void RCC_EanbleBKPWriteProtect(bool enable)
{
(enable) ? (RCC->BDCR &= ~RCC_BDCR_DBP_MASK) : (RCC->BDCR |= RCC_BDCR_DBP_MASK);
}
void RCC_EanbleBKPReset(bool enable)
{
(enable) ? (RCC->BDCR |= RCC_BDCR_BDRST_MASK) : (RCC->BDCR &= ~RCC_BDCR_BDRST_MASK);
}
void RCC_EanbleRTCClock(bool enable)
{
(enable) ? (RCC->BDCR |= RCC_BDCR_RTCEN_MASK) : (RCC->BDCR &= ~RCC_BDCR_RTCEN_MASK);
}
void RCC_SetRTCClockSource(uint32_t source)
{
RCC->BDCR |= RCC_BDCR_RTCSEL(source);
}
void RCC_EanbleLSEBypassMode(bool enable)
{
(enable) ? (RCC->BDCR |= RCC_BDCR_LSEBYP_MASK) : (RCC->BDCR &= ~RCC_BDCR_LSEBYP_MASK);
}
uint32_t GetLSEReadyStatus(void)
{
return (RCC->BDCR &= RCC_BDCR_LSERDY_MASK);
}
void RCC_EanbleLSEClock(bool enable)
{
(enable) ? (RCC->BDCR |= RCC_BDCR_LSEON_MASK) : (RCC->BDCR &= ~RCC_BDCR_LSEON_MASK);
}
uint32_t GetResetStatus(ResetStatus_Type status )
{
return (RCC->CSR &= status);
}
void ClearResetStatus(void)
{
RCC->CSR = RCC_CSR_RMVF_MASK;
}
void RCC_EanbleCPULock(bool enable)
{
(enable) ? (RCC->CSR |= RCC_CSR_LOCKUPEN_MASK) : (RCC->BDCR &= ~RCC_CSR_LOCKUPEN_MASK);
}
void RCC_EanblePVDReset(bool enable)
{
(enable) ? (RCC->CSR |= RCC_CSR_PVDRSTEN_MASK) : (RCC->BDCR &= ~RCC_CSR_PVDRSTEN_MASK);
}
void RCC_EanbleLSIClockOutput(bool enable)
{
(enable) ? (RCC->CSR |= RCC_CSR_LSIOE_MASK) : (RCC->BDCR &= ~RCC_CSR_LSIOE_MASK);
}
void RCC_EanbleLSIClock(bool enable)
{
(enable) ? (RCC->CSR |= RCC_CSR_LSION_MASK) : (RCC->BDCR &= ~RCC_CSR_LSION_MASK);
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_RCC_H__
#define __HAL_RCC_H__
#include "hal_common.h"
/*!
* @addtogroup RCC
* @{
*/
/*!
* @addtogroup RCC_AHB1_PERIPH
* @{
*/
#define RCC_AHB1_PERIPH_GPIOA (1u << 0u) /*!< AHB1 peripheral GPIOA clock 0 bit. */
#define RCC_AHB1_PERIPH_GPIOB (1u << 1u) /*!< AHB1 peripheral GPIOB clock 1 bit. */
#define RCC_AHB1_PERIPH_GPIOC (1u << 2u) /*!< AHB1 peripheral GPIOC clock 2 bit. */
#define RCC_AHB1_PERIPH_GPIOD (1u << 3u) /*!< AHB1 peripheral GPIOD clock 3 bit. */
#define RCC_AHB1_PERIPH_GPIOE (1u << 4u) /*!< AHB1 peripheral GPIOE clock 4 bit. */
#define RCC_AHB1_PERIPH_GPIOF (1u << 5u) /*!< AHB1 peripheral GPIOF clock 5 bit. */
#define RCC_AHB1_PERIPH_GPIOG (1u << 6u) /*!< AHB1 peripheral GPIOG clock 6 bit. */
#define RCC_AHB1_PERIPH_GPIOH (1u << 7u) /*!< AHB1 peripheral GPIOH clock 7 bit. */
#define RCC_AHB1_PERIPH_GPIOI (1u << 8u) /*!< AHB1 peripheral GPIOI clock 8 bit. */
#define RCC_AHB1_PERIPH_CRC (1u << 12u) /*!< AHB1 peripheral CRC clock 12 bit. */
#define RCC_AHB1_PERIPH_FLASH (1u << 13u) /*!< AHB1 peripheral FLASH clock 13 bit. */
#define RCC_AHB1_PERIPH_SRAM (1u << 14u) /*!< AHB1 peripheral SRAM clock 14 bit. */
#define RCC_AHB1_PERIPH_CORDIC (1u << 15u) /*!< AHB1 peripheral CORDIC clock 15 bit. */
#define RCC_AHB1_PERIPH_ITCM (1u << 16u) /*!< AHB1 peripheral ITCM clock 16 bit. */
#define RCC_AHB1_PERIPH_DTCM (1u << 17u) /*!< AHB1 peripheral DTCM clock 17 bit. */
#define RCC_AHB1_PERIPH_ETHMAC (1u << 19u) /*!< AHB1 peripheral ETHMAC clock 19 bit. */
#define RCC_AHB1_PERIPH_DMA1 (1u << 21u) /*!< AHB1 peripheral DMA1 clock 21 bit. */
#define RCC_AHB1_PERIPH_DMA2 (1u << 22u) /*!< AHB1 peripheral DMA2 clock 22 bit. */
#define RCC_AHB1_PERIPH_USBOTGFS (1u << 24u) /*!< AHB1 peripheral USBOTGFS clock 24 bit. */
#define RCC_AHB1_PERIPH_FSMC (1u << 28u) /*!< AHB1 peripheral FSMC clock 28 bit. */
#define RCC_AHB1_PERIPH_QSPI (1u << 30u) /*!< AHB1 peripheral QSPI clock 30 bit. */
/*!
* @}
*/
/*!
* @addtogroup RCC_APB1_PERIPH
* @{
*/
#define RCC_APB1_PERIPH_TIM2 (1u << 0u) /*!< APB1 peripheral TIM2 clock 0 bit. */
#define RCC_APB1_PERIPH_TIM3 (1u << 1u) /*!< APB1 peripheral TIM3 clock 1 bit. */
#define RCC_APB1_PERIPH_TIM4 (1u << 2u) /*!< APB1 peripheral TIM4 clock 2 bit. */
#define RCC_APB1_PERIPH_TIM5 (1u << 3u) /*!< APB1 peripheral TIM5 clock 3 bit. */
#define RCC_APB1_PERIPH_TIM6 (1u << 4u) /*!< APB1 peripheral TIM6 clock 4 bit. */
#define RCC_APB1_PERIPH_TIM7 (1u << 5u) /*!< APB1 peripheral TIM7 clock 5 bit. */
#define RCC_APB1_PERIPH_WWDG (1u << 11u) /*!< APB1 peripheral WWDG clock 11 bit. */
#define RCC_APB1_PERIPH_SPI2 (1u << 14u) /*!< APB1 peripheral SPI2 clock 14 bit. */
#define RCC_APB1_PERIPH_SPI3 (1u << 15u) /*!< APB1 peripheral SPI3 clock 15 bit. */
#define RCC_APB1_PERIPH_UART2 (1u << 17u) /*!< APB1 peripheral UART2 clock 17 bit. */
#define RCC_APB1_PERIPH_UART3 (1u << 18u) /*!< APB1 peripheral UART3 clock 18 bit. */
#define RCC_APB1_PERIPH_UART4 (1u << 19u) /*!< APB1 peripheral UART4 clock 19 bit. */
#define RCC_APB1_PERIPH_UART5 (1u << 20u) /*!< APB1 peripheral UART5 clock 20 bit. */
#define RCC_APB1_PERIPH_I2C1 (1u << 21u) /*!< APB1 peripheral I2C1 clock 21 bit. */
#define RCC_APB1_PERIPH_I2C2 (1u << 22u) /*!< APB1 peripheral I2C2 clock 22 bit. */
#define RCC_APB1_PERIPH_CRS (1u << 24u) /*!< APB1 peripheral CRS clock 24 bit. */
#define RCC_APB1_PERIPH_FLEXCAN1 (1u << 25u) /*!< APB1 peripheral FLEXCAN1 clock 25 bit. */
#define RCC_APB1_PERIPH_BKP (1u << 27u) /*!< APB1 peripheral BKP clock 27 bit. */
#define RCC_APB1_PERIPH_PWR_DBG (1u << 28u) /*!< APB1 peripheral PWR clock 28 bit. */
#define RCC_APB1_PERIPH_DAC (1u << 29u) /*!< APB1 peripheral DAC clock 29 bit. */
#define RCC_APB1_PERIPH_UART7 (1u << 30u) /*!< APB1 peripheral UART7 clock 30 bit. */
/*!
* @}
*/
/*!
* @addtogroup RCC_APB2_PERIPH
* @{
*/
#define RCC_APB2_PERIPH_TIM1 (1u << 0u) /*!< APB2 peripheral TIM1 clock 0 bit. */
#define RCC_APB2_PERIPH_TIM8 (1u << 1u) /*!< APB2 peripheral TIM8 clock 1 bit. */
#define RCC_APB2_PERIPH_UART1 (1u << 4u) /*!< APB2 peripheral UART1 clock 4 bit. */
#define RCC_APB2_PERIPH_UART6 (1u << 5u) /*!< APB2 peripheral UART6 clock 5 bit. */
#define RCC_APB2_PERIPH_ADC1 (1u << 8u) /*!< APB2 peripheral ADC1 clock 8 bit. */
#define RCC_APB2_PERIPH_ADC2 (1u << 9u) /*!< APB2 peripheral ADC2 clock 9 bit. */
#define RCC_APB2_PERIPH_SPI1 (1u << 12u) /*!< APB2 peripheral SPI1 clock 12 bit. */
#define RCC_APB2_PERIPH_SYSCFG (1u << 14u) /*!< APB2 peripheral SYSCFG clock 14 bit. */
#define RCC_APB2_PERIPH_COMP (1u << 15u) /*!< APB2 peripheral COMP clock 15 bit. */
#define RCC_APB2_PERIPH_FLEXCAN2 (1u << 24u) /*!< APB2 peripheral FLEXCAN2 clock 24 bit. */
#define RCC_APB2_PERIPH_MINDSWITCH (1u << 28u) /*!< APB2 peripheral MINDSWITCH clock 28 bit. */
#define RCC_APB2_PERIPH_LPTIM (1u << 30u) /*!< APB2 peripheral LPTIM clock 30 bit. */
#define RCC_APB2_PERIPH_LPUART (1u << 31u) /*!< APB2 peripheral LPUART clock 31 bit. */
/*!
* @}
*/
/*!
* @brief Define the clock source for MCO output.
*/
typedef enum
{
RCC_MCO_NoClock = 0u, /*!< MCO NoClock 0 bits. */
RCC_MCO_LSI = 2u, /*!< MCO LSI 2 bits. */
RCC_MCO_LSE = 3u, /*!< MCO LSE 3 bits. */
RCC_MCO_SYSCLK = 4u, /*!< MCO SYSCLK 4 bits. */
RCC_MCO_HSI = 5u, /*!< MCO HSI 5 bits. */
RCC_MCO_HSE = 6u, /*!< MCO HSE 6 bits. */
RCC_MCO_PLL1CLK = 7u, /*!< MCO PLL1CLK 7 bits. */
RCC_MCO_PLL2CLK = 8u, /*!< MCO PLL2CLK 8 bits. */
} RCC_MCO_Type;
/*!
* @brief Define the clock source for MCO output.
*/
typedef enum
{
RCC_ResetStatus_LPWR = 31u, /*!< Low Power Reset Flag. */
RCC_ResetStatus_WWDG = 30u, /*!< Window Watchdog Reset Flag. */
RCC_ResetStatus_IWDG = 29u, /*!< Independent Watchdog Reset Flag. */
RCC_ResetStatus_SW = 26u, /*!< Software Reset Flag. */
RCC_ResetStatus_POR = 27u, /*!< POR/PDR Reset Flag. */
RCC_ResetStatus_PIN = 26u, /*!< PIN Reset Flag. */
RCC_ResetStatus_CPULOCKUP = 23u, /*!< CPU Lockup Reset Flag. */
RCC_ResetStatus_PVD = 22u, /*!< PVD Reset Flag. */
RCC_ResetStatus_LSIREADY = 22u, /*!< LSI Ready. */
}ResetStatus_Type;
/*!
* @brief Enable the RCC AHB1 periphs clock module.
*
* @param ahb1_periphs AHB1 Peripheral instance.
* @param enable 'true' to enable the AHB1Periphs, 'false' to disable the AHB1Periphs.
* @return None.
*/
void RCC_EnableAHB1Periphs(uint32_t ahb1_periphs, bool enable);
/*!
* @brief Reset the RCC AHB1 periphs clock module.
*
* @param ahb1_periphs AHB1 Peripheral instance.
* @return None.
*/
void RCC_ResetAHB1Periphs(uint32_t ahb1_periphs);
/*!
* @brief Enable the RCC APB1 periphs clock module.
*
* @param apb1_periphs APB1 Peripheral instance.
* @param enable 'true' to enable the APB1Periphs, 'false' to disable the APB1Periphs.
* @return None.
*/
void RCC_EnableAPB1Periphs(uint32_t apb1_periphs, bool enable);
/*!
* @brief Reset the RCC APB1 periphs clock module.
*
* @param apb1_periphs APB1 Peripheral instance.
* @return None.
*/
void RCC_ResetAPB1Periphs(uint32_t apb1_periphs);
/*!
* @brief Enable the RCC APB2 periphs clock module.
*
* @param apb2_periphs APB1 Peripheral instance.
* @param enable 'true' to enable the APB2Periphs, 'false' to disable the APB2Periphs.
* @return None.
*/
void RCC_EnableAPB2Periphs(uint32_t apb2_periphs, bool enable);
/*!
* @brief Reset the RCC APB2 periphs clock module.
*
* @param apb2_periphs APB2 Peripheral instance.
* @return None.
*/
void RCC_ResetAPB2Periphs(uint32_t apb2_periphs);
/*!
* @brief MCO Configuration clock source.
*
* @param source The clock source for MCO Configuration.
* @return None.
*/
void RCC_SetMCOConf(RCC_MCO_Type source);
/*!
* @brief Set ADC clock div.
*
* @param ADCx ADC instance.
* @param div The ADC clock div.
* @return None.
*/
void RCC_SetADCClockDiv(ADC_Type * ADCx, uint32_t div);
/*!
* @brief Set ADC calibration clock div.
*
* @param ADCx ADC instance.
* @param div The ADC calibration clock div.
* @return None.
*/
void RCC_SetADCCalibClockDiv(ADC_Type * ADCx, uint32_t div);
/*!
* @brief Set DAC clock div.
*
* @param div The DAC clock div.
* @return None.
*/
void RCC_SetDACClockDiv(uint32_t div);
/*!
* @brief Enable FSMC synchronization.
*
* @param enable 'true' to enable the FSMC synchronization,'false' to disable the FSMC synchronization, .
* @return None.
*/
void RCC_EnableFSMCSyncMode(bool enable);
/*!
* @brief Set FSMC clock div.
*
* @param div The FSMC clock div.
* @return None.
*/
void RCC_SetFSMCClockdiv(uint32_t div);
/*!
* @brief Set TPIU clock div.
*
* @param div The TPIU clock div.
* @return None.
*/
void RCC_SetTPIUClockDiv(uint32_t div);
/*!
* @brief Enable BKP write Protect.
*
* @param enable 'true' to can not allow writting BKP & RTC ,'false' to allow writting BKP & RTC .
* @return None.
*/
void RCC_EanbleBKPWriteProtect(bool enable);
/*!
* @brief Enable BKP reset.
*
* @param enable 'true' to reset BKP ,'false' to not reset.
* @return None.
*/
void RCC_EanbleBKPReset(bool enable);
/*!
* @brief Enable RTC clock.
*
* @param enable 'true' to enable RTC cloxk ,'false' to disable.
* @return None.
*/
void RCC_EanbleRTCClock(bool enable);
/*!
* @brief Set RTC clock source.
*
* @param source the RTC clock source.
* @return None.
*/
void RCC_SetRTCClockSource(uint32_t source);
/*!
* @brief Enable LSE Bypass Mode.
*
* @param enable 'true' to enable LSE Bypass Mode ,'false' to disable.
* @return None.
*/
void RCC_EanbleLSEBypassMode(bool enable);
/*!
* @brief Get LSE Oscillator Ready.
*
* @param None.
* @return Ready Status.
*/
uint32_t GetLSEReadyStatus(void);
/*!
* @brief Enable LSE oscillator clock.
*
* @param enable 'true' to enable LSE oscillator clock ,'false' to disable.
* @return None.
*/
void RCC_EanbleLSEClock(bool enable);
/*!
* @brief Get Reset Status.
*
* @param status the reset status ,see to @ref ResetStatus_Type.
* @return the reset status.
*/
uint32_t GetResetStatus(ResetStatus_Type status );
/*!
* @brief Clear all Reset Status.
*
* @param None.
* @return None.
*/
void ClearResetStatus(void);
/*!
* @brief Enable CPU Lock.
*
* @param enable 'true' to enable lock CPU ,'false' to disable.
* @return None.
*/
void RCC_EanbleCPULock(bool enable);
/*!
* @brief Enable PVD Reset.
*
* @param enable 'true' to reset PVD ,'false' to disable.
* @return None.
*/
void RCC_EanblePVDReset(bool enable);
/*!
* @brief Enable LSI clock output.
*
* @param enable 'true' to enable LSI clock output,'false' to disable.
* @return None.
*/
void RCC_EanbleLSIClockOutput(bool enable);
/*!
* @brief Enable LSI Oscillator .
*
* @param enable 'true' to enable LSI Oscillator ,'false' to disable.
* @return None.
*/
void RCC_EanbleLSIClock(bool enable);
/*!
*@}
*/
#endif /* __HAL_RCC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_rtc.h"
/* Initialize RTC. */
void RTC_Init(RTC_Type * RTCx, RTC_Init_Type * init)
{
uint32_t temp = ( (init->ClockFreq / init->CountFreq) - 1u);
RTC_PutPrescalerValue(RTCx, temp);
}
/* Get the current status flags of the RTC module. */
uint32_t RTC_GetStatus(RTC_Type * RTCx)
{
return RTCx->CRL;
}
/* Clear the status flag of the RTC module. */
void RTC_ClearStatus(RTC_Type * RTCx, uint32_t status)
{
RTCx->CRL &= ~status;
}
/* Set the counter hopping frequency, open configration module before put data into RTC register. */
void RTC_PutPrescalerValue(RTC_Type * RTCx, uint32_t div)
{
RTCx->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */
RTCx->PRLH = div >> 16u; /* Setup the upper 16-bit value of prescaler, RTC_PRL[19:0] = (fRTC_CLK / fSC_CLK ) - 1u. */
RTCx->PRLL = div; /* Setup the lower 16-bit value of prescaler. */
RTCx->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */
}
/* Configure the value at which the counter starts counting. */
void RTC_PutCounterValue(RTC_Type * RTCx, uint32_t cnt)
{
RTCx->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */
RTCx->CNTH = cnt >> 16u; /* Setup the upper 16-bit value of counter. */
RTCx->CNTL = cnt; /* Setup the lower 16-bit value of counter. */
RTCx->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */
}
/* Configure alarm clock response time. */
void RTC_PutAlarmValue(RTC_Type * RTCx, uint32_t alarm)
{
RTCx->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */
RTCx->ALRH = alarm >> 16u; /* Setup the upper 16-bit value of alarm counter. */
RTCx->ALRL = alarm; /* Setup the lower 16-bit value of alarm counter. */
RTCx->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */
}
/* Get the current value from counter of RTC module. */
uint32_t RTC_GetCounterValue(RTC_Type * RTCx)
{
return ( (RTCx->CNTH << 16u) | RTCx->CNTL );
}
/* Get the alarm clock response time */
uint32_t RTC_GetAlarmValue(RTC_Type * RTCx)
{
return ( (RTCx->ALRH << 16u) | RTCx->ALRL);
}
/* Enable RTC interrupt of RTC module. */
void RTC_EnableInterrupts(RTC_Type * RTCx, uint32_t interrupts, bool enable)
{
if (enable)
{
RTCx->CRH |= interrupts;
}
else
{
RTCx->CRH &= ~interrupts;
}
}
/* Get the interrupts status flags of the RTC module. */
uint32_t RTC_GetInterruptStatus(RTC_Type * RTCx)
{
return (RTCx->CRL & RTCx->CRH);
}
/* Clear the status of RTC interrupt. */
void RTC_ClearInterruptStatus(RTC_Type * RTCx, uint32_t interrupts)
{
RTCx->CRL &= ~interrupts;
}
/* Judging whether the current year is a leap year, an ordinary leap year or a century leap year. */
bool RTC_JudgeLeapYear(uint16_t years)
{
if (years % 4u == 0u)
{
if (years % 100u == 0u)
{
if (years % 400u == 0u)
{
return true; /* Century leap year. */
}
else
{
return false;
}
}
else
{
return true; /* Ordinary leap year. */
}
}
else
{
return false;
}
}
/* Month correction table, used for calculation of month. */
const uint8_t month_table[12u] = {31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u};
/* Setup initialization time, calculate the year, month, day, hour, minute and second as the total number of seconds. */
void RTC_SetTime(RTC_Type * RTCx, RTC_Time_Type * time)
{
/* Calculate the total number of seconds of the current configuration time. */
uint32_t seccnt = 0u;
/* Calculate the number of seconds from the lowest years to the current setup years. */
for (uint16_t years = time->Lyears; years < time->Years; years++)
{
if ( RTC_JudgeLeapYear(years) )
{
seccnt += 31622400u; /* The number of seconds in leap year is 31622400. */
}
else
{
seccnt += 31536000u; /* The number of seconds in normal year is 31622400. */
}
}
/* Add up the seconds of the previous month. */
time->Months -= 1u; /* The month count starts from 0 instead of 1, so current months - 1. */
for (uint16_t months = 0u; months < time->Months; months++)
{
seccnt += (uint32_t)month_table[months] * 86400u; /* Calculate the number of seconds of months, the total number of seconds in a day is 86400. */
if ( ( RTC_JudgeLeapYear(time->Years) ) && (months == 1u) ) /* The time is in a leap year and february, add the number of seconds in one day. */
{
seccnt += 86400u; /* The number of seconds in day is 86400. */
}
}
/* Add up the seconds of the previous date. */
seccnt += (uint32_t)(time->Days - 1u) * 86400u; /* The day set for initialization is less than 24 hours, which needs to be subtracted by one day. */
seccnt += (uint32_t)(time->Hours) * 3600u; /* There are 3600 seconds in a hour. */
seccnt += (uint32_t)(time->Mins) * 60u; /* There are 60 seconds in a minute. */
seccnt += (time->Secs);
/* Configrate counter value. */
RTC_PutCounterValue(RTCx, seccnt); /* Put data into counter. */
}
/* Calculate the total number of seconds as year, month, day, hour, minute and second.. */
void RTC_CalcTime(RTC_Type * RTCx, RTC_Time_Type * time)
{
uint32_t count = RTC_GetCounterValue(RTCx); /* Get current seconds count. */
/* Calculated in days. */
uint16_t years = time->Lyears;
uint32_t days = count / 86400u;
for (; days >= 365u; days -= 365u)
{
if ( RTC_JudgeLeapYear(years) ) /* Determine whether it is a leap year. */
{
if (days >= 366u)
{
days -= 1u;
}
else
{
break;
}
}
years++;
}
time->Years = years; /* Get current years. */
uint16_t months = 0u;
for (; days >= 28u; days -= 28u)
{
if ( ( true == RTC_JudgeLeapYear(time->Years) ) && (months == 1u) ) /* The time is February of leap year. */
{
if (days >= 29u)
{
days -= 1u;
}
else
{
break;
}
}
else
{
if (days >= month_table[months]) /* Reach the maximum number of days in the current month. */
{
days = days - month_table[months] + 28u;
}
else
{
break;
}
}
months++;
}
time->Months = months + 1u; /* Get current months. */
time->Days = days + 1u; /* Get current days. */
time->Hours = ( count % 86400u) / 3600u; /* Get current hours. */
time->Mins = ((count % 86400u) % 3600u) / 60u; /* Get current minutes. */
time->Secs = ((count % 86400u) % 3600u) % 60u; /* Get current seconds. */
}
/* Setup the alarm response time. */
void RTC_SetAlarm(RTC_Type * RTCx, RTC_Time_Type * time)
{
uint32_t value = RTC_GetCounterValue(RTCx); /* Get the current total number of seconds. */
RTC_PutAlarmValue(RTCx, value + time->AlarmTime); /* Set alarm respond time. */
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_RTC_H__
#define __HAL_RTC_H__
#include "hal_common.h"
#include "hal_rcc.h"
/*!
* @addtogroup RTC
* @{
*/
/*!
* @addtogroup RTC_STATUS
* @{
*/
#define RTC_STATUS_OPERATION RTC_CRL_RTOFF_MASK /*!< Status flag when write operation of RTC register is completed. */
#define RTC_STATUS_SYNC RTC_CRL_RSF_MASK /*!< Status flag when registers synchronized. */
/*!
* @}
*/
/*!
* @addtogroup RTC_INT
* @{
*/
#define RTC_INT_SEC RTC_CRL_SECF_MASK /*!< Interrupt enable when seconds interrupt generation or overflow of prescaler. After the flag is generated, RTC counter + 1. */
#define RTC_INT_ALARM RTC_CRL_ALRF_MASK /*!< Interrupt enable when the alarm interrupt is generated, in other words, the value of the alarm counter is the same as the RTC counter. */
#define RTC_INT_OVERFLOW RTC_CRL_OWF_MASK /*!< Interrupt enable when overflow interrupt generaton or programmable counter overflow. */
/*!
* @}
*/
/*!
* @brief Define the callback function called when the RTC interrupt is done.
*/
typedef void (*RTC_Callback_1_Type)(void *param);
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref RTC_Init() to initialize the RTC module.
*/
typedef struct
{
uint32_t ClockFreq; /*!< Used to calculate the overload value of prescaler, RTC_PRL[19:0] = (ClockFreq / CountFreq) - 1u. */
uint32_t CountFreq; /*!< Used to set the clock hopping frequency of the counter, and the maximum frequency should not exceed 1 second. */
} RTC_Init_Type;
/*!
* @brief This type of structure instance is used to set and get time when set time and get current time.
*/
typedef struct
{
uint8_t Secs; /*!< Specify the clock seconds. */
uint8_t Mins; /*!< Specify the clock minutes. */
uint8_t Hours; /*!< Specify the clock hours. */
uint8_t Days; /*!< Specify the clock days. */
uint8_t Months; /*!< Specify the clock months. */
uint16_t Years; /*!< Specify the clock years. */
uint16_t Lyears; /*!< Specify term of lowest years. */
uint32_t AlarmTime; /*!< Specify the number of seconds that alarm clock will respond. */
} RTC_Time_Type;
/*!
* @brief Initialize the RTC module.
*
* @param RTCx RTC instance.
* @param init Pointer to the initialization structure. See to @ref RTC_Init_Type.
* @return None.
*/
void RTC_Init(RTC_Type * RTCx, RTC_Init_Type * init);
/*!
* @brief Get the current status flags of the RTC module.
*
* @param RTCx RTC instance.
* @return Status flags. See to @ref RTC_STATUS.
*/
uint32_t RTC_GetStatus(RTC_Type * RTCx);
/*!
* @brief Clear the status flags of the RTC module.
*
* @param RTCx RTC instance.
* @param status The mask code of the indicated flags to be clear. See to @ref RTC_STATUS.
* @return None.
*/
void RTC_ClearStatus(RTC_Type * RTCx, uint32_t status);
/*!
* @brief Configure the prescaler reload value.
*
* The value of div determines the hopping frequency of the counter.
* div = (ClockFreq / CountFreq) - 1u, CountFreq is hopping frequency of the counter, the counter jumps once every second at most.
* The counter maximum jumps once every second, so the maximum CountFreq is no more than 1.
*
* @param RTCx RTC instance.
* @param div Data value to be send into the prescaler register.
* @return None.
*/
void RTC_PutPrescalerValue(RTC_Type * RTCx, uint32_t div);
/*!
* @brief Configure the value at which the counter starts counting.
*
* The counter starts counting from value of cnt.
*
* @param RTCx RTC instance.
* @param cnt The value of counter starts counting.
* @return None.
*/
void RTC_PutCounterValue(RTC_Type * RTCx, uint32_t cnt);
/*!
* @brief Configure alarm clock response time.
*
* @param RTCx RTC instance.
* @param alarm Data value to be send into the alarm register.
* @return None.
*/
void RTC_PutAlarmValue(RTC_Type * RTCx, uint32_t alarm);
/*!
* @brief Get the current value from counter.
*
* @param RTCx RTC instance.
* @return The data value from counter.
*/
uint32_t RTC_GetCounterValue(RTC_Type * RTCx);
/*!
* @brief Get the value the alarm clock will respond to.
*
* @param RTCx RTC instance.
* @return The value the alarm clock will respond to.
*/
uint32_t RTC_GetAlarmValue(RTC_Type * RTCx);
/*!
* @brief Enabel interrupt of the RTC module.
*
* @param RTCx RTC instance.
* @param interrupts Interrupt code masks. See to @ref RTC_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void RTC_EnableInterrupts(RTC_Type * RTCx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the RTC module.
*
* @param RTCx RTC instance.
* @return Interrupt status flags. See to @ref RTC_INT.
*/
uint32_t RTC_GetInterruptStatus(RTC_Type * RTCx);
/*!
* @brief Clear the interrupts status flags of the RTC module.
*
* @param RTCx RTC instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared. See to @ref RTC_INT.
* @return None.
*/
void RTC_ClearInterruptStatus(RTC_Type * RTCx, uint32_t interrupts);
/*!
* @brief Setup the initialization time of the RTC module.
*
* Use RTC_PutCounterValue(), calculate the year, month, day, hour, minute and second as the total number of seconds.
*
* @param RTCx RTC instance.
* @param time Pointer to the time structure. See to @ref RTC_Time_Type.
* @return 'true' to set time succeess, 'false' to set time failed.
*/
void RTC_SetTime(RTC_Type * RTCx, RTC_Time_Type * time);
/*!
* @brief Calculate and get current time.
*
* Use RTC_GetCounterValue(), calculate the total number of seconds as year, month, day, hour, minute and second.
*
* @param RTCx RTC instance.
* @param time Pointer to the time structure. See to @ref RTC_Time_Type.
* @return None.
*/
void RTC_CalcTime(RTC_Type * RTCx, RTC_Time_Type * time);
/*!
* @brief Set alarm time of the RTC module.
*
* Use RTC_GetCounterValue() and RTC_PutAlarmValue()
* Get the current total seconds, plus the alarm response time, and put it into the alarm register.
*
* @param RTCx RTC instance.
* @param time Pointer to the time structure. See to @ref RTC_Time_Type.
* @return 'true' to set alarm time succeess, 'false' to set alarm time failed.
*/
void RTC_SetAlarm(RTC_Type * RTCx, RTC_Time_Type * time);
/*!
*@}
*/
#endif /* __HAL_RTC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_spi.h"
void SPI_SetBaudrate(SPI_Type * SPIx, uint32_t src_clk, uint32_t baudrate)
{
uint32_t div = src_clk / baudrate;
if (div < 2u)
{
/* div = 0, 1 is not allowed. */
div = 2u;
}
SPIx->SPBRG = div;
if (div <= 4)
{
/* to support high speed mode. */
SPIx->CCTL |= (SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK);
}
else
{
SPIx->CCTL &= ~(SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK);
}
}
/* SPI peripheral is disabled just after the initialization.
* user needs to call SPI_Enable() before using the module.
*/
void SPI_InitMaster(SPI_Type * SPIx, SPI_Master_Init_Type * init)
{
uint32_t gctl = SPIx->GCTL &~ ( SPI_I2S_GCTL_MODE_MASK
| SPI_I2S_GCTL_RXEN_MASK
| SPI_I2S_GCTL_TXEN_MASK
| SPI_I2S_GCTL_NSS_MASK
| SPI_I2S_GCTL_INTEN_MASK
| SPI_I2S_GCTL_DW832_MASK
);
uint32_t extctl = 0u;
uint32_t cctl = SPIx->CCTL &~ ( SPI_I2S_CCTL_CPHA_MASK
| SPI_I2S_CCTL_CPOL_MASK
| SPI_I2S_CCTL_LSBFE_MASK
| SPI_I2S_CCTL_SPILEN_MASK
);
/* Master. */
gctl |= SPI_I2S_GCTL_MODE_MASK; /* master mode, disable spi, and reset the other bits in CCTL. */
/* XferMode. */
switch (init->XferMode)
{
case SPI_XferMode_RxOnly:
gctl |= SPI_I2S_GCTL_RXEN_MASK;
break;
case SPI_XferMode_TxRx:
gctl |= (SPI_I2S_GCTL_RXEN_MASK | SPI_I2S_GCTL_TXEN_MASK);
break;
default:
break;
}
/* AutoCS. */
if (init->AutoCS)
{
gctl |= SPI_I2S_GCTL_NSS_MASK;
}
/* Interrupts. Always enable the global interrupt. The specific events are controlled by each bits in INTEN register. */
gctl |= SPI_I2S_GCTL_INTEN_MASK;
/* DataWidth. */
if (init->DataWidth == SPI_DataWidth_7b)
{
}
else if (init->DataWidth == SPI_DataWidth_8b)
{
cctl |= SPI_I2S_CCTL_SPILEN_MASK;
}
else
{
gctl |= SPI_I2S_GCTL_DW832_MASK;
extctl = SPI_I2S_EXTCTL_EXTLEN(init->DataWidth);
}
/* CPOL & CPHA. */
cctl |= ( (SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK)
& ((init->PolPha) << SPI_I2S_CCTL_CPHA_SHIFT)
);
/* MSB. */
if (init->LSB)
{
cctl |= SPI_I2S_CCTL_LSBFE_MASK;
}
SPIx->GCTL = gctl;
SPIx->CCTL = cctl;
SPIx->EXTCTL = extctl;
/* BaudRate. */
SPI_SetBaudrate(SPIx, init->ClockFreqHz, init->BaudRate);
}
void SPI_InitSlave(SPI_Type * SPIx, SPI_Slave_Init_Type * init)
{
uint32_t gctl = SPIx->GCTL &~ ( SPI_I2S_GCTL_MODE_MASK
| SPI_I2S_GCTL_RXEN_MASK
| SPI_I2S_GCTL_TXEN_MASK
| SPI_I2S_GCTL_NSS_MASK
| SPI_I2S_GCTL_INTEN_MASK
| SPI_I2S_GCTL_DW832_MASK
);
uint32_t cctl = SPIx->CCTL &~ ( SPI_I2S_CCTL_CPHA_MASK
| SPI_I2S_CCTL_CPOL_MASK
| SPI_I2S_CCTL_LSBFE_MASK
| SPI_I2S_CCTL_SPILEN_MASK
);
uint32_t extctl = 0u;
/* XferMode. */
switch (init->XferMode)
{
case SPI_XferMode_RxOnly:
gctl |= SPI_I2S_GCTL_RXEN_MASK;
break;
case SPI_XferMode_TxRx:
gctl |= (SPI_I2S_GCTL_RXEN_MASK | SPI_I2S_GCTL_TXEN_MASK);
break;
default:
break;
}
/* AutoCS. */
if (init->AutoCS)
{
gctl |= SPI_I2S_GCTL_NSS_MASK;
}
/* Interrupts. Always enable the global interrupt. The specific events are controlled by each bits in INTEN register. */
gctl |= SPI_I2S_GCTL_INTEN_MASK;
/* DataWidth. */
if (init->DataWidth == SPI_DataWidth_7b)
{
}
else if (init->DataWidth == SPI_DataWidth_8b)
{
cctl |= SPI_I2S_CCTL_SPILEN_MASK;
}
else
{
gctl |= SPI_I2S_GCTL_DW832_MASK;
extctl = SPI_I2S_EXTCTL_EXTLEN(init->DataWidth);
}
/* CPOL & CPHA. */
cctl |= ( (SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK)
& ((init->PolPha) << SPI_I2S_CCTL_CPHA_SHIFT)
);
/* MSB. */
if (init->LSB)
{
cctl |= SPI_I2S_CCTL_LSBFE_MASK;
}
SPIx->GCTL = gctl;
SPIx->CCTL = cctl;
SPIx->EXTCTL = extctl;
}
void SPI_Enable(SPI_Type * SPIx, bool enable)
{
if (enable)
{
SPIx->GCTL |= SPI_I2S_GCTL_SPIEN_MASK;
}
else
{
SPIx->GCTL &= ~SPI_I2S_GCTL_SPIEN_MASK;
}
}
uint32_t SPI_GetStatus(SPI_Type * SPIx)
{
return SPIx->CSTAT;
}
void SPI_EnableInterrupts(SPI_Type * SPIx, uint32_t interrupts, bool enable)
{
if (enable)
{
SPIx->INTEN |= interrupts;
}
else
{
SPIx->INTEN &= ~interrupts;
}
}
uint32_t SPI_GetInterruptStatus(SPI_Type * SPIx)
{
return SPIx->INTSTAT;
}
void SPI_ClearInterruptStatus(SPI_Type * SPIx, uint32_t interrupts)
{
SPIx->INTCLR = interrupts;
}
void SPI_PutData(SPI_Type * SPIx, uint32_t data)
{
SPIx->TXREG = data;
}
uint32_t SPI_GetData(SPI_Type * SPIx)
{
return SPIx->RXREG;
}
void SPI_EnableDMA(SPI_Type * SPIx, bool enable)
{
if (enable)
{
SPIx->GCTL |= SPI_I2S_GCTL_DMAMODE_MASK;
}
else
{
SPIx->GCTL &= ~SPI_I2S_GCTL_DMAMODE_MASK;
}
}
uint32_t SPI_GetEnabledInterrupts(SPI_Type * SPIx)
{
return SPIx->INTEN;
}
uint32_t SPI_GetRxDataRegAddr(SPI_Type * SPIx)
{
return (uint32_t)(&(SPIx->RXREG));
}
uint32_t SPI_GetTxDataRegAddr(SPI_Type * SPIx)
{
return (uint32_t)(&(SPIx->TXREG));
}
void SPI_EnableCS(SPI_Type * SPIx, uint32_t cs_mask)
{
SPIx->NSSR = ~(cs_mask);
}
void SPI_SetRxDataNum(SPI_Type * SPIx, uint16_t number)
{
SPIx->RXDNR = number;
}
void SPI_SetPadMux(SPI_Type * SPIx, SPI_PadMux_Type opt)
{
SPIx->GCTL = ( (SPIx->GCTL &~ SPI_I2S_GCTL_PADSEL_MASK)
| SPI_I2S_GCTL_PADSEL(opt)
);
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_SPI_H__
#define __HAL_SPI_H__
#include "hal_common.h"
/*!
* @addtogroup SPI
* @{
*/
/*!
* @brief SPI driver version number.
*/
#define SPI_DRIVER_VERSION 0u /*!< spi_0. */
/*!
* @addtogroup SPI_STATUS
* @{
*/
#define SPI_STATUS_BUSY SPI_I2S_CSTAT_BUSY_MASK /*!< Status flag when SPI is transmitting or receiving. */
#define SPI_STATUS_TX_EMPTY SPI_I2S_CSTAT_TXEPT_MASK /*!< Status flag when SPI transmiter buffer is empty. */
#define SPI_STATUS_RX_DONE SPI_I2S_CSTAT_RXAVL_MASK /*!< Status flag when SPI receiving buffer is with available data. */
#define SPI_STATUS_TX_FULL SPI_I2S_CSTAT_TXFULL_MASK /*!< Status flag when SPI transmiter buffer is full. */
/*!
* @}
*/
/*!
* @addtogroup SPI_INT
* @{
*/
#define SPI_INT_TX_DONE SPI_I2S_INTEN_TXIEN_MASK /*!< Interrupt enable when SPI transmiter buffer has started sending data. */
#define SPI_INT_RX_DONE SPI_I2S_INTEN_RXIEN_MASK /*!< Interrupt enable when SPI receiving buffer is with available data. */
#define SPI_INT_TX_UNDERRUN SPI_I2S_INTEN_UNDERRUNIEN_MASK /*!< Interrupt enable when SPI transmiter transmit empty data. */
#define SPI_INT_RX_OVERRUN SPI_I2S_INTEN_RXOERRIEN_MASK /*!< Interrupt enable when SPI receive data using the full buffer. */
#define SPI_INT_RX_MATCH SPI_I2S_INTEN_RXMATCHIEN_MASK /*!< Interrupt enable when SPI receiving buffer match the width set in RXDNR. */
#define SPI_INT_RX_FULL SPI_I2S_INTEN_RXFULLIEN_MASK /*!< Interrupt enable when SPI receiving buffer is full. */
#define SPI_INT_TX_EMPTY SPI_I2S_INTEN_TXEPTIEN_MASK /*!< Interrupt enable when SPI transmiter buffer is empty. */
/*!
* @}
*/
/*!
* @brief SPI Polarity Phase type.
*/
typedef enum
{
SPI_PolPha_Alt0 = 0u, /*!< CPOL = 0, CPHA = 1, Clock line is low when idle, Data valid when at falling edge */
SPI_PolPha_Alt1 = 1u, /*!< CPOL = 0, CPHA = 0, Clock line is low when idle, Data valid when at rising edge */
SPI_PolPha_Alt2 = 2u, /*!< CPOL = 1, CPHA = 1, Clock line is high when idle, Data valid when at rising edge */
SPI_PolPha_Alt3 = 3u, /*!< CPOL = 1, CPHA = 0, Clock line is high when idle, Data valid when at falling edge */
} SPI_PolPha_Type;
/*!
* @brief SPI data width type.
*/
typedef enum
{
SPI_DataWidth_32b = 0u, /*!< Data Width 32 bits. */
SPI_DataWidth_1b = 1u, /*!< Data Width 1 bits. */
SPI_DataWidth_2b = 2u, /*!< Data Width 2 bits. */
SPI_DataWidth_3b = 3u, /*!< Data Width 3 bits. */
SPI_DataWidth_4b = 4u, /*!< Data Width 4 bits. */
SPI_DataWidth_5b = 5u, /*!< Data Width 5 bits. */
SPI_DataWidth_6b = 6u, /*!< Data Width 6 bits. */
SPI_DataWidth_7b = 7u, /*!< Data Width 7 bits. */
SPI_DataWidth_8b = 8u, /*!< Data Width 8 bits. */
SPI_DataWidth_9b = 9u, /*!< Data Width 9 bits. */
SPI_DataWidth_10b = 10u, /*!< Data Width 10 bits. */
SPI_DataWidth_11b = 11u, /*!< Data Width 11 bits. */
SPI_DataWidth_12b = 12u, /*!< Data Width 12 bits. */
SPI_DataWidth_13b = 13u, /*!< Data Width 13 bits. */
SPI_DataWidth_14b = 14u, /*!< Data Width 14 bits. */
SPI_DataWidth_15b = 15u, /*!< Data Width 15 bits. */
SPI_DataWidth_16b = 16u, /*!< Data Width 16 bits. */
SPI_DataWidth_17b = 17u, /*!< Data Width 17 bits. */
SPI_DataWidth_18b = 18u, /*!< Data Width 18 bits. */
SPI_DataWidth_19b = 19u, /*!< Data Width 19 bits. */
SPI_DataWidth_20b = 20u, /*!< Data Width 20 bits. */
SPI_DataWidth_21b = 21u, /*!< Data Width 21 bits. */
SPI_DataWidth_22b = 22u, /*!< Data Width 22 bits. */
SPI_DataWidth_23b = 23u, /*!< Data Width 23 bits. */
SPI_DataWidth_24b = 24u, /*!< Data Width 24 bits. */
SPI_DataWidth_25b = 25u, /*!< Data Width 25 bits. */
SPI_DataWidth_26b = 26u, /*!< Data Width 26 bits. */
SPI_DataWidth_27b = 27u, /*!< Data Width 27 bits. */
SPI_DataWidth_28b = 28u, /*!< Data Width 28 bits. */
SPI_DataWidth_29b = 29u, /*!< Data Width 29 bits. */
SPI_DataWidth_30b = 30u, /*!< Data Width 30 bits. */
SPI_DataWidth_31b = 31u, /*!< Data Width 31 bits. */
} SPI_DataWidth_Type;
/*!
* @brief Pin mux for SCK, MOSI, NSS, MISO.
*/
typedef enum
{
SPI_PadMux_SCK_MOSI_NSS_MISO = 0u, /*!< Specifies SPI pin mux switcher 0. */
SPI_PadMux_SCK_MOSI_MISO_NSS = 1u, /*!< Specifies SPI pin mux switcher 1. */
SPI_PadMux_SCK_NSS_MOSI_MISO = 2u, /*!< Specifies SPI pin mux switcher 2. */
SPI_PadMux_SCK_NSS_MISO_MOSI = 3u, /*!< Specifies SPI pin mux switcher 3. */
SPI_PadMux_SCK_MISO_MOSI_NSS = 4u, /*!< Specifies SPI pin mux switcher 4. */
SPI_PadMux_SCK_MISO_NSS_MOSI = 5u, /*!< Specifies SPI pin mux switcher 5. */
SPI_PadMux_MOSI_SCK_NSS_MISO = 6u, /*!< Specifies SPI pin mux switcher 6. */
SPI_PadMux_MOSI_SCK_MISO_NSS = 7u, /*!< Specifies SPI pin mux switcher 7. */
SPI_PadMux_MOSI_NSS_SCK_MISO = 8u, /*!< Specifies SPI pin mux switcher 8. */
SPI_PadMux_MOSI_NSS_MISO_SCK = 9u, /*!< Specifies SPI pin mux switcher 9. */
SPI_PadMux_MOSI_MISO_SCK_NSS = 10u, /*!< Specifies SPI pin mux switcher 10. */
SPI_PadMux_MOSI_MISO_NSS_SCK = 11u, /*!< Specifies SPI pin mux switcher 11. */
SPI_PadMux_NSS_SCK_MOSI_MISO = 12u, /*!< Specifies SPI pin mux switcher 12. */
SPI_PadMux_NSS_SCK_MISO_MOSI = 13u, /*!< Specifies SPI pin mux switcher 13. */
SPI_PadMux_NSS_MOSI_SCK_MISO = 14u, /*!< Specifies SPI pin mux switcher 14. */
SPI_PadMux_NSS_MOSI_MISO_SCK = 15u, /*!< Specifies SPI pin mux switcher 15. */
SPI_PadMux_NSS_MISO_SCK_MOSI = 16u, /*!< Specifies SPI pin mux switcher 16. */
SPI_PadMux_NSS_MISO_MOSI_SCK = 17u, /*!< Specifies SPI pin mux switcher 17. */
SPI_PadMux_MISO_SCK_MOSI_NSS = 18u, /*!< Specifies SPI pin mux switcher 18. */
SPI_PadMux_MISO_SCK_NSS_MOSI = 19u, /*!< Specifies SPI pin mux switcher 19. */
SPI_PadMux_MISO_MOSI_SCK_NSS = 20u, /*!< Specifies SPI pin mux switcher 20. */
SPI_PadMux_MISO_MOSI_NSS_SCK = 21u, /*!< Specifies SPI pin mux switcher 21. */
SPI_PadMux_MISO_NSS_SCK_MOSI = 22u, /*!< Specifies SPI pin mux switcher 22. */
SPI_PadMux_MISO_NSS_MOSI_SCK = 23u, /*!< Specifies SPI pin mux switcher 23. */
} SPI_PadMux_Type;
/*!
* @brief SPI xfer mode type.
*/
typedef enum
{
SPI_XferMode_Disabled = 0u, /*!< Disable both Tx and Rx. */
SPI_XferMode_RxOnly = 1u, /*!< Enable Rx only. */
SPI_XferMode_TxRx = 2u, /*!< Enable both Tx and Rx. */
} SPI_XferMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SPI_InitMaster() to initialize the SPI module.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Bus Clock Freq. */
uint32_t BaudRate; /*!< This member configures the UART communication baud rate. */
SPI_PolPha_Type PolPha; /*!< Specifies different communication modes. */
SPI_DataWidth_Type DataWidth; /*!< Specifies the number of bits of data to be transmitted. */
SPI_XferMode_Type XferMode; /*!< Specifies whether the Receive or Transmit mode is enable or not. */
bool AutoCS; /*!< Specifies whether the chip selection signal is controlled by SPI or not. */
bool LSB; /*!< Specifies whether the current state is Thumb or ARM mode. */
} SPI_Master_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SPI_InitSlave() to initialize the SPI module.
*/
typedef struct
{
SPI_PolPha_Type PolPha; /*!< Specifies different communication modes. */
SPI_DataWidth_Type DataWidth; /*!< Specifies the number of bits of data to be transmitted. */
SPI_XferMode_Type XferMode; /*!< Specifies whether the Receive or Transmit mode is enable or not. */
bool AutoCS; /*!< Specifies whether the chip selection signal is controlled by SPI or not. */
bool LSB; /*!< Specifies whether the current state is Thumb or ARM mode. */
} SPI_Slave_Init_Type;
/*!
* @brief Initialize the SPI Master module.
*
* @param SPIx SPI instance.
* @param init Pointer to the initialization structure. See to @ref SPI_Master_Init_Type.
* @return None.
*/
void SPI_InitMaster(SPI_Type * SPIx, SPI_Master_Init_Type * init);
/*!
* @brief Initialize the SPI Slave module.
*
* @param SPIx SPI instance.
* @param init Pointer to the initialization structure. See to @ref SPI_Slave_Init_Type.
* @return None.
*/
void SPI_InitSlave(SPI_Type * SPIx, SPI_Slave_Init_Type * init);
/*!
* @brief Enable the SPI module.
*
* The SPI module should be enabled before sending or receiving data.
*
* @param SPIx SPI instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void SPI_Enable(SPI_Type * SPIx, bool enable);
/*!
* @brief Get the current status flags of the SPI module.
*
* @param SPIx SPI instance.
* @return Status flags. See to @ref SPI_STATUS.
*/
uint32_t SPI_GetStatus(SPI_Type * SPIx);
/*!
* @brief Enable interrupts of the SPI module.
*
* @param SPIx SPI instance.
* @param interrupts Interrupt code masks. See to @ref SPI_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void SPI_EnableInterrupts(SPI_Type * SPIx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the SPI module.
*
* @param SPIx SPI instance.
* @return Interrupt status flags. See to @ref SPI_INT.
*/
uint32_t SPI_GetInterruptStatus(SPI_Type * SPIx);
/*!
* @brief Clear the interrupts status flags of the SPI module.
*
* @param SPIx SPI instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return Interrupt status flags. See to @ref SPI_INT.
*/
void SPI_ClearInterruptStatus(SPI_Type * SPIx, uint32_t interrupts);
/*!
* @brief Put the data into transmiter buffer of the SPI module.
*
* @param SPIx SPI instance.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void SPI_PutData(SPI_Type * SPIx, uint32_t data);
/*!
* @brief Get the data from receiver buffer of the SPI module.
*
* @param SPIx SPI instance.
* @return The data value received from the receiver.
* @return None.
*/
uint32_t SPI_GetData(SPI_Type * SPIx);
/*!
* @brief Enable the DMA trigger from the SPI module.
*
* The DMA trigger events are the same as the intertupts.
*
* @param SPIx SPI instance.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void SPI_EnableDMA(SPI_Type * SPIx, bool enable);
/*!
* @brief Read the current enabled interrupts the SPI module.
*
* @param SPIx SPI instance.
* @return The mask codes enabled interrupts. See to ref@ SPI_INT.
*/
uint32_t SPI_GetEnabledInterrupts(SPI_Type * SPIx);
/*!
* @brief Get the hardware Rx data buffer's address the SPI module.
*
* The return value of the address is most used with DMA module.
*
* @param SPIx SPI instance.
* @return The value of the address for SPI module's hardware Rx data buffer.
*/
uint32_t SPI_GetRxDataRegAddr(SPI_Type * SPIx);
/*!
* @brief Get the hardware Tx data buffer's address the SPI module.
*
* The return value of the address is most used with DMA module.
*
* @param SPIx SPI instance.
* @return The value of the address for SPI module's hardware Tx data buffer.
*/
uint32_t SPI_GetTxDataRegAddr(SPI_Type * SPIx);
/*!
* @brief Enable the SPI CS module.
*
* @param SPIx SPI instance.
* @param cs_mask Code mask of whether the chip selection signal is controlled by SPI
* @return None.
*/
void SPI_EnableCS(SPI_Type * SPIx, uint32_t cs_mask);
/*!
* @brief Set the SPI master read only data length.
*
* @param SPIx SPI instance.
* @param length Data length the rx is expectated to receive.
* @return None.
*/
void SPI_SetRxDataLen(SPI_Type * SPIx, uint16_t length);
/*!
* @brief Set the PAD selection for SPI pins.
*
* @param SPIx SPI instance.
* @param opt SPI pad selection. See to @ref SPI_PadMux_Type.
* @return None.
*/
void SPI_SetPadMux(SPI_Type * SPIx, SPI_PadMux_Type opt);
/*!
*@}
*/
#endif /* __HAL_SPI_H__ */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_syscfg.h"
#define SYSCFG_EXTICR_MASK(x) ( (0x0Fu) << ( ( (uint32_t)(x) & 0x3u ) << 2u ) ) /* mask bit for clear exti line. */
#define SYSCFG_EXTICR(x, y) ( (uint32_t)( (uint32_t)(x) << ( ( (uint32_t)(y) & 0x3u ) << 2u ) ) ) /* set the data for indicated exti port and line. */
// void SYSCFG_SetBootMemMode(SYSCFG_BootMemMode_Type mode)
// {
// SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_MEMMODE_MASK )
// | SYSCFG_CFGR_MEMMODE(mode);
// }
void SYSCFG_SetFSMCPinUseMode(SYSCFG_FSMCPinUseMode_Type mode)
{
SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_FCODATAEN_MASK )
| SYSCFG_CFGR_FCODATAEN(mode);
}
void SYSCFG_SetFSMCMode(SYSCFG_FSMCMode_Type mode)
{
SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_FCMODESEL_MASK )
| SYSCFG_CFGR_FCMODESEL(mode);
}
void SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_Type port, SYSCFG_EXTILine_Type line)
{
if ( line < SYSCFG_EXTILine_4)
{
SYSCFG->EXTICR1 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
else if ( line < SYSCFG_EXTILine_8 )
{
SYSCFG->EXTICR2 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
else if ( line < SYSCFG_EXTILine_12 )
{
SYSCFG->EXTICR3 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
else
{
SYSCFG->EXTICR4 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
}
void SYSCFG_SetI2C0PortMode(SYSCFG_I2CPortMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C1MODESEL_MASK )
| SYSCFG_CFGR2_I2C1MODESEL(mode);
}
void SYSCFG_SetI2C1PortMode(SYSCFG_I2CPortMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C2MODESEL_MASK )
| SYSCFG_CFGR2_I2C2MODESEL(mode);
}
void SYSCFG_SetENETPortMode(SYSCFG_ENETPortMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_ENETMIIRMIISEL_MASK )
| SYSCFG_CFGR2_ENETMIIRMIISEL(mode);
}
void SYSCFG_SetENETSpeedMode(SYSCFG_ENETSpeedMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_ENETSPDSEL_MASK )
| SYSCFG_CFGR2_ENETSPDSEL(mode);
}
void SYSCFG_EnablePVD(SYSCFG_PVDConf_Type * conf)
{
if (conf == NULL)
{
SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_PVDE_MASK;
}
else
{
SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_PVDE_MASK
| SYSCFG_PDETCSR_PLS_MASK
| SYSCFG_PDETCSR_PVDO_MASK
) )
| SYSCFG_PDETCSR_PLS(conf->Thold)
| SYSCFG_PDETCSR_PVDO(conf->Output)
| SYSCFG_PDETCSR_PVDE_MASK
);
}
}
void SYSCFG_EnableVDT(SYSCFG_VDTConf_Type * conf)
{
if (conf == NULL)
{
SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VDTE_MASK;
}
else
{
SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_VDTE_MASK
| SYSCFG_PDETCSR_VDTLS_MASK
| SYSCFG_PDETCSR_VDTO_MASK
) )
| SYSCFG_PDETCSR_VDTLS(conf->Thold)
| SYSCFG_PDETCSR_VDTO(conf->Output)
| SYSCFG_PDETCSR_VDTE_MASK
);
}
}
void SYSCFG_EnableADCCheckVBatDiv3(bool enable)
{
if (enable)
{
SYSCFG->PDETCSR |= SYSCFG_PDETCSR_VBATDIV3EN_MASK;
}
else
{
SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VBATDIV3EN_MASK;
}
}
void SYSCFG_SetVOSDelayValue(uint32_t val)
{
SYSCFG->VOSDLY = val;
}
/* EOF. */

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/*
* Copyright 2022 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_SYSCFG_H__
#define __HAL_SYSCFG_H__
#include "hal_common.h"
/*!
* @addtogroup SYSCFG
* @{
*/
/*!
* @brief Boot memory mapping mode.
*/
typedef enum
{
SYSCFG_BootMemMode_Flash = 0u, /*!< SYSCFG Boot Memory Flash mode. */
SYSCFG_BootMemMode_ROM = 1u, /*!< SYSCFG Boot Memory ROM mode. */
SYSCFG_BootMemMode_SRAM = 3u, /*!< SYSCFG Boot Memory SRAM mode. */
} SYSCFG_BootMemMode_Type;
/*!
* @brief Set FSMC compatible mode.
*/
typedef enum
{
SYSCFG_FSMCMode_NorFlash = 0u, /*!< SYSCFG FSMC compatible with Nor Flash. */
SYSCFG_FSMCMode_8080 = 1u, /*!< SYSCFG FSMC compatible with 8080 protocal. */
} SYSCFG_FSMCMode_Type;
/*!
* @brief FSMC pin usage.
* FSMC pins can be used as data use only or mixed as data use and address use.
*/
typedef enum
{
SYSCFG_FSMCPinUseMode_DataAndAddrMixed = 0u, /*!< FSMC pins can be used mixedly. */
SYSCFG_FSMCPinUseMode_DataOnly = 1u, /*!< FSMC pins can be used for data only. */
} SYSCFG_FSMCPinUseMode_Type;
/*!
* @brief External interrupt port.
*/
typedef enum
{
SYSCFG_EXTIPort_GPIOA = (0x00U), /*!< SYSCFG External Interrupt GPIOA. */
SYSCFG_EXTIPort_GPIOB = (0x01U), /*!< SYSCFG External Interrupt GPIOB. */
SYSCFG_EXTIPort_GPIOC = (0x02U), /*!< SYSCFG External Interrupt GPIOC. */
SYSCFG_EXTIPort_GPIOD = (0x03U), /*!< SYSCFG External Interrupt GPIOD. */
SYSCFG_EXTIPort_GPIOE = (0x04U), /*!< SYSCFG External Interrupt GPIOE. */
SYSCFG_EXTIPort_GPIOF = (0x05U), /*!< SYSCFG External Interrupt GPIOF. */
} SYSCFG_EXTIPort_Type;
/*!
* @brief External interrupt line.
*/
typedef enum
{
SYSCFG_EXTILine_0 = (0x00U), /*!< Pin 0 selected. */
SYSCFG_EXTILine_1 = (0x01U), /*!< Pin 1 selected. */
SYSCFG_EXTILine_2 = (0x02U), /*!< Pin 2 selected. */
SYSCFG_EXTILine_3 = (0x03U), /*!< Pin 3 selected. */
SYSCFG_EXTILine_4 = (0x04U), /*!< Pin 4 selected. */
SYSCFG_EXTILine_5 = (0x05U), /*!< Pin 5 selected. */
SYSCFG_EXTILine_6 = (0x06U), /*!< Pin 6 selected. */
SYSCFG_EXTILine_7 = (0x07U), /*!< Pin 7 selected. */
SYSCFG_EXTILine_8 = (0x08U), /*!< Pin 8 selected. */
SYSCFG_EXTILine_9 = (0x09U), /*!< Pin 9 selected. */
SYSCFG_EXTILine_10 = (0x0AU), /*!< Pin 10 selected. */
SYSCFG_EXTILine_11 = (0x0BU), /*!< Pin 11 selected. */
SYSCFG_EXTILine_12 = (0x0CU), /*!< Pin 12 selected. */
SYSCFG_EXTILine_13 = (0x0DU), /*!< Pin 13 selected. */
SYSCFG_EXTILine_14 = (0x0EU), /*!< Pin 14 selected. */
SYSCFG_EXTILine_15 = (0x0FU), /*!< Pin 15 selected. */
} SYSCFG_EXTILine_Type;
/*!
* @brief I2C port mode.
*/
typedef enum
{
SYSCFG_I2CPortMode_OpenDrain = 0u, /*!< I2C output open-drain mode. */
SYSCFG_I2CPortMode_PushPull = 1u, /*!< I2C output push-pull mode. */
} SYSCFG_I2CPortMode_Type;
/*!
* @brief Ethernet port mode.
*/
typedef enum
{
SYSCFG_ENETPortMode_MII = 0u, /*!< Ethernet connect on MMI port. */
SYSCFG_ENETPortMode_RMII = 1u, /*!< Ethernet connect on RMMI port. */
} SYSCFG_ENETPortMode_Type;
/*!
* @brief Ethernet speed mode.
*/
typedef enum
{
SYSCFG_ENETSpeedMode_10Mb = 0u, /*!< Ethernet speed mode of 10 Mbps. */
SYSCFG_ENETSpeedMode_100Mb = 1u, /*!< Ethernet speed mode of 100 Mbps. */
} SYSCFG_ENETSpeedMode_Type;
/*!
* @brief PVD threshold.
*/
typedef enum
{
SYSCFG_PVDThold_1v8 = 0u, /*!< PVD threshold of 1.8 v.*/
SYSCFG_PVDThold_2v1 = 1u, /*!< PVD threshold of 2.1 v.*/
SYSCFG_PVDThold_2v4 = 2u, /*!< PVD threshold of 2.4 v.*/
SYSCFG_PVDThold_2v7 = 3u, /*!< PVD threshold of 2.7 v.*/
SYSCFG_PVDThold_3v0 = 4u, /*!< PVD threshold of 3.0 v.*/
SYSCFG_PVDThold_3v3 = 5u, /*!< PVD threshold of 3.3 v.*/
SYSCFG_PVDThold_3v6 = 6u, /*!< PVD threshold of 3.6 v.*/
SYSCFG_PVDThold_3v9 = 7u, /*!< PVD threshold of 3.9 v.*/
SYSCFG_PVDThold_4v2 = 8u, /*!< PVD threshold of 4.2 v.*/
SYSCFG_PVDThold_4v5 = 9u, /*!< PVD threshold of 4.5 v.*/
SYSCFG_PVDThold_4v8 = 10u, /*!< PVD threshold of 4.8 v.*/
} SYSCFG_PVDThold_Type;
/*!
* @brief PVD output state.
*/
typedef enum
{
SYSCFG_PVDOut_Low = 0u, /*!< PVD output low.*/
SYSCFG_PVDOut_High = 1u, /*!< PVD output high.*/
} SYSCFG_PVDOut_Type;
/*!
* @brief VDT threshold alt.
*/
typedef enum
{
SYSCFG_VDTThold_1v2 = 0u, /*!< VDT threshold of 1.2 v.*/
SYSCFG_VDTThold_1v1 = 1u, /*!< VDT threshold of 1.1 v.*/
SYSCFG_VDTThold_1v0 = 2u, /*!< VDT threshold of 1.0 v.*/
SYSCFG_VDTThold_0v9 = 3u, /*!< VDT threshold of 0.9 v.*/
} SYSCFG_VDTThold_Type;
/*!
* @brief VDT output state.
*/
typedef enum
{
SYSCFG_VDTOut_Low = 0u, /*!< VDT output low.*/
SYSCFG_VDTOut_High = 1u, /*!< VDT output high.*/
} SYSCFG_VDTOut_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SYSCFG_EnablePVD().
*/
typedef struct
{
SYSCFG_PVDThold_Type Thold; /* Set the threshold of the PVD. */
SYSCFG_PVDOut_Type Output; /* Set the output of the PVD. */
} SYSCFG_PVDConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SYSCFG_EnableVDT().
*/
typedef struct
{
SYSCFG_VDTThold_Type Thold; /* Set the threshold of the VDT. */
SYSCFG_VDTOut_Type Output; /* Set the output of the VDT. */
} SYSCFG_VDTConf_Type;
/*!
* @brief Set boot memory mode.
*
* @param mode The memory mode. See to @ref SYSCFG_BootMemMode_Type.
* @return None.
*/
void SYSCFG_SetBootMemMode(SYSCFG_BootMemMode_Type mode);
/*!
* @brief Set FSMC pin usage mode.
*
* @param mode FMSC pin use mode to be set. See to @ref SYSCFG_FSMCPinUseMode_Type.
* @return None.
*/
void SYSCFG_SetFSMCPinUseMode(SYSCFG_FSMCPinUseMode_Type mode);
/*!
* @brief Set the FMSC compatible mode.
*
* @param mode The compatible mode to be set for FMSC. See to @ref SYSCFG_FSMCMode_Type.
* @return None.
*/
void SYSCFG_SetFSMCMode(SYSCFG_FSMCMode_Type mode);
/*!
* @brief Set the external interrupt mux.
*
* @param port external interrupt port. See to @ref SYSCFG_EXTIPort_Type.
* @param line external interrupt line. See to @ref SYSCFG_EXTILine_Type.
* @return None.
*/
void SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_Type port, SYSCFG_EXTILine_Type line);
/*!
* @brief Set the I2C port 0 mode.
*
* @param mode The I2C output state to be set. See to @ref SYSCFG_I2CPortMode_Type.
* @return None.
*/
void SYSCFG_SetI2C0PortMode(SYSCFG_I2CPortMode_Type mode);
/*!
* @brief Set the I2C port 1 mode.
*
* @param mode The I2C output state to be set. See to @ref SYSCFG_I2CPortMode_Type.
* @return None.
*/
void SYSCFG_SetI2C1PortMode(SYSCFG_I2CPortMode_Type mode);
/*!
* @brief Set the Ethernet port mode.
*
* @param mode The Ethernet port mode. See to @ref SYSCFG_ENETPortMode_Type.
* @return None.
*/
void SYSCFG_SetENETPortMode(SYSCFG_ENETPortMode_Type mode);
/*!
* @brief Set the Ethernet speed mode.
*
* @param mode The Ethernet speed mode. See to @ref SYSCFG_ENETSpeedMode_Type.
* @return None.
*/
void SYSCFG_SetENETSpeedMode(SYSCFG_ENETSpeedMode_Type mode);
/*!
* @brief Enable the PVD.
*
* @param conf Pointer to the PDV configuration structure. See to @ref SYSCFG_PVDConf_Type.
* @return None.
*/
void SYSCFG_EnablePVD(SYSCFG_PVDConf_Type * conf);
/*!
* @brief Enable the VDT.
*
* @param conf Pointer to the VDT configuration structure. See to @ref SYSCFG_VDTConf_Type.
* @return None.
*/
void SYSCFG_EnableVDT(SYSCFG_VDTConf_Type * conf);
/*!
* @brief Enable ADC checking VBat_Div3.
*
* @param enable 'true' to enable ADC checking, 'false' to disable ADC checking.
* @return None.
*/
void SYSCFG_EnableADCCheckVBatDiv3(bool enable);
/*!
* @brief Set the VOS delay time.
*
* @param time VOS delay time.
* @return None.
*/
void SYSCFG_SetVOSDelayValue(uint32_t val);
/*!
* @}
*/
#endif /* __HAL_SYSCFG_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_tim.h"
bool TIM_Init(TIM_Type * TIMx, TIM_Init_Type * init)
{
uint32_t cr1 = TIMx->CR1 &~ ( TIM_CR1_OPM_MASK
| TIM_CR1_ARPE_MASK
| TIM_CR1_CMS_MASK
| TIM_CR1_DIR_MASK
);
cr1 |= TIM_CR1_OPM(init->PeriodMode);
cr1 |= ((init->EnablePreloadPeriod) ? TIM_CR1_ARPE_MASK: 0u);
TIMx->CR1 = cr1;
/* Check the vadility of StepFreqHz. */
if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) )
{
return false;
}
switch (init->CountMode)
{
case TIM_CountMode_Increasing:
break;
case TIM_CountMode_Decreasing:
cr1 |= TIM_CR1_DIR_MASK;
break;
case TIM_CountMode_CenterAligned1:
cr1 |= TIM_CR1_CMS(1u);
break;
case TIM_CountMode_CenterAligned2:
cr1 |= TIM_CR1_CMS(2u);
break;
case TIM_CountMode_CenterAligned3:
cr1 |= TIM_CR1_CMS(3u);
break;
default:
break;
}
/* Calculate the prescaler. */
TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u;
TIMx->ARR = init->Period;
return true;
}
void TIM_Start(TIM_Type * TIMx)
{
TIMx->CR1 |= TIM_CR1_CEN_MASK;
}
void TIM_Stop(TIM_Type * TIMx)
{
TIMx->CR1 &= ~TIM_CR1_CEN_MASK;
}
uint32_t TIM_GetCounterValue(TIM_Type * TIMx)
{
return TIMx->CNT;
}
void TIM_ClearCounterValue(TIM_Type * TIMx)
{
TIMx->CNT = 0u;
}
void TIM_EnableInterrupts(TIM_Type * TIMx, uint32_t interrupts, bool enable)
{
if (enable)
{
TIMx->DIER |= interrupts;
}
else
{
TIMx->DIER &= ~interrupts;
}
}
void TIM_EnableDMA(TIM_Type * TIMx, uint32_t dmas, bool enable)
{
if (enable)
{
TIMx->DIER |= dmas;
}
else
{
TIMx->DIER &= ~dmas;
}
}
void TIM_DoSwTrigger(TIM_Type * TIMx, uint32_t swtrgs)
{
TIMx->EGR = swtrgs;
}
uint32_t TIM_GetInterruptStatus(TIM_Type * TIMx)
{
return TIMx->SR;
}
void TIM_ClearInterruptStatus(TIM_Type * TIMx, uint32_t status)
{
TIMx->SR &= ~status;
}
/*******************************/
static void _TIM_WriteChannelCtrlReg(TIM_Type * TIMx, uint32_t channel, uint32_t regval)
{
switch (channel)
{
case TIM_CHN_1:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_CHN_2:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
case TIM_CHN_3:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_CHN_4:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
case TIM_CHN_5:
TIMx->CCMR3 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF);
break;
default:
break;
}
}
void TIM_EnableOutputCompare(TIM_Type * TIMx, uint32_t channel, TIM_OutputCompareConf_Type * conf)
{
uint32_t regval = TIM_CCMR1_CC1S(TIM_ChannelIOMode_Out) /* output compare mode. */
| ( (conf->EnableFastOutput) ? TIM_CCMR1_OC1FE_MASK : 0u ) /* fast output. */
| ( (conf->EnablePreLoadChannelValue) ? TIM_CCMR1_OC1PE_MASK : 0u) /* preload of channel value. */
| TIM_CCMR1_OC1M(conf->RefOutMode) /* output compare comparison mode. */
| ( (conf->ClearRefOutOnExtTrigger) ? TIM_CCMR1_OC1CE_MASK : 0u) /* external trigger clear ref. */
;
_TIM_WriteChannelCtrlReg(TIMx, channel, regval);
TIM_PutChannelValue(TIMx, channel, conf->ChannelValue);
switch (conf->PinPolarity)
{
case TIM_PinPolarity_Disabled:
TIMx->CCER &= ~( ( TIM_CCER_CC1E_MASK
| TIM_CCER_CC1NE_MASK
) << (channel<<2u) ); /* Disable both channel. */
break;
case TIM_PinPolarity_Rising:
TIMx->CCER = ( ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| ( ( TIM_CCER_CC1E_MASK ) /* Enable the pin output / input. */
) << (channel<<2u));
break;
case TIM_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input. */
| TIM_CCER_CC1P_MASK /* Set output active polarity. */
) << (channel<<2u));
break;
default:
break;
}
}
void TIM_EnableCompOutput(TIM_Type * TIMx, uint32_t channel, bool enable)
{
if (enable)
{
switch (channel)
{
case TIM_CHN_1:
TIMx->CCER |= TIM_CCER_CC1NE_MASK;
break;
case TIM_CHN_2:
TIMx->CCER |= TIM_CCER_CC2NE_MASK;
break;
case TIM_CHN_3:
TIMx->CCER |= TIM_CCER_CC3NE_MASK;
break;
case TIM_CHN_4:
TIMx->CCER |= TIM_CCER_CC4NE_MASK;
break;
default:
break;
}
}
else
{
switch (channel)
{
case TIM_CHN_1:
TIMx->CCER &= ~ TIM_CCER_CC1NE_MASK;
break;
case TIM_CHN_2:
TIMx->CCER &= ~ TIM_CCER_CC2NE_MASK;
break;
case TIM_CHN_3:
TIMx->CCER &= ~ TIM_CCER_CC3NE_MASK;
break;
case TIM_CHN_4:
TIMx->CCER &= ~ TIM_CCER_CC4NE_MASK;
break;
default:
break;
}
}
}
/* for some TIM instance, there is an additional switch to let the output signal go.
* in this case, the output is disabled by default. then, only the switch is enabled, the output signal can go.
*/
void TIM_EnableOutputCompareSwitch(TIM_Type * TIMx, bool enable)
{
if (enable)
{
TIMx->BDTR |= TIM_BDTR_MOE_MASK;
}
else
{
TIMx->BDTR &= ~ TIM_BDTR_MOE_MASK;
}
}
void TIM_EnableInputCapture(TIM_Type * TIMx, uint32_t channel, TIM_InputCaptureConf_Type * conf)
{
uint32_t regval = TIM_CCMR1_CC1S(TIM_ChannelIOMode_In) /* input capture mode. */
| TIM_CCMR1_IC1PSC(conf->InDiv)
| TIM_CCMR1_IC1F(conf->InFilter)
;
_TIM_WriteChannelCtrlReg(TIMx, channel, regval);
switch (conf->PinPolarity)
{
case TIM_PinPolarity_Disabled:
TIMx->CCER &= ~(TIM_CCER_CC1E_MASK << (channel<<2u));
break;
case TIM_PinPolarity_Rising:
TIMx->CCER = (TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */
) << (channel<<2u) );
break;
case TIM_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_CCER_CC1P_MASK /* Set active input edge. */
) << (channel<<2u) );
break;
case TIM_PinPolarity_RisingOrFalling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_CCER_CC1P_MASK /* Set active input edge. */
| TIM_CCER_CC1NP_MASK
) << (channel<<2u) );
break;
default:
break;
}
}
uint32_t TIM_GetChannelValue(TIM_Type * TIMx, uint32_t channel)
{
return TIMx->CCR[channel];
}
void TIM_PutChannelValue(TIM_Type * TIMx, uint32_t channel, uint32_t value)
{
if ( channel == TIM_CHN_5 )
{
TIMx->CCR5 = value;
}
else
{
TIMx->CCR[channel] = value;
}
}
void TIM_SetClockDiv(TIM_Type * TIMx, TIM_ClockDiv_Type div)
{
TIMx->CR1 = ( TIMx->CR1 &~ TIM_CR1_CKD_MASK )
| ( TIM_CR1_CKD(div) ); /* set the frequncy ratio. */
}
void TIM_EnableDeadPeriod(TIM_Type * TIMx, TIM_DeadPeriodConf_Type * conf)
{
TIMx->BDTR = ( TIMx->BDTR &~ TIM_BDTR_DTG_MASK )
| ( TIM_BDTR_DTG(conf->DeadPeriodCoef) ); /* set the coefficient. */
}
void TIM_EnableMasterMode(TIM_Type * TIMx, TIM_MasterModeConf_Type * conf)
{
TIMx->CR2 = ( TIMx->CR2 &~ TIM_CR2_MMS_MASK )
| ( TIM_CR2_MMS(conf->Out) ); /* Set master mode output. */
uint32_t smcr = TIMx->SMCR &~ TIM_SMCR_MSM_MASK;
if (conf->EnableSync) /* synchronize with slave timers. */
{
smcr |= TIM_SMCR_MSM_MASK;
}
TIMx->SMCR = smcr;
}
void TIM_EnableSlaveMode(TIM_Type * TIMx, TIM_SlaveModeConf_Type * conf)
{
if ( conf->Resp != TIM_SlaveResp_Disabled )
{
TIMx->SMCR = ( TIMx->SMCR &~ ( TIM_SMCR_TS_MASK
| TIM_SMCR_SMS_MASK
) )
| TIM_SMCR_TS(conf->In) /* set input trigger source. */
| TIM_SMCR_SMS(conf->Resp); /* set response to the source */
}
else
{
TIMx->SMCR &= ~ TIM_SMCR_SMS_MASK;
}
}
void TIM_EnableExtTriggerIn(TIM_Type * TIMx, TIM_ExtTriggerInConf_Type * conf)
{
uint32_t smcr = TIMx->SMCR &~ ( TIM_SMCR_ETPS_MASK
| TIM_SMCR_ETF_MASK
| TIM_SMCR_ECE_MASK
| TIM_SMCR_ETP_MASK
);
switch (conf->PinPolarity)
{
case TIM_PinPolarity_Disabled:
break;
case TIM_PinPolarity_Rising:
smcr |= TIM_SMCR_ECE_MASK; /* enable external trigger input. */
break;
case TIM_PinPolarity_Falling:
smcr |= TIM_SMCR_ETP_MASK; /* falling edge active. */
smcr |= TIM_SMCR_ECE_MASK; /* enable external trigger input. */
break;
default:
break;
}
smcr |= TIM_SMCR_ETPS( conf->InDiv ); /* division to the input external trigger. */
smcr |= TIM_SMCR_ETF( conf->InFilter ); /* set filter. */
TIMx->SMCR = smcr;
}
uint32_t TIM_EnableDMABurst(TIM_Type * TIMx, TIM_DMABurstConf_Type * conf)
{
TIMx->DCR = TIM_DCR_DBA(conf->BaseAddr) | TIM_DCR_DBL(conf->Length);
return (uint32_t)(&(TIMx->DMAR));
}
TIM_EncoderDirection_Type TIM_GetEncoder(TIM_Type * TIMx, uint32_t * value)
{
if (value)
{
* value = TIM_GetCounterValue(TIMx);
}
if ( (TIMx->CR1 & TIM_CR1_DIR_MASK) != 0u )
{
return TIM_EncoderDirection_Backward;
}
else
{
return TIM_EncoderDirection_Forward;
}
}
void TIM_SetRepCounter(TIM_Type * TIMx, uint8_t value)
{
TIMx->RCR = TIM_RCR_REP(value);
}
uint8_t TIM_GetRepCounterValue(TIM_Type * TIMx)
{
return TIMx->RCR >> TIM_RCR_REPCNT_SHIFT;
}
void TIM_EnableIdleOut(TIM_Type * TIMx, uint32_t channel, TIM_IdleOut_Type * conf)
{
uint32_t cr2 = TIMx->CR2 & ~ ( ( TIM_CR2_OIS1_MASK
| TIM_CR2_OIS1N_MASK
) << ( channel << 1u )
);
if ( conf->PinPolarity == TIM_PinPolarity_Rising )
{
cr2 |= ( TIM_CR2_OIS1_MASK << ( channel << 1u ) );
}
if ( conf->CompPinPolarity == TIM_PinPolarity_Rising )
{
cr2 |= ( TIM_CR2_OIS1N_MASK << ( channel << 1u ) );
}
TIMx->CR2 = cr2;
}
void TIM_EnableLock(TIM_Type * TIMx, TIM_LockLevel_Type lock)
{
TIMx->BDTR = ( TIMx->BDTR & ~ TIM_BDTR_LOCK_MASK )
| TIM_BDTR_LOCK(lock);
}
void TIM_EnableBreakIn(TIM_Type * TIMx, TIM_BreakIn_Type * conf)
{
uint32_t bdtr = TIMx->BDTR &~ ( TIM_BDTR_BKE_MASK
| TIM_BDTR_BKP_MASK
| TIM_BDTR_AOE_MASK
| TIM_BDTR_DOE_MASK
);
uint32_t bkinf = 0u;
switch (conf->PinPolarity)
{
case TIM_PinPolarity_Disabled:
break;
case TIM_PinPolarity_Rising:
bdtr |= ( TIM_BDTR_BKE_MASK
| TIM_BDTR_BKP_MASK
| ( conf->AutoSwitchOutput ? TIM_BDTR_AOE_MASK : 0u )
| ( conf->DirectIdleOutput ? TIM_BDTR_DOE_MASK : 0u )
);
break;
case TIM_PinPolarity_Falling:
bdtr |= ( TIM_BDTR_BKE_MASK
| ( conf->AutoSwitchOutput ? TIM_BDTR_AOE_MASK : 0u )
| ( conf->DirectIdleOutput ? TIM_BDTR_DOE_MASK : 0u )
);
break;
default:
break;
}
if ( conf->Filter != TIM_BreakInFilter_Disabled )
{
bkinf |= ( TIM_BKINF_BKINFE_MASK | TIM_BKINF_BKINF(conf->Filter) );
}
bkinf |= conf->Source;
TIMx->BKINF = bkinf;
}
void TIM_EnablePWMShift(TIM_Type * TIMx, uint32_t channel, uint16_t value)
{
if ( value == TIM_GetChannelValue(TIMx, channel) )
{
TIMx->PDER &= ~( TIM_PDER_CCR1SHIFTEN_MASK << channel );
}
else
{
TIMx->PDER |= ( TIM_PDER_CCR1SHIFTEN_MASK << channel );
TIMx->CCRFALL[channel] = value;
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_TIM_H__
#define __HAL_TIM_H__
#include "hal_common.h"
/*!
* @addtogroup TIM
* @{
*/
/*!
* @brief TIM driver version number.
*/
#define TIM_DRIVER_VERSION 1u /*!< TIM_1. */
/*!
* @addtogroup TIM_CHANNEL_SELECTION
* @{
*/
#define TIM_CHN_NUM (5u) /*!< The total number of TIM channel. */
#define TIM_CHN_1 (0u) /*!< The selection of TIM Channel 1. */
#define TIM_CHN_2 (1u) /*!< The selection of TIM Channel 2. */
#define TIM_CHN_3 (2u) /*!< The selection of TIM Channel 3. */
#define TIM_CHN_4 (3u) /*!< The selection of TIM Channel 4. */
#define TIM_CHN_5 (4u) /*!< The selection of TIM Channel 5. */
/*!
*@}
*/
/*!
* @addtogroup TIM_INT
* @brief Enable interrupt.
* @{
*/
#define TIM_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */
#define TIM_INT_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt switchers. */
#define TIM_INT_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt switchers. */
#define TIM_INT_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt switchers. */
#define TIM_INT_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt switchers. */
#define TIM_INT_COMP_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt switchers. */
#define TIM_INT_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt switchers. */
#define TIM_INT_BREAK_EVENT (1u << 7u) /*!< Break event interrupt switchers. */
#define TIM_INT_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_DMA
* @brief Enable DMA.
* @{
*/
#define TIM_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period DMA switchers. */
#define TIM_DMA_CHN1_EVENT (1u << 9u) /*!< Channel 1 event for output compare or input capture DMA switchers. */
#define TIM_DMA_CHN2_EVENT (1u << 10u) /*!< Channel 2 event for output compare or input capture DMA switchers. */
#define TIM_DMA_CHN3_EVENT (1u << 11u) /*!< Channel 3 event for output compare or input capture DMA switchers. */
#define TIM_DMA_CHN4_EVENT (1u << 12u) /*!< Channel 4 event for output compare or input capture DMA switchers. */
#define TIM_DMA_COMP_EVENT (1u << 13u) /*!< Channel complementary pwm commutation interrupt switchers. */
#define TIM_DMA_TRGOUT_EVENT (1u << 14u) /*!< Trigger out event DMA switchers. */
#define TIM_DMA_CHN5_EVENT (1u << 17u) /*!< Channel 5 event for output compare or input capture DMA switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_INT_STATUS
* @brief Check interrupt status.
* @{
*/
#define TIM_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */
#define TIM_STATUS_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt flag. */
#define TIM_STATUS_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt flag. */
#define TIM_STATUS_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt flag. */
#define TIM_STATUS_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt flag. */
#define TIM_STATUS_COMP_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt flag. */
#define TIM_STATUS_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt flag. */
#define TIM_STATUS_BREAK_EVENT (1u << 7u) /*!< Break event interrupt flag. */
#define TIM_STATUS_CHN1_OVER_EVENT (1u << 9u) /*!< Channel 1 event for output overcompare or input overcapture interrupt flag. */
#define TIM_STATUS_CHN2_OVER_EVENT (1u << 10u) /*!< Channel 2 event for output overcompare or input overcapture interrupt flag. */
#define TIM_STATUS_CHN3_OVER_EVENT (1u << 11u) /*!< Channel 3 event for output overcompare or input overcapture interrupt flag. */
#define TIM_STATUS_CHN4_OVER_EVENT (1u << 12u) /*!< Channel 4 event for output overcompare or input overcapture interrupt flag. */
#define TIM_STATUS_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt flag. */
/*!
* @}
*/
/*!
* @addtogroup TIM_SWTRG
* @brief Events to be triggered by software.
* @{
*/
#define TIM_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period software trigger. */
#define TIM_SWTRG_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture software trigger. */
#define TIM_SWTRG_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture software trigger. */
#define TIM_SWTRG_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture software trigger. */
#define TIM_SWTRG_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture software trigger. */
#define TIM_SWTRG_COMP_EVENT (1u << 5u) /*!< Channel complementary pwm commutation software trigger. */
#define TIM_SWTRG_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event software trigger. */
#define TIM_SWTRG_BREAK_EVENT (1u << 7u) /*!< Break event software trigger. */
#define TIM_SWTRG_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture software trigger. */
/*!
* @}
*/
/*!
* @addtogroup TIM_BKEAK_IN
* @brief Enable interrupt.
* @{
*/
#define TIM_BKEAK_IN_MASK0 (1u << 5u) /*!< TIM ADV break in source mask 0. */
#define TIM_BKEAK_IN_MASK1 (1u << 6u) /*!< TIM ADV break in source mask 1. */
#define TIM_BKEAK_IN_MASK2 (1u << 7u) /*!< TIM ADV break in source mask 2. */
#define TIM_BKEAK_IN_MASK3 (1u << 8u) /*!< TIM ADV break in source mask 3. */
#define TIM_BKEAK_IN_MASK4 (1u << 9u) /*!< TIM ADV break in source mask 4. */
#define TIM_BKEAK_IN_MASK5 (1u << 10u) /*!< TIM ADV break in source mask 5. */
#define TIM_BKEAK_IN_MASK6 (1u << 11u) /*!< TIM ADV break in source mask 6. */
#define TIM_BKEAK_IN_MASK7 (1u << 13u) /*!< TIM ADV break in source mask 7. */
#define TIM_BKEAK_IN_MASK8 (1u << 13u) /*!< TIM ADV break in source mask 8. */
#define TIM_BKEAK_IN_MASK9 (1u << 14u) /*!< TIM ADV break in source mask 9. */
#define TIM_BKEAK_IN_MASK10 (1u << 15u) /*!< TIM ADV break in source mask 10. */
#define TIM_BKEAK_IN_MASK11 (1u << 16u) /*!< TIM ADV break in source mask 11. */
/*!
* @}
*/
/*!
* @brief Counter period working mode.
*/
typedef enum
{
TIM_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */
TIM_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */
} TIM_PeriodMode_Type;
/*!
* @brief Counter count direction.
*/
typedef enum
{
TIM_CountMode_Increasing = 0u, /*!< Counter counts incrementally from 0 to period and generates an update. */
TIM_CountMode_Decreasing = 1u, /*!< Counter counts decrementally from period to 0 and generates an update. */
TIM_CountMode_CenterAligned1 = 2u, /*!< Counter counts center-aligned from 0 to period - 1 then from period to 0 and generates an update. */
TIM_CountMode_CenterAligned2 = 3u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0. */
TIM_CountMode_CenterAligned3 = 4u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0 and generates another update. */
} TIM_CountMode_Type;
/*!
* @brief TIM output compare reference polairty event.
*/
typedef enum
{
TIM_OutputCompareRefOut_None = 0u, /*!< Reference will not be changed. */
TIM_OutputCompareRefOut_HighOnMatch = 1u, /*!< Reference will be high when counter value equals channel value. */
TIM_OutputCompareRefOut_LowOnMatch = 2u, /*!< Reference will be low when counter value equals channel value. */
TIM_OutputCompareRefOut_ToggleOnMatch = 3u, /*!< Reference will toggle. */
TIM_OutputCompareRefOut_LowAlways = 4u, /*!< Reference will always be low. */
TIM_OutputCompareRefOut_HighAlways = 5u, /*!< Reference will always be high. */
TIM_OutputCompareRefOut_FallingEdgeOnMatch = 6u, /*!< PWM mode 1. */
TIM_OutputCompareRefOut_RisingEdgeOnMatch = 7u, /*!< PWM mode 2. */
} TIM_OutputCompareRefOut_Type;
/*!
* @brief TIM input capture active edge selection and output compare active polarity selection.
* | conf | TIM_PinPolarity_Rising | TIM_PinPolarity_Falling |
* | ----------------------- | -------------------------- | --------------------------- |
* | input capture | detects rising edge | detects falling edge |
* | output compare | high polarity is active | low polarity is active |
* | encoder mode | input remains | input reverses |
* | output under idle state | output high polarity | output low polarity |
*/
typedef enum
{
TIM_PinPolarity_Disabled = 0u, /*!< Disable channel. */
TIM_PinPolarity_Rising = 1u, /*!< See the table above. */
TIM_PinPolarity_Falling = 2u, /*!< See the table above.*/
TIM_PinPolarity_RisingOrFalling = 3u, /*!< For input capture, detect both the rising and falling edge. */
}TIM_PinPolarity_Type;
/*!
* @brief TIM Input active times to evoke capture.
*/
typedef enum
{
TIM_InputCaptureInDiv_OnEach1Capture = 0u, /*!< Every input call capture. */
TIM_InputCaptureInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_InputCaptureInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_InputCaptureInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_InputCaptureInDiv_Type;
/*!
* @brief TIM Input sampling filter.
*/
typedef enum
{
TIM_InputCaptureInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_InputCaptureInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_InputCaptureInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_InputCaptureInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_InputCaptureInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_InputCaptureInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_InputCaptureInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_InputCaptureInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_InputCaptureInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_InputCaptureInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_InputCaptureInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_InputCaptureInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_InputCaptureInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_InputCaptureInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_InputCaptureInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_InputCaptureInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_InputCaptureInFilter_Type;
/*!
* @brief TIM channel IO mode.
*/
typedef enum
{
TIM_ChannelIOMode_Alt0 = 0u, /*!< Channel output. */
TIM_ChannelIOMode_Alt1 = 1u, /*!< Channel input, capture signal from direct channel. */
TIM_ChannelIOMode_Alt2 = 2u, /*!< Channel input, capture signal from indirect channel. */
TIM_ChannelIOMode_Alt3 = 3u, /*!< Channel input, capture signal from trc. */
TIM_ChannelIOMode_Out = TIM_ChannelIOMode_Alt0, /*!< Channel output. */
TIM_ChannelIOMode_In = TIM_ChannelIOMode_Alt1, /*!< Channel input, capture signal from direct channel. */
} TIM_ChannelIOMode_Type;
/*!
* @brief TIM external trigger input active edge selection.
*/
typedef enum
{
TIM_ExtTriggerPinPolarity_Disabled = 0u, /*!< Disable external trigger input. */
TIM_ExtTriggerPinPolarity_Rising = 1u, /*!< Detect the rising edge from external trigger. */
TIM_ExtTriggerPinPolarity_Falling = 2u, /*!< Detect the falling edge from external trigger. */
}TIM_ExtTriggerPinPolarity_Type;
/*!
* @brief TIM external trigger active input times to drive counter.
*/
typedef enum
{
TIM_ExtTriggerInDiv_OnEach1Capture = 0u, /*!< Every input call capture. */
TIM_ExtTriggerInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_ExtTriggerInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_ExtTriggerInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_ExtTriggerInDiv_Type;
/*!
* @brief TIM external trigger sampling filter.
*/
typedef enum
{
TIM_ExtTriggerInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_ExtTriggerInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_ExtTriggerInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_ExtTriggerInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_ExtTriggerInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_ExtTriggerInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_ExtTriggerInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_ExtTriggerInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_ExtTriggerInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_ExtTriggerInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_ExtTriggerInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_ExtTriggerInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_ExtTriggerInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_ExtTriggerInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_ExtTriggerInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_ExtTriggerInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_ExtTriggerInFilter_Type;
/*!
* @brief TIM Dead area / ETR / TI time step length during sampling.
*/
typedef enum
{
TIM_ClockDiv_Alt0 = 0u, /*!< Dead area / ETR / TI step = clock source step. */
TIM_ClockDiv_Alt1 = 1u, /*!< Dead area / ETR / TI step = 2 * clock source step. */
TIM_ClockDiv_Alt2 = 2u, /*!< Dead area / ETR / TI step = 4 * clock source step. */
} TIM_ClockDiv_Type;
/*!
* @brief TIM master mode output signal source.
*/
typedef enum
{
TIM_MasterOut_Alt0 = 0u, /*!< Software update period trigger signal works as master output. */
TIM_MasterOut_Alt1 = 1u, /*!< Counter enable signal works as master output. */
TIM_MasterOut_Alt2 = 2u, /*!< Update period event works as master output. */
TIM_MasterOut_Alt3 = 3u, /*!< Channel capture or compare event works as master output. */
TIM_MasterOut_Alt4 = 4u, /*!< Reference signal of channel 1 works as master output. */
TIM_MasterOut_Alt5 = 5u, /*!< Reference signal of channel 2 works as master output. */
TIM_MasterOut_Alt6 = 6u, /*!< Reference signal of channel 3 works as master output. */
TIM_MasterOut_Alt7 = 7u, /*!< Reference signal of channel 4 works as master output. */
} TIM_MasterOut_Type;
/*!
* @brief TIM slave mode input object source.
*/
typedef enum
{
TIM_SlaveIn_Alt0 = 0u, /*!< Internal trigger 0. */
TIM_SlaveIn_Alt1 = 1u, /*!< Internal trigger 1. */
TIM_SlaveIn_Alt2 = 2u, /*!< Internal trigger 2.*/
TIM_SlaveIn_Alt3 = 3u, /*!< Internal trigger 3. */
TIM_SlaveIn_Alt4 = 4u, /*!< Edge detector of timer input channel 1. */
TIM_SlaveIn_Alt5 = 5u, /*!< Timer input channel 1. */
TIM_SlaveIn_Alt6 = 6u, /*!< Timer input channel 2. */
TIM_SlaveIn_Alt7 = 7u, /*!< External trigger input. */
} TIM_SlaveIn_Type;
/*!
* @brief TIM slave mode counter response.
*/
typedef enum
{
TIM_SlaveResp_Disabled = 0u, /*!< Disable the slave mode. */
TIM_SlaveResp_Alt1 = 1u, /*!< Counting in encoder mode 1. */
TIM_SlaveResp_Alt2 = 2u, /*!< Counting in encoder mode 2.*/
TIM_SlaveResp_Alt3 = 3u, /*!< Counting in encoder mode 3. */
TIM_SlaveResp_Alt4 = 4u, /*!< Reset counter. */
TIM_SlaveResp_Alt5 = 5u, /*!< Counter treat the signal as a gate. */
TIM_SlaveResp_Alt6 = 6u, /*!< Start the counter. */
TIM_SlaveResp_Alt7 = 7u, /*!< Counter counts on rising edges. */
} TIM_SlaveResp_Type;
/*!
* @brief TIM DMA Burst transfer base address.
*/
typedef enum
{
TIM_DMABurstBaseAddr_Alt0 = 0u, /*!< Start from CR1 register. */
TIM_DMABurstBaseAddr_Alt1 = 1u, /*!< Start from CR2 register. */
TIM_DMABurstBaseAddr_Alt2 = 2u, /*!< Start from SMCR register. */
TIM_DMABurstBaseAddr_Alt3 = 3u, /*!< Start from DIER register. */
TIM_DMABurstBaseAddr_Alt4 = 4u, /*!< Start from SR register. */
TIM_DMABurstBaseAddr_Alt5 = 5u, /*!< Start from EGR register. */
TIM_DMABurstBaseAddr_Alt6 = 6u, /*!< Start from CCMR1 register. */
TIM_DMABurstBaseAddr_Alt7 = 7u, /*!< Start from CCMR2 register. */
TIM_DMABurstBaseAddr_Alt8 = 8u, /*!< Start from CCER register. */
TIM_DMABurstBaseAddr_Alt9 = 9u, /*!< Start from CNT register. */
TIM_DMABurstBaseAddr_Alt10 = 10u, /*!< Start from PSC register. */
TIM_DMABurstBaseAddr_Alt11 = 11u, /*!< Start from ARR register. */
TIM_DMABurstBaseAddr_Alt12 = 12u, /*!< Start from CCR1 register. */
TIM_DMABurstBaseAddr_Alt13 = 13u, /*!< Start from CCR2 register. */
TIM_DMABurstBaseAddr_Alt14 = 14u, /*!< Start from CCR3 register. */
TIM_DMABurstBaseAddr_Alt15 = 15u, /*!< Start from CCR4 register. */
} TIM_DMABurstBaseAddr_Type;
/*!
* @brief TIM DMA Burst transfer length.
*/
typedef enum
{
TIM_DMABurstBaseLen_Alt0 = 0u, /*!< Sequentially visit 1 register from base register */
TIM_DMABurstBaseLen_Alt1 = 1u, /*!< Sequentially visit 2 registers from base register */
TIM_DMABurstBaseLen_Alt2 = 2u, /*!< Sequentially visit 3 registers from base register */
TIM_DMABurstBaseLen_Alt3 = 3u, /*!< Sequentially visit 4 registers from base register */
TIM_DMABurstBaseLen_Alt4 = 4u, /*!< Sequentially visit 5 registers from base register */
TIM_DMABurstBaseLen_Alt5 = 5u, /*!< Sequentially visit 6 registers from base register */
TIM_DMABurstBaseLen_Alt6 = 6u, /*!< Sequentially visit 7 registers from base register */
TIM_DMABurstBaseLen_Alt7 = 7u, /*!< Sequentially visit 8 registers from base register */
TIM_DMABurstBaseLen_Alt8 = 8u, /*!< Sequentially visit 9 registers from base register */
TIM_DMABurstBaseLen_Alt9 = 9u, /*!< Sequentially visit 10 registers from base register */
TIM_DMABurstBaseLen_Alt10 = 10u, /*!< Sequentially visit 11 registers from base register */
TIM_DMABurstBaseLen_Alt11 = 11u, /*!< Sequentially visit 12 registers from base register */
TIM_DMABurstBaseLen_Alt12 = 12u, /*!< Sequentially visit 13 registers from base register */
TIM_DMABurstBaseLen_Alt13 = 13u, /*!< Sequentially visit 14 registers from base register */
TIM_DMABurstBaseLen_Alt14 = 14u, /*!< Sequentially visit 15 registers from base register */
TIM_DMABurstBaseLen_Alt15 = 15u, /*!< Sequentially visit 16 registers from base register */
TIM_DMABurstBaseLen_Alt16 = 16u, /*!< Sequentially visit 17 registers from base register */
TIM_DMABurstBaseLen_Alt17 = 17u, /*!< Sequentially visit 18 registers from base register */
} TIM_DMABurstBaseLen_Type;
/*!
* @brief TIM encoder direction.
*/
typedef enum
{
TIM_EncoderDirection_Forward = 0u, /*!< Encoder rotates in forward direction. */
TIM_EncoderDirection_Backward = 1u, /*!< Encoder rotates in backward direction. */
} TIM_EncoderDirection_Type;
/*!
* @brief TIM break input sampling filter.
*/
typedef enum
{
TIM_BreakInFilter_Alt0 = 0u, /*!< Break In Filter swicther 0. */
TIM_BreakInFilter_Alt1 = 1u, /*!< Break In Filter swicther 1. */
TIM_BreakInFilter_Alt2 = 2u, /*!< Break In Filter swicther 2. */
TIM_BreakInFilter_Alt3 = 3u, /*!< Break In Filter swicther 3. */
TIM_BreakInFilter_Alt4 = 4u, /*!< Break In Filter swicther 4. */
TIM_BreakInFilter_Alt5 = 5u, /*!< Break In Filter swicther 5. */
TIM_BreakInFilter_Alt6 = 6u, /*!< Break In Filter swicther 6. */
TIM_BreakInFilter_Alt7 = 7u, /*!< Break In Filter swicther 7. */
TIM_BreakInFilter_Alt8 = 8u, /*!< Break In Filter swicther 8. */
TIM_BreakInFilter_Alt9 = 9u, /*!< Break In Filter swicther 9. */
TIM_BreakInFilter_Alt10 = 10u, /*!< Break In Filter swicther 10. */
TIM_BreakInFilter_Alt11 = 11u, /*!< Break In Filter swicther 11. */
TIM_BreakInFilter_Alt12 = 12u, /*!< Break In Filter swicther 12. */
TIM_BreakInFilter_Alt13 = 13u, /*!< Break In Filter swicther 13. */
TIM_BreakInFilter_Alt14 = 14u, /*!< Break In Filter swicther 14. */
TIM_BreakInFilter_Alt15 = 15u, /*!< Break In Filter swicther 15. */
TIM_BreakInFilter_Disabled = 16u, /*!< Not using Break In Filter. */
} TIM_BreakInFilter_Type;
/*!
* @brief TIM break input source switcher.
*/
typedef enum
{
TIM_BreakInSource_Alt0 = 1u, /*!< Break In Source swicther 0. */
TIM_BreakInSource_Alt1 = 2u, /*!< Break In Source swicther 1. */
} TIM_BreakInSource_Type;
/*!
* @brief TIM lock level.
*/
typedef enum
{
TIM_LockLevel_Disabled = 0u, /*!< Unlock. */
TIM_LockLevel_Alt0 = 1u, /*!< Lock level 1. */
TIM_LockLevel_Alt1 = 2u, /*!< Lock level 2. */
TIM_LockLevel_Alt2 = 3u, /*!< Lock level 3. */
} TIM_LockLevel_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref TIM_Init() to initialize the TIM module time base unit.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */
uint32_t StepFreqHz; /*!< Step length value. Counter freq = ClockSourceFreqHz / (ClockSourceDiv+1). */
uint32_t Period; /*!< Counter counting period length, from 0 to Period. */
bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */
TIM_PeriodMode_Type PeriodMode; /*!< Counter working period times. */
TIM_CountMode_Type CountMode; /*!< Counter count direction. */
} TIM_Init_Type;
/*!
* @brief This type of structure instance is used to setup the output compare feature when calling the @ref TIM_EnableOutputCompare() to enable the TIM module output compare channel.
*/
typedef struct
{
uint32_t ChannelValue; /*!< Value to be compared with counter. */
bool EnableFastOutput; /*!< Enable fast response to the trigger input event. */
bool EnablePreLoadChannelValue; /*!< Enable the preload of channel value. If enable, it will be updated in next period, otherwise immediately. */
TIM_OutputCompareRefOut_Type RefOutMode; /*!< The reference output when counter matching the channel value. */
bool ClearRefOutOnExtTrigger; /*!< External trigger high will clear the reference. */
TIM_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_OutputCompareConf_Type;
/*!
* @brief This type of structure instance is used to setup the input capture feature when calling the @ref TIM_EnableInputCapture() to enable the TIM module input capture channel.
*/
typedef struct
{
TIM_InputCaptureInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_InputCaptureInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_InputCaptureConf_Type;
/*!
* @brief This type of structure instance is used to setup the dead time feature when calling the @ref TIM_EnableDeadPeriod() to enable the TIM module dead time area set.
* | DeadPeriodCoef | Real Dead Area Time |
* | ------------ | --------------------------------------------------- |
* | 0xxxxxxx | DeadPeriodCoef * DeadPeriodStep |
* | 10xxxxxx | ( 64 + DeadPeriodCoef[5:0] ) * ( 2 * DeadPeriodStep ) |
* | 110xxxxx | ( 32 + DeadPeriodCoef[4:0] ) * ( 8 * DeadPeriodStep ） |
* | 111xxxxx | ( 32 + DeadPeriodCoef[4:0] ) * ( 16 * DeadPeriodStep ) |
*/
typedef struct
{
uint8_t DeadPeriodCoef; /*!< The coefficient with bias to multiply with StepFreqHz to get the final dead area time. */
} TIM_DeadPeriodConf_Type;
/*!
* @brief This type of structure instance is used to setup the master mode configuration when calling the @ref TIM_EnableMasterMode().
*/
typedef struct
{
TIM_MasterOut_Type Out; /*!< Master mode output selection. */
bool EnableSync; /*!< Enable sychronize with slave timers. */
} TIM_MasterModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the slave mode configuration when calling the @ref TIM_EnableSlaveMode().
*/
typedef struct
{
TIM_SlaveIn_Type In; /*!< Input trigger selection for slave timer. */
TIM_SlaveResp_Type Resp; /*!< Slave timer counter response for its input trigger. */
} TIM_SlaveModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the external trigger input configuration when calling the @ref TIM_EnableExtTriggerIn().
*/
typedef struct
{
TIM_ExtTriggerInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_ExtTriggerInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_ExtTriggerPinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_ExtTriggerInConf_Type;
/*!
* @brief This type of structure instance is used to setup the dma burst configuration when calling the @ref TIM_EnableDMABurst().
*/
typedef struct
{
TIM_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */
TIM_DMABurstBaseLen_Type Length; /*!< Length of sequential registers DMA burst visits. */
} TIM_DMABurstConf_Type;
/*!
* @brief This type of structure instance is used to setup the idle state output when calling the @ref TIM_EnableIdleOut().
*/
typedef struct
{
TIM_PinPolarity_Type PinPolarity; /*!< The output state of channel under idle mode. */
TIM_PinPolarity_Type CompPinPolarity; /*!< The output state of complementary channel under idle mode. */
} TIM_IdleOut_Type;
/*!
* @brief This type of structure instance is used to setup the break in configuration when calling the @ref TIM_EnableBreakIn().
*/
typedef struct
{
TIM_PinPolarity_Type PinPolarity; /*!< The active edge of the break in signal. */
bool AutoSwitchOutput; /*!< If input signal is inactive, switch the output compare at next update. */
bool DirectIdleOutput; /*!< If enable, output the set idle state directly. */
TIM_BreakInFilter_Type Filter; /*!< Break input filter type switcher. */
uint32_t Source; /*!< Break input source mask. See to macro TIM_BKEAK_IN_MASKx. */
} TIM_BreakIn_Type;
/*!
* @brief Set the timer's step for indicated TIM module.
*
* @param TIMx TIM instance.
* @param init Pointer to the initialization structure. See to @ref TIM_Init_Type.
* @return val 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz.
*/
bool TIM_Init(TIM_Type * TIMx, TIM_Init_Type * init);
/*!
* @brief Start counting.
*
* @param TIMx TIM instance.
* @return None.
*/
void TIM_Start(TIM_Type * TIMx);
/*!
* @brief Stop counting immediately.
*
* @param TIMx TIM instance.
* @return None.
*/
void TIM_Stop(TIM_Type * TIMx);
/*!
* @brief Get the indicated TIMx Counter value.
*
* @param TIMx TIM_Type instance.
* @return The current value of the counter register.
*/
uint32_t TIM_GetCounterValue(TIM_Type * TIMx);
/*!
* @brief Clear the indicated TIMx Counter.
*
* @param TIMx TIM_Type instance.
* @return None.
*/
void TIM_ClearCounterValue(TIM_Type * TIMx);
/*!
* @brief Enable the TIM interrupts.
*
* @param TIMx TIM_Type instance.
* @param interrupts Interrupts to be enabled.See to @ref TIM_INT.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_EnableInterrupts(TIM_Type * TIMx, uint32_t interrupts, bool enable);
/*!
* @brief Enable the TIM DMAs.
*
* @param TIMx TIM_Type instance.
* @param dmas DMA masks to be enabled. See to @ref TIM_DMA.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_EnableDMA(TIM_Type * TIMx, uint32_t dmas, bool enable);
/*!
* @brief Software trigger events to call interrupts or DMAs.
*
* Can simultaneously trigger multiple events.
*
* @param TIMx TIM instance. See to @ref TIM_SWTRG.
* @param swtrgs Trigger the events to generate interrupts.
*/
void TIM_DoSwTrigger(TIM_Type * TIMx, uint32_t swtrgs);
/*!
* @brief Get the status of the indicated timer.
*
* @param TIMx TIM_Type instance.
* @return Interrupt status flags. See to @ref TIM_INT_STATUS.
*/
uint32_t TIM_GetInterruptStatus(TIM_Type * TIMx);
/*!
* @brief Clear the status of indicated interrupt.
*
* @param TIMx TIM_Type instance.
* @param status The required clear flag type. See to @ref TIM_INT_STATUS.
* @return None.
*/
void TIM_ClearInterruptStatus(TIM_Type * TIMx, uint32_t status);
/*!
* @brief Set up the output compare feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_Type instance.
* @param channel Output channel instance. See to @ref TIM_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_OutputCompareConf_Type.
* @return None.
*/
void TIM_EnableOutputCompare(TIM_Type * TIMx, uint32_t channel, TIM_OutputCompareConf_Type * conf);
/*!
* @brief Set up the complementary output compare feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_Type instance.
* @param channel Output channel instance. See to @ref TIM_CHANNEL_SELECTION.
* @param enable 'true' to enable the complementary channel output, 'false' to disable the complementary channel output.
* @return None.
*/
void TIM_EnableCompOutput(TIM_Type * TIMx, uint32_t channel, bool enable);
/*!
* @brief Enable the TIM channel output for pulse generation.
*
* @param TIMx TIM_Type instance.
* @param enable 'true' to enable the channel output, 'false' to disable the channel output.
* @return None.
*/
void TIM_EnableOutputCompareSwitch(TIM_Type * TIMx, bool enable);
/*!
* @brief Enable the input capture feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_Type instance.
* @param channel Input channel instance. See to @ref TIM_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_InputCaptureConf_Type.
* @return None.
*/
void TIM_EnableInputCapture(TIM_Type * TIMx, uint32_t channel, TIM_InputCaptureConf_Type * conf);
/*!
* @brief Get the value of the indicated timer channel.
*
* When capture event happens, counter value will be kept in its indicated channel.
*
* @param TIMx TIM_Type instance.
* @param channel Channel instance to get the value. See to @ref TIM_CHANNEL_SELECTION.
* @return Value of the indiacted timer channel.
*/
uint32_t TIM_GetChannelValue(TIM_Type * TIMx, uint32_t channel);
/*!
* @brief Put the value into the indicated timer channel.
*
* When in output compare, channel value would be the compared with counter value.
*
* @param TIMx TIM_Type instance.
* @param channel Channel instance to put the value. See to @ref TIM_CHANNEL_SELECTION.
* @param value The value to be set in the indicated timer channel.
* @return None.
*/
void TIM_PutChannelValue(TIM_Type * TIMx, uint32_t channel, uint32_t value);
/*!
* @brief Set the step length between TIM internal clock and dead area clock / ETR / TI sample clock.
*
* @param TIMx TIM_Type instance.
* @param div Selected sample clock devision ratio.
* @return None.
*/
void TIM_SetClockDiv(TIM_Type * TIMx, TIM_ClockDiv_Type div);
/*!
* @brief Enable the dead area of the indicated timer.
*
* @param TIMx TIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_DeadPeriodConf_Type.
* @return None.
*/
void TIM_EnableDeadPeriod(TIM_Type * TIMx, TIM_DeadPeriodConf_Type * conf);
/*!
* @brief Enable the master mode of the indicated timer.
*
* Master mode transfer the timer signal to other timers.
*
* @param TIMx TIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_MasterModeConf_Type.
* @return None.
*/
void TIM_EnableMasterMode(TIM_Type * TIMx, TIM_MasterModeConf_Type * conf);
/*!
* @brief Enable the slave mode of the indicated timer.
*
* Slave mode can control the working state of counter.
*
* @param TIMx TIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_SlaveModeConf_Type.
* @return None.
*/
void TIM_EnableSlaveMode(TIM_Type * TIMx, TIM_SlaveModeConf_Type * conf);
/*!
* @brief Enable the external trigger input of the indicated counter.
*
* External trigger signal will trigger counter do addition.
* Its div and filter along with the counter StepFreqHz will affect.
*
* @param TIMx TIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_ExtTriggerInConf_Type.
* @return None.
*/
void TIM_EnableExtTriggerIn(TIM_Type * TIMx, TIM_ExtTriggerInConf_Type * conf);
/*!
* @brief Enable the dma burst transfer of the indicated timer.
*
* @param TIMx TIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_DMABurstConf_Type.
* @return Address of DMA Burst transfer base register address.
*/
uint32_t TIM_EnableDMABurst(TIM_Type * TIMx, TIM_DMABurstConf_Type * conf);
/*!
* @brief Get the encoder rotating direction and the counted encoder pulse times.
*
* @param TIMx TIM_Type instance.
* @param value The counter value for pulse times.
* @return Encoder rotating direction. See to @ref TIM_EncoderDirection_Type.
*/
TIM_EncoderDirection_Type TIM_GetEncoder(TIM_Type * TIMx, uint32_t * value);
/*!
* @brief Set the indicated TIMx repetition counter value.
*
* @param TIMx TIM_Type instance.
* @param value The repetition value to be set.
* @return The current value of the counter register.
*/
void TIM_SetRepCounter(TIM_Type * TIMx, uint8_t value);
/*!
* @brief Get the indicated TIMx Counter value.
*
* Real repetition's times number, meaning left repetition period times to run.
*
* @param TIMx TIM_Type instance.
* @return The current value of the counter register.
*/
uint8_t TIM_GetRepCounterValue(TIM_Type * TIMx);
/*!
* @brief Set the channel idle state output when switch off the output compare.
*
* @param TIMx TIM_Type instance.
* @param channel Channel instance to set the idle state output. See to @ref TIM_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_IdleOut_Type.
* @return None.
*/
void TIM_EnableIdleOut(TIM_Type * TIMx, uint32_t channel, TIM_IdleOut_Type * conf);
/*!
* @brief Set the lock level for protecting the timer config setting.
*
* @param TIMx TIM_Type instance.
* @param lock Lock level to be set for protecting Timer set. See to @ref TIM_LockLevel_Type.
* @return None.
*/
void TIM_EnableLock(TIM_Type * TIMx, TIM_LockLevel_Type lock);
/*!
* @brief Set the break input of the timer.
*
* @param TIMx TIM_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_BreakIn_Type.
* @return None.
*/
void TIM_EnableBreakIn(TIM_Type * TIMx, TIM_BreakIn_Type * conf);
/*!
* @brief Set the PWM shift of the indicated channel.
*
* @param TIMx TIM_Type instance.
* @param channel Channel instance to set the pwm shift. See to @ref TIM_CHANNEL_SELECTION.
* @param value The counter time when need pwm output shift. If val equals the channel value, disable the shift.
* @return None.
*/
void TIM_EnablePWMShift(TIM_Type * TIMx, uint32_t channel, uint16_t value);
/*!
*@}
*/
#endif /* __HAL_TIM_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_uart.h"
void UART_Init(UART_Type * UARTx, UART_Init_Type * init)
{
uint32_t ccr = UARTx->CCR & ~( UART_CCR_PEN_MASK
| UART_CCR_PSEL_MASK
| UART_CCR_SPB0_MASK
| UART_CCR_CHAR_MASK
| UART_CCR_SPB1_MASK
);
/* WordLength. */
ccr |= UART_CCR_CHAR(init->WordLength);
/* StopBits. */
if ( (init->StopBits == UART_StopBits_2) || (init->StopBits == UART_StopBits_1_5) )
{
ccr |= UART_CCR_SPB0_MASK;
}
if ( (init->StopBits == UART_StopBits_0_5) || (init->StopBits == UART_StopBits_1_5) )
{
ccr |= UART_CCR_SPB1_MASK;
}
/* Parity. */
if (init->Parity == UART_Parity_Even)
{
ccr |= UART_CCR_PEN_MASK;
}
if (init->Parity == UART_Parity_Odd)
{
ccr |= UART_CCR_PEN_MASK | UART_CCR_PSEL_MASK;
}
UARTx->CCR = ccr;
/* XferMode. */
uint32_t gcr = UARTx->GCR & ~( UART_GCR_RXEN_MASK
| UART_GCR_TXEN_MASK
| UART_GCR_AUTOFLOWEN_MASK
);
gcr |= ((uint32_t)(init->XferMode) << UART_GCR_RXEN_SHIFT);
if (init->HwFlowControl == UART_HwFlowControl_RTS_CTS)
{
gcr |= UART_GCR_AUTOFLOWEN_MASK;
}
UARTx->GCR = gcr;
/* Setup the baudrate. */
UARTx->BRR = (init->ClockFreqHz / init->BaudRate) / 16u;
UARTx->FRA = (init->ClockFreqHz / init->BaudRate) % 16u;
}
void UART_Enable(UART_Type * UARTx, bool enable)
{
if (enable)
{
UARTx->GCR |= UART_GCR_UARTEN_MASK;
}
else
{
UARTx->GCR &= ~UART_GCR_UARTEN_MASK;
}
}
void UART_EnableInterrupts(UART_Type * UARTx, uint32_t interrupts, bool enable)
{
(enable) ? (UARTx->IER |= interrupts) : (UARTx->IER &= ~interrupts);
}
uint32_t UART_GetEnabledInterrupts(UART_Type * UARTx)
{
return UARTx->IER;
}
void UART_EnableDMA(UART_Type * UARTx, bool enable)
{
if (enable)
{
UARTx->GCR |= UART_GCR_DMAMODE_MASK;
}
else
{
UARTx->GCR &= ~UART_GCR_DMAMODE_MASK;
}
}
void UART_PutData(UART_Type * UARTx, uint8_t value)
{
UARTx->TDR = value;
}
uint8_t UART_GetData(UART_Type * UARTx)
{
return (uint8_t)(UARTx->RDR & 0xFFU);
}
/* return flags */
uint32_t UART_GetStatus(UART_Type * UARTx)
{
return UARTx->CSR;
}
/* return flags. */
uint32_t UART_GetInterruptStatus(UART_Type * UARTx)
{
return UARTx->ISR;
}
void UART_ClearInterruptStatus(UART_Type * UARTx, uint32_t interrupts)
{
UARTx->ICR = interrupts;
}
uint32_t UART_GetRxDataRegAddr(UART_Type * UARTx)
{
return (uint32_t)(&(UARTx->RDR));
}
uint32_t UART_GetTxDataRegAddr(UART_Type * UARTx)
{
return (uint32_t)(&(UARTx->TDR));
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_UART_H__
#define __HAL_UART_H__
#include "hal_common.h"
/*!
* @addtogroup UART
* @{
*/
/*!
* @brief UART driver version number.
*/
#define UART_DRIVER_VERSION 0u /*!< uart_0. */
/*!
* @addtogroup UART_STATUS
* @{
*/
#define UART_STATUS_TX_DONE UART_CSR_TXC_MASK /*!< Status flag when UART transmiter shifter is empty after the transfer is done. */
#define UART_STATUS_RX_DONE UART_CSR_RXAVL_MASK /*!< Status flag when UART receiving buffer is with available data. */
#define UART_STATUS_TX_FULL UART_CSR_TXFULL_MASK /*!< Status flag when UART transmiter buffer is full. */
#define UART_STATUS_TX_EMPTY UART_CSR_TXEPT_MASK /*!< Status flag when UART transmiter buffer is empty. */
/*!
* @}
*/
/*!
* @addtogroup UART_INT
* @{
*/
#define UART_INT_TX_EMPTY UART_ISR_TXINTF_MASK /*!< Interrupt enable when UART transmiter buffer is empty. */
#define UART_INT_RX_DONE UART_ISR_RXINTF_MASK /*!< Interrupt enable when UART receiving buffer is with available data. */
#define UART_INT_TX_DONE UART_ISR_TXCINTF_MASK /*!< Interrupt enable when UART transmiter shifter is empty. */
/*!
* @}
*/
/*!
* @brief UART word length type.
*/
typedef enum
{
UART_WordLength_5b = 0u, /*!< Word length 5 bits. */
UART_WordLength_6b = 1u, /*!< Word length 6 bits. */
UART_WordLength_7b = 2u, /*!< Word length 7 bits. */
UART_WordLength_8b = 3u, /*!< Word length 8 bits. */
} UART_WordLength_Type;
/*!
* @brief UART stop bits type.
*/
typedef enum
{
UART_StopBits_1 = 0u, /*!< 1 stop bits. */
UART_StopBits_2 = 1u, /*!< 2 stop bits. */
UART_StopBits_0_5 = 2u, /*!< 0.5 stop bits. */
UART_StopBits_1_5 = 3u, /*!< 1.5 stop bits. */
} UART_StopBits_Type;
/*!
* @brief UART parity type.
*/
typedef enum
{
UART_Parity_None = 0u, /*!< No parity. */
UART_Parity_Even = 1u, /*!< Even parity. */
UART_Parity_Odd = 2u, /*!< Odd parity. */
} UART_Parity_Type;
/*!
* @brief UART hardware flow control type.
*/
typedef enum
{
UART_HwFlowControl_None = 0u, /*!< No hardware flow control. */
UART_HwFlowControl_RTS_CTS = 1u, /*!< Enable RTS and CTS hardware flow control.*/
} UART_HwFlowControl_Type;
/*!
* @brief UART xfer mode type.
*/
typedef enum
{
UART_XferMode_None = 0u, /*!< Disable both Tx and Rx. */
UART_XferMode_RxOnly = 1u, /*!< Enable Rx only. */
UART_XferMode_TxOnly = 2u, /*!< Enable Tx only. */
UART_XferMode_RxTx = 3u, /*!< Enable both Rx and Tx. */
} UART_XferMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref UART_Init() to initialize the UART module.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Bus Clock Freq. */
uint32_t BaudRate; /*!< Specify the UART communication baud rate. */
UART_WordLength_Type WordLength; /*!< Specify the number of data bits transmitted or received in a frame. */
UART_StopBits_Type StopBits; /*!< Specify the number of stop bits transmitted. */
UART_Parity_Type Parity; /*!< Specify the parity mode. */
UART_XferMode_Type XferMode; /*!< Specify whether the Receive or Transmit mode is enabled or not. */
UART_HwFlowControl_Type HwFlowControl; /*!< Specify whether the hardware flow control mode is enabled or not. */
} UART_Init_Type;
/*!
* @brief Initialize the UART module.
*
* @param UARTx UART instance.
* @param init Pointer to the initialization structure. See to @ref UART_Init_Type.
* @return None.
*/
void UART_Init(UART_Type * UARTx, UART_Init_Type * init);
/*!
* @brief Enable the UART module.
*
* The UART module should be enabled before sending or receiving data.
*
* @param UARTx UART instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void UART_Enable(UART_Type * UARTx, bool enable);
/*!
* @brief Get the current status flags of the UART module.
*
* @param UARTx UART instance.
* @return Status flags. See to @ref UART_STATUS.
*/
uint32_t UART_GetStatus(UART_Type * UARTx);
/*!
* @brief Enable interrupts of the UART module.
*
* @param UARTx UART instance.
* @param interrupts Interrupt code masks. See to @ref UART_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void UART_EnableInterrupts(UART_Type * UARTx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the UART module.
*
* @param UARTx UART instance.
* @return Interrupt status flags. See to @ref UART_INT.
*/
uint32_t UART_GetInterruptStatus(UART_Type * UARTx);
/*!
* @brief Clear the interrupts status flags of the UART module.
*
* @param UARTx UART instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return Interrupt status flags. See to @ref UART_INT.
*/
void UART_ClearInterruptStatus(UART_Type * UARTx, uint32_t interrupts);
/*!
* @brief Put the data into transmiter buffer of the UART module.
*
* @param UARTx UART instance.
* @param value Data value to be send through the transmiter.
* @return None.
*/
void UART_PutData(UART_Type * UARTx, uint8_t value);
/*!
* @brief Get the data from receiver buffer of the UART module.
*
* @param UARTx UART instance.
* @return The data value received from the receiver.
* @return None.
*/
uint8_t UART_GetData(UART_Type * UARTx);
/*!
* @brief Enable the DMA trigger from the UART module.
*
* The DMA trigger events are the same as the intertupts.
*
* @param UARTx UART instance.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void UART_EnableDMA(UART_Type * UARTx, bool enable);
/*!
* @brief Read the current enabled interrupts the UART module.
*
* @param UARTx UART instance.
* @return The mask codes enabled interrupts. See to @ref UART_INT
*/
uint32_t UART_GetEnabledInterrupts(UART_Type * UARTx);
/*!
* @brief Get the hardware Rx data buffer's address the UART module.
*
* The return value of the address is most used with DMA module.
*
* @param UARTx UART instance.
* @return The value of the address for UART module's hardware Rx data buffer.
*/
uint32_t UART_GetRxDataRegAddr(UART_Type * UARTx);
/*!
* @brief Get the hardware Tx data buffer's address the UART module.
*
* The return value of the address is most used with DMA module.
*
* @param UARTx UART instance.
* @return The value of the address for UART module's hardware Tx data buffer.
*/
uint32_t UART_GetTxDataRegAddr(UART_Type * UARTx);
/*!
*@}
*/
#endif /* __HAL_UART_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_usb.h"
void USB_SetBufDespTableAddr(USB_Type * USBx, uint32_t addr)
{
USBx->FSBDTPAGE1 = USB_FSBDTPAGE1_BDTBA(addr >> 9u);
USBx->FSBDTPAGE2 = USB_FSBDTPAGE2_BDTBA(addr >> 16u);
USBx->FSBDTPAGE3 = USB_FSBDTPAGE3_BDTBA(addr >> 24u);
}
void USB_InitDevice(USB_Type * USBx, USB_Device_Init_Type *init)
{
if ( (uintptr_t)(init->BufDespTable_Addr) % 512u != 0u)
{
return;
}
USB_SetDeviceAddr(USBx, 0x00u);
USB_SetBufDespTableAddr(USBx, init->BufDespTable_Addr);
USB_Enable(USBx, true);
}
void USB_EnableInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable)
{
if(enable)
{
USBx->FSINTENB |= interrupts;
}
else
{
USBx->FSINTENB &= ~interrupts;
}
}
uint32_t USB_GetEnabledInterrupts(USB_Type * USBx)
{
return USBx->FSINTENB;
}
uint32_t USB_GetInterruptStatus(USB_Type * USBx)
{
uint32_t stat = USBx->FSINTSTAT;
uint32_t enb = USBx->FSINTENB;
return stat & enb;
}
void USB_ClearInterruptStatus(USB_Type * USBx, uint32_t interrupts)
{
uint32_t enb = USBx->FSINTENB;
USBx->FSINTSTAT = interrupts & enb;
}
void USB_EnableErrInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable)
{
if(enable)
{
USBx->FSERRENB |= interrupts;
}
else
{
USBx->FSERRENB &= ~interrupts;
}
}
uint32_t USB_GetEnabledErrInterrupts(USB_Type * USBx)
{
return USBx->FSERRENB;
}
uint32_t USB_GetErrInterruptStatus(USB_Type * USBx)
{
uint32_t stat = USBx->FSERRSTAT;
uint32_t enb = USBx->FSERRENB;
USBx->FSERRSTAT = stat & ~enb;
return stat & enb;
}
void USB_ClearErrInterruptStatus(USB_Type * USBx, uint32_t interrupts)
{
uint32_t enb = USBx->FSERRENB;
USBx->FSERRSTAT = interrupts & enb;
}
uint32_t USB_GetBufDespIndex(USB_Type * USBx)
{
return (USBx->FSSTAT)>>2;
}
void USB_Enable(USB_Type * USBx, bool enable)
{
if(enable)
{
USBx->FSCTL |= USB_FSCTL_USBEN_MASK;
}
else
{
USBx->FSCTL &= ~USB_FSCTL_USBEN_MASK;
}
}
void USB_EnableOddEvenReset(USB_Type * USBx, bool enable)
{
if(enable)
{
USBx->FSCTL |= USB_FSCTL_ODDRST_MASK;
}
else
{
USBx->FSCTL &= ~USB_FSCTL_ODDRST_MASK;
}
}
void USB_EnableResumeSignal(USB_Type * USBx, bool enable)
{
if(enable)
{
USBx->FSCTL |= USB_FSCTL_RESUME_MASK;
}
else
{
USBx->FSCTL &= ~USB_FSCTL_RESUME_MASK;
}
}
void USB_EnableSuspend(USB_Type * USBx, bool enable)
{
if(true == enable)
{
USBx->FSCTL |= USB_FSCTL_TXDSUSPENDTOKENBUSY_MASK;
}
else
{
USBx->FSCTL &= ~USB_FSCTL_TXDSUSPENDTOKENBUSY_MASK;
}
}
void USB_SetDeviceAddr(USB_Type * USBx, uint8_t addr)
{
USBx->FSADDR = ( (USBx->FSADDR & ~USB_FSADDR_ADDR_MASK)
| (addr & USB_FSADDR_ADDR_MASK) )
;
}
uint8_t USB_GetDeviceAddr(USB_Type * USBx)
{
return USBx->FSADDR & USB_FSADDR_ADDR_MASK;
}
uint32_t USB_GetBufDespTableAddr(USB_Type * USBx)
{
return (uint32_t)
( ( (USBx->FSBDTPAGE1 >> USB_FSBDTPAGE1_BDTBA_SHIFT) << 9u )
| ( (USBx->FSBDTPAGE2 >> USB_FSBDTPAGE2_BDTBA_SHIFT) << 16u)
| ( (USBx->FSBDTPAGE3 >> USB_FSBDTPAGE3_BDTBA_SHIFT) << 24u)
);
}
uint32_t USB_GetFrameNumber(USB_Type * USBx)
{
return (USBx->FSFRMNUML) | (USBx->FSFRMNUML << 7u);
}
USB_BufDesp_Type * USB_GetBufDesp(USB_Type * USBx)
{
USB_BufDespTable_Type *bdt = (USB_BufDespTable_Type *)USB_GetBufDespTableAddr(USBx);
return &bdt->Index[USBx->FSSTAT >> 2];
}
USB_TokenPid_Type USB_BufDesp_GetTokenPid(USB_BufDesp_Type * bd)
{
return (USB_TokenPid_Type)bd->TOK_PID;
}
uint32_t USB_BufDesp_GetPacketAddr(USB_BufDesp_Type * bd)
{
return bd->ADDR;
}
uint32_t USB_BufDesp_GetPacketSize(USB_BufDesp_Type * bd)
{
return bd->BC;
}
void USB_BufDesp_Reset(USB_BufDesp_Type * bd)
{
bd->BDT_STALL = 0u;
bd->NINC = 0u;
bd->KEEP = 0u;
bd->DTS = 1u;
}
uint32_t USB_GetEndPointIndex(USB_Type * USBx)
{
return (USBx->FSSTAT & USB_FSSTAT_ENDP_MASK) >> USB_FSSTAT_ENDP_SHIFT;
}
USB_Direction_Type USB_GetXferDirection(USB_Type * USBx)
{
return (USB_Direction_Type)( (USBx->FSSTAT & USB_FSSTAT_TX_MASK) >> USB_FSSTAT_TX_SHIFT);
}
USB_BufDesp_OddEven_Type USB_GetBufDespOddEven(USB_Type * USBx)
{
return (USB_BufDesp_OddEven_Type)( (USBx->FSSTAT & USB_FSSTAT_ODD_MASK) >> USB_FSSTAT_ODD_SHIFT );
}
bool USB_BufDesp_Xfer(USB_BufDesp_Type * bd, uint32_t data_n, uint8_t * buffer, uint32_t len)
{
if (1u == bd->OWN)
{
return false;
}
bd->ADDR = (uint32_t)buffer;
bd->DATA = data_n;
bd->BC = len;
bd->OWN = 1u;
return true;
}
bool USB_BufDesp_IsBusy(USB_BufDesp_Type * bd)
{
if (1u == bd->OWN)
{
return true;
}
else
{
return false;
}
}
void USB_EnableEndPoint(USB_Type * USBx, uint32_t index, USB_EndPointMode_Type mode, bool enable)
{
if (false == enable)
{
USBx->FSEPCTL[index] = 0u;
USB_BufDespTable_Type * bdt = (USB_BufDespTable_Type * )USB_GetBufDespTableAddr(USBx);
bdt->Table[index][0u][0u].HEAD = 0u;
bdt->Table[index][0u][1u].HEAD = 0u;
bdt->Table[index][1u][0u].HEAD = 0u;
bdt->Table[index][1u][1u].HEAD = 0u;
return;
}
if (USB_EndPointMode_Control == mode)
{
USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(3) | USB_FSEPCTL_EPHSHK_MASK;
}
else if (USB_EndPointMode_Bulk == mode)
{
USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(7u) | USB_FSEPCTL_EPHSHK_MASK;
}
else if (USB_EndPointMode_Interrupt == mode)
{
USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(7u) | USB_FSEPCTL_EPHSHK_MASK;
}
else if (USB_EndPointMode_Isochronous == mode)
{
USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(7u);
}
}
void USB_EnableEndPointStall(USB_Type * USBx, uint32_t index, bool enable)
{
USB_BufDespTable_Type * bdt = (USB_BufDespTable_Type * )USB_GetBufDespTableAddr(USBx);
for (uint32_t i = 0; i < USB_BDT_EP_NUM; i++)
{
if (true == enable)
{
USBx->FSEPCTL[i] |= USB_FSEPCTL_EPSTALL_MASK;
bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_IN ].BDT_STALL = 1u;
bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_OUT].BDT_STALL = 1u;
bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_IN ].BDT_STALL = 1u;
bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_OUT].BDT_STALL = 1u;
}
else
{
USBx->FSEPCTL[i] &= ~USB_FSEPCTL_EPSTALL_MASK;
bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_IN ].BDT_STALL = 0u;
bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_IN ].OWN = 0u;
bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_OUT].BDT_STALL = 0u;
bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_OUT].OWN = 0u;
bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_IN ].BDT_STALL = 0u;
bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_IN ].OWN = 0u;
bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_OUT].BDT_STALL = 0u;
bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_OUT].OWN = 0u;
}
}
}
uint32_t USB_GetEnabledEndPointStall(USB_Type * USBx)
{
uint32_t status = 0u;
for(uint32_t i = 0u; i < USB_BDT_EP_NUM; i++)
{
if (0 != (USBx->FSEPCTL[i] & USB_FSEPCTL_EPSTALL_MASK) )
{
status |= 1u << i;
}
}
return status;
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_USB_H__
#define __HAL_USB_H__
#include "hal_common.h"
#include "hal_usb_bdt.h"
/*!
* @addtogroup USB
* @{
*/
/*!
* @brief USB driver version number.
*/
#define USB_DRIVER_VERSION 0u /*!< USB_0. */
/*!
* @addtogroup USB_INT
* @brief USB_INT mask codes
* @{
*/
#define USB_INT_RESET USB_FSINTSTAT_USBRST_MASK /*!< USB Interrupt: USB bus reset. */
#define USB_INT_ERROR USB_FSINTSTAT_ERROR_MASK /*!< USB Interrupt: Error happend. */
#define USB_INT_SOFTOK USB_FSINTSTAT_SOFTOK_MASK /*!< USB Interrupt: Recv a SOF_Tok. */
#define USB_INT_TOKENDONE USB_FSINTSTAT_TOKDNE_MASK /*!< USB Interrupt: Token done. */
#define USB_INT_SLEEP USB_FSINTSTAT_SLEEP_MASK /*!< USB Interrupt: Sleep. */
#define USB_INT_RESUME USB_FSINTSTAT_RESUME_MASK /*!< USB Interrupt: Resume. */
#define USB_INT_ATTACH USB_FSINTSTAT_ATTACH_MASK /*!< USB Interrupt: Attach. */
#define USB_INT_STALL USB_FSINTSTAT_STALL_MASK /*!< USB Interrupt: Stall. */
/*!
* @}
*/
/*!
* @addtogroup USB_INT_ERR
* @brief USB_INT_ERR mask codes
* @{
*/
#define USB_INT_ERR_PID USB_FSERRSTAT_PIDERR_MASK /*!< USB Error: PID check error. */
#define USB_INT_ERR_CRC5 USB_FSERRSTAT_CRC5EOF_MASK /*!< USB Error: CRC5 check failed. */
#define USB_INT_ERR_EOF USB_FSERRSTAT_CRC5EOF_MASK /*!< USB Error: EOF Error. */
#define USB_INT_ERR_CRC16 USB_FSERRSTAT_CRC16_MASK /*!< USB Error: CRC16 check failed. */
#define USB_INT_ERR_DFN8 USB_FSERRSTAT_DFN8_MASK /*!< USB Error: Data not 8bit. */
#define USB_INT_ERR_BTO USB_FSERRSTAT_BTOERR_MASK /*!< USB Error: BTO error. */
#define USB_INT_ERR_DMA USB_FSERRSTAT_DMAERR_MASK /*!< USB Error: DMA error. */
#define USB_INT_ERR_BTS USB_FSERRSTAT_BTSERR_MASK /*!< USB Error: Bit stuff error. */
/*!
* @}
*/
/*!
* @addtogroup USB_EP
* @brief USB_EP mask codes
* @{
*/
#define USB_EP_0 (1u << 0u ) /*!< EndPoint 0. */
#define USB_EP_1 (1u << 1u ) /*!< EndPoint 1. */
#define USB_EP_2 (1u << 2u ) /*!< EndPoint 2. */
#define USB_EP_3 (1u << 3u ) /*!< EndPoint 3. */
#define USB_EP_4 (1u << 4u ) /*!< EndPoint 4. */
#define USB_EP_5 (1u << 5u ) /*!< EndPoint 5. */
#define USB_EP_6 (1u << 6u ) /*!< EndPoint 6. */
#define USB_EP_7 (1u << 7u ) /*!< EndPoint 7. */
#define USB_EP_8 (1u << 8u ) /*!< EndPoint 8. */
#define USB_EP_9 (1u << 9u ) /*!< EndPoint 9. */
#define USB_EP_10 (1u << 10u) /*!< EndPoint 10. */
#define USB_EP_11 (1u << 11u) /*!< EndPoint 11. */
#define USB_EP_12 (1u << 12u) /*!< EndPoint 12. */
#define USB_EP_13 (1u << 13u) /*!< EndPoint 13. */
#define USB_EP_14 (1u << 14u) /*!< EndPoint 14. */
#define USB_EP_15 (1u << 15u) /*!< EndPoint 15. */
/*!
* @}
*/
/*!
* @brief USB TokenPid type.
*/
typedef enum
{
USB_TokenPid_OUT = 0x1u, /*!< USB Token Pid: OUT. */
USB_TokenPid_IN = 0x9u, /*!< USB Token Pid: IN. */
USB_TokenPid_SETUP = 0xDu, /*!< USB Token Pid: SETUP. */
} USB_TokenPid_Type;
/*!
* @brief USB Direction type.
*/
typedef enum
{
USB_Direction_OUT = 0x0u, /*!< USB Direstion: IN. */
USB_Direction_IN = 0x1u, /*!< USB Direstion: OUT. */
USB_Direction_NULL, /*!< USB Direstion: NULL. */
} USB_Direction_Type;
/*!
* @brief USB BufDesp OddEven type.
*/
typedef enum
{
USB_BufDesp_OddEven_Even = 0x0u, /*!< Buffer Descriptor OddEven: Even. */
USB_BufDesp_OddEven_Odd = 0x1u, /*!< Buffer Descriptor OddEven: Odd. */
} USB_BufDesp_OddEven_Type;
/*!
* @brief USB EndPoint Mode.
*/
typedef enum
{
USB_EndPointMode_Control = 1u, /*!< USB EndPoint Mode: Control xfer. */
USB_EndPointMode_Bulk = 2u, /*!< USB EndPoint Mode: Bulk xfer. */
USB_EndPointMode_Interrupt = 3u, /*!< USB EndPoint Mode: Interrupt xfer. */
USB_EndPointMode_Isochronous = 4u, /*!< USB EndPoint Mode: isoch xfer. */
USB_EndPointMode_NULL, /*!< USB EndPoint Mode: NULL. */
} USB_EndPointMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref USB_InitDevice() to initialize the USB module.
*/
typedef struct
{
uint32_t BufDespTable_Addr; /*!< BufDespTable addr. */
} USB_Device_Init_Type;
/*!
* @brief Initialize the USB module.
*
* @param USBx USB instance.
* @param init Pointer to the initialization structure. See to @ref USB_Device_Init_Type.
* @return None.
*/
void USB_InitDevice(USB_Type * USBx, USB_Device_Init_Type * init);
/*!
* @brief Enable interrupts of the USB module.
*
* @param USBx USB instance.
* @param interrupts Interrupt code masks. See to @ref USB_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void USB_EnableInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable);
/*!
* @brief Get the enabled interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT.
*/
uint32_t USB_GetEnabledInterrupts(USB_Type * USBx);
/*!
* @brief Get the interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT.
*/
uint32_t USB_GetInterruptStatus(USB_Type * USBx);
/*!
* @brief Clear the interrupts status flags of the USB module.
* @param USBx USB instance.
* @param interrupts Interrupt status flags. See to @ref USB_INT.
* @return None.
*/
void USB_ClearInterruptStatus(USB_Type * USBx, uint32_t interrupts);
/*!
* @brief Enable error interrupts of the USB module.
*
* @param USBx USB instance.
* @param interrupts Error Interrupt code masks. See to @ref USB_INT_ERR.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void USB_EnableErrInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable);
/*!
* @brief Get the enabled error interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT_ERR.
*/
uint32_t USB_GetEnabledErrInterrupts(USB_Type * USBx);
/*!
* @brief Get the error interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT_ERR.
*/
uint32_t USB_GetErrInterruptStatus(USB_Type * USBx);
/*!
* @brief Clear the error interrupts status flags of the USB module.
* @param USBx USB instance.
* @param interrupts Interrupt status flags. See to @ref USB_INT_ERR.
* @return None.
*/
void USB_ClearErrInterruptStatus(USB_Type * USBx, uint32_t interrupts);
/*!
* @brief Enable USB.
*
* @param USBx USB instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void USB_Enable(USB_Type * USBx, bool enable);
/*!
* @brief Enable USB BufDesp ODD_EVEN Reset, and make only even BufDesp can be used.
*
* @param USBx USB instance.
* @param enable 'true' to enable the feature, 'false' to disable the feature.
* @return None.
*/
void USB_EnableOddEvenReset(USB_Type * USBx, bool enable);
/*!
* @brief Enable USB Resume signal.
*
* @param USBx USB instance.
* @param enable 'true' to enable the resume signal, 'false' to disable the resume signal.
* @return None.
*/
void USB_EnableResumeSignal(USB_Type * USBx, bool enable);
/*!
* @brief Enable USB Suspend.
*
* @param USBx USB instance.
* @param enable 'true' to enable suspend, 'false' to disable suspend.
* @return None.
*/
void USB_EnableSuspend(USB_Type * USBx, bool enable);
/*!
* @brief Set Device address. This address is distribute by host.
*
* @param USBx USB instance.
* @param addr The Device address.
* @return None.
*/
void USB_SetDeviceAddr(USB_Type * USBx, uint8_t addr);
/*!
* @brief Get Device address.
*
* @param USBx USB instance.
* @return The Device address.
*/
uint8_t USB_GetDeviceAddr(USB_Type * USBx);
/*!
* @brief Get buffer descriptor table address.
*
* @param USBx USB instance.
* @return The BufDespTable address.
*/
uint32_t USB_GetBufDespTableAddr(USB_Type * USBx);
/*!
* @brief Get the USB Frame Number.
*
* @param USBx USB instance.
* @return The USB Frame Number.
*/
uint32_t USB_GetFrameNumber(USB_Type * USBx);
/*!
* @brief Get BufDesp after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return BufDesp address.
*/
USB_BufDesp_Type * USB_GetBufDesp(USB_Type * USBx);
/*!
* @brief Get Token Pid from BufDesp before the BufDesp Reset.
*
* @param bd BufDesp addr.
* @return Token Pid.
*/
USB_TokenPid_Type USB_BufDesp_GetTokenPid(USB_BufDesp_Type * bd);
/*!
* @brief Get packet addr from BufDesp before the BufDesp Reset.
*
* @param bd BufDesp addr.
* @return Packet addrress.
*/
uint32_t USB_BufDesp_GetPacketAddr(USB_BufDesp_Type * bd);
/*!
* @brief Get packet size from BufDesp before the BufDesp Reset.
*
* @param bd BufDesp addr.
* @return Packet size.
*/
uint32_t USB_BufDesp_GetPacketSize(USB_BufDesp_Type * bd);
/*!
* @brief Reset BufDesp.
*
* @param bd BufDesp addr.
* @return None.
*/
void USB_BufDesp_Reset(USB_BufDesp_Type * bd);
/*!
* @brief Get EndPoint index after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return EndPoint index.
*/
uint32_t USB_GetEndPointIndex(USB_Type * USBx);
/*!
* @brief Get Xfer Direction after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return Xfer Direction, See to @ref USB_Direction_Type.
*/
USB_Direction_Type USB_GetXferDirection(USB_Type * USBx);
/*!
* @brief Get BufDesp OddEven after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return BufDesp OddEven.
*/
USB_BufDesp_OddEven_Type USB_GetBufDespOddEven(USB_Type * USBx);
/*!
* @brief Enable the end point.
*
* @param USBx USB instance.
* @param index endpoint index.
* @param mode End point mode, See to @ref USB_EndPointMode_Type.
* @param enable 'true' to enable the EndPoint, 'false' to disable the EndPoint.
* @return None.
*/
void USB_EnableEndPoint(USB_Type * USBx, uint32_t index, USB_EndPointMode_Type mode, bool enable);
/*!
* @brief Stall EndPoint n.
*
* @param USBx USB instance.
* @param ep_mask EndPoint mask, see to @ref USB_EP mask codes.
* @param enable 'true' to enable the EndPoint stall, 'false' to disable the EndPoint stall.
* @return None.
*/
void USB_EnableEndPointStall(USB_Type * USBx, uint32_t ep_mask, bool enable);
/*!
* @brief Get Enabled EndPoint stall status.
*
* @param USBx USB instance.
* @return stall status, see to @ref USB_EP mask codes.
*/
uint32_t USB_GetEnabledEndPointStall(USB_Type * USBx);
/*!
* @brief Xfer data by usb.
*
* @param bd BufDesp.
* @param data_n DATAn packet, n equal 0 or 1.
* @param data the address of data.
* @param len Data length.
* @return 'true': BufDesp can be xfer data, 'false': BufDesp is busy.
*/
bool USB_BufDesp_Xfer(USB_BufDesp_Type * bd, uint32_t data_n, uint8_t * data, uint32_t len);
/*!
* @brief Check whether BufDesp is busy.
*
* @param bd BufDesp addr.
* @return 'true': BufDesp is busy, 'false': BufDesp is not busy.
*/
bool USB_BufDesp_IsBusy(USB_BufDesp_Type * bd);
/*!
*@}
*/
#endif /* __HAL_USB_H__ */

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