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save 48bytes when no need to switch task in interrupt handler

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This commit is contained in:
acevest
2019-10-06 15:51:34 +08:00
parent e5e905e9bb
commit b147d060fb
7 changed files with 72 additions and 198 deletions
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1
board/QEMU_Spike/GCC/demo/Makefile
View File

@@ -54,7 +54,6 @@ ASM_SOURCES =
ASM_SOURCES_S = \
$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \
$(TOP_DIR)/arch/risc-v/spike/gcc/riscv_port_s.S \
start.S

3
board/QEMU_Spike/GCC/demo/start.S
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@@ -1,3 +1,4 @@
.extern rv32_exception_entry
.align 2
.section .text.entry
.globl _start
@@ -6,7 +7,7 @@ _start:
csrc mstatus, 0x00000008
csrw mie, 0
la t0, rv32_trap_entry
la t0, rv32_exception_entry
csrw mtvec, t0
la sp, _stack_top

2
board/QEMU_Spike/eclipse/demo/.cproject
View File

@@ -111,7 +111,7 @@
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/demo/Inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/demo/TencentOS_tiny/arch/risc-v/rv32i}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/demo/TencentOS_tiny/arch/risc-v/spike}&quot;"/>
</option>

4
board/QEMU_Spike/eclipse/demo/start.S
View File

@@ -1,4 +1,4 @@
.extern rv32_trap_entry
.extern rv32_exception_entry
.align 2
.section .text.entry
@@ -8,7 +8,7 @@ _start:
csrc mstatus, 0x00000008
csrw mie, 0
la t0, rv32_trap_entry
la t0, rv32_exception_entry
csrw mtvec, t0
la sp, _stack_top