PowLu/TencentOS-tiny
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

save 48bytes when no need to switch task in interrupt handler

Browse Source
This commit is contained in:
acevest
2019-10-06 15:51:34 +08:00
parent e5e905e9bb
commit b147d060fb
7 changed files with 72 additions and 198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/risc-v/common/tos_cpu.c
View File

@@ -129,7 +129,7 @@ void SysTick_IRQHandler() {
} }
} }
void cpu_irq_entry(cpu_data_t irq, cpu_context_t *regs) void cpu_irq_entry(cpu_data_t irq)
{ {
if (irq != 7) { if (irq != 7) {
return; return;

140
arch/risc-v/rv32i/gcc/port_s.S
View File

@@ -12,10 +12,10 @@
.global port_sched_start .global port_sched_start
.global port_context_switch .global port_context_switch
.global rv32_exception_entry
.extern k_curr_task .extern k_curr_task
.extern k_next_task .extern k_next_task
.extern k_task_irq_switch_flag
.equ MSTATUS_MIE, 0x00000008 .equ MSTATUS_MIE, 0x00000008
.equ MSTATUS_MPP, 0x00001800 .equ MSTATUS_MPP, 0x00001800
@@ -236,7 +236,43 @@ port_context_switch:
.align 2 .align 2
.global rv32_exception_entry .global rv32_exception_entry
rv32_exception_entry: rv32_exception_entry:
addi sp, sp, -32*REGBYTES addi sp, sp, -20*REGBYTES
sw ra, (12-12)*REGBYTES(sp)
sw gp, (13-12)*REGBYTES(sp)
sw tp, (14-12)*REGBYTES(sp)
sw t0, (15-12)*REGBYTES(sp)
sw t1, (16-12)*REGBYTES(sp)
sw t2, (17-12)*REGBYTES(sp)
sw t3, (18-12)*REGBYTES(sp)
sw t4, (19-12)*REGBYTES(sp)
sw t5, (20-12)*REGBYTES(sp)
sw t6, (21-12)*REGBYTES(sp)
sw a0, (22-12)*REGBYTES(sp)
sw a1, (23-12)*REGBYTES(sp)
sw a2, (24-12)*REGBYTES(sp)
sw a3, (25-12)*REGBYTES(sp)
sw a4, (26-12)*REGBYTES(sp)
sw a5, (27-12)*REGBYTES(sp)
sw a6, (28-12)*REGBYTES(sp)
sw a7, (29-12)*REGBYTES(sp)
csrr t0, mepc
sw t0, (30-12)*REGBYTES(sp)
csrr t0, mstatus
sw t0, (31-12)*REGBYTES(sp)
// get irq num and call irq handler
li t0, SOC_MCAUSE_EXP_MASK
csrr a0, mcause
and a0, a0, t0
call cpu_irq_entry
la t0, k_curr_task
la t1, k_next_task
beq t0, t1, irq_restore
addi sp, sp, -12*REGBYTES
sw s0, 0*REGBYTES(sp) sw s0, 0*REGBYTES(sp)
sw s1, 1*REGBYTES(sp) sw s1, 1*REGBYTES(sp)
sw s2, 2*REGBYTES(sp) sw s2, 2*REGBYTES(sp)
@@ -250,49 +286,6 @@ rv32_exception_entry:
sw s10, 10*REGBYTES(sp) sw s10, 10*REGBYTES(sp)
sw s11, 11*REGBYTES(sp) sw s11, 11*REGBYTES(sp)
// caller save
sw ra, 12*REGBYTES(sp)
sw gp, 13*REGBYTES(sp)
sw tp, 14*REGBYTES(sp)
sw t0, 15*REGBYTES(sp)
sw t1, 16*REGBYTES(sp)
sw t2, 17*REGBYTES(sp)
sw t3, 18*REGBYTES(sp)
sw t4, 19*REGBYTES(sp)
sw t5, 20*REGBYTES(sp)
sw t6, 21*REGBYTES(sp)
sw a0, 22*REGBYTES(sp)
sw a1, 23*REGBYTES(sp)
sw a2, 24*REGBYTES(sp)
sw a3, 25*REGBYTES(sp)
sw a4, 26*REGBYTES(sp)
sw a5, 27*REGBYTES(sp)
sw a6, 28*REGBYTES(sp)
sw a7, 29*REGBYTES(sp)
csrr t0, mepc
sw t0, 30*REGBYTES(sp)
csrr t0, mstatus
sw t0, 31*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
csrr a0, mcause
mv a1, sp
li t0, SOC_MCAUSE_EXP_MASK
and a0, a0, t0
call cpu_irq_entry
la t0, k_curr_task
la t1, k_next_task
beq t0, t1, irq_restore
// save sp to k_curr_task.sp // save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task la t0, k_curr_task // t0 = &k_curr_task
lw t2, (t0) // t2 = k_curr_task->sp lw t2, (t0) // t2 = k_curr_task->sp
@@ -305,15 +298,6 @@ rv32_exception_entry:
// load new task sp // load new task sp
lw sp, (t1) lw sp, (t1)
irq_restore:
// restore context
lw t0, 30*REGBYTES(sp)
csrw mepc, t0
lw t0, 31*REGBYTES(sp)
csrw mstatus, t0
lw s0, 0*REGBYTES(sp) lw s0, 0*REGBYTES(sp)
lw s1, 1*REGBYTES(sp) lw s1, 1*REGBYTES(sp)
lw s2, 2*REGBYTES(sp) lw s2, 2*REGBYTES(sp)
@@ -326,27 +310,35 @@ irq_restore:
lw s9, 9*REGBYTES(sp) lw s9, 9*REGBYTES(sp)
lw s10, 10*REGBYTES(sp) lw s10, 10*REGBYTES(sp)
lw s11, 11*REGBYTES(sp) lw s11, 11*REGBYTES(sp)
addi sp, sp, 12*REGBYTES
// caller save irq_restore:
lw ra, 12*REGBYTES(sp) // restore context
lw gp, 13*REGBYTES(sp) lw t0, (30-12)*REGBYTES(sp)
lw tp, 14*REGBYTES(sp) csrw mepc, t0
lw t0, 15*REGBYTES(sp)
lw t1, 16*REGBYTES(sp) lw t0, (31-12)*REGBYTES(sp)
lw t2, 17*REGBYTES(sp) csrw mstatus, t0
lw t3, 18*REGBYTES(sp)
lw t4, 19*REGBYTES(sp) lw ra, (12-12)*REGBYTES(sp)
lw t5, 20*REGBYTES(sp) lw gp, (13-12)*REGBYTES(sp)
lw t6, 21*REGBYTES(sp) lw tp, (14-12)*REGBYTES(sp)
lw a0, 22*REGBYTES(sp) lw t0, (15-12)*REGBYTES(sp)
lw a1, 23*REGBYTES(sp) lw t1, (16-12)*REGBYTES(sp)
lw a2, 24*REGBYTES(sp) lw t2, (17-12)*REGBYTES(sp)
lw a3, 25*REGBYTES(sp) lw t3, (18-12)*REGBYTES(sp)
lw a4, 26*REGBYTES(sp) lw t4, (19-12)*REGBYTES(sp)
lw a5, 27*REGBYTES(sp) lw t5, (20-12)*REGBYTES(sp)
lw a6, 28*REGBYTES(sp) lw t6, (21-12)*REGBYTES(sp)
lw a7, 29*REGBYTES(sp) lw a0, (22-12)*REGBYTES(sp)
addi sp, sp, 32*REGBYTES lw a1, (23-12)*REGBYTES(sp)
lw a2, (24-12)*REGBYTES(sp)
lw a3, (25-12)*REGBYTES(sp)
lw a4, (26-12)*REGBYTES(sp)
lw a5, (27-12)*REGBYTES(sp)
lw a6, (28-12)*REGBYTES(sp)
lw a7, (29-12)*REGBYTES(sp)
addi sp, sp, 20*REGBYTES
mret mret

118
arch/risc-v/spike/gcc/riscv_port_s.S
View File

@@ -1,118 +0,0 @@
#include "port.h"
.align 2
.global rv32_trap_entry
rv32_trap_entry:
addi sp, sp, -32*REGBYTES
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
csrr t0, mepc
sw t0, 0*REGBYTES(sp)
csrr t0, mstatus
sw t0, 1*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
csrr a0, mcause
mv a1, sp
bltz a0, handle_irq
call cpu_trap_entry
j irq_restore
handle_irq:
slli a0, a0, 1
srli a0, a0, 1
call cpu_irq_entry
la t0, k_curr_task
la t1, k_next_task
beq t0, t1, irq_restore
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t2, (t0)
sw sp, (t2)
// switch task
lw t1, (t1) // t1 = k_next_task
sw t1, (t0) // k_curr_task = k_next_task
// load new task sp
lw sp, (t1)
irq_restore:
// restore context
lw t0, 0*REGBYTES(sp)
csrw mepc, t0
lw t0, 1*REGBYTES(sp)
csrw mstatus, t0
lw x1, 2*REGBYTES(sp)
lw x3, 3*REGBYTES(sp)
lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
lw x6, 6*REGBYTES(sp)
lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
lw x9, 9*REGBYTES(sp)
lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
lw x12, 12*REGBYTES(sp)
lw x13, 13*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp)
lw x16, 16*REGBYTES(sp)
lw x17, 17*REGBYTES(sp)
lw x18, 18*REGBYTES(sp)
lw x19, 19*REGBYTES(sp)
lw x20, 20*REGBYTES(sp)
lw x21, 21*REGBYTES(sp)
lw x22, 22*REGBYTES(sp)
lw x23, 23*REGBYTES(sp)
lw x24, 24*REGBYTES(sp)
lw x25, 25*REGBYTES(sp)
lw x26, 26*REGBYTES(sp)
lw x27, 27*REGBYTES(sp)
lw x28, 28*REGBYTES(sp)
lw x29, 29*REGBYTES(sp)
lw x30, 30*REGBYTES(sp)
lw x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret

1
board/QEMU_Spike/GCC/demo/Makefile
View File

@@ -54,7 +54,6 @@ ASM_SOURCES =
ASM_SOURCES_S = \ ASM_SOURCES_S = \
$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \ $(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \
$(TOP_DIR)/arch/risc-v/spike/gcc/riscv_port_s.S \
start.S start.S

3
board/QEMU_Spike/GCC/demo/start.S
View File

@@ -1,3 +1,4 @@
.extern rv32_exception_entry
.align 2 .align 2
.section .text.entry .section .text.entry
.globl _start .globl _start
@@ -6,7 +7,7 @@ _start:
csrc mstatus, 0x00000008 csrc mstatus, 0x00000008
csrw mie, 0 csrw mie, 0
la t0, rv32_trap_entry la t0, rv32_exception_entry
csrw mtvec, t0 csrw mtvec, t0
la sp, _stack_top la sp, _stack_top

2
board/QEMU_Spike/eclipse/demo/.cproject
View File

@@ -111,7 +111,7 @@
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/demo/Inc}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/demo/Inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/demo/TencentOS_tiny/arch/risc-v/rv32i}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/demo/TencentOS_tiny/arch/risc-v/spike}&quot;"/>
</option> </option>

4
board/QEMU_Spike/eclipse/demo/start.S
View File

@@ -1,4 +1,4 @@
.extern rv32_trap_entry .extern rv32_exception_entry
.align 2 .align 2
.section .text.entry .section .text.entry
@@ -8,7 +8,7 @@ _start:
csrc mstatus, 0x00000008 csrc mstatus, 0x00000008
csrw mie, 0 csrw mie, 0
la t0, rv32_trap_entry la t0, rv32_exception_entry
csrw mtvec, t0 csrw mtvec, t0
la sp, _stack_top la sp, _stack_top