organize risc-v code for spike and bumblebee

This commit is contained in:
acevest
2019-09-25 21:53:27 +08:00
parent 379427f879
commit b1b2d1eabc
15 changed files with 129 additions and 30 deletions

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _RISCV_PORT_H_
#define _RISCV_PORT_H_
#define CLINT_CTRL_ADDR 0xD1000000
#define CLINT_MSIP 0x0FFC
#define CLINT_MTIMECMP 0x0008
#define CLINT_MTIME 0x0000
void riscv_cpu_init();
#endif // _RISCV_PORT_H_

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#include "gd32vf103.h"
void riscv_cpu_init() {
eclic_irq_enable(CLIC_INT_TMR, 0, 0);
}