From b76a703108cbe295cf6bba8ba6f1415fe84057c2 Mon Sep 17 00:00:00 2001 From: Grey Huang <102242739@qq.com> Date: Fri, 25 Oct 2019 18:47:35 +0800 Subject: [PATCH] change files --- arch/arm/arm-v8m/cortex-m23/armcc/port_c.c | 2 +- .../TencentOS_tiny.uvguix.Administrator | 1837 ++++++++++++++++ .../KEIL/hello_world/TencentOS_tiny.uvoptx | 8 +- .../KEIL/hello_world/TencentOS_tiny.uvprojx | 2 - .../RTE/_TencentOS_tiny/RTE_Components.h | 14 + .../TencentOS_tiny.uvguix.Administrator | 1810 ++++++++++++++++ .../KEIL/hello_world/TencentOS_tiny.uvoptx | 4 +- .../KEIL/hello_world/TencentOS_tiny.uvprojx | 2 - .../RTE/_TencentOS_tiny/RTE_Components.h | 6 - .../TencentOS_tiny.uvguix.Administrator | 1828 ++++++++++++++++ .../KEIL/hello_world/TencentOS_tiny.uvoptx | 6 +- .../KEIL/hello_world/TencentOS_tiny.uvprojx | 2 - .../{STARTUP/Include => BSP/Inc}/M251.h | 0 .../{STARTUP/Include => BSP/Inc}/NuMicro.h | 0 .../{STARTUP/Include => BSP/Inc}/acmp_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/bpwm_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/clk_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/crc_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/crypto_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/dac_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/eadc_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/ebi_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/fmc_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/gpio_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/i2c_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/opa_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/pdma_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/psio_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/pwm_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/qspi_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/rtc_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/sc_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/spi_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/sys_reg.h | 0 .../Include => BSP/Inc}/system_M251.h | 0 .../{STARTUP/Include => BSP/Inc}/timer_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/uart_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/ui2c_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/usbd_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/uspi_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/uuart_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/wdt_reg.h | 0 .../{STARTUP/Include => BSP/Inc}/wwdt_reg.h | 0 .../Nuvoton_M251/{Project => BSP/Src}/main.c | 1 - .../{STARTUP => BSP/Src}/system_M251.c | 3 - board/Nuvoton_M251/CMSIS/cmsis_version.h | 39 - board/Nuvoton_M251/CMSIS/core_armv8mbl.h | 1878 ----------------- board/Nuvoton_M251/CMSIS/core_cm23.h | 1878 ----------------- .../{TencentOS => }/TOS_CONFIG/tos_config.h | 3 +- .../TencentOS/arch/include/tos_cpu.h | 124 -- .../TencentOS/arch/include/tos_cpu_def.h | 17 - .../TencentOS/arch/include/tos_cpu_types.h | 40 - .../TencentOS/arch/include/tos_fault.h | 219 -- board/Nuvoton_M251/TencentOS/arch/port.h | 73 - board/Nuvoton_M251/TencentOS/arch/port_c.c | 129 -- .../Nuvoton_M251/TencentOS/arch/port_config.h | 29 - board/Nuvoton_M251/TencentOS/arch/port_s.S | 137 -- board/Nuvoton_M251/TencentOS/arch/tos_cpu.c | 276 --- board/Nuvoton_M251/TencentOS/arch/tos_fault.c | 251 --- .../TencentOS/kernel/core/include/tos.h | 40 - .../kernel/core/include/tos_compiler.h | 110 - .../kernel/core/include/tos_config_check.h | 61 - .../kernel/core/include/tos_config_default.h | 114 - .../TencentOS/kernel/core/include/tos_err.h | 83 - .../TencentOS/kernel/core/include/tos_event.h | 116 - .../TencentOS/kernel/core/include/tos_fifo.h | 146 -- .../kernel/core/include/tos_global.h | 85 - .../TencentOS/kernel/core/include/tos_klib.h | 38 - .../kernel/core/include/tos_ktypes.h | 30 - .../TencentOS/kernel/core/include/tos_list.h | 103 - .../TencentOS/kernel/core/include/tos_mmblk.h | 90 - .../kernel/core/include/tos_mmheap.h | 207 -- .../TencentOS/kernel/core/include/tos_msg.h | 97 - .../TencentOS/kernel/core/include/tos_mutex.h | 97 - .../TencentOS/kernel/core/include/tos_pend.h | 67 - .../TencentOS/kernel/core/include/tos_queue.h | 102 - .../TencentOS/kernel/core/include/tos_robin.h | 42 - .../TencentOS/kernel/core/include/tos_sched.h | 35 - .../TencentOS/kernel/core/include/tos_sem.h | 86 - .../TencentOS/kernel/core/include/tos_sys.h | 143 -- .../TencentOS/kernel/core/include/tos_task.h | 311 --- .../TencentOS/kernel/core/include/tos_tick.h | 27 - .../TencentOS/kernel/core/include/tos_time.h | 93 - .../TencentOS/kernel/core/include/tos_timer.h | 136 -- .../TencentOS/kernel/core/tos_event.c | 168 -- .../TencentOS/kernel/core/tos_fifo.c | 196 -- .../TencentOS/kernel/core/tos_global.c | 69 - .../TencentOS/kernel/core/tos_mmblk.c | 118 -- .../TencentOS/kernel/core/tos_mmheap.c | 685 ------ .../TencentOS/kernel/core/tos_msg.c | 142 -- .../TencentOS/kernel/core/tos_mutex.c | 205 -- .../TencentOS/kernel/core/tos_pend.c | 138 -- .../TencentOS/kernel/core/tos_queue.c | 170 -- .../TencentOS/kernel/core/tos_robin.c | 92 - .../TencentOS/kernel/core/tos_sched.c | 171 -- .../TencentOS/kernel/core/tos_sem.c | 124 -- .../TencentOS/kernel/core/tos_sys.c | 262 --- .../TencentOS/kernel/core/tos_task.c | 416 ---- .../TencentOS/kernel/core/tos_tick.c | 143 -- .../TencentOS/kernel/core/tos_time.c | 49 - .../TencentOS/kernel/core/tos_timer.c | 329 --- .../TencentOS/kernel/hal/include/tos_hal.h | 9 - .../TencentOS/kernel/hal/include/tos_hal_sd.h | 49 - .../kernel/hal/include/tos_hal_uart.h | 28 - .../TencentOS/kernel/pm/include/tos_pm.h | 85 - .../kernel/pm/include/tos_tickless.h | 28 - .../Nuvoton_M251/TencentOS/kernel/pm/tos_pm.c | 144 -- .../TencentOS/kernel/pm/tos_tickless.c | 144 -- .../Nu_Link_Driver.ini | 0 .../NuvotonTos.uvguix.Administrator | 392 ++-- .../NuvotonTos.uvoptx | 132 +- .../NuvotonTos.uvprojx | 100 +- .../Objects/NuvotonTos.build_log.htm | 14 +- .../Objects/NuvotonTos.htm | 530 ++--- .../Objects/NuvotonTos.sct | 0 .../RTE/_Target_1/RTE_Components.h | 0 .../{STARTUP => hello world}/startup_M251.s | 0 .../RTE/_STM32F746NGH6/RTE_Components.h | 14 + .../STM32F746NGH6.uvguix.Administrator | 1828 ++++++++++++++++ .../KEIL/hello_world/STM32F746NGH6.uvoptx | 13 +- .../KEIL/hello_world/STM32F746NGH6.uvprojx | 2 - kernel/core/include/tos.h | 2 +- .../Nuvoton_M251/StdDriver/inc/acmp.h | 0 .../Nuvoton_M251/StdDriver/inc/bpwm.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/clk.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/crc.h | 0 .../Nuvoton_M251/StdDriver/inc/crypto.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/dac.h | 0 .../Nuvoton_M251/StdDriver/inc/eadc.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/ebi.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/fmc.h | 0 .../Nuvoton_M251/StdDriver/inc/gpio.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/i2c.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/opa.h | 0 .../Nuvoton_M251/StdDriver/inc/pdma.h | 0 .../Nuvoton_M251/StdDriver/inc/psio.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/pwm.h | 0 .../Nuvoton_M251/StdDriver/inc/qspi.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/rtc.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/sc.h | 0 .../Nuvoton_M251/StdDriver/inc/scuart.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/spi.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/sys.h | 0 .../Nuvoton_M251/StdDriver/inc/timer.h | 0 .../Nuvoton_M251/StdDriver/inc/timer_pwm.h | 0 .../Nuvoton_M251/StdDriver/inc/uart.h | 0 .../Nuvoton_M251/StdDriver/inc/usbd.h | 0 .../Nuvoton_M251/StdDriver/inc/usci_i2c.h | 0 .../Nuvoton_M251/StdDriver/inc/usci_spi.h | 0 .../Nuvoton_M251/StdDriver/inc/usci_uart.h | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/inc/wdt.h | 0 .../Nuvoton_M251/StdDriver/inc/wwdt.h | 0 .../Nuvoton_M251/StdDriver/src/acmp.c | 0 .../Nuvoton_M251/StdDriver/src/bpwm.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/clk.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/crc.c | 0 .../Nuvoton_M251/StdDriver/src/crypto.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/dac.c | 0 .../Nuvoton_M251/StdDriver/src/eadc.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/ebi.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/fmc.c | 0 .../Nuvoton_M251/StdDriver/src/gpio.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/i2c.c | 0 .../Nuvoton_M251/StdDriver/src/pdma.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/pwm.c | 0 .../Nuvoton_M251/StdDriver/src/qspi.c | 0 .../Nuvoton_M251/StdDriver/src/retarget.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/rtc.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/sc.c | 0 .../Nuvoton_M251/StdDriver/src/scuart.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/spi.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/sys.c | 0 .../Nuvoton_M251/StdDriver/src/timer.c | 0 .../Nuvoton_M251/StdDriver/src/timer_pwm.c | 0 .../Nuvoton_M251/StdDriver/src/uart.c | 0 .../Nuvoton_M251/StdDriver/src/usbd.c | 0 .../Nuvoton_M251/StdDriver/src/usci_i2c.c | 0 .../Nuvoton_M251/StdDriver/src/usci_spi.c | 0 .../Nuvoton_M251/StdDriver/src/usci_uart.c | 0 .../Nuvoton}/Nuvoton_M251/StdDriver/src/wdt.c | 0 .../Nuvoton_M251/StdDriver/src/wwdt.c | 0 181 files changed, 7927 insertions(+), 12141 deletions(-) create mode 100644 board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator create mode 100644 board/NXP_LPC824Lite/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h create mode 100644 board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator create mode 100644 board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/M251.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/NuMicro.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/acmp_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/bpwm_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/clk_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/crc_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/crypto_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/dac_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/eadc_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/ebi_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/fmc_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/gpio_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/i2c_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/opa_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/pdma_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/psio_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/pwm_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/qspi_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/rtc_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/sc_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/spi_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/sys_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/system_M251.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/timer_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/uart_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/ui2c_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/usbd_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/uspi_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/uuart_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/wdt_reg.h (100%) rename board/Nuvoton_M251/{STARTUP/Include => BSP/Inc}/wwdt_reg.h (100%) rename board/Nuvoton_M251/{Project => BSP/Src}/main.c (99%) rename board/Nuvoton_M251/{STARTUP => BSP/Src}/system_M251.c (95%) delete mode 100644 board/Nuvoton_M251/CMSIS/cmsis_version.h delete mode 100644 board/Nuvoton_M251/CMSIS/core_armv8mbl.h delete mode 100644 board/Nuvoton_M251/CMSIS/core_cm23.h rename board/Nuvoton_M251/{TencentOS => }/TOS_CONFIG/tos_config.h (93%) delete mode 100644 board/Nuvoton_M251/TencentOS/arch/include/tos_cpu.h delete mode 100644 board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_def.h delete mode 100644 board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_types.h delete mode 100644 board/Nuvoton_M251/TencentOS/arch/include/tos_fault.h delete mode 100644 board/Nuvoton_M251/TencentOS/arch/port.h delete mode 100644 board/Nuvoton_M251/TencentOS/arch/port_c.c delete mode 100644 board/Nuvoton_M251/TencentOS/arch/port_config.h delete mode 100644 board/Nuvoton_M251/TencentOS/arch/port_s.S delete mode 100644 board/Nuvoton_M251/TencentOS/arch/tos_cpu.c delete mode 100644 board/Nuvoton_M251/TencentOS/arch/tos_fault.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_compiler.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_check.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_default.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_err.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_event.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_fifo.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_global.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_klib.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_ktypes.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_list.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmblk.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmheap.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_msg.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mutex.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_pend.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_queue.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_robin.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sched.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sem.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sys.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_task.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_tick.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_time.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/include/tos_timer.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_event.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_fifo.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_global.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_mmblk.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_mmheap.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_msg.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_mutex.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_pend.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_queue.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_robin.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_sched.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_sem.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_sys.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_task.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_tick.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_time.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/core/tos_timer.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_sd.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_uart.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_pm.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_tickless.h delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/pm/tos_pm.c delete mode 100644 board/Nuvoton_M251/TencentOS/kernel/pm/tos_tickless.c rename board/Nuvoton_M251/{Project => hello world}/Nu_Link_Driver.ini (100%) rename board/Nuvoton_M251/{Project => hello world}/NuvotonTos.uvguix.Administrator (82%) rename board/Nuvoton_M251/{Project => hello world}/NuvotonTos.uvoptx (82%) rename board/Nuvoton_M251/{Project => hello world}/NuvotonTos.uvprojx (85%) rename board/Nuvoton_M251/{Project => hello world}/Objects/NuvotonTos.build_log.htm (90%) rename board/Nuvoton_M251/{Project => hello world}/Objects/NuvotonTos.htm (82%) rename board/Nuvoton_M251/{Project => hello world}/Objects/NuvotonTos.sct (100%) rename board/Nuvoton_M251/{Project => hello world}/RTE/_Target_1/RTE_Components.h (100%) rename board/Nuvoton_M251/{STARTUP => hello world}/startup_M251.s (100%) create mode 100644 board/STM32F746NGH6_discovery/KEIL/hello_world/RTE/_STM32F746NGH6/RTE_Components.h create mode 100644 board/STM32F746NGH6_discovery/KEIL/hello_world/STM32F746NGH6.uvguix.Administrator rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/acmp.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/bpwm.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/clk.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/crc.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/crypto.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/dac.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/eadc.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/ebi.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/fmc.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/gpio.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/i2c.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/opa.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/pdma.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/psio.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/pwm.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/qspi.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/rtc.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/sc.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/scuart.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/spi.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/sys.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/timer.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/timer_pwm.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/uart.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/usbd.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/usci_i2c.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/usci_spi.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/usci_uart.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/wdt.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/inc/wwdt.h (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/acmp.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/bpwm.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/clk.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/crc.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/crypto.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/dac.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/eadc.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/ebi.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/fmc.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/gpio.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/i2c.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/pdma.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/pwm.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/qspi.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/retarget.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/rtc.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/sc.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/scuart.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/spi.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/sys.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/timer.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/timer_pwm.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/uart.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/usbd.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/usci_i2c.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/usci_spi.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/usci_uart.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/wdt.c (100%) rename {board => platform/vendor_bsp/Nuvoton}/Nuvoton_M251/StdDriver/src/wwdt.c (100%) diff --git a/arch/arm/arm-v8m/cortex-m23/armcc/port_c.c b/arch/arm/arm-v8m/cortex-m23/armcc/port_c.c index b2e55608..70189783 100644 --- a/arch/arm/arm-v8m/cortex-m23/armcc/port_c.c +++ b/arch/arm/arm-v8m/cortex-m23/armcc/port_c.c @@ -16,7 +16,7 @@ *---------------------------------------------------------------------------*/ #include "tos.h" -#include "core_cm0plus.h" +#include "core_armv8mbl.h" __PORT__ void port_cpu_reset(void) { diff --git a/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator b/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator new file mode 100644 index 00000000..c25867c1 --- /dev/null +++ b/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator @@ -0,0 +1,1837 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 1 + + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S + 0 + 144 + 1 + 1 + + 0 + + + ..\..\..\..\osal\cmsis_os\cmsis_os.c + 0 + 1 + 1 + 1 + + 0 + + + + + diff --git a/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvoptx b/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvoptx index b3b425ec..59aa8162 100644 --- a/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvoptx +++ b/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvoptx @@ -101,9 +101,7 @@ 0 0 1 - 0 - 0 - 4 + 3 @@ -560,7 +558,7 @@ tos/arch - 0 + 1 0 0 0 @@ -604,7 +602,7 @@ tos/kernel - 0 + 1 0 0 0 diff --git a/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvprojx b/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvprojx index eb8f6cb8..4ed614e3 100644 --- a/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvprojx +++ b/board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvprojx @@ -184,7 +184,6 @@ 0 0 2 - 0 1 0 8 @@ -325,7 +324,6 @@ 0 0 1 - 1 0 1 1 diff --git a/board/NXP_LPC824Lite/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h b/board/NXP_LPC824Lite/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h new file mode 100644 index 00000000..152b308c --- /dev/null +++ b/board/NXP_LPC824Lite/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h @@ -0,0 +1,14 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'TencentOS_tiny' + * Target: 'TencentOS_tiny' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +#endif /* RTE_COMPONENTS_H */ diff --git a/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator b/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator new file mode 100644 index 00000000..b5162e1b --- /dev/null +++ b/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator @@ -0,0 +1,1810 @@ + + + + -6.1 + +
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+ + + + 0 + 1920 + 1080 + + + + + diff --git a/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvoptx b/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvoptx index 3ff71778..7db2f626 100644 --- a/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvoptx +++ b/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvoptx @@ -101,9 +101,7 @@ 0 0 1 - 0 - 0 - 3 + 2 diff --git a/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvprojx b/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvprojx index 0a89a9a5..3325a818 100644 --- a/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvprojx +++ b/board/NXP_LPC824Lite/KEIL/hello_world/TencentOS_tiny.uvprojx @@ -184,7 +184,6 @@ 0 0 0 - 0 0 0 8 @@ -325,7 +324,6 @@ 0 0 1 - 0 0 1 1 diff --git a/board/Nordic_NRF52832/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h b/board/Nordic_NRF52832/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h index 62ca151f..152b308c 100644 --- a/board/Nordic_NRF52832/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h +++ b/board/Nordic_NRF52832/KEIL/hello_world/RTE/_TencentOS_tiny/RTE_Components.h @@ -11,10 +11,4 @@ #define RTE_COMPONENTS_H -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "nrf.h" - - #endif /* RTE_COMPONENTS_H */ diff --git a/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator b/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator new file mode 100644 index 00000000..f8fb4b30 --- /dev/null +++ b/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvguix.Administrator @@ -0,0 +1,1828 @@ + + + + -6.1 + +
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 0 + + ..\..\TOS_CONFIG\tos_config.h + 40 + 1 + 20 + 1 + + 0 + + + + + diff --git a/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvoptx b/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvoptx index ab365b7b..3a63f807 100644 --- a/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvoptx +++ b/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvoptx @@ -101,9 +101,7 @@ 0 0 1 - 0 - 0 - 6 + 5 @@ -616,7 +614,7 @@ CONFIG - 0 + 1 0 0 0 diff --git a/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvprojx b/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvprojx index a60c400a..04308f31 100644 --- a/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvprojx +++ b/board/Nordic_NRF52832/KEIL/hello_world/TencentOS_tiny.uvprojx @@ -184,7 +184,6 @@ 0 0 2 - 0 0 0 8 @@ -325,7 +324,6 @@ 0 0 1 - 0 0 1 1 diff --git a/board/Nuvoton_M251/STARTUP/Include/M251.h b/board/Nuvoton_M251/BSP/Inc/M251.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/M251.h rename to board/Nuvoton_M251/BSP/Inc/M251.h diff --git a/board/Nuvoton_M251/STARTUP/Include/NuMicro.h b/board/Nuvoton_M251/BSP/Inc/NuMicro.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/NuMicro.h rename to board/Nuvoton_M251/BSP/Inc/NuMicro.h diff --git a/board/Nuvoton_M251/STARTUP/Include/acmp_reg.h b/board/Nuvoton_M251/BSP/Inc/acmp_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/acmp_reg.h rename to board/Nuvoton_M251/BSP/Inc/acmp_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/bpwm_reg.h b/board/Nuvoton_M251/BSP/Inc/bpwm_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/bpwm_reg.h rename to board/Nuvoton_M251/BSP/Inc/bpwm_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/clk_reg.h b/board/Nuvoton_M251/BSP/Inc/clk_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/clk_reg.h rename to board/Nuvoton_M251/BSP/Inc/clk_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/crc_reg.h b/board/Nuvoton_M251/BSP/Inc/crc_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/crc_reg.h rename to board/Nuvoton_M251/BSP/Inc/crc_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/crypto_reg.h b/board/Nuvoton_M251/BSP/Inc/crypto_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/crypto_reg.h rename to board/Nuvoton_M251/BSP/Inc/crypto_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/dac_reg.h b/board/Nuvoton_M251/BSP/Inc/dac_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/dac_reg.h rename to board/Nuvoton_M251/BSP/Inc/dac_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/eadc_reg.h b/board/Nuvoton_M251/BSP/Inc/eadc_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/eadc_reg.h rename to board/Nuvoton_M251/BSP/Inc/eadc_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/ebi_reg.h b/board/Nuvoton_M251/BSP/Inc/ebi_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/ebi_reg.h rename to board/Nuvoton_M251/BSP/Inc/ebi_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/fmc_reg.h b/board/Nuvoton_M251/BSP/Inc/fmc_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/fmc_reg.h rename to board/Nuvoton_M251/BSP/Inc/fmc_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/gpio_reg.h b/board/Nuvoton_M251/BSP/Inc/gpio_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/gpio_reg.h rename to board/Nuvoton_M251/BSP/Inc/gpio_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/i2c_reg.h b/board/Nuvoton_M251/BSP/Inc/i2c_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/i2c_reg.h rename to board/Nuvoton_M251/BSP/Inc/i2c_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/opa_reg.h b/board/Nuvoton_M251/BSP/Inc/opa_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/opa_reg.h rename to board/Nuvoton_M251/BSP/Inc/opa_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/pdma_reg.h b/board/Nuvoton_M251/BSP/Inc/pdma_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/pdma_reg.h rename to board/Nuvoton_M251/BSP/Inc/pdma_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/psio_reg.h b/board/Nuvoton_M251/BSP/Inc/psio_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/psio_reg.h rename to board/Nuvoton_M251/BSP/Inc/psio_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/pwm_reg.h b/board/Nuvoton_M251/BSP/Inc/pwm_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/pwm_reg.h rename to board/Nuvoton_M251/BSP/Inc/pwm_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/qspi_reg.h b/board/Nuvoton_M251/BSP/Inc/qspi_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/qspi_reg.h rename to board/Nuvoton_M251/BSP/Inc/qspi_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/rtc_reg.h b/board/Nuvoton_M251/BSP/Inc/rtc_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/rtc_reg.h rename to board/Nuvoton_M251/BSP/Inc/rtc_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/sc_reg.h b/board/Nuvoton_M251/BSP/Inc/sc_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/sc_reg.h rename to board/Nuvoton_M251/BSP/Inc/sc_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/spi_reg.h b/board/Nuvoton_M251/BSP/Inc/spi_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/spi_reg.h rename to board/Nuvoton_M251/BSP/Inc/spi_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/sys_reg.h b/board/Nuvoton_M251/BSP/Inc/sys_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/sys_reg.h rename to board/Nuvoton_M251/BSP/Inc/sys_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/system_M251.h b/board/Nuvoton_M251/BSP/Inc/system_M251.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/system_M251.h rename to board/Nuvoton_M251/BSP/Inc/system_M251.h diff --git a/board/Nuvoton_M251/STARTUP/Include/timer_reg.h b/board/Nuvoton_M251/BSP/Inc/timer_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/timer_reg.h rename to board/Nuvoton_M251/BSP/Inc/timer_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/uart_reg.h b/board/Nuvoton_M251/BSP/Inc/uart_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/uart_reg.h rename to board/Nuvoton_M251/BSP/Inc/uart_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/ui2c_reg.h b/board/Nuvoton_M251/BSP/Inc/ui2c_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/ui2c_reg.h rename to board/Nuvoton_M251/BSP/Inc/ui2c_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/usbd_reg.h b/board/Nuvoton_M251/BSP/Inc/usbd_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/usbd_reg.h rename to board/Nuvoton_M251/BSP/Inc/usbd_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/uspi_reg.h b/board/Nuvoton_M251/BSP/Inc/uspi_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/uspi_reg.h rename to board/Nuvoton_M251/BSP/Inc/uspi_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/uuart_reg.h b/board/Nuvoton_M251/BSP/Inc/uuart_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/uuart_reg.h rename to board/Nuvoton_M251/BSP/Inc/uuart_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/wdt_reg.h b/board/Nuvoton_M251/BSP/Inc/wdt_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/wdt_reg.h rename to board/Nuvoton_M251/BSP/Inc/wdt_reg.h diff --git a/board/Nuvoton_M251/STARTUP/Include/wwdt_reg.h b/board/Nuvoton_M251/BSP/Inc/wwdt_reg.h similarity index 100% rename from board/Nuvoton_M251/STARTUP/Include/wwdt_reg.h rename to board/Nuvoton_M251/BSP/Inc/wwdt_reg.h diff --git a/board/Nuvoton_M251/Project/main.c b/board/Nuvoton_M251/BSP/Src/main.c similarity index 99% rename from board/Nuvoton_M251/Project/main.c rename to board/Nuvoton_M251/BSP/Src/main.c index 6131a942..a3ff2469 100644 --- a/board/Nuvoton_M251/Project/main.c +++ b/board/Nuvoton_M251/BSP/Src/main.c @@ -69,7 +69,6 @@ void task1_fun(void *Parameter) } -//task2 function void task2_task(void *Parameter) { diff --git a/board/Nuvoton_M251/STARTUP/system_M251.c b/board/Nuvoton_M251/BSP/Src/system_M251.c similarity index 95% rename from board/Nuvoton_M251/STARTUP/system_M251.c rename to board/Nuvoton_M251/BSP/Src/system_M251.c index 47377129..95efa0d5 100644 --- a/board/Nuvoton_M251/STARTUP/system_M251.c +++ b/board/Nuvoton_M251/BSP/Src/system_M251.c @@ -140,9 +140,6 @@ void Uart0DefaultMPF(void) { /* Set GPB multi-function pins for UART0 RXD and TXD */ - // SYS->GPB_MFPH = (SYS->GPB_MFPH & ~SYS_GPB_MFPH_PB12MFP_Msk) | SYS_GPB_MFPH_PB12MFP_UART0_RXD; - // SYS->GPB_MFPH = (SYS->GPB_MFPH & ~SYS_GPB_MFPH_PB13MFP_Msk) | SYS_GPB_MFPH_PB13MFP_UART0_TXD; - SYS->GPA_MFPL = (SYS->GPA_MFPL & ~SYS_GPA_MFPL_PA0MFP_Msk) | SYS_GPA_MFPL_PA0MFP_UART0_RXD; SYS->GPA_MFPL = (SYS->GPA_MFPL & ~SYS_GPA_MFPL_PA1MFP_Msk) | SYS_GPA_MFPL_PA1MFP_UART0_TXD; diff --git a/board/Nuvoton_M251/CMSIS/cmsis_version.h b/board/Nuvoton_M251/CMSIS/cmsis_version.h deleted file mode 100644 index d458a6c8..00000000 --- a/board/Nuvoton_M251/CMSIS/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/board/Nuvoton_M251/CMSIS/core_armv8mbl.h b/board/Nuvoton_M251/CMSIS/core_armv8mbl.h deleted file mode 100644 index 13003e1c..00000000 --- a/board/Nuvoton_M251/CMSIS/core_armv8mbl.h +++ /dev/null @@ -1,1878 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/board/Nuvoton_M251/CMSIS/core_cm23.h b/board/Nuvoton_M251/CMSIS/core_cm23.h deleted file mode 100644 index b97fa9dd..00000000 --- a/board/Nuvoton_M251/CMSIS/core_cm23.h +++ /dev/null @@ -1,1878 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/board/Nuvoton_M251/TencentOS/TOS_CONFIG/tos_config.h b/board/Nuvoton_M251/TOS_CONFIG/tos_config.h similarity index 93% rename from board/Nuvoton_M251/TencentOS/TOS_CONFIG/tos_config.h rename to board/Nuvoton_M251/TOS_CONFIG/tos_config.h index faa25daa..87fef541 100644 --- a/board/Nuvoton_M251/TencentOS/TOS_CONFIG/tos_config.h +++ b/board/Nuvoton_M251/TOS_CONFIG/tos_config.h @@ -1,7 +1,6 @@ #ifndef _TOS_CONFIG_H_ #define _TOS_CONFIG_H_ -//#include "stm32f10x.h" #include "M251.h" //change your mcu #include @@ -17,7 +16,7 @@ #define TOS_CFG_MMHEAP_EN 1u -#define TOS_CFG_MMHEAP_POOL_SIZE 0x100 +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x100 #define TOS_CFG_MUTEX_EN 1u diff --git a/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu.h b/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu.h deleted file mode 100644 index 955789bb..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu.h +++ /dev/null @@ -1,124 +0,0 @@ -#ifndef _TOS_CPU_H_ -#define _TOS_CPU_H_ - -typedef struct cpu_context_st { - cpu_data_t _R4; - cpu_data_t _R5; - cpu_data_t _R6; - cpu_data_t _R7; - cpu_data_t _R8; - cpu_data_t _R9; - cpu_data_t _R10; - cpu_data_t _R11; -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - cpu_data_t EXC_RETURN; -#endif - cpu_data_t _R0; - cpu_data_t _R1; - cpu_data_t _R2; - cpu_data_t _R3; - cpu_data_t _R12; - cpu_data_t _R14; - cpu_data_t _PC; - cpu_data_t _xPSR; -} cpu_context_t; - -__API__ uint32_t tos_cpu_clz(uint32_t val); - -__API__ void tos_cpu_int_disable(void); - -__API__ void tos_cpu_int_enable(void); - -__API__ cpu_cpsr_t tos_cpu_cpsr_save(void); - -__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr); - -#if (TOS_CFG_CPU_HRTIMER_EN > 0u) - -__API__ void tos_cpu_hrtimer_init(void); - -__API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); - -#endif - -__KERNEL__ void cpu_init(void); - -__KERNEL__ void cpu_reset(void); - -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); - -__KERNEL__ void cpu_sched_start(void); - -__KERNEL__ void cpu_context_switch(void); - -__KERNEL__ void cpu_irq_context_switch(void); - -#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u - -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); - -#endif - -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, - void *arg, - void *exit, - k_stack_t *stk_base, - size_t stk_size); - -#if TOS_CFG_TICKLESS_EN > 0u - -__KERNEL__ void cpu_systick_resume(void); - -__KERNEL__ void cpu_systick_suspend(void); - -__KERNEL__ void cpu_systick_reload_reset(void); - -__KERNEL__ void cpu_systick_pending_reset(void); - -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); - -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); - -__KERNEL__ void cpu_systick_reset(void); - -#endif - -#if TOS_CFG_PWR_MGR_EN > 0u - -__KERNEL__ void cpu_sleep_mode_enter(void); - -__KERNEL__ void cpu_stop_mode_enter(void); - -__KERNEL__ void cpu_standby_mode_enter(void); - -#endif - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - -__KERNEL__ void cpu_flush_fpu(void); - -#endif /* TOS_CFG_CPU_ARM_FPU_EN */ - -__KERNEL__ void cpu_fault_diagnosis(void); - -#endif - -/* Allocates CPU status register word. */ -#define TOS_CPU_CPSR_ALLOC() cpu_cpsr_t cpu_cpsr = (cpu_cpsr_t)0u - -/* Save CPU status word & disable interrupts.*/ -#define TOS_CPU_INT_DISABLE() \ - do { \ - cpu_cpsr = tos_cpu_cpsr_save(); \ - } while (0) - -/* Restore CPU status word. */ -#define TOS_CPU_INT_ENABLE() \ - do { \ - tos_cpu_cpsr_restore(cpu_cpsr); \ - } while (0) - -#endif /* _TOS_CPU_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_def.h b/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_def.h deleted file mode 100644 index cde7ce52..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_def.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _TOS_CPU_DEF_H_ -#define _TOS_CPU_DEF_H_ - -enum CPU_WORD_SIZE { - CPU_WORD_SIZE_08, - CPU_WORD_SIZE_16, - CPU_WORD_SIZE_32, - CPU_WORD_SIZE_64, -}; - -enum CPU_STK_GROWTH { - CPU_STK_GROWTH_ASCENDING, - CPU_STK_GROWTH_DESCENDING, -}; - -#endif /* _TOS_CPU_DEF_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_types.h b/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_types.h deleted file mode 100644 index 6027a354..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/include/tos_cpu_types.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef _TOS_CPU_TYPES_H_ -#define _TOS_CPU_TYPES_H_ - -/* CPU address type based on address bus size. */ -#if (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_32) -typedef uint32_t cpu_addr_t; -#elif (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_16) -typedef uint16_t cpu_addr_t; -#else -typedef uint8_t cpu_addr_t; -#endif - -/* CPU data type based on data bus size. */ -#if (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_32) -typedef uint32_t cpu_data_t; -#elif (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_16) -typedef uint16_t cpu_data_t; -#else -typedef uint8_t cpu_data_t; -#endif - -#if (TOS_CFG_CPU_HRTIMER_EN > 0) -#if (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_08) -typedef uint8_t cpu_hrtimer_t; -#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_16) -typedef uint16_t cpu_hrtimer_t; -#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_64) -typedef uint64_t cpu_hrtimer_t; -#else -typedef uint32_t cpu_hrtimer_t; -#endif -#else -typedef uint32_t cpu_hrtimer_t; -#endif - -//typedef cpu_addr_t size_t; -typedef cpu_addr_t cpu_cpsr_t; - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/arch/include/tos_fault.h b/board/Nuvoton_M251/TencentOS/arch/include/tos_fault.h deleted file mode 100644 index f2e17269..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/include/tos_fault.h +++ /dev/null @@ -1,219 +0,0 @@ -#ifndef _TOS_FAULT_H_ -#define _TOS_FAULT_H_ - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u - -typedef int (*k_fault_log_writer_t)(const char *format, ...); - -#define K_FAULT_STACK_DUMP_DEPTH 10u - -#define K_FAULT_CALL_STACK_BACKTRACE_DEPTH 5u - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -typedef struct fault_fpu_frame_st { - cpu_data_t s0; - cpu_data_t s1; - cpu_data_t s2; - cpu_data_t s3; - cpu_data_t s4; - cpu_data_t s5; - cpu_data_t s6; - cpu_data_t s7; - cpu_data_t s8; - cpu_data_t s9; - cpu_data_t s10; - cpu_data_t s11; - cpu_data_t s12; - cpu_data_t s13; - cpu_data_t s14; - cpu_data_t s15; - cpu_data_t fpscr; -} fault_fpu_frame_t; -#endif - -typedef struct fault_cpu_frame_st { - cpu_data_t r0; - cpu_data_t r1; - cpu_data_t r2; - cpu_data_t r3; - cpu_data_t r12; - cpu_data_t lr; - cpu_data_t pc; - cpu_data_t spsr; -} fault_cpu_frame_t; - -typedef struct fault_exc_frame_st { - fault_cpu_frame_t cpu_frame; - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - fault_fpu_frame_t fpu_frame; -#endif -} fault_exc_frame_t; - -/** - * information we need to do fault backtrace - */ -typedef struct fault_information_st { - int is_thumb : 1; /**< whether it is thumb we use when we fall into fault? */ - int is_on_task : 1; /**< whether we are on a task when fall into fault? */ - int is_stk_ovrf : 1; /**< whether we get a stack overflow */ - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - int is_ext_stk_frm : 1; /**< whether it is a extended stack frame?(whether the cpu has pushed fpu registers onto the stack) */ -#endif - - cpu_addr_t pc; /**< just where fault happens */ - - cpu_addr_t sp_before_fault; /**< original sp just before the cpu push the fault exception frame */ - - /** - * we need main_stack_start & main_stack_limit to do call stack backtrace - * when we fall into fault during a task, we should do the call stack backtrace on the task's stack - * but if not, which means we are in kernel, we should do the call stack backtrace on the main stack - * in arm v7-m, this should be the MSP's start and limit - * in arm v7-a, call stack backtrace is another story(much more elegant because we have FP). - */ - cpu_addr_t stack_start; /**< current sp start address we use. if on task, it'll be the task's stack, otherwise it'll be the msp */ - cpu_addr_t stack_limit; /**< current sp limit address */ - cpu_addr_t code_start; /**< current code start address */ - cpu_addr_t code_limit; /**< current code limit address */ -} fault_info_t; - -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - -#define DEFAULT_CODE_SECTION_NAME ER_IROM1 -#define DEFAULT_CSTACK_SECTION_NAME STACK - -#define SECTION_START(_name_) _name_##$$Base -#define SECTION_END(_name_) _name_##$$Limit -#define IMAGE_SECTION_START(_name_) Image$$##_name_##$$Base -#define IMAGE_SECTION_END(_name_) Image$$##_name_##$$Limit -#define CSTACK_BLOCK_START(_name_) SECTION_START(_name_) -#define CSTACK_BLOCK_END(_name_) SECTION_END(_name_) -#define CODE_SECTION_START(_name_) IMAGE_SECTION_START(_name_) -#define CODE_SECTION_END(_name_) IMAGE_SECTION_END(_name_) - -extern const int CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME); -extern const int CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME); -extern const int CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME); -extern const int CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME); - -__STATIC_INLINE__ cpu_addr_t fault_code_start(void) -{ - return (cpu_addr_t)&CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME); -} - -__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) -{ - return (cpu_addr_t)&CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME); -} - -__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) -{ - return (cpu_addr_t)&CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME); -} - -__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) -{ - return (cpu_addr_t)&CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME); -} - -#elif defined(__ICCARM__) - -#define DEFAULT_CODE_SECTION_NAME ".text" -#define DEFAULT_CSTACK_SECTION_NAME "CSTACK" - -#pragma section=DEFAULT_CSTACK_SECTION_NAME -#pragma section=DEFAULT_CODE_SECTION_NAME - -__STATIC_INLINE__ cpu_addr_t fault_code_start(void) -{ - return (cpu_addr_t)__section_begin(DEFAULT_CODE_SECTION_NAME); -} - -__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) -{ - return (cpu_addr_t)__section_end(DEFAULT_CODE_SECTION_NAME); -} - -__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) -{ - return (cpu_addr_t)__section_begin(DEFAULT_CSTACK_SECTION_NAME); -} - -__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) -{ - return (cpu_addr_t)__section_end(DEFAULT_CSTACK_SECTION_NAME); -} - -#elif defined(__GNUC__) - -/** - * if we are using keil(armcc) or mdk(iccarm), we probably use the defult link script supplied by the IDE. - * the way to locate the text/stack section start and limit is to find them in default link script. - * but if we build our project by makefile(or something like scons, cmake, etc), we probably need to write - * our own link scrpit, if so, we should do like this(just a demo): - * - _stext = .; - .text : { - *(.text.startup) - *(.text) - *(.text.*) - } - _etext = .; - - __bss_start = .; - .bss : { - *(.bss) - *(.bss.*) - *(COMMON) - _sstack = .; - *(.cstack) - _estack = .; - } - __bss_end = .; - * by this, we can locate text/stack section start and limit by _stext/_etext and _sstack/_estack - */ -#define DEFAULT_CODE_SECTION_START _stext -#define DEFAULT_CODE_SECTION_END _etext -#define DEFAULT_CSTACK_SECTION_START _sstack -#define DEFAULT_CSTACK_SECTION_END _estack - -extern const int DEFAULT_CODE_SECTION_START; -extern const int DEFAULT_CODE_SECTION_END; - -extern const int DEFAULT_CSTACK_SECTION_START; -extern const int DEFAULT_CSTACK_SECTION_END; - -__STATIC_INLINE__ cpu_addr_t fault_code_start(void) -{ - return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_START)); -} - -__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) -{ - return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_END)); -} - -__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) -{ - return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_START)); -} - -__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) -{ - return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_END)); -} - -#endif - -__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); - -__KERNEL__ int fault_default_log_writer(const char *format, ...); - -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); - -#endif - -#endif /* _TOS_FAULT_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/arch/port.h b/board/Nuvoton_M251/TencentOS/arch/port.h deleted file mode 100644 index 10a6c89b..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/port.h +++ /dev/null @@ -1,73 +0,0 @@ -/*---------------------------------------------------------------------------- - * Tencent is pleased to support the open source community by making TencentOS - * available. - * - * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. - * If you have downloaded a copy of the TencentOS binary from Tencent, please - * note that the TencentOS binary is licensed under the BSD 3-Clause License. - * - * If you have downloaded a copy of the TencentOS source code from Tencent, - * please note that TencentOS source code is licensed under the BSD 3-Clause - * License, except for the third-party components listed below which are - * subject to different license terms. Your integration of TencentOS into your - * own projects may require compliance with the BSD 3-Clause License, as well - * as the other licenses applicable to the third-party components included - * within TencentOS. - *---------------------------------------------------------------------------*/ - -#ifndef _PORT_H_ -#define _PORT_H_ - -__PORT__ void port_int_disable(void); - -__PORT__ void port_int_enable(void); - -__PORT__ cpu_cpsr_t port_cpsr_save(void); - -__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); - -__PORT__ void port_cpu_reset(void); - -__PORT__ void port_sched_start(void) __NO_RETURN__; - -__PORT__ void port_context_switch(void); - -__PORT__ void port_irq_context_switch(void); - -__PORT__ void port_systick_config(uint32_t cycle_per_tick); - -__PORT__ void port_systick_priority_set(uint32_t prio); - -#if TOS_CFG_TICKLESS_EN > 0u - -__PORT__ void port_systick_resume(void); - -__PORT__ void port_systick_suspend(void); - -__PORT__ void port_systick_reload(uint32_t cycle_per_tick); - -__PORT__ void port_systick_pending_reset(void); - -__PORT__ k_time_t port_systick_max_delay_millisecond(void); - -#endif - -#if TOS_CFG_PWR_MGR_EN > 0u - -__PORT__ void port_sleep_mode_enter(void); - -__PORT__ void port_stop_mode_enter(void); - -__PORT__ void port_standby_mode_enter(void); - -#endif - - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u -__PORT__ void HardFault_Handler(void); - -__PORT__ void port_fault_diagnosis(void); -#endif - -#endif /* _PORT_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/arch/port_c.c b/board/Nuvoton_M251/TencentOS/arch/port_c.c deleted file mode 100644 index 3c4c903a..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/port_c.c +++ /dev/null @@ -1,129 +0,0 @@ -#include "tos.h" -//#include "core_cm0plus.h" -#include "core_armv8mbl.h" //change core - -__PORT__ void port_cpu_reset(void) -{ - NVIC_SystemReset(); -} - -__PORT__ void port_systick_config(uint32_t cycle_per_tick) -{ - (void)SysTick_Config(cycle_per_tick); -} - -__PORT__ void port_systick_priority_set(uint32_t prio) -{ - NVIC_SetPriority(SysTick_IRQn, prio); -} - -#if TOS_CFG_TICKLESS_EN > 0u - -__PORT__ k_time_t port_systick_max_delay_millisecond(void) -{ - k_time_t max_millisecond; - uint32_t max_cycle; - - max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit - max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second - return max_millisecond; -} - -__PORT__ void port_systick_resume(void) -{ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; -} - -__PORT__ void port_systick_suspend(void) -{ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -__PORT__ void port_systick_reload(uint32_t cycle_per_tick) -{ - uint32_t max_cycle; - - max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit - - if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) { - SysTick->LOAD = max_cycle; - } else { - SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL; - } - - SysTick->VAL = 0; -} - -__PORT__ void port_systick_pending_reset(void) -{ - SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk; -} - -#endif - -#if TOS_CFG_PWR_MGR_EN > 0u - -__PORT__ void port_sleep_mode_enter(void) -{ -#if 1 - HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); -#else - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); -#endif -} - -__PORT__ void port_stop_mode_enter(void) -{ - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); -} - -__PORT__ void port_standby_mode_enter(void) -{ - HAL_PWR_EnterSTANDBYMode(); -} - -#endif - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u -__PORT__ void port_fault_diagnosis(void) -{ - k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n"); -} - -/*------------------ RealView Compiler -----------------*/ -/* V5 */ -#if defined(__CC_ARM) - -__PORT__ __ASM__ void HardFault_Handler(void) -{ - IMPORT fault_backtrace - - MOV r0, lr - TST lr, #0x04 - ITE EQ - MRSEQ r1, MSP - MRSNE r1, PSP - BL fault_backtrace -} - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - -__PORT__ void __NAKED__ HardFault_Handler(void) -{ - __ASM__ __VOLATILE__ ( - "MOV r0, lr\n\t" - "TST lr, #0x04\n\t" - "ITE EQ\n\t" - "MRSEQ r1, MSP\n\t" - "MRSNE r1, PSP\n\t" - "BL fault_backtrace\n\t" - ); -} - -#endif /* ARMCC VERSION */ - -#endif /* TOS_CFG_FAULT_BACKTRACE_EN */ - diff --git a/board/Nuvoton_M251/TencentOS/arch/port_config.h b/board/Nuvoton_M251/TencentOS/arch/port_config.h deleted file mode 100644 index b0300236..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/port_config.h +++ /dev/null @@ -1,29 +0,0 @@ -/*---------------------------------------------------------------------------- - * Tencent is pleased to support the open source community by making TencentOS - * available. - * - * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. - * If you have downloaded a copy of the TencentOS binary from Tencent, please - * note that the TencentOS binary is licensed under the BSD 3-Clause License. - * - * If you have downloaded a copy of the TencentOS source code from Tencent, - * please note that TencentOS source code is licensed under the BSD 3-Clause - * License, except for the third-party components listed below which are - * subject to different license terms. Your integration of TencentOS into your - * own projects may require compliance with the BSD 3-Clause License, as well - * as the other licenses applicable to the third-party components included - * within TencentOS. - *---------------------------------------------------------------------------*/ - -#ifndef _PORT_CONFIG_H_ -#define _PORT_CONFIG_H_ - -#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32 -#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32 -#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING -// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32 -#define TOS_CFG_CPU_HRTIMER_EN 0u -#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u - -#endif /* _PORT_CONFIG_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/arch/port_s.S b/board/Nuvoton_M251/TencentOS/arch/port_s.S deleted file mode 100644 index 114a99cf..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/port_s.S +++ /dev/null @@ -1,137 +0,0 @@ - EXPORT port_int_disable - EXPORT port_int_enable - - EXPORT port_cpsr_save - EXPORT port_cpsr_restore - - EXPORT port_sched_start - EXPORT port_context_switch - EXPORT port_irq_context_switch - - EXPORT PendSV_Handler - - IMPORT k_curr_task - IMPORT k_next_task - - -NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register. -NVIC_SYSPRI14 EQU 0xE000ED20 ; System priority register (priority 14). -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest). -NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. - - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - GLOBAL port_int_disable -port_int_disable - CPSID I - BX LR - - - GLOBAL port_int_enable -port_int_enable - CPSIE I - BX LR - - - GLOBAL port_cpsr_save -port_cpsr_save - MRS R0, PRIMASK - CPSID I - BX LR - - - GLOBAL port_cpsr_restore -port_cpsr_restore - MSR PRIMASK, R0 - BX LR - - - GLOBAL port_sched_start -port_sched_start - LDR R0, =NVIC_SYSPRI14 - LDR R1, =NVIC_PENDSV_PRI - STR R1, [R0] - - MOVS R0, #0 - MSR PSP, R0 - - LDR R0, =NVIC_INT_CTRL - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - - CPSIE I - -__unreachable - B __unreachable - - - GLOBAL port_context_switch -port_context_switch - LDR R0, =NVIC_INT_CTRL - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - BX LR - - - GLOBAL port_irq_context_switch -port_irq_context_switch - LDR R0, =NVIC_INT_CTRL - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - BX LR - - - GLOBAL PendSV_Handler -PendSV_Handler - CPSID I - MRS R0, PSP - CMP R0, #0 - BEQ PendSVHandler_nosave - - SUBS R0, R0, #0x20 - STMIA R0!, {R4 - R7} - MOV R4, R8 - MOV R5, R9 - MOV R6, R10 - MOV R7, R11 - STMIA R0!, {R4-R7} - SUBS R0, R0, #0x20 - - LDR R1, =k_curr_task - LDR R1, [R1] - STR R0, [R1] - -PendSVHandler_nosave - LDR R0, =k_curr_task - LDR R1, =k_next_task - LDR R2, [R1] - STR R2, [R0] - - LDR R0, [R2] - - LDMIA R0!, {R4 - R7} - LDMIA R0!, {R2 - R3} - MOV R8, R2 - MOV R9, R3 - LDMIA R0!, {R2 - R3} - MOV R10, R2 - MOV R11, R3 - MSR PSP, R0 - - MOV R0, R14 - MOVS R1, #0x04 - ORRS R0, R1 - MOV R14, R0 - - CPSIE I - - BX LR - - ALIGN - - END - diff --git a/board/Nuvoton_M251/TencentOS/arch/tos_cpu.c b/board/Nuvoton_M251/TencentOS/arch/tos_cpu.c deleted file mode 100644 index 49d355f5..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/tos_cpu.c +++ /dev/null @@ -1,276 +0,0 @@ -#include - -__API__ uint32_t tos_cpu_clz(uint32_t val) -{ -#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 0u) - uint32_t nbr_lead_zeros = 0; - - if (!(val & 0XFFFF0000)) { - val <<= 16; - nbr_lead_zeros += 16; - } - - if (!(val & 0XFF000000)) { - val <<= 8; - nbr_lead_zeros += 8; - } - - if (!(val & 0XF0000000)) { - val <<= 4; - nbr_lead_zeros += 4; - } - - if (!(val & 0XC0000000)) { - val <<= 2; - nbr_lead_zeros += 2; - } - - if (!(val & 0X80000000)) { - nbr_lead_zeros += 1; - } - - if (!val) { - nbr_lead_zeros += 1; - } - - return (nbr_lead_zeros); -#else - return port_clz(val); -#endif -} - -__API__ void tos_cpu_int_disable(void) -{ - port_int_disable(); -} - -__API__ void tos_cpu_int_enable(void) -{ - port_int_enable(); -} - -__API__ cpu_cpsr_t tos_cpu_cpsr_save(void) -{ - return port_cpsr_save(); -} - -__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) -{ - port_cpsr_restore(cpsr); -} - -__KERNEL__ void cpu_init(void) -{ - k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; - cpu_systick_init(k_cpu_cycle_per_tick); - -#if (TOS_CFG_CPU_HRTIMER_EN > 0) - tos_cpu_hrtimer_init(); -#endif -} - -__KERNEL__ void cpu_reset(void) -{ - port_cpu_reset(); -} - -__KERNEL__ void cpu_sched_start(void) -{ - port_sched_start(); -} - -__KERNEL__ void cpu_context_switch(void) -{ - port_context_switch(); -} - -__KERNEL__ void cpu_irq_context_switch(void) -{ - port_irq_context_switch(); -} - -__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) -{ - port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); - port_systick_config(cycle_per_tick); -} - -#if TOS_CFG_TICKLESS_EN > 0u - -/** - * @brief Set value to systick reload value register - * - * @param cycles The value set to register - * - * @return None - */ -__STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) -{ - port_systick_reload(cycle_per_tick); -} - -/** - * @brief Enable systick interrupt - * - * @return None - */ -__KERNEL__ void cpu_systick_resume(void) -{ - port_systick_resume(); -} - -/** - * @brief Disable systick interrupt - * - * @return None - */ -__KERNEL__ void cpu_systick_suspend(void) -{ - port_systick_suspend(); -} - -__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) -{ - return port_systick_max_delay_millisecond(); -} - -__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) -{ - k_cycle_t cycles; - - cycles = (k_cycle_t)((uint64_t)millisecond * TOS_CFG_CPU_CLOCK / K_TIME_MILLISEC_PER_SEC); /* CLOCK means cycle per second */ - - cpu_systick_reload(cycles - 12); /* interrupt delay */ -} - -__KERNEL__ void cpu_systick_pending_reset(void) -{ - port_systick_pending_reset(); -} - -__KERNEL__ void cpu_systick_reset(void) -{ - cpu_systick_reload(k_cpu_cycle_per_tick); -} - -#endif /* TOS_CFG_TICKLESS_EN */ - -#if TOS_CFG_PWR_MGR_EN > 0u - -__KERNEL__ void cpu_sleep_mode_enter(void) -{ - port_sleep_mode_enter(); -} - -__KERNEL__ void cpu_stop_mode_enter(void) -{ - port_stop_mode_enter(); -} - -__KERNEL__ void cpu_standby_mode_enter(void) -{ - port_standby_mode_enter(); -} - -#endif /* TOS_CFG_PWR_MGR_EN */ - -__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, - void *arg, - void *exit, - k_stack_t *stk_base, - size_t stk_size) -{ - cpu_data_t *sp; - - sp = (cpu_data_t *)&stk_base[stk_size]; - sp = (cpu_data_t *)((cpu_addr_t)sp & 0xFFFFFFF8); - -#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u - uint8_t *slot = (uint8_t *)&stk_base[0]; - for (; slot < (uint8_t *)sp; ++slot) { - *slot = 0xCC; - } -#endif - - /* auto-saved on exception(pendSV) by hardware */ - *--sp = (cpu_data_t)0x01000000u; /* xPSR */ - *--sp = (cpu_data_t)entry; /* entry */ - *--sp = (cpu_data_t)exit; /* R14 (LR) */ - *--sp = (cpu_data_t)0x12121212u; /* R12 */ - *--sp = (cpu_data_t)0x03030303u; /* R3 */ - *--sp = (cpu_data_t)0x02020202u; /* R2 */ - *--sp = (cpu_data_t)0x01010101u; /* R1 */ - *--sp = (cpu_data_t)arg; /* R0: arg */ - - /* Remaining registers saved on process stack */ - /* EXC_RETURN = 0xFFFFFFFDL - Initial state: Thread mode + non-floating-point state + PSP - 31 - 28 : EXC_RETURN flag, 0xF - 27 - 5 : reserved, 0xFFFFFE - 4 : 1, basic stack frame; 0, extended stack frame - 3 : 1, return to Thread mode; 0, return to Handler mode - 2 : 1, return to PSP; 0, return to MSP - 1 : reserved, 0 - 0 : reserved, 1 - */ -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - *--sp = (cpu_data_t)0xFFFFFFFDL; -#endif - - *--sp = (cpu_data_t)0x11111111u; /* R11 */ - *--sp = (cpu_data_t)0x10101010u; /* R10 */ - *--sp = (cpu_data_t)0x09090909u; /* R9 */ - *--sp = (cpu_data_t)0x08080808u; /* R8 */ - *--sp = (cpu_data_t)0x07070707u; /* R7 */ - *--sp = (cpu_data_t)0x06060606u; /* R6 */ - *--sp = (cpu_data_t)0x05050505u; /* R5 */ - *--sp = (cpu_data_t)0x04040404u; /* R4 */ - - return (k_stack_t *)sp; -} - -#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u - -__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) -{ - uint8_t *slot; - uint8_t *sp, *bp; - int the_depth = 0; - - bp = (uint8_t *)&stk_base[0]; - - sp = &stk_base[stk_size]; - sp = (uint8_t *)((cpu_addr_t)sp & 0xFFFFFFF8); - - for (slot = sp - 1; slot >= bp; --slot) { - if (*slot != 0xCC) { - the_depth = sp - slot; - } - } - - *depth = the_depth; - if (the_depth == stk_size) { - return K_ERR_TASK_STK_OVERFLOW; - } - - return K_ERR_NONE; -} - -#endif - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__KERNEL__ void cpu_flush_fpu(void) -{ - (void)__get_FPSCR(); -} -#endif - -__KERNEL__ void cpu_fault_diagnosis(void) -{ - port_fault_diagnosis(); -} - -#endif /* TOS_CFG_FAULT_BACKTRACE_EN */ - diff --git a/board/Nuvoton_M251/TencentOS/arch/tos_fault.c b/board/Nuvoton_M251/TencentOS/arch/tos_fault.c deleted file mode 100644 index e55e6e56..00000000 --- a/board/Nuvoton_M251/TencentOS/arch/tos_fault.c +++ /dev/null @@ -1,251 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u - -__STATIC_INLINE__ void fault_spin(void) -{ - tos_knl_sched_lock(); - tos_cpu_int_disable(); - while (K_TRUE) { - ; - } -} - -/* EXC_RETURN: - 31 - 28 : EXC_RETURN flag - 27 - 5 : reserved - 4 : 1, basic stack frame; 0, extended stack frame - 3 : 1, return to Thread mode; 0, return to Handler mode - 2 : 1, return to PSP; 0, return to MSP - 1 : reserved, 0 - 0 : reserved, 1 - */ -__STATIC_INLINE__ int fault_is_on_task(cpu_data_t lr) -{ - return (lr & (1u << 2)) != 0; -} - -__STATIC_INLINE__ int fault_is_thumb(cpu_data_t psr) -{ - return (psr & (1u << 24)) != 0; -} - -__STATIC_INLINE__ int fault_is_code(fault_info_t *info, cpu_data_t value) -{ - return value >= info->code_start && value <= info->code_limit; -} - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) -__STATIC_INLINE__ int fault_is_extended_stack_frame(cpu_data_t lr) -{ - return (lr & (1u << 4)) == 0; -} - -__STATIC__ void fault_dump_fpu_frame(fault_fpu_frame_t *fpu_frame) -{ - /* - * As known, v7-m has a feature named "LAZY PUSH", for the reason we do not do any float - * operation in fault_backtrace, cpu will not do the real fpu register push to the stack. - * that means the value we dump in fault_dump_fpu_frame will not be the correct value of - * each FPU register. - * We define a function here which access to FPSCR, if this function involved, cpu will do - * the real FPU register push so we will get the correct dump. - * I know it's ugly, but it works. If you know a better way, please tell me. - */ - cpu_flush_fpu(); - - k_fault_log_writer("\n\n====================== FPU Registers =======================\n"); - k_fault_log_writer(" %s: %08x\n", "FPSCR", fpu_frame->fpscr); - k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", - "S0 ", fpu_frame->s0, - "S1 ", fpu_frame->s1, - "S2 ", fpu_frame->s2, - "S3 ", fpu_frame->s3); - k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", - "S4 ", fpu_frame->s4, - "S5 ", fpu_frame->s5, - "S6 ", fpu_frame->s6, - "S7 ", fpu_frame->s7); - k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", - "S8 ", fpu_frame->s8, - "S9 ", fpu_frame->s9, - "S10", fpu_frame->s10, - "S11", fpu_frame->s11); - k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", - "S12", fpu_frame->s12, - "S13", fpu_frame->s13, - "S14", fpu_frame->s14, - "S15", fpu_frame->s15); -} - -#endif - -__STATIC__ void fault_dump_cpu_frame(fault_cpu_frame_t *cpu_frame) -{ - k_fault_log_writer("\n\n====================== CPU Registers =======================\n"); - k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", - "R0 ", cpu_frame->r0, - "R1 ", cpu_frame->r1, - "R2 ", cpu_frame->r2, - "R3 ", cpu_frame->r3); - k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", - "R12", cpu_frame->r12, - "LR ", cpu_frame->lr, - "PC ", cpu_frame->pc, - "PSR", cpu_frame->spsr); -} - -__STATIC__ void fault_dump_stack(fault_info_t *info, size_t depth) -{ - cpu_addr_t sp = info->sp_before_fault;; - - k_fault_log_writer("\nTASK STACK DUMP:\n"); - while (sp <= info->stack_limit && depth--) { - k_fault_log_writer(" addr: %08x data: %08x\n", sp, (cpu_data_t)*(cpu_data_t *)sp); - sp += sizeof(cpu_addr_t); - } -} - -__STATIC__ void fault_call_stack_backtrace(fault_info_t *info, size_t depth) -{ - cpu_data_t value; - cpu_addr_t sp = info->sp_before_fault; - - if (info->is_stk_ovrf) { - return; - } - - k_fault_log_writer("\n\n====================== Dump Call Stack =====================\n"); - - k_fault_log_writer(" %x\n", info->pc); - - /* walk through the stack, check every content on stack whether is a instruction(code) */ - for (; sp < info->stack_limit && depth; sp += sizeof(cpu_addr_t)) { - value = *((cpu_addr_t *)sp) - sizeof(cpu_addr_t); - - /* if thumb, a instruction's first bit must be 1 */ - if (info->is_thumb && !(value & 1)) { - continue; - } - - if (fault_is_code(info, value)) { - k_fault_log_writer(" %x\n", value); - --depth; - } - } -} - -__STATIC__ void fault_dump_task(fault_info_t *info) -{ - k_task_t *task; - - if (!info->is_on_task) { - return; - } - - task = k_curr_task; - k_fault_log_writer("\n\n====================== Fault on task =======================\n"); - k_fault_log_writer(" TASK NAME: %s\n", task->name); - k_fault_log_writer(" STK BASE: %x\n", info->stack_start); - k_fault_log_writer(" STK SIZE: %x\n", task->stk_size * sizeof(k_stack_t)); - k_fault_log_writer(" STK LIMIT: %x\n", info->stack_limit); - - if (!info->is_stk_ovrf) { - fault_dump_stack(info, K_FAULT_STACK_DUMP_DEPTH); - } -} - -__STATIC__ void fault_dump_information(fault_info_t *info) -{ - k_fault_log_writer("\n\n================== Dump Fault Information ==================\n"); - k_fault_log_writer(" THUMB: %s\n", info->is_thumb ? "TRUE" : "FALSE"); - k_fault_log_writer(" ON TASK: %s\n", info->is_on_task? "TRUE" : "FALSE"); - k_fault_log_writer(" STK OVRF: %s\n", info->is_stk_ovrf? "TRUE" : "FALSE"); - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - k_fault_log_writer(" EXT STK: %s\n", info->is_ext_stk_frm? "TRUE" : "FALSE"); -#endif - - k_fault_log_writer(" PC: %08x\n", info->pc); - k_fault_log_writer(" SP: %08x\n", info->sp_before_fault); - k_fault_log_writer(" STK START: %08x\n", info->stack_start); - k_fault_log_writer(" STK LIMIT: %08x\n", info->stack_limit); - k_fault_log_writer(" COD START: %08x\n", info->code_start); - k_fault_log_writer(" COD LIMIT: %08x\n", info->code_limit); -} - -__STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame, fault_info_t *info) -{ - info->is_thumb = fault_is_thumb(frame->cpu_frame.spsr); - info->is_on_task = fault_is_on_task(lr); - - info->pc = frame->cpu_frame.pc; - - info->sp_before_fault = (cpu_addr_t)frame + sizeof(fault_cpu_frame_t); - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - info->is_ext_stk_frm = fault_is_extended_stack_frame(lr); - - if (info->is_ext_stk_frm) { - info->sp_before_fault += sizeof(fault_fpu_frame_t); - } -#endif - - info->code_start = fault_code_start(); - info->code_limit = fault_code_limit(); - - if (info->is_on_task) { - info->stack_start = (cpu_addr_t)k_curr_task->stk_base; - info->stack_limit = info->stack_start + k_curr_task->stk_size * sizeof(k_task_t); - } else { - info->stack_start = fault_msp_start(); - info->stack_limit = fault_msp_limit(); - } - - info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); -} - -__KERNEL__ int fault_default_log_writer(const char *format, ...) -{ - int len; - va_list ap; - - va_start(ap, format); - len = vprintf(format, ap); - va_end(ap); - - return len; -} - -__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) -{ - k_fault_log_writer = log_writer; -} - -__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) -{ - fault_info_t info; - - fault_gather_information(lr, frame, &info); - - fault_dump_information(&info); - - fault_dump_task(&info); - - fault_dump_cpu_frame(&frame->cpu_frame); - -#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) - if (info.is_ext_stk_frm) { - fault_dump_fpu_frame(&frame->fpu_frame); - } -#endif - - fault_call_stack_backtrace(&info, K_FAULT_CALL_STACK_BACKTRACE_DEPTH); - - cpu_fault_diagnosis(); - - fault_spin(); -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos.h deleted file mode 100644 index 10f58204..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef _TOS_H_ -#define _TOS_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif /* _TOS_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_compiler.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_compiler.h deleted file mode 100644 index 88a36c45..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_compiler.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef _TOS_COMPILER_H_ -#define _TOS_COMPILER_H_ - -// function with __API__ prefix, api for user -#define __API__ - -// function with __KERNEL__ prefix, only for kernel -#define __KERNEL__ - -// function with __HOOK__ prefix, should be implemented by user -#define __HOOK__ - -// function with __DEBUG__ prefix, only for debug -#define __DEBUG__ - -// function with __PORT__ is architecture depended -#define __PORT__ - -/*------------------ RealView Compiler -----------------*/ -#if defined(__CC_ARM) - -#define __ASM__ __asm -#define __VOLATILE__ volatile - -#define __INLINE__ inline -#define __STATIC__ static - -#if (__ARMCC_VERSION < 5060750) // how to know the exact number? -#define __STATIC_INLINE__ static -#else -#define __STATIC_INLINE__ static inline -#endif - -#define likely(x) __builtin_expect(!!(x), 1) -#define unlikely(x) __builtin_expect(!!(x), 0) -#define __UNUSED__ __attribute__((__unused__)) -#define __USED__ __attribute__((__used__)) -#define __PACKED__ __attribute__((packed)) -#define __ALIGNED__(x) __attribute__((aligned(x))) -#define __PURE__ __attribute__((__pure__)) -#define __CONST__ __attribute__((__const__)) -#define __NO_RETURN__ __attribute__((__noreturn__)) - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - -#define __ASM__ __asm -#define __VOLATILE__ volatile - -#define __INLINE__ inline -#define __STATIC__ static -#define __STATIC_INLINE__ static inline - -#define likely(x) __builtin_expect(!!(x), 1) -#define unlikely(x) __builtin_expect(!!(x), 0) -#define __UNUSED__ __attribute__((__unused__)) -#define __USED__ __attribute__((__used__)) -#define __PACKED__ __attribute__((packed)) -#define __ALIGNED__(x) __attribute__((aligned(x))) -#define __PURE__ __attribute__((__pure__)) -#define __CONST__ __attribute__((__const__)) -#define __NO_RETURN__ __attribute__((__noreturn__)) -#define __NAKED__ __attribute__((naked)) - -/*------------------ ICC Compiler ----------------------*/ -#elif defined(__ICCARM__) - -#define __ASM__ __asm -#define __VOLATILE__ volatile - -#define __INLINE__ inline -#define __STATIC__ static -#define __STATIC_INLINE__ static inline - -#define likely(x) (x) -#define unlikely(x) (x) -#define __UNUSED__ -#define __USED__ -#define __PACKED__ -#define __ALIGNED__(x) -#define __PURE__ -#define __CONST__ -#define __NO_RETURN__ -#define __NAKED__ - -/*------------------ GNU Compiler ----------------------*/ -#elif defined(__GNUC__) - -#define __ASM__ __asm -#define __VOLATILE__ volatile - -#define __INLINE__ inline -#define __STATIC__ static -#define __STATIC_INLINE__ static inline - -#define likely(x) __builtin_expect(!!(x), 1) -#define unlikely(x) __builtin_expect(!!(x), 0) -#define __UNUSED__ __attribute__((__unused__)) -#define __USED__ __attribute__((__used__)) -#define __PACKED__ __attribute__((packed)) -#define __ALIGNED__(x) __attribute__((aligned(x))) -#define __PURE__ __attribute__((__pure__)) -#define __CONST__ __attribute__((__const__)) -#define __NO_RETURN__ __attribute__((__noreturn__)) -#define __NAKED__ __attribute__((naked)) - -#endif - -#endif /* _TOS_COMPILER_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_check.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_check.h deleted file mode 100644 index 0d369a68..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_check.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef _TOS_CONFIG_CHECK_H_ -#define _TOS_CONFIG_CHECK_H_ - -#if TOS_CFG_TASK_PRIO_MAX < 8u -#error "INVALID config, TOS_CFG_TASK_PRIO_MAX must be >= 8" -#endif - -#if (TOS_CFG_QUEUE_EN > 0u) && (TOS_CFG_MSG_EN == 0u) -#error "INVALID config, must enable tos_msg to use tos_queue" -#endif - -#if ((TOS_CFG_TIMER_EN > 0u) && !defined(TOS_CFG_TIMER_AS_PROC)) -#error "UNDECLARED config, TOS_CFG_TIMER_AS_PROC" -#endif - -#if (TOS_CFG_VFS_EN > 0u) && (TOS_CFG_MMHEAP_EN == 0u) -#error "INVALID config, must enable tos_mmheap to use tos_vfs" -#endif - -#ifndef TOS_CFG_CPU_HRTIMER_EN -#error "UNDECLARED config, TOS_CFG_CPU_HRTIMER_EN should be declared in 'port.h'" -#elif (TOS_CFG_CPU_HRTIMER_EN > 0u) && !defined(TOS_CFG_CPU_HRTIMER_SIZE) -#error "UNDECLARED config, TOS_CFG_CPU_HRTIMER_SIZE should be declared in 'port.h'" -#elif ((TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_08) && \ - (TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_16) && \ - (TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_32) && \ - (TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_64)) -#error "INVALID config, TOS_CFG_CPU_HRTIMER_SIZE" -#endif - -#ifndef TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT -#error "UNDECLARED config, TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT, should be declared in 'port.h'" -#endif - -#ifndef TOS_CFG_CPU_STK_GROWTH -#error "UNDECLARED config, TOS_CFG_CPU_STK_GROWTH, should be declared in 'port.h'" -#elif ((TOS_CFG_CPU_STK_GROWTH != CPU_STK_GROWTH_ASCENDING) && \ - (TOS_CFG_CPU_STK_GROWTH != CPU_STK_GROWTH_DESCENDING)) -#error "INVALID config, TOS_CFG_CPU_STK_GROWTH" -#endif - -#ifndef TOS_CFG_CPU_ADDR_SIZE -#error "UNDECLARED config, TOS_CFG_CPU_ADDR_SIZE, should be declared in 'port.h'" -#elif ((TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_08) && \ - (TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_16) && \ - (TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_32) && \ - (TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_64)) -#error "INVALID config, TOS_CFG_CPU_ADDR_SIZE" -#endif - -#ifndef TOS_CFG_CPU_DATA_SIZE -#error "UNDECLARED config, TOS_CFG_CPU_DATA_SIZE, should be declared in 'port.h'" -#elif ((TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_08) && \ - (TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_16) && \ - (TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_32) && \ - (TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_64)) -#error "INVALID config, TOS_CFG_CPU_DATA_SIZE" -#endif - -#endif /* _TOS_CHECK_CONFIG_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_default.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_default.h deleted file mode 100644 index 3087ee4f..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_config_default.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef _TOS_CONFIG_DEFAULT_H_ -#define _TOS_CONFIG_DEFAULT_H_ - -#ifndef TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN -#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 0u -#endif - -#ifndef TOS_CFG_ROUND_ROBIN_EN -#define TOS_CFG_ROUND_ROBIN_EN 0u -#endif - -#ifndef TOS_CFG_EVENT_EN -#define TOS_CFG_EVENT_EN 0u -#endif - -#ifndef TOS_CFG_MMHEAP_EN -#define TOS_CFG_MMHEAP_EN 0u -#endif - -#ifndef TOS_CFG_MUTEX_EN -#define TOS_CFG_MUTEX_EN 0u -#endif - -#ifndef TOS_CFG_QUEUE_EN -#define TOS_CFG_QUEUE_EN 0u -#endif - -#ifndef TOS_CFG_SEM_EN -#define TOS_CFG_SEM_EN 0u -#endif - -#if (TOS_CFG_QUEUE_EN > 0u) && !defined(TOS_CFG_MSG_EN) -#define TOS_CFG_MSG_EN 1u -#elif (TOS_CFG_QUEUE_EN == 0u) && !defined(TOS_CFG_MSG_EN) -#define TOS_CFG_MSG_EN 0u -#endif - -#ifndef TOS_CFG_TIMER_EN -#define TOS_CFG_TIMER_EN 0u -#endif - -#if (TOS_CFG_TIMER_EN > 0u) && !defined(TOS_CFG_TIMER_AS_PROC) -#define TOS_CFG_TIMER_AS_PROC 0u -#endif - -#ifndef TOS_CFG_MSG_POOL_SIZE -#define TOS_CFG_MSG_POOL_SIZE 100u -#endif - -#ifndef TOS_CFG_IDLE_TASK_STK_SIZE -#define TOS_CFG_IDLE_TASK_STK_SIZE 128u -#endif - -#ifndef TOS_CFG_OBJECT_VERIFY_EN -#define TOS_CFG_OBJECT_VERIFY_EN 0u -#endif - -#if (TOS_CFG_TIMER_AS_PROC == 0u) && !defined(TOS_CFG_TIMER_TASK_PRIO) -#define TOS_CFG_TIMER_TASK_PRIO (k_prio_t)(K_TASK_PRIO_IDLE - (k_prio_t)1u) -#endif - -#if (TOS_CFG_TIMER_AS_PROC == 0u) && !defined(TOS_CFG_TIMER_TASK_STK_SIZE) -#define TOS_CFG_TIMER_TASK_STK_SIZE 128u -#endif - -#ifndef TOS_CFG_CPU_SYSTICK_PRIO -#define TOS_CFG_CPU_SYSTICK_PRIO 0u -#endif - -#ifndef TOS_CFG_CPU_TICK_PER_SECOND -#define TOS_CFG_CPU_TICK_PER_SECOND 1000u -#endif - -#ifndef TOS_CFG_CPU_CLOCK -#define TOS_CFG_CPU_CLOCK 16000000u -#endif - -#ifndef TOS_CFG_TASK_PRIO_MAX -#define TOS_CFG_TASK_PRIO_MAX 10u -#endif - -#ifndef TOS_CFG_MMBLK_EN -#define TOS_CFG_MMBLK_EN 0u -#endif - -#ifndef TOS_CFG_MMHEAP_EN -#define TOS_CFG_MMHEAP_EN 0u -#endif - -#if (TOS_CFG_MMHEAP_EN > 0u) && !defined(TOS_CFG_MMHEAP_POOL_SIZE) -#define TOS_CFG_MMHEAP_POOL_SIZE 0x1000 -#endif - -#ifndef TOS_CFG_PWR_MGR_EN -#define TOS_CFG_PWR_MGR_EN 0u -#endif - -#ifndef TOS_CFG_TICKLESS_EN -#define TOS_CFG_TICKLESS_EN 0u -#endif - -#if (TOS_CFG_PWR_MGR_EN > 0u) || (TOS_CFG_TICKLESS_EN > 0u) -#if TOS_CFG_IDLE_TASK_STK_SIZE < 256 -#undef TOS_CFG_IDLE_TASK_STK_SIZE -#define TOS_CFG_IDLE_TASK_STK_SIZE 256u -#endif -#endif - -#ifndef TOS_CFG_FAULT_BACKTRACE_EN -#define TOS_CFG_FAULT_BACKTRACE_EN 0u -#endif - -#endif /* _TOS_CONFIG_DEFAULT_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_err.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_err.h deleted file mode 100644 index c1806952..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_err.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef _TOS_ERR_H_ -#define _TOS_ERR_H_ - -typedef enum k_err_en { - K_ERR_NONE = 0u, - - K_ERR_DELAY_ZERO = 100u, - K_ERR_DELAY_FOREVER, - - K_ERR_EVENT_PEND_OPT_INVALID = 200u, - - K_ERR_FIFO_FULL = 300u, - K_ERR_FIFO_EMPTY, - - K_ERR_IN_IRQ = 400u, - - K_ERR_KNL_NOT_RUNNING = 500u, - K_ERR_KNL_RUNNING, - - K_ERR_LOCK_NESTING_OVERFLOW = 600u, - - K_ERR_MMBLK_POOL_FULL = 700u, - K_ERR_MMBLK_POOL_EMPTY, - K_ERR_MMBLK_INVALID_BLK_SIZE, - K_ERR_MMBLK_INVALID_POOL_ADDR, - - K_ERR_MMHEAP_INVALID_POOL_ADDR = 800u, - K_ERR_MMHEAP_INVALID_POOL_SIZE, - - K_ERR_MSG_QUEUE_FULL = 900u, - K_ERR_MSG_QUEUE_EMPTY, - - K_ERR_MUTEX_NOT_OWNER = 1000u, - K_ERR_MUTEX_NESTING, - K_ERR_MUTEX_NESTING_OVERFLOW, - - K_ERR_OBJ_PTR_NULL = 1100u, - K_ERR_OBJ_INVALID, - - K_ERR_PM_DEVICE_ALREADY_REG = 1200u, - K_ERR_PM_DEVICE_OVERFLOW = 1300u, - K_ERR_PM_WKUP_SOURCE_NOT_INSTALL = 1400u, - - K_ERR_QUEUE_EMPTY = 1500u, - K_ERR_QUEUE_FULL, - - K_ERR_PEND_NOWAIT = 1600u, - K_ERR_PEND_SCHED_LOCKED, - K_ERR_PEND_ABNORMAL, - K_ERR_PEND_TIMEOUT, - K_ERR_PEND_DESTROY, - K_ERR_PEND_OWNER_DIE, - - K_ERR_SCHED_LOCKED = 1700u, - K_ERR_SCHED_NOT_LOCKED, - - K_ERR_SEM_OVERFLOW = 1800u, - - K_ERR_TASK_DESTROY_IDLE = 1900u, - K_ERR_TASK_NOT_DELAY, - K_ERR_TASK_PRIO_INVALID, - K_ERR_TASK_RESUME_SELF, - K_ERR_TASK_SUSPENDED, - K_ERR_TASK_SUSPEND_IDLE, - K_ERR_TASK_STK_OVERFLOW, - K_ERR_TASK_STK_SIZE_INVALID, - - K_ERR_TICKLESS_WKUP_ALARM_NOT_INSTALLED = 2000u, - K_ERR_TICKLESS_WKUP_ALARM_NO_INIT, - K_ERR_TICKLESS_WKUP_ALARM_INIT_FAILED, - - K_ERR_TIMER_INACTIVE = 2100u, - K_ERR_TIMER_DELAY_FOREVER, - K_ERR_TIMER_PERIOD_FOREVER, - K_ERR_TIMER_INVALID_DELAY, - K_ERR_TIMER_INVALID_PERIOD, - K_ERR_TIMER_INVALID_STATE, - K_ERR_TIMER_INVALID_OPT, - K_ERR_TIMER_STOPPED, -} k_err_t; - -#endif /* _TOS_ERR_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_event.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_event.h deleted file mode 100644 index f7d02e2f..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_event.h +++ /dev/null @@ -1,116 +0,0 @@ -#ifndef _TOS_EVENT_H_ -#define _TOS_EVENT_H_ - -#if TOS_CFG_EVENT_EN > 0 - -// if we are pending an event, for any flag we expect is set is ok, this flag should be passed to tos_event_pend -#define TOS_OPT_EVENT_PEND_ANY (k_opt_t)0x0001 - -// if we are pending an event, must all the flag we expect is set is ok, this flag should be passed to tos_event_pend -#define TOS_OPT_EVENT_PEND_ALL (k_opt_t)0x0002 - -// if we are pending an event, and we wanna clear the event's flag after we read, this flag should be passed to tos_event_pend -/* ATTENTION: - we can pass both TOS_OPT_EVENT_PEND_CLR and TOS_OPT_EVENT_PEND_ANY, or TOS_OPT_EVENT_PEND_CLR and TOS_OPT_EVENT_PEND_ALL - to tos_event_pend, if we wanna do this, a (TOS_OPT_EVENT_PEND_CLR | TOS_OPT_EVENT_PEND_ANY) or - (TOS_OPT_EVENT_PEND_CLR | TOS_OPT_EVENT_PEND_ALL) should be passed. - but, (TOS_OPT_EVENT_PEND_ANY | TOS_OPT_EVENT_PEND_ALL) is invalid, we cannot both wanna any and all flag is set. - */ -#define TOS_OPT_EVENT_PEND_CLR (k_opt_t)0x0004 - -typedef enum opt_event_post_en { - OPT_EVENT_POST_KEP, - OPT_EVENT_POST_CLR, -} opt_event_post_t; - -typedef struct k_event_st { - pend_obj_t pend_obj; - k_event_flag_t flag; -} k_event_t; - -/** - * @brief Create an event. - * create an event. - * - * @attention None - * - * @param[in] event pointer to the handler of the event. - * @param[in] init_flag initial flag of the event. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_event_create(k_event_t *event, k_event_flag_t init_flag); - -/** - * @brief Destroy an event. - * destroy an event. - * - * @attention None - * - * @param[in] event pointer to the handler of the event. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_event_destroy(k_event_t *event); - -/** - * @brief Pend an event. - * pend an event. - * - * @attention if opt is TOS_OPT_EVENT_PEND_ANY, any of the flag_expect is set is ok; - * if opt is TOS_OPT_EVENT_PEND_ALL£¬ must all the flag_expect is set is ok. - * - * @param[in] event pointer to the handler of the event. - * @param[in] flag_expect the flag we expect from the event. - * @param[OUT] flag_match if we get the flag we expect, what exactly they are? - * @param[in] timeout how much time(in k_tick_t) we would like to wait. - * @param[in] opt option for pend. - * - * @return errcode - * @retval #K_ERR_EVENT_PEND_OPT_INVALID opt is invalid - * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. - * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. - * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. - * @retval #K_ERR_PEND_DESTROY the event we are pending is destroyed. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_event_pend(k_event_t *event, k_event_flag_t flag_expect, k_event_flag_t *flag_match, k_tick_t timeout, k_opt_t opt); - -/** - * @brief Post an event. - * post an event. - * - * @attention if you are posting an event in tos_event_post, event's own flag will be overwrited by the flag we post. - * eg. if an event's own flag is 0x0001, and we are posting a flag 0x0030, after the post, the event's flag - * will be overwrited to 0x0030. - * - * @param[in] event pointer to the handler of the event. - * @param[in] flag the flag we post. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_event_post(k_event_t *event, k_event_flag_t flag); - -/** - * @brief Post an event. - * post an event, and keep the original own flag of the event. - * - * @attention the original own flag of the event will be keeped. - * eg.if an event's own flag is 0x0001, and we are posting a flag 0x0030, after the post, the event's flag - * will be changed to 0x0031(0x0030 | 0x0001), which means the event's original flag is keeped. - * - * @param[in] event pointer to the handler of the event. - * @param[in] flag the flag we post. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_event_post_keep(k_event_t *event, k_event_flag_t flag); - -#endif - -#endif /* _TOS_EVENT_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_fifo.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_fifo.h deleted file mode 100644 index 8affcb85..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_fifo.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef _TOS_FIFO_H_ -#define _TOS_FIFO_H_ - -typedef struct k_fifo_st { -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_obj_t knl_obj; -#endif - - int beg; - int end; - size_t cnt; - uint8_t *buf; - size_t siz; -} k_fifo_t; - -/** - * @brief Create a fifo. - * Create a fifo. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * @param[in] buffer memory buffer provided to be as the inner buffer. - * @param[in] size size of the memory buffer. - * - * @return errno - * @retval #K_ERR_OBJ_PTR_NULL fifo is a NULL pointer. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_fifo_create(k_fifo_t *fifo, uint8_t *buffer, size_t size); - -/** - * @brief Destroy a fifo. - * Destroy a fifo. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * - * @return errno - * @retval #K_ERR_OBJ_PTR_NULL fifo is a NULL pointer. - * @retval #K_ERR_OBJ_INVALID not a valid pointer to a fifo. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_fifo_destroy(k_fifo_t *fifo); - -/** - * @brief Push data into fifo. - * Push one single data into the fifo. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * @param[in] data data to push into the fifo. - * - * @return errno - * @retval #K_ERR_FIFO_FULL the fifo is full. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_fifo_push(k_fifo_t *fifo, uint8_t data); - -/** - * @brief Push stream into fifo. - * Push a stream data into the fifo. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * @param[IN] stream stream to be pushed into the fifo. - * @param[OUT] size size of the stream. - * - * @return the actual number of the data pushed into the fifo. - */ -__API__ int tos_fifo_push_stream(k_fifo_t *fifo, uint8_t *stream, size_t size); - -/** - * @brief Pop data from fifo. - * Pop one single data from the fifo. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * @param[OUT] out one signle buffer to hold the data poped from the fifo. - * - * @return errno - * @retval #K_ERR_FIFO_EMPTY the fifo is empty. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_fifo_pop(k_fifo_t *fifo, uint8_t *out); - -/** - * @brief Pop stream from fifo. - * Pop a stream data from the fifo. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * @param[OUT] buffer pointer to the buffer to receive the stream poped. - * @param[OUT] size size of the buffer. - * - * @return the actual number of the data poped from the fifo. - */ -__API__ int tos_fifo_pop_stream(k_fifo_t *fifo, uint8_t *buffer, size_t size); - -/** - * @brief Flush fifo. - * Flush/reset the fifo. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * - * @return None. - */ -__API__ void tos_fifo_flush(k_fifo_t *fifo); - -/** - * @brief Whether the fifo is empty. - * Whether the fifo is empty. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * - * @return whether the fifo is emtpy. - * @retval #0 the fifo is not empty. - * @retval #Not 0 the fifo is empty. - */ -__API__ int tos_fifo_is_empty(k_fifo_t *fifo); - -/** - * @brief Whether the fifo is full. - * Whether the fifo is full. - * - * @attention None - * - * @param[in] fifo pointer to the handler of the fifo. - * - * @return whether the fifo is full. - * @retval #0 the fifo is not full. - * @retval #Not 0 the fifo is full. - */ -__API__ int tos_fifo_is_full(k_fifo_t *fifo); - -#endif // _TOS_FIFO_H_ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_global.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_global.h deleted file mode 100644 index 9193d51c..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_global.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifndef _TOS_GLOBAL_H_ -#define _TOS_GLOBAL_H_ - -/* interrupt nesting count */ -extern k_nesting_t k_irq_nest_cnt; - -/* schedule lock nesting count */ -extern k_nesting_t k_sched_lock_nest_cnt; - -/* kernel running state */ -extern knl_state_t k_knl_state; - -/* ready queue of tasks */ -extern readyqueue_t k_rdyq; - -/* ticks since boot up */ -extern k_tick_t k_tick_count; - -/* current task */ -extern k_task_t *k_curr_task; -/* next task to run */ -extern k_task_t *k_next_task; - -/* idle task related stuff */ -extern k_task_t k_idle_task; -extern k_stack_t k_idle_task_stk[]; -extern k_stack_t *const k_idle_task_stk_addr; -extern size_t const k_idle_task_stk_size; - -/* list to hold all the task delayed or pend for timeout */ -extern k_list_t k_tick_list; - -/* how many ticks will be triggered in a second */ -extern k_tick_t k_cpu_tick_per_second; - -/* how many cycle per tick */ -extern k_cycle_t k_cpu_cycle_per_tick; - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u - -extern k_fault_log_writer_t k_fault_log_writer; - -#endif - -#if TOS_CFG_MMHEAP_EN > 0u -extern uint8_t k_mmheap_pool[] __ALIGNED__(4); -extern k_mmheap_ctl_t k_mmheap_ctl; -#endif - -#if TOS_CFG_ROUND_ROBIN_EN > 0u -extern k_timeslice_t k_robin_default_timeslice; -extern k_robin_state_t k_robin_state; -#endif - -#if TOS_CFG_TIMER_EN > 0u -/* list holding all the timer */ -extern timer_ctl_t k_timer_ctl; -#if TOS_CFG_TIMER_AS_PROC == 0u -extern k_task_t k_timer_task; -extern k_stack_t k_timer_task_stk[]; -extern k_prio_t const k_timer_task_prio; -extern k_stack_t *const k_timer_task_stk_addr; -extern size_t const k_timer_task_stk_size; -#endif -#endif - -#if (TOS_CFG_MSG_EN > 0u) -extern k_list_t k_msg_freelist; -extern k_msg_t k_msg_pool[]; -#endif - -#if TOS_CFG_PWR_MGR_EN > 0u -extern pm_device_ctl_t k_pm_device_ctl; - -extern idle_pwrmgr_mode_t k_idle_pwr_mgr_mode; - -extern k_cpu_lpwr_mode_t k_cpu_lpwr_mode; -#endif - -#if TOS_CFG_TICKLESS_EN > 0u -extern k_tickless_wkup_alarm_t *k_tickless_wkup_alarm[__LOW_POWER_MODE_DUMMY]; -#endif - -#endif /* _TOS_GLOBAL_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_klib.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_klib.h deleted file mode 100644 index 957c4c0c..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_klib.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef _TOS_KLIB_H_ -#define _TOS_KLIB_H_ - -#include -#include -#include -#include -#include - -#define TOS_OFFSET_OF_FIELD(type, field) \ - ((uint32_t)&(((type *)0)->field)) - -#define TOS_CONTAINER_OF_FIELD(ptr, type, field) \ - ((type *)((uint8_t *)(ptr) - TOS_OFFSET_OF_FIELD(type, field))) - -#define TOS_PTR_SANITY_CHECK(ptr) \ - do { \ - if (unlikely((ptr) == K_NULL)) { \ - return K_ERR_OBJ_PTR_NULL; \ - } \ - } while(0) - -#define TOS_IN_IRQ_CHECK() \ - do { \ - if (unlikely(knl_is_inirq())) { \ - return K_ERR_IN_IRQ; \ - } \ - } while(0) - -// currently we use default microlib supplied by mdk -#define tos_kprintf(...) printf(__VA_ARGS__); - -#define tos_kprintln(...) \ - printf(__VA_ARGS__); \ - printf("\n"); - -#endif /* _TOS_KLIB_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_ktypes.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_ktypes.h deleted file mode 100644 index 7d5f9f57..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_ktypes.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _TOS_KTYPES_H_ -#define _TOS_KTYPES_H_ - -#include - -typedef uint8_t k_prio_t; -typedef uint8_t k_stack_t; -typedef uint8_t k_task_state_t; - -typedef uint8_t k_nesting_t; - -typedef uint16_t k_opt_t; -typedef uint16_t k_sem_cnt_t; -typedef uint32_t k_event_flag_t; - -typedef uint32_t k_time_t; -typedef uint32_t k_timeslice_t; - -typedef uint32_t k_cycle_t; -typedef uint64_t k_tick_t; - -#define K_TRUE (1u) -#define K_FALSE (0u) - -#ifndef K_NULL -#define K_NULL 0 -#endif - -#endif /* _TOS_KTYPES_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_list.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_list.h deleted file mode 100644 index 9abd889e..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_list.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef _TOS_LIST_H_ -#define _TOS_LIST_H_ - -typedef struct k_list_node_st { - struct k_list_node_st *next; - struct k_list_node_st *prev; -} k_list_t; - -#define TOS_LIST_NODE(node) \ - { &(node), &(node) } - -#define TOS_LIST_DEFINE(list) \ - k_list_t list = { &(list), &(list) } - -#define TOS_LIST_ENTRY(list, type, field) \ - TOS_CONTAINER_OF_FIELD(list, type, field) - -#define TOS_LIST_FIRST_ENTRY(list, type, field) \ - TOS_LIST_ENTRY((list)->next, type, field) - -#define TOS_LIST_FIRST_ENTRY_OR_NULL(list, type, field) \ - (tos_list_empty(list) ? K_NULL : TOS_LIST_FIRST_ENTRY(list, type, field)) - -#define TOS_LIST_FOR_EACH(curr, list) \ - for (curr = (list)->next; curr != (list); curr = curr->next) - -#define TOS_LIST_FOR_EACH_PREV(curr, list) \ - for (curr = (list)->prev; curr != (list); curr = curr->prev) - -#define TOS_LIST_FOR_EACH_SAFE(curr, next, list) \ - for (curr = (list)->next, next = curr->next; curr != (list); \ - curr = next, next = curr->next) - -#define TOS_LIST_FOR_EACH_PREV_SAFE(curr, next, list) \ - for (curr = (list)->prev, next = curr->prev; \ - curr != (list); \ - curr = next, next = curr->prev) - -__STATIC_INLINE__ void _list_add(k_list_t *node, k_list_t *prev, k_list_t *next) -{ - next->prev = node; - node->next = next; - node->prev = prev; - prev->next = node; -} - -__STATIC_INLINE__ void _list_del(k_list_t *prev, k_list_t *next) -{ - next->prev = prev; - prev->next = next; -} - -__STATIC_INLINE__ void _list_del_entry(k_list_t *entry) -{ - _list_del(entry->prev, entry->next); -} - -__API__ __STATIC_INLINE__ void tos_list_init(k_list_t *list) -{ - list->next = list; - list->prev = list; -} - -__API__ __STATIC_INLINE__ void tos_list_add(k_list_t *node, k_list_t *list) -{ - _list_add(node, list, list->next); -} - -__API__ __STATIC_INLINE__ void tos_list_add_tail(k_list_t *node, k_list_t *list) -{ - _list_add(node, list->prev, list); -} - -__API__ __STATIC_INLINE__ void tos_list_del(k_list_t *entry) -{ - _list_del(entry->prev, entry->next); -} - -__API__ __STATIC_INLINE__ void tos_list_del_init(k_list_t *entry) -{ - _list_del_entry(entry); - tos_list_init(entry); -} - -__API__ __STATIC_INLINE__ void tos_list_move(k_list_t *node, k_list_t *list) -{ - _list_del_entry(node); - tos_list_add(node, list); -} - -__API__ __STATIC_INLINE__ void tos_list_move_tail(k_list_t *node, k_list_t *list) -{ - _list_del_entry(node); - tos_list_add_tail(node, list); -} - -__API__ __STATIC_INLINE__ int tos_list_empty(const k_list_t *list) -{ - return list->next == list; -} - -#endif /* _TOS_LIST_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmblk.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmblk.h deleted file mode 100644 index 2f4a666e..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmblk.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef _TOS_MMBLK_H_ -#define _TOS_MMBLK_H_ - -#if TOS_CFG_MMBLK_EN > 0u - -#define K_MMBLK_NEXT_BLK(blk_curr, blk_size) ((void *)((cpu_addr_t)blk_curr + blk_size)) -#define K_MMBLK_ALIGN_MASK (sizeof(void *) - 1u) - -typedef struct k_mmblk_pool_st { -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_obj_t knl_obj; -#endif - - void *pool_start; - void *free_list; - size_t blk_size; - size_t blk_max; - size_t blk_free; -} k_mmblk_pool_t; - -/** - * @brief Create a memory manage block pool. - * Create a memory manage block pool. - * - * @attention None - * - * @param[in] mbp pointer to the memory block pool handler. - * @param[in] pool_start start address of the pool. - * @param[in] blk_num number of the blocks in the pool. - * @param[in] blk_size size of each block in the pool. - * - * @return errcode - * @retval #K_ERR_MMBLK_INVALID_POOL_ADDR start address of the pool is invalid. - * @retval #K_ERR_MMBLK_INVALID_BLK_SIZE size of the block is invalid. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mmblk_pool_create(k_mmblk_pool_t *mbp, void *pool_start, size_t blk_num, size_t blk_size); - -/** - * @brief Destroy a memory manage block pool. - * Destroy a memory manage block pool. - * - * @attention None - * - * @param[in] mbp pointer to the memory block pool handler. - * - * @return errcode - * @retval #K_ERR_OBJ_INVALID mbp is not a valid memory block pool handler. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mmblk_pool_destroy(k_mmblk_pool_t *mbp); - -/** - * @brief Create a memory manage block pool. - * Create a memory manage block pool. - * - * @attention None - * - * @param[in] mbp pointer to the memory block pool handler. - * @param[in] pool_start start address of the pool. - * @param[in] blk_num number of the blocks in the pool. - * @param[in] blk_size size of each block in the pool. - * - * @return errcode - * @retval #K_ERR_MMBLK_POOL_EMPTY the pool is empty. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mmblk_alloc(k_mmblk_pool_t *mbp, void **blk); - -/** - * @brief Create a memory manage block pool. - * Create a memory manage block pool. - * - * @attention None - * - * @param[in] mbp pointer to the memory block pool handler. - * @param[in] pool_start start address of the pool. - * @param[in] blk_num number of the blocks in the pool. - * @param[in] blk_size size of each block in the pool. - * - * @return errcode - * @retval #K_ERR_MMBLK_POOL_FULL the pool is full. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mmblk_free(k_mmblk_pool_t *mbp, void *blk); - -#endif - -#endif /* _TOS_MMBLK_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmheap.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmheap.h deleted file mode 100644 index e14e7e36..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mmheap.h +++ /dev/null @@ -1,207 +0,0 @@ -/* -** Two Level Segregated Fit memory allocator, version 3.1. -** Written by Matthew Conte -** http://tlsf.baisoku.org -** -** Based on the original documentation by Miguel Masmano: -** http://www.gii.upv.es/tlsf/main/docs -** -** This implementation was written to the specification -** of the document, therefore no GPL restrictions apply. -** -** Copyright (c) 2006-2016, Matthew Conte -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted provided that the following conditions are met: -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** * Neither the name of the copyright holder nor the -** names of its contributors may be used to endorse or promote products -** derived from this software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL MATTHEW CONTE BE LIABLE FOR ANY -** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _TOS_MMHEAP_H_ -#define _TOS_MMHEAP_H_ - -#if TOS_CFG_MMHEAP_EN > 0u - -/** - * log2 of number of linear subdivisions of block sizes. Larger - * values require more memory in the control structure. Values of - * 4 or 5 are typical. - */ -#define K_MMHEAP_SL_INDEX_COUNT_LOG2 5 - -/* All allocation sizes and addresses are aligned to 4 bytes. */ -#define K_MMHEAP_ALIGN_SIZE_LOG2 2 -#define K_MMHEAP_ALIGN_SIZE (1 << K_MMHEAP_ALIGN_SIZE_LOG2) - -/* - * We support allocations of sizes up to (1 << K_MMHEAP_FL_INDEX_MAX) bits. - * However, because we linearly subdivide the second-level lists, and - * our minimum size granularity is 4 bytes, it doesn't make sense to - * create first-level lists for sizes smaller than K_MMHEAP_SL_INDEX_COUNT * 4, - * or (1 << (K_MMHEAP_SL_INDEX_COUNT_LOG2 + 2)) bytes, as there we will be - * trying to split size ranges into more slots than we have available. - * Instead, we calculate the minimum threshold size, and place all - * blocks below that size into the 0th first-level list. - */ -#define K_MMHEAP_FL_INDEX_MAX 30 -#define K_MMHEAP_SL_INDEX_COUNT (1 << K_MMHEAP_SL_INDEX_COUNT_LOG2) -#define K_MMHEAP_FL_INDEX_SHIFT (K_MMHEAP_SL_INDEX_COUNT_LOG2 + K_MMHEAP_ALIGN_SIZE_LOG2) -#define K_MMHEAP_FL_INDEX_COUNT (K_MMHEAP_FL_INDEX_MAX - K_MMHEAP_FL_INDEX_SHIFT + 1) - -#define K_MMHEAP_SMALL_BLOCK_SIZE (1 << K_MMHEAP_FL_INDEX_SHIFT) - -#define K_MMHEAP_BLOCK_CURR_FREE (1 << 0) -#define K_MMHEAP_BLOCK_PREV_FREE (1 << 1) -#define K_MMHEAP_BLOCK_SIZE_MASK ~(K_MMHEAP_BLOCK_CURR_FREE | K_MMHEAP_BLOCK_PREV_FREE) -#define K_MMHEAP_BLOCK_STATE_MASK (K_MMHEAP_BLOCK_CURR_FREE | K_MMHEAP_BLOCK_PREV_FREE) - -/** - * Block structure. - * - * There are several implementation subtleties involved: - * - The prev_phys_block field is only valid if the previous block is free. - * - The prev_phys_block field is actually stored at the end of the - * previous block. It appears at the beginning of this structure only to - * simplify the implementation. - * - The next_free / prev_free fields are only valid if the block is free. - */ -typedef struct mmheap_blk_st { - struct mmheap_blk_st *prev_phys_blk; - - size_t size; - - struct mmheap_blk_st *next_free; - struct mmheap_blk_st *prev_free; -} mmheap_blk_t; - -/** - * A free block must be large enough to store its header minus the size of - * the prev_phys_block field, and no larger than the number of addressable - * bits for FL_INDEX. - */ -#define K_MMHEAP_BLK_SIZE_MIN (sizeof(mmheap_blk_t) - sizeof(mmheap_blk_t *)) -#define K_MMHEAP_BLK_SIZE_MAX (1 << K_MMHEAP_FL_INDEX_MAX) - -#define K_MMHEAP_BLK_HEADER_OVERHEAD (sizeof(size_t)) -#define K_MMHEAP_BLK_START_OFFSET (TOS_OFFSET_OF_FIELD(mmheap_blk_t, size) + sizeof(size_t)) - -/** - * memory heap control - */ -typedef struct k_mmheap_control_st { - mmheap_blk_t block_null; /**< Empty lists point at this block to indicate they are free. */ - - uint32_t fl_bitmap; /**< Bitmaps for free lists. */ - uint32_t sl_bitmap[K_MMHEAP_FL_INDEX_COUNT]; - - mmheap_blk_t *blocks[K_MMHEAP_FL_INDEX_COUNT][K_MMHEAP_SL_INDEX_COUNT]; /**< Head of free lists. */ -} k_mmheap_ctl_t; - -/** - * @brief Add a pool. - * Add addtional pool to the heap. - * - * @attention None - * - * @param[in] pool_start start address of the pool. - * @param[in] pool_size size of the pool. - * - * @return errcode - * @retval #K_ERR_MMHEAP_INVALID_POOL_ADDR start address of the pool is invalid. - * @retval #K_ERR_MMHEAP_INVALID_POOL_SIZE size of the pool is invalid. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mmheap_pool_add(void *pool_start, size_t pool_size); - -/** - * @brief Remove a pool. - * Remove a pool from the heap. - * - * @attention None - * - * @param[in] pool_start start address of the pool. - * - * @return None - */ -__API__ void tos_mmheap_pool_rmv(void *pool_start); - -/** - * @brief Alloc memory. - * Allocate size bytes and returns a pointer to the allocated memory. - * - * @attention size should no bigger than K_MMHEAP_BLK_SIZE_MAX. - * - * @param[in] size size of the memory. - * - * @return the pointer to the allocated memory. - */ -__API__ void *tos_mmheap_alloc(size_t size); - -__API__ void *tos_mmheap_calloc(size_t num, size_t size); - -/** - * @brief Alloc start address aligned memory from the heap. - * Alloc aligned address and specified size memory from the heap. - * - * @attention - * - * @param[in] size size of the memory. - * @param[in] align address align mask of the memory. - * - * @return the pointer to the allocated memory. - */ -__API__ void *tos_mmheap_aligned_alloc(size_t size, size_t align); - -/** - * @brief Realloc memory from the heap. - * Change the size of the memory block pointed to by ptr to size bytes. - * - * @attention - *
    - *
  • if ptr is K_NULL, then the call is equivalent to tos_mmheap_alloc(size), for all values of size. - *
  • if ptr is if size is equal to zero, and ptr is not K_NULL, then the call is equivalent to tos_mmheap_free(ptr). - *
- * - * @param[in] ptr old pointer to the memory space. - * @param[in] size new size of the memory space. - * - * @return the new pointer to the allocated memory. - */ -__API__ void *tos_mmheap_realloc(void *ptr, size_t size); - -/** - * @brief Free the memory. - * Free the memory space pointed to by ptr, which must have been returned by a previous call to tos_mmheap_alloc(), tos_mmheap_aligned_alloc(), or tos_mmheap_realloc(). - * - * @attention - * - * @param[in] ptr pointer to the memory. - * - * @return None. - */ -__API__ void tos_mmheap_free(void *ptr); - -__KERNEL__ k_err_t mmheap_init(void *pool_start, size_t pool_size); - -#endif - -#endif /* _TOS_MMHEAP_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_msg.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_msg.h deleted file mode 100644 index 1e6d5a4b..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_msg.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _TOS_MSG_H_ -#define _TOS_MSG_H_ - -#define TOS_OPT_MSG_PUT_LIFO (k_opt_t)0x0001 -#define TOS_OPT_MSG_PUT_FIFO (k_opt_t)0x0002 - -typedef struct k_message_st { - k_list_t list; - void *msg_addr; - size_t msg_size; -} k_msg_t; - -typedef struct k_msg_queue_st { -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_obj_t knl_obj; -#endif - - k_list_t queue_head; -} k_msg_queue_t; - -/** - * @brief Create a message queue. - * Initialize a message queue. - * - * @attention None - * - * @param[IN] msg_queue the pointer to the handler of the message queue. - * - * @return errcode. - * @retval #K_ERR_OBJ_PTR_NULL msg_queue is a null pointer - * @retval #K_ERR_NONE return successfully - */ -__API__ k_err_t tos_msg_queue_create(k_msg_queue_t *msg_queue); - -/** - * @brief Destroy a message queue. - * - * @attention None - * - * @param[IN] msg_queue the pointer to the handler of the message queue. - * - * @return errcode. - * @retval #K_ERR_OBJ_PTR_NULL msg_queue is a null pointer - * @retval #K_ERR_OBJ_INVALID msg_queue is not a valid pointer to a message queue - * @retval #K_ERR_NONE return successfully - */ -__API__ k_err_t tos_msg_queue_destroy(k_msg_queue_t *msg_queue); - -/** - * @brief Get a message. - * Get a message from the queue. - * - * @attention None - * - * @param[IN] msg_queue the pointer to the handler of the message queue. - * @param[OUT] msg_body the pointer to the body of the message. - * @param[OUT] msg_size the pointer to the size of the message. - * - * @return errcode. - * @retval #K_ERR_QUEUE_EMPTY the queue is empty. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_msg_queue_get(k_msg_queue_t *msg_queue, void **msg_addr, size_t *msg_size); - -/** - * @brief Put a message. - * Put a message to the queue. - * - * @attention None - * - * @param[IN] msg_queue the pointer to the handler of the message queue. - * @param[IN] msg_body the pointer to the body of the message. - * @param[IN] msg_size the pointer to the size of the message. - * @param[IN] opt option for the function call. - * - * @return errcode. - * @retval #K_ERR_QUEUE_FULL the queue is full. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_msg_queue_put(k_msg_queue_t *msg_queue, void *msg_addr, size_t msg_size, k_opt_t opt); - -/** - * @brief Flush all of the messages. - * Flush all of the messages in the queue. - * - * @attention None - * - * @param[IN] msg_queue the pointer to the handler of the message queue. - * - * @return None. - */ -__API__ void tos_msg_queue_flush(k_msg_queue_t *msg_queue); - -__KERNEL__ void msgpool_init(void); - -#endif /* _TOS_MSG_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mutex.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mutex.h deleted file mode 100644 index d87abec7..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_mutex.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _TOS_MUTEX_H_ -#define _TOS_MUTEX_H_ - -#if TOS_CFG_MUTEX_EN > 0u - -typedef struct k_mutex_st { - pend_obj_t pend_obj; - k_nesting_t pend_nesting; - k_task_t *owner; - k_prio_t owner_orig_prio; - k_list_t owner_list; -} k_mutex_t; - -/** - * @brief Create a mutex. - * create a mutex. - * - * @attention None - * - * @param[in] mutex pointer to the handler of the mutex. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mutex_create(k_mutex_t *mutex); - -/** - * @brief Destroy a mutex. - * destroy a mutex. - * - * @attention None - * - * @param[in] mutex pointer to the handler of the mutex. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mutex_destroy(k_mutex_t *mutex); - -/** - * @brief Pend a mutex. - * pend a mutex. - * - * @attention The task will keep blocked until the mutex is obtained or a timeout comes. - * - * @param[in] mutex pointer to the handler of the mutex. - * @param[in] timeout how much time(in k_tick_t) we would like to wait. - * - * @return errcode - * @retval #K_ERR_MUTEX_NESTING_OVERFLOW we are the owner of the mutex, and we are nesting pend too much on this mutex. - * @retval #K_ERR_MUTEX_NESTING we are the owner of the mutex, and we are nesting pend on it. - * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. - * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. - * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. - * @retval #K_ERR_PEND_DESTROY the mutex we are pending is destroyed. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mutex_pend_timed(k_mutex_t *mutex, k_tick_t timeout); - -/** - * @brief Pend a mutex. - * pend a mutex. - * - * @attention The task will keep blocked until the mutex is obtained. - * - * @param[in] mutex pointer to the handler of the mutex. - * - * @return errcode - * @retval #K_ERR_MUTEX_NESTING_OVERFLOW we are the owner of the mutex, and we are nesting pend too much on this mutex. - * @retval #K_ERR_MUTEX_NESTING we are the owner of the mutex, and we are nesting pend on it. - * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. - * @retval #K_ERR_PEND_DESTROY the mutex we are pending is destroyed. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mutex_pend(k_mutex_t *mutex); - -/** - * @brief Post a mutex. - * post a mutex. - * - * @attention None - * - * @param[in] mutex pointer to the handler of the mutex. - * - * @return errcode - * @retval #K_ERR_MUTEX_NOT_OWNER we are posting a mutex of which the owner is not us. - * @retval #K_ERR_MUTEX_NESTING we are posting a mutex owned by us, and we are still in a nesting. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_mutex_post(k_mutex_t *mutex); - -__KERNEL__ void mutex_release(k_mutex_t *mutex); - -#endif - -#endif /* _TOS_MUTEX_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_pend.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_pend.h deleted file mode 100644 index b1130b7a..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_pend.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef _TOS_PEND_H_ -#define _TOS_PEND_H_ - -typedef struct k_task_st k_task_t; - -/** - * The reason why we wakeup from a pend. - * when we wakeup, we need to know why. - */ -typedef enum pend_state_en { - PEND_STATE_NONE, /**< nothing. */ - PEND_STATE_POST, /**< someone has post, we get what we want. */ - PEND_STATE_TIMEOUT, /**< a post has never came until time is out. */ - PEND_STATE_DESTROY, /**< someone has destroyed what we are pending for. */ - PEND_STATE_OWNER_DIE, /**< the pend object owner task is destroyed. */ -} pend_state_t; - -// what we are pending -/* actually, it's some kind of magic number, mainly for identifing whether the pend - is initialized, or whether user pass the correct parameter. - */ -typedef enum pend_type_en { - PEND_TYPE_NONE = 0x0000, - PEND_TYPE_SEM = 0x1BEE, - PEND_TYPE_MUTEX = 0x2BEE, - PEND_TYPE_EVENT = 0x3BEE, - PEND_TYPE_QUEUE = 0x4BEE, -} pend_type_t; - -typedef enum opt_post_en { - OPT_POST_ONE, - OPT_POST_ALL, -} opt_post_t; - -typedef struct pend_object_st { - pend_type_t type; - k_list_t list; -} pend_obj_t; - -__KERNEL__ void pend_object_init(pend_obj_t *object, pend_type_t type); - -__KERNEL__ void pend_object_deinit(pend_obj_t *object); - -__KERNEL__ int pend_object_verify(pend_obj_t *object, pend_type_t type); - -__KERNEL__ int pend_is_nopending(pend_obj_t *object); - -__KERNEL__ k_prio_t pend_highest_prio_get(pend_obj_t *object); - -__KERNEL__ void pend_list_remove(k_task_t *task); - -__KERNEL__ void pend_list_adjust(k_task_t *task); - -__KERNEL__ k_err_t pend_state2errno(pend_state_t state); - -__KERNEL__ void pend_task_wakeup(k_task_t *task, pend_state_t state); - -__KERNEL__ void pend_task_block(k_task_t *task, pend_obj_t *object, k_tick_t timeout); - -__KERNEL__ void pend_wakeup_one(pend_obj_t *object, pend_state_t state); - -__KERNEL__ void pend_wakeup_all(pend_obj_t *object, pend_state_t state); - -__KERNEL__ void pend_wakeup(pend_obj_t *object, pend_state_t state, opt_post_t opt); - -#endif /* _TOS_PEND_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_queue.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_queue.h deleted file mode 100644 index 01d49b31..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_queue.h +++ /dev/null @@ -1,102 +0,0 @@ -#ifndef _TOS_QUEUE_H_ -#define _TOS_QUEUE_H_ - -#if TOS_CFG_QUEUE_EN > 0u - -typedef struct k_queue_st { - pend_obj_t pend_obj; - k_msg_queue_t msg_queue; -} k_queue_t; - -/** - * @brief Create a queue. - * create a queue. - * - * @attention None - * - * @param[in] queue pointer to the handler of the queue. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_queue_create(k_queue_t *queue); - -/** - * @brief Destroy a queue. - * destroy a queue. - * - * @attention None - * - * @param[in] queue pointer to the handler of the queue. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_queue_destroy(k_queue_t *queue); - -/** - * @brief Flush a queue. - * flush a queue, clear all the msg in the queue. - * - * @attention None - * - * @param[in] queue pointer to the handler of the queue. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_queue_flush(k_queue_t *queue); - -/** - * @brief Pend a queue. - * pend a queue. - * - * @attention we DONNOT perform a memcpy when msg_addr returned, we just let the *msg_addr point to an inner memory block. - * that means you DONNOT need to alloc memory for msg_addr, msg_addr can just be a pointer. - * - * @param[in] queue pointer to the handler of the queue. - * @param[OUT] msg_addr a pointer point to the message we wanna recive. - * @param[OUT] msg_size pointer to the message size returned. - * @param[in] timeout how much time(in k_tick_t) we would like to wait. - * - * @return errcode - * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. - * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. - * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. - * @retval #K_ERR_PEND_DESTROY the queue we are pending is destroyed. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_queue_pend(k_queue_t *queue, void **msg_addr, size_t *msg_size, k_tick_t timeout); - -/** - * @brief Post a queue. - * post a queue and wakeup one pending task. - * - * @attention when tos_queue_post return successfully, only one task who are waitting for the queue will be woken up. - * - * @param[in] queue pointer to the handler of the queue. - * - * @return errcode - * @retval #K_ERR_QUEUE_FULL the message pool is full. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_queue_post(k_queue_t *queue, void *msg_addr, size_t msg_size); - -/** - * @brief Post a queue. - * post a queue and wakeup all the pending task. - * - * @attention when tos_queue_post_all return successfully, all of the tasks who are waitting for the queue will be woken up. - * - * @param[in] queue pointer to the handler of the queue. - * - * @return errcode - * @retval #K_ERR_QUEUE_FULL the message pool is full. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_queue_post_all(k_queue_t *queue, void *msg_addr, size_t msg_size); - -#endif - -#endif /* _TOS_QUEUE_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_robin.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_robin.h deleted file mode 100644 index f6678b67..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_robin.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _TOS_ROBIN_H_ -#define _TOS_ROBIN_H_ - -#if TOS_CFG_ROUND_ROBIN_EN > 0u - -typedef enum k_robin_state_en { - TOS_ROBIN_STATE_ENABLED, - TOS_ROBIN_STATE_DISABLED, -} k_robin_state_t; - -/** - * @brief Set time slice. - * Set time slice of a task. - * - * @attention None - * - * @param[in] task pointer to the handler of the task. - * @param[in] timeslice time slice of the task - * - * @return None - */ -__API__ void tos_robin_timeslice_set(k_task_t *task, k_timeslice_t timeslice); - -/** - * @brief Configure round robin. - * Set the round robin state and the default time slice of the task. - * - * @attention None - * - * @param[in] robin_state state of the round robin. - * @param[in] default_timeslice default time slice of the task. - * - * @return None - */ -__API__ void tos_robin_config(k_robin_state_t robin_state, k_timeslice_t default_timeslice); - -__KERNEL__ void robin_sched(k_prio_t prio); - -#endif - -#endif /* _TOS_ROBIN_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sched.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sched.h deleted file mode 100644 index b1634f84..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sched.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef _TOS_SCHED_H_ -#define _TOS_SCHED_H_ - -#define K_PRIO_TBL_SIZE ((TOS_CFG_TASK_PRIO_MAX + 31) / 32) -#define K_PRIO_TBL_SLOT_SIZE (32u) - -#define K_PRIO_NDX(prio) ((prio) >> 5u) /* prio / 32u */ -#define K_PRIO_BIT(prio) (1u << (K_PRIO_TBL_SLOT_SIZE - 1u - ((prio) & (K_PRIO_TBL_SLOT_SIZE - 1u)))) - -typedef struct readyqueue_st { - k_list_t task_list_head[TOS_CFG_TASK_PRIO_MAX]; - uint32_t prio_mask[K_PRIO_TBL_SIZE]; - k_prio_t highest_prio; -} readyqueue_t; - -__KERNEL__ void readyqueue_init(void); - -__KERNEL__ int readyqueue_is_prio_onlyone(k_prio_t prio); - -__KERNEL__ k_task_t *readyqueue_first_task_get(k_prio_t prio); - -__KERNEL__ k_task_t *readyqueue_highest_ready_task_get(void); - -__KERNEL__ void readyqueue_add_head(k_task_t *task); - -__KERNEL__ void readyqueue_add_tail(k_task_t *task); - -__KERNEL__ void readyqueue_add(k_task_t *task); - -__KERNEL__ void readyqueue_remove(k_task_t *task); - -__KERNEL__ void readyqueue_move_head_to_tail(k_prio_t prio); - -#endif /* _TOS_SCHED_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sem.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sem.h deleted file mode 100644 index 8997be70..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sem.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef _TOS_SEM_H_ -#define _TOS_SEM_H_ - -#if TOS_CFG_SEM_EN > 0u - -typedef struct k_sem_st { - pend_obj_t pend_obj; - k_sem_cnt_t count; -} k_sem_t; - -/** - * @brief Create a semaphore. - * create a semaphore. - * - * @attention None - * - * @param[in] sem pointer to the handler of the semaphore. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_sem_create(k_sem_t *sem, k_sem_cnt_t init_count); - -/** - * @brief Destroy a semaphore. - * destroy a semaphore. - * - * @attention None - * - * @param[in] semaphore pointer to the handler of the semaphore. - * - * @return errcode - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_sem_destroy(k_sem_t *sem); - -/** - * @brief Pend a semaphore. - * pend a semaphore. - * - * @attention None - * - * @param[in] sem pointer to the handler of the semaphore. - * @param[in] timeout how much time(in k_tick_t) we would like to wait. - * - * @return errcode - * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. - * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. - * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. - * @retval #K_ERR_PEND_DESTROY the semaphore we are pending is destroyed. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_sem_pend(k_sem_t *sem, k_tick_t timeout); - -/** - * @brief Post a semaphore. - * post a semaphore and wakeup one pending task. - * - * @attention when tos_sem_post return successfully, only one task who are waitting for the semaphore will be woken up. - * - * @param[in] sem pointer to the handler of the semaphore. - * - * @return errcode - * @retval #K_ERR_SEM_OVERFLOW we are nesting post a semaphore too much. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_sem_post(k_sem_t *sem); - -/** - * @brief Post a semaphore. - * post a semaphore and wakeup all the pending task. - * - * @attention when tos_sem_post_all return successfully, all of the tasks who are waitting for the semaphore will be woken up. - * - * @param[in] sem pointer to the handler of the semaphore. - * - * @return errcode - * @retval #K_ERR_SEM_OVERFLOW we are nesting post a semaphore too much. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_sem_post_all(k_sem_t *sem); - -#endif - -#endif /* _TOS_SEM_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sys.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sys.h deleted file mode 100644 index 11ef6aa1..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_sys.h +++ /dev/null @@ -1,143 +0,0 @@ -#ifndef _TOS_SYS_H_ -#define _TOS_SYS_H_ - -#define K_NESTING_LIMIT_IRQ (k_nesting_t)250u -#define K_NESTING_LIMIT_SCHED_LOCK (k_nesting_t)250u - -typedef enum knl_state_en { - KNL_STATE_STOPPED, - KNL_STATE_RUNNING, -} knl_state_t; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u -// some kind of magic number, mainly for identifing whether the object is initialized, or whether user pass the correct parameter. -typedef enum knl_obj_type_en { - KNL_OBJ_TYPE_NONE = 0x0000, - KNL_OBJ_TYPE_TASK = 0xDAD1, - KNL_OBJ_TYPE_TIMER = 0xDAD2, - KNL_OBJ_TYPE_MSG_QUEUE = 0xDAD4, - KNL_OBJ_TYPE_MMBLK_POOL = 0xDAD8, - KNL_OBJ_TYPE_FIFO = 0xDAE1, -} knl_obj_type_t; - -typedef struct knl_object_st { - knl_obj_type_t type; -} knl_obj_t; -#endif - -/** - * @brief Initialize the kernel. - * initialize the tos tiny kernel. - * - * @attention None - * - * @param None - * - * @return errcode - * @retval Non-#K_ERR_NONE return failed. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_knl_init(void); - -/** - * @brief Start the kernel. - * get the kernel start to run, which means start the multitask scheduling. - * - * @attention None - * - * @param None - * - * @return errcode - * @retval #K_ERR_KNL_RUNNING the kernel is already running. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_knl_start(void); - -/** - * @brief Get the kernel state. - * whether the kernel is running. - * - * @attention None - * - * @param None - * - * @return whether the kernel is running. - * @retval Non-0 the kernel is running. - * @retval 0 the kernel is not running. - */ -__API__ int tos_knl_is_running(void); - -/** - * @brief Kernel enter the interrupt. - * this function should be called in the entrance of a interrupt handler. - * - * @attention None - * - * @param None - * - * @return None - */ -__API__ void tos_knl_irq_enter(void); - -/** - * @brief Kernel exit the interrupt. - * this function should be called in the exit of a interrupt handler. - * - * @attention None - * - * @param None - * - * @return None - */ -__API__ void tos_knl_irq_leave(void); - -/** - * @brief Lock the scheduler. - * prevent the kernel from performing task schedule. - * - * @attention None - * - * @param None - * - * @return errcode - * @retval K_ERR_KNL_NOT_RUNNING the kernel is not running. - * @retval K_ERR_LOCK_NESTING_OVERFLOW the schedule lock nesting is overflow. - * @retval K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_knl_sched_lock(void); - -/** - * @brief Unlock the scheduler. - * re-enable the task schedule. - * - * @attention None - * - * @param None - * - * @return errcode - * @retval K_ERR_KNL_NOT_RUNNING the kernel is not running. - * @retval K_ERR_SCHED_NOT_LOCKED the scheduler is not locked. - * @retval K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_knl_sched_unlock(void); - -#if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ k_tick_t knl_next_expires_get(void); -#endif - -__KERNEL__ void knl_sched(void); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u -__KERNEL__ int knl_object_verify(knl_obj_t *object, knl_obj_type_t type); -__KERNEL__ int knl_object_init(knl_obj_t *object, knl_obj_type_t type); -__KERNEL__ int knl_object_deinit(knl_obj_t *object); -#endif - -__KERNEL__ int knl_is_sched_locked(void); -__KERNEL__ int knl_is_inirq(void); -__KERNEL__ int knl_is_idle(k_task_t *task); -__KERNEL__ int knl_is_self(k_task_t *task); -__KERNEL__ k_err_t knl_idle_init(void); - -#endif /* _TOS_SYS_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_task.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_task.h deleted file mode 100644 index 49e11ad1..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_task.h +++ /dev/null @@ -1,311 +0,0 @@ -#ifndef _TOS_TASK_H_ -#define _TOS_TASK_H_ - -// task state is just a flag, indicating which manager list we are in. - -// ready to schedule -// a task's pend_list is in readyqueue -#define K_TASK_STATE_READY (k_task_state_t)0x0000 - -// delayed, or pend for a timeout -// a task's tick_list is in k_tick_list -#define K_TASK_STATE_SLEEP (k_task_state_t)0x0001 - -// pend for something -// a task's pend_list is in some pend object's list -#define K_TASK_STATE_PEND (k_task_state_t)0x0002 - -// suspended -#define K_TASK_STATE_SUSPENDED (k_task_state_t)0x0004 - -// deleted -#define K_TASK_STATE_DELETED (k_task_state_t)0x0008 - -// actually we don't really need those TASK_STATE below, if you understand the task state deeply, the code can be much more elegant. - -// we are pending, also we are waitting for a timeout(eg. tos_sem_pend with a valid timeout, not TOS_TIME_FOREVER) -// both a task's tick_list and pend_list is not empty -#define K_TASK_STATE_PENDTIMEOUT (k_task_state_t)(K_TASK_STATE_PEND | K_TASK_STATE_SLEEP) - -// suspended when sleeping -#define K_TASK_STATE_SLEEP_SUSPENDED (k_task_state_t)(K_TASK_STATE_SLEEP | K_TASK_STATE_SUSPENDED) - -// suspened when pending -#define K_TASK_STATE_PEND_SUSPENDED (k_task_state_t)(K_TASK_STATE_PEND | K_TASK_STATE_SUSPENDED) - -// suspended when pendtimeout -#define K_TASK_STATE_PENDTIMEOUT_SUSPENDED (k_task_state_t)(K_TASK_STATE_PENDTIMEOUT | K_TASK_STATE_SUSPENDED) - - -// if you configure TOS_CFG_TASK_PRIO_MAX as 10, means the priority for kernel is (0 ... 9] -// the priority 9(TOS_CFG_TASK_PRIO_MAX - 1) is only for idle, so avaliable priority for you is (0 ... 8] -#define K_TASK_PRIO_IDLE (k_prio_t)(TOS_CFG_TASK_PRIO_MAX - (k_prio_t)1u) -#define K_TASK_PRIO_INVALID (k_prio_t)(TOS_CFG_TASK_PRIO_MAX) - -typedef void (*k_task_entry_t)(void *arg); - -/** - * task control block - */ -typedef struct k_task_st { - k_stack_t *sp; /**< task stack pointer. This lady always comes first, we use her in port_s.S for context switch. */ - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_obj_t knl_obj; /**< just for verification, test whether current object is really a task. */ -#endif - - char *name; /**< task name */ - k_task_entry_t entry; /**< task entry */ - void *arg; /**< argument for task entry */ - k_task_state_t state; /**< just state */ - k_prio_t prio; /**< just priority */ - - k_stack_t *stk_base; /**< task stack base address */ - size_t stk_size; /**< stack size of the task */ - - k_tick_t tick_expires; /**< if we are in k_tick_list, how much time will we wait for? */ - - k_list_t tick_list; /**< list for hooking us to the k_tick_list */ - k_list_t pend_list; /**< when we are ready, our pend_list is in readyqueue; when pend, in a certain pend object's list. */ - -#if TOS_CFG_MUTEX_EN > 0u - k_list_t mutex_own_list; /**< the list hold all the mutex we own. - When we die(tos_task_destroy), we have an obligation to wakeup all the task pending for those mutexs we own; - if not, those pending tasks may never get a change to wakeup. */ - k_prio_t prio_pending; /*< when tos_task_prio_change called, we may be just the owner of a mutex. - to avoid PRIORITY INVERSION, must make sure our priority is higher than any one who is pending for - the mutex we hold. So, if the prio_new of tos_task_prio_change is not appropriate - (may against the principle of PRIORITY INVERSION), we just mark the prio_new here, do the real priority - change in the right time(mutex_old_owner_release) later. */ -#endif - - pend_obj_t *pending_obj; /**< if we are pending, which pend object's list we are in? */ - pend_state_t pend_state; /**< why we wakeup from a pend */ - -#if TOS_CFG_ROUND_ROBIN_EN > 0u - k_timeslice_t timeslice_reload; /**< if current time slice is used up, use time_slice_reload to reload our time slice */ - k_timeslice_t timeslice; /**< how much time slice left for us? */ -#endif - -#if TOS_CFG_MSG_EN > 0u - void *msg_addr; /**< if we pend a queue successfully, our msg_addr and msg_size will be set by the queue poster */ - size_t msg_size; -#endif - -#if TOS_CFG_EVENT_EN > 0u - k_opt_t opt_event_pend; /**< if we are pending an event, what's the option for the pending(TOS_OPT_EVENT_PEND_*)? */ - k_event_flag_t flag_expect; /**< if we are pending an event, what event flag are we pending for ? */ - k_event_flag_t *flag_match; /**< if we pend an event successfully, flag_match will be set by the event poster, and will be returned - by tos_event_pend to the caller */ -#endif -} k_task_t; - -/** - * @brief Create a task. - * create a task. - * - * @attention None - * - * @param[in] task pointer to the handler of the task. - * @param[in] name name of the task. - * @param[in] entry running entry of the task. - * @param[in] arg argument for the entry of the task. - * @param[in] prio priority of the task. - * @param[in] stk_base stack base address of the task. - * @param[in] stk_size stack size of the task. - * @param[in] timeslice time slice of the task. - * @param[in] opt option for the function call. - * - * @return errcode - * @retval #K_ERR_TASK_STK_SIZE_INVALID stack size is invalid. - * @retval #K_ERR_TASK_PRIO_INVALID priority is invalid. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_task_create(k_task_t *task, - char *name, - k_task_entry_t entry, - void *arg, - k_prio_t prio, - k_stack_t *stk_base, - size_t stk_size, - k_timeslice_t timeslice); - -/** - * @brief Destroy a task. - * delete a task. - * - * @attention None - * - * @param[in] task pointer to the handler of the task to be deleted. - * - * @return errcode - * @retval #K_ERR_TASK_DESTROY_IDLE attempt to destroy idle task. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_task_destroy(k_task_t *task); - -/** - * @brief Delay current task for ticks. - * Delay for a specified amount of ticks. - * - * @attention None - * - * @param[in] delay amount of ticks to delay. - * - * @return errcode - * @retval #K_ERR_DELAY_ZERO delay is zero. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_task_delay(k_tick_t delay); - -/** - * @brief Resume task from delay. - * Resume a delayed task from delay. - * - * @attention None - * - * @param[in] task the pointer to the handler of the task. - * - * @return errcode - * @retval #K_ERR_TASK_NOT_DELAY task is not delayed. - * @retval #K_ERR_TASK_SUSPENDED task is suspended. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_task_delay_abort(k_task_t *task); - -/** - * @brief Suspend a task. - * Bring a task to sleep. - * - * @attention None - * - * @param[in] task pointer to the handler of the task to be resume. - * - * @return errcode - * @retval #K_ERR_TASK_SUSPEND_IDLE attempt to suspend idle task. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_task_suspend(k_task_t *task); - -/** - * @brief Resume a task. - * Bring a task to run. - * - * @attention None - * - * @param[in] task pointer to the handler of the task to be resume. - * - * @return errcode - * @retval #K_ERR_TASK_RESUME_SELF attempt to resume self-task. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_task_resume(k_task_t *task); - -/** - * @brief Change task priority. - * Change a priority of the task. - * - * @attention None - * - * @param[in] task pointer to the handler of the task to be resume. - * @param[in] prio_new new priority. - * - * @return errcode - * @retval #K_ERR_TASK_PRIO_INVALID new priority is invalid. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_task_prio_change(k_task_t *task, k_prio_t prio_new); - -/** - * @brief Quit schedule this time. - * Quit the cpu this time. - * - * @attention None - * - * @param None - * - * @return None - */ -__API__ void tos_task_yield(void); - - -#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u - -/** - * @brief Get the maximum stack draught depth of a task. - * - * @attention None - * - * @param[in] task pointer to the handler of the task. - * @param[out] depth task stack draught depth. - * - * @return errcode - * @retval #K_ERR_NONE get depth successfully. - * @retval #K_ERR_TASK_STK_OVERFLOW task stack is overflow. - */ -__API__ k_err_t tos_task_stack_draught_depth(k_task_t *task, int *depth); - -#endif - -__KERNEL__ __STATIC_INLINE__ int task_state_is_ready(k_task_t *task) -{ - return task->state == K_TASK_STATE_READY; -} - -__KERNEL__ __STATIC_INLINE__ int task_state_is_sleeping(k_task_t *task) -{ - return task->state & K_TASK_STATE_SLEEP; -} - -__KERNEL__ __STATIC_INLINE__ int task_state_is_pending(k_task_t *task) -{ - return task->state & K_TASK_STATE_PEND; -} - -__KERNEL__ __STATIC_INLINE__ int task_state_is_suspended(k_task_t *task) -{ - return task->state & K_TASK_STATE_SUSPENDED; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_reset_pending(k_task_t *task) -{ - task->state &= ~K_TASK_STATE_PEND; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_reset_sleeping(k_task_t *task) -{ - task->state &= ~K_TASK_STATE_SLEEP; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_reset_suspended(k_task_t *task) -{ - task->state &= ~K_TASK_STATE_SUSPENDED; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_set_suspended(k_task_t *task) -{ - task->state |= K_TASK_STATE_SUSPENDED; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_set_pend(k_task_t *task) -{ - task->state |= K_TASK_STATE_PEND; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_set_ready(k_task_t *task) -{ - task->state = K_TASK_STATE_READY; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_set_deleted(k_task_t *task) -{ - task->state = K_TASK_STATE_DELETED; -} - -__KERNEL__ __STATIC_INLINE__ void task_state_set_sleeping(k_task_t *task) -{ - task->state |= K_TASK_STATE_SLEEP; -} - -#endif /* _TOS_TASK_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_tick.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_tick.h deleted file mode 100644 index 1874f1a9..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_tick.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _TOS_TICK_H_ -#define _TOS_TICK_H_ - -/** - * @brief Systick interrupt handler. - * systick interrupt handler. - * - * @attention called from the systick interrupt entrance. - * - * @param None - * - * @return None - */ -__API__ void tos_tick_handler(void); - -__KERNEL__ void tick_update(k_tick_t tick); - -__KERNEL__ k_err_t tick_list_add(k_task_t *task, k_tick_t timeout); - -__KERNEL__ void tick_list_remove(k_task_t *task); - -#if TOS_CFG_TICKLESS_EN > 0u -__KERNEL__ k_tick_t tick_next_expires_get(void); -#endif - -#endif /* _TOS_TICK_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_time.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_time.h deleted file mode 100644 index 8374d3ef..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_time.h +++ /dev/null @@ -1,93 +0,0 @@ -#ifndef _TOS_TIME_H_ -#define _TOS_TIME_H_ - -// if you wanna pend for something forever, use TOS_TIME_FOREVER -#define TOS_TIME_FOREVER (k_tick_t)(-1) -// if you don't wanna wait when you pend nothing, use TOS_TIME_NOWAIT -#define TOS_TIME_NOWAIT (k_tick_t)0u - -// those two are not for you, for kernel only. -#define K_TIME_MILLISEC_PER_SEC 1000u -#define K_TIME_MAX (k_tick_t)(TOS_TIME_FOREVER - 1) - -/** - * @brief Get system tick. - * Get the number of ticks since boot. - * - * @attention None - * - * @param None - * - * @return tick count since boot - */ -__API__ k_tick_t tos_systick_get(void); - -/** - * @brief Set system tick. - * Set the number of ticks. - * - * @attention None - * - * @param tick systick count to set - * - * @return tick count since boot - */ -__API__ void tos_systick_set(k_tick_t tick); - -/** - * @brief Convert ticks to milliseconds. - * Convert tick to millisecond. - * - * @attention None - * - * @param[in] tick tick to convert. - * - * @return milliseconds equals to the ticks. - */ -__API__ k_time_t tos_tick2millisec(k_tick_t tick); - -/** - * @brief Convert milliseconds to ticks. - * Convert milliseconds to ticks. - * - * @attention None - * - * @param[in] millisec millisecond to convert. - * - * @return ticks equals to the millisecond. - */ -__API__ k_tick_t tos_millisec2tick(k_time_t millisec); - -/** - * @brief Sleep current task. - * Sleep for a specified amount of milliseconds. - * - * @attention None - * - * @param[in] millisec amount of milliseconds to delay. - * - * @return errcode - * @retval #K_ERR_DELAY_ZERO millisec is zero. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_sleep_ms(k_time_t millisec); - -/** - * @brief Sleep current task. - * Sleep for a specified amount of time. - * - * @attention None - * - * @param[in] hour amount of hours. - * @param[in] minute amount of minutes. - * @param[in] second amount of seconds. - * @param[in] millisec amount of milliseconds. - * - * @return errcode - * @retval #K_ERR_DELAY_ZERO time is zero. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_sleep_hmsm(k_time_t hour, k_time_t minute, k_time_t second, k_time_t millisec); - -#endif /* _TOS_TIME_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_timer.h b/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_timer.h deleted file mode 100644 index 179e1096..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/include/tos_timer.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef _TOS_TIMER_H_ -#define _TOS_TIMER_H_ - -#if TOS_CFG_TIMER_EN > 0u - -// if we just want the timer to run only once, this option should be passed to tos_timer_create. -#define TOS_OPT_TIMER_ONESHOT (k_opt_t)(0x0001u) - -// if we want the timer run periodically, this option should be passed to tos_timer_create. -#define TOS_OPT_TIMER_PERIODIC (k_opt_t)(0x0002u) - -/** - * state for timer - */ -typedef enum timer_state_en { - TIMER_STATE_UNUSED, /**< the timer has been destroyed */ - TIMER_STATE_STOPPED, /**< the timer has been created but not been started, or just be stopped(tos_timer_stop) */ - TIMER_STATE_RUNNING, /**< the timer has been created and been started */ - TIMER_STATE_COMPLETED /**< the timer has finished its expires, it can only happen when the timer's opt is TOS_OPT_TIMER_ONESHOT */ -} timer_state_t; - -// callback function type for a timer -typedef void (*k_timer_callback_t)(void *arg); - -/** - * timer control block - */ -typedef struct k_timer_st { -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_obj_t knl_obj; /**< just for verification, test whether current object is really a timer */ -#endif - - k_timer_callback_t cb; /**< callback when time is up */ - void *cb_arg; /**< argument for callback */ - k_list_t list; /**< list for hooking us to the k_tick_list */ - k_tick_t expires; /**< how much time left until time expires */ - k_tick_t delay; /**< how much time from now to begin the first run of the timer */ - k_tick_t period; /**< if the time expires, how much time after should we begin the next round */ - k_opt_t opt; /**< option for the timer, see TOS_OPT_TIMER_* */ - timer_state_t state; /**< state for the timer, see TIMER_STATE_* */ -} k_timer_t; - -typedef struct timer_control_st { - k_tick_t next_expires; - k_list_t list; -} timer_ctl_t; - -/** - * @brief Create a timer. - * Create a timer. - * - * @attention I dont't think a timer need a name. If you do, help yourself. - * - * @param[in] tmr pointer to the handler of the timer. - * @param[in] delay time interval for a timer to run. - * @param[in] period period for a timer to restart to run. - * @param[in] callback callback function called when the timer expires. - * @param[in] cb_arg argument for the callback. - * @param[in] opt option for the function call. - * - * @return errcode - * @retval #K_ERR_TIMER_INVALID_PERIOD period is invalid. - * @retval #K_ERR_TIMER_INVALID_DELAY delay is invalid. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_timer_create(k_timer_t *tmr, k_tick_t delay, k_tick_t period, - k_timer_callback_t callback, void *cb_arg, k_opt_t opt); - -/** - * @brief Delete a timer. - * Delete the timer. - * - * @attention None - * - * @param[in] tmr pointer to the handler of the timer. - * - * @return errcode - * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_timer_destroy(k_timer_t *tmr); - -/** - * @brief Start a timer. - * Start the timer to run. - * - * @attention None - * - * @param[in] tmr pointer to the handler of the timer. - * - * @return errcode - * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. - * @retval #K_ERR_TIMER_INVALID_STATE state of the timer is invalid. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_timer_start(k_timer_t *tmr); - -/** - * @brief Stop a timer. - * Stop the timer from running. - * - * @attention None - * - * @param[in] tmr pointer to the handler of the timer. - * - * @return errcode - * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. - * @retval #K_ERR_TIMER_STOPPED the timer is already stoppped. - * @retval #K_ERR_NONE return successfully. - */ -__API__ k_err_t tos_timer_stop(k_timer_t *tmr); - -#if TOS_CFG_TIMER_AS_PROC > 0u - -/** - * @brief Timer update function. - * When enable timer as a process function not a task, this will be the function entry. - * - * @attention None - * - * @param None - * - * @return None - */ -__KERNEL__ void timer_update(void); - -#endif - -__KERNEL__ k_err_t timer_init(void); - -__KERNEL__ k_tick_t timer_next_expires_get(void); - -#endif - -#endif /* _TOS_TIMER_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_event.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_event.c deleted file mode 100644 index 5aa776dc..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_event.c +++ /dev/null @@ -1,168 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_EVENT_EN > 0 - -__API__ k_err_t tos_event_create(k_event_t *event, k_event_flag_t init_flag) -{ - TOS_PTR_SANITY_CHECK(event); - - pend_object_init(&event->pend_obj, PEND_TYPE_EVENT); - event->flag = init_flag; - return K_ERR_NONE; -} - -__API__ k_err_t tos_event_destroy(k_event_t *event) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(event); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&event->pend_obj, PEND_TYPE_EVENT)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (!pend_is_nopending(&event->pend_obj)) { - pend_wakeup_all(&event->pend_obj, PEND_STATE_DESTROY); - } - - pend_object_deinit(&event->pend_obj); - event->flag = (k_event_flag_t)0u; - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__STATIC__ int event_is_match(k_event_flag_t event, k_event_flag_t flag_expect, k_event_flag_t *flag_match, k_opt_t opt_pend) -{ - if (opt_pend & TOS_OPT_EVENT_PEND_ALL) { - if ((event & flag_expect) == flag_expect) { - *flag_match = flag_expect; - return K_TRUE; - } - } else if (opt_pend & TOS_OPT_EVENT_PEND_ANY) { - if (event & flag_expect) { - *flag_match = event & flag_expect; - return K_TRUE; - } - } - return K_FALSE; -} - -__API__ k_err_t tos_event_pend(k_event_t *event, k_event_flag_t flag_expect, k_event_flag_t *flag_match, k_tick_t timeout, k_opt_t opt_pend) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(event); - TOS_PTR_SANITY_CHECK(flag_match); - TOS_IN_IRQ_CHECK(); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&event->pend_obj, PEND_TYPE_EVENT)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (!(opt_pend & TOS_OPT_EVENT_PEND_ALL) && !(opt_pend & TOS_OPT_EVENT_PEND_ANY)) { - return K_ERR_EVENT_PEND_OPT_INVALID; - } - - if ((opt_pend & TOS_OPT_EVENT_PEND_ALL) && (opt_pend & TOS_OPT_EVENT_PEND_ANY)) { - return K_ERR_EVENT_PEND_OPT_INVALID; - } - - TOS_CPU_INT_DISABLE(); - - if (event_is_match(event->flag, flag_expect, flag_match, opt_pend)) { - if (opt_pend & TOS_OPT_EVENT_PEND_CLR) { // destroy the bridge after get across the river - event->flag = (k_event_flag_t)0u; - } - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; - } - - if (timeout == TOS_TIME_NOWAIT) { - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_NOWAIT; - } - - if (knl_is_sched_locked()) { - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_SCHED_LOCKED; - } - - k_curr_task->flag_expect = flag_expect; - k_curr_task->flag_match = flag_match; - k_curr_task->opt_event_pend = opt_pend; - - pend_task_block(k_curr_task, &event->pend_obj, timeout); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - k_curr_task->flag_expect = (k_event_flag_t)0u; - k_curr_task->flag_match = (k_event_flag_t *)K_NULL; - k_curr_task->opt_event_pend = (k_opt_t)0u; - - return pend_state2errno(k_curr_task->pend_state); -} - -__STATIC__ k_err_t event_do_post(k_event_t *event, k_event_flag_t flag, opt_event_post_t opt_post) -{ - TOS_CPU_CPSR_ALLOC(); - k_task_t *task; - k_list_t *curr, *next; - - TOS_PTR_SANITY_CHECK(event); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&event->pend_obj, PEND_TYPE_EVENT)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (opt_post == OPT_EVENT_POST_KEP) { - event->flag |= flag; - } else { - event->flag = flag; - } - - TOS_CPU_INT_DISABLE(); - - TOS_LIST_FOR_EACH_SAFE(curr, next, &event->pend_obj.list) { - task = TOS_LIST_ENTRY(curr, k_task_t, pend_list); - - if (event_is_match(event->flag, task->flag_expect, task->flag_match, task->opt_event_pend)) { - pend_task_wakeup(TOS_LIST_ENTRY(curr, k_task_t, pend_list), PEND_STATE_POST); - - // if anyone pending the event has set the TOS_OPT_EVENT_PEND_CLR, then no wakeup for the others pendig for the event. - if (task->opt_event_pend & TOS_OPT_EVENT_PEND_CLR) { - event->flag = (k_event_flag_t)0u; - break; - } - } - } - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_event_post(k_event_t *event, k_event_flag_t flag) -{ - return event_do_post(event, flag, OPT_EVENT_POST_CLR); -} - -__API__ k_err_t tos_event_post_keep(k_event_t *event, k_event_flag_t flag) -{ - return event_do_post(event, flag, OPT_EVENT_POST_KEP); -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_fifo.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_fifo.c deleted file mode 100644 index 01e7a4c9..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_fifo.c +++ /dev/null @@ -1,196 +0,0 @@ -#include "tos.h" - -__STATIC_INLINE__ int fifo_next(k_fifo_t *fifo, int index) -{ - return (index + 1) % fifo->siz; -} - -__API__ k_err_t tos_fifo_create(k_fifo_t *fifo, uint8_t *buffer, size_t size) -{ - TOS_PTR_SANITY_CHECK(fifo); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_init(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO); -#endif - - fifo->beg = 0; - fifo->end = 0; - fifo->cnt = 0; - fifo->buf = buffer; - fifo->siz = size; - - return K_ERR_NONE; -} - -__API__ k_err_t tos_fifo_destroy(k_fifo_t *fifo) -{ - TOS_PTR_SANITY_CHECK(fifo); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return K_ERR_OBJ_INVALID; - } -#endif - - fifo->beg = 0; - fifo->end = 0; - fifo->cnt = 0; - fifo->buf = K_NULL; - fifo->siz = 0; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_deinit(&fifo->knl_obj); -#endif - - return K_ERR_NONE; -} - -__API__ k_err_t tos_fifo_push(k_fifo_t *fifo, uint8_t data) -{ - TOS_CPU_CPSR_ALLOC(); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (tos_fifo_is_full(fifo)) { - TOS_CPU_INT_ENABLE(); - return K_ERR_FIFO_FULL; - } - - fifo->buf[fifo->end] = data; - fifo->end = fifo_next(fifo, fifo->end); - ++fifo->cnt; - - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; -} - -__API__ int tos_fifo_push_stream(k_fifo_t *fifo, uint8_t *stream, size_t size) -{ - TOS_CPU_CPSR_ALLOC(); - int i = 0; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - while (!tos_fifo_is_full(fifo) && i < size) { - if (tos_fifo_push(fifo, stream[i]) != K_ERR_NONE) { - TOS_CPU_INT_ENABLE(); - return i; - } - ++i; - } - TOS_CPU_INT_ENABLE(); - return i; -} - -__API__ k_err_t tos_fifo_pop(k_fifo_t *fifo, uint8_t *out) -{ - TOS_CPU_CPSR_ALLOC(); - uint8_t data; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (tos_fifo_is_empty(fifo)) { - TOS_CPU_INT_ENABLE(); - return K_ERR_FIFO_EMPTY; - } - - data = fifo->buf[fifo->beg]; - fifo->beg = fifo_next(fifo, fifo->beg); - --fifo->cnt; - - TOS_CPU_INT_ENABLE(); - - *out = data; - return K_ERR_NONE; -} - -__API__ int tos_fifo_pop_stream(k_fifo_t *fifo, uint8_t *buffer, size_t size) -{ - TOS_CPU_CPSR_ALLOC(); - int i = 0; - uint8_t data; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - while (!tos_fifo_is_empty(fifo) && i < size) { - if (tos_fifo_pop(fifo, &data) != K_ERR_NONE) { - TOS_CPU_INT_ENABLE(); - return i; - } - buffer[i++] = data; - } - TOS_CPU_INT_ENABLE(); - return i; -} - -__API__ void tos_fifo_flush(k_fifo_t *fifo) -{ -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return; - } -#endif - - fifo->beg = 0; - fifo->end = 0; - fifo->cnt = 0; -} - -__API__ int tos_fifo_is_empty(k_fifo_t *fifo) -{ - TOS_CPU_CPSR_ALLOC(); - int is_empty = 0; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - is_empty = (fifo->cnt == 0); - TOS_CPU_INT_ENABLE(); - - return is_empty; -} - -__API__ int tos_fifo_is_full(k_fifo_t *fifo) -{ - TOS_CPU_CPSR_ALLOC(); - int is_full = 0; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&fifo->knl_obj, KNL_OBJ_TYPE_FIFO)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - is_full = (fifo->cnt == fifo->siz); - TOS_CPU_INT_ENABLE(); - - return is_full; -} - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_global.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_global.c deleted file mode 100644 index e0b8f53a..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_global.c +++ /dev/null @@ -1,69 +0,0 @@ -#include - -k_nesting_t k_irq_nest_cnt = (k_nesting_t)0; -k_nesting_t k_sched_lock_nest_cnt = (k_nesting_t)0; -knl_state_t k_knl_state = KNL_STATE_STOPPED; - -readyqueue_t k_rdyq; - -k_tick_t k_tick_count = (k_tick_t)0u; -k_task_t *k_curr_task = K_NULL; -k_task_t *k_next_task = K_NULL; - -k_task_t k_idle_task; -k_stack_t k_idle_task_stk[TOS_CFG_IDLE_TASK_STK_SIZE]; -k_stack_t *const k_idle_task_stk_addr = &k_idle_task_stk[0]; -size_t const k_idle_task_stk_size = TOS_CFG_IDLE_TASK_STK_SIZE; - -k_tick_t k_cpu_tick_per_second = TOS_CFG_CPU_TICK_PER_SECOND; - -k_cycle_t k_cpu_cycle_per_tick = (k_cycle_t)0u; - -TOS_LIST_DEFINE(k_tick_list); - -#if TOS_CFG_FAULT_BACKTRACE_EN > 0u -k_fault_log_writer_t k_fault_log_writer = fault_default_log_writer; -#endif - -#if TOS_CFG_MMHEAP_EN > 0u -uint8_t k_mmheap_pool[TOS_CFG_MMHEAP_POOL_SIZE] __ALIGNED__(4); -k_mmheap_ctl_t k_mmheap_ctl; -#endif - -#if TOS_CFG_ROUND_ROBIN_EN > 0u -k_timeslice_t k_robin_default_timeslice = TOS_CFG_CPU_TICK_PER_SECOND / 10; -k_robin_state_t k_robin_state = TOS_ROBIN_STATE_DISABLED; -#endif - -#if TOS_CFG_TIMER_EN > 0u -timer_ctl_t k_timer_ctl = { TOS_TIME_FOREVER, TOS_LIST_NODE(k_timer_ctl.list) }; - -#if TOS_CFG_TIMER_AS_PROC == 0u -k_task_t k_timer_task; -k_stack_t k_timer_task_stk[TOS_CFG_TIMER_TASK_STK_SIZE]; -k_prio_t const k_timer_task_prio = TOS_CFG_TIMER_TASK_PRIO; -k_stack_t *const k_timer_task_stk_addr = &k_timer_task_stk[0]; -size_t const k_timer_task_stk_size = TOS_CFG_TIMER_TASK_STK_SIZE; -#endif /* TOS_CFG_TIMER_AS_PROC == 0u */ - -#endif - -#if TOS_CFG_MSG_EN > 0u -TOS_LIST_DEFINE(k_msg_freelist); -k_msg_t k_msg_pool[TOS_CFG_MSG_POOL_SIZE]; -#endif - -#if TOS_CFG_PWR_MGR_EN > 0u -pm_device_ctl_t k_pm_device_ctl = { 0u }; - -/* default idle power manager mode is SLEEP */ -idle_pwrmgr_mode_t k_idle_pwr_mgr_mode = IDLE_POWER_MANAGER_MODE_SLEEP; - -/* default low power mode is SLEEP */ -k_cpu_lpwr_mode_t k_cpu_lpwr_mode = TOS_LOW_POWER_MODE_SLEEP; -#endif - -#if TOS_CFG_TICKLESS_EN > 0u -k_tickless_wkup_alarm_t *k_tickless_wkup_alarm[__LOW_POWER_MODE_DUMMY] = { K_NULL }; -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_mmblk.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_mmblk.c deleted file mode 100644 index f86ff99e..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_mmblk.c +++ /dev/null @@ -1,118 +0,0 @@ -#include - -#if TOS_CFG_MMBLK_EN > 0u - -__API__ k_err_t tos_mmblk_pool_create(k_mmblk_pool_t *mbp, void *pool_start, size_t blk_num, size_t blk_size) -{ - uint32_t i; - void *blk_curr; - void *blk_next; - - TOS_IN_IRQ_CHECK(); - TOS_PTR_SANITY_CHECK(pool_start); - - if (((cpu_addr_t)pool_start & K_MMBLK_ALIGN_MASK) != 0u) { - return K_ERR_MMBLK_INVALID_POOL_ADDR; - } - - if ((blk_size & K_MMBLK_ALIGN_MASK) != 0u) { - return K_ERR_MMBLK_INVALID_BLK_SIZE; - } - - blk_curr = pool_start; - blk_next = K_MMBLK_NEXT_BLK(blk_curr, blk_size); - - for (i = 0; i < blk_num - 1u; ++i) { - *(void **)blk_curr = blk_next; - blk_curr = blk_next; - blk_next = K_MMBLK_NEXT_BLK(blk_next, blk_size); - } - *(void **)blk_next = K_NULL; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_init(&mbp->knl_obj, KNL_OBJ_TYPE_MMBLK_POOL); -#endif - - mbp->pool_start = pool_start; - mbp->free_list = pool_start; - mbp->blk_free = blk_num; - mbp->blk_max = blk_num; - mbp->blk_size = blk_size; - return K_ERR_NONE; -} - -__API__ k_err_t tos_mmblk_pool_destroy(k_mmblk_pool_t *mbp) -{ - TOS_PTR_SANITY_CHECK(mbp); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&mbp->knl_obj, KNL_OBJ_TYPE_MMBLK_POOL)) { - return K_ERR_OBJ_INVALID; - } -#endif - - mbp->pool_start = K_NULL; - mbp->free_list = K_NULL; - mbp->blk_free = 0; - mbp->blk_max = 0; - mbp->blk_size = 0; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_deinit(&mbp->knl_obj); -#endif - - return K_ERR_NONE; -} - -__API__ k_err_t tos_mmblk_alloc(k_mmblk_pool_t *mbp, void **blk) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(mbp); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&mbp->knl_obj, KNL_OBJ_TYPE_MMBLK_POOL)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - if (mbp->blk_free == 0) { - TOS_CPU_INT_ENABLE(); - *blk = K_NULL; - return K_ERR_MMBLK_POOL_EMPTY; - } - *blk = mbp->free_list; - mbp->free_list = *(void **)mbp->free_list; - --mbp->blk_free; - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; -} - -__API__ k_err_t tos_mmblk_free(k_mmblk_pool_t *mbp, void *blk) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(mbp); - TOS_PTR_SANITY_CHECK(blk); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&mbp->knl_obj, KNL_OBJ_TYPE_MMBLK_POOL)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - if (mbp->blk_free >= mbp->blk_max) { - TOS_CPU_INT_ENABLE(); - return K_ERR_MMBLK_POOL_FULL; - } - *(void **)blk = mbp->free_list; - mbp->free_list = blk; - ++mbp->blk_free; - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_mmheap.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_mmheap.c deleted file mode 100644 index 1967f460..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_mmheap.c +++ /dev/null @@ -1,685 +0,0 @@ -/* -** Two Level Segregated Fit memory allocator, version 3.1. -** Written by Matthew Conte -** http://tlsf.baisoku.org -** -** Based on the original documentation by Miguel Masmano: -** http://www.gii.upv.es/tlsf/main/docs -** -** This implementation was written to the specification -** of the document, therefore no GPL restrictions apply. -** -** Copyright (c) 2006-2016, Matthew Conte -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted provided that the following conditions are met: -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** * Neither the name of the copyright holder nor the -** names of its contributors may be used to endorse or promote products -** derived from this software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL MATTHEW CONTE BE LIABLE FOR ANY -** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include - -#if TOS_CFG_MMHEAP_EN > 0u - -#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 0u) -__STATIC__ int generic_fls(uint32_t x) -{ - int r = 32; - if (!x) - return 0; - - if (!(x & 0xffff0000u)) { - x <<= 16; - r -= 16; - } - if (!(x & 0xff000000u)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf0000000u)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc0000000u)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x80000000u)) { - x <<= 1; - r -= 1; - } - return r; -} -#else -__STATIC__ int generic_fls(uint32_t x) -{ - return 32 - tos_cpu_clz(x); -} -#endif - -__STATIC__ int __ffs(uint32_t word) -{ - return generic_fls(word & (~word + 1)) - 1; -} - -__STATIC__ int __fls(uint32_t word) -{ - return generic_fls(word) - 1; -} - -/* -** TLSF utility functions. In most cases, these are direct translations of -** the documentation found in the white paper. -*/ -__STATIC__ void mapping_insert(size_t size, int *fli, int *sli) -{ - int fl, sl; - - if (size < K_MMHEAP_SMALL_BLOCK_SIZE) { - /* Store small blocks in first list. */ - fl = 0; - sl = (int)size / (K_MMHEAP_SMALL_BLOCK_SIZE / K_MMHEAP_SL_INDEX_COUNT); - } else { - fl = __fls(size); - sl = ((int)size >> (fl - K_MMHEAP_SL_INDEX_COUNT_LOG2)) ^ (1 << K_MMHEAP_SL_INDEX_COUNT_LOG2); - fl -= (K_MMHEAP_FL_INDEX_SHIFT - 1); - } - *fli = fl; - *sli = sl; -} - -/* This version rounds up to the next block size (for allocations) */ -__STATIC__ void mapping_search(size_t size, int *fli, int *sli) -{ - size_t round; - - if (size >= K_MMHEAP_SMALL_BLOCK_SIZE) { - round = (1 << (__fls(size) - K_MMHEAP_SL_INDEX_COUNT_LOG2)) - 1; - size += round; - } - mapping_insert(size, fli, sli); -} - -__STATIC__ size_t blk_size(const mmheap_blk_t *blk) -{ - return blk->size & K_MMHEAP_BLOCK_SIZE_MASK; -} - -__STATIC__ void blk_set_size(mmheap_blk_t *blk, size_t size) -{ - blk->size = size | (blk->size & K_MMHEAP_BLOCK_STATE_MASK); -} - -__STATIC__ int blk_is_free(const mmheap_blk_t *blk) -{ - return blk->size & K_MMHEAP_BLOCK_CURR_FREE; -} - -__STATIC__ void blk_set_free(mmheap_blk_t *blk) -{ - blk->size |= K_MMHEAP_BLOCK_CURR_FREE; -} - -__STATIC__ void blk_set_used(mmheap_blk_t *blk) -{ - blk->size &= ~K_MMHEAP_BLOCK_CURR_FREE; -} - -__STATIC__ int blk_is_prev_free(const mmheap_blk_t *blk) -{ - return blk->size & K_MMHEAP_BLOCK_PREV_FREE; -} - -__STATIC__ void blk_set_prev_free(mmheap_blk_t *blk) -{ - blk->size |= K_MMHEAP_BLOCK_PREV_FREE; -} - -__STATIC__ void blk_set_prev_used(mmheap_blk_t *blk) -{ - blk->size &= ~K_MMHEAP_BLOCK_PREV_FREE; -} - -__STATIC__ mmheap_blk_t *blk_from_ptr(const void *ptr) -{ - return (mmheap_blk_t *)((cpu_addr_t)ptr - K_MMHEAP_BLK_START_OFFSET); -} - -__STATIC__ void *blk_to_ptr(const mmheap_blk_t *blk) -{ - return (void *)((cpu_addr_t)blk + K_MMHEAP_BLK_START_OFFSET); -} - -/* Return location of next block after block of given size. */ -__STATIC__ mmheap_blk_t *offset_to_block(const void *ptr, int diff) -{ - return (mmheap_blk_t *)((cpu_addr_t)ptr + diff); -} - -/* Return location of previous block. */ -__STATIC__ mmheap_blk_t *blk_prev(const mmheap_blk_t *blk) -{ - return blk->prev_phys_blk; -} - -/* Return location of next existing block. */ -__STATIC__ mmheap_blk_t *blk_next(const mmheap_blk_t *blk) -{ - mmheap_blk_t *next_blk; - - next_blk = offset_to_block(blk_to_ptr(blk), blk_size(blk) - K_MMHEAP_BLK_HEADER_OVERHEAD); - return next_blk; -} - -/* Link a new block with its physical neighbor, return the neighbor. */ -__STATIC__ mmheap_blk_t *blk_link_next(mmheap_blk_t *blk) -{ - mmheap_blk_t *next_blk; - - next_blk = blk_next(blk); - next_blk->prev_phys_blk = blk; - return next_blk; -} - -__STATIC__ void blk_mark_as_free(mmheap_blk_t *blk) -{ - mmheap_blk_t *next_blk; - - /* Link the block to the next block, first. */ - next_blk = blk_link_next(blk); - blk_set_prev_free(next_blk); - blk_set_free(blk); -} - -__STATIC__ void blk_mark_as_used(mmheap_blk_t *blk) -{ - mmheap_blk_t *next_blk; - - next_blk = blk_next(blk); - blk_set_prev_used(next_blk); - blk_set_used(blk); -} - -__STATIC__ size_t align_up(size_t x, size_t align) -{ - return (x + (align - 1)) & ~(align - 1); -} - -__STATIC__ size_t align_down(size_t x, size_t align) -{ - return x - (x & (align - 1)); -} - -__STATIC__ void *align_ptr(const void *ptr, size_t align) -{ - return (void *)(((cpu_addr_t)ptr + (align -1)) & ~(align -1)); -} - -/* Insert a free block into the free block list. */ -__STATIC__ void insert_free_block(mmheap_blk_t *blk, int fl, int sl) -{ - mmheap_blk_t *curr; - - curr = k_mmheap_ctl.blocks[fl][sl]; - blk->next_free = curr; - blk->prev_free = &k_mmheap_ctl.block_null; - curr->prev_free = blk; - - /* - ** Insert the new block at the head of the list, and mark the first- - ** and second-level bitmaps appropriately. - */ - k_mmheap_ctl.blocks[fl][sl] = blk; - k_mmheap_ctl.fl_bitmap |= (1 << fl); - k_mmheap_ctl.sl_bitmap[fl] |= (1 << sl); -} - -/* Remove a free block from the free list.*/ -__STATIC__ void remove_free_block(mmheap_blk_t *blk, int fl, int sl) -{ - mmheap_blk_t *prev_blk; - mmheap_blk_t *next_blk; - - prev_blk = blk->prev_free; - next_blk = blk->next_free; - next_blk->prev_free = prev_blk; - prev_blk->next_free = next_blk; - - /* If this block is the head of the free list, set new head. */ - if (k_mmheap_ctl.blocks[fl][sl] == blk) { - k_mmheap_ctl.blocks[fl][sl] = next_blk; - - /* If the new head is null, clear the bitmap. */ - if (next_blk == &k_mmheap_ctl.block_null) { - k_mmheap_ctl.sl_bitmap[fl] &= ~(1 << sl); - - /* If the second bitmap is now empty, clear the fl bitmap. */ - if (!k_mmheap_ctl.sl_bitmap[fl]) { - k_mmheap_ctl.fl_bitmap &= ~(1 << fl); - } - } - } -} - -/* Remove a given block from the free list. */ -__STATIC__ void blk_remove(mmheap_blk_t *blk) -{ - int fl, sl; - - mapping_insert(blk_size(blk), &fl, &sl); - remove_free_block(blk, fl, sl); -} - -/* Insert a given block into the free list. */ -__STATIC__ void blk_insert(mmheap_blk_t *blk) -{ - int fl, sl; - - mapping_insert(blk_size(blk), &fl, &sl); - insert_free_block(blk, fl, sl); -} - -__STATIC__ int blk_can_split(mmheap_blk_t *blk, size_t size) -{ - return blk_size(blk) >= sizeof(mmheap_blk_t) + size; -} - -/* Split a block into two, the second of which is free. */ -__STATIC__ mmheap_blk_t *blk_split(mmheap_blk_t *blk, size_t size) -{ - mmheap_blk_t *remaining; - size_t remain_size; - - /* Calculate the amount of space left in the remaining block. */ - remaining = offset_to_block(blk_to_ptr(blk), size - K_MMHEAP_BLK_HEADER_OVERHEAD); - remain_size = blk_size(blk) - (size + K_MMHEAP_BLK_HEADER_OVERHEAD); - - blk_set_size(remaining, remain_size); - - blk_set_size(blk, size); - blk_mark_as_free(remaining); - - return remaining; -} - -/* Absorb a free block's storage into an adjacent previous free block. */ -__STATIC__ mmheap_blk_t *blk_absorb(mmheap_blk_t *prev_blk, mmheap_blk_t *blk) -{ - prev_blk->size += blk_size(blk) + K_MMHEAP_BLK_HEADER_OVERHEAD; - blk_link_next(prev_blk); - return prev_blk; -} - -/* Merge a just-freed block with an adjacent previous free block. */ -__STATIC__ mmheap_blk_t *blk_merge_prev(mmheap_blk_t *blk) -{ - mmheap_blk_t *prev_blk; - - if (blk_is_prev_free(blk)) { - prev_blk = blk_prev(blk); - blk_remove(prev_blk); - blk = blk_absorb(prev_blk, blk); - } - - return blk; -} - -/* Merge a just-freed block with an adjacent free block. */ -__STATIC__ mmheap_blk_t *blk_merge_next(mmheap_blk_t *blk) -{ - mmheap_blk_t *next_blk; - - next_blk = blk_next(blk); - if (blk_is_free(next_blk)) { - blk_remove(next_blk); - blk = blk_absorb(blk, next_blk); - } - - return blk; -} - -/* Trim any trailing block space off the end of a block, return to pool. */ -__STATIC__ void blk_trim_free(mmheap_blk_t *blk, size_t size) -{ - mmheap_blk_t *remaining_blk; - - if (blk_can_split(blk, size)) { - remaining_blk = blk_split(blk, size); - blk_link_next(blk); - blk_set_prev_free(remaining_blk); - blk_insert(remaining_blk); - } -} - -/* Trim any trailing block space off the end of a used block, return to pool. */ -__STATIC__ void blk_trim_used(mmheap_blk_t *blk, size_t size) -{ - mmheap_blk_t *remaining_blk; - - if (blk_can_split(blk, size)) { - /* If the next block is free, we must coalesce. */ - remaining_blk = blk_split(blk, size); - blk_set_prev_used(remaining_blk); - - remaining_blk = blk_merge_next(remaining_blk); - blk_insert(remaining_blk); - } -} - -__STATIC__ mmheap_blk_t *blk_trim_free_leading(mmheap_blk_t *blk, size_t size) -{ - mmheap_blk_t *remaining_blk; - - remaining_blk = blk; - if (blk_can_split(blk, size)) { - /* We want the 2nd block. */ - remaining_blk = blk_split(blk, size - K_MMHEAP_BLK_HEADER_OVERHEAD); - blk_set_prev_free(remaining_blk); - - blk_link_next(blk); - blk_insert(blk); - } - - return remaining_blk; -} - -__STATIC__ mmheap_blk_t *blk_search_suitable(int *fli, int *sli) -{ - int fl, sl; - uint32_t sl_map, fl_map; - - fl = *fli; - sl = *sli; - - /* - ** First, search for a block in the list associated with the given - ** fl/sl index. - */ - sl_map = k_mmheap_ctl.sl_bitmap[fl] & (~0U << sl); - if (!sl_map) { - /* No block exists. Search in the next largest first-level list. */ - fl_map = k_mmheap_ctl.fl_bitmap & (~0U << (fl + 1)); - if (!fl_map) { - /* No free blocks available, memory has been exhausted. */ - return 0; - } - - fl = __ffs(fl_map); - *fli = fl; - sl_map = k_mmheap_ctl.sl_bitmap[fl]; - } - sl = __ffs(sl_map); - *sli = sl; - - /* Return the first block in the free list. */ - return k_mmheap_ctl.blocks[fl][sl]; -} - -__STATIC__ mmheap_blk_t *blk_locate_free(size_t size) -{ - int fl = 0, sl = 0; - mmheap_blk_t *blk = K_NULL; - - if (!size) { - return K_NULL; - } - - mapping_search(size, &fl, &sl); - - /* - ** mapping_search can futz with the size, so for excessively large sizes it can sometimes wind up - ** with indices that are off the end of the block array. - ** So, we protect against that here, since this is the only callsite of mapping_search. - ** Note that we don't need to check sl, since it comes from a modulo operation that guarantees it's always in range. - */ - if (fl < K_MMHEAP_FL_INDEX_COUNT) { - blk = blk_search_suitable(&fl, &sl); - } - - if (blk) { - remove_free_block(blk, fl, sl); - } - - return blk; -} - -/* -** Adjust an allocation size to be aligned to word size, and no smaller -** than internal minimum. -*/ -__STATIC__ size_t adjust_request_size(size_t size, size_t align) -{ - size_t adjust_size = 0; - - if (!size) { - return 0; - } - - adjust_size = align_up(size, align); - if (adjust_size > K_MMHEAP_BLK_SIZE_MAX) { - return 0; - } - - /* aligned sized must not exceed block_size_max or we'll go out of bounds on sl_bitmap */ - return adjust_size > K_MMHEAP_BLK_SIZE_MIN ? adjust_size : K_MMHEAP_BLK_SIZE_MIN; -} - -__STATIC__ void *blk_prepare_used(mmheap_blk_t *blk, size_t size) -{ - if (!blk) { - return K_NULL; - } - blk_trim_free(blk, size); - blk_mark_as_used(blk); - return blk_to_ptr(blk); -} - -__STATIC__ void mmheap_ctl_init(void) -{ - int i, j; - - k_mmheap_ctl.block_null.next_free = &k_mmheap_ctl.block_null; - k_mmheap_ctl.block_null.prev_free = &k_mmheap_ctl.block_null; - - k_mmheap_ctl.fl_bitmap = 0; - for (i = 0; i < K_MMHEAP_FL_INDEX_COUNT; ++i) { - k_mmheap_ctl.sl_bitmap[i] = 0; - for (j = 0; j < K_MMHEAP_SL_INDEX_COUNT; ++j) { - k_mmheap_ctl.blocks[i][j] = &k_mmheap_ctl.block_null; - } - } -} - -__KERNEL__ k_err_t mmheap_init(void *pool_start, size_t pool_size) -{ - mmheap_ctl_init(); - - return tos_mmheap_pool_add(pool_start, pool_size); -} - -__API__ void *tos_mmheap_alloc(size_t size) -{ - size_t adjust_size; - mmheap_blk_t *blk; - - adjust_size = adjust_request_size(size, K_MMHEAP_ALIGN_SIZE); - blk = blk_locate_free(adjust_size); - if (!blk) { - return K_NULL; - } - - return blk_prepare_used(blk, adjust_size); -} - -__API__ void *tos_mmheap_calloc(size_t num, size_t size) -{ - void *ptr; - - ptr = tos_mmheap_alloc(num * size); - if (ptr) { - memset(ptr, 0, num * size); - } - - return ptr; -} - -__API__ void *tos_mmheap_aligned_alloc(size_t size, size_t align) -{ - mmheap_blk_t *blk; - void *ptr, *aligned, *next_aligned; - size_t adjust_size, aligned_size; - size_t gap_minimum, size_with_gap, gap, gap_remain, offset; - - adjust_size = adjust_request_size(size, K_MMHEAP_ALIGN_SIZE); - gap_minimum = sizeof(mmheap_blk_t); - size_with_gap = adjust_request_size(adjust_size + align + gap_minimum, align); - aligned_size = (adjust_size && align > K_MMHEAP_ALIGN_SIZE) ? size_with_gap : adjust_size; - - blk = blk_locate_free(aligned_size); - if (!blk) { - return K_NULL; - } - - ptr = blk_to_ptr(blk); - aligned = align_ptr(ptr, align); - gap = (size_t)((cpu_addr_t)aligned - (cpu_addr_t)ptr); - - if (gap && gap < gap_minimum) { - gap_remain = gap_minimum - gap; - offset = gap_remain > align ? gap_remain : align; - next_aligned = (void *)((cpu_data_t)aligned + offset); - - aligned = align_ptr(next_aligned, align); - gap = (size_t)((cpu_addr_t)aligned - (cpu_addr_t)ptr); - } - - if (gap) { - blk = blk_trim_free_leading(blk, gap); - } - - return blk_prepare_used(blk, adjust_size); -} - -__API__ void tos_mmheap_free(void *ptr) -{ - mmheap_blk_t *blk; - - if (!ptr) { - return; - } - - blk = blk_from_ptr(ptr); - blk_mark_as_free(blk); - blk = blk_merge_prev(blk); - blk = blk_merge_next(blk); - blk_insert(blk); -} - -__API__ void *tos_mmheap_realloc(void *ptr, size_t size) -{ - void *p = 0; - mmheap_blk_t *curr_blk, *next_blk; - size_t curr_size, combined_size, adjust_size, min_size; - - if (ptr && size == 0) { - tos_mmheap_free(ptr); - return K_NULL; - } - - if (!ptr) { - return tos_mmheap_alloc(size); - } - - curr_blk = blk_from_ptr(ptr); - next_blk = blk_next(curr_blk); - - curr_size = blk_size(curr_blk); - combined_size = curr_size + blk_size(next_blk) + K_MMHEAP_BLK_HEADER_OVERHEAD; - adjust_size = adjust_request_size(size, K_MMHEAP_ALIGN_SIZE); - - if (adjust_size > curr_size && (!blk_is_free(next_blk) || adjust_size > combined_size)) { - p = tos_mmheap_alloc(size); - if (p) { - min_size = curr_size < size ? curr_size : size; - memcpy(p, ptr, min_size); - tos_mmheap_free(ptr); - } - } else { - if (adjust_size > curr_size) { - blk_merge_next(curr_blk); - blk_mark_as_used(curr_blk); - } - - blk_trim_used(curr_blk, adjust_size); - p = ptr; - } - - return p; -} - -__API__ k_err_t tos_mmheap_pool_add(void *pool_start, size_t pool_size) -{ - mmheap_blk_t *curr_blk; - mmheap_blk_t *next_blk; - size_t size_aligned; - - size_aligned = align_down(pool_size - 2 * K_MMHEAP_BLK_HEADER_OVERHEAD, K_MMHEAP_ALIGN_SIZE); - - if (((cpu_addr_t)pool_start % K_MMHEAP_ALIGN_SIZE) != 0u) { - return K_ERR_MMHEAP_INVALID_POOL_ADDR; - } - - if (size_aligned < K_MMHEAP_BLK_SIZE_MIN || - size_aligned > K_MMHEAP_BLK_SIZE_MAX) { - return K_ERR_MMHEAP_INVALID_POOL_SIZE; - } - - /* - ** Create the main free block. Offset the start of the block slightly - ** so that the prev_phys_block field falls outside of the pool - - ** it will never be used. - */ - curr_blk = offset_to_block(pool_start, -K_MMHEAP_BLK_HEADER_OVERHEAD); - blk_set_size(curr_blk, size_aligned); - blk_set_free(curr_blk); - blk_set_prev_used(curr_blk); - blk_insert(curr_blk); - - /* Split the block to create a zero-size sentinel block. */ - next_blk = blk_link_next(curr_blk); - blk_set_size(next_blk, 0); - blk_set_used(next_blk); - blk_set_prev_free(next_blk); - return K_ERR_NONE; -} - -__API__ void tos_mmheap_pool_rmv(void *pool_start) -{ - int fl = 0, sl = 0; - mmheap_blk_t *blk; - - blk = offset_to_block(pool_start, -K_MMHEAP_BLK_HEADER_OVERHEAD); - mapping_insert(blk_size(blk), &fl, &sl); - remove_free_block(blk, fl, sl); -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_msg.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_msg.c deleted file mode 100644 index c0dfbc35..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_msg.c +++ /dev/null @@ -1,142 +0,0 @@ -#include - -#if TOS_CFG_MSG_EN > 0u - -__KERNEL__ void msgpool_init(void) -{ - uint32_t i; - - for (i = 0; i < TOS_CFG_MSG_POOL_SIZE; ++i) { - tos_list_init(&k_msg_pool[i].list); - tos_list_add(&k_msg_pool[i].list, &k_msg_freelist); - } -} - -__STATIC__ k_msg_t *msgpool_alloc(void) -{ - k_msg_t *msg = K_NULL; - - if (tos_list_empty(&k_msg_freelist)) { - return K_NULL; - } - - msg = TOS_LIST_FIRST_ENTRY(&k_msg_freelist, k_msg_t, list); - tos_list_del(&msg->list); - return msg; -} - -__STATIC__ void msgpool_free(k_msg_t *msg) -{ - tos_list_del(&msg->list); - tos_list_add(&msg->list, &k_msg_freelist); -} - -__API__ void tos_msg_queue_flush(k_msg_queue_t *msg_queue) -{ - TOS_CPU_CPSR_ALLOC(); - k_list_t *curr, *next; - - TOS_CPU_INT_DISABLE(); - - TOS_LIST_FOR_EACH_SAFE(curr, next, &msg_queue->queue_head) { - msgpool_free(TOS_LIST_ENTRY(curr, k_msg_t, list)); - } - - TOS_CPU_INT_ENABLE(); -} - -__API__ k_err_t tos_msg_queue_create(k_msg_queue_t *msg_queue) -{ - TOS_PTR_SANITY_CHECK(msg_queue); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_init(&msg_queue->knl_obj, KNL_OBJ_TYPE_MSG_QUEUE); -#endif - - tos_list_init(&msg_queue->queue_head); - return K_ERR_NONE; -} - -__API__ k_err_t tos_msg_queue_destroy(k_msg_queue_t *msg_queue) -{ - TOS_PTR_SANITY_CHECK(msg_queue); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&msg_queue->knl_obj, KNL_OBJ_TYPE_MSG_QUEUE)) { - return K_ERR_OBJ_INVALID; - } -#endif - - tos_msg_queue_flush(msg_queue); - tos_list_init(&msg_queue->queue_head); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_deinit(&msg_queue->knl_obj); -#endif - - return K_ERR_NONE; -} - -__API__ k_err_t tos_msg_queue_get(k_msg_queue_t *msg_queue, void **msg_addr, size_t *msg_size) -{ - TOS_CPU_CPSR_ALLOC(); - k_msg_t *msg; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&msg_queue->knl_obj, KNL_OBJ_TYPE_MSG_QUEUE)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - msg = TOS_LIST_FIRST_ENTRY_OR_NULL(&msg_queue->queue_head, k_msg_t, list); - if (!msg) { - TOS_CPU_INT_ENABLE(); - return K_ERR_MSG_QUEUE_EMPTY; - } - - *msg_addr = msg->msg_addr; - *msg_size = msg->msg_size; - msgpool_free(msg); - - TOS_CPU_INT_ENABLE(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_msg_queue_put(k_msg_queue_t *msg_queue, void *msg_addr, size_t msg_size, k_opt_t opt) -{ - TOS_CPU_CPSR_ALLOC(); - k_msg_t *msg; - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&msg_queue->knl_obj, KNL_OBJ_TYPE_MSG_QUEUE)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - msg = msgpool_alloc(); - if (!msg) { - TOS_CPU_INT_ENABLE(); - return K_ERR_MSG_QUEUE_FULL; - } - - msg->msg_addr = msg_addr; - msg->msg_size = msg_size; - - if (opt & TOS_OPT_MSG_PUT_LIFO) { - tos_list_add(&msg->list, &msg_queue->queue_head); - } else { - tos_list_add_tail(&msg->list, &msg_queue->queue_head); - } - - TOS_CPU_INT_ENABLE(); - - return K_ERR_NONE; -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_mutex.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_mutex.c deleted file mode 100644 index 267879cd..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_mutex.c +++ /dev/null @@ -1,205 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_MUTEX_EN > 0u - -__STATIC_INLINE__ void mutex_old_owner_release(k_mutex_t *mutex) -{ - k_task_t *owner; - - owner = mutex->owner; - - tos_list_del(&mutex->owner_list); - mutex->owner = K_NULL; - - // the right time comes! let's do it! - if (owner->prio_pending != K_TASK_PRIO_INVALID) { - tos_task_prio_change(owner, owner->prio_pending); - owner->prio_pending = K_TASK_PRIO_INVALID; - } else if (owner->prio != mutex->owner_orig_prio) { - tos_task_prio_change(owner, mutex->owner_orig_prio); - mutex->owner_orig_prio = K_TASK_PRIO_INVALID; - } -} - -__STATIC_INLINE__ void mutex_fresh_owner_mark(k_mutex_t *mutex, k_task_t *task) -{ - mutex->pend_nesting = (k_nesting_t)1u; - mutex->owner = task; - mutex->owner_orig_prio = task->prio; - - tos_list_add(&mutex->owner_list, &task->mutex_own_list); -} - -__STATIC_INLINE__ void mutex_new_owner_mark(k_mutex_t *mutex, k_task_t *task) -{ - k_prio_t highest_pending_prio; - - mutex_fresh_owner_mark(mutex, task); - - // we own the mutex now, make sure our priority is higher than any one in the pend list. - highest_pending_prio = pend_highest_prio_get(&mutex->pend_obj); - if (task->prio > highest_pending_prio) { - tos_task_prio_change(task, highest_pending_prio); - } -} - -__KERNEL__ void mutex_release(k_mutex_t *mutex) -{ - mutex_old_owner_release(mutex); - pend_wakeup_all(&mutex->pend_obj, PEND_STATE_OWNER_DIE); -} - -__API__ k_err_t tos_mutex_create(k_mutex_t *mutex) -{ - TOS_PTR_SANITY_CHECK(mutex); - - pend_object_init(&mutex->pend_obj, PEND_TYPE_MUTEX); - mutex->pend_nesting = (k_nesting_t)0u; - mutex->owner = K_NULL; - mutex->owner_orig_prio = K_TASK_PRIO_INVALID; - tos_list_init(&mutex->owner_list); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_mutex_destroy(k_mutex_t *mutex) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(mutex); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&mutex->pend_obj, PEND_TYPE_MUTEX)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (!pend_is_nopending(&mutex->pend_obj)) { - pend_wakeup_all(&mutex->pend_obj, PEND_STATE_DESTROY); - } - - pend_object_deinit(&mutex->pend_obj); - mutex->pend_nesting = (k_nesting_t)0u; - - if (mutex->owner) { - mutex_old_owner_release(mutex); - } - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_mutex_pend_timed(k_mutex_t *mutex, k_tick_t timeout) -{ - TOS_CPU_CPSR_ALLOC(); - k_err_t err; - - TOS_PTR_SANITY_CHECK(mutex); - TOS_IN_IRQ_CHECK(); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&mutex->pend_obj, PEND_TYPE_MUTEX)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - if (mutex->pend_nesting == (k_nesting_t)0u) { // first come - mutex_fresh_owner_mark(mutex, k_curr_task); - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; - } - - if (knl_is_self(mutex->owner)) { // come again - if (mutex->pend_nesting == (k_nesting_t)-1) { - TOS_CPU_INT_ENABLE(); - return K_ERR_MUTEX_NESTING_OVERFLOW; - } - ++mutex->pend_nesting; - TOS_CPU_INT_ENABLE(); - return K_ERR_MUTEX_NESTING; - } - - if (timeout == TOS_TIME_NOWAIT) { // no wait, return immediately - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_NOWAIT; - } - - if (knl_is_sched_locked()) { - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_SCHED_LOCKED; - } - - if (mutex->owner->prio > k_curr_task->prio) { - // PRIORITY INVERSION: - // we are declaring a mutex, which's owner has a lower(numerically bigger) priority. - // make owner the same priority with us. - tos_task_prio_change(mutex->owner, k_curr_task->prio); - } - - pend_task_block(k_curr_task, &mutex->pend_obj, timeout); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - err = pend_state2errno(k_curr_task->pend_state); - - if (err == K_ERR_NONE) { - // good, we are the owner now. - TOS_CPU_INT_DISABLE(); - mutex_new_owner_mark(mutex, k_curr_task); - TOS_CPU_INT_ENABLE(); - } - - return err; -} - -__API__ k_err_t tos_mutex_pend(k_mutex_t *mutex) -{ - return tos_mutex_pend_timed(mutex, TOS_TIME_FOREVER); -} - -__API__ k_err_t tos_mutex_post(k_mutex_t *mutex) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(mutex); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&mutex->pend_obj, PEND_TYPE_MUTEX)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - if (!knl_is_self(mutex->owner)) { - TOS_CPU_INT_ENABLE(); - return K_ERR_MUTEX_NOT_OWNER; - } - - --mutex->pend_nesting; - if (mutex->pend_nesting > (k_nesting_t)0u) { - TOS_CPU_INT_ENABLE(); - return K_ERR_MUTEX_NESTING; - } - - mutex_old_owner_release(mutex); - - if (pend_is_nopending(&mutex->pend_obj)) { - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; - } - - pend_wakeup_one(&mutex->pend_obj, PEND_STATE_POST); - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_pend.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_pend.c deleted file mode 100644 index 6d51108b..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_pend.c +++ /dev/null @@ -1,138 +0,0 @@ -#include "tos.h" - -__STATIC__ void pend_list_add(k_task_t *task, pend_obj_t *pend_obj) -{ - k_list_t *curr, *pend_list; - k_task_t *iter; - - pend_list = &pend_obj->list; - /* keep priority in descending order, the boss(task with highest priority, - numerically smallest) always comes first - */ - TOS_LIST_FOR_EACH(curr, pend_list) { - iter = TOS_LIST_ENTRY(curr, k_task_t, pend_list); - if (task->prio < iter->prio) { - break; - } - } - tos_list_add_tail(&task->pend_list, curr); - - // remember me, you may use me someday - task->pending_obj = pend_obj; - task_state_set_pend(task); -} - -__KERNEL__ k_prio_t pend_highest_prio_get(pend_obj_t *object) -{ - k_task_t *task; - - // we keep the task priority in descending order, so the first one is just fine. - task = TOS_LIST_FIRST_ENTRY_OR_NULL(&object->list, k_task_t, pend_list); - return task ? task->prio : K_TASK_PRIO_INVALID; -} - -__KERNEL__ void pend_list_remove(k_task_t *task) -{ - tos_list_del(&task->pend_list); - - task->pending_obj = (pend_obj_t *)K_NULL; - task_state_reset_pending(task); -} - -__KERNEL__ void pend_object_init(pend_obj_t *object, pend_type_t type) -{ - object->type = type; - tos_list_init(&object->list); -} - -__KERNEL__ void pend_object_deinit(pend_obj_t *object) -{ - object->type = PEND_TYPE_NONE; - tos_list_init(&object->list); -} - -__KERNEL__ int pend_is_nopending(pend_obj_t *object) -{ - return tos_list_empty(&object->list); -} - -__KERNEL__ void pend_list_adjust(k_task_t *task) -{ - // we may be the boss, so re-enter the pend list - tos_list_del(&task->pend_list); - // the "someday" comes - pend_list_add(task, task->pending_obj); -} - -__KERNEL__ int pend_object_verify(pend_obj_t *object, pend_type_t type) -{ - return object->type == type; -} - -__KERNEL__ k_err_t pend_state2errno(pend_state_t state) -{ - if (state == PEND_STATE_POST) { - return K_ERR_NONE; - } else if (state == PEND_STATE_TIMEOUT) { - return K_ERR_PEND_TIMEOUT; - } else if (state == PEND_STATE_DESTROY) { - return K_ERR_PEND_DESTROY; - } else if (state == PEND_STATE_OWNER_DIE) { - return K_ERR_PEND_OWNER_DIE; - } else { - return K_ERR_PEND_ABNORMAL; - } -} - -__KERNEL__ void pend_task_wakeup(k_task_t *task, pend_state_t state) -{ - if (task_state_is_pending(task)) { - // mark why we wakeup - task->pend_state = state; - pend_list_remove(task); - } - - if (task_state_is_sleeping(task)) { - tick_list_remove(task); - } - - if (task_state_is_suspended(task)) { - return; - } - - readyqueue_add(task); -} - -__KERNEL__ void pend_task_block(k_task_t *task, pend_obj_t *object, k_tick_t timeout) -{ - readyqueue_remove(task); - pend_list_add(task, object); - - if (timeout != TOS_TIME_FOREVER) { - tick_list_add(task, timeout); - } -} - -__KERNEL__ void pend_wakeup_one(pend_obj_t *object, pend_state_t state) -{ - pend_task_wakeup(TOS_LIST_FIRST_ENTRY(&object->list, k_task_t, pend_list), state); -} - -__KERNEL__ void pend_wakeup_all(pend_obj_t *object, pend_state_t state) -{ - k_list_t *curr, *next; - - TOS_LIST_FOR_EACH_SAFE(curr, next, &object->list) { - pend_task_wakeup(TOS_LIST_ENTRY(curr, k_task_t, pend_list), state); - } -} - -__KERNEL__ void pend_wakeup(pend_obj_t *object, pend_state_t state, opt_post_t opt) -{ - if (opt == OPT_POST_ONE) { - pend_wakeup_one(object, state); - } else { - pend_wakeup_all(object, state); - } -} - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_queue.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_queue.c deleted file mode 100644 index fbed18a0..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_queue.c +++ /dev/null @@ -1,170 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_QUEUE_EN > 0u - -__API__ k_err_t tos_queue_create(k_queue_t *queue) -{ - TOS_PTR_SANITY_CHECK(queue); - - pend_object_init(&queue->pend_obj, PEND_TYPE_QUEUE); - tos_msg_queue_create(&queue->msg_queue); - return K_ERR_NONE; -} - -__API__ k_err_t tos_queue_destroy(k_queue_t *queue) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(queue); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&queue->pend_obj, PEND_TYPE_QUEUE)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (!pend_is_nopending(&queue->pend_obj)) { - pend_wakeup_all(&queue->pend_obj, PEND_STATE_DESTROY); - } - - pend_object_deinit(&queue->pend_obj); - tos_msg_queue_flush(&queue->msg_queue); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_queue_flush(k_queue_t *queue) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(queue); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&queue->pend_obj, PEND_TYPE_QUEUE)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - tos_msg_queue_flush(&queue->msg_queue); - TOS_CPU_INT_ENABLE(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_queue_pend(k_queue_t *queue, void **msg_addr, size_t *msg_size, k_tick_t timeout) -{ - TOS_CPU_CPSR_ALLOC(); - k_err_t err; - - TOS_PTR_SANITY_CHECK(queue); - TOS_PTR_SANITY_CHECK(msg_addr); - TOS_PTR_SANITY_CHECK(msg_size); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&queue->pend_obj, PEND_TYPE_QUEUE)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (tos_msg_queue_get(&queue->msg_queue, msg_addr, msg_size) == K_ERR_NONE) { - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; - } - - if (timeout == TOS_TIME_NOWAIT) { - *msg_addr = K_NULL; - *msg_size = 0; - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_NOWAIT; - } - - if (knl_is_sched_locked()) { - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_SCHED_LOCKED; - } - - pend_task_block(k_curr_task, &queue->pend_obj, timeout); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - err = pend_state2errno(k_curr_task->pend_state); - - if (err == K_ERR_NONE) { - *msg_addr = k_curr_task->msg_addr; - *msg_size = k_curr_task->msg_size; - k_curr_task->msg_addr = K_NULL; - k_curr_task->msg_size = 0; - } - - return err; -} - -__STATIC__ void queue_task_msg_recv(k_task_t *task, void *msg_addr, size_t msg_size) -{ - task->msg_addr = msg_addr; - task->msg_size = msg_size; - pend_task_wakeup(task, PEND_STATE_POST); -} - -__STATIC__ k_err_t queue_do_post(k_queue_t *queue, void *msg_addr, size_t msg_size, opt_post_t opt) -{ - TOS_CPU_CPSR_ALLOC(); - k_list_t *curr, *next; - - TOS_PTR_SANITY_CHECK(queue); - TOS_PTR_SANITY_CHECK(msg_addr); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&queue->pend_obj, PEND_TYPE_QUEUE)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (pend_is_nopending(&queue->pend_obj)) { - if (tos_msg_queue_put(&queue->msg_queue, msg_addr, msg_size, TOS_OPT_MSG_PUT_FIFO) != K_ERR_NONE) { - TOS_CPU_INT_ENABLE(); - return K_ERR_QUEUE_FULL; - } - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; - } - - if (opt == OPT_POST_ONE) { - queue_task_msg_recv(TOS_LIST_FIRST_ENTRY(&queue->pend_obj.list, k_task_t, pend_list), - msg_addr, msg_size); - } else { // OPT_QUEUE_POST_ALL - TOS_LIST_FOR_EACH_SAFE(curr, next, &queue->pend_obj.list) { - queue_task_msg_recv(TOS_LIST_ENTRY(curr, k_task_t, pend_list), - msg_addr, msg_size); - } - } - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_queue_post(k_queue_t *queue, void *msg_addr, size_t msg_size) -{ - return queue_do_post(queue, msg_addr, msg_size, OPT_POST_ONE); -} - -__API__ k_err_t tos_queue_post_all(k_queue_t *queue, void *msg_addr, size_t msg_size) -{ - return queue_do_post(queue, msg_addr, msg_size, OPT_POST_ALL); -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_robin.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_robin.c deleted file mode 100644 index 0e0d39f5..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_robin.c +++ /dev/null @@ -1,92 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_ROUND_ROBIN_EN > 0u - -__API__ void tos_robin_config(k_robin_state_t robin_state, k_timeslice_t default_timeslice) -{ - TOS_CPU_CPSR_ALLOC(); - TOS_CPU_INT_DISABLE(); - - k_robin_state = robin_state; - - if (default_timeslice > (k_timeslice_t)0u) { - k_robin_default_timeslice = default_timeslice; - } else { - k_robin_default_timeslice = TOS_CFG_CPU_TICK_PER_SECOND / 10; - } - TOS_CPU_INT_ENABLE(); -} - -__API__ void tos_robin_timeslice_set(k_task_t *task, k_timeslice_t timeslice) -{ - TOS_CPU_CPSR_ALLOC(); - - if (!task) { - task = k_curr_task; - } - - TOS_CPU_INT_DISABLE(); - - if (timeslice == (k_timeslice_t)0u) { - task->timeslice_reload = k_robin_default_timeslice; - } else { - task->timeslice_reload = timeslice; - } - - if (task->timeslice_reload > task->timeslice) { - task->timeslice = task->timeslice_reload; - } - TOS_CPU_INT_ENABLE(); -} - -__KERNEL__ void robin_sched(k_prio_t prio) -{ - TOS_CPU_CPSR_ALLOC(); - k_task_t *task; - - if (k_robin_state != TOS_ROBIN_STATE_ENABLED) { - return; - } - - TOS_CPU_INT_DISABLE(); - - task = readyqueue_first_task_get(prio); - if (!task || knl_is_idle(task)) { - TOS_CPU_INT_ENABLE(); - return; - } - - if (readyqueue_is_prio_onlyone(prio)) { - TOS_CPU_INT_ENABLE(); - return; - } - - if (knl_is_sched_locked()) { - TOS_CPU_INT_ENABLE(); - return; - } - - if (task->timeslice > (k_timeslice_t)0u) { - --task->timeslice; - } - - if (task->timeslice > (k_timeslice_t)0u) { - TOS_CPU_INT_ENABLE(); - return; - } - - readyqueue_move_head_to_tail(k_curr_task->prio); - - task = readyqueue_first_task_get(prio); - if (task->timeslice_reload == (k_timeslice_t)0u) { - task->timeslice = k_robin_default_timeslice; - } else { - task->timeslice = task->timeslice_reload; - } - - TOS_CPU_INT_ENABLE(); - knl_sched(); -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_sched.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_sched.c deleted file mode 100644 index 9ab93b2b..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_sched.c +++ /dev/null @@ -1,171 +0,0 @@ -#include - -__STATIC__ k_prio_t readyqueue_prio_highest_get(void) -{ - uint32_t *tbl; - k_prio_t prio; - - prio = 0; - tbl = &k_rdyq.prio_mask[0]; - - while (*tbl == 0) { - prio += K_PRIO_TBL_SLOT_SIZE; - ++tbl; - } - prio += tos_cpu_clz(*tbl); - return prio; -} - -__STATIC_INLINE__ void readyqueue_prio_insert(k_prio_t prio) -{ - k_rdyq.prio_mask[K_PRIO_NDX(prio)] |= K_PRIO_BIT(prio); -} - -__STATIC_INLINE__ void readyqueue_prio_remove(k_prio_t prio) -{ - k_rdyq.prio_mask[K_PRIO_NDX(prio)] &= ~K_PRIO_BIT(prio); -} - -__STATIC_INLINE__ void readyqueue_prio_mark(k_prio_t prio) -{ - readyqueue_prio_insert(prio); - - if (prio < k_rdyq.highest_prio) { - k_rdyq.highest_prio = prio; - } -} - -/** - * when this function involved, must be at least one task in the task list of the certain priority - */ -__KERNEL__ int readyqueue_is_prio_onlyone(k_prio_t prio) -{ - k_list_t *task_list; - k_task_t *task; - - task_list = &k_rdyq.task_list_head[prio]; - task = TOS_LIST_FIRST_ENTRY(task_list, k_task_t, pend_list); - return task->pend_list.next == task_list; -} - -__KERNEL__ k_task_t *readyqueue_first_task_get(k_prio_t prio) -{ - k_list_t *task_list; - - task_list = &k_rdyq.task_list_head[prio]; - return TOS_LIST_FIRST_ENTRY_OR_NULL(task_list, k_task_t, pend_list); -} - -__KERNEL__ k_task_t *readyqueue_highest_ready_task_get(void) -{ - k_list_t *task_list; - - task_list = &k_rdyq.task_list_head[k_rdyq.highest_prio]; - return TOS_LIST_FIRST_ENTRY(task_list, k_task_t, pend_list); -} - -__KERNEL__ void readyqueue_init(void) -{ - uint8_t i; - - k_rdyq.highest_prio = TOS_CFG_TASK_PRIO_MAX; - - for (i = 0; i < TOS_CFG_TASK_PRIO_MAX; ++i) { - tos_list_init(&k_rdyq.task_list_head[i]); - } - - for (i = 0; i < K_PRIO_TBL_SIZE; ++i) { - k_rdyq.prio_mask[i] = 0; - } -} - -__DEBUG__ void readyqueue_walkthru(void) -{ - uint8_t i; - k_task_t *task; - k_list_t *task_list, *curr; - - tos_kprintf("==========================\n"); - tos_kprintf("%d\n", k_rdyq.highest_prio); - - for (i = 0; i < TOS_CFG_TASK_PRIO_MAX; ++i) { - task_list = &k_rdyq.task_list_head[i]; - if (!tos_list_empty(task_list)) { - TOS_LIST_FOR_EACH(curr, task_list) { - task = TOS_LIST_ENTRY(curr, k_task_t, pend_list); - tos_kprintf("---- %d %d [%d] %s\n", task->prio, i, task->state, task->name); - } - } - } - tos_kprintf("\n\n"); -} - -__KERNEL__ void readyqueue_add_head(k_task_t *task) -{ - k_prio_t task_prio; - k_list_t *task_list; - - task_prio = task->prio; - task_list = &k_rdyq.task_list_head[task_prio]; - - if (tos_list_empty(task_list)) { - readyqueue_prio_mark(task_prio); - } - - tos_list_add(&task->pend_list, task_list); -} - -__KERNEL__ void readyqueue_add_tail(k_task_t *task) -{ - k_prio_t task_prio; - k_list_t *task_list; - - task_prio = task->prio; - task_list = &k_rdyq.task_list_head[task_prio]; - - if (tos_list_empty(task_list)) { - readyqueue_prio_mark(task_prio); - } - - tos_list_add_tail(&task->pend_list, task_list); -} - -__KERNEL__ void readyqueue_add(k_task_t *task) -{ - if (task->prio == k_curr_task->prio) { - readyqueue_add_tail(task); - } else { - readyqueue_add_head(task); - } -} - -__KERNEL__ void readyqueue_remove(k_task_t *task) -{ - k_prio_t task_prio; - k_list_t *task_list; - - task_prio = task->prio; - task_list = &k_rdyq.task_list_head[task_prio]; - - tos_list_del(&task->pend_list); - - if (tos_list_empty(task_list)) { - readyqueue_prio_remove(task_prio); - } - - if (task_prio == k_rdyq.highest_prio) { - k_rdyq.highest_prio = readyqueue_prio_highest_get(); - } -} - -__KERNEL__ void readyqueue_move_head_to_tail(k_prio_t prio) -{ - k_list_t *task_list; - - task_list = &k_rdyq.task_list_head[prio]; - - if (!tos_list_empty(task_list)) { - tos_list_move_tail(task_list->next, task_list); - } -} - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_sem.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_sem.c deleted file mode 100644 index a9c2ae3c..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_sem.c +++ /dev/null @@ -1,124 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_SEM_EN > 0u - -__API__ k_err_t tos_sem_create(k_sem_t *sem, k_sem_cnt_t init_count) -{ - TOS_PTR_SANITY_CHECK(sem); - - pend_object_init(&sem->pend_obj, PEND_TYPE_SEM); - sem->count = init_count; - - return K_ERR_NONE; -} - -__API__ k_err_t tos_sem_destroy(k_sem_t *sem) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(sem); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&sem->pend_obj, PEND_TYPE_SEM)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (!pend_is_nopending(&sem->pend_obj)) { - pend_wakeup_all(&sem->pend_obj, PEND_STATE_DESTROY); - } - - pend_object_deinit(&sem->pend_obj); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__STATIC__ k_err_t sem_do_post(k_sem_t *sem, opt_post_t opt) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(sem); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&sem->pend_obj, PEND_TYPE_SEM)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (sem->count == (k_sem_cnt_t)-1) { - TOS_CPU_INT_ENABLE(); - return K_ERR_SEM_OVERFLOW; - } - - if (pend_is_nopending(&sem->pend_obj)) { - ++sem->count; - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; - } - - pend_wakeup(&sem->pend_obj, PEND_STATE_POST, opt); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_sem_post(k_sem_t *sem) -{ - return sem_do_post(sem, OPT_POST_ONE); -} - -__API__ k_err_t tos_sem_post_all(k_sem_t *sem) -{ - return sem_do_post(sem, OPT_POST_ALL); -} - -__API__ k_err_t tos_sem_pend(k_sem_t *sem, k_tick_t timeout) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(sem); - TOS_IN_IRQ_CHECK(); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!pend_object_verify(&sem->pend_obj, PEND_TYPE_SEM)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (sem->count > (k_sem_cnt_t)0u) { - --sem->count; - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; - } - - if (timeout == TOS_TIME_NOWAIT) { // no wait, return immediately - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_NOWAIT; - } - - if (knl_is_sched_locked()) { - TOS_CPU_INT_ENABLE(); - return K_ERR_PEND_SCHED_LOCKED; - } - - pend_task_block(k_curr_task, &sem->pend_obj, timeout); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return pend_state2errno(k_curr_task->pend_state); -} - -#endif // TOS_CFG_SEM_EN - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_sys.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_sys.c deleted file mode 100644 index c09fd365..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_sys.c +++ /dev/null @@ -1,262 +0,0 @@ -#include - -__API__ k_err_t tos_knl_init(void) -{ - k_err_t err; - - cpu_init(); - - readyqueue_init(); - -#if TOS_CFG_MMHEAP_EN > 0 - mmheap_init(k_mmheap_pool, TOS_CFG_MMHEAP_POOL_SIZE); -#endif - -#if (TOS_CFG_MSG_EN) > 0 - msgpool_init(); -#endif - - err = knl_idle_init(); - if (err != K_ERR_NONE) { - return err; - } - -#if TOS_CFG_TIMER_EN > 0 - err = timer_init(); - if (err != K_ERR_NONE) { - return err; - } -#endif - -#if TOS_CFG_PWR_MGR_EN > 0U - pm_init(); -#endif - -#if TOS_CFG_TICKLESS_EN > 0u - tickless_init(); -#endif - - return K_ERR_NONE; -} - -__API__ void tos_knl_irq_enter(void) -{ - if (!tos_knl_is_running()) { - return; - } - - if (unlikely(k_irq_nest_cnt >= K_NESTING_LIMIT_IRQ)) { - return; - } - - ++k_irq_nest_cnt; -} - -__API__ void tos_knl_irq_leave(void) -{ - TOS_CPU_CPSR_ALLOC(); - - if (!tos_knl_is_running()) { - return; - } - - TOS_CPU_INT_DISABLE(); - if (!knl_is_inirq()) { - TOS_CPU_INT_ENABLE(); - return; - } - - --k_irq_nest_cnt; - - if (knl_is_inirq()) { - TOS_CPU_INT_ENABLE(); - return; - } - - if (knl_is_sched_locked()) { - TOS_CPU_INT_ENABLE(); - return; - } - - k_next_task = readyqueue_highest_ready_task_get(); - if (knl_is_self(k_next_task)) { - TOS_CPU_INT_ENABLE(); - return; - } - - cpu_irq_context_switch(); - TOS_CPU_INT_ENABLE(); -} - -__API__ k_err_t tos_knl_sched_lock(void) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_IN_IRQ_CHECK(); - - if (!tos_knl_is_running()) { - return K_ERR_KNL_NOT_RUNNING; - } - - if (k_sched_lock_nest_cnt >= K_NESTING_LIMIT_SCHED_LOCK) { - return K_ERR_LOCK_NESTING_OVERFLOW; - } - - TOS_CPU_INT_DISABLE(); - ++k_sched_lock_nest_cnt; - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; -} - -__API__ k_err_t tos_knl_sched_unlock(void) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_IN_IRQ_CHECK(); - - if (!tos_knl_is_running()) { - return K_ERR_KNL_NOT_RUNNING; - } - - if (!knl_is_sched_locked()) { - return K_ERR_SCHED_NOT_LOCKED; - } - - TOS_CPU_INT_DISABLE(); - --k_sched_lock_nest_cnt; - TOS_CPU_INT_ENABLE(); - - knl_sched(); - return K_ERR_NONE; -} - -__API__ k_err_t tos_knl_start(void) -{ - if (tos_knl_is_running()) { - return K_ERR_KNL_RUNNING; - } - - k_next_task = readyqueue_highest_ready_task_get(); - k_curr_task = k_next_task; - k_knl_state = KNL_STATE_RUNNING; - cpu_sched_start(); - - return K_ERR_NONE; -} - -__API__ int tos_knl_is_running(void) -{ - return k_knl_state == KNL_STATE_RUNNING; -} - -#if TOS_CFG_TICKLESS_EN > 0u - -/** - * @brief Get the remain ticks of the first oncoming task. - * - * @return The remian ticks of the first oncoming task to be scheduled. - */ -__KERNEL__ k_tick_t knl_next_expires_get(void) -{ - k_tick_t tick_next_expires; -#if TOS_CFG_TIMER_EN > 0u - k_tick_t timer_next_expires; -#endif - - tick_next_expires = tick_next_expires_get(); - -#if TOS_CFG_TIMER_EN > 0u - timer_next_expires = timer_next_expires_get(); -#endif - -#if TOS_CFG_TIMER_EN > 0u - return tick_next_expires < timer_next_expires ? tick_next_expires : timer_next_expires; -#else - return tick_next_expires; -#endif -} - -#endif - - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u -__KERNEL__ int knl_object_verify(knl_obj_t *object, knl_obj_type_t type) -{ - return object->type == type; -} - -__KERNEL__ int knl_object_init(knl_obj_t *object, knl_obj_type_t type) -{ - return object->type = type; -} - -__KERNEL__ int knl_object_deinit(knl_obj_t *object) -{ - return object->type = KNL_OBJ_TYPE_NONE; -} -#endif - -__KERNEL__ void knl_sched(void) -{ - TOS_CPU_CPSR_ALLOC(); - - if (knl_is_inirq()) { - return; - } - - if (knl_is_sched_locked()) { - return; - } - - TOS_CPU_INT_DISABLE(); - k_next_task = readyqueue_highest_ready_task_get(); - if (knl_is_self(k_next_task)) { - TOS_CPU_INT_ENABLE(); - return; - } - - cpu_context_switch(); - TOS_CPU_INT_ENABLE(); -} - -__KERNEL__ int knl_is_sched_locked(void) -{ - return k_sched_lock_nest_cnt > 0u; -} - -__KERNEL__ int knl_is_inirq(void) -{ - return k_irq_nest_cnt > 0u; -} - -__KERNEL__ int knl_is_idle(k_task_t *task) -{ - return task == &k_idle_task; -} - -__KERNEL__ int knl_is_self(k_task_t *task) -{ - return task == k_curr_task; -} - -__STATIC__ void knl_idle_entry(void *arg) -{ - arg = arg; // make compiler happy - - while (K_TRUE) { -#if TOS_CFG_PWR_MGR_EN > 0u - pm_power_manager(); -#endif - } -} - -__KERNEL__ k_err_t knl_idle_init(void) -{ - return tos_task_create(&k_idle_task, "idle", - knl_idle_entry, K_NULL, - K_TASK_PRIO_IDLE, - k_idle_task_stk_addr, - k_idle_task_stk_size, - 0); -} - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_task.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_task.c deleted file mode 100644 index ff3ec11a..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_task.c +++ /dev/null @@ -1,416 +0,0 @@ -#include - -__STATIC_INLINE__ void task_reset(k_task_t *task) -{ -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_deinit(&task->knl_obj); -#endif - - tos_list_init(&task->tick_list); - tos_list_init(&task->pend_list); - -#if TOS_CFG_MUTEX_EN > 0u - tos_list_init(&task->mutex_own_list); - task->prio_pending = K_TASK_PRIO_INVALID; -#endif - - task->pend_state = PEND_STATE_NONE; - task->pending_obj = (pend_obj_t *)K_NULL; - -#if TOS_CFG_MSG_EN > 0u - task->msg_addr = K_NULL; - task->msg_size = 0; -#endif -} - -__STATIC__ void task_exit(void) -{ - tos_task_destroy(K_NULL); -} - -#if TOS_CFG_MUTEX_EN > 0u -__STATIC__ k_prio_t task_highest_pending_prio_get(k_task_t *task) -{ - k_list_t *curr; - k_mutex_t *mutex; - k_prio_t prio, highest_prio_pending = K_TASK_PRIO_INVALID; - - TOS_LIST_FOR_EACH(curr, &task->mutex_own_list) { - mutex = TOS_LIST_ENTRY(curr, k_mutex_t, owner_list); - prio = pend_highest_prio_get(&mutex->pend_obj); - if (prio < highest_prio_pending) { - highest_prio_pending = prio; - } - } - return highest_prio_pending; -} - -__STATIC__ void task_mutex_release(k_task_t *task) -{ - k_list_t *curr, *next; - - TOS_LIST_FOR_EACH_SAFE(curr, next, &task->mutex_own_list) { - mutex_release(TOS_LIST_ENTRY(curr, k_mutex_t, owner_list)); - } -} -#endif - -__API__ k_err_t tos_task_create(k_task_t *task, - char *name, - k_task_entry_t entry, - void *arg, - k_prio_t prio, - k_stack_t *stk_base, - size_t stk_size, - k_timeslice_t timeslice) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_IN_IRQ_CHECK(); - - TOS_PTR_SANITY_CHECK(task); - TOS_PTR_SANITY_CHECK(entry); - TOS_PTR_SANITY_CHECK(stk_base); - - if (unlikely(stk_size < sizeof(cpu_context_t))) { - return K_ERR_TASK_STK_SIZE_INVALID; - } - - if (unlikely(prio == K_TASK_PRIO_IDLE && !knl_is_idle(task))) { - return K_ERR_TASK_PRIO_INVALID; - } - - if (unlikely(prio > K_TASK_PRIO_IDLE)) { - return K_ERR_TASK_PRIO_INVALID; - } - - task_reset(task); -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_init(&task->knl_obj, KNL_OBJ_TYPE_TASK); -#endif - - task->sp = cpu_task_stk_init((void *)entry, arg, (void *)task_exit, stk_base, stk_size); - task->entry = entry; - task->arg = arg; - task->name = name; - task->prio = prio; - task->stk_base = stk_base; - task->stk_size = stk_size; - -#if TOS_CFG_ROUND_ROBIN_EN > 0u - task->timeslice_reload = timeslice; - - if (timeslice == (k_timeslice_t)0u) { - task->timeslice = k_robin_default_timeslice; - } else { - task->timeslice = timeslice; - } -#endif - - TOS_CPU_INT_DISABLE(); - task_state_set_ready(task); - readyqueue_add_tail(task); - TOS_CPU_INT_ENABLE(); - - if (tos_knl_is_running()) { - knl_sched(); - } - - return K_ERR_NONE; -} - -__API__ k_err_t tos_task_destroy(k_task_t *task) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_IN_IRQ_CHECK(); - - if (unlikely(!task)) { - task = k_curr_task; - } - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&task->knl_obj, KNL_OBJ_TYPE_TASK)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (knl_is_idle(task)) { - return K_ERR_TASK_DESTROY_IDLE; - } - - if (knl_is_self(task) && knl_is_sched_locked()) { - return K_ERR_SCHED_LOCKED; - } - - TOS_CPU_INT_DISABLE(); - -#if TOS_CFG_MUTEX_EN > 0u - // when we die, wakeup all the people in this land. - if (!tos_list_empty(&task->mutex_own_list)) { - task_mutex_release(task); - } -#endif - - if (task_state_is_ready(task)) { // that's simple, good kid - readyqueue_remove(task); - } - if (task_state_is_sleeping(task)) { - tick_list_remove(task); - } - if (task_state_is_pending(task)) { - pend_list_remove(task); - } - - task_reset(task); - task_state_set_deleted(task); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ void tos_task_yield(void) -{ - TOS_CPU_CPSR_ALLOC(); - - if (knl_is_inirq()) { - return; - } - - TOS_CPU_INT_DISABLE(); - - readyqueue_remove(k_curr_task); - readyqueue_add_tail(k_curr_task); - - TOS_CPU_INT_ENABLE(); - knl_sched(); -} - -__API__ k_err_t tos_task_prio_change(k_task_t *task, k_prio_t prio_new) -{ - TOS_CPU_CPSR_ALLOC(); -#if TOS_CFG_MUTEX_EN > 0u - k_prio_t highest_pending_prio; -#endif - - TOS_PTR_SANITY_CHECK(task); - TOS_IN_IRQ_CHECK(); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&task->knl_obj, KNL_OBJ_TYPE_TASK)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (unlikely(prio_new >= K_TASK_PRIO_IDLE)) { - return K_ERR_TASK_PRIO_INVALID; - } - - TOS_CPU_INT_DISABLE(); - - if (task->prio == prio_new) { // just kidding - TOS_CPU_INT_ENABLE(); - knl_sched(); - return K_ERR_NONE; - } - -#if TOS_CFG_MUTEX_EN > 0u - if (!tos_list_empty(&task->mutex_own_list)) { - highest_pending_prio = task_highest_pending_prio_get(task); - if (prio_new > highest_pending_prio) { - task->prio_pending = prio_new; - prio_new = highest_pending_prio; - } - } -#endif - - if (task_state_is_pending(task)) { - task->prio = prio_new; - pend_list_adjust(task); - } else if (task_state_is_sleeping(task)) { - task->prio = prio_new; - } else if (task_state_is_ready(task)) { // good kid - readyqueue_remove(task); - - /* ATTENTION: - must do the prio assignment after readyqueue_remove - otherwise the k_rdyq.highest_prio refresh in readyqueue_remove will be wrong. - */ - task->prio = prio_new; - if (knl_is_self(task)) { - readyqueue_add_head(task); - } else { - readyqueue_add_tail(task); - } - } - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_task_suspend(k_task_t *task) -{ - TOS_CPU_CPSR_ALLOC(); - - if (unlikely(!task)) { - task = k_curr_task; - } - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&task->knl_obj, KNL_OBJ_TYPE_TASK)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (knl_is_idle(task)) { - return K_ERR_TASK_SUSPEND_IDLE; - } - - if (unlikely(knl_is_self(task)) && knl_is_sched_locked()) { // if not you, who? - return K_ERR_SCHED_LOCKED; - } - - TOS_CPU_INT_DISABLE(); - - if (task_state_is_ready(task)) { // kill the good kid - readyqueue_remove(task); - } - task_state_set_suspended(task); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_task_resume(k_task_t *task) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(task); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&task->knl_obj, KNL_OBJ_TYPE_TASK)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (unlikely(knl_is_self(task))) { - return K_ERR_TASK_RESUME_SELF; - } - - TOS_CPU_INT_DISABLE(); - - if (!task_state_is_suspended(task)) { - TOS_CPU_INT_ENABLE(); - knl_sched(); - return K_ERR_NONE; - } - - task_state_reset_suspended(task); - if (task_state_is_ready(task)) { // we are good kid now - readyqueue_add(task); - } - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_task_delay(k_tick_t delay) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_IN_IRQ_CHECK(); - - if (knl_is_sched_locked()) { - return K_ERR_SCHED_LOCKED; - } - - if (unlikely(delay == (k_tick_t)0u)) { - tos_task_yield(); - return K_ERR_NONE; - } - - TOS_CPU_INT_DISABLE(); - - if (tick_list_add(k_curr_task, delay) != K_ERR_NONE) { - TOS_CPU_INT_ENABLE(); - return K_ERR_DELAY_FOREVER; - } - - readyqueue_remove(k_curr_task); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -__API__ k_err_t tos_task_delay_abort(k_task_t *task) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_PTR_SANITY_CHECK(task); - TOS_IN_IRQ_CHECK(); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&task->knl_obj, KNL_OBJ_TYPE_TASK)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - - if (knl_is_self(task) || !task_state_is_sleeping(task)) { - TOS_CPU_INT_ENABLE(); - return K_ERR_TASK_NOT_DELAY; - } - - if (task_state_is_suspended(task)) { - TOS_CPU_INT_ENABLE(); - return K_ERR_TASK_SUSPENDED; - } - - tick_list_remove(task); - readyqueue_add(task); - - TOS_CPU_INT_ENABLE(); - knl_sched(); - - return K_ERR_NONE; -} - -#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u - -__API__ k_err_t tos_task_stack_draught_depth(k_task_t *task, int *depth) -{ - TOS_CPU_CPSR_ALLOC(); - k_err_t rc; - - TOS_PTR_SANITY_CHECK(depth); - - if (unlikely(!task)) { - task = k_curr_task; - } - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&task->knl_obj, KNL_OBJ_TYPE_TASK)) { - return K_ERR_OBJ_INVALID; - } -#endif - - TOS_CPU_INT_DISABLE(); - rc = cpu_task_stack_draught_depth(task->stk_base, task->stk_size, depth); - TOS_CPU_INT_ENABLE(); - - return rc; -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_tick.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_tick.c deleted file mode 100644 index 0d764426..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_tick.c +++ /dev/null @@ -1,143 +0,0 @@ -#include - -__STATIC__ void tick_task_place(k_task_t *task, k_tick_t timeout) -{ - TOS_CPU_CPSR_ALLOC(); - k_list_t *curr; - k_task_t *curr_task = K_NULL; - k_tick_t curr_expires, prev_expires = (k_tick_t)0u; - - TOS_CPU_INT_DISABLE(); - - task->tick_expires = timeout; - - TOS_LIST_FOR_EACH(curr, &k_tick_list) { - curr_task = TOS_LIST_ENTRY(curr, k_task_t, tick_list); - curr_expires = prev_expires + curr_task->tick_expires; - - if (task->tick_expires < curr_expires) { - break; - } - prev_expires = curr_expires; - } - task->tick_expires -= prev_expires; - if (curr != &k_tick_list && curr_task) { - curr_task->tick_expires -= task->tick_expires; - } - tos_list_add_tail(&task->tick_list, curr); - - TOS_CPU_INT_ENABLE(); -} - -__STATIC__ void tick_task_takeoff(k_task_t *task) -{ - TOS_CPU_CPSR_ALLOC(); - k_task_t *next; - - TOS_CPU_INT_DISABLE(); - - next = TOS_LIST_FIRST_ENTRY_OR_NULL(&task->tick_list, k_task_t, tick_list); - if (next && task->tick_list.next != &k_tick_list) { // not the only one - if (next->tick_expires <= K_TIME_MAX - task->tick_expires) { - next->tick_expires += task->tick_expires; - } else { - next->tick_expires = K_TIME_MAX; - } - } - - tos_list_del(&task->tick_list); - - TOS_CPU_INT_ENABLE(); -} - -__KERNEL__ k_err_t tick_list_add(k_task_t *task, k_tick_t timeout) -{ - if (timeout == TOS_TIME_NOWAIT) { - return K_ERR_DELAY_ZERO; - } - - if (timeout == TOS_TIME_FOREVER) { - return K_ERR_DELAY_FOREVER; - } - - task->tick_expires = timeout; - - tick_task_place(task, timeout); - task_state_set_sleeping(task); - return K_ERR_NONE; -} - -__KERNEL__ void tick_list_remove(k_task_t *task) -{ - tick_task_takeoff(task); - task_state_reset_sleeping(task); -} - -__KERNEL__ void tick_update(k_tick_t tick) -{ - TOS_CPU_CPSR_ALLOC(); - k_task_t *first, *task; - k_list_t *curr, *next; - - TOS_CPU_INT_DISABLE(); - k_tick_count += tick; - - if (tos_list_empty(&k_tick_list)) { - TOS_CPU_INT_ENABLE(); - return; - } - - first = TOS_LIST_FIRST_ENTRY(&k_tick_list, k_task_t, tick_list); - if (first->tick_expires <= tick) { - first->tick_expires = (k_tick_t)0u; - } else { - first->tick_expires -= tick; - TOS_CPU_INT_ENABLE(); - return; - } - - TOS_LIST_FOR_EACH_SAFE(curr, next, &k_tick_list) { - task = TOS_LIST_ENTRY(curr, k_task_t, tick_list); - if (task->tick_expires > (k_tick_t)0u) { - break; - } - - // we are pending on something, but tick's up, no longer waitting - pend_task_wakeup(task, PEND_STATE_TIMEOUT); - } - - TOS_CPU_INT_ENABLE(); -} - -__KERNEL__ k_tick_t tick_next_expires_get(void) -{ - TOS_CPU_CPSR_ALLOC(); - k_tick_t next_expires; - k_task_t *first; - - TOS_CPU_INT_DISABLE(); - - first = TOS_LIST_FIRST_ENTRY_OR_NULL(&k_tick_list, k_task_t, tick_list); - next_expires = first ? first->tick_expires : TOS_TIME_FOREVER; - - TOS_CPU_INT_ENABLE(); - return next_expires; -} - -__API__ void tos_tick_handler(void) -{ - if (unlikely(!tos_knl_is_running())) { - return; - } - - tick_update((k_tick_t)1u); - -#if TOS_CFG_TIMER_EN > 0u && TOS_CFG_TIMER_AS_PROC > 0u - timer_update(); -#endif - -#if TOS_CFG_ROUND_ROBIN_EN > 0u - robin_sched(k_curr_task->prio); -#endif -} - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_time.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_time.c deleted file mode 100644 index 014b2b87..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_time.c +++ /dev/null @@ -1,49 +0,0 @@ -#include - -__API__ k_tick_t tos_systick_get(void) -{ - TOS_CPU_CPSR_ALLOC(); - k_tick_t tick; - - TOS_CPU_INT_DISABLE(); - tick = k_tick_count; - TOS_CPU_INT_ENABLE(); - return tick; -} - -__API__ void tos_systick_set(k_tick_t tick) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_CPU_INT_DISABLE(); - k_tick_count = tick; - TOS_CPU_INT_ENABLE(); -} - -__API__ k_time_t tos_tick2millisec(k_tick_t tick) -{ - return (k_time_t)(tick * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_TICK_PER_SECOND); -} - -__API__ k_tick_t tos_millisec2tick(k_time_t ms) -{ - return ((k_tick_t)ms * TOS_CFG_CPU_TICK_PER_SECOND / K_TIME_MILLISEC_PER_SEC); -} - -__API__ k_err_t tos_sleep_ms(k_time_t ms) -{ - return tos_task_delay(tos_millisec2tick(ms)); -} - -__STATIC_INLINE__ k_tick_t time_hmsm2tick(k_time_t hour, k_time_t minute, k_time_t second, k_time_t millisec) -{ - return ((k_tick_t)hour * (k_tick_t)3600u + (k_tick_t)minute * (k_tick_t)60u + - (k_tick_t)second) * TOS_CFG_CPU_TICK_PER_SECOND + - (TOS_CFG_CPU_TICK_PER_SECOND * ((k_tick_t)millisec + (k_tick_t)500u / TOS_CFG_CPU_TICK_PER_SECOND)) / (k_tick_t)1000u; -} - -__API__ k_err_t tos_sleep_hmsm(k_time_t hour, k_time_t minute, k_time_t second, k_time_t millisec) -{ - return tos_task_delay(time_hmsm2tick(hour, minute, second, millisec)); -} - diff --git a/board/Nuvoton_M251/TencentOS/kernel/core/tos_timer.c b/board/Nuvoton_M251/TencentOS/kernel/core/tos_timer.c deleted file mode 100644 index db8ff673..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/core/tos_timer.c +++ /dev/null @@ -1,329 +0,0 @@ -#include - -#if TOS_CFG_TIMER_EN > 0u - -__STATIC__ void timer_place(k_timer_t *tmr) -{ - TOS_CPU_CPSR_ALLOC(); - k_list_t *curr; - k_timer_t *iter = K_NULL; - - TOS_CPU_INT_DISABLE(); - - tmr->expires += k_tick_count; - - TOS_LIST_FOR_EACH(curr, &k_timer_ctl.list) { - iter = TOS_LIST_ENTRY(curr, k_timer_t, list); - if (tmr->expires < iter->expires) { - break; - } - } - tos_list_add_tail(&tmr->list, curr); - - if (k_timer_ctl.list.next == &tmr->list) { - // we are the first guy now - k_timer_ctl.next_expires = tmr->expires; - -#if TOS_CFG_TIMER_AS_PROC == 0u - if (task_state_is_sleeping(&k_timer_task)) { - tos_task_delay_abort(&k_timer_task); - } -#endif - } - -#if TOS_CFG_TIMER_AS_PROC == 0u - if (task_state_is_suspended(&k_timer_task)) { - tos_task_resume(&k_timer_task); - } -#endif - - TOS_CPU_INT_ENABLE(); -} - -__STATIC__ void timer_takeoff(k_timer_t *tmr) -{ - TOS_CPU_CPSR_ALLOC(); - k_timer_t *first, *next; - - TOS_CPU_INT_DISABLE(); - - first = TOS_LIST_FIRST_ENTRY(&k_timer_ctl.list, k_timer_t, list); - - tos_list_del(&tmr->list); - - if (first == tmr) { - // if the first guy removed, we need to refresh k_timer_ctl.next_expires - next = TOS_LIST_FIRST_ENTRY_OR_NULL(&tmr->list, k_timer_t, list); - if (!next) { - // the only guy removed - k_timer_ctl.next_expires = TOS_TIME_FOREVER; - } else { - k_timer_ctl.next_expires = next->expires; - } - } - - TOS_CPU_INT_ENABLE(); -} - -__STATIC_INLINE__ void timer_reset(k_timer_t *tmr) -{ -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_deinit(&tmr->knl_obj); -#endif - - tmr->state = TIMER_STATE_UNUSED; - tmr->delay = (k_tick_t)0u; - tmr->expires = (k_tick_t)0u; - tmr->period = (k_tick_t)0u; - tmr->opt = (k_opt_t)0u; - tmr->cb = K_NULL; - tmr->cb_arg = K_NULL; - tos_list_init(&tmr->list); -} - -__API__ k_err_t tos_timer_create(k_timer_t *tmr, - k_tick_t delay, - k_tick_t period, - k_timer_callback_t callback, - void *cb_arg, - k_opt_t opt) -{ - TOS_PTR_SANITY_CHECK(tmr); - TOS_PTR_SANITY_CHECK(callback); - - if (opt == TOS_OPT_TIMER_PERIODIC && period == (k_tick_t)0u) { - return K_ERR_TIMER_INVALID_PERIOD; - } - - if (opt == TOS_OPT_TIMER_ONESHOT && delay == (k_tick_t)0u) { - return K_ERR_TIMER_INVALID_DELAY; - } - - if (opt != TOS_OPT_TIMER_ONESHOT && opt != TOS_OPT_TIMER_PERIODIC) { - return K_ERR_TIMER_INVALID_OPT; - } - - if (delay == TOS_TIME_FOREVER) { - return K_ERR_TIMER_DELAY_FOREVER; - } - - if (period == TOS_TIME_FOREVER) { - return K_ERR_TIMER_PERIOD_FOREVER; - } - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - knl_object_init(&tmr->knl_obj, KNL_OBJ_TYPE_TIMER); -#endif - - tmr->state = TIMER_STATE_STOPPED; - tmr->delay = delay; - tmr->expires = (k_tick_t)0u; - tmr->period = period; - tmr->opt = opt; - tmr->cb = callback; - tmr->cb_arg = cb_arg; - tos_list_init(&tmr->list); - return K_ERR_NONE; -} - -__API__ k_err_t tos_timer_destroy(k_timer_t *tmr) -{ - TOS_PTR_SANITY_CHECK(tmr); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&tmr->knl_obj, KNL_OBJ_TYPE_TIMER)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (tmr->state == TIMER_STATE_UNUSED) { - return K_ERR_TIMER_INACTIVE; - } - - if (tmr->state == TIMER_STATE_RUNNING) { - timer_takeoff(tmr); - } - - timer_reset(tmr); - return K_ERR_NONE; -} - -__API__ k_err_t tos_timer_start(k_timer_t *tmr) -{ - TOS_PTR_SANITY_CHECK(tmr); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&tmr->knl_obj, KNL_OBJ_TYPE_TIMER)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (tmr->state == TIMER_STATE_UNUSED) { - return K_ERR_TIMER_INACTIVE; - } - - if (tmr->state == TIMER_STATE_RUNNING) { - timer_takeoff(tmr); - tmr->expires = tmr->delay; - timer_place(tmr); - return K_ERR_NONE; - } - - if (tmr->state == TIMER_STATE_STOPPED || - tmr->state == TIMER_STATE_COMPLETED) { - tmr->state = TIMER_STATE_RUNNING; - if (tmr->delay == (k_tick_t)0u) { - tmr->expires = tmr->period; - } else { - tmr->expires = tmr->delay; - } - timer_place(tmr); - return K_ERR_NONE; - } - - return K_ERR_TIMER_INVALID_STATE; -} - -__API__ k_err_t tos_timer_stop(k_timer_t *tmr) -{ - TOS_PTR_SANITY_CHECK(tmr); - -#if TOS_CFG_OBJECT_VERIFY_EN > 0u - if (!knl_object_verify(&tmr->knl_obj, KNL_OBJ_TYPE_TIMER)) { - return K_ERR_OBJ_INVALID; - } -#endif - - if (tmr->state == TIMER_STATE_UNUSED) { - return K_ERR_TIMER_INACTIVE; - } - - if (tmr->state == TIMER_STATE_COMPLETED || - tmr->state == TIMER_STATE_STOPPED) { - return K_ERR_TIMER_STOPPED; - } - - if (tmr->state == TIMER_STATE_RUNNING) { - tmr->state = TIMER_STATE_STOPPED; - timer_takeoff(tmr); - } - - return K_ERR_NONE; -} - -__KERNEL__ k_tick_t timer_next_expires_get(void) -{ - TOS_CPU_CPSR_ALLOC(); - k_tick_t next_expires; - - TOS_CPU_INT_DISABLE(); - - if (k_timer_ctl.next_expires == TOS_TIME_FOREVER) { - next_expires = TOS_TIME_FOREVER; - } else if (k_timer_ctl.next_expires <= k_tick_count) { - next_expires = (k_tick_t)0u; - } else { - next_expires = k_timer_ctl.next_expires - k_tick_count; - } - - TOS_CPU_INT_ENABLE(); - return next_expires; -} - -#if TOS_CFG_TIMER_AS_PROC > 0u - -__KERNEL__ void timer_update(void) -{ - k_timer_t *tmr; - k_list_t *curr, *next; - - if (k_timer_ctl.next_expires < k_tick_count) { - return; - } - - tos_knl_sched_lock(); - - TOS_LIST_FOR_EACH_SAFE(curr, next, &k_timer_ctl.list) { - tmr = TOS_LIST_ENTRY(curr, k_timer_t, list); - if (tmr->expires > k_tick_count) { - break; - } - - // time's up - timer_takeoff(tmr); - - if (tmr->opt == TOS_OPT_TIMER_PERIODIC) { - tmr->expires = tmr->period; - timer_place(tmr); - } else { - tmr->state = TIMER_STATE_COMPLETED; - } - - (*tmr->cb)(tmr->cb_arg); - } - - tos_knl_sched_unlock(); -} - -#else /* TOS_CFG_TIMER_AS_PROC > 0u */ - -__STATIC__ void timer_task_entry(void *arg) -{ - k_timer_t *tmr; - k_list_t *curr, *next; - k_tick_t next_expires; - - arg = arg; // make compiler happy - while (K_TRUE) { - next_expires = timer_next_expires_get(); - if (next_expires == TOS_TIME_FOREVER) { - tos_task_suspend(K_NULL); - } else if (next_expires > (k_tick_t)0u) { - tos_task_delay(next_expires); - } - - tos_knl_sched_lock(); - - TOS_LIST_FOR_EACH_SAFE(curr, next, &k_timer_ctl.list) { - tmr = TOS_LIST_ENTRY(curr, k_timer_t, list); - if (tmr->expires > k_tick_count) { // not yet - break; - } - - // time's up - timer_takeoff(tmr); - - if (tmr->opt == TOS_OPT_TIMER_PERIODIC) { - tmr->expires = tmr->period; - timer_place(tmr); - } else { - tmr->state = TIMER_STATE_COMPLETED; - } - - (*tmr->cb)(tmr->cb_arg); - } - - tos_knl_sched_unlock(); - } -} - -#endif - -__KERNEL__ k_err_t timer_init(void) -{ -#if TOS_CFG_TIMER_AS_PROC > 0u - return K_ERR_NONE; -#else - return tos_task_create(&k_timer_task, - "timer", - timer_task_entry, - K_NULL, - k_timer_task_prio, - k_timer_task_stk_addr, - k_timer_task_stk_size, - 0); -#endif -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal.h b/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal.h deleted file mode 100644 index 50ef205f..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _TOS_HAL_H_ -#define _TOS_HAL_H_ - -#include "tos.h" -#include "tos_hal_sd.h" -#include "tos_hal_uart.h" - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_sd.h b/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_sd.h deleted file mode 100644 index 0b18dfc9..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_sd.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef _TOS_HAL_SD_H_ -#define _TOS_HAL_SD_H_ - -typedef enum hal_sd_state_en { - HAL_SD_STAT_RESET, /*< not yet initialized or disabled */ - HAL_SD_STAT_READY, /*< initialized and ready for use */ - HAL_SD_STAT_TIMEOUT, /*< timeout state */ - HAL_SD_STAT_BUSY, /*< process ongoing */ - HAL_SD_STAT_PROGRAMMING, /*< programming state */ - HAL_SD_STAT_RECEIVING, /*< receinving state */ - HAL_SD_STAT_TRANSFER, /*< transfert state */ - HAL_SD_STAT_ERROR, /*< error state */ -} hal_sd_state_t; - -typedef struct hal_sd_info_st { - uint32_t card_type; /*< card type */ - uint32_t card_version; /*< card version */ - uint32_t class; /*< card class */ - uint32_t relative_card_addr; /*< relative card address */ - uint32_t blk_num; /*< card capacity in blocks */ - uint32_t blk_size; /*< one block size in bytes */ - uint32_t logical_blk_num; /*< card logical capacity in blocks */ - uint32_t logical_blk_size; /*< logical block size in bytes */ -} hal_sd_info_t; - -typedef struct hal_sd_st { - void *private_sd; -} hal_sd_t; - -__API__ int tos_hal_sd_init(hal_sd_t *sd); - -__API__ int tos_hal_sd_read(hal_sd_t *sd, uint8_t *buf, uint32_t blk_addr, uint32_t blk_num, uint32_t timeout); - -__API__ int tos_hal_sd_write(hal_sd_t *sd, const uint8_t *buf, uint32_t blk_addr, uint32_t blk_num, uint32_t timeout); - -__API__ int tos_hal_sd_read_dma(hal_sd_t *sd, uint8_t *buf, uint32_t blk_addr, uint32_t blk_num); - -__API__ int tos_hal_sd_write_dma(hal_sd_t *sd, const uint8_t *buf, uint32_t blk_addr, uint32_t blk_num); - -__API__ int tos_hal_sd_erase(hal_sd_t *sd, uint32_t blk_add_start, uint32_t blk_addr_end); - -__API__ int tos_hal_sd_info_get(hal_sd_t *sd, hal_sd_info_t *info); - -__API__ int tos_hal_sd_state_get(hal_sd_t *sd, hal_sd_state_t *state); - -__API__ int tos_hal_sd_deinit(hal_sd_t *sd); - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_uart.h b/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_uart.h deleted file mode 100644 index e0dfc7bb..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/hal/include/tos_hal_uart.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _TOS_HAL_UART_H_ -#define _TOS_HAL_UART_H_ - -typedef enum hal_uart_port_en { - HAL_UART_PORT_0 = 0, - HAL_UART_PORT_1, - HAL_UART_PORT_2, - HAL_UART_PORT_3, - HAL_UART_PORT_4, - HAL_UART_PORT_5, - HAL_UART_PORT_6, -} hal_uart_port_t; - -typedef struct hal_uart_st { - hal_uart_port_t port; - void *private_uart; -} hal_uart_t; - -__API__ int tos_hal_uart_init(hal_uart_t *uart, hal_uart_port_t port); - -__API__ int tos_hal_uart_write(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout); - -__API__ int tos_hal_uart_read(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout); - -__API__ int tos_hal_uart_deinit(hal_uart_t *uart); - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_pm.h b/board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_pm.h deleted file mode 100644 index d565ab4e..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_pm.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifndef _TOS_PM_H_ -#define _TOS_PM_H_ - -#if TOS_CFG_PWR_MGR_EN > 0u - -#define K_PM_DEVICE_MAX_COUNT 10u - -typedef enum idle_power_manager_mode_en { - IDLE_POWER_MANAGER_MODE_SLEEP, - IDLE_POWER_MANAGER_MODE_TICKLESS, -} idle_pwrmgr_mode_t; - -/* - Low-power mode summary -|-------------------------------------------------------------------------------------------------------------------| -| Mode name | Entry | Wakeup | Effect on 1.8V | Effect on VDD | Voltage regulator | -| | | | domain clocks | domain clocks | | -|----------------|------------------|--------------------|--------------------|-----------------|-------------------| -| Sleep | WFI | Any interrupt | CPU clock OFF | | | -| (Sleep now or |------------------|--------------------| no effect on other | None | ON | -| Sleep-on-exit) | WFE | Wakeup event | clocks or analog | | | -| | | | clock sources | | | -|----------------|------------------|--------------------|--------------------|-----------------|-------------------| -| | | | | | ON or in | -| Stop | PDDS and LPDS | Any EXTI line | | | low-power mode | -| | bits + SLEEPDEEP | (configured in the | | | (depends on Power | -| | bit + WFI or WFE | EXTI registers | | | control register | -| | | | | | (PWR_CR) | -|----------------|------------------|--------------------| All 1.8V domain | HSI and HSE |-------------------| -| | | WKUP pin rising | clocks OFF | oscillators OFF | | -| Standby | PDDS bit + | edge, RTC alarm, | | | | -| | SLEEPDEEP bit + | external reset in | | | OFF | -| | WFI or WFE | NRST pin, | | | | -| | | IWDG reset | | | | -| | | | | | | -|-------------------------------------------------------------------------------------------------------------------| - */ -typedef enum k_cpu_low_power_mode_en { - TOS_LOW_POWER_MODE_SLEEP = 0, /* wakeup source: systick/tim/rtc */ - TOS_LOW_POWER_MODE_STOP, /* wakeup source: rtc wakeup/alarm */ - TOS_LOW_POWER_MODE_STANDBY, /* wakeup source: rtc alarm */ - __LOW_POWER_MODE_DUMMY, -} k_cpu_lpwr_mode_t; - -typedef struct k_pm_device_st { - char *name; - - int (*init)(void); - int (*suspend)(void); - int (*resume)(void); -} k_pm_device_t; - -typedef struct pm_device_control_st { - uint8_t count; - k_pm_device_t *mgr[K_PM_DEVICE_MAX_COUNT]; -} pm_device_ctl_t; - -#if TOS_CFG_TICKLESS_EN > 0u -__API__ k_err_t tos_pm_cpu_lpwr_mode_set(k_cpu_lpwr_mode_t cpu_lpwr_mode); -#endif - -__API__ k_err_t tos_pm_device_register(k_pm_device_t *device); - -__KERNEL__ void pm_init(void); - -__KERNEL__ void pm_cpu_lpwr_mode_enter(k_cpu_lpwr_mode_t lpwr_mode); - -__KERNEL__ k_cpu_lpwr_mode_t pm_cpu_lpwr_mode_get(void); - -__KERNEL__ void pm_idle_pwr_mgr_mode_set(idle_pwrmgr_mode_t idle_pwrmgr_mode); - -__KERNEL__ int pm_idle_pwr_mgr_mode_is_sleep(void); - -__KERNEL__ int pm_idle_pwr_mgr_mode_is_tickless(void); - -__KERNEL__ void pm_power_manager(void); - -__KERNEL__ int pm_device_suspend(void); - -__KERNEL__ int pm_device_resume(void); - -#endif /* TOS_CFG_PWR_MGR_EN */ - -#endif /* _TOS_PM_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_tickless.h b/board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_tickless.h deleted file mode 100644 index c1ba76ae..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/pm/include/tos_tickless.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _TOS_TICKLESS_H_ -#define _TOS_TICKLESS_H_ - -#if TOS_CFG_TICKLESS_EN > 0u - -typedef struct k_tickless_wakeup_alarm_st { - int (*init)(void); - int (*setup)(k_time_t millisecond); - int (*dismiss)(void); - k_time_t (*max_delay)(void); /* in millisecond */ -} k_tickless_wkup_alarm_t; - -__API__ void tos_tickless_wkup_alarm_install(k_cpu_lpwr_mode_t mode, k_tickless_wkup_alarm_t *wkup_alarm); - -__API__ k_err_t tos_tickless_wkup_alarm_init(k_cpu_lpwr_mode_t mode); - -__HOOK__ int tos_bsp_tickless_setup(void); - -__KERNEL__ int tickless_wkup_alarm_is_installed(k_cpu_lpwr_mode_t mode); - -__KERNEL__ void tickless_init(void); - -__KERNEL__ void tickless_proc(void); - -#endif /* TOS_CFG_TICKLESS_EN */ - -#endif /* _TOS_TICKLESS_H_ */ - diff --git a/board/Nuvoton_M251/TencentOS/kernel/pm/tos_pm.c b/board/Nuvoton_M251/TencentOS/kernel/pm/tos_pm.c deleted file mode 100644 index 7fa053aa..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/pm/tos_pm.c +++ /dev/null @@ -1,144 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_PWR_MGR_EN > 0u - -#if TOS_CFG_TICKLESS_EN > 0u -__API__ k_err_t tos_pm_cpu_lpwr_mode_set(k_cpu_lpwr_mode_t cpu_lpwr_mode) -{ - TOS_CPU_CPSR_ALLOC(); - - if (!tickless_wkup_alarm_is_installed(cpu_lpwr_mode)) { - return K_ERR_PM_WKUP_SOURCE_NOT_INSTALL; - } - - TOS_CPU_INT_DISABLE(); - k_cpu_lpwr_mode = cpu_lpwr_mode; - TOS_CPU_INT_ENABLE(); - return K_ERR_NONE; -} -#endif - -__STATIC__ int pm_device_is_registered(k_pm_device_t *device) -{ - uint8_t i = 0; - - for (i = 0; i < k_pm_device_ctl.count; ++i) { - if (strcmp(k_pm_device_ctl.mgr[i]->name, device->name) == 0) { - return 1; - } - } - return 0; -} - -__API__ k_err_t tos_pm_device_register(k_pm_device_t *device) -{ - TOS_PTR_SANITY_CHECK(device); - - if (pm_device_is_registered(device)) { - return K_ERR_PM_DEVICE_ALREADY_REG; - } - - if (k_pm_device_ctl.count >= K_PM_DEVICE_MAX_COUNT) { - return K_ERR_PM_DEVICE_OVERFLOW; - } - - k_pm_device_ctl.mgr[k_pm_device_ctl.count++] = device; - - return K_ERR_NONE; -} - -__KERNEL__ void pm_init(void) -{ - memset(&k_pm_device_ctl, 0, sizeof(k_pm_device_ctl)); - k_pm_device_ctl.count = 0u; -} - -__STATIC_INLINE__ void pm_cpu_sleep_mode_enter(void) -{ - cpu_sleep_mode_enter(); -} - -__STATIC_INLINE__ void pm_cpu_stop_mode_enter(void) -{ - cpu_stop_mode_enter(); -} - -__STATIC_INLINE__ void pm_cpu_standby_mode_enter(void) -{ - cpu_standby_mode_enter(); -} - -__KERNEL__ void pm_cpu_lpwr_mode_enter(k_cpu_lpwr_mode_t lpwr_mode) -{ - if (TOS_LOW_POWER_MODE_SLEEP == lpwr_mode) { - pm_cpu_sleep_mode_enter(); - } else if (TOS_LOW_POWER_MODE_STOP == lpwr_mode) { - pm_device_suspend(); - pm_cpu_stop_mode_enter(); - pm_device_resume(); - } else if (TOS_LOW_POWER_MODE_STANDBY == lpwr_mode) { - pm_device_suspend(); - pm_cpu_standby_mode_enter(); - pm_device_resume(); - } -} - -__KERNEL__ k_cpu_lpwr_mode_t pm_cpu_lpwr_mode_get(void) -{ - return k_cpu_lpwr_mode; -} - -__KERNEL__ void pm_idle_pwr_mgr_mode_set(idle_pwrmgr_mode_t idle_pwrmgr_mode) -{ - k_idle_pwr_mgr_mode = idle_pwrmgr_mode; -} - -__KERNEL__ int pm_idle_pwr_mgr_mode_is_sleep(void) -{ - return k_idle_pwr_mgr_mode == IDLE_POWER_MANAGER_MODE_SLEEP; -} - -__KERNEL__ int pm_idle_pwr_mgr_mode_is_tickless(void) -{ - return k_idle_pwr_mgr_mode == IDLE_POWER_MANAGER_MODE_TICKLESS; -} - -__KERNEL__ void pm_power_manager(void) -{ - if (pm_idle_pwr_mgr_mode_is_sleep()) { - pm_cpu_sleep_mode_enter(); - } - -#if TOS_CFG_TICKLESS_EN > 0u - else if (pm_idle_pwr_mgr_mode_is_tickless()) { - tickless_proc(); - } -#endif -} - -__KERNEL__ int pm_device_suspend(void) -{ - uint8_t i = 0; - - for (i = 0; i < k_pm_device_ctl.count; ++i) { - if (*k_pm_device_ctl.mgr[i]->suspend) { - (*k_pm_device_ctl.mgr[i]->suspend)(); - } - } - return 0; -} - -__KERNEL__ int pm_device_resume(void) -{ - uint8_t i = 0; - - for (i = 0; i < k_pm_device_ctl.count; ++i) { - if (*k_pm_device_ctl.mgr[i]->resume) { - (*k_pm_device_ctl.mgr[i]->resume)(); - } - } - return 0; -} - -#endif - diff --git a/board/Nuvoton_M251/TencentOS/kernel/pm/tos_tickless.c b/board/Nuvoton_M251/TencentOS/kernel/pm/tos_tickless.c deleted file mode 100644 index 2b498ac3..00000000 --- a/board/Nuvoton_M251/TencentOS/kernel/pm/tos_tickless.c +++ /dev/null @@ -1,144 +0,0 @@ -#include "tos.h" - -#if TOS_CFG_TICKLESS_EN > 0u - -__API__ void tos_tickless_wkup_alarm_install(k_cpu_lpwr_mode_t mode, k_tickless_wkup_alarm_t *wkup_alarm) -{ - k_tickless_wkup_alarm[mode] = wkup_alarm; -} - -__API__ k_err_t tos_tickless_wkup_alarm_init(k_cpu_lpwr_mode_t mode) -{ - if (!k_tickless_wkup_alarm[mode]) { - return K_ERR_TICKLESS_WKUP_ALARM_NOT_INSTALLED; - } - - if (!k_tickless_wkup_alarm[mode]->init) { - return K_ERR_TICKLESS_WKUP_ALARM_NO_INIT; - } - - if (k_tickless_wkup_alarm[mode]->init() != 0) { - return K_ERR_TICKLESS_WKUP_ALARM_INIT_FAILED; - } - return K_ERR_NONE; -} - -__KERNEL__ int tickless_wkup_alarm_is_installed(k_cpu_lpwr_mode_t mode) -{ - return k_tickless_wkup_alarm[mode] != K_NULL; -} - -__STATIC__ int tickless_wkup_alarm_setup(k_cpu_lpwr_mode_t mode, k_time_t expires) -{ - if (k_tickless_wkup_alarm[mode] && k_tickless_wkup_alarm[mode]->setup) { - return k_tickless_wkup_alarm[mode]->setup(expires); - } - return -1; -} - -__STATIC__ int tickless_wkup_alarm_dismiss(k_cpu_lpwr_mode_t mode) -{ - if (k_tickless_wkup_alarm[mode] && k_tickless_wkup_alarm[mode]->dismiss) { - return k_tickless_wkup_alarm[mode]->dismiss(); - } - return -1; -} - -__STATIC__ k_time_t tickless_wkup_alarm_max_delay(k_cpu_lpwr_mode_t mode) -{ - if (k_tickless_wkup_alarm[mode] && k_tickless_wkup_alarm[mode]->max_delay) { - return k_tickless_wkup_alarm[mode]->max_delay(); - } - return (k_time_t)0u; -} - -__STATIC__ k_time_t tickless_cpu_sleep_time_get(k_cpu_lpwr_mode_t lpwr_mode) -{ - k_tick_t next_expires; - k_time_t time_sleep_ms, max_delay_ms; - - /* the max time(in millisecond) we can sleep */ - max_delay_ms = tickless_wkup_alarm_max_delay(lpwr_mode); - - next_expires = knl_next_expires_get(); - if (next_expires == TOS_TIME_FOREVER) { - return max_delay_ms; - } - - /* how much time should we sleep(in millisecond) */ - time_sleep_ms = (k_time_t)(next_expires * K_TIME_MILLISEC_PER_SEC / k_cpu_tick_per_second); - - return time_sleep_ms > max_delay_ms ? max_delay_ms : time_sleep_ms; -} - -__STATIC__ void tickless_systick_suspend(void) -{ - cpu_systick_suspend(); - cpu_systick_pending_reset(); -} - -__STATIC__ void tickless_systick_resume(void) -{ - cpu_systick_suspend(); - cpu_systick_reset(); - cpu_systick_resume(); -} - -__STATIC__ void tickless_systick_fix(k_tick_t tick_sleep) -{ - TOS_CPU_CPSR_ALLOC(); - - TOS_CPU_INT_DISABLE(); - - /* we wakeup from SLEEP mode, fix the system's tick & timer */ - tick_update(tick_sleep); - -#if TOS_CFG_TIMER_EN > 0u && TOS_CFG_TIMER_AS_PROC > 0u - timer_update(); -#endif - - tickless_systick_resume(); - - TOS_CPU_INT_ENABLE(); -} - -__STATIC__ void tickless_enter(void) -{ - tickless_systick_suspend(); -} - -__STATIC__ void tickless_leave(k_time_t time_sleep_ms) -{ - k_tick_t tick_sleep; - - /* how many "ticks" have we sleep */ - tick_sleep = k_cpu_tick_per_second * time_sleep_ms / K_TIME_MILLISEC_PER_SEC; - - tickless_systick_fix(tick_sleep); -} - -__KERNEL__ void tickless_proc(void) -{ - k_time_t time_sleep; - k_cpu_lpwr_mode_t lpwr_mode; - - lpwr_mode = pm_cpu_lpwr_mode_get(); - - time_sleep = tickless_cpu_sleep_time_get(lpwr_mode); /* in millisecond */ - - tickless_enter(); - tickless_wkup_alarm_setup(lpwr_mode, time_sleep); - pm_cpu_lpwr_mode_enter(lpwr_mode); - tickless_wkup_alarm_dismiss(lpwr_mode); - tickless_leave(time_sleep); -} - -__KERNEL__ void tickless_init(void) -{ - pm_idle_pwr_mgr_mode_set(IDLE_POWER_MANAGER_MODE_TICKLESS); - - tos_bsp_tickless_setup(); -} - -#endif - diff --git a/board/Nuvoton_M251/Project/Nu_Link_Driver.ini b/board/Nuvoton_M251/hello world/Nu_Link_Driver.ini similarity index 100% rename from board/Nuvoton_M251/Project/Nu_Link_Driver.ini rename to board/Nuvoton_M251/hello world/Nu_Link_Driver.ini diff --git a/board/Nuvoton_M251/Project/NuvotonTos.uvguix.Administrator b/board/Nuvoton_M251/hello world/NuvotonTos.uvguix.Administrator similarity index 82% rename from board/Nuvoton_M251/Project/NuvotonTos.uvguix.Administrator rename to board/Nuvoton_M251/hello world/NuvotonTos.uvguix.Administrator index 602f19a3..a5e4343b 100644 --- a/board/Nuvoton_M251/Project/NuvotonTos.uvguix.Administrator +++ b/board/Nuvoton_M251/hello world/NuvotonTos.uvguix.Administrator @@ -16,12 +16,12 @@ 346 Code Coverage - 1010 160 + 770 160 204 Performance Analyzer - 1170 + 930 @@ -80,8 +80,8 @@ 44 - 2 - 3 + 0 + 1 -1 -1 @@ -91,17 +91,17 @@ -1 - 93 - 395 - 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1423 @@ -1772,7 +1772,7 @@ Build 678 - 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E00000000000000000000000000000000010000000100000001809E8A0000000000001F0000000000000000000000000000000001000000010000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64CF010000 + 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000004001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E00000000000000000000000000000000010000000100000001809E8A0000000000001F0000000000000000000000000000000001000000010000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64CF010000 583 @@ -1807,58 +1807,4 @@ - - 1 - 0 - - 100 - 0 - - .\main.c - 6 - 13 - 34 - 0 - - 0 - - - ..\TencentOS\arch\port_c.c - 42 - 1 - 3 - 1 - - 0 - - - ..\TencentOS\arch\port_s.S - 0 - 1 - 1 - 1 - - 0 - - - ..\TencentOS\TOS_CONFIG\tos_config.h - 103 - 8 - 42 - 1 - - 0 - - - ..\STARTUP\system_M251.c - 0 - 131 - 153 - 1 - - 0 - - - - diff --git a/board/Nuvoton_M251/Project/NuvotonTos.uvoptx b/board/Nuvoton_M251/hello world/NuvotonTos.uvoptx similarity index 82% rename from board/Nuvoton_M251/Project/NuvotonTos.uvoptx rename to board/Nuvoton_M251/hello world/NuvotonTos.uvoptx index f1b2aa8c..fa5c5284 100644 --- a/board/Nuvoton_M251/Project/NuvotonTos.uvoptx +++ b/board/Nuvoton_M251/hello world/NuvotonTos.uvoptx @@ -180,7 +180,7 @@ 0 0 0 - ..\STARTUP\system_M251.c + ..\BSP\Src\system_M251.c system_M251.c 0 0 @@ -192,7 +192,7 @@ 0 0 0 - ..\STARTUP\startup_M251.s + .\startup_M251.s startup_M251.s 0 0 @@ -201,7 +201,7 @@ StdDriver - 0 + 1 0 0 0 @@ -212,7 +212,7 @@ 0 0 0 - ..\StdDriver\src\clk.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\clk.c clk.c 0 0 @@ -224,8 +224,8 @@ 0 0 0 - ..\StdDriver\src\retarget.c - retarget.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\gpio.c + gpio.c 0 0 @@ -236,8 +236,8 @@ 0 0 0 - ..\StdDriver\src\uart.c - uart.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\retarget.c + retarget.c 0 0 @@ -248,8 +248,8 @@ 0 0 0 - ..\StdDriver\src\gpio.c - gpio.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\sys.c + sys.c 0 0 @@ -260,8 +260,8 @@ 0 0 0 - ..\StdDriver\src\sys.c - sys.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\uart.c + uart.c 0 0 @@ -280,7 +280,7 @@ 0 0 0 - .\main.c + ..\BSP\Src\main.c main.c 0 0 @@ -289,7 +289,7 @@ Tos/arch - 1 + 0 0 0 0 @@ -300,8 +300,8 @@ 0 0 0 - ..\TencentOS\arch\port_c.c - port_c.c + ..\..\..\arch\arm\arm-v8m\common\tos_cpu.c + tos_cpu.c 0 0 @@ -312,40 +312,40 @@ 0 0 0 - ..\TencentOS\arch\tos_cpu.c - tos_cpu.c - 0 - 0 - - - 4 - 11 - 1 - 0 - 0 - 0 - ..\TencentOS\arch\tos_fault.c + ..\..\..\arch\arm\arm-v8m\common\tos_fault.c tos_fault.c 0 0 4 - 12 + 11 2 0 0 0 - ..\TencentOS\arch\port_s.S + ..\..\..\arch\arm\arm-v8m\cortex-m23\armcc\port_s.S port_s.S 0 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\..\arch\arm\arm-v8m\cortex-m23\armcc\port_c.c + port_c.c + 0 + 0 + Tos/kernel - 0 + 1 0 0 0 @@ -356,7 +356,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_event.c + ..\..\..\kernel\core\tos_event.c tos_event.c 0 0 @@ -368,7 +368,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_fifo.c + ..\..\..\kernel\core\tos_fifo.c tos_fifo.c 0 0 @@ -380,7 +380,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_global.c + ..\..\..\kernel\core\tos_global.c tos_global.c 0 0 @@ -392,7 +392,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_mmblk.c + ..\..\..\kernel\core\tos_mmblk.c tos_mmblk.c 0 0 @@ -404,7 +404,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_mmheap.c + ..\..\..\kernel\core\tos_mmheap.c tos_mmheap.c 0 0 @@ -416,7 +416,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_msg.c + ..\..\..\kernel\core\tos_msg.c tos_msg.c 0 0 @@ -428,7 +428,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_mutex.c + ..\..\..\kernel\core\tos_mutex.c tos_mutex.c 0 0 @@ -440,7 +440,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_pend.c + ..\..\..\kernel\core\tos_pend.c tos_pend.c 0 0 @@ -452,7 +452,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_queue.c + ..\..\..\kernel\core\tos_queue.c tos_queue.c 0 0 @@ -464,7 +464,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_robin.c + ..\..\..\kernel\core\tos_robin.c tos_robin.c 0 0 @@ -476,7 +476,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_sched.c + ..\..\..\kernel\core\tos_sched.c tos_sched.c 0 0 @@ -488,7 +488,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_sem.c + ..\..\..\kernel\core\tos_sem.c tos_sem.c 0 0 @@ -500,7 +500,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_sys.c + ..\..\..\kernel\core\tos_sys.c tos_sys.c 0 0 @@ -512,7 +512,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_task.c + ..\..\..\kernel\core\tos_task.c tos_task.c 0 0 @@ -524,7 +524,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_tick.c + ..\..\..\kernel\core\tos_tick.c tos_tick.c 0 0 @@ -536,7 +536,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_time.c + ..\..\..\kernel\core\tos_time.c tos_time.c 0 0 @@ -548,7 +548,7 @@ 0 0 0 - ..\TencentOS\kernel\core\tos_timer.c + ..\..\..\kernel\core\tos_timer.c tos_timer.c 0 0 @@ -560,7 +560,7 @@ 0 0 0 - ..\TencentOS\kernel\pm\tos_pm.c + ..\..\..\kernel\pm\tos_pm.c tos_pm.c 0 0 @@ -572,27 +572,51 @@ 0 0 0 - ..\TencentOS\kernel\pm\tos_tickless.c + ..\..\..\kernel\pm\tos_tickless.c tos_tickless.c 0 0 + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\kernel\core\tos_completion.c + tos_completion.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\kernel\core\tos_countdownlatch.c + tos_countdownlatch.c + 0 + 0 + Tos/config - 1 + 0 0 0 0 6 - 32 + 34 5 0 0 0 - ..\TencentOS\TOS_CONFIG\tos_config.h + ..\TOS_CONFIG\tos_config.h tos_config.h 0 0 diff --git a/board/Nuvoton_M251/Project/NuvotonTos.uvprojx b/board/Nuvoton_M251/hello world/NuvotonTos.uvprojx similarity index 85% rename from board/Nuvoton_M251/Project/NuvotonTos.uvprojx rename to board/Nuvoton_M251/hello world/NuvotonTos.uvprojx index 220a0d3d..bb49b217 100644 --- a/board/Nuvoton_M251/Project/NuvotonTos.uvprojx +++ b/board/Nuvoton_M251/hello world/NuvotonTos.uvprojx @@ -336,7 +336,7 @@ - ..\CMSIS;..\STARTUP;..\StdDriver\inc;..\TencentOS\arch\include;..\TencentOS\kernel\core\include;..\TencentOS\kernel\pm\include;..\TencentOS\TOS_CONFIG;..\TencentOS\arch;..\STARTUP\Include + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\inc;..\TOS_CONFIG;..\..\..\arch\arm\arm-v8m\common\include;..\..\..\arch\arm\arm-v8m\cortex-m23\armcc;..\..\..\kernel\core\include;..\..\..\kernel\pm\include;..\BSP\Src;..\BSP\Inc;..\..\..\platform\vendor_bsp\st\CMSIS\Core\Include @@ -383,12 +383,12 @@ system_M251.c 1 - ..\STARTUP\system_M251.c + ..\BSP\Src\system_M251.c startup_M251.s 2 - ..\STARTUP\startup_M251.s + .\startup_M251.s @@ -398,27 +398,27 @@ clk.c 1 - ..\StdDriver\src\clk.c - - - retarget.c - 1 - ..\StdDriver\src\retarget.c - - - uart.c - 1 - ..\StdDriver\src\uart.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\clk.c gpio.c 1 - ..\StdDriver\src\gpio.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\gpio.c + + + retarget.c + 1 + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\retarget.c sys.c 1 - ..\StdDriver\src\sys.c + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\sys.c + + + uart.c + 1 + ..\..\..\platform\vendor_bsp\Nuvoton\Nuvoton_M251\StdDriver\src\uart.c @@ -428,32 +428,32 @@ main.c 1 - .\main.c + ..\BSP\Src\main.c Tos/arch - - port_c.c - 1 - ..\TencentOS\arch\port_c.c - tos_cpu.c 1 - ..\TencentOS\arch\tos_cpu.c + ..\..\..\arch\arm\arm-v8m\common\tos_cpu.c tos_fault.c 1 - ..\TencentOS\arch\tos_fault.c + ..\..\..\arch\arm\arm-v8m\common\tos_fault.c port_s.S 2 - ..\TencentOS\arch\port_s.S + ..\..\..\arch\arm\arm-v8m\cortex-m23\armcc\port_s.S + + + port_c.c + 1 + ..\..\..\arch\arm\arm-v8m\cortex-m23\armcc\port_c.c @@ -463,97 +463,107 @@ tos_event.c 1 - ..\TencentOS\kernel\core\tos_event.c + ..\..\..\kernel\core\tos_event.c tos_fifo.c 1 - ..\TencentOS\kernel\core\tos_fifo.c + ..\..\..\kernel\core\tos_fifo.c tos_global.c 1 - ..\TencentOS\kernel\core\tos_global.c + ..\..\..\kernel\core\tos_global.c tos_mmblk.c 1 - ..\TencentOS\kernel\core\tos_mmblk.c + ..\..\..\kernel\core\tos_mmblk.c tos_mmheap.c 1 - ..\TencentOS\kernel\core\tos_mmheap.c + ..\..\..\kernel\core\tos_mmheap.c tos_msg.c 1 - ..\TencentOS\kernel\core\tos_msg.c + ..\..\..\kernel\core\tos_msg.c tos_mutex.c 1 - ..\TencentOS\kernel\core\tos_mutex.c + ..\..\..\kernel\core\tos_mutex.c tos_pend.c 1 - ..\TencentOS\kernel\core\tos_pend.c + ..\..\..\kernel\core\tos_pend.c tos_queue.c 1 - ..\TencentOS\kernel\core\tos_queue.c + ..\..\..\kernel\core\tos_queue.c tos_robin.c 1 - ..\TencentOS\kernel\core\tos_robin.c + ..\..\..\kernel\core\tos_robin.c tos_sched.c 1 - ..\TencentOS\kernel\core\tos_sched.c + ..\..\..\kernel\core\tos_sched.c tos_sem.c 1 - ..\TencentOS\kernel\core\tos_sem.c + ..\..\..\kernel\core\tos_sem.c tos_sys.c 1 - ..\TencentOS\kernel\core\tos_sys.c + ..\..\..\kernel\core\tos_sys.c tos_task.c 1 - ..\TencentOS\kernel\core\tos_task.c + ..\..\..\kernel\core\tos_task.c tos_tick.c 1 - ..\TencentOS\kernel\core\tos_tick.c + ..\..\..\kernel\core\tos_tick.c tos_time.c 1 - ..\TencentOS\kernel\core\tos_time.c + ..\..\..\kernel\core\tos_time.c tos_timer.c 1 - ..\TencentOS\kernel\core\tos_timer.c + ..\..\..\kernel\core\tos_timer.c tos_pm.c 1 - ..\TencentOS\kernel\pm\tos_pm.c + ..\..\..\kernel\pm\tos_pm.c tos_tickless.c 1 - ..\TencentOS\kernel\pm\tos_tickless.c + ..\..\..\kernel\pm\tos_tickless.c + + + tos_completion.c + 1 + ..\..\..\kernel\core\tos_completion.c + + + tos_countdownlatch.c + 1 + ..\..\..\kernel\core\tos_countdownlatch.c @@ -563,7 +573,7 @@ tos_config.h 5 - ..\TencentOS\TOS_CONFIG\tos_config.h + ..\TOS_CONFIG\tos_config.h diff --git a/board/Nuvoton_M251/Project/Objects/NuvotonTos.build_log.htm b/board/Nuvoton_M251/hello world/Objects/NuvotonTos.build_log.htm similarity index 90% rename from board/Nuvoton_M251/Project/Objects/NuvotonTos.build_log.htm rename to board/Nuvoton_M251/hello world/Objects/NuvotonTos.build_log.htm index bde5ca26..6721cb7f 100644 --- a/board/Nuvoton_M251/Project/Objects/NuvotonTos.build_log.htm +++ b/board/Nuvoton_M251/hello world/Objects/NuvotonTos.build_log.htm @@ -21,7 +21,7 @@ Target DLL: NULink\Nu_Link.dll V3.00 Dialog DLL: TCM.DLL V1.32.0.0

Project:

-C:\Users\Administrator\Desktop\Nuvoton_code\Nuvoton_M251\Project\NuvotonTos.uvprojx +C:\Users\Administrator\Desktop\TencentOS-tiny\board\Nuvoton_M251\hello world\NuvotonTos.uvprojx Project File Date: 10/25/2019

Output:

@@ -30,15 +30,15 @@ Rebuild target 'Target 1' compiling system_M251.c... assembling startup_M251.s... compiling clk.c... -compiling retarget.c... -compiling uart.c... compiling gpio.c... +compiling retarget.c... compiling sys.c... +compiling uart.c... compiling main.c... -compiling port_c.c... compiling tos_cpu.c... compiling tos_fault.c... assembling port_s.S... +compiling port_c.c... compiling tos_event.c... compiling tos_fifo.c... compiling tos_global.c... @@ -58,8 +58,10 @@ compiling tos_time.c... compiling tos_timer.c... compiling tos_pm.c... compiling tos_tickless.c... +compiling tos_completion.c... +compiling tos_countdownlatch.c... linking... -Program Size: Code=7956 RO-data=552 RW-data=64 ZI-data=6880 +Program Size: Code=8136 RO-data=552 RW-data=72 ZI-data=6920 ".\Objects\NuvotonTos.axf" - 0 Error(s), 0 Warning(s).

Software Packages used:

@@ -83,7 +85,7 @@ Package Vendor: Nuvoton

Collection of Component Files used:

* Component: ARM::CMSIS:CORE:5.0.1 -Build Time Elapsed: 00:00:16 +Build Time Elapsed: 00:00:19 diff --git a/board/Nuvoton_M251/Project/Objects/NuvotonTos.htm b/board/Nuvoton_M251/hello world/Objects/NuvotonTos.htm similarity index 82% rename from board/Nuvoton_M251/Project/Objects/NuvotonTos.htm rename to board/Nuvoton_M251/hello world/Objects/NuvotonTos.htm index 6e633f6d..b9cd1e0e 100644 --- a/board/Nuvoton_M251/Project/Objects/NuvotonTos.htm +++ b/board/Nuvoton_M251/hello world/Objects/NuvotonTos.htm @@ -3,7 +3,7 @@ Static Call Graph - [.\Objects\NuvotonTos.axf]

Static Call Graph for image .\Objects\NuvotonTos.axf

-

#<CALLGRAPH># ARM Linker, 6070001: Last Updated: Fri Oct 25 16:19:59 2019 +

#<CALLGRAPH># ARM Linker, 6070001: Last Updated: Fri Oct 25 18:45:40 2019

Maximum Stack Usage = 176 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

Call chain for Maximum Stack Depth:

@@ -12,10 +12,10 @@ __rt_entry_main ⇒ main ⇒ SYS_Init ⇒ CLK_SetCoreClock ⇒ CLK_E

Functions with no stack information