fix bumblebee irq entry aligment, fix eclic

arch/risc-v/bumblebee/gcc/riscv_port_c.c

@@ -75,13 +75,13 @@ static void eclic_set_irq_level(uint32_t source, uint8_t level) {
         return ;
     }
 
-    uint8_t intctrl_val = eclic_get_intctrl(CLIC_INT_TMR);
+    uint8_t intctrl_val = eclic_get_intctrl(source);
 
     intctrl_val <<= nlbits;
     intctrl_val >>= nlbits;
     intctrl_val  |= (level << (8- nlbits));
 
-    eclic_set_intctrl(CLIC_INT_TMR, intctrl_val);
+    eclic_set_intctrl(source, intctrl_val);
 }
 
 static void eclic_set_irq_priority(uint32_t source, uint8_t priority) {
@@ -98,29 +98,34 @@ static void eclic_set_irq_priority(uint32_t source, uint8_t priority) {
     pad         >>= cicbits;
 
 
-    uint8_t intctrl_val = eclic_get_intctrl(CLIC_INT_TMR);
+    uint8_t intctrl_val = eclic_get_intctrl(source);
 
     intctrl_val >>= (8 - nlbits);
     intctrl_val <<= (8 - nlbits);
     intctrl_val  |= (priority << (8 - cicbits));
     intctrl_val  |= pad;
 
-    eclic_set_intctrl(CLIC_INT_TMR, intctrl_val);
+    eclic_set_intctrl(source, intctrl_val);
 }
 
-void rv32_exception_entry();
+#define USE_DEFAULT_IRQ_ENTRY    1
+
 __PORT__ void port_cpu_init() {
 
-    __ASM__ __VOLATILE__("csrw mtvec, %0"::"r"(rv32_exception_entry));
+    void rv32_exception_entry();
+    uint32_t entry = (uint32_t) rv32_exception_entry;
+
+    // 0x03 means use eclic
+    __ASM__ __VOLATILE__("csrw mtvec, %0"::"r"(entry | 0x03));
 
     // MTVT2: 0x7EC
+    // set mtvt2.MTVT2EN = 0 needs to clear bit 0
     // use mtvec as entry of irq and other trap
     __ASM__ __VOLATILE__("csrc 0x7EC, 0x1");
 
     eclic_enable_interrupt(CLIC_INT_TMR);
 
     eclic_set_irq_level(CLIC_INT_TMR, 0);
-
 }
 
 __PORT__ void port_systick_priority_set(uint32_t priority) {
@@ -129,7 +134,7 @@ __PORT__ void port_systick_priority_set(uint32_t priority) {
 
 
 __PORT__ void *port_get_irq_vector_table() {
-    void *base = 0;
+    unsigned int *base = 0;
 
     // MTVT:  0x307
     __ASM__ __VOLATILE__("csrr %0, 0x307":"=r"(base));

arch/risc-v/bumblebee/gcc/riscv_port_s.S

@@ -15,15 +15,23 @@
  * within TencentOS.
  *---------------------------------------------------------------------------*/
 
-.global eclic_mtip_handler
+//.global eclic_mtip_handler
+//.section .text
+#if 0
 .global irq_entry
 .global trap_entry
 
 .align 2
 irq_entry:
+	nop
+	nop
+	nop
+	nop
+	j rv32_exception_entry
     j irq_entry
 
 .align 2
 trap_entry:
     j trap_entry
 
+#endif

arch/risc-v/common/tos_cpu.c

@@ -159,15 +159,21 @@ void cpu_trap_entry(cpu_data_t cause, cpu_context_t *regs)
     }
 }
 
+void eclic_mtip_handler();
 void cpu_irq_entry(cpu_data_t irq)
 {
-    void (*irq_handler)();
+    typedef void (*irq_handler_t)();
 
-    irq_handler = *((void (**)())(port_get_irq_vector_table() + irq*sizeof(cpu_addr_t)));
-    if((*irq_handler) == 0) {
+
+    irq_handler_t *irq_handler_base = port_get_irq_vector_table();
+
+    irq_handler_t irq_handler = irq_handler_base[irq];
+
+    if(irq_handler == 0) {
         return;
     }
 
+
     (*irq_handler)();
 }
 
@@ -175,27 +181,27 @@ __API__ uint32_t tos_cpu_clz(uint32_t val)
 {
     uint32_t nbr_lead_zeros = 0;
 
-    if (!(val & 0XFFFF0000)) {
+    if (!(val & 0xFFFF0000)) {
         val <<= 16;
         nbr_lead_zeros += 16;
     }
 
-    if (!(val & 0XFF000000)) {
+    if (!(val & 0xFF000000)) {
         val <<= 8;
         nbr_lead_zeros += 8;
     }
 
-    if (!(val & 0XF0000000)) {
+    if (!(val & 0xF0000000)) {
         val <<= 4;
         nbr_lead_zeros += 4;
     }
 
-    if (!(val & 0XC0000000)) {
+    if (!(val & 0xC0000000)) {
         val <<= 2;
         nbr_lead_zeros += 2;
     }
 
-    if (!(val & 0X80000000)) {
+    if (!(val & 0x80000000)) {
         nbr_lead_zeros += 1;
     }
 

arch/risc-v/rv32i/gcc/port_s.S

@@ -267,7 +267,7 @@ restore_context:
     mret
 
 
-.align 2
+.align 6
 .global rv32_exception_entry
 rv32_exception_entry:
     addi   sp,  sp, -128