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fix bumblebee irq entry aligment, fix eclic

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This commit is contained in:
acevest
2020-01-09 20:18:18 +08:00
parent 5920066f21
commit bce32faac2
12 changed files with 113 additions and 41 deletions
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21
arch/risc-v/bumblebee/gcc/riscv_port_c.c
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@@ -75,13 +75,13 @@ static void eclic_set_irq_level(uint32_t source, uint8_t level) {
return ;
}
uint8_t intctrl_val = eclic_get_intctrl(CLIC_INT_TMR);
uint8_t intctrl_val = eclic_get_intctrl(source);
intctrl_val <<= nlbits;
intctrl_val >>= nlbits;
intctrl_val |= (level << (8- nlbits));
eclic_set_intctrl(CLIC_INT_TMR, intctrl_val);
eclic_set_intctrl(source, intctrl_val);
}
static void eclic_set_irq_priority(uint32_t source, uint8_t priority) {
@@ -98,29 +98,34 @@ static void eclic_set_irq_priority(uint32_t source, uint8_t priority) {
pad >>= cicbits;
uint8_t intctrl_val = eclic_get_intctrl(CLIC_INT_TMR);
uint8_t intctrl_val = eclic_get_intctrl(source);
intctrl_val >>= (8 - nlbits);
intctrl_val <<= (8 - nlbits);
intctrl_val |= (priority << (8 - cicbits));
intctrl_val |= pad;
eclic_set_intctrl(CLIC_INT_TMR, intctrl_val);
eclic_set_intctrl(source, intctrl_val);
}
void rv32_exception_entry();
#define USE_DEFAULT_IRQ_ENTRY 1
__PORT__ void port_cpu_init() {
__ASM__ __VOLATILE__("csrw mtvec, %0"::"r"(rv32_exception_entry));
void rv32_exception_entry();
uint32_t entry = (uint32_t) rv32_exception_entry;
// 0x03 means use eclic
__ASM__ __VOLATILE__("csrw mtvec, %0"::"r"(entry | 0x03));
// MTVT2: 0x7EC
// set mtvt2.MTVT2EN = 0 needs to clear bit 0
// use mtvec as entry of irq and other trap
__ASM__ __VOLATILE__("csrc 0x7EC, 0x1");
eclic_enable_interrupt(CLIC_INT_TMR);
eclic_set_irq_level(CLIC_INT_TMR, 0);
}
__PORT__ void port_systick_priority_set(uint32_t priority) {
@@ -129,7 +134,7 @@ __PORT__ void port_systick_priority_set(uint32_t priority) {
__PORT__ void *port_get_irq_vector_table() {
void *base = 0;
unsigned int *base = 0;
// MTVT: 0x307
__ASM__ __VOLATILE__("csrr %0, 0x307":"=r"(base));

10
arch/risc-v/bumblebee/gcc/riscv_port_s.S
View File

@@ -15,15 +15,23 @@
* within TencentOS.
*---------------------------------------------------------------------------*/
.global eclic_mtip_handler
//.global eclic_mtip_handler
//.section .text
#if 0
.global irq_entry
.global trap_entry
.align 2
irq_entry:
nop
nop
nop
nop
j rv32_exception_entry
j irq_entry
.align 2
trap_entry:
j trap_entry
#endif