add bh1750 demo on tos_evb_aiot board
This commit is contained in:
mculover666
@@ -0,0 +1,145 @@
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#include "bh1750_i2c_drv.h"
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#if defined(USE_ST_HAL)
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static void bh1750_i2c_init(void)
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{
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// it will be called in main.
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// MX_I2C1_Init();
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}
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static int bh1750_send_cmd(uint8_t cmd)
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{
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return HAL_I2C_Master_Transmit(&BH1750_I2C_HANDLE, BH1750_ADDR_WRITE, &cmd, 1, 0xFFFF);
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}
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static int bh1750_read_dat(uint8_t* dat)
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{
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return HAL_I2C_Master_Receive(&BH1750_I2C_HANDLE, BH1750_ADDR_READ, dat, 2, 0xFFFF);
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}
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#elif defined(USE_NXP_FSL)
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static void bh1750_i2c_init(void)
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{
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lpi2c_master_config_t masterConfig;
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/*Clock setting for LPI2C */
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CLOCK_SetMux(kCLOCK_Lpi2cMux, LPI2C_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER);
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/*
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* masterConfig.debugEnable = false;
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* masterConfig.ignoreAck = false;
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* masterConfig.pinConfig = kLPI2C_2PinOpenDrain;
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* masterConfig.baudRate_Hz = 100000U;
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* masterConfig.busIdleTimeout_ns = 0;
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* masterConfig.pinLowTimeout_ns = 0;
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* masterConfig.sdaGlitchFilterWidth_ns = 0;
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* masterConfig.sclGlitchFilterWidth_ns = 0;
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*/
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LPI2C_MasterGetDefaultConfig(&masterConfig);
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/* Change the default baudrate configuration */
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masterConfig.baudRate_Hz = LPI2C_BAUDRATE;
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/* Initialize the LPI2C master peripheral */
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LPI2C_MasterInit(BH1750_I2C_MASTER, &masterConfig, LPI2C_MASTER_CLOCK_FREQUENCY);
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}
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static int bh1750_send_cmd(uint8_t cmd)
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{
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status_t reVal = kStatus_Fail;
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/* Send master blocking data to slave */
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if (kStatus_Success != LPI2C_MasterStart(BH1750_I2C_MASTER, BH1750_DEVICE_ADDR_7BIT, kLPI2C_Write))
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{
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return -1;
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}
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/* Check communicate with slave successful or not */
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if (LPI2C_MasterGetStatusFlags(BH1750_I2C_MASTER) & kLPI2C_MasterNackDetectFlag)
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{
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return kStatus_LPI2C_Nak;
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}
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reVal = LPI2C_MasterSend(BH1750_I2C_MASTER, (uint8_t *)&cmd, 1);
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if (reVal != kStatus_Success)
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{
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if (reVal == kStatus_LPI2C_Nak)
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{
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LPI2C_MasterStop(BH1750_I2C_MASTER);
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}
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return -1;
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}
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reVal = LPI2C_MasterStop(BH1750_I2C_MASTER);
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if (reVal != kStatus_Success)
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{
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return -1;
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}
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return 0;
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}
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static int bh1750_read_dat(uint8_t* dat)
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{
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status_t reVal = kStatus_Fail;
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if (kStatus_Success != LPI2C_MasterStart(BH1750_I2C_MASTER, BH1750_DEVICE_ADDR_7BIT, kLPI2C_Read)) {
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return -1;
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}
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reVal = LPI2C_MasterReceive(BH1750_I2C_MASTER, dat, 2);
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if (reVal != kStatus_Success)
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{
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if (reVal == kStatus_LPI2C_Nak)
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{
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LPI2C_MasterStop(BH1750_I2C_MASTER);
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}
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return -1;
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}
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reVal = LPI2C_MasterStop(BH1750_I2C_MASTER);
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if (reVal != kStatus_Success)
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{
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return -1;
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}
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return 0;
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}
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#endif /* USE_ST_HAL or USE_NXP_FSL */
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static uint16_t bh1750_dat2lux(uint8_t* dat)
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{
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uint16_t lux = 0;
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lux = dat[0];
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lux <<= 8;
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lux += dat[1];
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lux = (int)(lux / 1.2);
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return lux;
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}
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int bh1750_init(void)
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{
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bh1750_i2c_init();
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return 0;
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}
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int bh1750_start(bh1750_mode_t mode)
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{
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return bh1750_send_cmd(mode);
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}
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int bh1750_read_lux(uint16_t *lux)
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{
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uint8_t dat[2] = {0};
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if (bh1750_read_dat(dat) != 0) {
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return -1;
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}
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*lux = bh1750_dat2lux(dat);
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return 0;
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}
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@@ -0,0 +1,50 @@
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#ifndef _BH1750_I2C_DRV_H_
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#define _BH1750_I2C_DRV_H_
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//#define USE_ST_HAL
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#define USE_NXP_FSL
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#if defined(USE_ST_HAL)
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#include "stm32l4xx_hal.h"
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// address(7 bit) + read or write(1 bit)
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#define BH1750_ADDR_WRITE 0x46
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#define BH1750_ADDR_READ 0x47
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#define BH1750_I2C_HANDLE hi2c1
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#elif defined(USE_NXP_FSL)
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#include "fsl_lpi2c.h"
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#define BH1750_DEVICE_ADDR_7BIT 0x23
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#define BH1750_I2C_MASTER LPI2C1
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/* Select USB1 PLL (480 MHz) as master lpi2c clock source */
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#define LPI2C_CLOCK_SOURCE_SELECT (0U)
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/* Clock divider for master lpi2c clock source */
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#define LPI2C_CLOCK_SOURCE_DIVIDER (5U)
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/* Get frequency of lpi2c clock */
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#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U))
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#define LPI2C_MASTER_CLOCK_FREQUENCY LPI2C_CLOCK_FREQUENCY
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#define LPI2C_BAUDRATE 100000U
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#endif /* USE_ST_HAL or USE_NXP_FSL */
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typedef enum
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{
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POWER_OFF_CMD = 0x00, // Power off
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POWER_ON_CMD = 0x01, // Power on
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RESET_REGISTER = 0x07, // Reset digital register
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CONT_H_MODE = 0x10, // Continuous high resolution mode, measurement time 120ms
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CONT_H_MODE2 = 0x11, // Continuous high resolution mode2, measurement time 120ms
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CONT_L_MODE = 0x13, // Continuous low resolution mode, measurement time 16ms
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ONCE_H_MODE = 0x20, // Once high resolution mode, measurement time 120ms
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ONCE_H_MODE2 = 0x21, // Once high resolution mode2, measurement time 120ms
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ONCE_L_MODE = 0x23 // Once low resolution mode2, measurement time 120ms
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} bh1750_mode_t;
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int bh1750_init(void);
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int bh1750_start(bh1750_mode_t mode);
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int bh1750_read_lux(uint16_t *lux);
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#endif
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@@ -0,0 +1,111 @@
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#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
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/*
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** ###################################################################
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** Processors: MIMXRT1062CVJ5A
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** MIMXRT1062CVL5A
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** MIMXRT1062DVJ6A
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** MIMXRT1062DVL6A
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
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** Version: rev. 0.1, 2017-01-10
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** Build: b191015
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**
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** Abstract:
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** Linker file for the Keil ARM C/C++ Compiler
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2019 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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#if (defined(__ram_vector_table__))
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#define __ram_vector_table_size__ 0x00000400
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#else
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#define __ram_vector_table_size__ 0x00000000
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#endif
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#define m_flash_config_start 0x60000000
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#define m_flash_config_size 0x00001000
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#define m_ivt_start 0x60001000
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#define m_ivt_size 0x00001000
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#define m_interrupts_start 0x60002000
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#define m_interrupts_size 0x00000400
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#define m_text_start 0x60002400
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#define m_text_size 0x007FDC00
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#define m_interrupts_ram_start 0x20000000
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#define m_interrupts_ram_size __ram_vector_table_size__
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#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
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#define m_data_size (0x00020000 - m_interrupts_ram_size)
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#define m_data2_start 0x20200000
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#define m_data2_size 0x000C0000
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/* Sizes */
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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#else
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#define Stack_Size 0x0400
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#endif
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#if (defined(__heap_size__))
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#define Heap_Size __heap_size__
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#else
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#define Heap_Size 0x0400
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#endif
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
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RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
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* (.boot_hdr.conf, +FIRST)
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}
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RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
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* (.boot_hdr.ivt, +FIRST)
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* (.boot_hdr.boot_data)
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* (.boot_hdr.dcd_data)
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}
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#else
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LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
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#endif
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VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
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* (.isr_vector,+FIRST)
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}
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ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
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* (InRoot$$Sections)
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.ANY (+RO)
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}
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#if (defined(__ram_vector_table__))
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VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
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}
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#else
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VECTOR_RAM m_interrupts_start EMPTY 0 {
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}
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#endif
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RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
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.ANY (+RW +ZI)
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* (RamFunction)
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* (NonCacheable.init)
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* (*NonCacheable)
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}
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ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
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}
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ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
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}
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RW_m_ncache m_data2_start EMPTY 0 {
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}
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RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
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}
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}
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@@ -0,0 +1,77 @@
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#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
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/*
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||||||
|
** ###################################################################
|
||||||
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** Processors: MIMXRT1062CVJ5A
|
||||||
|
** MIMXRT1062CVL5A
|
||||||
|
** MIMXRT1062DVJ6A
|
||||||
|
** MIMXRT1062DVL6A
|
||||||
|
**
|
||||||
|
** Compiler: Keil ARM C/C++ Compiler
|
||||||
|
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
|
||||||
|
** Version: rev. 0.1, 2017-01-10
|
||||||
|
** Build: b191015
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Linker file for the Keil ARM C/C++ Compiler
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2019 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** ###################################################################
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*/
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#define m_interrupts_start 0x00000000
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#define m_interrupts_size 0x00000400
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#define m_text_start 0x00000400
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#define m_text_size 0x0001FC00
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#define m_data_start 0x20000000
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#define m_data_size 0x00020000
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#define m_data2_start 0x20200000
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#define m_data2_size 0x000C0000
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|
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||||||
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/* Sizes */
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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||||||
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#else
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||||||
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#define Stack_Size 0x0400
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#endif
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||||||
|
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||||||
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#if (defined(__heap_size__))
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||||||
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#define Heap_Size __heap_size__
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||||||
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#else
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||||||
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#define Heap_Size 0x0400
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||||||
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#endif
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||||||
|
|
||||||
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LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||||
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VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||||
|
* (.isr_vector,+FIRST)
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||||||
|
}
|
||||||
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ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||||
|
* (InRoot$$Sections)
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||||||
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.ANY (+RO)
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||||||
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}
|
||||||
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VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||||
|
}
|
||||||
|
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
* (NonCacheable.init)
|
||||||
|
* (*NonCacheable)
|
||||||
|
}
|
||||||
|
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||||
|
}
|
||||||
|
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||||
|
}
|
||||||
|
RW_m_ncache m_data2_start EMPTY 0 {
|
||||||
|
}
|
||||||
|
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,89 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018-2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
FUNC void _loadDcdcTrim(void)
|
||||||
|
{
|
||||||
|
unsigned int dcdc_trim_loaded;
|
||||||
|
unsigned long ocotp_base;
|
||||||
|
unsigned long ocotp_fuse_bank0_base;
|
||||||
|
unsigned long dcdc_base;
|
||||||
|
unsigned long reg;
|
||||||
|
unsigned long trim_value;
|
||||||
|
unsigned int index;
|
||||||
|
|
||||||
|
ocotp_base = 0x401F4000;
|
||||||
|
ocotp_fuse_bank0_base = ocotp_base + 0x400;
|
||||||
|
dcdc_base = 0x40080000;
|
||||||
|
|
||||||
|
dcdc_trim_loaded = 0;
|
||||||
|
|
||||||
|
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
|
||||||
|
if (reg & (1<<10))
|
||||||
|
{
|
||||||
|
// DCDC: REG0->VBG_TRM
|
||||||
|
trim_value = (reg & (0x1F << 11)) >> 11;
|
||||||
|
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
|
||||||
|
_WDWORD(dcdc_base + 0x4, reg);
|
||||||
|
dcdc_trim_loaded = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
|
||||||
|
if (reg & (1<<30))
|
||||||
|
{
|
||||||
|
index = (reg & (3 << 28)) >> 28;
|
||||||
|
if (index < 4)
|
||||||
|
{
|
||||||
|
// DCDC: REG3->TRG
|
||||||
|
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
|
||||||
|
_WDWORD(dcdc_base + 0xC, reg);
|
||||||
|
dcdc_trim_loaded = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dcdc_trim_loaded)
|
||||||
|
{
|
||||||
|
// delay about 400us till dcdc is stable.
|
||||||
|
_Sleep_(1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
FUNC void restoreFlexRAM(void)
|
||||||
|
{
|
||||||
|
unsigned int value;
|
||||||
|
unsigned int base;
|
||||||
|
|
||||||
|
base = 0x400AC000;
|
||||||
|
|
||||||
|
value = _RDWORD(base + 0x44);
|
||||||
|
value &= ~(0xFFFFFFFF);
|
||||||
|
value |= 0x55AFFA55;
|
||||||
|
_WDWORD(base + 0x44, value);
|
||||||
|
|
||||||
|
value = _RDWORD(base + 0x40);
|
||||||
|
value |= (1 << 2);
|
||||||
|
_WDWORD(base + 0x40, value);
|
||||||
|
}
|
||||||
|
|
||||||
|
FUNC void Setup (void) {
|
||||||
|
_loadDcdcTrim();
|
||||||
|
SP = _RDWORD(0x60002000); // Setup Stack Pointer
|
||||||
|
PC = _RDWORD(0x60002004); // Setup Program Counter
|
||||||
|
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
|
||||||
|
}
|
||||||
|
|
||||||
|
FUNC void OnResetExec (void) { // executes upon software RESET
|
||||||
|
restoreFlexRAM();
|
||||||
|
Setup(); // Setup for Running
|
||||||
|
}
|
||||||
|
|
||||||
|
restoreFlexRAM();
|
||||||
|
|
||||||
|
LOAD %L INCREMENTAL // Download
|
||||||
|
|
||||||
|
Setup(); // Setup for Running
|
||||||
|
|
||||||
|
// g, main
|
||||||
@@ -0,0 +1,89 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018-2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
FUNC void _loadDcdcTrim(void)
|
||||||
|
{
|
||||||
|
unsigned int dcdc_trim_loaded;
|
||||||
|
unsigned long ocotp_base;
|
||||||
|
unsigned long ocotp_fuse_bank0_base;
|
||||||
|
unsigned long dcdc_base;
|
||||||
|
unsigned long reg;
|
||||||
|
unsigned long trim_value;
|
||||||
|
unsigned int index;
|
||||||
|
|
||||||
|
ocotp_base = 0x401F4000;
|
||||||
|
ocotp_fuse_bank0_base = ocotp_base + 0x400;
|
||||||
|
dcdc_base = 0x40080000;
|
||||||
|
|
||||||
|
dcdc_trim_loaded = 0;
|
||||||
|
|
||||||
|
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
|
||||||
|
if (reg & (1<<10))
|
||||||
|
{
|
||||||
|
// DCDC: REG0->VBG_TRM
|
||||||
|
trim_value = (reg & (0x1F << 11)) >> 11;
|
||||||
|
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
|
||||||
|
_WDWORD(dcdc_base + 0x4, reg);
|
||||||
|
dcdc_trim_loaded = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
|
||||||
|
if (reg & (1<<30))
|
||||||
|
{
|
||||||
|
index = (reg & (3 << 28)) >> 28;
|
||||||
|
if (index < 4)
|
||||||
|
{
|
||||||
|
// DCDC: REG3->TRG
|
||||||
|
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
|
||||||
|
_WDWORD(dcdc_base + 0xC, reg);
|
||||||
|
dcdc_trim_loaded = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dcdc_trim_loaded)
|
||||||
|
{
|
||||||
|
// delay about 400us till dcdc is stable.
|
||||||
|
_Sleep_(1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
FUNC void restoreFlexRAM(void)
|
||||||
|
{
|
||||||
|
unsigned int value;
|
||||||
|
unsigned int base;
|
||||||
|
|
||||||
|
base = 0x400AC000;
|
||||||
|
|
||||||
|
value = _RDWORD(base + 0x44);
|
||||||
|
value &= ~(0xFFFFFFFF);
|
||||||
|
value |= 0x55AFFA55;
|
||||||
|
_WDWORD(base + 0x44, value);
|
||||||
|
|
||||||
|
value = _RDWORD(base + 0x40);
|
||||||
|
value |= (1 << 2);
|
||||||
|
_WDWORD(base + 0x40, value);
|
||||||
|
}
|
||||||
|
|
||||||
|
FUNC void Setup (void) {
|
||||||
|
_loadDcdcTrim();
|
||||||
|
SP = _RDWORD(0x00000000); // Setup Stack Pointer
|
||||||
|
PC = _RDWORD(0x00000004); // Setup Program Counter
|
||||||
|
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
|
||||||
|
}
|
||||||
|
|
||||||
|
FUNC void OnResetExec (void) { // executes upon software RESET
|
||||||
|
restoreFlexRAM();
|
||||||
|
Setup(); // Setup for Running
|
||||||
|
}
|
||||||
|
|
||||||
|
restoreFlexRAM();
|
||||||
|
|
||||||
|
LOAD %L INCREMENTAL // Download
|
||||||
|
|
||||||
|
Setup(); // Setup for Running
|
||||||
|
|
||||||
|
// g, main
|
||||||
@@ -0,0 +1,389 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018-2019 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
#include "fsl_debug_console.h"
|
||||||
|
#include "board.h"
|
||||||
|
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||||
|
#include "fsl_lpi2c.h"
|
||||||
|
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||||
|
#include "fsl_iomuxc.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables
|
||||||
|
******************************************************************************/
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/* Get debug console frequency. */
|
||||||
|
uint32_t BOARD_DebugConsoleSrcFreq(void)
|
||||||
|
{
|
||||||
|
uint32_t freq;
|
||||||
|
|
||||||
|
/* To make it simple, we assume default PLL and divider settings, and the only variable
|
||||||
|
from application is use PLL3 source or OSC source */
|
||||||
|
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
|
||||||
|
{
|
||||||
|
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||||
|
}
|
||||||
|
|
||||||
|
return freq;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize debug console. */
|
||||||
|
void BOARD_InitDebugConsole(void)
|
||||||
|
{
|
||||||
|
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
|
||||||
|
|
||||||
|
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||||
|
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
|
||||||
|
{
|
||||||
|
lpi2c_master_config_t lpi2cConfig = {0};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* lpi2cConfig.debugEnable = false;
|
||||||
|
* lpi2cConfig.ignoreAck = false;
|
||||||
|
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
|
||||||
|
* lpi2cConfig.baudRate_Hz = 100000U;
|
||||||
|
* lpi2cConfig.busIdleTimeout_ns = 0;
|
||||||
|
* lpi2cConfig.pinLowTimeout_ns = 0;
|
||||||
|
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
|
||||||
|
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
|
||||||
|
*/
|
||||||
|
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
|
||||||
|
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subAddressSize,
|
||||||
|
uint8_t *txBuff,
|
||||||
|
uint8_t txBuffSize)
|
||||||
|
{
|
||||||
|
lpi2c_master_transfer_t xfer;
|
||||||
|
|
||||||
|
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||||
|
xfer.slaveAddress = deviceAddress;
|
||||||
|
xfer.direction = kLPI2C_Write;
|
||||||
|
xfer.subaddress = subAddress;
|
||||||
|
xfer.subaddressSize = subAddressSize;
|
||||||
|
xfer.data = txBuff;
|
||||||
|
xfer.dataSize = txBuffSize;
|
||||||
|
|
||||||
|
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subAddressSize,
|
||||||
|
uint8_t *rxBuff,
|
||||||
|
uint8_t rxBuffSize)
|
||||||
|
{
|
||||||
|
lpi2c_master_transfer_t xfer;
|
||||||
|
|
||||||
|
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||||
|
xfer.slaveAddress = deviceAddress;
|
||||||
|
xfer.direction = kLPI2C_Read;
|
||||||
|
xfer.subaddress = subAddress;
|
||||||
|
xfer.subaddressSize = subAddressSize;
|
||||||
|
xfer.data = rxBuff;
|
||||||
|
xfer.dataSize = rxBuffSize;
|
||||||
|
|
||||||
|
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subAddressSize,
|
||||||
|
uint8_t *txBuff,
|
||||||
|
uint8_t txBuffSize)
|
||||||
|
{
|
||||||
|
lpi2c_master_transfer_t xfer;
|
||||||
|
|
||||||
|
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||||
|
xfer.slaveAddress = deviceAddress;
|
||||||
|
xfer.direction = kLPI2C_Write;
|
||||||
|
xfer.subaddress = subAddress;
|
||||||
|
xfer.subaddressSize = subAddressSize;
|
||||||
|
xfer.data = txBuff;
|
||||||
|
xfer.dataSize = txBuffSize;
|
||||||
|
|
||||||
|
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subAddressSize,
|
||||||
|
uint8_t *rxBuff,
|
||||||
|
uint8_t rxBuffSize)
|
||||||
|
{
|
||||||
|
status_t status;
|
||||||
|
lpi2c_master_transfer_t xfer;
|
||||||
|
|
||||||
|
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||||
|
xfer.slaveAddress = deviceAddress;
|
||||||
|
xfer.direction = kLPI2C_Write;
|
||||||
|
xfer.subaddress = subAddress;
|
||||||
|
xfer.subaddressSize = subAddressSize;
|
||||||
|
xfer.data = NULL;
|
||||||
|
xfer.dataSize = 0;
|
||||||
|
|
||||||
|
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||||
|
|
||||||
|
if (kStatus_Success == status)
|
||||||
|
{
|
||||||
|
xfer.subaddressSize = 0;
|
||||||
|
xfer.direction = kLPI2C_Read;
|
||||||
|
xfer.data = rxBuff;
|
||||||
|
xfer.dataSize = rxBuffSize;
|
||||||
|
|
||||||
|
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
void BOARD_Accel_I2C_Init(void)
|
||||||
|
{
|
||||||
|
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||||
|
{
|
||||||
|
uint8_t data = (uint8_t)txBuff;
|
||||||
|
|
||||||
|
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Accel_I2C_Receive(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||||
|
{
|
||||||
|
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
void BOARD_Codec_I2C_Init(void)
|
||||||
|
{
|
||||||
|
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Codec_I2C_Send(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||||
|
{
|
||||||
|
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||||
|
txBuffSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Codec_I2C_Receive(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||||
|
{
|
||||||
|
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
void BOARD_Camera_I2C_Init(void)
|
||||||
|
{
|
||||||
|
CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
|
||||||
|
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
|
||||||
|
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Camera_I2C_Send(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||||
|
{
|
||||||
|
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||||
|
txBuffSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Camera_I2C_Receive(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||||
|
{
|
||||||
|
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||||
|
rxBuffSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Camera_I2C_SendSCCB(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||||
|
{
|
||||||
|
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||||
|
txBuffSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||||
|
{
|
||||||
|
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||||
|
rxBuffSize);
|
||||||
|
}
|
||||||
|
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||||
|
|
||||||
|
/* MPU configuration. */
|
||||||
|
void BOARD_ConfigMPU(void)
|
||||||
|
{
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||||
|
extern uint32_t Image$$RW_m_ncache$$Base[];
|
||||||
|
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
|
||||||
|
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
|
||||||
|
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
|
||||||
|
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
|
||||||
|
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
|
||||||
|
0 :
|
||||||
|
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
|
||||||
|
#elif defined(__MCUXPRESSO)
|
||||||
|
extern uint32_t __base_NCACHE_REGION;
|
||||||
|
extern uint32_t __top_NCACHE_REGION;
|
||||||
|
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
|
||||||
|
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
|
||||||
|
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||||
|
extern uint32_t __NCACHE_REGION_START[];
|
||||||
|
extern uint32_t __NCACHE_REGION_SIZE[];
|
||||||
|
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
|
||||||
|
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
|
||||||
|
#endif
|
||||||
|
volatile uint32_t i = 0;
|
||||||
|
|
||||||
|
/* Disable I cache and D cache */
|
||||||
|
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
||||||
|
{
|
||||||
|
SCB_DisableICache();
|
||||||
|
}
|
||||||
|
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
||||||
|
{
|
||||||
|
SCB_DisableDCache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Disable MPU */
|
||||||
|
ARM_MPU_Disable();
|
||||||
|
|
||||||
|
/* MPU configure:
|
||||||
|
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
||||||
|
* SubRegionDisable, Size)
|
||||||
|
* API in mpu_armv7.h.
|
||||||
|
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
||||||
|
* disabled.
|
||||||
|
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
||||||
|
* Privileged mode.
|
||||||
|
* Use MACROS defined in mpu_armv7.h:
|
||||||
|
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||||
|
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||||
|
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
||||||
|
* 0 x 0 0 Strongly Ordered shareable
|
||||||
|
* 0 x 0 1 Device shareable
|
||||||
|
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||||
|
* through no write allocate
|
||||||
|
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||||
|
* back no write allocate
|
||||||
|
* 0 1 1 0 Normal shareable Outer and inner write
|
||||||
|
* through no write allocate
|
||||||
|
* 0 1 1 1 Normal shareable Outer and inner write
|
||||||
|
* back no write allocate
|
||||||
|
* 1 0 0 0 Normal not shareable outer and inner
|
||||||
|
* noncache
|
||||||
|
* 1 1 0 0 Normal shareable outer and inner
|
||||||
|
* noncache
|
||||||
|
* 1 0 1 1 Normal not shareable outer and inner write
|
||||||
|
* back write/read acllocate
|
||||||
|
* 1 1 1 1 Normal shareable outer and inner write
|
||||||
|
* back write/read acllocate
|
||||||
|
* 2 x 0 0 Device not shareable
|
||||||
|
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
||||||
|
* policy.
|
||||||
|
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||||
|
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||||
|
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
||||||
|
* mpu_armv7.h.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Add default region to deny access to whole address space to workaround speculative prefetch.
|
||||||
|
* Refer to Arm errata 1013783-B for more details.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/* Region 0 setting: Instruction access disabled, No data access permission. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
|
||||||
|
|
||||||
|
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||||
|
|
||||||
|
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||||
|
|
||||||
|
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||||
|
/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||||
|
|
||||||
|
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||||
|
|
||||||
|
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||||
|
|
||||||
|
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
|
||||||
|
|
||||||
|
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||||
|
|
||||||
|
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||||
|
|
||||||
|
while ((size >> i) > 0x1U)
|
||||||
|
{
|
||||||
|
i++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i != 0)
|
||||||
|
{
|
||||||
|
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||||
|
assert(!(nonCacheStart % size));
|
||||||
|
assert(size == (uint32_t)(1 << i));
|
||||||
|
assert(i >= 5);
|
||||||
|
|
||||||
|
/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
|
||||||
|
|
||||||
|
/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
|
||||||
|
|
||||||
|
/* Enable MPU */
|
||||||
|
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||||
|
|
||||||
|
/* Enable I cache and D cache */
|
||||||
|
SCB_EnableDCache();
|
||||||
|
SCB_EnableICache();
|
||||||
|
}
|
||||||
@@ -0,0 +1,220 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018-2019 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BOARD_H_
|
||||||
|
#define _BOARD_H_
|
||||||
|
|
||||||
|
#include "clock_config.h"
|
||||||
|
#include "fsl_common.h"
|
||||||
|
#include "fsl_gpio.h"
|
||||||
|
#include "fsl_clock.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/*! @brief The board name */
|
||||||
|
#define BOARD_NAME "MIMXRT1060-EVK"
|
||||||
|
|
||||||
|
/* The UART to use for debug messages. */
|
||||||
|
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||||
|
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
|
||||||
|
#define BOARD_DEBUG_UART_INSTANCE 1U
|
||||||
|
|
||||||
|
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||||
|
|
||||||
|
#define BOARD_UART_IRQ LPUART1_IRQn
|
||||||
|
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
|
||||||
|
|
||||||
|
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||||
|
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
|
||||||
|
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||||
|
|
||||||
|
/*! @brief The USER_LED used for board */
|
||||||
|
#define LOGIC_LED_ON (0U)
|
||||||
|
#define LOGIC_LED_OFF (1U)
|
||||||
|
#ifndef BOARD_USER_LED_GPIO
|
||||||
|
#define BOARD_USER_LED_GPIO GPIO1
|
||||||
|
#endif
|
||||||
|
#ifndef BOARD_USER_LED_GPIO_PIN
|
||||||
|
#define BOARD_USER_LED_GPIO_PIN (9U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define USER_LED_INIT(output) \
|
||||||
|
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
|
||||||
|
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
|
||||||
|
#define USER_LED_ON() \
|
||||||
|
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
|
||||||
|
#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
|
||||||
|
#define USER_LED_TOGGLE() \
|
||||||
|
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
|
||||||
|
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
|
||||||
|
|
||||||
|
/*! @brief Define the port interrupt number for the board switches */
|
||||||
|
#ifndef BOARD_USER_BUTTON_GPIO
|
||||||
|
#define BOARD_USER_BUTTON_GPIO GPIO5
|
||||||
|
#endif
|
||||||
|
#ifndef BOARD_USER_BUTTON_GPIO_PIN
|
||||||
|
#define BOARD_USER_BUTTON_GPIO_PIN (0U)
|
||||||
|
#endif
|
||||||
|
#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
|
||||||
|
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
|
||||||
|
#define BOARD_USER_BUTTON_NAME "SW8"
|
||||||
|
|
||||||
|
/*! @brief The board flash size */
|
||||||
|
#define BOARD_FLASH_SIZE (0x800000U)
|
||||||
|
|
||||||
|
/*! @brief The ENET PHY address. */
|
||||||
|
#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
|
||||||
|
|
||||||
|
/* USB PHY condfiguration */
|
||||||
|
#define BOARD_USB_PHY_D_CAL (0x0CU)
|
||||||
|
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
|
||||||
|
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
|
||||||
|
|
||||||
|
#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
|
||||||
|
#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
|
||||||
|
#define BOARD_ARDUINO_I2C_INDEX (1)
|
||||||
|
|
||||||
|
/*! @brief The WIFI-QCA shield pin. */
|
||||||
|
#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||||
|
#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
|
||||||
|
#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
|
||||||
|
#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
|
||||||
|
#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
|
||||||
|
#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
|
||||||
|
#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
|
||||||
|
|
||||||
|
#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||||
|
#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
|
||||||
|
#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
|
||||||
|
#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
|
||||||
|
#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
|
||||||
|
#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
|
||||||
|
#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
|
||||||
|
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
|
||||||
|
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
|
||||||
|
#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
|
||||||
|
|
||||||
|
/* @Brief Board accelerator sensor configuration */
|
||||||
|
#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
|
||||||
|
/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
|
||||||
|
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||||
|
/* Clock divider for LPI2C clock source */
|
||||||
|
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||||
|
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||||
|
|
||||||
|
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
|
||||||
|
#define BOARD_CODEC_I2C_INSTANCE 1U
|
||||||
|
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||||
|
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||||
|
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
|
||||||
|
|
||||||
|
/* @Brief Board CAMERA configuration */
|
||||||
|
#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
|
||||||
|
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||||
|
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
|
||||||
|
#define BOARD_CAMERA_I2C_CLOCK_FREQ \
|
||||||
|
(CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||||
|
|
||||||
|
#define BOARD_CAMERA_I2C_SCL_GPIO GPIO1
|
||||||
|
#define BOARD_CAMERA_I2C_SCL_PIN 16
|
||||||
|
#define BOARD_CAMERA_I2C_SDA_GPIO GPIO1
|
||||||
|
#define BOARD_CAMERA_I2C_SDA_PIN 17
|
||||||
|
#define BOARD_CAMERA_PWDN_GPIO GPIO1
|
||||||
|
#define BOARD_CAMERA_PWDN_PIN 4
|
||||||
|
|
||||||
|
/* @Brief Board Bluetooth HCI UART configuration */
|
||||||
|
#define BOARD_BT_UART_BASEADDR LPUART3
|
||||||
|
#define BOARD_BT_UART_INSTANCE 3
|
||||||
|
#define BOARD_BT_UART_BAUDRATE 3000000
|
||||||
|
#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||||
|
#define BOARD_BT_UART_IRQ LPUART3_IRQn
|
||||||
|
#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
|
||||||
|
|
||||||
|
/*! @brief board has sdcard */
|
||||||
|
#define BOARD_HAS_SDCARD (1U)
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
uint32_t BOARD_DebugConsoleSrcFreq(void);
|
||||||
|
|
||||||
|
void BOARD_InitDebugConsole(void);
|
||||||
|
|
||||||
|
void BOARD_ConfigMPU(void);
|
||||||
|
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||||
|
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
|
||||||
|
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subaddressSize,
|
||||||
|
uint8_t *txBuff,
|
||||||
|
uint8_t txBuffSize);
|
||||||
|
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subaddressSize,
|
||||||
|
uint8_t *rxBuff,
|
||||||
|
uint8_t rxBuffSize);
|
||||||
|
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subaddressSize,
|
||||||
|
uint8_t *txBuff,
|
||||||
|
uint8_t txBuffSize);
|
||||||
|
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||||
|
uint8_t deviceAddress,
|
||||||
|
uint32_t subAddress,
|
||||||
|
uint8_t subaddressSize,
|
||||||
|
uint8_t *rxBuff,
|
||||||
|
uint8_t rxBuffSize);
|
||||||
|
void BOARD_Accel_I2C_Init(void);
|
||||||
|
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||||
|
status_t BOARD_Accel_I2C_Receive(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||||
|
void BOARD_Codec_I2C_Init(void);
|
||||||
|
status_t BOARD_Codec_I2C_Send(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||||
|
status_t BOARD_Codec_I2C_Receive(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||||
|
void BOARD_Camera_I2C_Init(void);
|
||||||
|
status_t BOARD_Camera_I2C_Send(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||||
|
status_t BOARD_Camera_I2C_Receive(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||||
|
|
||||||
|
status_t BOARD_Camera_I2C_SendSCCB(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||||
|
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||||
|
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||||
|
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||||
|
|
||||||
|
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
|
||||||
|
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
#endif /* _BOARD_H_ */
|
||||||
@@ -0,0 +1,503 @@
|
|||||||
|
/*
|
||||||
|
* How to setup clock using clock driver functions:
|
||||||
|
*
|
||||||
|
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||||
|
*
|
||||||
|
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||||
|
*
|
||||||
|
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
|
||||||
|
*
|
||||||
|
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
|
||||||
|
*
|
||||||
|
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!GlobalInfo
|
||||||
|
product: Clocks v8.0
|
||||||
|
processor: MIMXRT1062xxxxA
|
||||||
|
package_id: MIMXRT1062DVL6A
|
||||||
|
mcu_data: ksdk2_0
|
||||||
|
processor_version: 10.0.0
|
||||||
|
board: MIMXRT1060-EVK
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||||
|
|
||||||
|
#include "clock_config.h"
|
||||||
|
#include "fsl_iomuxc.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables
|
||||||
|
******************************************************************************/
|
||||||
|
/* System clock frequency. */
|
||||||
|
extern uint32_t SystemCoreClock;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
************************ BOARD_InitBootClocks function ************************
|
||||||
|
******************************************************************************/
|
||||||
|
void BOARD_InitBootClocks(void)
|
||||||
|
{
|
||||||
|
BOARD_BootClockRUN();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
********************** Configuration BOARD_BootClockRUN ***********************
|
||||||
|
******************************************************************************/
|
||||||
|
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!Configuration
|
||||||
|
name: BOARD_BootClockRUN
|
||||||
|
called_from_default_init: true
|
||||||
|
outputs:
|
||||||
|
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
|
||||||
|
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
|
||||||
|
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||||
|
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||||
|
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||||
|
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||||
|
- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
|
||||||
|
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||||
|
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||||
|
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||||
|
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
|
||||||
|
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
|
||||||
|
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
|
||||||
|
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||||
|
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||||
|
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
|
||||||
|
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
|
||||||
|
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||||
|
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||||
|
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
|
||||||
|
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
|
||||||
|
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
|
||||||
|
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
|
||||||
|
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
|
||||||
|
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||||
|
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
|
||||||
|
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||||
|
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
|
||||||
|
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||||
|
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
|
||||||
|
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
|
||||||
|
settings:
|
||||||
|
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||||
|
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
|
||||||
|
- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
|
||||||
|
- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
|
||||||
|
- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
|
||||||
|
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
|
||||||
|
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||||
|
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||||
|
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||||
|
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
|
||||||
|
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
|
||||||
|
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||||
|
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||||
|
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||||
|
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||||
|
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||||
|
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||||
|
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||||
|
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||||
|
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||||
|
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||||
|
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||||
|
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||||
|
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
|
||||||
|
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
|
||||||
|
- {id: CCM_ANALOG.PLL5.num, value: '0'}
|
||||||
|
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
|
||||||
|
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
|
||||||
|
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
|
||||||
|
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
|
||||||
|
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||||
|
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
|
||||||
|
sources:
|
||||||
|
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
|
||||||
|
{
|
||||||
|
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
|
||||||
|
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||||
|
};
|
||||||
|
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
|
||||||
|
{
|
||||||
|
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||||
|
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||||
|
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||||
|
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||||
|
};
|
||||||
|
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
|
||||||
|
{
|
||||||
|
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||||
|
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||||
|
};
|
||||||
|
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
|
||||||
|
{
|
||||||
|
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||||
|
.postDivider = 8, /* Divider after PLL */
|
||||||
|
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||||
|
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||||
|
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||||
|
};
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
void BOARD_BootClockRUN(void)
|
||||||
|
{
|
||||||
|
/* Init RTC OSC clock frequency. */
|
||||||
|
CLOCK_SetRtcXtalFreq(32768U);
|
||||||
|
/* Enable 1MHz clock output. */
|
||||||
|
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||||
|
/* Use free 1MHz clock output. */
|
||||||
|
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||||
|
/* Set XTAL 24MHz clock frequency. */
|
||||||
|
CLOCK_SetXtalFreq(24000000U);
|
||||||
|
/* Enable XTAL 24MHz clock source. */
|
||||||
|
CLOCK_InitExternalClk(0);
|
||||||
|
/* Enable internal RC. */
|
||||||
|
CLOCK_InitRcOsc24M();
|
||||||
|
/* Switch clock source to external OSC. */
|
||||||
|
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||||
|
/* Set Oscillator ready counter value. */
|
||||||
|
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||||
|
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||||
|
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||||
|
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||||
|
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
|
||||||
|
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
|
||||||
|
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||||
|
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* Set AHB_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||||
|
/* Disable IPG clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Adc2);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Xbar3);
|
||||||
|
/* Set IPG_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||||
|
/* Set ARM_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
|
||||||
|
/* Set PERIPH_CLK2_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||||
|
/* Disable PERCLK clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Pit);
|
||||||
|
/* Set PERCLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||||
|
/* Disable USDHC1 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||||
|
/* Set USDHC1_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
|
||||||
|
/* Set Usdhc1 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||||
|
/* Disable USDHC2 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Usdhc2);
|
||||||
|
/* Set USDHC2_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
|
||||||
|
/* Set Usdhc2 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||||
|
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||||
|
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||||
|
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||||
|
#ifndef SKIP_SYSCLK_INIT
|
||||||
|
/* Disable Semc clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Semc);
|
||||||
|
/* Set SEMC_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
|
||||||
|
/* Set Semc alt clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||||
|
/* Set Semc clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||||
|
#endif
|
||||||
|
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||||
|
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||||
|
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||||
|
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||||
|
/* Disable Flexspi clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||||
|
/* Set FLEXSPI_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
|
||||||
|
/* Set Flexspi clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
|
||||||
|
#endif
|
||||||
|
/* Disable Flexspi2 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_FlexSpi2);
|
||||||
|
/* Set FLEXSPI2_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
|
||||||
|
/* Set Flexspi2 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
|
||||||
|
/* Disable CSI clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Csi);
|
||||||
|
/* Set CSI_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
|
||||||
|
/* Set Csi clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_CsiMux, 0);
|
||||||
|
/* Disable LPSPI clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpspi3);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||||||
|
/* Set LPSPI_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||||
|
/* Set Lpspi clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||||
|
/* Disable TRACE clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Trace);
|
||||||
|
/* Set TRACE_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
|
||||||
|
/* Set Trace clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_TraceMux, 0);
|
||||||
|
/* Disable SAI1 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||||
|
/* Set SAI1_CLK_PRED. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||||
|
/* Set SAI1_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||||
|
/* Set Sai1 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||||
|
/* Disable SAI2 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||||
|
/* Set SAI2_CLK_PRED. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||||
|
/* Set SAI2_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||||
|
/* Set Sai2 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||||
|
/* Disable SAI3 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||||
|
/* Set SAI3_CLK_PRED. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||||
|
/* Set SAI3_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||||
|
/* Set Sai3 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||||
|
/* Disable Lpi2c clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||||||
|
/* Set LPI2C_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||||
|
/* Set Lpi2c clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||||
|
/* Disable CAN clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Can1);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Can2);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Can3);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Can1S);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Can2S);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Can3S);
|
||||||
|
/* Set CAN_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||||||
|
/* Set Can clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||||
|
/* Disable UART clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||||||
|
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||||||
|
/* Set UART_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||||
|
/* Set Uart clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||||
|
/* Disable LCDIF clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_LcdPixel);
|
||||||
|
/* Set LCDIF_PRED. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
|
||||||
|
/* Set LCDIF_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
|
||||||
|
/* Set Lcdif pre clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
|
||||||
|
/* Disable SPDIF clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||||
|
/* Set SPDIF0_CLK_PRED. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||||
|
/* Set SPDIF0_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||||
|
/* Set Spdif clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||||
|
/* Disable Flexio1 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||||
|
/* Set FLEXIO1_CLK_PRED. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||||
|
/* Set FLEXIO1_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||||
|
/* Set Flexio1 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||||
|
/* Disable Flexio2 clock gate. */
|
||||||
|
CLOCK_DisableClock(kCLOCK_Flexio2);
|
||||||
|
/* Set FLEXIO2_CLK_PRED. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
|
||||||
|
/* Set FLEXIO2_CLK_PODF. */
|
||||||
|
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
|
||||||
|
/* Set Flexio2 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
|
||||||
|
/* Set Pll3 sw clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||||
|
/* Init ARM PLL. */
|
||||||
|
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||||
|
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||||
|
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||||
|
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||||
|
#ifndef SKIP_SYSCLK_INIT
|
||||||
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||||
|
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||||||
|
#endif
|
||||||
|
/* Init System PLL. */
|
||||||
|
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||||
|
/* Init System pfd0. */
|
||||||
|
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||||
|
/* Init System pfd1. */
|
||||||
|
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||||||
|
/* Init System pfd2. */
|
||||||
|
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
|
||||||
|
/* Init System pfd3. */
|
||||||
|
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
|
||||||
|
#endif
|
||||||
|
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||||
|
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||||
|
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||||
|
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||||
|
/* Init Usb1 PLL. */
|
||||||
|
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||||
|
/* Init Usb1 pfd0. */
|
||||||
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
|
||||||
|
/* Init Usb1 pfd1. */
|
||||||
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||||
|
/* Init Usb1 pfd2. */
|
||||||
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||||
|
/* Init Usb1 pfd3. */
|
||||||
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
|
||||||
|
/* Disable Usb1 PLL output for USBPHY1. */
|
||||||
|
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||||||
|
#endif
|
||||||
|
/* DeInit Audio PLL. */
|
||||||
|
CLOCK_DeinitAudioPll();
|
||||||
|
/* Bypass Audio PLL. */
|
||||||
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||||
|
/* Set divider for Audio PLL. */
|
||||||
|
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||||
|
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||||
|
/* Enable Audio PLL output. */
|
||||||
|
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||||
|
/* Init Video PLL. */
|
||||||
|
uint32_t pllVideo;
|
||||||
|
/* Disable Video PLL output before initial Video PLL. */
|
||||||
|
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||||
|
/* Bypass PLL first */
|
||||||
|
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
|
||||||
|
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
|
||||||
|
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
|
||||||
|
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
|
||||||
|
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
|
||||||
|
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
|
||||||
|
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||||
|
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||||
|
CCM_ANALOG->PLL_VIDEO = pllVideo;
|
||||||
|
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* Disable bypass for Video PLL. */
|
||||||
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
|
||||||
|
/* DeInit Enet PLL. */
|
||||||
|
CLOCK_DeinitEnetPll();
|
||||||
|
/* Bypass Enet PLL. */
|
||||||
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||||
|
/* Set Enet output divider. */
|
||||||
|
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||||
|
/* Enable Enet output. */
|
||||||
|
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||||
|
/* Set Enet2 output divider. */
|
||||||
|
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
|
||||||
|
/* Enable Enet2 output. */
|
||||||
|
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
|
||||||
|
/* Enable Enet25M output. */
|
||||||
|
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||||
|
/* DeInit Usb2 PLL. */
|
||||||
|
CLOCK_DeinitUsb2Pll();
|
||||||
|
/* Bypass Usb2 PLL. */
|
||||||
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
|
||||||
|
/* Enable Usb2 PLL output. */
|
||||||
|
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
|
||||||
|
/* Set preperiph clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||||
|
/* Set periph clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||||
|
/* Set periph clock2 clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||||
|
/* Set per clock source. */
|
||||||
|
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||||
|
/* Set lvds1 clock source. */
|
||||||
|
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||||
|
/* Set clock out1 divider. */
|
||||||
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||||
|
/* Set clock out1 source. */
|
||||||
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||||
|
/* Set clock out2 divider. */
|
||||||
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||||
|
/* Set clock out2 source. */
|
||||||
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
|
||||||
|
/* Set clock out1 drives clock out1. */
|
||||||
|
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||||
|
/* Disable clock out1. */
|
||||||
|
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||||
|
/* Disable clock out2. */
|
||||||
|
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||||
|
/* Set SAI1 MCLK1 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||||
|
/* Set SAI1 MCLK2 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||||
|
/* Set SAI1 MCLK3 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||||
|
/* Set SAI2 MCLK3 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||||
|
/* Set SAI3 MCLK3 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||||
|
/* Set MQS configuration. */
|
||||||
|
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||||
|
/* Set ENET Ref clock source. */
|
||||||
|
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
|
||||||
|
/* Set ENET2 Ref clock source. */
|
||||||
|
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
|
||||||
|
/* Set GPT1 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||||
|
/* Set GPT2 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||||
|
/* Set SystemCoreClock variable. */
|
||||||
|
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||||
|
}
|
||||||
|
|
||||||
@@ -0,0 +1,121 @@
|
|||||||
|
#ifndef _CLOCK_CONFIG_H_
|
||||||
|
#define _CLOCK_CONFIG_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||||
|
|
||||||
|
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||||
|
/*******************************************************************************
|
||||||
|
************************ BOARD_InitBootClocks function ************************
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief This function executes default configuration of clocks.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_InitBootClocks(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
********************** Configuration BOARD_BootClockRUN ***********************
|
||||||
|
******************************************************************************/
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||||
|
|
||||||
|
/* Clock outputs (values are in Hz): */
|
||||||
|
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
|
||||||
|
|
||||||
|
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
|
||||||
|
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||||
|
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||||
|
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief This function executes configuration of clocks.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_BootClockRUN(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
#endif /* _CLOCK_CONFIG_H_ */
|
||||||
|
|
||||||
@@ -0,0 +1,308 @@
|
|||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#include "dcd.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||||
|
__attribute__((section(".boot_hdr.dcd_data"), used))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma location = ".boot_hdr.dcd_data"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!GlobalInfo
|
||||||
|
product: DCDx v3.0
|
||||||
|
processor: MIMXRT1062xxxxA
|
||||||
|
package_id: MIMXRT1062DVL6A
|
||||||
|
mcu_data: ksdk2_0
|
||||||
|
processor_version: 10.0.0
|
||||||
|
board: MIMXRT1060-EVK
|
||||||
|
output_format: c_array
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||||
|
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
|
||||||
|
const uint8_t dcd_data[] = {
|
||||||
|
/* HEADER */
|
||||||
|
/* Tag */
|
||||||
|
0xD2,
|
||||||
|
/* Image Length */
|
||||||
|
0x04, 0x10,
|
||||||
|
/* Version */
|
||||||
|
0x41,
|
||||||
|
|
||||||
|
/* COMMANDS */
|
||||||
|
|
||||||
|
/* group: 'Imported Commands' */
|
||||||
|
/* #1.1-113, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x03, 0x8C, 0x04,
|
||||||
|
/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
|
||||||
|
0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
|
||||||
|
/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
|
||||||
|
0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
|
||||||
|
/* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
|
||||||
|
0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
|
||||||
|
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
|
||||||
|
0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
|
||||||
|
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
|
||||||
|
0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
|
||||||
|
/* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||||
|
/* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
|
||||||
|
/* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
|
||||||
|
/* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
|
||||||
|
/* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
|
||||||
|
/* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
|
||||||
|
/* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
|
||||||
|
/* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
|
||||||
|
/* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
|
||||||
|
/* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
|
||||||
|
/* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
|
||||||
|
/* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
|
||||||
|
/* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
|
||||||
|
/* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
|
||||||
|
/* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
|
||||||
|
/* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
|
||||||
|
/* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
|
||||||
|
/* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
|
||||||
|
/* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
|
||||||
|
/* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
|
||||||
|
/* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||||
|
/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||||
|
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||||
|
/* #3.1-2, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x00, 0x14, 0x04,
|
||||||
|
/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||||
|
/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||||
|
/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||||
|
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||||
|
/* #5.1-2, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x00, 0x14, 0x04,
|
||||||
|
/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||||
|
/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||||
|
/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||||
|
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||||
|
/* #7.1-3, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x00, 0x1C, 0x04,
|
||||||
|
/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
|
||||||
|
/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||||
|
/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
|
||||||
|
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
|
||||||
|
/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||||
|
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||||
|
/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
|
||||||
|
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
|
||||||
|
};
|
||||||
|
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
|
||||||
|
|
||||||
|
#else
|
||||||
|
const uint8_t dcd_data[] = {0x00};
|
||||||
|
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
|
||||||
|
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||||
@@ -0,0 +1,25 @@
|
|||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __DCD__
|
||||||
|
#define __DCD__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||||
|
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*************************************
|
||||||
|
* DCD Data
|
||||||
|
*************************************/
|
||||||
|
#define DCD_TAG_HEADER (0xD2)
|
||||||
|
#define DCD_VERSION (0x41)
|
||||||
|
#define DCD_TAG_HEADER_SHIFT (24)
|
||||||
|
#define DCD_ARRAY_SIZE 1
|
||||||
|
|
||||||
|
#endif /* __DCD__ */
|
||||||
@@ -0,0 +1,54 @@
|
|||||||
|
#include "mcu_init.h"
|
||||||
|
#include "tos_at.h"
|
||||||
|
|
||||||
|
void board_init(void)
|
||||||
|
{
|
||||||
|
/* Init board hardware. */
|
||||||
|
BOARD_ConfigMPU();
|
||||||
|
BOARD_InitPins();
|
||||||
|
BOARD_InitBootClocks();
|
||||||
|
|
||||||
|
BOARD_InitDebugConsole();
|
||||||
|
}
|
||||||
|
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
if (tos_knl_is_running()) {
|
||||||
|
tos_knl_irq_enter();
|
||||||
|
tos_tick_handler();
|
||||||
|
tos_knl_irq_leave();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* LPUART2_IRQn interrupt handler */
|
||||||
|
void LPUART2_IRQHandler(void) {
|
||||||
|
uint8_t data;
|
||||||
|
|
||||||
|
tos_knl_irq_enter();
|
||||||
|
|
||||||
|
/* If new data arrived. */
|
||||||
|
if ((kLPUART_RxDataRegFullFlag)&LPUART_GetStatusFlags(LPUART2))
|
||||||
|
{
|
||||||
|
data = LPUART_ReadByte(LPUART2);
|
||||||
|
tos_at_uart_input_byte(data);
|
||||||
|
}
|
||||||
|
|
||||||
|
tos_knl_irq_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* LPUART4_IRQn interrupt handler */
|
||||||
|
void LPUART4_IRQHandler(void) {
|
||||||
|
uint8_t data;
|
||||||
|
|
||||||
|
tos_knl_irq_enter();
|
||||||
|
|
||||||
|
/* If new data arrived. */
|
||||||
|
if ((kLPUART_RxDataRegFullFlag)&LPUART_GetStatusFlags(LPUART4))
|
||||||
|
{
|
||||||
|
data = LPUART_ReadByte(LPUART4);
|
||||||
|
tos_at_uart_input_byte(data);
|
||||||
|
}
|
||||||
|
|
||||||
|
tos_knl_irq_leave();
|
||||||
|
}
|
||||||
|
|
||||||
@@ -0,0 +1,20 @@
|
|||||||
|
#ifndef __MCU_INIT_H
|
||||||
|
#define __MCU_INIT_H
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "tos_k.h"
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
#include "fsl_debug_console.h"
|
||||||
|
#include "pin_mux.h"
|
||||||
|
#include "clock_config.h"
|
||||||
|
#include "board.h"
|
||||||
|
#include "fsl_lpuart.h"
|
||||||
|
|
||||||
|
void board_init(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif /*__ __MCU_INIT_H */
|
||||||
@@ -0,0 +1,111 @@
|
|||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!GlobalInfo
|
||||||
|
product: Pins v10.0
|
||||||
|
processor: MIMXRT1062xxxxA
|
||||||
|
package_id: MIMXRT1062DVL6A
|
||||||
|
mcu_data: ksdk2_0
|
||||||
|
processor_version: 10.0.0
|
||||||
|
board: MIMXRT1060-EVK
|
||||||
|
pin_labels:
|
||||||
|
- {pin_num: B14, pin_signal: GPIO_B1_15}
|
||||||
|
- {pin_num: M3, pin_signal: GPIO_SD_B1_02}
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
#include "fsl_iomuxc.h"
|
||||||
|
#include "fsl_gpio.h"
|
||||||
|
#include "pin_mux.h"
|
||||||
|
|
||||||
|
/* FUNCTION ************************************************************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : BOARD_InitBootPins
|
||||||
|
* Description : Calls initialization functions.
|
||||||
|
*
|
||||||
|
* END ****************************************************************************************************************/
|
||||||
|
void BOARD_InitBootPins(void) {
|
||||||
|
BOARD_InitPins();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
BOARD_InitPins:
|
||||||
|
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||||
|
- pin_list:
|
||||||
|
- {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
|
||||||
|
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||||
|
- {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
|
||||||
|
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||||
|
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||||
|
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||||
|
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||||
|
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||||
|
- {pin_num: M12, peripheral: LPUART2, signal: RX, pin_signal: GPIO_AD_B1_03}
|
||||||
|
- {pin_num: L11, peripheral: LPUART2, signal: TX, pin_signal: GPIO_AD_B1_02}
|
||||||
|
- {pin_num: L5, peripheral: LPUART4, signal: TX, pin_signal: GPIO_SD_B1_00}
|
||||||
|
- {pin_num: M5, peripheral: LPUART4, signal: RX, pin_signal: GPIO_SD_B1_01}
|
||||||
|
- {pin_num: M3, peripheral: GPIO3, signal: 'gpio_io, 02', pin_signal: GPIO_SD_B1_02, direction: OUTPUT}
|
||||||
|
- {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, direction: OUTPUT}
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* FUNCTION ************************************************************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : BOARD_InitPins
|
||||||
|
* Description : Configures pin routing and optionally pin electrical features.
|
||||||
|
*
|
||||||
|
* END ****************************************************************************************************************/
|
||||||
|
void BOARD_InitPins(void) {
|
||||||
|
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||||
|
|
||||||
|
/* GPIO configuration on GPIO_B1_15 (pin B14) */
|
||||||
|
gpio_pin_config_t gpio2_pinB14_config = {
|
||||||
|
.direction = kGPIO_DigitalOutput,
|
||||||
|
.outputLogic = 0U,
|
||||||
|
.interruptMode = kGPIO_NoIntmode
|
||||||
|
};
|
||||||
|
/* Initialize GPIO functionality on GPIO_B1_15 (pin B14) */
|
||||||
|
GPIO_PinInit(GPIO2, 31U, &gpio2_pinB14_config);
|
||||||
|
|
||||||
|
/* GPIO configuration on GPIO_SD_B1_02 (pin M3) */
|
||||||
|
gpio_pin_config_t gpio3_pinM3_config = {
|
||||||
|
.direction = kGPIO_DigitalOutput,
|
||||||
|
.outputLogic = 0U,
|
||||||
|
.interruptMode = kGPIO_NoIntmode
|
||||||
|
};
|
||||||
|
/* Initialize GPIO functionality on GPIO_SD_B1_02 (pin M3) */
|
||||||
|
GPIO_PinInit(GPIO3, 2U, &gpio3_pinM3_config);
|
||||||
|
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_LPUART4_TX, 0U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_LPUART4_RX, 0U);
|
||||||
|
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, 0U);
|
||||||
|
IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
|
||||||
|
(~(BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)))
|
||||||
|
| IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U)
|
||||||
|
);
|
||||||
|
IOMUXC_GPR->GPR28 = ((IOMUXC_GPR->GPR28 &
|
||||||
|
(~(BOARD_INITPINS_IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK)))
|
||||||
|
| IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL(0x00U)
|
||||||
|
);
|
||||||
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
|
||||||
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
|
||||||
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
|
||||||
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* EOF
|
||||||
|
**********************************************************************************************************************/
|
||||||
@@ -0,0 +1,90 @@
|
|||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _PIN_MUX_H_
|
||||||
|
#define _PIN_MUX_H_
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*! @brief Direction type */
|
||||||
|
typedef enum _pin_mux_direction
|
||||||
|
{
|
||||||
|
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||||
|
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||||
|
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||||
|
} pin_mux_direction_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup pin_mux
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* API
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Calls initialization functions.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_InitBootPins(void);
|
||||||
|
|
||||||
|
#define BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x80000000U /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */
|
||||||
|
#define BOARD_INITPINS_IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK 0x04U /*!< GPIO3 and GPIO8 share same IO MUX function, GPIO_MUX3 selects one GPIO function: affected bits mask */
|
||||||
|
|
||||||
|
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
|
||||||
|
/* Routed pin properties */
|
||||||
|
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
|
||||||
|
#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
|
||||||
|
|
||||||
|
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
|
||||||
|
/* Routed pin properties */
|
||||||
|
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
|
||||||
|
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
|
||||||
|
|
||||||
|
/* GPIO_AD_B1_03 (coord M12), SPDIF_IN/J22[8] */
|
||||||
|
/* Routed pin properties */
|
||||||
|
#define BOARD_INITPINS_SPDIF_IN_PERIPHERAL LPUART2 /*!< Peripheral name */
|
||||||
|
#define BOARD_INITPINS_SPDIF_IN_SIGNAL RX /*!< Signal name */
|
||||||
|
|
||||||
|
/* GPIO_AD_B1_02 (coord L11), SPDIF_OUT/J22[7] */
|
||||||
|
/* Routed pin properties */
|
||||||
|
#define BOARD_INITPINS_SPDIF_OUT_PERIPHERAL LPUART2 /*!< Peripheral name */
|
||||||
|
#define BOARD_INITPINS_SPDIF_OUT_SIGNAL TX /*!< Signal name */
|
||||||
|
|
||||||
|
/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */
|
||||||
|
/* Routed pin properties */
|
||||||
|
#define BOARD_INITPINS_FlexSPI_D3_B_PERIPHERAL LPUART4 /*!< Peripheral name */
|
||||||
|
#define BOARD_INITPINS_FlexSPI_D3_B_SIGNAL TX /*!< Signal name */
|
||||||
|
|
||||||
|
/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */
|
||||||
|
/* Routed pin properties */
|
||||||
|
#define BOARD_INITPINS_FlexSPI_D2_B_PERIPHERAL LPUART4 /*!< Peripheral name */
|
||||||
|
#define BOARD_INITPINS_FlexSPI_D2_B_SIGNAL RX /*!< Signal name */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Configures pin routing and optionally pin electrical features.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_InitPins(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* _PIN_MUX_H_ */
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* EOF
|
||||||
|
**********************************************************************************************************************/
|
||||||
@@ -0,0 +1,48 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018-2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "tosevbrt1062_flexspi_nor_config.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||||
|
__attribute__((section(".boot_hdr.conf"), used))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma location = ".boot_hdr.conf"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
const flexspi_nor_config_t qspiflash_config = {
|
||||||
|
.memConfig =
|
||||||
|
{
|
||||||
|
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||||
|
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||||
|
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||||
|
.csHoldTime = 3u,
|
||||||
|
.csSetupTime = 3u,
|
||||||
|
.sflashPadType = kSerialFlash_4Pads,
|
||||||
|
.serialClkFreq = kFlexSpiSerialClk_100MHz,
|
||||||
|
.sflashA1Size = 8u * 1024u * 1024u,
|
||||||
|
.lookupTable =
|
||||||
|
{
|
||||||
|
// Read LUTs
|
||||||
|
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||||
|
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
.pageSize = 256u,
|
||||||
|
.sectorSize = 4u * 1024u,
|
||||||
|
.blockSize = 64u * 1024u,
|
||||||
|
.isUniformBlockSize = false,
|
||||||
|
};
|
||||||
|
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||||
@@ -0,0 +1,268 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018-2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||||
|
#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||||
|
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/* FLEXSPI memory config block related defintions */
|
||||||
|
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||||
|
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||||
|
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||||
|
|
||||||
|
/* FLEXSPI Feature related definitions */
|
||||||
|
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||||
|
|
||||||
|
/* Lookup table related defintions */
|
||||||
|
#define CMD_INDEX_READ 0
|
||||||
|
#define CMD_INDEX_READSTATUS 1
|
||||||
|
#define CMD_INDEX_WRITEENABLE 2
|
||||||
|
#define CMD_INDEX_WRITE 4
|
||||||
|
|
||||||
|
#define CMD_LUT_SEQ_IDX_READ 0
|
||||||
|
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||||
|
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||||
|
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||||
|
|
||||||
|
#define CMD_SDR 0x01
|
||||||
|
#define CMD_DDR 0x21
|
||||||
|
#define RADDR_SDR 0x02
|
||||||
|
#define RADDR_DDR 0x22
|
||||||
|
#define CADDR_SDR 0x03
|
||||||
|
#define CADDR_DDR 0x23
|
||||||
|
#define MODE1_SDR 0x04
|
||||||
|
#define MODE1_DDR 0x24
|
||||||
|
#define MODE2_SDR 0x05
|
||||||
|
#define MODE2_DDR 0x25
|
||||||
|
#define MODE4_SDR 0x06
|
||||||
|
#define MODE4_DDR 0x26
|
||||||
|
#define MODE8_SDR 0x07
|
||||||
|
#define MODE8_DDR 0x27
|
||||||
|
#define WRITE_SDR 0x08
|
||||||
|
#define WRITE_DDR 0x28
|
||||||
|
#define READ_SDR 0x09
|
||||||
|
#define READ_DDR 0x29
|
||||||
|
#define LEARN_SDR 0x0A
|
||||||
|
#define LEARN_DDR 0x2A
|
||||||
|
#define DATSZ_SDR 0x0B
|
||||||
|
#define DATSZ_DDR 0x2B
|
||||||
|
#define DUMMY_SDR 0x0C
|
||||||
|
#define DUMMY_DDR 0x2C
|
||||||
|
#define DUMMY_RWDS_SDR 0x0D
|
||||||
|
#define DUMMY_RWDS_DDR 0x2D
|
||||||
|
#define JMP_ON_CS 0x1F
|
||||||
|
#define STOP 0
|
||||||
|
|
||||||
|
#define FLEXSPI_1PAD 0
|
||||||
|
#define FLEXSPI_2PAD 1
|
||||||
|
#define FLEXSPI_4PAD 2
|
||||||
|
#define FLEXSPI_8PAD 3
|
||||||
|
|
||||||
|
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||||
|
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||||
|
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||||
|
|
||||||
|
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||||
|
typedef enum _FlexSpiSerialClockFreq
|
||||||
|
{
|
||||||
|
kFlexSpiSerialClk_30MHz = 1,
|
||||||
|
kFlexSpiSerialClk_50MHz = 2,
|
||||||
|
kFlexSpiSerialClk_60MHz = 3,
|
||||||
|
kFlexSpiSerialClk_75MHz = 4,
|
||||||
|
kFlexSpiSerialClk_80MHz = 5,
|
||||||
|
kFlexSpiSerialClk_100MHz = 6,
|
||||||
|
kFlexSpiSerialClk_120MHz = 7,
|
||||||
|
kFlexSpiSerialClk_133MHz = 8,
|
||||||
|
kFlexSpiSerialClk_166MHz = 9,
|
||||||
|
} flexspi_serial_clk_freq_t;
|
||||||
|
|
||||||
|
//!@brief FlexSPI clock configuration type
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||||
|
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI Read Sample Clock Source definition
|
||||||
|
typedef enum _FlashReadSampleClkSource
|
||||||
|
{
|
||||||
|
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||||
|
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||||
|
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||||
|
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||||
|
} flexspi_read_sample_clk_t;
|
||||||
|
|
||||||
|
//!@brief Misc feature bit definitions
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||||
|
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||||
|
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||||
|
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||||
|
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||||
|
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||||
|
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief Flash Type Definition
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||||
|
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||||
|
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||||
|
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||||
|
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief Flash Pad Definitions
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kSerialFlash_1Pad = 1,
|
||||||
|
kSerialFlash_2Pads = 2,
|
||||||
|
kSerialFlash_4Pads = 4,
|
||||||
|
kSerialFlash_8Pads = 8,
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI LUT Sequence structure
|
||||||
|
typedef struct _lut_sequence
|
||||||
|
{
|
||||||
|
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||||
|
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||||
|
uint16_t reserved;
|
||||||
|
} flexspi_lut_seq_t;
|
||||||
|
|
||||||
|
//!@brief Flash Configuration Command Type
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||||
|
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||||
|
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||||
|
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||||
|
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||||
|
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI Memory Configuration Block
|
||||||
|
typedef struct _FlexSPIConfig
|
||||||
|
{
|
||||||
|
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||||
|
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||||
|
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||||
|
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||||
|
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||||
|
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||||
|
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||||
|
//! Serial NAND, need to refer to datasheet
|
||||||
|
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||||
|
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||||
|
//! Generic configuration, etc.
|
||||||
|
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||||
|
//! DPI/QPI/OPI switch or reset command
|
||||||
|
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||||
|
//! sequence number, [31:16] Reserved
|
||||||
|
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||||
|
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||||
|
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||||
|
flexspi_lut_seq_t
|
||||||
|
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||||
|
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||||
|
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||||
|
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||||
|
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||||
|
//! details
|
||||||
|
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||||
|
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||||
|
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||||
|
//! Chapter for more details
|
||||||
|
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||||
|
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||||
|
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||||
|
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||||
|
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||||
|
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||||
|
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||||
|
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||||
|
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||||
|
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||||
|
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||||
|
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||||
|
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||||
|
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||||
|
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||||
|
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||||
|
//! busy flag is 0 when flash device is busy
|
||||||
|
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||||
|
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||||
|
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||||
|
} flexspi_mem_config_t;
|
||||||
|
|
||||||
|
/* */
|
||||||
|
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||||
|
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||||
|
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||||
|
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||||
|
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||||
|
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||||
|
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||||
|
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||||
|
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||||
|
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||||
|
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||||
|
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||||
|
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||||
|
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||||
|
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||||
|
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial NOR configuration block
|
||||||
|
*/
|
||||||
|
typedef struct _flexspi_nor_config
|
||||||
|
{
|
||||||
|
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||||
|
uint32_t pageSize; //!< Page size of Serial NOR
|
||||||
|
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||||
|
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||||
|
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||||
|
uint8_t reserved0[2]; //!< Reserved for future use
|
||||||
|
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||||
|
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||||
|
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||||
|
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||||
|
uint32_t blockSize; //!< Block size
|
||||||
|
uint32_t reserve2[11]; //!< Reserved for future use
|
||||||
|
} flexspi_nor_config_t;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
|
||||||
@@ -0,0 +1,28 @@
|
|||||||
|
#include "mcu_init.h"
|
||||||
|
|
||||||
|
#define APPLICATION_TASK_STK_SIZE 4096
|
||||||
|
k_task_t application_task;
|
||||||
|
uint8_t application_task_stk[APPLICATION_TASK_STK_SIZE];
|
||||||
|
|
||||||
|
extern void application_entry(void *arg);
|
||||||
|
|
||||||
|
#pragma weak application_entry
|
||||||
|
void application_entry(void *arg)
|
||||||
|
{
|
||||||
|
while (1) {
|
||||||
|
printf("This is a demo task,please use your task entry!\r\n");
|
||||||
|
tos_task_delay(1000);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
board_init();
|
||||||
|
PRINTF("Welcome to TencentOS tiny(%s)\r\n", TOS_VERSION);
|
||||||
|
tos_knl_init(); // TencentOS Tiny kernel initialize
|
||||||
|
tos_task_create(&application_task, "application_task", application_entry, NULL, 4, application_task_stk, APPLICATION_TASK_STK_SIZE, 0);
|
||||||
|
tos_knl_start();
|
||||||
|
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
||||||
@@ -0,0 +1,197 @@
|
|||||||
|
#include "mcu_init.h"
|
||||||
|
#include "tos_k.h"
|
||||||
|
#include "mqttclient.h"
|
||||||
|
#include "cjson.h"
|
||||||
|
#include "sal_module_wrapper.h"
|
||||||
|
#include "bh1750_i2c_drv.h"
|
||||||
|
|
||||||
|
#define USE_ESP8266
|
||||||
|
//#define USE_EC600S
|
||||||
|
|
||||||
|
#if defined(USE_ESP8266)
|
||||||
|
#include "esp8266.h"
|
||||||
|
|
||||||
|
#elif defined(USE_EC600S)
|
||||||
|
#include "ec600s.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
k_event_t report_result_event;
|
||||||
|
k_event_flag_t report_success = 1<<0;
|
||||||
|
k_event_flag_t report_fail = 1<<1;
|
||||||
|
|
||||||
|
static void tos_topic_handler(void* client, message_data_t* msg)
|
||||||
|
{
|
||||||
|
(void) client;
|
||||||
|
cJSON* cjson_root = NULL;
|
||||||
|
cJSON* cjson_method = NULL;
|
||||||
|
cJSON* cjson_status = NULL;
|
||||||
|
cJSON* cjson_params = NULL;
|
||||||
|
cJSON* cjson_switch = NULL;
|
||||||
|
char* status = NULL;
|
||||||
|
char* method = NULL;
|
||||||
|
k_event_flag_t event_flag = report_fail;
|
||||||
|
int power_switch;
|
||||||
|
|
||||||
|
/* <20><>ӡ<EFBFBD><D3A1>־ */
|
||||||
|
MQTT_LOG_I("-----------------------------------------------------------------------------------");
|
||||||
|
MQTT_LOG_I("%s:%d %s()...\ntopic: %s, qos: %d. \nmessage:\n\t%s\n", __FILE__, __LINE__, __FUNCTION__,
|
||||||
|
msg->topic_name, msg->message->qos, (char*)msg->message->payload);
|
||||||
|
MQTT_LOG_I("-----------------------------------------------------------------------------------\n");
|
||||||
|
|
||||||
|
/* ʹ<><CAB9>cjson<6F><6E><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD> */
|
||||||
|
cjson_root = cJSON_Parse((char*)msg->message->payload);
|
||||||
|
if (cjson_root == NULL) {
|
||||||
|
printf("report reply message parser fail\r\n");
|
||||||
|
event_flag = report_fail;
|
||||||
|
goto exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* <20><>ȡmethod */
|
||||||
|
cjson_method = cJSON_GetObjectItem(cjson_root, "method");
|
||||||
|
method = cJSON_GetStringValue(cjson_method);
|
||||||
|
if (cjson_method == NULL || method == NULL) {
|
||||||
|
printf("report reply status parser fail\r\n");
|
||||||
|
event_flag = report_fail;
|
||||||
|
goto exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (strstr(method, "report_reply")) {
|
||||||
|
/* <20><>ȡstatus״̬ */
|
||||||
|
cjson_status = cJSON_GetObjectItem(cjson_root, "status");
|
||||||
|
status = cJSON_GetStringValue(cjson_status);
|
||||||
|
if (cjson_status == NULL || status == NULL) {
|
||||||
|
printf("report reply status parser fail\r\n");
|
||||||
|
event_flag = report_fail;
|
||||||
|
goto exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* <20>ж<EFBFBD>status״̬ */
|
||||||
|
if (strstr(status,"success")) {
|
||||||
|
event_flag = report_success;
|
||||||
|
}else {
|
||||||
|
event_flag = report_fail;
|
||||||
|
}
|
||||||
|
} else if (strstr(method, "control")) {
|
||||||
|
cjson_params = cJSON_GetObjectItem(cjson_root, "params");
|
||||||
|
cjson_switch = cJSON_GetObjectItem(cjson_params, "power_switch");
|
||||||
|
if (cjson_params == NULL || cjson_switch == NULL) {
|
||||||
|
printf("control data parser fail\r\n");
|
||||||
|
cJSON_Delete(cjson_root);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
power_switch = cjson_switch->valueint;
|
||||||
|
if (power_switch == 0) {
|
||||||
|
GPIO_PinWrite(GPIO2, 31, 0);
|
||||||
|
} else if (power_switch == 1) {
|
||||||
|
GPIO_PinWrite(GPIO2, 31, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
cJSON_Delete(cjson_root);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
exit:
|
||||||
|
cJSON_Delete(cjson_root);
|
||||||
|
cjson_root = NULL;
|
||||||
|
status = NULL;
|
||||||
|
method = NULL;
|
||||||
|
|
||||||
|
tos_event_post(&report_result_event, event_flag);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define REPORT_DATA_TEMPLATE "{\"method\":\"report\",\"clientToken\":\"00000001\",\"params\":{\"brightness\":%d,\"name\":\"bedroom\"}}"
|
||||||
|
|
||||||
|
char report_buf[200];
|
||||||
|
|
||||||
|
void mqttclient_task(void)
|
||||||
|
{
|
||||||
|
int error;
|
||||||
|
mqtt_client_t *client = NULL;
|
||||||
|
mqtt_message_t msg;
|
||||||
|
k_event_flag_t match_flag;
|
||||||
|
char host_ip[20];
|
||||||
|
uint16_t lux;
|
||||||
|
|
||||||
|
memset(&msg, 0, sizeof(msg));
|
||||||
|
|
||||||
|
#ifdef USE_ESP8266
|
||||||
|
esp8266_sal_init(HAL_UART_PORT_2);
|
||||||
|
esp8266_join_ap("Mculover666", "mculover666");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef USE_EC600S
|
||||||
|
ec600s_sal_init(HAL_UART_PORT_4);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
bh1750_init();
|
||||||
|
|
||||||
|
mqtt_log_init();
|
||||||
|
|
||||||
|
client = mqtt_lease();
|
||||||
|
|
||||||
|
tos_event_create(&report_result_event, (k_event_flag_t)0u);
|
||||||
|
|
||||||
|
/* Domain Format: <your product ID>.iotcloud.tencentdevices.com */
|
||||||
|
tos_sal_module_parse_domain("FWR8PGACUS.iotcloud.tencentdevices.com",host_ip,sizeof(host_ip));
|
||||||
|
|
||||||
|
/*
|
||||||
|
These infomation is generated by mqtt_config_gen.py tool in "TencentOS-tiny\tools" directory.
|
||||||
|
*/
|
||||||
|
mqtt_set_port(client, "1883");
|
||||||
|
mqtt_set_host(client, host_ip);
|
||||||
|
mqtt_set_client_id(client, "FWR8PGACUSdev001");
|
||||||
|
mqtt_set_user_name(client, "FWR8PGACUSdev001;21010406;12365;4294967295");
|
||||||
|
mqtt_set_password(client, "273f218b35f52900b8b85183d93c1fcc6b9c9444;hmacsha1");
|
||||||
|
mqtt_set_clean_session(client, 1);
|
||||||
|
|
||||||
|
error = mqtt_connect(client);
|
||||||
|
|
||||||
|
MQTT_LOG_D("mqtt connect error is %#0x", error);
|
||||||
|
|
||||||
|
error = mqtt_subscribe(client, "$thing/down/property/FWR8PGACUS/dev001", QOS0, tos_topic_handler);
|
||||||
|
|
||||||
|
MQTT_LOG_D("mqtt subscribe error is %#0x", error);
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
bh1750_start(ONCE_H_MODE);
|
||||||
|
tos_task_delay(160);
|
||||||
|
bh1750_read_lux(&lux);
|
||||||
|
printf("bh1750 lux is %d\r\n", lux);
|
||||||
|
|
||||||
|
memset(&msg, 0, sizeof(msg));
|
||||||
|
snprintf(report_buf, sizeof(report_buf), REPORT_DATA_TEMPLATE, lux);
|
||||||
|
|
||||||
|
msg.qos = QOS0;
|
||||||
|
msg.payload = (void *) report_buf;
|
||||||
|
error = mqtt_publish(client, "$thing/up/property/FWR8PGACUS/dev001", &msg);
|
||||||
|
MQTT_LOG_D("mqtt publish error is %#0x", error);
|
||||||
|
|
||||||
|
tos_event_pend(&report_result_event,
|
||||||
|
report_success|report_fail,
|
||||||
|
&match_flag,
|
||||||
|
TOS_TIME_FOREVER,
|
||||||
|
TOS_OPT_EVENT_PEND_ANY | TOS_OPT_EVENT_PEND_CLR);
|
||||||
|
|
||||||
|
if (match_flag == report_success) {
|
||||||
|
printf("report to Tencent IoT Explorer success\r\n");
|
||||||
|
|
||||||
|
}else if (match_flag == report_fail){
|
||||||
|
printf("report to Tencent IoT Explorer fail\r\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
tos_task_delay(5000);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void application_entry(void *arg)
|
||||||
|
{
|
||||||
|
mqttclient_task();
|
||||||
|
while (1) {
|
||||||
|
printf("This is a mqtt demo!\r\n");
|
||||||
|
tos_task_delay(1000);
|
||||||
|
}
|
||||||
|
}
|
||||||
Reference in New Issue
Block a user