add wifi project.(board/EVB_LN882x, example/wifi_ln882x, platform/vendor_bsp)

platform/vendor_bsp/LN/ln882x/include/atcmd/at_cmd_basic.h

@@ -0,0 +1,26 @@
+#ifndef AT_CMD_BASIC_H
+#define AT_CMD_BASIC_H
+
+#include "types.h"
+#include "atcmd/at_list.h"
+
+
+char at_at_excute(char *str);
+char at_ate0_excute(char *str);
+char at_ate1_excute(char *str);
+char at_rst_excute(char *str);
+char at_gmr_excute(char *str);
+char at_gslp_excute(char *str);
+char at_restore_excute(char *str);
+char at_uart_cur_get(char *str);
+char at_sleep_get(char *str);
+char at_sleep_set(char *str);
+char at_wakeupgpio_set(char *str);
+char at_sysgpiodir_set(char *str);
+char at_sysgpiowrite_set(char *str);
+char at_sysgpioread_set(char *str);
+char at_cal_excute(char *str);
+
+
+
+#endif

platform/vendor_bsp/LN/ln882x/include/atcmd/at_cmd_wifi.h

@@ -0,0 +1,152 @@
+
+#ifndef AT_CMD_WIFI_H
+#define AT_CMD_WIFI_H
+
+#include "proj_config.h"
+#include "types.h"
+#include "atcmd/at_list.h"
+#define IP4_ADDR_LENGTH		4
+
+char at_pvtcmd_set(char *str);
+
+//station+softap
+char at_set_wifi_mode(char *str);
+char at_get_wifi_mode(char *str);
+char at_help_wifi_mode(char *str);
+char at_set_wifi_mode_current(char *str);
+char at_get_wifi_mode_current(char *str);
+char at_help_wifi_mode_current(char *str);
+char at_set_wifi_mode_def(char *str);
+char at_get_wifi_mode_def(char *str);
+char at_help_wifi_mode_def(char *str);
+
+
+//station
+char at_station_setmac(char *str);
+char at_station_getmac(char *str);
+char at_station_setmac_current(char *str);
+char at_station_getmac_current(char *str);
+char at_station_setmac_def(char *str);
+char at_station_getmac_def(char *str);
+char at_station_connect(char *str);
+char at_station_connect_current(char *str);
+char at_station_get_connected_info(char *str);
+char at_station_get_connected_info_current(char *str);
+char at_station_get_connected_info_def(char *str);
+char at_station_disconnect(void);
+char at_station_set_scan_list_display_option(char *str);
+char at_station_scan(char *str);
+char at_station_scan_no_filter(char *str);
+#if WIFI_SNIFFER_TEST
+char at_notify_aplist(void);
+char at_station_aplx(char *str);
+#endif
+
+//softap
+char at_softap_setmac(char *str);
+char at_softap_getmac(char *str);
+char at_softap_setmac_current(char *str);
+char at_softap_getmac_current(char *str);
+char at_softap_setmac_def(char *str);
+char at_softap_getmac_def(char *str);
+char at_softap_set_config(char *str);
+char at_softap_get_config(char *str);
+char at_softap_set_config_current(char *str);
+char at_softap_get_config_current(char *str);
+char at_softap_set_config_def(char *str);
+char at_softap_get_config_def(char *str);
+char at_softap_get_station_list(char *str);
+
+//get station ip
+char at_get_sta_ip(char *str);
+char at_get_sta_ip_cur(char *str);
+char at_get_sta_ip_def(char *str);//!!!(esp8266)[AT+CIPSTA_DEF?]Why not take parameters from flash?
+//set statation ip
+char at_set_sta_ip_cur(char *str);
+char at_set_sta_ip_def(char *str);
+//get spatAP ip
+char at_get_ap_ip(char *str);
+char at_get_ap_ip_cur(char *str);
+char at_get_ap_ip_def(char *str);//!!!(esp8266)[AT+CIPAP_DEF?]Why not take parameters from flash?
+//set softAP ip
+char at_set_ap_ip_cur(char *str);
+char at_set_ap_ip_def(char *str);
+
+//set dhcp
+char at_set_dhcp_cur(char * str);
+char at_set_dhcp_def(char * str);
+//get dhcp
+char at_get_dhcp_cur(char * str);
+char at_get_dhcp_def(char * str);
+//set dhcps
+char at_set_dhcps_cur(char * str);
+char at_set_dhcps_def(char * str);
+//get dhcps
+char at_get_dhcps_cur(char * str);
+char at_get_dhcps_def(char * str);
+
+//ping
+char at_ping(char * str);
+
+//get CPU usage
+char at_get_cpu_usage(char * str);
+
+//chip SN
+char at_get_chip_sn(char * str);
+char at_set_chip_sn(char * str);
+
+//bt id
+char at_get_bt_id(char * str);
+char at_set_bt_id(char * str);
+
+//bt mac
+char at_get_bt_mac(char * str);
+char at_set_bt_mac(char * str);
+
+//CNVDS
+char at_nvds(char * str);
+
+//CEFUSE
+char at_get_efuse(char * str);
+char at_set_efuse(char * str);
+
+//XTAL_COMP
+char at_get_xtal_cap_comp(char * str);
+char at_set_xtal_cap_comp(char * str);
+
+//TXPOWER_COMP
+char at_get_tx_power_comp(char * str);
+char at_set_tx_power_comp(char * str);
+
+
+//-------------All the code below is waiting to be deleted!----------------------
+
+char at_set_station_auto_connect(char *str);
+char at_get_station_auto_connect(char *str);
+
+char at_set_sta_host_name(char *str);
+char at_get_sta_host_name(char *str);
+char at_set_ip_connect(char *str);
+char at_set_tcp_server(char *str);
+char at_set_udp_server(char *str);
+char at_set_ip_send_ex_length(char *str);
+char at_set_cip_mux(char *str);
+char at_get_cip_mux(char *str);
+char at_set_netconn_disconnect(char *str);
+char at_set_ip_close(char *str);
+char at_get_cip_status(char *str);
+
+#if WIFI_SWITCH
+void wifi_sniffer_deinit(void);
+void wifi_sniffer_reinit(void);
+char at_wifi_switch(char *str);
+bool wifi_init(void);
+bool wifi_deinit(void);
+#endif
+
+char at_iperf(char *str);
+
+
+#endif
+
+

platform/vendor_bsp/LN/ln882x/include/atcmd/at_list.h

@@ -0,0 +1,35 @@
+#ifndef AT_LIST_H
+#define AT_LIST_H
+
+#include "types.h"
+
+typedef char (*at_callback)(char *value);
+
+
+typedef struct _at_command
+{
+    unsigned long hash;
+    at_callback setter;
+    at_callback getter;
+    at_callback test;
+    at_callback execute;
+} AT_COMMAND;
+
+#ifndef AT_PLUS_CMD_NUM
+#define AT_PLUS_CMD_NUM 80
+
+#endif
+
+#ifndef AT_SHORT_CMD_NUM
+#define AT_SHORT_CMD_NUM 3
+#endif
+
+
+
+void at_cmd_init(void);
+
+
+
+
+#endif
+

platform/vendor_bsp/LN/ln882x/include/atcmd/at_parser.h

@@ -0,0 +1,32 @@
+#ifndef AT_PARSER_H
+#define AT_PARSER_H
+
+#include "atcmd/at_string.h"
+#include "atcmd/at_list.h"
+#include "console/console.h"
+#define AT_MAX_TEMP_STRING	50
+
+#define AT_OK 		0
+#define AT_ERROR 	1
+
+#define AT_PARSER_STATE_COMMAND 	0
+#define AT_PARSER_STATE_TEST		1
+#define AT_PARSER_STATE_READ		2
+#define AT_PARSER_STATE_WRITE		3
+#define AT_PARSER_STATE_EQUAL		4
+
+#ifndef AT_COMMAND_MARKER
+#define AT_COMMAND_MARKER "AT+"
+#endif
+
+#define at_printf console_printf
+
+unsigned long at_hash(char * str);
+void at_register_command(char * command, at_callback getter, at_callback setter, at_callback test, at_callback execute);
+void at_register_short_command(char * command, at_callback getter, at_callback setter, at_callback test, at_callback execute);
+char at_parse_plus_cmd(char * line);
+char at_parse_short_cmd(char * line);
+
+
+
+#endif

platform/vendor_bsp/LN/ln882x/include/atcmd/at_string.h

@@ -0,0 +1,21 @@
+#ifndef __AT_STRING__
+#define __AT_STRING__
+
+#include "types.h"
+
+
+typedef enum
+{
+    AT_SHORT_CMD=0,
+    AT_PLUS_CMD,
+    AT_CMD_INVALID
+}AT_CMD_TYPE;
+
+
+int16_t at_str_find(char *haystack, char *needle);
+void at_array_slice_to_string(char *array, uint16_t start, uint16_t end, char *ret);
+uint16_t at_strlen(char *string);
+AT_CMD_TYPE at_check_cmdtype(char * line);
+void str_remove_cr_lf(char * str);
+
+#endif

platform/vendor_bsp/LN/ln882x/include/atcmd/at_task.h

@@ -0,0 +1,30 @@
+
+#ifndef AT_TASK_H
+#define AT_TASK_H
+#include "proj_config.h"
+#include "types.h"
+#include "osal/osal.h"
+
+
+typedef struct
+{
+    uint8_t len;
+    char *pBuffer;
+#ifdef __CONFIG_OS_KERNEL
+    OS_Semaphore_t              *sem;
+#endif
+}AT_MSG_T;
+
+#ifdef __CONFIG_OS_KERNEL
+  #define ATMSG_QUEUE_LEN     6
+  extern OS_Queue_t g_at_msg_queue;
+  extern OS_Thread_t g_at_thread;
+
+  void at_task(void *params);
+#endif
+
+extern void at_init(void);
+
+#endif
+
+

platform/vendor_bsp/LN/ln882x/include/console/console.h

@@ -0,0 +1,48 @@
+#ifndef __CONSOLE_H__
+#define __CONSOLE_H__
+#include "proj_config.h"
+
+#include "types.h"
+#ifdef __CONFIG_OS_KERNEL
+  #include "osal/osal.h"
+#endif
+#include "utils/wrap_stdio.h"
+
+/* extern function */
+#define	CMD_MAXARGS	   4
+#if (TCP_TEST_DATA_FROM_CONSOLE==1)
+#define CMD_CBSIZE     256*4
+#define CMD_PBSIZE     256*4
+#else
+#define CMD_CBSIZE     256
+#define CMD_PBSIZE     256
+#endif
+#define CMD_END_MARK_CR   ("\r")
+#define CMD_END_MARK_LF   ("\n")
+#define CMD_END_MARK_CRLF ("\r\n")
+
+
+typedef struct
+{
+    char	console_cmd_buffer[CMD_CBSIZE];
+    char	cmd_line[CMD_PBSIZE];
+    int		index;
+    bool    echo;
+#ifdef __CONFIG_OS_KERNEL
+    OS_Semaphore_t              sem;
+#endif
+} CONSOLE_CTRL_T;
+
+
+int command_stdio_write(char *buf, size_t size);
+extern void console_echo_enable(bool en);
+extern void console_init(void);
+extern void console_exe_command(char *cmd, unsigned int cmd_len);
+
+#if (CHIP_ROLE == CHIP_MCU)
+#define console_printf(format, ...)     __wrap_sprintf((stdio_write_fn)command_stdio_write, format, ##__VA_ARGS__)
+#else
+#define console_printf(format, ...)     __wrap_sprintf((stdio_write_fn)NULL, format, ##__VA_ARGS__)
+#endif
+
+#endif /* end console.h */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/CMSIS_5.3.0/cmsis_armcc.h

@@ -0,0 +1,814 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/CMSIS_5.3.0/cmsis_compiler.h

@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/CMSIS_5.3.0/cmsis_iccarm.h

@@ -0,0 +1,913 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.5
+ * @date     10. January 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
+  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/CMSIS_5.3.0/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/CMSIS_5.3.0/mpu_armv7.h

@@ -0,0 +1,273 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.5
+ * @date     06. September 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/ln88xx/base_addr_ln882x.h

@@ -0,0 +1,43 @@
+#ifndef __BASE_ADDR_LN882X_H_
+#define __BASE_ADDR_LN882X_H_
+
+#define    REG_ROM_BASE                   0x00000000
+#define    REG_CACHE_FLASH_BASE           0x10000000
+#define    REG_SRAM0_BASE                 0x1FFF0000
+#define    REG_SRAM1_BASE                 0x20000000
+#define    REG_SRAM2_BASE                 0x20010000
+#define    REG_SRAM3_BASE                 0x20020000
+#define    REG_DMA_BASE                   0x20100000
+#define    REG_CACHE_BASE                 0x20200000
+#define    REG_SYSC_CMP_BASE              0x40000000
+#define    REG_ADC_BASE                   0x40000800
+
+#define    REG_PWM_BASE                   0x40001000
+#define    REG_EFUSE_BASE                 0x40001800
+
+#define    REG_UART0_BASE                 0x40002000
+#define    REG_UART1_BASE                 0x40003000
+#define    REG_SPI_M1_BASE                0x40004000
+#define    REG_SPI_M0_BASE                0x40005000
+#define    REG_SPI_S0_BASE                0x40006000
+#define    REG_I2C0_BASE                  0x40007000
+#define    REG_I2C1_BASE                  0x40008000
+#define    REG_I2S_BASE                   0x40009000
+#define    REG_TIMER_BASE                 0x4000a000
+#define    REG_WDT_BASE                   0x4000b000
+#define    REG_GPIO_BASE                  0x4000c000
+
+#define    REG_TRNG_BASE                  0x4000c800
+
+#define    REG_BUS_PTCH_BASE              0x4000d000
+#define    REG_MAC_PCU_REG_BASE           0x40010000
+#define    REG_MAC_CE_REG_BASE            0x40011000
+#define    REG_RF_P0_BASE                 0x40012000
+#define    REG_RF_P1_BASE                 0x40012400
+#define    REG_SYSC_AWO_BASE              0x40100000
+#define    REG_RTC_BASE                   0x40101000
+#define    REG_QSPI_BASE                  0x40200000
+#define    REG_SDIO_BASE                  0x40300000
+#define    REG_AES_BASE                   0x40400000
+
+#endif /* __BASE_ADDR_LN882X_H_ */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/ln88xx/common_def_ln88xx.h

@@ -0,0 +1,30 @@
+#ifndef __COMMON_DEF_LN88XX_H__
+#define __COMMON_DEF_LN88XX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DISABLE                 0
+#define ENABLE                  1
+
+#define CHIP_SLAVE                          0 //As a device for the master chip
+#define CHIP_MCU                            1
+
+
+#define RTOS_FREERTOS						0
+#define RTOS_ALIOS   						1
+#define RTOS_RT_THREAD     				    2
+#define RTOS_UCOS     						3
+
+/*
+ * Clock settings section
+ */
+#define PLL_CLOCK                               (160000000)
+#define XTAL_CLOCK                              (40000000)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __COMMON_DEF_LN88XX_H__ */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/ln88xx/interrupt.h

@@ -0,0 +1,83 @@
+#ifndef _INTERRUPT_H_
+#define _INTERRUPT_H_
+
+
+//------------------------------------------------------------------------------
+//
+//   Weak attribute allows to replace default handler with the user's one
+//
+#define WEAK __attribute__ ((weak))
+//------------------------------------------------------------------------------
+
+extern unsigned long __top_of_stack[];
+//------------------------------------------------------------------------------
+//
+//   Vector table item. Can be pointer to function or plain address value
+//
+typedef void (*intfun_t)(void);
+typedef struct
+{
+    unsigned long *tos;
+    intfun_t      vectors[101];
+}__vector_table_t;
+
+//------------------------------------------------------------------------------
+//
+//   Startup handler
+//
+void Reset_Handler(void);
+
+//------------------------------------------------------------------------------
+//
+//   Cortex-M internal exceptions
+//
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+
+//------------------------------------------------------------------------------
+//
+//   Controller specific peripheral interrupts
+//
+WEAK void WDT_IRQHandler();
+WEAK void EXTERNAL_IRQHandler();
+WEAK void RTC_IRQHandler();
+WEAK void SLEEP_IRQHandler();
+WEAK void MAC_IRQHandler();
+WEAK void DMAC_IRQHandler();
+WEAK void QSPI_IRQHandler();
+WEAK void SDIOCFUN1_IRQHandler();
+WEAK void SDIOCFUN2_IRQHandler();
+WEAK void SDIOCFUN3_IRQHandler();
+WEAK void SDIOCFUN4_IRQHandler();
+WEAK void SDIOCFUN5_IRQHandler();
+WEAK void SDIOCFUN6_IRQHandler();
+WEAK void SDIOCFUN7_IRQHandler();
+WEAK void SDIOC_ASYNC_HOST_IRQHandler();
+WEAK void SDIOC_M2S_IRQHandler();
+WEAK void CM4_INTR0_IRQHandler();
+WEAK void CM4_INTR1_IRQHandler();
+WEAK void CM4_INTR2_IRQHandler();
+WEAK void CM4_INTR3_IRQHandler();
+WEAK void CM4_INTR4_IRQHandler();
+WEAK void CM4_INTR5_IRQHandler();
+WEAK void ADCC_IRQHandler();
+WEAK void TIMER_IRQHandler();
+WEAK void I2C0_IRQHandler();
+WEAK void I2C1_IRQHandler();
+WEAK void SPIM_IRQHandler();
+WEAK void SPIS_IRQHandler();
+WEAK void UART0_IRQHandler();
+WEAK void UART1_IRQHandler();
+WEAK void SPIM2_IRQHandler();
+WEAK void GPIO_IRQHandler();
+WEAK void I2S_IRQHandler();
+WEAK void PAOTD_IRQHandler();
+
+#endif /* _INTERRUPT_H_ */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/ln88xx/ln88xx.h

@@ -0,0 +1,159 @@
+#ifndef __LN88XX_H__
+#define __LN88XX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+typedef enum IRQn
+{
+    /* -------------------  Processor Exceptions Numbers  ----------------------------- */
+    Reset_IRQn              = -15,              /* -15  Reset Vector, invoked on Power up and warm reset                       */
+    NMI_IRQn                = -14,              /* -14  Non maskable Interrupt, cannot be stopped or preempted                           */
+    HardFault_IRQn          = -13,              /* -13  Hard Fault, all classes of Fault                                       */
+    MemoryManagement_IRQn   = -12,              /* -12  Memory Management, MPU mismatch, including Access Violation and No Match */
+    BusFault_IRQn           = -11,              /* -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                        related Fault                                                          */
+    UsageFault_IRQn         = -10,              /* -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition          */
+    SVCall_IRQn             =  -5,              /* -5   System Service Call via SVC instruction                                */
+    DebugMonitor_IRQn       =  -4,              /* -4   Debug Monitor                                                          */
+    PendSV_IRQn             =  -2,              /* -2   Pendable request for system service                                    */
+    SysTick_IRQn            =  -1,              /* -1   System Tick Timer                                                      */
+
+    /* -------------------  Processor Interrupt Numbers  ------------------------------ */
+    WDT_IRQn                = 0,
+    EXTERNAL_IRQn           = 1,
+    RTC_IRQn                = 2,
+    SLEEP_IRQn              = 3,
+    MAC_IRQn                = 4,
+    DMA_IRQn                = 5,
+    QSPI_IRQn               = 6,
+    SDIO_FUN1_IRQn          = 7,
+    SDIO_FUN2_IRQn          = 8,
+    SDIO_FUN3_IRQn          = 9,
+    SDIO_FUN4_IRQn          = 10,
+    SDIO_FUN5_IRQn          = 11,
+    SDIO_FUN6_IRQn          = 12,
+    SDIO_FUN7_IRQn          = 13,
+    SDIO_ASYNC_HOST_IRQn    = 14,
+    SDIO_M2S_IRQn           = 15,
+    CM4_INTR0_IRQn          = 16,
+    CM4_INTR1_IRQn          = 17,
+    CM4_INTR2_IRQn          = 18,
+    CM4_INTR3_IRQn          = 19,
+    CM4_INTR4_IRQn          = 20,
+    CM4_INTR5_IRQn          = 21,
+    ADC_IRQn                = 22,
+    TIMER_IRQn              = 23,
+    I2C0_IRQn               = 24,
+    I2C1_IRQn               = 25,
+    SPI0_IRQn               = 26,
+    SPI2_IRQn               = 27,
+    UART0_IRQn              = 28,
+    UART1_IRQn              = 29,
+    SPI1_IRQn               = 30,
+    GPIO_IRQn               = 31,
+    I2S_IRQn                = 32,
+    PAOTD_IRQn              = 33,  
+#if   defined (LN881x)
+#elif defined (LN882x)
+    PWM_IRQn                = 34,
+    TRNG_IRQn               = 35,
+    AES_IRQn                = 36,
+#else 
+  #error Not supported device type
+#endif
+} IRQn_Type;
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+#define __CM4_REV                 0x0201U    /*!< Core Revision r2p1 */
+/* ToDo: define the correct core features for the <Device> */
+#define __MPU_PRESENT             1U         /*!< Set to 1 if MPU is present */
+#define __VTOR_PRESENT            1U         /*!< Set to 1 if VTOR is present */
+#define __NVIC_PRIO_BITS          3U         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0U         /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1U         /*!< Set to 1 if FPU is present */
+#define __FPU_DP                  0U         /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */
+#define __ICACHE_PRESENT          0U         /*!< Set to 1 if I-Cache is present */
+#define __DCACHE_PRESENT          0U         /*!< Set to 1 if D-Cache is present */
+#define __DTCM_PRESENT            0U         /*!< Set to 1 if DTCM is present */
+
+#include "core_cm4.h"                        /* Processor and core peripherals */
+#include "system_ln88xx.h"                   /* System Header */
+
+#include <stdbool.h>
+#include <stddef.h>
+
+/* -------  Start of section using anonymous unions and disabling warnings  ------- */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+
+
+/* --------  End of section using anonymous unions and disabling warnings  -------- */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+#if   defined (LN881x)
+  #include "base_addr_ln881x.h"
+  #include "mem_map_ln881x.h"
+#elif defined (LN882x)
+  #include "base_addr_ln882x.h"
+  #include "mem_map_ln882x.h"
+#else 
+  #error Not supported device type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __LN88XX_H__ */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/ln88xx/mem_map_ln882x.h

@@ -0,0 +1,95 @@
+#ifndef __MEMORY_MAP_LN882X_H__
+#define __MEMORY_MAP_LN882X_H__
+
+#define SIZE_4KB                    (0x1000)
+#define SIZE_8KB                    (2 * SIZE_4KB)
+#define SIZE_16KB                   (4 * SIZE_4KB)
+#define SIZE_32KB                   (8 * SIZE_4KB)
+#define SIZE_64KB                   (16 * SIZE_4KB)
+#define SIZE_128KB                  (32 * SIZE_4KB)
+#define SIZE_2MB                    (32 * SIZE_64KB)
+
+// Memory map is shown in the following figure:
+
+// *--------------------------------------------------------------------------------------------------------------------*
+// |        RAM_BLOCK0            |               RAM_BLOCK1                    |  RETENTION_MEM   | User unavailable   |
+// *--------------------------------------------------------------------------------------------------------------------*
+// |                              |              |               |              |                  |                    |
+// |        SRAM0 128KB           |   SRAM1 64KB |   SRAM2 64KB  | SRAM3_0  32KB|  SRAM3_1  8KB    |    SRAM3_2  32KB   |
+// |                              |              |               |              |  retention mem   |    cache mem       |
+// *--------------------------------------------------------------------------------------------------------------------*
+// @0x1FFE0000                    @0x20000000    @0x20010000     @0x20020000    @0x20028000        @0x2002A000          @0x20032000
+
+//RAM
+#define RAM_BASE					(0x1ffe0000)
+#define SRAM0_BASE                  (RAM_BASE)
+#define SRAM0_SIZE                  (SIZE_128KB)
+
+#define SRAM1_BASE                  (SRAM0_BASE + SRAM0_SIZE)
+#define SRAM1_SIZE                  (SIZE_64KB)
+
+#define SRAM2_BASE                  (SRAM1_BASE + SRAM1_SIZE)
+#define SRAM2_SIZE                  (SIZE_64KB)
+
+#define SRAM3_0_BASE                (SRAM2_BASE + SRAM2_SIZE)
+#define SRAM3_0_SIZE                (SIZE_32KB)
+
+#define SRAM3_1_BASE                (SRAM3_0_BASE + SRAM3_0_SIZE)
+#define SRAM3_1_SIZE                (SIZE_8KB)
+
+#define SRAM3_2_BASE                (SRAM3_1_BASE + SRAM3_1_SIZE)
+#define SRAM3_2_SIZE                (SIZE_32KB)
+
+#define RETENTION_MEM_BASE			(SRAM3_1_BASE)
+#define RETENTION_MEM_SIZE			(SIZE_8KB)
+
+#define CACHE_MEM_BASE				(SRAM3_2_BASE)
+#define CACHE_MEM_SIZE				(SIZE_32KB)
+
+#define RAM_TOP						(CACHE_MEM_BASE + CACHE_MEM_SIZE)
+
+#define RAM_BLOCK0_BASE             (RAM_BASE)
+#define RAM_BLOCK0_SIZE             (SRAM0_SIZE)
+#define RAM_BLOCK1_BASE             (SRAM1_BASE)
+#define RAM_BLOCK1_SIZE             (SRAM1_SIZE + SRAM2_SIZE + SRAM3_0_SIZE)
+
+//ROM and BOOTROM
+#define ROM_MEM_BASE                (0x00000000)
+#define ROM_MEM_SIZE				(SIZE_16KB)
+
+#define BOOTROM_BASE 				(ROM_MEM_BASE)
+#define BOOTROM_LIMIT				(ROM_MEM_SIZE)
+
+#define BOOTROM_RW_SECTION_BASE	    (SRAM2_BASE)
+#define BOOTROM_RW_SECTION_LIMIT    (SIZE_32KB)
+
+//BOOTRAM
+#define BOOTRAM_BASE                 (RAM_BASE)
+#define BOOTRAM_LIMIT                (SIZE_32KB)
+
+
+//FLASH
+#define FLASH_BASE_OFFSET                   (0)
+
+#define BOOTRAM_HEADER_ON_FLASH_OFFSET      (FLASH_BASE_OFFSET)
+#define BOOTRAM_ON_FLASH_OFFSET             (BOOTRAM_HEADER_ON_FLASH_OFFSET + BOOTRAM_HEADER_SIZE)
+#define BOOTRAM_PARTITION_SIZE			    (8 * SIZE_4KB)
+#define BOOTRAM_SIZE                        (BOOTRAM_PARTITION_SIZE - BOOTRAM_HEADER_SIZE)
+
+#define PARTITION_TABLE0_OFFSET             (BOOTRAM_HEADER_ON_FLASH_OFFSET + BOOTRAM_PARTITION_SIZE)
+#define PARTITION_TABLE0_SIZE               (SIZE_4KB)
+
+#define PARTITION_TABLE1_OFFSET             (PARTITION_TABLE0_OFFSET + PARTITION_TABLE0_SIZE)
+#define PARTITION_TABLE1_SIZE               (SIZE_4KB)
+
+#define PARTITION_TABLE_FLAG_OFFSET         (PARTITION_TABLE1_OFFSET + PARTITION_TABLE1_SIZE)
+#define PARTITION_TABLE_FLAG_SIZE           (SIZE_4KB)
+
+#define SYSTEM_PARAMETER_OFFSET             (PARTITION_TABLE_FLAG_OFFSET + PARTITION_TABLE_FLAG_SIZE)
+#define SYSTEM_PARAMETER_SIZE               (2 * SIZE_4KB)
+
+#define USR_NVDS_PARAM_OFFSET               (SIZE_2MB-(3*SIZE_4KB))
+#define USR_NVDS_PARAM_SIZE                 (3 * SIZE_4KB)
+
+
+#endif /* __MEMORY_MAP_LN882X_H__ */

platform/vendor_bsp/LN/ln882x/include/cpu/ARM_CM4F/ln88xx/system_ln88xx.h

@@ -0,0 +1,32 @@
+#ifndef __SYSTEM_LN88XX_H__
+#define __SYSTEM_LN88XX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+extern void SetSysClock(void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+extern uint32_t get_SystemCoreClock(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LN88XX_H__ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/drv/drv_adc_measure.h

@@ -0,0 +1,13 @@
+#ifndef __DRV_ADC_MEASURE_H__
+#define __DRV_ADC_MEASURE_H__
+
+#include <stdint.h>
+
+
+void drv_adc_init(void);
+void drv_adc_trigger(void);
+uint16_t drv_adc_read(uint8_t ch);
+
+
+
+#endif // __DRV_ADC_MEASURE_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/cache.h

@@ -0,0 +1,39 @@
+#ifndef __CACHE_H__
+#define __CACHE_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/**
+ * @brief Init flash cache.
+ *
+ * @param flash_base_addr Base address of flash.
+ */
+void flash_cache_init(uint32_t flash_base_addr);
+
+/**
+ * @brief Disable flash cache.
+ */
+void flash_cache_disable(void);
+
+/**
+ * @brief Flush cache block.
+ * @param low_addr Lower address to flush.
+ * @param high_addr Higher address to flush.
+ */
+void flash_cache_flush(uint32_t low_addr,uint32_t high_addr);
+
+/**
+ * @brief Flush all flash.
+ *
+ */
+void flash_cache_flush_all(void);
+
+
+#ifdef __cplusplus
+    }
+#endif // __cplusplus
+#endif

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/exflash.h

@@ -0,0 +1,150 @@
+#ifndef __EXFLASH_H__
+#define __EXFLASH_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+///////////////////////////////  External FLASH  //////////////////////////////
+#define EXFLASH_PAGE_PROGRAM            0x02
+#define EXFLASH_READ_DATA_BYTES         0x03
+#define EXFLASH_WRITE_DISABLE           0x04
+#define EXFLASH_READ_STATUS_REG_LOW     0x05
+#define EXFLASH_WRITE_ENABLE            0x06
+#define EXFLASH_FAST_READ               0x0B
+#define EXFLASH_SECTOR_ERASE            0x20
+#define EXFLASH_READ_STATUS_REG_HIGH    0x35
+#define EXFLASH_BLOCK_ERASE_32KB        0x52
+#define EXFLASH_BLOCK_ERASE_64KB        0xD8
+#define EXFLASH_CHIP_ERASE              0x60
+#define EXFLASH_READ_MANUFACTURER_ID    0x90
+#define EXFLASH_READ_IDENTIFICATION     0x9F
+
+#define EXFLASH_PAGE_SIZE       (256)
+#define EXFALSH_SIZE_4K         (4*1024)
+#define EXFALSH_SIZE_32K        (32*1024)
+#define EXFALSH_SIZE_64K		(64*1024)
+#define EXFALSH_SIZE_MAX		(2*1024*1024)
+
+//////////////////////////// Function Declarations  ///////////////////////////
+
+/**
+ * @brief Configurate baudrate of the External FLASH interface.
+ *
+ * @param baud like 1000000
+ */
+void ExFlash_Init(uint32_t baud);
+
+/**
+ * @brief Deinit the interface of FLASH.
+ */
+void ExFlash_Deinit(void);
+
+/**
+ * @brief Read Manufacture ID/Device ID (REMS) (90H)
+ *
+ * @return uint16_t MSB is Manufacturer ID, LSB is Device ID.
+ */
+uint16_t ExFlash_Read_ManufactureID(void);
+
+/**
+ * @brief Read FLASH Status Register all 16 bits.
+ *
+ * @return uint16_t FLASH status.
+ */
+uint16_t ExFlash_Read_Status(void);
+
+/**
+ * @brief Read Identification (RDID, 0x9F)
+ *
+ * @return uint32_t identification
+ */
+uint32_t ExFlash_Read_Identification(void);
+
+/**
+ * @brief The WREN command is for setting the Write Enable Latch bit, which
+ * must be set prior to every Page Program, Sector Erase, Block Erase, Chip
+ * Erase and Write Status Register command.
+ *
+ */
+void ExFlash_Write_Enable(void);
+
+/**
+ * @brief The WRDI command is for setting the Write Enable Latch (WEL) bit.
+ * The WEL bit is reset by following condition: Power-up and upon completion
+ * of the Write Status Register, Page Program, Sector Erase, Block Erase and
+ * Chip Erase commands.
+ *
+ */
+void ExFlash_Write_Disable(void);
+
+/**
+ * @brief Read data from FLASH.
+ *
+ * @param addr start address
+ * @param length how many bytes to read
+ * @param recv_buf receive buffer
+ * @return int8_t return 0 on success; return others on failure.
+ */
+int8_t ExFlash_Read_Data_Bytes(uint32_t addr, uint8_t *recv_buf, uint32_t length);
+
+/**
+ * @brief Erase all data of the chip.
+ */
+void ExFlash_Chip_Erase(void);
+
+/**
+ * @brief Program one page.
+ *
+ * @param addr  start of address of one page.
+ * @param data  data
+ * @param length length of data.
+ */
+void ExFlash_Page_Program(uint32_t addr, uint8_t *data, uint16_t length);
+
+/**
+ * @brief Program at any address inside the FLASH address space.
+ *
+ * @param offset start address
+ * @param length how many bytes to program
+ * @param buffer start address of the buffer
+ */
+void ExFlash_Program(uint32_t offset, uint8_t *buffer, uint32_t length);
+
+/**
+ * @brief Read Data Bytes at Higher Speed (Fast Read).
+ *
+ * @param addr start address to read
+ * @param length how many bytes to read
+ * @param recv_buf receive buffer
+ * @return int8_t return 0 on success; return others on failure.
+ */
+int8_t ExFlash_Fast_Read(uint32_t addr, uint8_t *recv_buf, uint32_t length);
+
+/**
+ * @brief Erase an sector at which the addr is located.
+ *
+ * @param addr Any addrss inside the sector is a valid address for
+ *              the Sector Erase command.
+ */
+void ExFlash_Erase_Sector(uint32_t addr);
+
+/**
+ * @brief Block erase by 32KB or 64KB according to type.
+ *
+ * @param addr Any address inside the block is a valid address for the block erase command.
+ * @param type to indicate a 32KB or 64KB block erase.
+ */
+void ExFlash_Erase_Block(uint32_t addr, uint8_t type);
+
+/**
+ * @brief Erase flash start from offset.
+ *
+ * @param offset start address inside the external FLASH.
+ * @param length how many bytes to erase.
+ */
+void ExFlash_Erase(uint32_t offset, uint32_t length);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __EXFLASH_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/flash.h

@@ -0,0 +1,132 @@
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+#include "types.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/****************************  Data types and Macros  ************************/
+#define FLASH_QUAD_READ_DUMMY_CLOCKS    8
+
+#define FLASH_SECURITY_SIZE_MAX  (4*256)
+#define FLASH_SECURITY_PAGE_SIZE (256)
+        
+#define FLASH_PAGE_SIZE         (256)
+#define FALSH_SIZE_4K           (4 *1024)
+#define FALSH_SIZE_BLOCK_32K    (32*1024)
+#define FALSH_SIZE_BLOCK_64K    (64*1024)
+#define FALSH_SIZE_MAX		    (2 *1024*1024)
+
+
+typedef enum
+{
+    FLASH_WRITE_NON_VOLATILE_SR = 0x01,
+    FLASH_WRITE_VOLATILE_SR     = 0x50,
+    FLASH_READ_STATUS_REG_1   = 0x05,
+    FLASH_READ_STATUS_REG_2   = 0x35,
+                              
+    FLASH_WRITE_DISABLE       = 0x04,
+    FLASH_WRITE_ENABLE        = 0x06,
+                              
+    FLASH_STANDARD_READ       = 0x03,
+    FLASH_DUAL_FAST_READ      = 0x3B,
+    FLASH_QUAD_FAST_READ      = 0x6B,
+                              
+    FLASH_PAGE_PROGRAM        = 0x02,
+    FLASH_QUAD_PAGE_PROGRAMM  = 0x32,
+                              
+    FLASH_SECTOR_ERASE        = 0x20,
+    FLASH_32KB_BLOCK_ERASE    = 0x52,
+    FLASH_64KB_BLOCK_ERASE    = 0xd8,
+    FLASH_CHIP_ERASE          = 0x60,//0x60 or 0xc7
+                              
+    FLASH_SUSPEND             = 0x75,//Program/Erase Suspend
+    FLASH_RESUME              = 0x7A,//Program/Erase Resume
+    FLASH_READ_ID             = 0x9F,//Read Identification
+    FLASH_READ_DEVICE_ID      = 0x90,//Read Manufacture ID/Device ID
+    
+    FLASH_SECURITY_ERASE      = 0x44,
+    FLASH_SECURITY_PROGRAM    = 0x42,
+    FLASH_SECURITY_READ       = 0x48,
+
+    FLASH_POWER_DOWN          = 0xB9,
+    FLASH_POWER_ON            = 0xAB,
+} Flash_Cmd_t;
+
+typedef enum
+{
+    NORMAL_AREA = 0,
+    SECURITY_AREA,   
+} Flash_AreaType;
+
+
+typedef union
+{
+  struct
+  {
+      uint8_t WIP   : 1;//Write  In Progress
+      uint8_t WEL   : 1;//Write  Enable Latch
+      uint8_t BP0_4 : 5;//Block  Protect
+      uint8_t SRP   : 1;//Status Register Protect        
+  }bits;
+  uint8_t reg1_data;
+} FlashStatusReg1_t;
+
+typedef union
+{
+  struct
+  {
+      uint8_t Res1  : 1;// 
+      uint8_t QE    : 1;//Quad Enable
+      uint8_t LB    : 1;//One Time Program   
+      uint8_t Res2  : 3;// 
+      uint8_t CMP   : 1;// 
+      uint8_t Res3  : 1;
+  }bits;
+  uint8_t reg2_data;
+} FlashStatusReg2_t;
+
+
+typedef enum
+{
+    ERASE_SECTOR_4KB,
+    ERASE_BLOCK_32KB,
+    ERASE_BLOCK_64KB,
+    ERASE_CHIP,
+}Flash_EraseType_t;
+
+
+/****************************  FLASH API  **************************/
+void     FLASH_Init(void);
+void     FLASH_Deinit(void);
+uint8_t  FLASH_ReadByCache(uint32_t offset, uint32_t length, uint8_t *buffer);
+uint8_t  FLASH_Read(uint32_t offset, uint32_t length, uint8_t *buffer);
+uint8_t  FLASH_Program(uint32_t offset, uint32_t length, uint8_t *buffer);
+void     FLASH_Erase(uint32_t offset, uint32_t length);//@param: offset,length(Note:4K Aligned)
+void     FLASH_ChipErase(void);
+uint8_t  FLASH_QuadProgram(uint32_t offset, uint32_t length, uint8_t *buffer);
+uint32_t FLASH_ReadID(void);
+uint16_t FLASH_ReadDeviceID(void);
+uint8_t  FLASH_ReadSR1(void);
+uint8_t  FLASH_ReadSR2(void);
+uint16_t FLASH_ReadStatus(void);
+void     FLASH_ProgramEraseSuspend(void);
+void     FLASH_ProgramEraseResume(void);
+void     FLASH_WriteEnable(void);
+void     FLASH_WriteDisable(void);
+void     FLASH_LockOTP(void);
+uint8_t  FLASH_GetOTPState(void);
+void     FLASH_QuadModeEnable(uint8_t enable);
+void     FLASH_OperationWait(void);
+
+void     FLASH_SecurityAreaErase(uint32_t offset);
+uint8_t  FLASH_SecurityAreaProgram(uint32_t offset, uint32_t len, uint8_t * buf);
+void     FLASH_SecurityAreaRead(uint32_t offset, uint32_t len, uint8_t * buf);
+
+
+#ifdef __cplusplus
+    }
+#endif // __cplusplus
+#endif // __FLASH_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_adc.h

@@ -0,0 +1,198 @@
+#ifndef __HAL_ADC_LN882X_H__
+#define __HAL_ADC_LN882X_H__
+
+#include "types.h"
+#include "ln88xx.h"
+#include "ll/ll_adc.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////     Macros and Constants   //////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+#define IS_ADC_ALL_PERIPH(PERIPH)   ( (PERIPH) == ADC )
+
+typedef enum {FDISABLE = 0, FENABLE = !FDISABLE} FunctionalState;
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == FDISABLE) || ((STATE) == FENABLE))
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////          DataTypes    ///////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+typedef struct
+{
+
+    FunctionalState ADC_Autoff;             /*!< When AUTOFF = 1, the ADC is always powered off when not converting
+                                                and automatically wakes-up when a conversion is started (by software
+                                                or hardware trigger) */
+    FunctionalState ADC_WaitMode;           /*!< When WaitMode = 1, a new conversion can start only if the previous
+                                                data has been treated, once the ADC_DR register has been read or if the
+                                                EOC bit has been cleared. */
+
+    FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+                                                Continuous or Single mode.
+                                                This parameter can be set to FENABLE or FDISABLE */
+    // TODO:
+    // uint32_t        ADC_ExternalTrigConv;   /*!< Defines the external trigger used to start the analog to digital conversion of regular channels. */
+
+    uint32_t        ADC_DataAlign;          /*!< Specifies whether the ADC data alignment is left or right.
+                                                This parameter can be a value of @ref ADC_data_align. */
+} ADC_InitTypeDef;
+
+
+#define ADC_DataAlign_Right     (0)
+#define ADC_DataAlign_Left      (1)
+#define IS_ADC_DATA_ALIGN(align)    ( ((align) == ADC_DataAlign_Right) || \
+                                    ((align) == ADC_DataAlign_Left) )
+
+
+#define ADC_IT_AWD              (0x0400)
+#define ADC_IT_OVR              (0x0200)
+#define ADC_IT_EOS              (0x0100)
+#define ADC_IT_EOC(chan_map)    ((chan_map) & 0xFF)
+#define IS_ADC_IT(it)           ( ((it) & ADC_IT_AWD) || \
+                                ((it) & ADC_IT_OVR) || \
+                                ((it) & ADC_IT_EOS) || \
+                                ADC_IT_EOC(it) )
+
+typedef enum {
+    ADC_CHAN_0 = (0x01),
+    ADC_CHAN_1 = (0x02),
+    ADC_CHAN_2 = (0x04),
+    ADC_CHAN_3 = (0x08),
+    ADC_CHAN_4 = (0x10),
+    ADC_CHAN_5 = (0x20),
+    ADC_CHAN_6 = (0x40),
+    ADC_CHAN_7 = (0x80),
+    ADC_CHAN_MAX = 8
+} adc_chan_t;
+#define IS_ADC_CHANMAP(chmap)   ( (chmap) & 0xFF )
+#define IS_ADC_CHANX(chx)       (((chx) == ADC_CHAN_0) || \
+                                ((chx) == ADC_CHAN_1) || \
+                                ((chx) == ADC_CHAN_2) || \
+                                ((chx) == ADC_CHAN_3) || \
+                                ((chx) == ADC_CHAN_4) || \
+                                ((chx) == ADC_CHAN_5) || \
+                                ((chx) == ADC_CHAN_6) || \
+                                ((chx) == ADC_CHAN_7) )
+
+#define ADC_OVERSAMPLE_2X       (0x00)
+#define ADC_OVERSAMPLE_4X       (0x01)
+#define ADC_OVERSAMPLE_8X       (0x02)
+#define ADC_OVERSAMPLE_16X      (0x03)
+#define ADC_OVERSAMPLE_32X      (0x04)
+#define ADC_OVERSAMPLE_64X      (0x05)
+#define IS_ADC_OVERSAMPLE(ovsr)     ( ((ovsr) == ADC_OVERSAMPLE_2X) || \
+                                    ((ovsr) == ADC_OVERSAMPLE_4X) || \
+                                    ((ovsr) == ADC_OVERSAMPLE_8X) || \
+                                    ((ovsr) == ADC_OVERSAMPLE_16X) || \
+                                    ((ovsr) == ADC_OVERSAMPLE_32X) || \
+                                    ((ovsr) == ADC_OVERSAMPLE_64X) )
+
+
+// #define ADC_EXTTRIG_DISABLE         (0)
+// #define ADC_EXTTRIG_RISING_EDGE     (1)
+// #define ADC_EXTTRIG_FALLING_EDGE    (2)
+// #define ADC_EXTTRIG_BOTH_EDGE       (3)
+
+typedef enum {
+    ADC_EXTTRIG_DISABLE = 0,
+    ADC_EXTTRIG_RISING_EDGE = 1,
+    ADC_EXTTRIG_FALLING_EDGE = 2,
+    ADC_EXTTRIG_BOTH_EDGE = 3
+} ADC_ExtTrig_t;
+
+#define IS_ADC_EXTTRIG(trig)    (((trig) == ADC_EXTTRIG_DISABLE) || \
+                                ((trig) == ADC_EXTTRIG_RISING_EDGE) || \
+                                ((trig) == ADC_EXTTRIG_FALLING_EDGE) || \
+                                ((trig) == ADC_EXTTRIG_BOTH_EDGE))
+
+typedef enum
+{
+    ADC_EXTTRIG_SEL_TRG0 = 0,
+    ADC_EXTTRIG_SEL_TRG1 = 1,
+    ADC_EXTTRIG_SEL_TRG2 = 2,
+    ADC_EXTTRIG_SEL_TRG3 = 3,
+} ADC_ExtTrigSel_t;
+
+#define IS_ADC_EXT_TRIG(exttrig)    (((exttrig) == (ADC_EXTTRIG_SEL_TRG0)) || \
+                                    ((exttrig) == (ADC_EXTTRIG_SEL_TRG1)) || \
+                                    ((exttrig) == (ADC_EXTTRIG_SEL_TRG2)) || \
+                                    ((exttrig) == (ADC_EXTTRIG_SEL_TRG3)))
+
+
+#define IS_ADC_PRESC(presc)         ((presc) <= 63)
+
+
+typedef struct
+{
+    uint8_t isSingle;   /*!< watch on single channel or all selected channels */
+    adc_chan_t chanX;      /*!< single channel to watch, this chan must be in the active selected channels */
+} AnalogWatchDogCfg_t;
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////          Functions    ///////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+void HAL_ADC_DeInit(ADC_Instance* ADCx);
+
+void HAL_ADC_Init(ADC_Instance* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+
+void HAL_ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+
+void HAL_ADC_Cmd(ADC_Instance* ADCx, FunctionalState NewState);
+
+void HAL_ADC_ITConfig(ADC_Instance* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+
+void HAL_ADC_SoftwareStartConvCmd(ADC_Instance* ADCx);
+
+void HAL_ADC_StopConvCmd(ADC_Instance *ADCx);
+
+uint8_t HAL_ADC_GetSoftwareStartConvStatus(ADC_Instance* ADCx);
+
+void HAL_ADC_WaitModeCmd(ADC_Instance *ADCx, FunctionalState NewState);
+
+void HAL_ADC_DiscModeCmd(ADC_Instance* ADCx, FunctionalState NewState);
+
+void HAL_ADC_SeqChanSelect_Cfg(ADC_Instance *ADCx, uint8_t chan_map);
+
+void HAL_ADC_RegularChannelConfig(ADC_Instance* ADCx, uint8_t Chan_map, uint8_t ratio);
+
+void HAL_ADC_ExternalTrigConvCmd(ADC_Instance* ADCx, uint8_t exttrigcfg);
+
+uint16_t HAL_ADC_GetConversionValue(ADC_Instance* ADCx, uint8_t ChanX);
+
+void HAL_ADC_AnalogWatchdogCfg(ADC_Instance* ADCx, AnalogWatchDogCfg_t *cfg);
+
+void HAL_ADC_AnalogWatchdogThresholdsConfig(ADC_Instance* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+
+void HAL_ADC_PrescCfg(ADC_Instance *ADCx, uint8_t presc);
+
+uint16_t HAL_ADC_GetAllIT_Status(ADC_Instance *ADCx);
+
+uint8_t HAL_ADC_IT_IsAnaWatchDog(ADC_Instance *ADCx);
+
+uint8_t HAL_ADC_IT_IsOverrun(ADC_Instance *ADCx);
+
+uint8_t HAL_ADC_IT_IsEndofSeq(ADC_Instance *ADCx);
+
+uint8_t HAL_ADC_IT_EndOfConv_Status(ADC_Instance *ADCx);
+
+void HAL_ADC_IT_ClrAll(ADC_Instance *ADCx);
+
+void HAL_ADC_IT_Clr_AnaWatchDog(ADC_Instance *ADCx);
+
+void HAL_ADC_IT_Clr_Overrun(ADC_Instance *ADCx);
+
+void HAL_ADC_IT_Clr_EndOfSeq(ADC_Instance *ADCx);
+
+void HAL_ADC_IT_Clr_EndOfConv(ADC_Instance *ADCx);
+
+#ifdef __cplusplus
+    }
+#endif
+#endif //!__HAL_ADC_LN882X_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_aes.h

@@ -0,0 +1,284 @@
+#ifndef _HAL_AES_H_
+#define _HAL_AES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define AES_LITTLE_ENDIAN   0x00000100
+#define AES_MAX_KEY_LENGTH  32
+#define AES_IT_DATAINT      0x4
+#define AES_IT_KEYINT       0x2
+#define AES_IT_BUSY         0x1
+#define AES_IT_ALL          0x7
+#define AES_CRYPTO_KEYEXP   0x2
+#define CONFIG_AES_NUM      1 
+#define AES_WORK_ENABLE_OFFSET  0
+#define AES_INT_KEY_OFFSET      1
+#define AES_INT_ENABLE_OFFSET   2
+#define AES_MODE_OFFSET         3
+#define AES_KEY_LEN_OFFSET      4
+#define AES_OPCODE_OFFSET       6
+#define __IOM    volatile 
+#define AES   (void*)REG_AES_BASE
+#define DRV_ERRNO_AES_BASE      0x40400000
+  
+typedef enum {
+    DRV_ERROR = 1,//ERRNO_DRV_START,   ///< Unspecified error
+    DRV_ERROR_BUSY,                ///< Driver is busy
+    DRV_ERROR_TIMEOUT,             ///< Timeout occurred
+    DRV_ERROR_UNSUPPORTED,         ///< Operation not supported
+    DRV_ERROR_PARAMETER,           ///< Parameter error
+    DRV_ERROR_SPECIFIC             ///< Start of driver specific errors
+} drv_err_e;
+    
+typedef enum  {
+    DRV_POWER_OFF,                        ///< Power off: no operation possible
+    DRV_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+    DRV_POWER_FULL,                       ///< Power on: full operation at maximum performance
+    DRV_POWER_SUSPEND,                    ///< Power suspend: power saving operation
+} aes_power_stat_e;
+
+typedef void *aes_handle_t;
+typedef enum {
+    AES_CRYPTO_MODE_ENCRYPT                  = 0,   ///< encrypt Mode
+    AES_CRYPTO_MODE_DECRYPT,                        ///< decrypt Mode
+} aes_crypto_mode_e;
+typedef enum {
+    AES_KEY_LEN_BITS_128        = 0,      ///< 128 Data bits
+    AES_KEY_LEN_BITS_192,                 ///< 192 Data bits
+    AES_KEY_LEN_BITS_256                  ///< 256 Data bits
+} aes_key_len_bits_e;
+
+typedef struct {
+    __IOM uint32_t DATAIN[4];                 /* Offset: 0x000 (R/W) Data input 0~127 */
+    __IOM uint32_t KEY[8];                    /* Offset: 0x010 (R/W) Key 0~255 */
+    __IOM uint32_t IV[4];                     /* Offset: 0x030 (R/W) Initial Vector: 0~127 */
+    __IOM uint32_t CTRL;                      /* Offset: 0x040 (R/W) AES Control Register */
+    __IOM uint32_t STATE;                     /* Offset: 0x044 (R/W) AES State Register */
+    __IOM uint32_t DATAOUT[4];                /* Offset: 0x048 (R/W) Data Output 0~31 */
+} aes_reg_t;
+
+/****** AES specific error codes *****/
+typedef enum {
+    AES_ERROR_MODE  = (DRV_ERROR_SPECIFIC + 1),        ///< Specified Mode not supported
+    AES_ERROR_DATA_BITS,                               ///< Specified number of Data bits not supported
+    AES_ERROR_ENDIAN                                   ///< Specified endian not supported
+} aes_error_e;
+
+/*----- AES Control Codes: Mode -----*/
+typedef enum {
+    AES_MODE_ECB                  = 0,   ///< ECB Mode
+    AES_MODE_CBC,                        ///< CBC Mode
+    AES_MODE_CFB1,                       ///< CFB1 Mode
+    AES_MODE_CFB8,                       ///< CFB8 Mode
+    AES_MODE_CFB128,                     ///< CFB128 Mode
+    AES_MODE_OFB,                        ///< OFB Mode
+    AES_MODE_CTR                         ///< CTR Mode
+} aes_mode_e;
+
+/*----- AES Control Codes: Mode Parameters: Endian -----*/
+typedef enum {
+    AES_ENDIAN_LITTLE          = 0,       ///< Little Endian
+    AES_ENDIAN_BIG                        ///< Big Endian
+} aes_endian_mode_e;
+
+/**
+\brief AES Status
+*/
+typedef struct {
+    uint32_t busy             : 1;        ///< busy flag
+} aes_status_t;
+
+/****** AES Event *****/
+typedef enum {
+    AES_EVENT_CRYPTO_COMPLETE    = 0   ///< Encrypt completed
+} aes_event_e;
+typedef void (*aes_event_cb_t)(int32_t idx, aes_event_e event);   ///< Pointer to \ref aes_event_cb_t : AES Event call back.
+
+
+/**
+\brief AES Device Driver Capabilities.
+*/
+typedef struct {
+    uint32_t ecb_mode           : 1;      ///< supports ECB mode
+    uint32_t cbc_mode           : 1;      ///< supports CBC mode
+    uint32_t cfb1_mode          : 1;      ///< supports CFB1 mode
+    uint32_t cfb8_mode          : 1;      ///< supports CFB8 mode
+    uint32_t cfb128_mode        : 1;      ///< supports CFB128 mode
+    uint32_t ofb_mode           : 1;      ///< supports OFB mode
+    uint32_t ctr_mode           : 1;      ///< supports CTR mode
+    uint32_t bits_128           : 1;      ///< supports 128bits key length
+    uint32_t bits_192           : 1;      ///< supports 192bits key length
+    uint32_t bits_256           : 1;      ///< supports 256bits key length
+} aes_capabilities_t;
+
+
+// Function documentation
+
+/**
+  \brief       aes_interrupt_handler 
+  \param[in]   idx   device id
+  \param[in]   event  interrupt event  type
+  \return      NULL
+*/
+void aes_interrupt_handler(int32_t idx, aes_event_e event);
+/**
+  \brief       Initialize AES Interface. 1. Initializes the resources needed for the AES interface 2.registers event callback function
+  \param[in]   idx   device id
+  \param[in]   cb_event  event callback function \ref aes_event_cb_t
+  \return      if success return aes handle else return NULL
+*/
+aes_handle_t hal_aes_initialize(int32_t idx, aes_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize AES Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  aes handle to operate.
+  \return      error code
+*/
+int32_t hal_aes_uninitialize(aes_handle_t handle);
+
+/**
+  \brief       control aes power.
+  \param[in]   handle  aes handle to operate.
+  \param[in]   state   power state.\ref aes_power_stat_e.
+  \return      error code
+*/
+#ifdef CONFIG_LPM
+int32_t hal_aes_power_control(aes_handle_t handle, aes_power_stat_e state);
+#endif
+/**
+  \brief       Get driver capabilities.
+  \param[in]   idx device id
+  \return      \ref aes_capabilities_t
+*/
+aes_capabilities_t hal_aes_get_capabilities(int32_t idx);
+
+/**
+  \brief       config aes mode.
+  \param[in]   handle  aes handle to operate.
+  \param[in]   mode      \ref aes_mode_e
+  \param[in]   keylen_bits \ref aes_key_len_bits_e
+  \param[in]   endian    \ref aes_endian_mode_e
+  \return      error code
+*/
+int32_t hal_aes_config(aes_handle_t handle,
+                       aes_mode_e mode,
+                       aes_key_len_bits_e keylen_bits,
+                       aes_endian_mode_e endian
+                      );
+
+/**
+  \brief       set crypto key.
+  \param[in]   handle    aes handle to operate.
+  \param[in]   context   aes information context
+  \param[in]   key       Pointer to the key buf
+  \param[in]   key_len   Pointer to \ref aes_key_len_bits_e
+  \param[in]   enc       \ref aes_crypto_mode_e
+  \return      error code
+*/
+int32_t hal_aes_set_key(aes_handle_t handle, void *context, void *key, aes_key_len_bits_e key_len, aes_crypto_mode_e enc);
+
+/**
+  \brief       aes ecb encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \return      error code
+*/
+int32_t hal_aes_ecb_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len);
+
+/**
+  \brief       aes cbc encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \param[in]   iv   Pointer to initialization vector
+  \return      error code
+*/
+int32_t hal_aes_cbc_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16]);
+
+/**
+  \brief       aes cfb1 encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \param[in]   iv   Pointer to initialization vector
+  \return      error code
+*/
+int32_t hal_aes_cfb1_crypto(aes_handle_t handle, void *context, void *in, void *out,  uint32_t len, uint8_t iv[16]);
+
+/**
+  \brief       aes cfb8 encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \param[in]   iv   Pointer to initialization vector
+  \return      error code
+*/
+int32_t hal_aes_cfb8_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16]);
+
+/**
+  \brief       aes cfb128 encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \param[in]   iv   Pointer to initialization vector
+  \param[in]   num  the number of the 128-bit block we have used
+  \return      error code
+*/
+int32_t hal_aes_cfb128_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16], uint32_t *num);
+
+/**
+  \brief       aes ofb encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \param[in]   iv   Pointer to initialization vector
+  \param[in]   num  the number of the 128-bit block we have used
+  \return      error code
+*/
+int32_t hal_aes_ofb_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16], uint32_t *num);
+
+/**
+  \brief       aes ctr encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \param[in]   nonce_counter   Pointer to the 128-bit nonce and counter
+  \param[in]   stream_block  Pointer to the saved stream-block for resuming
+  \param[in]   num  the number of the 128-bit block we have used
+  \return      error code
+*/
+int32_t hal_aes_ctr_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t nonce_counter[16], uint8_t stream_block[16], uint32_t *num);
+
+/**
+  \brief       Get AES status.
+  \param[in]   handle  aes handle to operate.
+  \return      AES status \ref aes_status_t
+*/
+aes_status_t hal_aes_get_status(aes_handle_t handle);
+
+void aes_irqhandler(int32_t idx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_AES_H_ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_common.h

@@ -0,0 +1,46 @@
+#ifndef __HAL_COMMON_H_
+#define __HAL_COMMON_H_
+
+#ifdef __cpluscplus
+    extern "C" {
+#endif // __cpluscplus
+
+#include "proj_config.h"
+#include "stdint.h"
+        
+//---------------------HAL define------------------------------
+typedef enum 
+{
+	HAL_OK       = 0x00,
+	HAL_ERROR    = 0x01,
+	HAL_BUSY     = 0x02,
+	HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+typedef enum 
+{
+	HAL_UNLOCKED = 0x00,
+	HAL_LOCKED   = 0x01  
+} HAL_LockTypeDef;
+
+        
+#if (FULL_ASSERT == ENABLE)
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+    void assert_failed(uint8_t* file, uint32_t line);
+    #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+#else
+    #define assert_param(expr) ((void)0U)
+#endif /* FULL_ASSERT */  
+
+
+#ifdef __cpluscplus
+    }
+#endif // __cpluscplus
+#endif // __HAL_COMMON_H_

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_dma.h

@@ -0,0 +1,381 @@
+#ifndef __HAL_DMA_H_
+#define __HAL_DMA_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/******************************  Data Type and Macros  **********************/
+
+/**
+ * @brief enum to enable/disable DMA controller.
+ *
+ */
+typedef enum 
+{
+    DMAC_DISABLE = 0,
+    DMAC_ENABLE
+} DMAC_Enable;
+
+/**
+ * @brief
+ *
+ */
+typedef enum 
+{
+    DMA_CHANNEL_0   = 0x01,
+    DMA_CHANNEL_1   = 0x02,
+    DMA_CHANNEL_2   = 0x04,
+    DMA_CHANNEL_NUM = 0x03
+} DMA_Channel;
+
+
+/**
+ * @brief enum of DMA_Int_En to enable or disable DMA interrupt.
+ *
+ */
+typedef enum 
+{
+    DMA_INTERRUPT_DISABLE   = 0,
+    DMA_INTERRUPT_ENABLE
+} DMA_Int_En;
+
+/**
+ * @brief Handshake ploarity.
+ *
+ */
+typedef enum 
+{
+    DMA_HS_POLARITY_ACTIVE_HIGH = 0,
+    DMA_HS_POLARITY_ACTIVE_LOW
+} DMA_Handshake_Polarity;
+
+/**
+ * @brief Select handshake interface to software or hardware.
+ *
+ */
+typedef enum 
+{
+    DMA_HANDSHAKE_HARDWARE = 0,
+    DMA_HANDSHAKE_SOFTWARE
+} DMA_Handshake_Source;
+
+/**
+ * @brief Channel Suspend.
+ * 0 -- Not suspended.
+ * 1 -- Suspend DMA transfer from the source.
+ */
+typedef enum 
+{
+    DMA_CHAN_SUSPEND_NO = 0,
+    DMA_CHAN_SUSPEND_YES
+} DMA_Chan_Suspend;
+
+/**
+ * @brief enum of transfer width.
+ *
+ */
+typedef enum 
+{
+    DMA_TRANSFER_WIDTH_8_BITS   = 0,
+    DMA_TRANSFER_WIDTH_16_BITS,
+    DMA_TRANSFER_WIDTH_32_BITS,
+    DMA_TRANSFER_WIDTH_64_BITS,
+    DMA_TRANSFER_WIDTH_128_BITS,
+    DMA_TRANSFER_WIDTH_256_BITS
+} DMA_Src_Dst_Width;
+
+/**
+ * @brief Define the address increasement of source or destination device.
+ * when working in memory to memory mode, source and destination address are all set to DMA_ADDRESS_INCREMENT;
+ * when working in memory to peripheral mdoe, source address is set to DMA_ADDRESS_INCREMENT and destination is set to DMA_ADDRESS_UNCHANGE;
+ * when working in peripheral to memory mode, destination address is set to DMA_ADDRESS_INCREMENT and source address is set to DMA_ADDRESS_UNCHANGE.
+ *
+ */
+typedef enum 
+{
+    DMA_ADDRESS_INCREMENT = 0,
+    DMA_ADDRESS_DECREMENT,
+    DMA_ADDRESS_UNCHANGE
+} DMA_Sinc_Dinc;
+
+/**
+ * @brief Set the burst transaction length. The threashold to request of DMA transfer in peripheral should be less than the length set here.
+ * Normally, the threshold = msize - 1. For example, msize = DMA_BURST_TRANSACTION_LENGTH_4, then the threshold should set to 3.
+ *
+ */
+typedef enum 
+{
+    DMA_BURST_TRANSACTION_LENGTH_1  = 0,
+    DMA_BURST_TRANSACTION_LENGTH_4,
+    DMA_BURST_TRANSACTION_LENGTH_8,
+    DMA_BURST_TRANSACTION_LENGTH_16,
+    DMA_BURST_TRANSACTION_LENGTH_32,
+    DMA_BURST_TRANSACTION_LENGTH_64,
+    DMA_BURST_TRANSACTION_LENGTH_128,
+    DMA_BURST_TRANSACTION_LENGTH_256
+} DMA_Src_Dst_Msize;
+
+/**
+ * @brief Set the DMA Transfer Type.
+ *
+ */
+typedef enum 
+{
+    DMA_TRANS_TYPE_MEMORY_TO_MEMORY_DMAC_FLOW_CONTROLLER    = 0,
+    DMA_TRANS_TYPE_MEMORY_TO_PERIPHERAL_DMAC_FLOW_CONTROLLER,
+    DMA_TRANS_TYPE_PERIPHERAL_TO_MEMORY_DMAC_FLOW_CONTROLLER
+} DMA_Transfer_Type;
+
+/**
+ * @brief Set the device type.
+ *
+ */
+typedef enum 
+{
+    DMA_DEVICE_QSPI_RX = 0,
+    DMA_DEVICE_QSPI_TX,
+    DMA_DEVICE_UART0_TX,
+    DMA_DEVICE_UART0_RX,
+    DMA_DEVICE_UART1_TX,
+    DMA_DEVICE_UART1_RX,
+    DMA_DEVICE_SPIM_TX,
+    DMA_DEVICE_SPIM_RX,
+    DMA_DEVICE_SPIS_TX,
+    DMA_DEVICE_SPIS_RX,
+    DMA_DEVICE_I2C0_TX,
+    DMA_DEVICE_I2C0_RX,
+    DMA_DEVICE_I2C1_TX,
+    DMA_DEVICE_I2C1_RX,
+    DMA_DEVICE_AUXADC
+} DMA_Dev_Type;
+
+/**
+ * @brief define the bitmap of DMA interrupt.
+ *
+ */
+typedef enum 
+{
+    DMA_INT_STATUS_TFR      = 0x01,
+    DMA_INT_STATUS_BLOCK    = 0x02,
+    DMA_INT_STATUS_SRCTRAN  = 0x04,
+    DMA_INT_STATUS_DSTTRAN  = 0x08,
+    DMA_INT_STATUS_ERR      = 0x10
+} DMA_Int_Status;
+
+#define MAX_DMAC_TRANSFER_SIZE  (4095)
+
+#define DMA_I2C0_RW_ADDRESS     ( (void *)0x40007010 )
+#define DMA_SPIM_RW_ADDRESS     ( (void *)0x40005060 )
+#define DMA_UART0_RW_ADDRESS    ( (void *)0x40002000 )
+
+typedef struct 
+{
+    DMA_Dev_Type device;        /**< device: select which device need to perform a DMA operation */
+    DMA_Transfer_Type type;     /**< type: define the DMA transfer type */
+    DMA_Src_Dst_Msize msize;    /**< msize: define the burst transaction length */
+    DMA_Src_Dst_Width width;    /**< width: define the DMA transfer width */
+    DMA_Sinc_Dinc src_inc;      /**< src_inc: define the source address increasement */
+    DMA_Sinc_Dinc dst_inc;      /**< dst_inc: define the destination address increasement */
+    DMA_Int_En int_en;          /**< int_en: enable or disable the interrupt */
+} DMA_InitTypeDef;
+
+/***************************** sanity check *********************************/
+#define IS_DMAC_ENABLEX(en)     ((en) == DMAC_DISABLE || (en) == DMAC_ENABLE)
+#define IS_DMA_CHANNELS(chan)   ((chan) == DMA_CHANNEL_0 || (chan) == DMA_CHANNEL_1 || (chan) == DMA_CHANNEL_2)
+#define IS_DMA_INT_ENX(en)      ((en) == DMA_INTERRUPT_DISABLE || (en) == DMA_INTERRUPT_ENABLE)
+#define IS_DMA_HS_POLX(pol)     ((pol) == DMA_HS_POLARITY_ACTIVE_HIGH || (pol) == DMA_HS_POLARITY_ACTIVE_LOW)
+#define IS_DMA_HS_SOURCEX(src)  ((src) == DMA_HANDSHAKE_HARDWARE || (src) == DMA_HANDSHAKE_SOFTWARE)
+#define IS_DMA_CHAN_SUSPX(susp) ((susp) == DMA_CHAN_SUSPEND_NO || (susp) == DMA_CHAN_SUSPEND_YES)
+#define IS_DMA_SRCDST_WIDTH(w)  ((w) == DMA_TRANSFER_WIDTH_8_BITS || \
+                                 (w) == DMA_TRANSFER_WIDTH_16_BITS || \
+                                 (w) == DMA_TRANSFER_WIDTH_32_BITS || \
+                                 (w) == DMA_TRANSFER_WIDTH_64_BITS || \
+                                 (w) == DMA_TRANSFER_WIDTH_128_BITS ||\
+                                 (w) == DMA_TRANSFER_WIDTH_256_BITS)
+#define IS_DMA_SINCDINC(inc)    ((inc) == DMA_ADDRESS_INCREMENT || (inc) == DMA_ADDRESS_DECREMENT || (inc) == DMA_ADDRESS_UNCHANGE)
+#define IS_DMA_SRCDST_MSIZE(s)  ((s) == DMA_BURST_TRANSACTION_LENGTH_1 || \
+                                 (s) == DMA_BURST_TRANSACTION_LENGTH_4 || \
+                                 (s) == DMA_BURST_TRANSACTION_LENGTH_8 || \
+                                 (s) == DMA_BURST_TRANSACTION_LENGTH_16 || \
+                                 (s) == DMA_BURST_TRANSACTION_LENGTH_32 || \
+                                 (s) == DMA_BURST_TRANSACTION_LENGTH_64 || \
+                                 (s) == DMA_BURST_TRANSACTION_LENGTH_128 || \
+                                 (s) == DMA_BURST_TRANSACTION_LENGTH_256)
+#define IS_DMA_TT_FC(tt_fc)     ((tt_fc) == DMA_TRANS_TYPE_MEMORY_TO_MEMORY_DMAC_FLOW_CONTROLLER || \
+                                 (tt_fc) == DMA_TRANS_TYPE_MEMORY_TO_PERIPHERAL_DMAC_FLOW_CONTROLLER || \
+                                 (tt_fc) == DMA_TRANS_TYPE_PERIPHERAL_TO_MEMORY_DMAC_FLOW_CONTROLLER)
+#define IS_DMA_DEV_TYPE(dev)    ((dev) == DMA_DEVICE_QSPI_RX || \
+                                 (dev) == DMA_DEVICE_QSPI_TX || \
+                                 (dev) == DMA_DEVICE_UART0_TX || \
+                                 (dev) == DMA_DEVICE_UART0_RX || \
+                                 (dev) == DMA_DEVICE_UART1_TX || \
+                                 (dev) == DMA_DEVICE_UART1_RX || \
+                                 (dev) == DMA_DEVICE_SPIM_TX || \
+                                 (dev) == DMA_DEVICE_SPIM_RX || \
+                                 (dev) == DMA_DEVICE_SPIS_TX || \
+                                 (dev) == DMA_DEVICE_SPIS_RX || \
+                                 (dev) == DMA_DEVICE_I2C0_TX || \
+                                 (dev) == DMA_DEVICE_I2C0_RX || \
+                                 (dev) == DMA_DEVICE_I2C1_TX || \
+                                 (dev) == DMA_DEVICE_I2C1_RX || \
+                                 (dev) == DMA_DEVICE_AUXADC)
+#define IS_DMA_INT_STATUS(st)   ((st) == DMA_INT_STATUS_TFR || \
+                                 (st) == DMA_INT_STATUS_BLOCK || \
+                                 (st) == DMA_INT_STATUS_SRCTRAN || \
+                                 (st) == DMA_INT_STATUS_DSTTRAN || \
+                                 (st) == DMA_INT_STATUS_ERR)
+
+
+/******************************  Function Declaration  **********************/
+
+/**
+ * @brief DMA init.
+ *
+ * @param chanIndex
+ * @param config
+ */
+void HAL_DMA_Init(DMA_Channel chanIndex, DMA_InitTypeDef *config);
+
+/**
+ * @brief DMA Deinit.
+ *
+ * @param chanIndex
+ */
+
+void HAL_DMA_DeInit(DMA_Channel chanIndex);
+
+/**
+ * @brief DMA config.
+ *
+ * @param chanIndex
+ * @param config
+ */
+void HAL_DMA_Config(DMA_Channel chanIndex, DMA_InitTypeDef *config);
+
+/**
+ * @brief Start DMA transfer.
+ *
+ * @param chanIndex DMA channel.
+ * @param src Source address.
+ * @param dst Destination address.
+ * @param length data length.
+ */
+void HAL_DMA_StartTransfer(DMA_Channel chanIndex, void *src, void *dst, uint32_t length);
+
+/**
+ * @brief Wait for DMA transfer to finish.
+ *
+ * @param chanIndex DMA channel.
+ */
+void HAL_DMA_WaitDone(DMA_Channel chanIndex);
+
+/**
+ * @brief Enable/disalbe DMA controller, which must be done before
+ * any channel activity can begin.
+ *
+ * @param enable @see DMAC_Enable.
+ */
+void HAL_DMA_GlobalEnable(DMAC_Enable en);
+
+/**
+ * @brief Software can poll the channel bits to determine when these channl bits
+ * are free for a new DMA transfer.
+ *
+ * @return uint8_t ORed value from these enabled channels.
+ */
+uint8_t HAL_DMA_GetBusyChannel(void);
+
+/**
+ * @brief Interrupt events are stored in these Raw Interrupt Status registers before masking.
+ * Each Raw Interrupt Status register has a bit allocated per channel; for example,
+ * RawTfr[2] is the Channel 2 raw transfer complete interrupt.
+ *
+ * @return uint8_t
+ */
+uint8_t HAL_DMA_RawStatusTfr(void);
+uint8_t HAL_DMA_RawStatusBlock(void);
+uint8_t HAL_DMA_RawStatusSrcTran(void);
+uint8_t HAL_DMA_RawStatusDstTran(void);
+uint8_t HAL_DMA_RawStatusErr(void);
+
+/**
+ * @brief All interrupt events from all channles are stored in these Interrupt
+ * Status registers after masking.
+ * Each Interrupt Status register has a bit allocated per channel: for example,
+ * StatusTfr[2] is the Channel 2 status transfer complete interrupt.
+ *
+ * @return uint8_t
+ */
+uint8_t HAL_DMA_StatusTfr(void);
+uint8_t HAL_DMA_StatusBlock(void);
+uint8_t HAL_DMA_StatusSrcTran(void);
+uint8_t HAL_DMA_StatusDstTran(void);
+uint8_t HAL_DMA_StatusErr(void);
+
+/**
+ * @brief The contents of the Raw Status registers are masked with the contents of the Mask registers.
+ * Each Interrupt Mask register has a bit allocated per channel: for example, MaksTfr[2] is the mask
+ * bit for the Channel 2 transfer complete interrupt.
+ * @param chanIndex
+ */
+void HAL_DMA_UnMaskTfr(DMA_Channel chanIndex);
+void HAL_DMA_UnMaskBlock(DMA_Channel chanIndex);
+void HAL_DMA_UnMaskSrcTran(DMA_Channel chanIndex);
+void HAL_DMA_UnMaskDstTran(DMA_Channel chanIndex);
+void HAL_DMA_UnMaskErr(DMA_Channel chanIndex);
+
+/**
+ * @brief Each Interrupt Clear register has a bit allocated per channel; for example, ClearTfr[2]
+ * is the clear bit for the Channel 2 transfer complete interrupt.
+ *
+ * @param chanIndex
+ */
+void HAL_DMA_ClearTfr(DMA_Channel chanIndex);
+void HAL_DMA_ClearBlock(DMA_Channel chanIndex);
+void HAL_DMA_ClearSrcTran(DMA_Channel chanIndex);
+void HAL_DMA_ClearDstTran(DMA_Channel chanIndex);
+void HAL_DMA_ClearErr(DMA_Channel chanIndex);
+
+/**
+ * @brief Combined Interrupt Status Register.
+ *
+ * @return uint8_t The contents of each of teh five status registers is ORed to produce a single bit for
+ * each interrupt type in the Combined Status register.
+ */
+uint8_t HAL_DMA_IntStatus(void);
+
+// TODO: add annotation here.
+void HAL_DMA_SWSrcTranRequest(DMA_Channel chanIndex);
+
+uint8_t HAL_DMA_SWSrcTranRead(void);
+
+void HAL_DMA_SWDstTranRequest(DMA_Channel chanIndex);
+
+uint8_t HAL_DMA_SWDstTranRead(void);
+
+void HAL_DMA_SingleSrcTranRequest(DMA_Channel chanIndex);
+
+uint8_t HAL_DMA_SingleSrcTranRead(void);
+
+void HAL_DMA_SingleDstTranRequest(DMA_Channel chanIndex);
+
+uint8_t HAL_DMA_SingleDstTranRead(void);
+
+void HAL_DMA_LastSrcTranRequest(DMA_Channel chanIndex);
+
+uint8_t HAL_DMA_LastSrcTranRead(void);
+
+void HAL_DMA_LastDstTranRequest(DMA_Channel chanIndex);
+
+uint8_t HAL_DMA_LastDstTranRead(void);
+
+
+
+
+#ifdef __cplusplus
+    }
+#endif // __cplusplus
+#endif // __HAL_DMA_H_

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_efuse.h

@@ -0,0 +1,72 @@
+#ifndef __HAL_EFUSE_H__
+#define __HAL_EFUSE_H__
+
+#include "ll/ll_efuse.h"
+
+#define IS_EFUSE_ALL_INSTANCES(efusex)  ((efusex) == EFUSE)
+
+typedef enum {
+    EFUSE_REG_0 = 0,
+    EFUSE_REG_1,
+    EFUSE_REG_2,
+    EFUSE_REG_3,
+    EFUSE_REG_4,
+    EFUSE_REG_5,
+    EFUSE_REG_6,
+    EFUSE_REG_7,
+} EFUSE_Reg_Index_t;
+
+#define IS_EFUSE_REG_INDEX(index)   (   ((index) == EFUSE_REG_0) || \
+                                        ((index) == EFUSE_REG_1) || \
+                                        ((index) == EFUSE_REG_2) || \
+                                        ((index) == EFUSE_REG_3) || \
+                                        ((index) == EFUSE_REG_4) || \
+                                        ((index) == EFUSE_REG_5) || \
+                                        ((index) == EFUSE_REG_6) || \
+                                        ((index) == EFUSE_REG_7) )
+
+/**
+ * @brief This function must be called before any EFUSE register writing operations.
+ *
+ * @param EFUSEx
+ */
+void HAL_EFUSE_WriteEnable(EFUSE_Instance * EFUSEx);
+
+/**
+ * @brief Write shadow register, but the effective value is stored in correct register.
+ *
+ * @param EFUSEx
+ * @param regIndex valid value is 0~7.
+ * @param regValue
+ */
+void HAL_EFUSE_WriteShadowReg(EFUSE_Instance * EFUSEx, EFUSE_Reg_Index_t regIndex, uint32_t regValue);
+
+/**
+ * @brief Read from shadow register.
+ *
+ * @param EFUSEx
+ * @param regIndex
+ * @return uint32_t
+ */
+uint32_t HAL_EFUSE_ReadShadowReg(EFUSE_Instance * EFUSEx, EFUSE_Reg_Index_t regIndex);
+
+/**
+ * @brief The effective value is stored in correct register.
+ *
+ * @param EFUSEx
+ * @param regIndex valid value is 0~7.
+ * @return uint32_t
+ */
+uint32_t HAL_EFUSE_ReadCorrectReg(EFUSE_Instance * EFUSEx, EFUSE_Reg_Index_t regIndex);
+
+
+/**
+ * @brief Set one bit to 1.
+ *
+ * @param EFUSEx
+ * @param regIndex valid value is 0~7
+ * @param bitIndex valid value is 0~26
+ */
+void HAL_EFUSE_EnforceBit(EFUSE_Instance * EFUSEx, EFUSE_Reg_Index_t regIndex, uint8_t bitIndex);
+
+#endif // !__HAL_EFUSE_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_gpio.h

@@ -0,0 +1,187 @@
+/**
+****************************************************************************************
+*
+* @file hal_gpio.h
+*
+* @brief gpio driver interface.
+*
+* Copyright (C) LightningSemi electronics 2016-2017
+*
+*
+****************************************************************************************
+*/
+
+
+
+/**
+****************************************************************************************
+* @defgroup GPIO
+* @ingroup DRIVERS
+* @brief GPIO Drivers.
+****************************************************************************************
+*/
+
+#ifndef __HAL_GPIO_H_
+#define __HAL_GPIO_H_
+#include "types.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+
+//////////////////////////////  Data type and Macros  /////////////////////////
+
+#include "ll/ll_gpio.h"
+#include "hal/syscon_types.h"
+
+/**
+ * @brief This is the struct to initialize the gpio module.
+ */
+typedef struct
+{
+    GPIO_Direction  dir;        /**< dir: select GPIO direction */
+    GPIO_Debounce   debounce;   /**< debounce: enable debounce */
+    GPIO_Value      value;      /**< value: set gpio pin value */
+    // Irq releated data
+    GPIO_TrigType   trig_type;  /**< trig_type: set gpio trigger type */
+} GPIO_InitTypeDef;
+
+
+//////////////////////////////  Function Declaration  /////////////////////////
+
+/**
+ * @brief Set the GPIO trigger type.
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @param  type: the GPIO_TrigType, choosing from enum GPIO_TrigType
+ * @return This function has no return.
+ */
+void HAL_GPIO_TrigType(GPIO_Num n, GPIO_TrigType type);
+
+/**
+ * @brief Set the GPIO to trigger a interrupt at both edge, rising and falling.
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @param  enable: enable or disable whether a gpio trigger an interrupt at both edge.
+ * @return This function has no return.
+ */
+void HAL_GPIO_TrigBothEdge(GPIO_Num n, uint8_t enable);
+
+/**
+ * @brief GPIO Initialize.
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @param  config: a struct to initialize a GPIO.
+ * @return This function has no return.
+ */
+void HAL_GPIO_Init(GPIO_Num n, GPIO_InitTypeDef config);
+
+/**
+ * @brief Set GPIO Direction, Input or Output
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @param  dir: choose from GPIO_Direction, GPIO_INPUT or GPIO_OUTPUT
+ * @return This function has no return.
+ */
+void HAL_GPIO_SetDir(GPIO_Num n, GPIO_Direction dir);
+
+/**
+ * @brief Get GPIO Direction, Input or Output
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @return return the direction of the specific gpio
+ */
+GPIO_Direction HAL_GPIO_GetDir(GPIO_Num n);
+
+/**
+ * @brief Enable the interrupt of specific GPIO
+ * @param  n: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void HAL_GPIO_IntEnable(GPIO_Num n);
+
+/**
+ * @brief Disable the interrupt of specific GPIO
+ * @param  n: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void HAL_GPIO_IntDisable(GPIO_Num n);
+
+/**
+ * @brief When GPIO direction is output, write value to set gpio level.
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @param  value: value can be choose from GPIO_Value, GPIO_VALUE_LOW or GPIO_VALUE_HIGH
+ * @return This function has no return.
+ */
+void HAL_GPIO_WritePin(GPIO_Num n, GPIO_Value value);
+
+/**
+ * @brief When GPIO direction is input, read current gpio level.
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @return return the result of current gpio level.
+ */
+GPIO_Value HAL_GPIO_ReadPin(GPIO_Num n);
+
+/**
+ * @brief Toggle a gpio pin
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @return This function has no return.
+ */
+void HAL_GPIO_TogglePin(GPIO_Num n);
+
+/**
+ * @brief Mask the interrupt of specific GPIO, when the interrupt is masked, no interrupt will trigger to CPU
+ * @param  n: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void HAL_GPIO_MaskIrq(GPIO_Num n);
+
+/**
+ * @brief Unmask the interrupt of specific GPIO, when the interrupt is unmasked, the interrupt will trigger to CPU
+ * @param  n: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void HAL_GPIO_UnmaskIrq(GPIO_Num n);
+
+/**
+ * @brief Get all the interrupt status of gpio
+ * @return return all the interrupt status of gpio ranging from GPIOA_0 to GPIOA_20
+ */
+uint32_t HAL_GPIO_IntStatus(void);
+
+/**
+ * @brief Clear the interrupt of specific gpio
+ * @param  n: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void HAL_GPIO_IrqClear(GPIO_Num n);
+
+/**
+ * @brief Controls the polarity of edge or level sensitivity that can occur on GPIO ranging from GPIOA_0 to GPIOA_20
+ * @param  n: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @param  ply: choose from enum GPIO_Polarity to configures the interrupt type to falling-edge or rising-edge.
+ * @return This function has no return.
+ */
+void HAL_GPIO_PolaritySet(GPIO_Num n, GPIO_Polarity ply);
+
+/**
+ * @brief Controls the type of interrupt that can occur on GPIO ranging from GPIOA_0 to GPIOA_20
+ * @param  n: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @param  irqLvl: it configures the interrupt type to be level-sensitive or edge-sensitive.
+ * @return This function has no return.
+ */
+void HAL_GPIO_IrqLevelSet(GPIO_Num n,GPIO_IrqLvl irqLvl);
+
+/**
+ * @brief Controls whether an external signal that is the source of an interrupt needs to be debounced to remove any spurious glitches.
+ * @param  n: the GPIO_Num to define which GPIO to operate.
+ * @return This function has no return.
+ */
+void HAL_GPIO_SetDebounce(GPIO_Num n, GPIO_Debounce debounce);
+
+SYSTEM_EXT_INT_Wakeup_Index HAL_GPIO_Mapping_To_Ext_Int(GPIO_Num gpio);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __HAL_GPIO_H_
+
+/// @} GPIO
+

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_i2c.h

@@ -0,0 +1,266 @@
+#ifndef __HAL_I2C_H__
+#define __HAL_I2C_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+#define I2C_RX_TX_FIFO_DEPTH 16
+
+/**
+ * @brief enum of I2C mode. I2C module can work in master mode or slave mode.
+ */
+typedef enum
+{
+    I2C_SLAVE = 0,
+    I2C_MASTER
+} I2C_Mode_Enum_t;
+
+/**
+ * @brief enum of I2C Speed. I2C module can work at different speed.
+          Normally Standard Mode work in less than 100kbps
+          Fast Mode work in less than 400kbps
+          HighSpeed Mode work in 3.4Mbps
+ */
+typedef enum
+{
+    I2C_STANDARD_MODE = 1,
+    I2C_FAST_MODE,
+    I2C_HIGHSPEED_MODE
+} I2C_SpeedMode_Enum_t;
+
+/**
+ * @brief enum of Special bit.
+           indicates whether software performs a Device-ID, General Call or START BYTE command.
+ */
+typedef enum
+{
+    I2C_NORMALLY = 0,
+    I2C_GENERALCALL_STARTBYTE
+} I2C_Special_Enum_t;
+
+/**
+ * @brief enum of I2C Addressing. Can be select to use 7bit addressing or 10bit addressing
+ */
+typedef enum
+{
+    I2C_7_ADDRESSING = 0,
+    I2C_10_ADDRESSING
+} I2C_7_10Addressing_Enum_t;
+
+/**
+ * @brief enum of int status.
+ */
+typedef enum
+{
+    I2C_INTR_RX_UNDER = 0,
+    I2C_INTR_RX_OVER, // 1
+    I2C_INTR_RX_FULL,
+    I2C_INTR_TX_OVER,
+    I2C_INTR_TX_EMPTY,
+    I2C_INTR_RD_REQ, // 5
+    I2C_INTR_TX_ABORT,
+    I2C_INTR_RX_DONE,
+    I2C_INTR_ACTIVITY,
+    I2C_INTR_STOP_DET,
+    I2C_INTR_START_DET, // 10
+    I2C_INTR_GEN_CALL,
+    I2C_INTR_RESTART_DET,
+    I2C_INTR_MST_ON_HOLD,
+    I2C_INTR_SCL_STUCK_LOW,	//14
+    I2C_INTR_MAX
+} I2C_Int_Status_Enum_t;
+
+/**
+ * @brief enum of tx abort src.
+ */
+typedef enum
+{
+    I2C_ABRT_7BADDR_NOACK = 0,
+    I2C_ABRT_10BADDR1_NOACK,
+    I2C_ABRT_10BADDR2_NOACK,
+    I2C_ABRT_TXDATA_NOACK,
+    I2C_ABRT_GCALL_NOACK,
+    I2C_ABRT_GCALL_READ,        //5
+    I2C_ABRT_HS_ACKDET,
+    I2C_ABRT_SBYTE_ACKDET,
+    I2C_ABRT_HS_NORSTRT,
+    I2C_ABRT_SBYTE_NORSTRT,
+    I2C_ABRT_10B_RD_NORSTRT,    //10
+    I2C_ABRT_MASTER_DIS,
+    I2C_ABRT_ARB_LOST,
+    I2C_ABRT_SLVFLUSH_TXFIFO,
+    I2C_ABRT_SLV_ARBLOST,
+    I2C_ABRT_SLVRD_INTX,        //15
+    I2C_ABRT_USER_ABRT,
+    I2C_ABRT_SDA_STUCK_AT_LOW,
+    I2C_ABRT_DEVICE_NOACK,
+    I2C_ABRT_DEVICE_SLVADDR_NOACK,
+    I2C_ABRT_DEVICE_WRITE       //20
+} I2C_TX_Abort_Src_Enum_t;
+
+/**
+ * @brief enum of int mask.
+ */
+typedef enum
+{
+    I2C_MASK_RX_UNDER = 0,
+    I2C_MASK_RX_OVER,
+    I2C_MASK_RX_FULL,
+    I2C_MASK_TX_OVER,
+    I2C_MASK_TX_EMPTY,
+    I2C_MASK_RD_REQ,        //5
+    I2C_MASK_TX_ABRT,
+    I2C_MASK_RX_DONE,
+    I2C_MASK_ACTIVITY,
+    I2C_MASK_STOP_DET,
+    I2C_MASK_START_DET,     //10
+    I2C_MASK_GEN_CALL,
+    I2C_MASK_RESTART_DET,
+    I2C_MASK_MST_ON_HOLD,
+    I2C_MASK_SCL_STUCK_AT_LOW   //14
+} I2C_Int_Mask_Enum_t;
+
+
+/**
+ * @brief using the default i2c timing parameter or define your own parameter.
+ */
+typedef enum
+{
+    I2C_TIMING_DEFAULT = 0,
+    I2C_TIMING_USER_DEFINE
+} I2C_Timing_Enum_t;
+
+
+/**
+ * @brief This is the struct to initialize the i2c module.
+ */
+typedef struct
+{
+	I2C_Mode_Enum_t mode;                  /**< mode: I2C mode. slave mode or master mode. */
+	uint16_t dev_addr;              /**< dev_addr: I2C slave address indicate */
+	I2C_7_10Addressing_Enum_t addr_type;   /**< addr_type: 7bit or 10bit addressing select */
+	I2C_SpeedMode_Enum_t speed;            /**< speed: select from standard mode, fast mode or high speed mode */
+	I2C_Timing_Enum_t timing;          /**< timing: use default timing or define your own i2c timing */
+	uint8_t restart_en;             /**< restart_en: Determines whether RESTART conditions may be sent when acting as a master */
+} I2C_InitTypeDef;
+
+
+/**
+ * @brief This is the struct to define the i2c timing, only define this when you define your own i2c timing(I2C_TIMING_USER_DEFINE)
+ */
+typedef struct
+{
+    uint16_t ss_scl_hcnt;
+    uint16_t ss_scl_lcnt;
+
+    uint16_t fs_scl_hcnt;
+    uint16_t fs_scl_lcnt;
+
+    uint16_t hs_scl_hcnt;
+    uint16_t hs_scl_lcnt;
+
+    uint16_t ic_sda_rx_hold;
+    uint16_t ic_sda_tx_hold;
+} I2C_Timing_Setting_t;
+
+
+void HAL_I2C_Enable(I2CInstance *i2cX, uint8_t en);
+
+void HAL_I2C_Abort(I2CInstance *i2cX, uint8_t en);
+
+void HAL_I2C_SetMode(I2CInstance *i2cX, I2C_Mode_Enum_t mode);
+
+I2C_Mode_Enum_t HAL_I2C_GetMode(I2CInstance *i2cX);
+
+void HAL_I2C_SetSpecialBit(I2CInstance *i2cX, I2C_Special_Enum_t special);
+
+void HAL_I2C_GeneralCall_OR_Start(I2CInstance *i2cX, uint8_t start);
+
+void HAL_I2C_RestartMode_Enable(I2CInstance *i2cX, uint8_t en);
+
+void HAL_I2C_Set7_10Addressing_Master(I2CInstance *i2cX, I2C_7_10Addressing_Enum_t addr);
+
+void HAL_I2C_Set7_10Addressing_Slave(I2CInstance *i2cX, I2C_7_10Addressing_Enum_t addr);
+
+void HAL_I2C_SetTarAddr(I2CInstance *i2cX, uint16_t addr);
+
+void HAL_I2C_SlaveAddr_Set(I2CInstance *i2cX, uint16_t addr);
+
+void HAL_I2C_Int_Threshold_Set(I2CInstance *i2cX, uint8_t tx_tl, uint8_t rx_tl);
+
+void HAL_I2C_Read_FIFO(I2CInstance *i2cX, uint8_t *buf, uint32_t length);
+
+void HAL_I2C_Data_Cmd_Pack(I2CInstance *i2cX, uint8_t restart, uint8_t stop, uint8_t cmd, uint8_t dat);
+
+void HAL_I2C_ReadData_Polling(I2CInstance *i2cX, uint8_t *buf, uint32_t length);
+
+void HAL_I2C_ReadData(I2CInstance *i2cX, uint32_t length);
+
+void HAL_I2C_Read_LastByte(I2CInstance *i2cX);
+
+uint32_t HAL_I2C_WriteData(I2CInstance *i2cX, uint8_t *buf, uint32_t length);
+
+void HAL_I2C_Write_LastByte(I2CInstance *i2cX, uint8_t buf);
+
+uint32_t HAL_I2C_SendAddrCmd(I2CInstance *i2cX, uint8_t *regAddr, uint8_t len);
+
+uint8_t HAL_I2C_Tx_FIFO_Level(I2CInstance *i2cX);
+
+uint32_t HAL_I2C_TxAbortSource_Get(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_Rx_FIFO_Level(I2CInstance *i2cX);
+
+void HAL_I2C_SetSpeed(I2CInstance *i2cX, uint32_t src_clock, I2C_SpeedMode_Enum_t speedMode, I2C_Timing_Enum_t timing, I2C_Timing_Setting_t *setting);
+
+void HAL_I2C_HighSpeed_MasterAddr_Set(I2CInstance *i2cX, uint8_t maddr);
+
+void HAL_I2C_DMA_Ctrl(I2CInstance *i2cX, uint8_t tx_dma_en, uint8_t rx_dma_en, uint8_t tx_data_level, uint8_t rx_data_level);
+
+void HAL_I2C_HighSpeed_SPKLEN_Set(I2CInstance *i2cX, uint8_t spklen);
+
+void HAL_I2C_FastSpeed_SPKLEN_Set(I2CInstance *i2cX, uint8_t spklen);
+
+uint8_t HAL_I2C_IntClr_RestartDet(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_GenCall(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_StartDet(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_StopDet(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntCrl_Activity(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_RxDone(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_TxAbort(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_RdReq(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_RxOver(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_TxOver(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_RxUnder(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IntClr_All(I2CInstance *i2cX);
+
+uint32_t HAL_I2C_RawIntStatus(I2CInstance *i2cX);
+
+void HAL_I2C_IntMask_Set(I2CInstance *i2cX, uint16_t mask);
+
+uint16_t HAL_I2C_IntMask_Get(I2CInstance *i2cX);
+
+uint16_t HAL_I2C_IntStatus(I2CInstance *i2cX);
+
+uint8_t HAL_I2C_IC_Enable_Status(I2CInstance *i2cX);
+
+uint32_t HAL_I2C_IC_Status(I2CInstance *i2cX);
+
+void HAL_I2C_Init(I2CInstance *i2cX, uint32_t src_clk, I2C_InitTypeDef config, I2C_Timing_Setting_t *setting);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __HAL_I2C_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_i2s.h

@@ -0,0 +1,116 @@
+#ifndef __HAL_I2S_H__
+#define __HAL_I2S_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+#include "ll/ll_i2s.h"
+
+////////////////////////////  Data type and Macros  //////////////////////////
+
+#define I2S_RX_FIFO_DEPTH           8
+#define I2S_TX_FIFO_DEPTH           8
+
+/**
+ * @brief enum of I2S Enable and I2S Disable.
+ */
+typedef enum
+{
+    I2S_DISABLE = 0,
+    I2S_ENABLE  = 1
+}I2S_En;
+
+/**
+ * @brief enum of I2S Tx Enable and Tx Disable.
+ */
+typedef enum
+{
+    I2S_TX_DISABLE = 0,
+    I2S_TX_ENABLE  = 1
+}I2S_TX_En;
+
+/**
+ * @brief enum of I2S Rx Enable and Rx Disable.
+ */
+typedef enum
+{
+    I2S_RX_DISABLE = 0,
+    I2S_RX_ENABLE  = 1
+}I2S_RX_En;
+
+/**
+ * @brief enum of I2S Resolution, can be defined to 12bit, 16bit, 20bit, 24bit and 32bit.
+ */
+typedef enum
+{
+    I2S_WORD_LENGTH_NONE  = 0,
+    I2S_WORD_LENGTH_12BIT = 1,
+    I2S_WORD_LENGTH_16BIT = 2,
+    I2S_WORD_LENGTH_20BIT = 3,
+    I2S_WORD_LENGTH_24BIT = 4,
+    I2S_WORD_LENGTH_32BIT = 5
+}I2S_Resolution;
+
+/**
+ * @brief enum of I2S Int status.
+ */
+typedef enum
+{
+    I2S_RX_DATA_AVALIABLE         = 0x01,
+    I2S_RX_FIFO_OVERRUN           = 0x02,
+    I2S_TX_FIFO_EMPTY_LVL_REACHED = 0x10,
+    I2S_TX_FIFO_OVERRUN           = 0x20
+}I2S_Int_Status;
+
+/**
+ * @brief enum of I2S Int Mask.
+ */
+typedef enum{
+    I2S_MASK_RX_DATA_AVALIABLE         = 0x01,
+    I2S_MASK_RX_FIFO_OVERRUN           = 0x02,
+    I2S_MASK_TX_FIFO_EMPTY_LVL_REACHED = 0x10,
+    I2S_MASK_TX_FIFO_OVERRUN           = 0x20
+}I2S_Int_Mask;
+
+////////////////////////////  Function Declarations  //////////////////////////
+
+void HAL_I2S_Enable(I2S_En en);
+
+void HAL_I2S_Tx_Init(I2S_Chan_Enum_t chan, I2S_Resolution resolution);
+
+void HAL_I2S_Rx_Init(I2S_Chan_Enum_t chan, I2S_Resolution resolution);
+
+void HAL_I2S_Write(I2S_Chan_Enum_t chan, uint32_t *left_data, uint32_t *right_data, uint32_t length);
+
+void HAL_I2S_Read(I2S_Chan_Enum_t chan, uint32_t *left_data, uint32_t *right_data, uint32_t length);
+
+void HAL_I2S_InterruptEnable(I2S_Chan_Enum_t chan, uint8_t mask_map);
+void HAL_I2S_InterruptDisable(I2S_Chan_Enum_t chan, uint8_t mask_map);
+
+uint8_t HAL_I2S_IntStatus(I2S_Chan_Enum_t chan);
+
+void HAL_I2S_RxFIFO_TrigLvl_Set(I2S_Chan_Enum_t chan, uint8_t rx_lvl);
+
+void HAL_I2S_TxFIFO_TrigLvl_Set(I2S_Chan_Enum_t chan, uint8_t tx_lvl);
+
+void HAL_I2S_TxFIFO_Flush(I2S_Chan_Enum_t chan);
+
+void HAL_I2S_RxFIFO_Flush(I2S_Chan_Enum_t chan);
+
+uint8_t HAL_I2S_IntClr_RxOverrun(I2S_Chan_Enum_t chan);
+
+uint8_t HAL_I2S_IntClr_TxOverrun(I2S_Chan_Enum_t chan);
+
+void HAL_I2S_Reset_TxDMA(void);
+
+void HAL_I2S_Reset_RxDMA(void);
+
+void HAL_I2S_Tx_MultiData(uint32_t *ch0_left_data, uint32_t *ch0_right_data, uint32_t *ch1_left_data, uint32_t *ch1_right_data, uint16_t length);
+
+void HAL_I2S_Rx_MultiData(uint32_t *ch0_left_data, uint32_t *ch0_right_data, uint32_t *ch1_left_data, uint32_t *ch1_right_data, uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __HAL_I2S_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_interrupt.h

@@ -0,0 +1,20 @@
+#ifndef __HAL_INTERRUPT_LN882X_H__
+#define __HAL_INTERRUPT_LN882X_H__
+
+#include "stdbool.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif /* __cplusplus */
+
+
+void set_interrupt_priority(void);
+void switch_global_interrupt(bool enable);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __HAL_INTERRUPT_LN882X_H__ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_pwm.h

@@ -0,0 +1,61 @@
+#ifndef __HAL_PWM_H__
+#define __HAL_PWM_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+typedef enum {
+    PWM_CH0    = 0,
+    PWM_CH1    = 1,
+    PWM_CH2    = 2,
+    PWM_CH3    = 3,
+    PWM_CH4    = 4,
+    PWM_CH5    = 5,
+    PWM_CH6    = 6,
+    PWM_CH7    = 7,
+    PWM_CH8    = 8,
+    PWM_CH9    = 9,
+    PWM_CH10   = 10,
+    PWM_CH11   = 11,
+    PWM_CH_MAX = 12
+} pwm_channel_enum_t;
+
+#define IS_PWM_CHAN(chanX)  ( ( PWM_CH0 <= (chanX) ) && ( (chanX) <= PWM_CH11 ) )
+
+/**
+ * @brief Start one PWM channel.
+ *
+ * @param chan
+ */
+void HAL_PWM_Start(pwm_channel_enum_t chan);
+
+/**
+ * @brief Stop one PWM channel.
+ *
+ * @param chan
+ */
+void HAL_PWM_Stop(pwm_channel_enum_t chan);
+
+/**
+ * @brief Config frequency and duty cycle of one channel.
+ *
+ * @param chan
+ * @param freq  100Hz <= freq <= 800KHz
+ * @param duty 0~1.0
+ */
+void HAL_PWM_Config(pwm_channel_enum_t chan, uint32_t freq, float duty);
+
+/**
+ * @brief Invert output polarity.
+ * The default duty cycle is low, after invert, the output is high.
+ * @param chan
+ * @param en
+ */
+void HAL_PWM_Invert(pwm_channel_enum_t chan, uint8_t en);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __HAL_PWM_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_rtc.h

@@ -0,0 +1,146 @@
+#ifndef __HAL_RTC_H_
+#define __HAL_RTC_H_
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+//////////////////////////////  Data type and Macros  /////////////////////////
+
+/**
+ * @brief Set whether the counter should wrap when a match occurs instead of waiting until the maximum count is reached.
+ */
+typedef enum 
+{
+    RTC_WRAP_DISABLE = 0,
+    RTC_WRAP_ENABLE,
+} RTC_WrapEn;
+
+/**
+ * @brief Set the int mask of rtc module.
+ */
+typedef enum 
+{
+    RTC_INT_UNMASK = 0,
+    RTC_INT_MASK,
+} RTC_IntMask;
+
+/**
+ * @brief Enable or disable the interrupt of rtc.
+ */
+typedef enum 
+{
+    RTC_INT_DISABLE = 0,
+    RTC_INT_ENABLE,
+} RTC_IntEn;
+
+
+typedef enum 
+{
+    RTC_INT_STATUS_INACTIVE = 0,
+    RTC_INT_STATUS_ACTIVE
+} RTC_IntStatus;
+
+/**
+ * @brief Enable or disable counter of rtc.
+ */
+typedef enum 
+{
+    RTC_DISABLE = 0,
+    RTC_ENABLE
+} RTC_Enable;
+
+/**
+ * @brief Struct to define parameter of RTC. 
+ */
+typedef struct 
+{
+    uint32_t counter_match;     ///**< counter_match: 32bit. When RTC start counting from counter_load to counter_match a interrupt will occur if interrupt is enabled. */
+    uint32_t counter_load;      ///**< counter_match: 32bit. Set from where the rtc counter start counting from */
+    RTC_WrapEn wrap_en;         ///**< wrap_en: Set whether the counter should wrap when a match occurs instead of waiting until the maximum count is reached. */
+    RTC_IntMask int_mask;       ///**< int_mask: mask the interrupt or not */
+    RTC_IntEn int_en;           ///**< int_en: enable the interrupt or not */
+} RTC_InitTypeDef;
+
+
+//////////////////////////////  Function Declaration  /////////////////////////
+/**
+ * @brief  Get the current value of the internal counter.
+ * @return return the interal counter of rtc.
+ */
+uint32_t HAL_RTC_GetCurValue(void);
+
+/**
+ * @brief  Set the match counter of rtc.
+ * @param  matchCounter: the match counter of rtc. 
+ *         The rtc counter always count forward. when the load counter reach the match counter an interrupt will trigger.
+ * @return This function has no return value.
+ */
+void HAL_RTC_SetMatchCounter(uint32_t matchCounter);
+
+/**
+ * @brief  Set the load counter of rtc.
+ * @param  loadCounter: the load counter of rtc. It is the value where rtc start counting forward
+ * @return This function has no return value.
+ */
+void HAL_RTC_SetLoadCounter(uint32_t loadCounter);
+
+/**
+ * @brief  To force the counter to wrap when a match occurs
+ * @param  en: 1 to enable a wrap, 0 to disable a wrap
+ * @return This function has no return value.
+ */
+void HAL_RTC_Wrap(RTC_WrapEn wrapEn);
+
+/**
+ * @brief  Enable the RTC counter.
+ * @param  en: 1 to enable the counter, 0 to disable the counter
+ * @return This function has no return value.
+ */
+void HAL_RTC_Enable(RTC_Enable enable);
+
+/**
+ * @brief  Set whether to mask the rtc interrupt or not
+ * @param  en: 1 to mask the interrupt, 0 to unmask the interrupt
+ * @return This function has no return value.
+ */
+void HAL_RTC_IntMask(RTC_IntMask mask);
+
+/**
+ * @brief  Set whether to enable the rtc interrupt or not
+ * @param  en: 1 to enable the interrupt, 0 to disable the interrupt
+ * @return This function has no return value.
+ */
+void HAL_RTC_IntEnable(RTC_IntEn enable);
+
+/**
+ * @brief  Get the status of rtc interrupt, after the mask
+ * @return The interrupt status after the int mask. 1 means interrupt is active, 0 means interrupt is inactive.
+ */
+RTC_IntStatus HAL_RTC_IntStatus(void);
+
+/**
+ * @brief  Get the raw status of rtc interrupt, before the mask
+ * @return The interrupt status before the int mask. 1 means interrupt is active, 0 means interrupt is inactive.
+ */
+RTC_IntStatus HAL_RTC_IntRawStatus(void);
+
+/**
+ * @brief  Clear rtc interrupt
+ * @return This function has no return value.
+ */
+void HAL_RTC_ClearInt(void);
+
+/**
+ * @brief Initialize the RTC
+ * @param config: Struct to define parameter of RTC. 
+ * @return This function has no return value.
+ */
+void HAL_RTC_Init(RTC_InitTypeDef config);
+uint32_t HAL_RTC_GetMatchCounter(void);
+
+#ifdef __cplusplus
+    }
+#endif // __cplusplus
+#endif // __HAL_RTC_H_

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_sdio.h

@@ -0,0 +1,40 @@
+#ifndef __HAL_SDIO_H__
+#define __HAL_SDIO_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+#include "osal/osal.h"
+#include "ll/ll_sdio.h"
+
+typedef int (*receive_from_host_cb_t)(uint8_t *addr, int len, bool mmcopy);
+typedef uint8_t *(*get_buffer_for_receive_from_host_cb_t)(void);
+typedef struct
+{
+    receive_from_host_cb_t                      receive_from_host_cb;
+    get_buffer_for_receive_from_host_cb_t       get_buffer_for_receive;
+}host_ops_t;
+
+typedef struct
+{
+    OS_Mutex_t          lock;
+    OS_Semaphore_t      sdio_sem;
+    bool                fn1_en;
+    host_ops_t          host_ops;
+    uint8_t             sdio_cis_fn0[128];
+    uint8_t             sdio_cis_fn1[128];
+    uint8_t             rx_buffer[1600];
+}hal_sdio_ctrl_t;
+
+void hal_sdio_xfer_to_host(uint8_t *addr, int len);
+void hal_sdio_init(sdio_config_t *config, host_ops_t *sdio_ops);
+void hal_sdio_reset(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __HAL_SDIO_H__
+

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_sleep.h

@@ -0,0 +1,57 @@
+#ifndef __HAL_SLEEP_H__
+#define __HAL_SLEEP_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+#include "hal/hal_gpio.h"
+#include "ll/ll_sleep.h"
+
+typedef enum {
+    SLEEP_TIMER_WAKEUP = (1 << 0),
+    MAC_WAKEUP = (1 << 1),
+    EXT_INT_WAKEUP = (1 << 2),
+    RTC_WAKEUP = (1 << 3),
+}hal_sleep_wakeup_src_enum_t;
+
+typedef void (* reinitialize_phy_cb_t)(void);
+typedef bool (* wifi_is_slept_cb_t)(void);
+typedef struct
+{
+    GPIO_Num                    gpio;
+    SYSTEM_EXT_INT_Triggle_Type triggle_type;
+}ext_irq_cfg_t ;
+typedef struct {
+    sleep_mode_enum_t       sleep_mode;
+    uint32_t                wakeup_src;//bit[0]--SLEEP_IRQn; bit[1]--MAC_IRQn;bit[2]--EXTERNAL_IRQn;bit[3]--RTC_IRQn
+    ext_irq_cfg_t           ext_irq_cfg;
+}hal_sleep_config_t;
+
+typedef struct
+{
+    bool                    flag;
+    hal_sleep_config_t      sleep_config;
+    uint32_t                nvic_int_en[2];
+    uint64_t                compensation;
+    uint32_t                msec;
+    wifi_is_slept_cb_t      wifi_is_slept_cb;
+    reinitialize_phy_cb_t   reinit_phy_cb;
+    bool                    inited;
+}hal_sleep_ctrl_t ;
+
+void hal_sleep_init(hal_sleep_config_t *sleep_config);
+void hal_sleep_deinit(void);
+void hal_sleep_set_config(hal_sleep_config_t *sleep_config);
+sleep_mode_enum_t hal_sleep_get_mode(void);
+void hal_pre_sleep_processing(uint32_t *ticks);
+uint32_t hal_post_sleep_processing(uint32_t ticks);
+void hal_sleep_register_callback(reinitialize_phy_cb_t reinit_phy_cb, wifi_is_slept_cb_t wifi_is_slept_cb);
+void hal_sleep_wakeup_source_set(hal_sleep_wakeup_src_enum_t wakeup_src);
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __HAL_SLEEP_H__
+

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_spim.h

@@ -0,0 +1,344 @@
+#ifndef __HAL_SPIM__H__
+#define __HAL_SPIM__H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+#include "hal/spi_type.h"
+
+#define RX_FIFO_DEPTH       16
+#define TX_FIFO_DEPTH       16
+
+/**
+ * @brief enum of SPIM_Slave_Id. We can select from SPI_SLAVE_0 to SPI_SLAVE_2 (We have three cs pin).
+ */
+typedef enum
+{
+    SPI_SLAVE_0 = 1,
+    SPI_SLAVE_1 = 2,
+    SPI_SLAVE_2 = 4
+} SPIM_Slave_Id;
+
+/**
+ * @brief This is the struct to initialize the spi master module.
+ */
+typedef struct
+{
+	uint32_t                speed;      /**< speed: set the spi clock speed */
+    SPI_Protocol_Type       format;     /**< format: the protocol type of spi */
+    SPI_Dataframe_Size      dfs;        /**< dfs: set the dataframe size */
+    SPI_Controlframe_Size   cfs;        /**< cfs: set the control frame size, it is useful when only format = National_Semiconductors_Microwire*/
+    SPI_Clock_Polarity      scpol;      /**< scpol: set the clock polarity when spi is inactive */
+    SPI_Clock_Phase         scph;       /**< scph: set the spi clock phase */
+} SPIM_InitTypeDef;
+
+/**
+ * @brief enum of spi master int status.
+ */
+typedef enum
+{
+    SPIM_INT_TXFIFO_EMPTY       = (1<<0),
+    SPIM_INT_TXFIFO_OVERFLOW    = (1<<1),
+    SPIM_INT_RXFIFO_UNDERFLOW   = (1<<2),
+    SPIM_INT_RXFIFO_OVERFLOW    = (1<<3),
+    SPIM_INT_RXFIFO_FULL        = (1<<4),
+    SPIM_INT_MULTI_MASTER       = (1<<5)
+} SPIM_Int_Status;
+
+/**
+ * @brief enum of spi master int mask.
+ */
+typedef enum
+{
+    SPIM_MASK_TXFIFO_EMPTY      = (1<<0),
+    SPIM_MASK_TXFIFO_OVERFLOW   = (1<<1),
+    SPIM_MASK_RXFIFO_UNDERFLOW  = (1<<2),
+    SPIM_MASK_RXFIFO_OVERFLOW   = (1<<3),
+    SPIM_MASK_RXFIFO_FULL       = (1<<4),
+    SPIM_MASK_MULTI_MASTER      = (1<<5)
+} SPIM_Int_Mask;
+
+/**
+ * @brief enum of spi master status.
+ */
+typedef enum
+{
+    SPIM_STATUS_BUSY            = (1<<0),
+    SPIM_STATUS_TXFIFO_NOTFULL  = (1<<1),
+    SPIM_STATUS_TXFIFO_EMPTY    = (1<<2),
+    SPIM_STATUS_RXFIFO_NOTEMPTY = (1<<3),
+    SPIM_STATUS_RXFIFO_FULL     = (1<<4),
+    SPIM_STATUS_TRANSMIT_ERROR  = (1<<5),
+    SPIM_STATUS_DATA_COLLISION  = (1<<6)
+} SPIM_Normal_Status;
+
+/**
+ * @brief Initialize spi master module.
+ * @param src_clk: input the src_clk of spi module.
+ * @param config: input the spi configure structure to initialize the module.
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Init(uint32_t src_clk, SPIM_InitTypeDef config);
+
+/**
+ * @brief Read Register through spi interface in polling mode. The function will not return before all data are successfully sent and receive. And then spi is disabled.
+          By using this function the spi master work in half-duplex mode(send data and then receive).
+ * @param id: select the slave id to operate.
+ * @param wr_ptr: pointer to the buffer of output data
+ * @param wr_len: data length of output data
+ * @param rd_ptr: pointer to the buffer of input data
+ * @param rd_len: data length of input data
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Read_Register_Polling(SPIM_Slave_Id id,uint32_t *wr_ptr,uint16_t wr_len,uint32_t *rd_ptr,uint16_t rd_len);
+
+/**
+ * @brief Read data from spi interface in polling mode. The function will not return before all data are successfully received. And then spi is disabled.
+          By using this function the spi master send dummy data and read specific length of data.
+ * @param id: select the slave id to operate.
+ * @param rd_ptr: pointer to the buffer of input data
+ * @param rd_len: data length of input data
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Read_Only_Polling(SPIM_Slave_Id id, uint32_t *rd_ptr, uint16_t rd_len);
+
+/**
+ * @brief write data from spi interface in polling mode. The function will not return before all data are successfully sent. And then spi is disabled.
+          By using this function the spi master send specific length of data.
+ * @param id: select the slave id to operate.
+ * @param wr_ptr: pointer to the buffer of output data
+ * @param wr_len: data length of output data
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Write_Polling(SPIM_Slave_Id id, uint32_t *wr_ptr, uint16_t wr_len);
+
+/**
+ * @brief Transmit and receive data at the same time. Data are received into fifo and user should enable rx interrupt and get data when interrupt triggered.
+          By using this function the spi master send specific length of data and read specific length of data at the same time. Received data can be read when interrupt triggered by using HAL_SPIM_Read_RxFIFO
+          It's the users responsible to disable spi when all data flow is finished.
+ * @param id: select the slave id to operate.
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Transmit_And_Receive(SPIM_Slave_Id id);
+
+/**
+ * @brief Read register and the function return immediately. Data are received into fifo and user should enable rx interrupt and get data when interrupt triggered.
+          By using this function the spi master send specific length of data and read specific length of data at the same time. Received data can be read when interrupt triggered by using HAL_SPIM_Read_RxFIFO
+          It's the users responsible to disable spi when all data flow is finished.
+ * @param id: select the slave id to operate.
+ * @param rd_len: data length of input data
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Read_Register(SPIM_Slave_Id id, uint16_t rd_len);
+
+/**
+ * @brief Write data and the function return when all data are written into fifo. It's user's responsible to enable the interrupt SPIM_MASK_TXFIFO_EMPTY.
+          By using this function the spi master send specific length of data and SPIM_MASK_TXFIFO_EMPTY will trigger. Then user can check status and disable spi.
+ * @param id: select the slave id to operate.
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Write(SPIM_Slave_Id id);
+
+/**
+ * @brief Read data from spi and the function return immediately. It's user's responsible to enable the interrupt SPIM_INT_RXFIFO_FULL.
+          By using this function the spi master read specific length of data and SPIM_INT_RXFIFO_FULL will trigger. Then user can check status and disable spi.
+ * @param id: select the slave id to operate.
+ * @param rd_len: data length of input data
+ * @param dummy_data: value to send as dummy data.
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Read_Only(SPIM_Slave_Id id, uint16_t rd_len, uint32_t dummy_data);
+
+/**
+ * @brief Set read data length
+ * @param rd_len: number of data to read from rx fifo. rd_len should minus 1. For example, rd_len = 4 means 5 data will receive from spi.
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Set_Read_Len(uint16_t rd_len);
+
+/**
+ * @brief Read specific length of data from rx fifo
+ * @param rd_ptr: pointer to the receive data buffer.
+ * @param rd_len: data length to read in fifo
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Read_RxFIFO(uint32_t *rd_ptr, uint16_t rd_len);
+
+/**
+ * @brief Write specific length of data to tx fifo
+ * @param wr_ptr: pointer to the transmit data buffer.
+ * @param wr_len: data length to write to fifo
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Write_TxFIFO(uint32_t * wr_ptr, uint16_t wr_len);
+
+/**
+ * @brief Set Rx Sample delay.
+ * @param dly: serveral spi clk to dly
+ * @return This function has no return value.
+ */
+void HAL_SPIM_RxSample_Dly(uint8_t dly);
+
+/**
+ * @brief Config DMA of spi, enable or disable them
+ * @param tx_dma_en: enable tx dma
+ * @param rx_dma_en: enable rx dma
+ * @param tx_data_level: This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level
+ * @param rx_data_level: This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Set_DMA(uint8_t tx_dma_en, uint8_t rx_dma_en, uint8_t tx_data_level, uint8_t rx_data_level);
+
+/**
+ * @brief Get the status and clear int at the same time.  A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts.
+ * @return return the int status of combined Interrupt.
+ */
+uint8_t HAL_SPIM_IntClr(void);
+
+/**
+ * @brief Clear Multi-Master Contention Interrupt.
+ * @return return the int status of Multi-Master Contention Interrupt.
+ */
+uint8_t HAL_SPIM_IntClr_MST(void);
+
+/**
+ * @brief Clear Receive FIFO Underflow Interrupt.
+ * @return return the int status of rx underflow.
+ */
+uint8_t HAL_SPIM_IntClr_RXU(void);
+
+/**
+ * @brief Clear Receive FIFO Overflow Interrupt.
+ * @return return the int status of rx overflow.
+ */
+uint8_t HAL_SPIM_IntClr_RXO(void);
+
+/**
+ * @brief Clear Transmit FIFO Overflow Interrupt.
+ * @return return the int status of tx overflow.
+ */
+uint8_t HAL_SPIM_IntClr_TXO(void);
+
+/**
+ * @brief Get interrupt raw status (before int mask).
+ * @return return the raw int status before int mask.
+ */
+uint8_t HAL_SPIM_RawInt_Status(void);
+
+/**
+ * @brief Get interrupt status (after int mask).
+ * @return  return the int status after int mask.
+ */
+uint8_t HAL_SPIM_Int_Status(void);
+
+/**
+ * @brief Set interrupt mask.
+ * @param mask: bit map of mask. The input mask is ored from enum SPIM_Int_Mask.
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Set_Mask(uint8_t mask);
+
+/**
+ * @brief Get interrupt mask.
+ * @return return the current int mask.
+ */
+uint8_t HAL_SPIM_Get_Mask(void);
+
+/**
+ * @brief Get normal status(not interrupt status).
+ * @return return the status of spim.
+ */
+uint8_t HAL_SPIM_Normal_Status(void);
+
+/**
+ * @brief Read current tx fifo level.
+ * @return return tx fifo level.
+ */
+uint8_t HAL_SPIM_Current_TxFIFO_Level(void);
+
+/**
+ * @brief Read current rx fifo level.
+ * @return return rx fifo level.
+ */
+uint8_t HAL_SPIM_Current_RxFIFO_Level(void);
+
+/**
+ * @brief Set the spi fifo threshold.
+ * @param tx_thd: tx threshold, the FIFO depth is configurable in the range 2-16
+ * @param rx_thd: rx threshold, the FIFO depth is configurable in the range 2-16
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Set_FIFO_Threshold(uint8_t tx_thd, uint8_t rx_thd);
+
+/**
+ * @brief Set the clock divider of spim
+ * @param div: divider of the src clk
+ * @return This function has no return value.
+ */
+void HAL_SPIM_CLK_Div(uint16_t div);
+
+/**
+ * @brief Select the slave id.
+          When the slave id is select the cs pull low and and data enter tx fifo will send out immediately.
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Slave_Select_En(SPIM_Slave_Id id);
+
+/**
+ * @brief Settings of microwire.
+ * @param handshake_en: set to enable or disable handshaking interface.
+ * @param mode: Defines the direction of the data word when the Microwire serial protocol is used.
+ * @param transfer_mode: Defines whether the Microwire transfer is sequential or non-sequential. 0 �C non-sequential transfer 1 �C sequential transfer
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Microwire_Setting(uint8_t handshake_en, uint8_t mode, uint8_t transfer_mode);
+
+/**
+ * @brief Enable the spi module.
+ * @param en: set to enable or disable spi module
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Enable(SPI_En en);
+
+/**
+ * @brief Set ctrl0 register of spi master
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Ctrl0(uint8_t dfs,uint8_t cfs,uint8_t srl,uint8_t slv_oe,uint8_t tmod,uint8_t scpol,uint8_t scph,uint8_t frf);
+
+/**
+ * @brief Set ctrl1 register of spi master
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Ctrl1(uint16_t ndf);
+
+/**
+ * @brief Read 1 data
+ * @return return the data read
+ */
+uint32_t HAL_SPIM_Data_Read(void);
+
+/**
+ * @brief write 1 data
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Data_Write(uint32_t data);
+
+/**
+ * @brief Get spi busy status.
+ * @return return true if spim is busy.
+ */
+bool HAL_SPIM_Is_Busy(void);
+
+/**
+ * @brief Set transfer mode
+ * @param mode: transmit mode
+ * @return This function has no return value.
+ */
+void HAL_SPIM_Mode_Set(SPI_Transmit_Mode mode);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __HAL_SPIM__H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_spis.h

@@ -0,0 +1,199 @@
+#ifndef __HAL_SPIS_H__
+#define __HAL_SPIS_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+#include "hal/spi_type.h"
+
+#define RX_FIFO_DEPTH       16
+#define TX_FIFO_DEPTH       16
+
+/**
+ * @brief This is the struct to initialize the spi slave module.
+ */
+typedef struct
+{
+    SPI_Protocol_Type  format;          /**< format: the protocol type of spi */
+    SPI_Transmit_Mode tmod;             /**< tmod: the transmit mode of spi */
+    SPI_Dataframe_Size dfs;             /**< dfs: set the dataframe size */
+    SPI_Controlframe_Size cfs;          /**< cfs: set the control frame size, it is useful when only format = National_Semiconductors_Microwire*/
+    SPI_Slave_Output_Enable oe;         /**< oe: spi output enable when work as a slave*/
+    SPI_Clock_Polarity scpol;           /**< scpol: set the clock polarity when spi is inactive */
+    SPI_Clock_Phase scph;               /**< scph: set the spi clock phase */
+} SPIS_InitTypeDef;
+
+/**
+ * @brief enum of spi slave int status.
+ */
+typedef enum
+{
+    SPIS_INT_TXFIFO_EMPTY     = (1<<0),
+    SPIS_INT_TXFIFO_OVERFLOW  = (1<<1),
+    SPIS_INT_RXFIFO_UNDERFLOW = (1<<2),
+    SPIS_INT_RXFIFO_OVERFLOW  = (1<<3),
+    SPIS_INT_RXFIFO_FULL      = (1<<4)
+}SPIS_Int_Status;
+
+/**
+* @brief enum of spi slave int mask.
+*/
+typedef enum
+{
+    SPIS_MASK_TXFIFO_EMPTY     = (1<<0),
+    SPIS_MASK_TXFIFO_OVERFLOW  = (1<<1),
+    SPIS_MASK_RXFIFO_UNDERFLOW = (1<<2),
+    SPIS_MASK_RXFIFO_OVERFLOW  = (1<<3),
+    SPIS_MASK_RXFIFO_FULL      = (1<<4)
+} SPIS_Int_Mask;
+
+/**
+* @brief enum of spi slave status.
+*/
+typedef enum
+{
+    SPIS_STATUS_BUSY              = (1<<0),
+    SPIS_STATUS_TXFIFO_NOTFULL    = (1<<1),
+    SPIS_STATUS_TXFIFO_EMPTY      = (1<<2),
+    SPIS_STATUS_RXFIFO_NOTEMPTY   = (1<<3),
+    SPIS_STATUS_RXFIFO_FULL       = (1<<4),
+    SPIS_STATUS_TRANSMIT_ERROR    = (1<<5),
+    SPIS_STATUS_DATA_COLLISION    = (1<<6)
+}SPIS_Normal_Status;
+
+
+/**
+ * @brief Initialize spi slave module.
+ * @param config: input the spi configure structure to initialize the module.
+ * @return This function has no return value.
+ */
+void HAL_SPIS_Init(SPIS_InitTypeDef config);
+/**
+ * @brief Enable the spi module.
+ * @param en: set to enable or disable spi module
+ * @return This function has no return value.
+ */
+void HAL_SPIS_ENABLE(SPI_En en);
+/**
+ * @brief Settings of microwire.
+ * @param handshake_en: set to enable or disable handshaking interface.
+ * @param mode: Defines the direction of the data word when the Microwire serial protocol is used.
+ * @param transfer_mode: Defines whether the Microwire transfer is sequential or non-sequential. 0 �C non-sequential transfer 1 �C sequential transfer
+ * @return This function has no return value.
+ */
+void HAL_SPIS_Microwire_Setting(uint8_t handshake_en, uint8_t mode, uint8_t transfer_mode);
+/**
+ * @brief Set the spi fifo threshold.
+ * @param tx_thd: tx threshold, the FIFO depth is configurable in the range 2-16
+ * @param rx_thd: rx threshold, the FIFO depth is configurable in the range 2-16
+ * @return This function has no return value.
+ */
+void HAL_SPIS_FIFO_Threshold_Set(uint8_t tx_thd, uint8_t rx_thd);
+/**
+ * @brief Read current tx fifo level.
+ * @return return tx fifo level.
+ */
+uint8_t HAL_SPIS_Current_TxFIFO_Level(void);
+/**
+ * @brief Read current rx fifo level.
+ * @return return rx fifo level.
+ */
+uint8_t HAL_SPIS_Current_RxFIFO_Level(void);
+/**
+ * @brief Get normal status(not interrupt status).
+ * @return return the status of spim.
+ */
+uint8_t HAL_SPIS_Normal_Status(void);
+uint8_t HAL_SPIS_Is_DataCollision(void);
+uint8_t HAL_SPIS_Is_TxError(void);
+uint8_t HAL_SPIS_Is_RxFIFO_Full(void);
+uint8_t HAL_SPIS_Is_RxFIFO_NotEmpty(void);
+uint8_t HAL_SPIS_Is_TxFIFO_Empty(void);
+uint8_t HAL_SPIS_Is_TxFIFO_NotFull(void);
+uint8_t HAL_SPIS_Is_Busy(void);
+
+/**
+ * @brief Set interrupt mask.
+ * @param mask: bit map of mask. The input mask is ored from enum SPIM_Int_Mask.
+ * @return This function has no return value.
+ */
+void HAL_SPIS_IntMask_Set(uint8_t mask);
+/**
+ * @brief Get interrupt mask.
+ * @return return the current int mask.
+ */
+uint8_t HAL_SPIS_IntMask_Get(void);
+/**
+ * @brief Get interrupt status (after int mask).
+ * @return return the int status after int mask.
+ */
+uint8_t HAL_SPIS_Int_Status(void);
+/**
+ * @brief Get interrupt raw status (before int mask).
+ * @return return the raw int status before int mask.
+ */
+uint8_t HAL_SPIS_RawInt_Status(void);
+/**
+ * @brief Get interrupt tx overflow.
+ * @return return the tx overflow int status.
+ */
+uint8_t HAL_SPIS_IntClr_TxOverflow(void);
+/**
+ * @brief Clear Receive FIFO Overflow Interrupt.
+ * @return return the int status of rx overflow
+ */
+uint8_t HAL_SPIS_IntClr_RxOverflow(void);
+/**
+ * @brief Clear Receive FIFO Underflow Interrupt.
+ * @return return the int status of rx underflow
+ */
+uint8_t HAL_SPIS_IntClr_RxUnderflow(void);
+/**
+ * @brief Clear Multi-Master Contention Interrupt.
+ * @return return the int status of  Multi-Master Contention Interrupt.
+ */
+uint8_t HAL_SPIS_IntClr_MultiMaster(void);
+/**
+ * @brief Get the status and clear int at the same time.  A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts.
+ * @return return the int status of combined Interrupt.
+ */
+uint8_t HAL_SPIS_IntClr_All(void);       // get the status and clear int at the same time
+/**
+ * @brief Config DMA of spi, enable or disable them
+ * @param tx_dma_en: enable tx dma
+ * @param rx_dma_en: enable rx dma
+ * @param tx_data_level: This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level
+ * @param rx_data_level: This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level
+ * @return This function has no return value.
+ */
+void HAL_SPIS_DMA_Config(uint8_t tx_dma_en, uint8_t rx_dma_en, uint8_t tx_data_level, uint8_t rx_data_level);
+/**
+ * @brief Read 1 data
+ * @return return the data read
+ */
+uint32_t HAL_SPIS_Data_Read(void);
+/**
+ * @brief write 1 data
+ * @return This function has no return value.
+ */
+void HAL_SPIS_Data_Write(uint32_t data);
+/**
+ * @brief Read specific length of data from rx fifo
+ * @return return value.
+ */
+uint32_t HAL_SPIS_Read_RxFIFO(void);
+
+
+/**
+ * @brief Write specific length of data from tx fifo
+ * @param data: data to the write data buffer.
+ * @return This function has no return value.
+ */
+void HAL_SPIS_Write_FIFO(uint32_t data);
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __HAL_SPIS_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_syscon.h

@@ -0,0 +1,324 @@
+#ifndef _HAL_SYSCON_H_
+#define _HAL_SYSCON_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "types.h"
+#include "syscon_types.h"
+
+/**
+ * @brief Real 32K period, can be used by SW to calculate PPM.
+ *
+ * @return uint16_t
+ */
+uint16_t HAL_SYSCON_Get32KPeriodNs(void);
+
+/**
+ * @brief Enable of cal 32K, enable of update calibratioin result.
+ *
+ */
+void HAL_SYSCON_32KCaliEnable(void);
+
+/**
+ * @brief Set CPU sleep duration time, unit: ns.
+ *
+ * @param n_ns CPU sleep duration time, unit is ns.
+ */
+void HAL_SYSCON_CPUSleepDurationEnable(unsigned long long n_ns);
+
+/**
+ * @brief Disable CPU sleep.
+ *
+ */
+void HAL_SYSCON_CPUSleepDurationDisable(void);
+
+/**
+ * @brief Get CPU real sleep time.
+ *
+ * @return uint64_t real sleep time, unit is ns.
+ */
+uint64_t HAL_SYSCON_RealSleepTime(void);
+
+/**
+ * @brief Get always on idle reg value.
+ *
+ * @return uint32_t awo idle reg value
+ */
+uint32_t HAL_SYSCON_IdleReg(void);
+
+
+/**
+ * @brief Calculate compensate time, unit is ns.
+ *
+ * @return uint32_t compensate time.
+ */
+uint32_t HAL_SYSCON_CalculateCompensateNs(void);
+
+/**
+ * @brief Indicate a true lock after debounce logic.
+ *
+ * @return true locked.
+ * @return false not locked.
+ */
+bool HAL_SYSCON_IsSysPllLocked(void);
+
+/**
+ * @brief Set lock signal parity, debounce delay.
+ *
+ * @param lock_polarity 1 bit.
+ * @param debounce_dly threshold to indicate a true lock.
+ */
+void HAL_SYSCON_SysPllDebounceSet(uint8_t lock_polarity, uint8_t debounce_dly);
+
+/**
+ * @brief Select flash mode or mirror mode.
+ *
+ * @param mode 1 -- flash mode; 0 -- mirror mode.
+ */
+void HAL_SYSCON_FlashOrMirrorMode(uint8_t mode);
+
+/**
+ * @brief Get boot mode.
+ *
+ * @return uint8_t 0 -- flash mode; 1 -- uart mode.
+ */
+uint8_t HAL_SYSCON_GetBootMode(void);
+
+/**
+ * @brief Reset Core, only five options is valid: all, phy, rtc, wic, pmu.
+ *
+ * @param src one option of pmu, wic, rtc, phy, all.
+ */
+void HAL_SYSCON_SoftwareResetCore(SYSCON_SwRst_Core src);
+
+/**
+ * @brief Select HCLK source to PLL.
+ *
+ */
+void HAL_SYSCON_ClkSwitchToPll(void);
+
+/**
+ * @brief Select HCLK source to XTAL.
+ *
+ */
+void HAL_SYSCON_ClkSwitchToXtal(void);
+
+/**
+ * @brief Set HCLK division.
+ *
+ * @param ahb_divider
+ */
+void HAL_SYSCON_SetHclkDivision(uint8_t ahb_divider);
+
+/**
+ * @brief Set PCLK0 division.
+ *
+ * @param apb0_divider
+ */
+void HAL_SYSCON_SetPclk0Division(uint8_t apb0_divider);
+
+/**
+ * @brief Set PCLK1 Division.
+ *
+ * @param apb1_divider
+ */
+void HAL_SYSCON_SetPclk1Division(uint8_t apb1_divider);
+
+/**
+ * @brief Clock gate enable.
+ *
+ * @param src core clock src.
+ * @param ena 1 -- enable or 0 -- disable.
+ */
+void HAL_SYSCON_CoreClockEnable(SYSCON_ClkGate_Core src, bool ena);
+
+/**
+ * @brief Get core clock enable status, 1 bit for 1 core clock.
+ *
+ * @return uint32_t ORed value, 1 bit for 1 core clock, @see SYSCON_ClkGate_Core.
+ */
+uint32_t HAL_SYSCON_CoreClockStatus(void);
+
+/**
+ * @brief Peripheral clock enable.
+ * Note: call this function one time to enable one clock.
+ *
+ * @param src peripheral module.
+ * @param ena enable / disable.
+ */
+void HAL_SYSCON_PeripheralClockEnable(SYSCON_ClkGate_Peripheral src, bool ena);
+
+/**
+ * @brief Get peripheral clock enable status.
+ *
+ * @return uint32_t ORed value, @see SYSCON_ClkGate_Peripheral.
+ */
+uint32_t HAL_SYSCON_PeripheralClockStatus(void);
+
+/**
+ * @brief Reset peripheral module.
+ * Note: call this function one time to reset one peripheral module.
+ *
+ * @param peri @see SYSCON_SwRst_Peripheral.
+ */
+void HAL_SYSCON_SoftwareResetPeripheral(SYSCON_SwRst_Peripheral peri);
+
+/**
+ * @brief Set IO function.
+ *
+ * @param af_type function type, @see GPIO_AltFunctionType.
+ * @param af_io_idx IO index, @see GPIO_AltFunctionIoIndex.
+ * @param en enable / disable.
+ */
+void HAL_SYSCON_FuncIOSet(GPIO_AltFunctionType af_type, GPIO_AltFunctionIoIndex af_io_idx, uint8_t en);
+
+/**
+ * @brief Disable all function on all configurable IO pad.
+ *
+ */
+void HAL_SYSCON_FuncIODisableAll(void);
+
+
+/**
+ * @brief GPIO Pull Up
+ *
+ */
+void HAL_SYSCON_GPIO_PullUp(GPIO_Num gpio_num);
+
+/**
+ * @brief GPIO Pull Down
+ *
+ */
+void HAL_SYSCON_GPIO_PullDown(GPIO_Num gpio_num);
+
+
+/**
+ * @brief Select SPIS as IO pad.
+ *
+ * @param en 1 -- enable; 0 -- disable.
+ */
+void HAL_SYSCON_SPIS_Enable(uint8_t en);
+
+/**
+ * @brief Select spim and csnX IO as pad.
+ *
+ * @param index @see SYSCON_SPIM_Index.
+ */
+void HAL_SYSCON_SPIMEnable(SYSCON_SPIM_Index index);
+
+/**
+ * @brief Deselect SPIM and csnX IO as pad.
+ *
+ * @param index @see SYSCON_SPIM_Index
+ */
+void HAL_SYSCON_SPIMDisable(SYSCON_SPIM_Index index);
+
+/**
+ * @brief Disable all SPIM.
+ *
+ */
+void HAL_SYSCON_SPIMDisableAll(void);
+
+/**
+ * @brief Select SDIO IO as pad.
+ *
+ */
+void HAL_SYSCON_SDIOEnable(void);
+
+/**
+ * @brief Deselect SDIO IO as pad.
+ *
+ */
+void HAL_SYSCON_SDIODisable(void);
+
+/**
+ * @brief Select/Deselect SPIFlash as pad.
+ *
+ * @param enable
+ */
+void HAL_SYSCON_SPIFlashEnable(uint8_t enable);
+
+/**
+ * @brief Select I2S chnX IO as pad.
+ *
+ * @param index @see SYSCON_I2S_Index.
+ */
+void HAL_SYSCON_I2SEnable(SYSCON_I2S_Index index);
+
+/**
+ * @brief Disable all I2S module.
+ *
+ */
+void HAL_SYSCON_I2SDisable(void);
+
+/**
+ * @brief SWD enable.
+ *
+ */
+void HAL_SYSCON_SWDEnable(void);
+
+/**
+ * @brief SWD disable.
+ *
+ */
+void HAL_SYSCON_SWDDisable(void);
+
+/**
+ * @brief DBGH enable.
+ *
+ */
+void HAL_SYSCON_DBGHEnable(void);
+
+/**
+ * @brief DBHG disable.
+ *
+ */
+void HAL_SYSCON_DBGHDisable(void);
+
+
+/**
+ * @brief HCLK source select.
+ *
+ * @param src @see SYSTEM_CLOCK_SRC.
+ */
+void HAL_SYSCON_SelectSysClkSrc(SYSTEM_CLOCK_SRC src);
+
+/**
+ * @brief Set CPU reset request mask.
+ *
+ * @param mask 1 -- mask, 0 -- not masked.
+ */
+void HAL_SYSCON_CPUResetReqMask(uint8_t mask);
+
+/**
+ * @brief PHY must be reset after TxImgCal.
+ */
+
+void HAL_SysconPhyReset(void);
+/**
+ * @brief  Reset the mcu by software
+ *
+ * @param  none
+ *
+ * @note   use the 3.5 version of the firmware library. 
+ */
+void HAL_SYSCON_SoftReset(void);
+
+
+void HAL_SYSCON_EXT_INTR_Enable(SYSTEM_EXT_INT_Wakeup_Index ext_int_idx, bool enable);
+void HAL_SYSCON_EXT_INTR_Set_Triggle_Condition(SYSTEM_EXT_INT_Wakeup_Index ext_int_idx, SYSTEM_EXT_INT_Triggle_Type triggle);
+uint8_t HAL_SYSCON_EXT_INTR_Stat(void);
+uint8_t HAL_SYSCON_EXT_INTR_Stat_Raw(void);
+void HAL_SYSCON_EXT_INTR_Clear(void);
+void HAL_SYSCON_RCO32K_Bitsel_Set(uint8_t bitsel);
+void HAL_SYSCON_RCO32K_Cbit_Set(uint8_t cbit);
+void HAL_SYSCON_Xtal40MCap_Set(uint8_t cap);
+void HAL_SYSCON_PmuCfg(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_SYSCON_H_ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_timer.h

@@ -0,0 +1,196 @@
+#ifndef __HAL_TIMER_H_
+#define __HAL_TIMER_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+    extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief There are totally 4 hardware timers.
+ *
+ */
+typedef enum
+{
+    TIMER_1 = 1,
+    TIMER_2,
+    TIMER_3,
+    TIMER_4
+} TIMER_Index;
+
+
+/**
+ * @brief Mask the timer interrupt or not.
+ *
+ */
+typedef enum
+{
+    TIMER_MASKED_NO = 0,
+    TIMER_MASKED_YES
+} TIMER_Mask;
+
+
+/**
+ * @brief Choose the running mode of timer.
+          user_defined: Use this mode if you want a fixed, timed interrupt.
+          free_running: Use this mode if you want a single timed interrupt.
+ */
+typedef enum
+{
+    TIMER_MODE_FREERUNNING = 0,     /**< TIMER_MODE_FREE_RUNNING: Use this mode if you want a single timed interrupt. */
+    TIMER_MODE_USERDEFINED          /**< TIMER_MODE_USER_DEFINED: Use this mode if you want a fixed, timed interrupt. */
+} TIMER_Mode;
+
+
+/**
+ * @brief Enable or Disable the timer
+ */
+typedef enum
+{
+    TIMER_DISABLE = 0,
+    TIMER_ENABLE
+} TIMER_Enable;
+
+
+/**
+ * @brief This is the struct to initialize the timer module.
+ */
+typedef struct
+{
+    TIMER_Index index;      /**< index: select which timer to use */
+    TIMER_Mask mask;        /**< mask: mask or unmask the timer interrupt */
+    TIMER_Mode mode;        /**< mode: select the running mode of timer, free-running or user define mode */
+    uint32_t user_freq;     /**< user_freq: user-defined timer clock frequency fx, which must meet the request:  321.5KHz <= fx <= 80MHz */
+} TIMER_InitTypeDef;
+
+
+#define IS_TIMER_INDEX(TimerX)      ((TimerX) == TIMER_1 || (TimerX) == TIMER_2 || (TimerX) == TIMER_3 || (TimerX) == TIMER_4)
+#define IS_TIMER_MASK(mask)         ((mask) == TIMER_MASKED_NO || (mask) == TIMER_MASKED_YES)
+#define IS_TIMER_MODE(mode)         ((mode) == TIMER_MODE_USER_DEFINED || (mode) == TIMER_MODE_FREE_RUNNING)
+#define IS_TIMER_ENABLE(enable)     ((enable) == TIMER_ENABLE || (enable) == TIMER_DISABLE)
+
+///////////////////////////   function declaration  ///////////////////////////
+/**
+ * @brief Initialize the timer according to the input param config.
+ * @param  config: the structure to initialize the timer, user_freq must meet the requierement: [312.5KHz, 80MHz]
+ * @return This function has no return.
+ */
+void HAL_TIMER_Init(TIMER_InitTypeDef config);
+
+
+/**
+ * @brief Set the loadcounter of the timer
+ * @param  index: define which timer to operate.
+ * @param  count: the counter is 24bit.
+ * @return This function has no return.
+ */
+void HAL_TIMER_LoadCount_Set(TIMER_Index index, uint32_t count);
+
+
+/**
+ * @brief Get timer loadcount.
+ *
+ * @param index timer index.
+ * @return uint32_t loadcount of this timer.
+ */
+uint32_t HAL_TIMER_LoadCount_Get(TIMER_Index index);
+
+
+/**
+ * @brief Enable or disable the timer. When enabled, the counter starts counting down from the loadcounter to 0
+ * @param  index: define which timer to operate.
+ * @param  en: Enable or disable the timer.
+ * @return This function has no return.
+ */
+void HAL_TIMER_Enable(TIMER_Index index, TIMER_Enable en);
+
+
+/**
+ * @brief Get the interrupt status of specific timer.
+ * @param  index: define which timer to operate.
+ * @return return 1 means a timer interrupt is active, else inactive.
+ */
+uint8_t HAL_TIMER_Int_Status(TIMER_Index index);
+
+
+/**
+ * @brief Clear the interrupt status of specific timer.
+ * @param  index: define which timer to operate.
+ * @return This function has no return.
+ */
+void HAL_TIMER_Int_Clr(TIMER_Index index);
+
+
+/**
+ * @brief Get the current counter of specific timer.
+ * @param  index: define which timer to operate.
+ * @return It return the current count value.
+ */
+uint32_t HAL_TIMER_Current_Value(TIMER_Index index);
+
+
+/**
+ * @brief Configure and enable the pwm function of timer. Timer should be initialize before using this function. For details please refer to examples.
+          And iomux of pwm should be configed by user. Timer use pwm0-pwm3 in function io
+ * @param  index: define which timer to operate.
+ * @param  high_count: 24bit counter to define high period of pwm
+ * @param  low_count: 24bit counter to define low period of pwm
+ * @return This function has no return.
+ */
+void HAL_TIMER_PWM_Enable(TIMER_Index index, uint32_t high_count, uint32_t low_count);
+
+
+/**
+ * @brief Disable the Timer PWM
+ * @param  index: define which timer to operate.
+ * @return This function has no return.
+ */
+void HAL_TIMER_PWM_Disable(TIMER_Index index);
+
+
+/**
+ * @brief Get all timers interrupt status.
+ *
+ * @return uint8_t 4bit value, one bit for a timer interrupt status after masked operation.
+ */
+uint8_t HAL_TIMERS_IntStat_Get(void);
+
+
+/**
+ * @brief Clear all timers interrupt.
+ *
+ */
+void HAL_TIMERS_INT_Clear(void);
+
+
+/**
+ * @brief Get the raw interrupt status of all timers.
+ *
+ * @return uint8_t
+ */
+uint8_t HAL_TIMERS_RawIntStat_Get(void);
+
+
+/**
+ * @brief Set loadcount2 for the specified timer.
+ *
+ * @param index
+ * @param loadCount2
+ */
+void HAL_TIMER_LoadCount2_Set(TIMER_Index index, uint32_t loadCount2);
+
+
+/**
+ * @brief Get loadcount2 of the specified timer.
+ *
+ * @param index Timer index.
+ * @return uint32_t loadcount2 value.
+ */
+uint32_t HAL_TIMER_LoadCount2_Get(TIMER_Index index);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __HAL_TIMRE_H_ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_trng.h

@@ -0,0 +1,47 @@
+#ifndef __HAL_TRNG_H__
+#define __HAL_TRNG_H__
+
+#include "ll/ll_trng.h"
+
+#define TRNG_INTMASK_VN_ERR         (0x08)
+#define TRNG_INTMASK_CRNGT_ERR      (0x04)
+#define TRNG_INTMASK_AUTOCORR_ERR   (0x02)
+#define TRNG_INTMASK_EHR_VALID      (0x01)
+
+typedef enum
+{
+    Length_Shortest = 0,
+    Length_Short = 1,
+    Length_Long = 2,
+    Length_Longest = 3
+} TrngSrcLength_t;
+
+typedef struct
+{
+    TrngSrcLength_t srcLength; /*!< reset value is shortest. */
+    uint32_t sampleCnt; /*!< how often the TRNG samples the single output bit of the ring oscillator. */
+} TRNG_InitStruct;
+
+
+void HAL_TRNG_Reset(TRNG_Instance *TRNGx);
+
+void HAL_TRNG_Init(TRNG_Instance *TRNGx, TRNG_InitStruct initStruct);
+
+void HAL_TRNG_Start(TRNG_Instance *TRNGx);
+
+void HAL_TRNG_Stop(TRNG_Instance *TRNGx);
+
+uint8_t HAL_TRNG_isDataReady(TRNG_Instance *TRNGx);
+
+uint8_t HAL_TRNG_isBusy(TRNG_Instance *TRNGx);
+
+/**
+ * @brief Get random number form a EHR data register.
+ *
+ * @param TRNGx
+ * @param index EHR register index, 0~5 is valid.
+ * @return uint32_t
+ */
+uint32_t HAL_TRNG_GetRandomNumber(TRNG_Instance *TRNGx, uint8_t index);
+
+#endif // !__HAL_TRNG_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_uart.h

@@ -0,0 +1,344 @@
+#ifndef __HAL_UART_H__
+#define __HAL_UART_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif /* __cplusplus */
+
+#include "ll/ll_uart.h"
+#include "hal/hal_common.h"
+
+
+/****************************  UART Instances: UART  ***********************/
+#define IS_UART_INSTANCE( INSTANCE ) ( (INSTANCE == UART0) || (INSTANCE == UART1) )
+
+#define IS_UART_IT_ENABLE_BITMAP( IT_ENABLE ) ( (IT_ENABLE == UART_INT_EN_RECEIVE_DATA_AVAILABLE)  || \
+                                                (IT_ENABLE == UART_INT_EN_TRANSMIT_HOLD_REG_EMPTY) || \
+                                                (IT_ENABLE == UART_INT_EN_RECEIVER_LINE_STATUS)    || \
+                                                (IT_ENABLE == UART_INT_EN_MODEM_STATUS)            || \
+                                                (IT_ENABLE == UART_INT_EN_PROGRAMMABLE_THRE) )
+
+        
+/**
+ * @brief Uart interrupt bit map
+ */
+typedef enum
+{
+    UART_INT_EN_RECEIVE_DATA_AVAILABLE  = 0x01,
+    UART_INT_EN_TRANSMIT_HOLD_REG_EMPTY = 0x02,
+    UART_INT_EN_RECEIVER_LINE_STATUS    = 0x04,
+    UART_INT_EN_MODEM_STATUS            = 0x08,
+    UART_INT_EN_PROGRAMMABLE_THRE       = 0x80
+} Uart_It_Enable;//Enable the specified UART interrupt
+
+
+/**
+ * @brief Rx trigger level. Above the trigger level, an uart rx interrupt will trigger. Uart Rx Fifo is 8 bytes.
+ */
+typedef enum
+{
+    UART_RCVR_TRIGGER_FIFO_HAS_ONE_CHARACTER   = 0x00,
+    UART_RCVR_TRIGGER_FIFO_ONE_QUARTER_FULL    = 0x01,
+    UART_RCVR_TRIGGER_FIFO_HALF_FULL           = 0x02,
+    UART_RCVR_TRIGGER_FIFO_TWO_LESS_THAN_FULL  = 0x03
+} Uart_RX_Trigger_Lvl;
+
+
+/**
+ * @brief Tx trigger level.Below the trigger level, an uart tx interrupt will trigger. Uart Tx Fifo is 8 bytes.
+ */
+typedef enum
+{
+    UART_TX_EMPTY_TRIGGER_FIFO_EMPTY              = 0x00,
+    UART_TX_EMPTY_TRIGGER_TWO_CHARACTERS_IN_FIFO  = 0x01,
+    UART_TX_EMPTY_TRIGGER_ONE_QUARTER_FULL        = 0x02,
+    UART_TX_EMPTY_TRIGGER_HALF_FULL               = 0x03
+} Uart_TX_Trigger_Lvl;
+
+
+/**
+ * @brief Set Uart DMA mode
+ */
+typedef enum
+{
+    UART_DMA_MODE0 = 0,
+    UART_DMA_MODE1
+} Uart_Dma_Mode;
+
+
+/**
+ * @brief The status of the uart interrupt.
+ */
+typedef enum
+{
+	UART_INT_ID_MODEM_STATUS             = 0,
+	UART_INT_ID_NO_INTERRUPT_PENDING     = 1,
+	UART_INT_ID_THR_EMPTY                = 2, //Transmitter holding register empty
+	UART_INT_ID_RECV_DATA_AVAILABLE      = 4,
+	UART_INT_ID_RECV_LINE_STATUS         = 6,
+	UART_INT_ID_BUSY_DETECT              = 7,
+	UART_INT_ID_RECV_CHAR_TIMEOUT        = 12
+} Uart_Int_Id;
+
+
+/**
+ * @brief Data Length Select. The number of bits that may be selected are 5, 6, 7, 8bits
+ */
+typedef enum
+{
+	UART_DATALEN_5BIT = 0x00,
+	UART_DATALEN_6BIT = 0x01,
+	UART_DATALEN_7BIT = 0x02,
+	UART_DATALEN_8BIT = 0x03,
+} Uart_DataLength;
+
+/**
+ * @brief Select type of parity check.
+ */
+typedef enum
+{
+	UART_PARITY_NONE = 0,
+	UART_PARITY_ODD  = 1,
+	UART_PARITY_EVEN = 2,
+} Uart_Parity;
+
+/**
+ * @brief Number of stop bits. 
+ * If set to stop_bit_1_5_OR_2 and the data bits are set to 5, one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted.
+ */
+typedef enum
+{
+	UART_STOP_BIT_1 	   = 0,
+	UART_STOP_BIT_1_5_OR_2 = 1, //Note:When the UART_DATALEN is set to 5 bits, the stop bit is 1.5 bit;Otherwise,2 stop bits are transmitted. 
+} Uart_StopBits;
+
+
+/**
+ * @brief Select mode of flow control. When select hardware flow control, rts is controlled by hardware, otherwise controlled by software.
+ */
+typedef enum
+{
+    UART_FLOW_CONTROL_SOFTWARE = 0x00,
+    UART_FLOW_CONTROL_HARDWARE = 0x01
+} UART_FlowControl;
+
+
+/**
+ * @brief This is the struct to initialize the uart module.
+ */
+typedef struct
+{
+    uint32_t         BaudRate;
+    Uart_DataLength  DataLength;
+    Uart_StopBits    StopBits;
+    Uart_Parity      Parity;
+    UART_FlowControl FlowControl;
+} UART_ConfigTypeDef;
+
+
+/**
+ * @brief Bitmap of line status.
+ */
+typedef enum
+{
+	UART_LSR_DATA_READY       = 0x01,
+	UART_LSR_OVERRUN_ERR      = 0x02,
+	UART_LSR_PARITY_ERR       = 0x04,
+	UART_LSR_FRAMING_ERR      = 0x08,
+	UART_LSR_BREAK_INT        = 0x10,
+	UART_LSR_TX_HOLDING_EMPTY = 0x20,
+	UART_LSR_TX_EMPTY         = 0x40,
+	UART_LSR_RECV_FIFO_ERR    = 0x80,
+    UART_LSR_ADDR_RECEIVED    = 0x100
+} Uart_Line_Status;
+
+
+/**
+ * @brief Bitmap of Modem Status
+ */
+typedef enum
+{
+    UART_MODEM_STATUS_DELTA_CLEAR_TO_SEND           = 0x01,
+    UART_MODEM_STATUS_DELTA_DATA_SET_READY          = 0x02,
+    UART_MODEM_STATUS_TRAILING_EDGE_RING_INDICATOR  = 0x04,
+    UART_MODEM_STATUS_DELTA_DATA_CARRIER_DETECT     = 0x08,
+    UART_MODEM_STATUS_CLEAR_TO_SEND                 = 0x10,
+    UART_MODEM_STATUS_DATA_SET_READY                = 0x20,
+    UART_MODEM_STATUS_RING_INDICATOR                = 0x40,
+    UART_MODEM_STATUS_DATA_CARRIER_DETECT           = 0x80
+} Uart_Modem_Status;
+
+
+/**
+ * @brief Bitmap of Uart normal Status
+ */
+typedef enum
+{
+    UART_STATUS_UART_BUSY               = 0x01,
+    UART_STATUS_TRANSMIT_FIFO_NOT_FULL  = 0x02,
+    UART_STATUS_TRANSMIT_FIFO_EMPTY     = 0x04,
+    UART_STATUS_RECEIVE_FIFO_NOT_EMPTY  = 0x08,
+    UART_STATUS_RECEIVE_FIFO_FULL       = 0x10
+} Uart_Status;
+
+typedef struct
+{
+	UartInstance       *Instance;
+	UART_ConfigTypeDef Config;
+} UART_DevTypeDef;
+
+typedef void (*pIsrRecvCharCb)(uint8_t *ch);
+typedef void (*pIsrSendCharCb)(uint8_t *ch);
+void HAL_UART_SetIsrRecvCharCallback(UartInstance * pUARTx, pIsrRecvCharCb callback_fun);
+void HAL_UART_SetIsrSendCharCallback(UartInstance * pUARTx, pIsrSendCharCb callback_fun);
+
+/****************************  Function Declaration  ************************/
+
+/**
+ * @brief Initialize an UART, config its baudrate, datalenth, stopbits, and parity check, flow control.
+ *  
+ * @param[in]  pUartDev the UART interface
+ * @return  HAL_OK for OK, HAL_ERROR for error.
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_DevTypeDef *pUartDev);
+
+/**
+ * @brief Deinitialize an UART.
+ * 
+ * @param hw Serial layer, which contains an UART instance.
+ */
+HAL_StatusTypeDef HAL_UART_Deinit(UART_DevTypeDef *pUartDev);
+
+
+/**
+ * @brief Set TX, RX FIFO depth and DMA mode.
+ * 
+ * @param hw Serial layer, which contains an UART instance.
+ * @param tx_lvl TX FIFO empty trigger level.
+ * @param rx_lvl  RX FIFO trigger level.
+ * @param dma_mode DMA mode.
+ */
+void HAL_UART_FIFOControl(UART_DevTypeDef *pUartDev, Uart_TX_Trigger_Lvl tx_lvl, Uart_RX_Trigger_Lvl rx_lvl, Uart_Dma_Mode dma_mode);
+
+
+/**
+ * @brief Set flow control. (Only UART0 Support AFCE -- hardware flow control.)
+ * @param hw Serial layer, which contains an UART instance.
+ * @param on true -- for hardware flow control; false for software flow control.
+ */
+void HAL_UART_Flow_Control(UART_DevTypeDef *pUartDev, bool on);
+
+
+/**
+ * @brief Wait for TX FIFO empty.
+ * 
+ * @param hw Serial layer, which contains an UART instance.
+ */
+void HAL_UART_Finish_Transfer(UART_DevTypeDef *pUartDev);
+
+/**
+ * Config band rate of a UART interface
+ * @param[in]  pUartDev the UART interface
+ * @param[in]  baudRate  band rate (9600:误码率,115200:误码率,230400:误码率)
+ * @return     HAL_OK for OK, others for error.
+ */
+HAL_StatusTypeDef HAL_UART_BaudRateConfig(UART_DevTypeDef *pUartDev, uint32_t baudRate);
+
+/**
+ * Init a UART interface
+ * @param[in]  pUartDev the UART interface
+ * @return  HAL_OK for OK, HAL_ERROR for error.
+ */
+HAL_StatusTypeDef HAL_UART_Init_Raw(UART_DevTypeDef *pUartDev);
+
+/**
+ * @brief Get Modem Status, which contains information like Data Carrier Detect,
+ * Ring Indicator, Data Set Ready, Clear to Send, Delta Data Carrier Detect, 
+ * Trailing Edge of Ring Indicator, Delta Data Set Ready, Delta Clear to Send.
+ * 
+ * @param hw Serial layer, which contains an UART instance.
+ * @return uint8_t Modem status, ORed bits, @see Uart_Modem_Status.
+ */
+Uart_Modem_Status HAL_UART_Get_Modem_Status(UART_DevTypeDef *pUartDev);
+
+
+/**
+ * @brief Set Low Power parameter. (Only UART0 supports low power mode.)
+ * 
+ * @param hw Serial layer, which contains an UART instance.
+ * @param divisor 
+ */
+void HAL_UART_Low_Power_Set(UART_DevTypeDef *pUartDev, uint16_t divisor);
+
+
+/**
+ * @brief Enable/Disable specifical UART Interrupt.
+ * 
+ * @param hw Serial layer, which contains an UART instance.
+ * @param en true -- enabe; false -- disable.
+ */
+void HAL_UART_INT_Switch_RecvDataAvailable(UART_DevTypeDef *pUartDev, uint8_t en);
+void HAL_UART_INT_Switch_TransmitHoldingRegEmpty(UART_DevTypeDef *pUartDev, uint8_t en);
+void HAL_UART_INT_Switch_RecvLineStatus(UART_DevTypeDef *pUartDev, uint8_t en);
+void HAL_UART_INT_Switch_ModemStatus(UART_DevTypeDef *pUartDev, uint8_t en);
+void HAL_UART_INT_Switch_ProgramTransmitHoldingRegEmpty(UART_DevTypeDef *pUartDev, uint8_t en);
+
+
+/**
+ * Read one byte on a UART interface in the polling mode
+ * @param[in]  pUartDev the UART interface
+ * @param[in]  pData    pointer to the data
+ * @return  HAL_OK for OK, HAL_TIMEOUT for timeout.
+ */
+HAL_StatusTypeDef HAL_UART_ReadOneChar(UartInstance *pUARTx, uint8_t * pData);
+
+
+/**
+ * Write one byte on a UART interface in the polling mode
+ * @param[in]  pUartDev the UART interface
+ * @param[in]  pData    pointer to the data
+ * @return  HAL_OK for OK, HAL_TIMEOUT for timeout.
+ */
+HAL_StatusTypeDef HAL_UART_WriteOneChar(UartInstance *pUARTx, uint8_t * pData);
+
+
+/**
+ * Receive data on a UART interface in the polling mode
+ * @param[in]  pUartDev   the UART interface
+ * @param[in]  pData      pointer to the start of data
+ * @param[in]  expectSize number of bytes to transmit
+ * @param[in]  timeOut    timeOut in milisecond, set this value to HAL_WAIT_FOREVER
+ *                        if you want to wait forever
+ * @return  >=0 : actual number of recive, -1 : if an error occurred with any step
+ */
+int32_t HAL_UART_ReceiveDataPolling(UART_DevTypeDef *pUartDev, void * pData, uint32_t expectSize, uint32_t timeOut);
+
+
+
+/**
+ * Transmit data on a UART interface in the polling mode
+ * @param[in]  pUartDev the UART interface
+ * @param[in]  pData    pointer to the start of data
+ * @param[in]  dataLen     number of bytes to transmit
+ * @param[in]  timeOut  timeOut in milisecond, set this value to HAL_WAIT_FOREVER
+ *                      if you want to wait forever
+ * @return  >=0 : actual number of sent, -1 : if an error occurred with any step
+ */
+int32_t HAL_UART_TransmitDataPolling(UART_DevTypeDef *pUartDev, const void * pData, uint32_t dataLen, uint32_t timeOut);
+
+
+/**
+ * @brief Enable/Disable all UART interrupts.
+ * 
+ * @param pUartDev  the UART interface.
+ * @param enable 
+ */
+void HAL_UART_INT_Switch_All(UART_DevTypeDef *pUartDev, bool enable);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __HAL_UART_H__ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/hal_wdt.h

@@ -0,0 +1,149 @@
+#ifndef __HAL_WDT_H_
+#define __HAL_WDT_H_
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cpluscplus
+
+#include "types.h"
+
+/******************************  Data Type and Macros  **********************/
+/**
+ * @brief Watch dog has two reset mode.
+ */
+typedef enum wdt_resetmode
+{
+    WDT_RESET_DIRECT = 0,           ///**< WDT_RESET_DIRECT: watch dog will directly reset the mcu as soon as watch dog triggerred */
+    WDT_RESET_IRQ = 1               ///**< WDT_RESET_IRQ: watch dog will first trigger an interrupt. if we don't reset watch dog after another period of time, it will reset mcu */
+} WDT_ResetMode;
+
+/**
+ * @brief Define the pulse width to reset the mcu
+ */
+typedef enum wdt_resetpulse
+{
+    WDT_RESET_PULSE_2_PCLK = 0,
+    WDT_RESET_PULSE_4_PCLK,
+    WDT_RESET_PULSE_8_PCLK,
+    WDT_RESET_PULSE_16_PCLK,
+    WDT_RESET_PULSE_32_PCLK,
+    WDT_RESET_PULSE_64_PCLK,
+    WDT_RESET_PULSE_128_PCLK,
+    WDT_RESET_PULSE_256_PCLK,
+    WDT_RESET_PULSE_MAX = 0x8
+} WDT_ResetPulse;
+
+/**
+ * @brief Define the how many pclk to wait before wdt int trigger. For example WDT_PERIOD_3FF means the period wdt int trigger is 0x3ff cycles
+ */
+typedef enum wdt_timeoutperiod
+{
+    WDT_PERIOD_FF       = 0,    // 8ms @40MHz
+    WDT_PERIOD_1FF      = 1,    // 16ms @40MHz
+    WDT_PERIOD_3FF      = 2,    // 32ms @40MHz
+    WDT_PERIOD_7FF      = 3,    // 64ms @40MHz
+    WDT_PERIOD_FFF      = 4,    // 128ms @40MHz
+    WDT_PERIOD_1FFF     = 5,    // 256ms @40MHz
+    WDT_PERIOD_3FFF     = 6,    // 512ms @40MHz
+    WDT_PERIOD_7FFF     = 7,    // 1024ms @40MHz
+    WDT_PERIOD_FFFF     = 8,    // 2048ms @40MHz
+    WDT_PERIOD_1FFFF    = 9,    // 4096ms @40MHz
+    WDT_PERIOD_3FFFF    = 10,   // 8192ms @40MHz
+    WDT_PERIOD_7FFFF    = 11,   // 16384ms @40MHz
+    WDT_PERIOD_FFFFF    = 12,   // 32768ms @40MHz
+    WDT_PERIOD_1FFFFF   = 13,   // 65536ms @40MHz
+    WDT_PERIOD_3FFFFF   = 14,   // 131072ms @40MHz
+    WDT_PERIOD_7FFFFF   = 15    // 262144ms @40MHz
+} WDT_TimeoutPeriod;
+
+
+/**
+ * @brief Struct to define parameter of watch dog. 
+ */
+typedef struct wdt_inittypedef
+{
+		WDT_ResetMode   mode;
+		WDT_ResetPulse  pulse_width;
+		WDT_TimeoutPeriod period;
+} WDT_InitTypeDef;
+
+
+#define IS_WDT_RESET_MODE(mode)         ( (mode) == WDT_RESET_DIRECT || (mode) == WDT_RESET_IRQ )
+#define IS_WDT_RESET_PULSE(pulse)       ( (pulse) == WDT_RESET_PULSE_2_PCLK      || \
+                                          (pulse) == WDT_RESET_PULSE_4_PCLK      || \
+                                          (pulse) == WDT_RESET_PULSE_8_PCLK      || \
+                                          (pulse) == WDT_RESET_PULSE_16_PCLK     || \
+                                          (pulse) == WDT_RESET_PULSE_32_PCLK     || \
+                                          (pulse) == WDT_RESET_PULSE_64_PCLK     || \
+                                          (pulse) == WDT_RESET_PULSE_128_PCLK    || \
+                                          (pulse) == WDT_RESET_PULSE_256_PCLK    || \
+                                          (pulse) == WDT_RESET_PULSE_MAX )
+
+#define IS_WDT_TIMEOUT_PERIOD(period)   ( (period) == WDT_PERIOD_FF     || \
+                                          (period) == WDT_PERIOD_1FF    || \
+                                          (period) == WDT_PERIOD_3FF    || \
+                                          (period) == WDT_PERIOD_7FF    || \
+                                          (period) == WDT_PERIOD_FFF    || \
+                                          (period) == WDT_PERIOD_1FFF   || \
+                                          (period) == WDT_PERIOD_3FFF   || \
+                                          (period) == WDT_PERIOD_7FFF   || \
+                                          (period) == WDT_PERIOD_FFFF   || \
+                                          (period) == WDT_PERIOD_1FFFF  || \
+                                          (period) == WDT_PERIOD_3FFFF  || \
+                                          (period) == WDT_PERIOD_7FFFF  || \
+                                          (period) == WDT_PERIOD_FFFFF  || \
+                                          (period) == WDT_PERIOD_1FFFFF || \
+                                          (period) == WDT_PERIOD_3FFFFF || \
+                                          (period) == WDT_PERIOD_7FFFFF )
+
+
+/******************************  Function Declaration  **********************/
+/**
+ * @brief Enable the watch dog. Once enabled it cannot be disabled.
+ * @return This function has no return value.
+ */
+void HAL_WDT_Enable(void);
+
+/**
+ * @brief Set the watch dog timeout period
+ * @param  period: the period to trigger an wdt interrupt. For example WDT_PERIOD_3FF means the period wdt int trigger is 0x3ff cycles
+ * @return This function has no return value.
+ */
+void HAL_WDT_SetTimeoutPeriod(WDT_TimeoutPeriod period);
+
+/**
+ * @brief Clears the watchdog interrupt. This can be used to clear the interrupt without restarting the watchdog counter.
+ * @return return 1 when an interrupt is triggered.
+ */
+uint8_t HAL_WDT_ClrIRQ(void);
+
+/**
+ * @brief Get the current value of the internal counter
+ * @return return the current value of the internal counter.
+ */
+uint16_t HAL_WDT_CurrentCounter(void);
+
+/**
+ * @brief To restart the WDT counter (and clear WDT interrupt.)
+ * @return This function has no return value.
+ */
+void HAL_WDT_Restart(void);
+
+/**
+ * @brief To get the interrupt status of the WDT.
+ * @return return the interrupt status. 0 means interrupt is inactive, 1 means interrupt is active.
+ */
+uint8_t HAL_WDT_IntStatus(void);
+
+/**
+ * @brief Initialize the watch dog
+ * @param config: Struct to define parameter of watch dog. 
+ * @return This function has no return value.
+ */
+void HAL_WDT_Init(WDT_InitTypeDef config);
+
+
+#ifdef __cplusplus
+}
+#endif // __cpluscplus
+#endif /* __HAL_WDT_H_ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/qspi.h

@@ -0,0 +1,126 @@
+#ifndef __QSPI_H__
+#define __QSPI_H__
+
+#include <stdint.h>
+#include "proj_config.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/***************************  Data types and Macros  *************************/
+
+#define QSPI_READ_MAX_LENGTH            0x10000
+#define QSPI_TX_FIFO_DEPTH              16
+#define QSPI_RX_FIFO_DEPTH              16
+#define QSPI_SLAVE_INDEX                1
+#define QSPI_DMA_Receive_Data_Level     8  //match with DMAC.CTL.SRC_MSIZE
+#define QSPI_DMA_Transmit_Data_Level    8  //match with DMAC.CTL.DST_MSIZE
+
+typedef enum
+{
+    INSTRUCTION_LENGTH_0_BIT = 0,
+    INSTRUCTION_LENGTH_4_BITS,
+    INSTRUCTION_LENGTH_8_BITS,
+    INSTRUCTION_LENGTH_16_BITS,
+} SPI_CTRLR0_INST_L_FIELD;
+
+typedef enum
+{
+    ADDR_WIDTH_0_BIT = 0,
+    ADDR_WIDTH_4_BITS,
+    ADDR_WIDTH_8_BITS,
+    ADDR_WIDTH_12_BITS,
+    ADDR_WIDTH_16_BITS,
+    ADDR_WIDTH_20_BITS,
+    ADDR_WIDTH_24_BITS,
+    ADDR_WIDTH_28_BITS,
+    ADDR_WIDTH_32_BITS,
+    ADDR_WIDTH_36_BITS,
+    ADDR_WIDTH_40_BITS,
+    ADDR_WIDTH_44_BITS,
+    ADDR_WIDTH_48_BITS,
+    ADDR_WIDTH_52_BITS,
+    ADDR_WIDTH_56_BITS,
+    ADDR_WIDTH_60_BITS
+} SPI_CTRLR0_ADDR_L_FIELD;
+
+typedef enum
+{
+    BOTH_STANDARD_SPI_MODE = 0,
+    INSTRUCTION_STANDARD_ADDRESS_SPECIFIC,
+    BOTH_SPECIFIC_MODE,
+} SPI_CTRLR0_TRANS_TYPE_FIELD;
+
+/********************************  sanity check  *****************************/
+// TODO: add sanity check here.
+
+/****************************  Function Declaration  *************************/
+
+/**
+ * @brief QSPI init.
+ * 
+ * @param clk_divider 
+ * @param rx_sample_dly 
+ */
+void qspi_init(uint16_t clk_divider, uint8_t rx_sample_dly);
+
+/**
+ * @brief QSPI deinit.
+ */
+void qspi_deinit(void);
+
+/**
+ * @brief Write data via Standard SPI format.
+ * 
+ * @param bufptr 
+ * @param length 
+ */
+void qspi_standard_write(uint8_t *bufptr, uint32_t length);
+
+/**
+ * @brief Send a cmd, which is represented by `wr_ptr`, and wait for data, which is represented by `rd_ptr`.
+ * 
+ * @param rd_ptr read buffer.
+ * @param rd_len expected read length in bytes.
+ * @param wr_ptr cmd buffer.
+ * @param wr_len cmd buffer length.
+ */
+void qspi_standard_read_byte(uint8_t *rd_ptr, uint32_t rd_len, uint8_t *wr_ptr, uint8_t wr_len);
+
+/**
+ * @brief Read data from FLASH via Standard SPI format.
+ * 
+ * @param rd_ptr read buffer. 
+ * @param rd_len_in_word expected read length in WORD size.
+ * @param instruction cmd.
+ * @param addr address on FLASH.
+ */
+void qspi_standard_read_word(uint32_t *rd_ptr, uint32_t rd_len_in_word, uint8_t instruction, uint32_t addr);
+
+/**
+ * @brief Read data via Dual SPI format.
+ * 
+ * @param rd_ptr 
+ * @param rd_len_in_word 
+ * @param instruction 
+ * @param addr 
+ * @param wait_cycles 
+ */
+void qspi_flash_dual_read_word(uint32_t *rd_ptr, uint32_t rd_len_in_word, uint8_t instruction, uint32_t addr, uint8_t wait_cycles);
+
+/**
+ * @brief Read data via Quad SPI format.
+ * 
+ * @param rd_ptr 
+ * @param rd_len_in_word 
+ * @param instruction 
+ * @param addr 
+ * @param wait_cycles 
+ */
+void qspi_flash_quad_read_word(uint32_t *rd_ptr, uint32_t rd_len_in_word, uint8_t instruction, uint32_t addr, uint8_t wait_cycles);
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+#endif // __QSPI_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/sd_card.h

@@ -0,0 +1,72 @@
+#ifndef __SD_CARD_H__
+#define __SD_CARD_H__
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+///////////////////////////////////////////////////////////////////////////////
+////////      SD card interface, only supported for SPI operations   //////////
+///////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////  SD Type  ////////////////////////////////////
+#define SD_TYPE_ERR     0X00
+#define SD_TYPE_MMC     0X01
+#define SD_TYPE_V1      0X02
+#define SD_TYPE_V2      0X04
+#define SD_TYPE_V2HC    0X06
+
+//////////////////////////////////  SD command  ///////////////////////////////
+#define CMD0    0       // reset
+#define CMD1    1
+#define CMD8    8       // SEND_IF_COND
+#define CMD9    9       // read CSD
+#define CMD10   10      // read CID
+#define CMD12   12      // stop transmission
+#define CMD16   16      // set SectorSize, it should return 0x00
+#define CMD17   17      // read sector
+#define CMD18   18      // read multi sectors
+#define CMD23   23      // set multi sectors, erase multi blocks before writing.
+#define CMD24   24      // write sector
+#define CMD25   25      // write multi sectors
+#define CMD41   41      // it should return 0x00
+#define CMD55   55      // it should return 0x01
+#define CMD58   58      // read OCR information
+#define CMD59   59      // enable/disable CRC, it should return 0x00
+
+// response when writing data
+#define MSD_DATA_OK                0x05
+#define MSD_DATA_CRC_ERROR         0x0B
+#define MSD_DATA_WRITE_ERROR       0x0D
+#define MSD_DATA_OTHER_ERROR       0xFF
+
+// response when sending command
+#define MSD_RESPONSE_NO_ERROR      0x00
+#define MSD_IN_IDLE_STATE          0x01
+#define MSD_ERASE_RESET            0x02
+#define MSD_ILLEGAL_COMMAND        0x04
+#define MSD_COM_CRC_ERROR          0x08
+#define MSD_ERASE_SEQUENCE_ERROR   0x10
+#define MSD_ADDRESS_ERROR          0x20
+#define MSD_PARAMETER_ERROR        0x40
+#define MSD_RESPONSE_FAILURE       0xFF
+
+uint8_t  SD_Init(void);
+uint8_t  SD_GetType(void);
+uint8_t  SD_SPI_ReadWriteByte(uint8_t data);
+void     SD_SPI_SpeedLow(void);
+void     SD_SPI_SpeedHigh(void);
+uint8_t  SD_WaitReady(void);
+uint8_t  SD_GetResponse(uint8_t Response);
+uint8_t  SD_ReadDisk(uint8_t*buf,uint32_t sector,uint8_t cnt);
+uint8_t  SD_WriteDisk(uint8_t*buf,uint32_t sector,uint8_t cnt);
+uint32_t SD_GetSectorCount(void);
+uint8_t  SD_GetCID(uint8_t *cid_data);
+uint8_t  SD_GetCSD(uint8_t *csd_data);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __SD_CARD_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/simi2c.h

@@ -0,0 +1,31 @@
+#ifndef __SOFT_I2C_H__
+#define __SOFT_I2C_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+void I2C_Delay(uint16_t dly);
+void I2C_Init(void);
+void I2C_Start(void);
+void I2C_Stop(void);
+uint8_t I2C_GetAck(void);
+void I2C_PutAck(uint8_t ack);
+void I2C_WriteByte(uint8_t data);
+uint8_t I2C_ReadByte(uint8_t ack);
+
+uint8_t OLED_Write_Command(uint8_t command);
+uint8_t OLED_Write_Data(uint8_t data);
+void OLED_Fill(uint8_t _8pixel);
+void OLED_ClearScreen(void);
+void OLED_FillDot(void);
+void OLED_On(void);
+void OLED_Off(void);
+void OLED_StartDisplay(void);
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __SOFT_I2C_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/spi_type.h

@@ -0,0 +1,178 @@
+#ifndef __SPI_TYPE_H__
+#define __SPI_TYPE_H__
+
+#ifdef __cplusplus
+	extern "C" {
+#endif // __cplusplus
+
+// TODO: rename data types.
+typedef enum
+{
+	Standard_SPI_Format = 0,
+	Dual_SPI_Format = 1,
+	Quad_SPI_Format = 2,
+} SPI_Format;
+
+typedef enum
+{
+	DFS_32_4_bits = 3,
+	DFS_32_5_bits ,
+	DFS_32_6_bits ,
+	DFS_32_7_bits ,
+	DFS_32_8_bits ,
+	DFS_32_9_bits ,
+	DFS_32_10_bits ,
+	DFS_32_11_bits ,
+	DFS_32_12_bits ,
+	DFS_32_13_bits ,
+	DFS_32_14_bits ,
+	DFS_32_15_bits ,
+	DFS_32_16_bits ,
+	DFS_32_17_bits ,
+	DFS_32_18_bits ,
+	DFS_32_19_bits ,
+	DFS_32_20_bits ,
+	DFS_32_21_bits ,
+	DFS_32_22_bits ,
+	DFS_32_23_bits ,
+	DFS_32_24_bits ,
+	DFS_32_25_bits ,
+	DFS_32_26_bits ,
+	DFS_32_27_bits ,
+	DFS_32_28_bits ,
+	DFS_32_29_bits ,
+	DFS_32_30_bits ,
+	DFS_32_31_bits ,
+	DFS_32_32_bits
+} SPI_Dataframe_Size;
+
+typedef enum
+{
+	Control_Word_1_bit = 0,
+	Control_Word_2_bit ,
+	Control_Word_3_bit ,
+	Control_Word_4_bit ,
+	Control_Word_5_bit ,
+	Control_Word_6_bit ,
+	Control_Word_7_bit ,
+	Control_Word_8_bit ,
+	Control_Word_9_bit ,
+	Control_Word_10_bit ,
+	Control_Word_11_bit ,
+	Control_Word_12_bit ,
+	Control_Word_13_bit ,
+	Control_Word_14_bit ,
+	Control_Word_15_bit ,
+	Control_Word_16_bit ,
+} SPI_Controlframe_Size;
+
+typedef enum
+{
+	Slave_txd_Enabled = 0,
+	Slave_txd_Disabled
+} SPI_Slave_Output_Enable;
+
+typedef enum
+{
+	Transmit_and_Receive = 0,
+	Transmit_Only,
+	Receive_Only,
+	EEPROM_Read
+} SPI_Transmit_Mode;
+
+typedef enum
+{
+	Inactive_Low = 0,
+	Inactive_High
+} SPI_Clock_Polarity;
+
+typedef enum
+{
+	SCLK_Toggle_In_Middle = 0,
+	SCLK_Toggle_At_Start
+} SPI_Clock_Phase;
+
+typedef enum
+{
+	Motorola_SPI = 0,
+	Texas_Instruments_SSP,
+	National_Semiconductors_Microwire,
+} SPI_Protocol_Type;
+
+typedef enum
+{
+	Microwire_Receive = 0,
+	Microwire_Transmit
+} SPI_Microwire_Control;
+
+typedef enum
+{
+	Non_Sequential_Transfer = 0,
+	Sequential_Transfer
+} SPI_Microwire_Mode;
+
+typedef enum
+{
+	SSI_Disabled = 0,
+	SSI_Enabled
+} SPI_En;
+
+typedef enum
+{
+	No_Transmit_Data_Collision_Error = 0,
+	Transmit_Data_Collision_Error
+} SPI_Status_Dcol;
+
+typedef enum
+{
+	No_Transmission_Error = 0,
+	Transmission_Error
+} SPI_Status_TXE;
+
+typedef enum
+{
+	Receive_FIFO_Not_Full = 0,
+	Receive_FIFO_Full
+} SPI_Status_RFF;
+
+typedef enum
+{
+	Receive_FIFO_Empty = 0,
+	Receive_FIFO_Not_Empty
+} SPI_Status_RFNE;
+
+typedef enum
+{
+	Transmit_FIFO_Not_Empty = 0,
+	Transmit_FIFO_Empty
+} SPI_Status_TFE;
+
+typedef enum
+{
+	Transmit_FIFO_Full = 0,
+	Transmit_FIFO_Not_Full
+} SPI_Status_TFNF;
+
+typedef enum
+{
+	SSI_Idle_or_Disabled = 0,
+	SSI_Busy
+} SPI_Status_Busy;
+
+typedef enum
+{
+	Transmit_DMA_Disabled = 0,
+	Transmit_DMA_Enabled
+} SPI_TXDMA_En;
+
+typedef enum
+{
+	Receive_DMA_Disabled = 0,
+	Receive_DMA_Enabled
+} SPI_RXDMA_En;
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __SPI_TYPE_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/spim.h

@@ -0,0 +1,19 @@
+#ifndef __SPIM_H__
+#define __SPIM_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+void spim_init(uint32_t baud);
+// FIXME: uint8_t ? <at least be uint16_t>
+int spim_write(uint8_t addr, uint16_t data);
+int spim_read(uint8_t addr, uint16_t *data);
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __SPIM_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/hal/syscon_types.h

@@ -0,0 +1,377 @@
+#ifndef _SYSCON_TYPES_H_
+#define _SYSCON_TYPES_H_
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+
+
+// PORT A ranges GPIOA_0 to GPIOA_15
+#define GPIO_PWIDTH_A 16
+
+
+/**
+ * @brief enum of GPIO_Num.
+ */
+typedef enum
+{
+	GPIOA_0  =  0,//gpio port A
+	GPIOA_1  =  1,
+	GPIOA_2  =  2,
+	GPIOA_3  =  3,
+	GPIOA_4  =  4,
+	GPIOA_5  =  5,
+	GPIOA_6  =  6,
+	GPIOA_7  =  7,
+	GPIOA_8  =  8,
+	GPIOA_9  =  9,
+	GPIOA_10 = 10,
+	GPIOA_11 = 11,
+	GPIOA_12 = 12,
+	GPIOA_13 = 13,
+	GPIOA_14 = 14,
+	GPIOA_15 = 15,
+	GPIOB_0  = 16,//gpio port B
+	GPIOB_1  = 17,
+	GPIOB_2  = 18,
+	GPIOB_3  = 19,
+	GPIOB_4  = 20,
+	GPIOB_5  = 21,
+	GPIOB_6  = 22,
+	GPIOB_7  = 23,
+	GPIOB_8  = 24,
+	GPIOB_9  = 25,
+	GPIO_NUM_MAX = 26,
+} GPIO_Num;
+
+#define IS_PORTA_GPIO(num)      ( (num) == GPIOA_0  || \
+                                    (num) == GPIOA_1  || \
+                                    (num) == GPIOA_2  || \
+                                    (num) == GPIOA_3  || \
+                                    (num) == GPIOA_4  || \
+                                    (num) == GPIOA_5  || \
+                                    (num) == GPIOA_6  || \
+                                    (num) == GPIOA_7  || \
+                                    (num) == GPIOA_8  || \
+                                    (num) == GPIOA_9  || \
+                                    (num) == GPIOA_10 || \
+                                    (num) == GPIOA_11 || \
+                                    (num) == GPIOA_12 || \
+                                    (num) == GPIOA_13 || \
+                                    (num) == GPIOA_14 || \
+                                    (num) == GPIOA_15 )
+
+
+typedef enum
+{
+	GPIO_AF_I2C0_SCL     = 0, //I2C0,I2C1
+	GPIO_AF_I2C0_SDA     = 1,
+	GPIO_AF_I2C1_SCL     = 2,
+	GPIO_AF_I2C1_SDA     = 3,
+	GPIO_AF_UART0_TX     = 4, //UART0,UART1
+	GPIO_AF_UART0_RX     = 5,
+	GPIO_AF_UART0_RTS    = 6,
+	GPIO_AF_UART0_CTS    = 7,
+	GPIO_AF_UART1_TX     = 8,
+	GPIO_AF_UART1_RX     = 9,
+	GPIO_AF_TIMER0_PWM   = 10,//TIMERx_PWM,PWM
+	GPIO_AF_TIMER1_PWM   = 11,
+	GPIO_AF_TIMER2_PWM   = 12,
+	GPIO_AF_TIMER3_PWM   = 13,
+	GPIO_AF_PWM0         = 14,
+	GPIO_AF_PWM1         = 15,
+	GPIO_AF_PWM2         = 16,
+	GPIO_AF_PWM3         = 17,
+	GPIO_AF_PWM4         = 18,
+	GPIO_AF_PWM5         = 19,
+	GPIO_AF_PWM6         = 20,
+	GPIO_AF_PWM7         = 21,
+	GPIO_AF_PWM8         = 22,
+	GPIO_AF_PWM9         = 23,
+	GPIO_AF_PWM10        = 24,
+	GPIO_AF_PWM11        = 25,
+	GPIO_AF_SPI_M1_CLK   = 26,//SPI_Master1
+	GPIO_AF_SPI_M1_CS    = 27,
+	GPIO_AF_SPI_M1_MOSI  = 28,
+	GPIO_AF_SPI_M1_MISO  = 29,
+	GPIO_AF_SPI_S0_CLK   = 30,//SPI_Slaver0
+	GPIO_AF_SPI_S0_CS    = 31,
+	GPIO_AF_SPI_S0_MOSI  = 32,
+	GPIO_AF_SPI_S0_MISO  = 33,
+	GPIO_AF_SPI_M0_CLK   = 34,//SPI_Master0
+	GPIO_AF_SPI_M0_CS    = 35,
+	GPIO_AF_SPI_M0_MOSI  = 36,
+	GPIO_AF_SPI_M0_MISO  = 37,
+} GPIO_AltFunctionType;
+
+
+
+typedef enum
+{
+    GPIO_AF_IO_0  = 0,
+    GPIO_AF_IO_1  = 1,
+    GPIO_AF_IO_2  = 2,
+    GPIO_AF_IO_3  = 3,
+    GPIO_AF_IO_4  = 4,
+    GPIO_AF_IO_5  = 5,
+    GPIO_AF_IO_6  = 6,
+    GPIO_AF_IO_7  = 7,
+    GPIO_AF_IO_8  = 8,
+    GPIO_AF_IO_9  = 9,
+    GPIO_AF_IO_10 = 10,
+    GPIO_AF_IO_11 = 11,
+    GPIO_AF_IO_12 = 12,
+    GPIO_AF_IO_13 = 13,
+    GPIO_AF_IO_14 = 14,
+    GPIO_AF_IO_15 = 15,
+    GPIO_AF_IO_16 = 16,
+    GPIO_AF_IO_17 = 17,
+    GPIO_AF_IO_18 = 18,
+    GPIO_AF_IO_19 = 19
+} GPIO_AltFunctionIoIndex;
+
+typedef enum        //reset only one device at a time
+{
+    SW_RST_CORE_PMU = 0,
+    SW_RST_CORE_WIC = 1,
+    SW_RST_CORE_RTC = 2,
+    SW_RST_CORE_PHY = 3,
+    SW_RST_CORE_ALL = 4
+} SYSCON_SwRst_Core;
+
+typedef enum       //reset only one device at a time
+{
+    SW_RST_PATCH  = 0,
+    SW_RST_QSPI   = 1,
+    SW_RST_ADCC   = 2,
+    SW_RST_I2S    = 3,
+    SW_RST_GPIO   = 4,
+    SW_RST_SPIM   = 5,
+    SW_RST_SPIS   = 6,
+    SW_RST_I2C0   = 7,
+    SW_RST_I2C1   = 8,
+    SW_RST_UART0  = 9,
+    SW_RST_UART1  = 10,
+    SW_RST_SPIM2  = 11,
+    SW_RST_WDT    = 12,
+    SW_RST_TIMER  = 13,
+    SW_RST_DBGH   = 14,
+    SW_RST_SDIO   = 15,
+    SW_RST_MAC    = 16,
+    SW_RST_CACHE  = 17,
+    SW_RST_DMA    = 18,
+    SW_RST_RFREG  = 19
+} SYSCON_SwRst_Peripheral;
+
+typedef enum
+{
+    SW_CLKGATE_CORE_RTC    = 0,
+    SW_CLKGATE_CORE_WIC    = 1,
+    SW_CLKGATE_CORE_PHY    = 2,
+    SW_CLKGATE_CORE_MAC20M = 3,
+    SW_CLKGATE_CORE_MAC40M = 4,
+    SW_CLKGATE_CORE_MAC80M = 5
+} SYSCON_ClkGate_Core;
+
+typedef enum
+{
+    SW_CLKGATE_PATCH   = 0,
+    SW_CLKGATE_QSPI    = 1,
+    SW_CLKGATE_ADCC    = 2,
+    SW_CLKGATE_I2S     = 3,
+    SW_CLKGATE_GPIO    = 4,
+    SW_CLKGATE_SPIM    = 5,
+    SW_CLKGATE_SPIS    = 6,
+    SW_CLKGATE_I2C0    = 7,
+    SW_CLKGATE_I2C1    = 8,
+    SW_CLKGATE_UART0   = 9,
+    SW_CLKGATE_UART1   = 10,
+    SW_CLKGATE_SPIM2   = 11,
+    SW_CLKGATE_WDT     = 12,
+    SW_CLKGATE_TIMER   = 13,
+    SW_CLKGATE_TIMER_1 = 14,
+    SW_CLKGATE_TIMER_2 = 15,
+    SW_CLKGATE_TIMER_3 = 16,
+    SW_CLKGATE_TIMER_4 = 17,
+    SW_CLKGATE_DBGH    = 18,
+    SW_CLKGATE_SDIO    = 19,
+    SW_CLKGATE_MAC     = 20,
+    SW_CLKGATE_CACHE   = 21,
+    SW_CLKGATE_DMA     = 22,
+    SW_CLKGATE_RFREG   = 23
+} SYSCON_ClkGate_Peripheral;
+
+typedef enum
+{
+    SPIM_IO_EN0 = 0,
+    SPIM_IO_EN1 = 1,
+    SPIM_IO_EN2 = 2
+} SYSCON_SPIM_Index;
+
+typedef enum
+{
+    I2S_IO_EN0 = 0,
+    I2S_IO_EN1 = 1
+} SYSCON_I2S_Index;
+
+typedef enum
+{
+    SYSCLK_SRC_XTAL = 0,
+    SYSCLK_SRC_PLL
+} SYSTEM_CLOCK_SRC;
+typedef enum
+{
+    SYSTEM_EXT_INT0 = 0,
+    SYSTEM_EXT_INT1 = 1,
+    SYSTEM_EXT_INT2 = 2,
+    SYSTEM_EXT_INT3 = 3,
+    SYSTEM_EXT_INT4 = 4,
+    SYSTEM_EXT_INT5 = 5,
+    SYSTEM_EXT_INT6 = 6,
+    SYSTEM_EXT_INT7 = 7,
+    SYSTEM_EXT_INT_ERROR
+}SYSTEM_EXT_INT_Wakeup_Index;
+typedef enum
+{
+    SYSTEM_EXT_INT_TRIG_HIGH_LEVEL   = 0,
+    SYSTEM_EXT_INT_TRIG_LOW_LEVEL    = 1,
+    SYSTEM_EXT_INT_TRIG_RISING_EDGE  = 2,
+    SYSTEM_EXT_INT_TRIG_FALLING_EDGE = 3,
+}SYSTEM_EXT_INT_Triggle_Type;
+
+
+////////////////////////////////////////  Macros  /////////////////////////////
+#define IS_GPIO_AF_TYPE(type)   ((type) == GPIO_AF_I2C0_SCL    || \
+                                   (type) == GPIO_AF_I2C0_SDA    || \
+                                   (type) == GPIO_AF_I2C1_SCL    || \
+                                   (type) == GPIO_AF_I2C1_SDA    || \
+                                   (type) == GPIO_AF_UART0_TX    || \
+                                   (type) == GPIO_AF_UART0_RX    || \
+                                   (type) == GPIO_AF_UART0_RTS   || \
+                                   (type) == GPIO_AF_UART0_CTS   || \
+                                   (type) == GPIO_AF_UART1_TX    || \
+                                   (type) == GPIO_AF_UART1_RX    || \
+                                   (type) == GPIO_AF_TIMER0_PWM  || \
+                                   (type) == GPIO_AF_TIMER1_PWM  || \
+                                   (type) == GPIO_AF_TIMER2_PWM  || \
+                                   (type) == GPIO_AF_TIMER3_PWM  || \
+                                   (type) == GPIO_AF_PWM0        || \
+                                   (type) == GPIO_AF_PWM1        || \
+                                   (type) == GPIO_AF_PWM2        || \
+                                   (type) == GPIO_AF_PWM3        || \
+                                   (type) == GPIO_AF_PWM4        || \
+                                   (type) == GPIO_AF_PWM5        || \
+                                   (type) == GPIO_AF_PWM6        || \
+                                   (type) == GPIO_AF_PWM7        || \
+                                   (type) == GPIO_AF_PWM8        || \
+                                   (type) == GPIO_AF_PWM9        || \
+                                   (type) == GPIO_AF_PWM10       || \
+                                   (type) == GPIO_AF_PWM11       || \
+                                   (type) == GPIO_AF_SPI_M1_CLK  || \
+                                   (type) == GPIO_AF_SPI_M1_CS   || \
+                                   (type) == GPIO_AF_SPI_M1_MOSI || \
+                                   (type) == GPIO_AF_SPI_M1_MISO || \
+                                   (type) == GPIO_AF_SPI_S0_CLK  || \
+                                   (type) == GPIO_AF_SPI_S0_CS   || \
+                                   (type) == GPIO_AF_SPI_S0_MOSI || \
+                                   (type) == GPIO_AF_SPI_S0_MISO || \
+                                   (type) == GPIO_AF_SPI_M0_CLK  || \
+                                   (type) == GPIO_AF_SPI_M0_CS   || \
+                                   (type) == GPIO_AF_SPI_M0_MOSI || \
+                                   (type) == GPIO_AF_SPI_M0_MISO)
+
+
+
+
+#define IS_GPIO_AF_IO_INDEX(index)  ((index) == GPIO_AF_IO_0  || \
+                                     (index) == GPIO_AF_IO_1  || \
+                                     (index) == GPIO_AF_IO_2  || \
+                                     (index) == GPIO_AF_IO_3  || \
+                                     (index) == GPIO_AF_IO_4  || \
+                                     (index) == GPIO_AF_IO_5  || \
+                                     (index) == GPIO_AF_IO_6  || \
+                                     (index) == GPIO_AF_IO_7  || \
+                                     (index) == GPIO_AF_IO_8  || \
+                                     (index) == GPIO_AF_IO_9  || \
+                                     (index) == GPIO_AF_IO_10 || \
+                                     (index) == GPIO_AF_IO_11 || \
+                                     (index) == GPIO_AF_IO_12 || \
+                                     (index) == GPIO_AF_IO_13 || \
+                                     (index) == GPIO_AF_IO_14 || \
+                                     (index) == GPIO_AF_IO_15 || \
+                                     (index) == GPIO_AF_IO_16 || \
+                                     (index) == GPIO_AF_IO_17 || \
+                                     (index) == GPIO_AF_IO_18 || \
+                                     (index) == GPIO_AF_IO_19)
+
+
+#define IS_SWRST_CORE(core)     ((core) == SW_RST_CORE_PMU || \
+                                 (core) == SW_RST_CORE_WIC || \
+                                 (core) == SW_RST_CORE_RTC || \
+                                 (core) == SW_RST_CORE_PHY || \
+                                 (core) <= SW_RST_CORE_ALL)
+
+#define IS_SWRST_PERIPHERAL(peri)   ((peri) == SW_RST_PATCH || \
+                                     (peri) == SW_RST_QSPI  || \
+                                     (peri) == SW_RST_ADCC  || \
+                                     (peri) == SW_RST_I2S   || \
+                                     (peri) == SW_RST_GPIO  || \
+                                     (peri) == SW_RST_SPIM  || \
+                                     (peri) == SW_RST_SPIS  || \
+                                     (peri) == SW_RST_I2C0  || \
+                                     (peri) == SW_RST_I2C1  || \
+                                     (peri) == SW_RST_UART0 || \
+                                     (peri) == SW_RST_UART1 || \
+                                     (peri) == SW_RST_SPIM2 || \
+                                     (peri) == SW_RST_WDT   || \
+                                     (peri) == SW_RST_TIMER || \
+                                     (peri) == SW_RST_DBGH  || \
+                                     (peri) == SW_RST_SDIO  || \
+                                     (peri) == SW_RST_MAC   || \
+                                     (peri) == SW_RST_CACHE || \
+                                     (peri) == SW_RST_DMA   || \
+                                     (peri) == SW_RST_RFREG)
+
+#define IS_CLKGATE_CORE(clkgate)    ((clkgate) == SW_CLKGATE_CORE_RTC    || \
+                                     (clkgate) == SW_CLKGATE_CORE_WIC    || \
+                                     (clkgate) == SW_CLKGATE_CORE_PHY    || \
+                                     (clkgate) == SW_CLKGATE_CORE_MAC20M || \
+                                     (clkgate) == SW_CLKGATE_CORE_MAC40M || \
+                                     (clkgate) == SW_CLKGATE_CORE_MAC80M)
+
+#define IS_CLKGATE_PERIPHERAL(clkgate)  ((clkgate) == SW_CLKGATE_PATCH   || \
+                                         (clkgate) == SW_CLKGATE_QSPI    || \
+                                         (clkgate) == SW_CLKGATE_ADCC    || \
+                                         (clkgate) == SW_CLKGATE_I2S     || \
+                                         (clkgate) == SW_CLKGATE_GPIO    || \
+                                         (clkgate) == SW_CLKGATE_SPIM    || \
+                                         (clkgate) == SW_CLKGATE_SPIS    || \
+                                         (clkgate) == SW_CLKGATE_I2C0    || \
+                                         (clkgate) == SW_CLKGATE_I2C1    || \
+                                         (clkgate) == SW_CLKGATE_UART0   || \
+                                         (clkgate) == SW_CLKGATE_UART1   || \
+                                         (clkgate) == SW_CLKGATE_SPIM2   || \
+                                         (clkgate) == SW_CLKGATE_WDT     || \
+                                         (clkgate) == SW_CLKGATE_TIMER   || \
+                                         (clkgate) == SW_CLKGATE_TIMER_1 || \
+                                         (clkgate) == SW_CLKGATE_TIMER_2 || \
+                                         (clkgate) == SW_CLKGATE_TIMER_3 || \
+                                         (clkgate) == SW_CLKGATE_TIMER_4 || \
+                                         (clkgate) == SW_CLKGATE_DBGH    || \
+                                         (clkgate) == SW_CLKGATE_SDIO    || \
+                                         (clkgate) == SW_CLKGATE_MAC     || \
+                                         (clkgate) == SW_CLKGATE_CACHE   || \
+                                         (clkgate) == SW_CLKGATE_DMA     || \
+                                         (clkgate) == SW_CLKGATE_RFREG)
+
+#define IS_SPIM_INDEX(index)    ((index) == SPIM_IO_EN0 || (index) == SPIM_IO_EN1 || (index) == SPIM_IO_EN2)
+
+#define IS_I2S_INDEX(index)     ((index) == I2S_IO_EN0 || (index) == I2S_IO_EN1)
+
+#define IS_CLOCK_SRC(src)       ((src) == SYSCLK_SRC_XTAL || (src) == SYSCLK_SRC_PLL)
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif /* _SYSCON_TYPES_H_ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_adc.h

@@ -0,0 +1,298 @@
+#ifndef __LL_ADC_LN882X_H__
+#define __LL_ADC_LN882X_H__
+
+#include "types.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef     void    ADC_Instance;
+#define     ADC     ((ADC_Instance *) REG_ADC_BASE)
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_ISR
+////// Desc: ADC interrupt and status register
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Check ADC status, including:
+ * 1. awd, at bit10, Analog watchdog flag;
+ * 2. ovr, at bit9, ADC overrun;
+ * 3. eos, at bit8, End of sequence flag;
+ * 4. eoc, at bit7~bit0, End of Conversion flag.
+ *
+ * @param ADCx
+ * @return uint16_t
+ */
+uint16_t LL_ADC_IT_Status(ADC_Instance *ADCx);
+
+void LL_ADC_IT_ClrAll(ADC_Instance *ADCx);
+
+bool LL_ADC_IT_IsAnaWatchDog(ADC_Instance *ADCx);
+
+bool LL_ADC_IT_IsOverrun(ADC_Instance *ADCx);
+
+bool LL_ADC_IT_IsEndOfSeq(ADC_Instance *ADCx);
+
+uint8_t LL_ADC_IT_EndOfConv(ADC_Instance *ADCx);
+
+void LL_ADC_IT_Clr_AnaWatchDog(ADC_Instance *ADCx);
+
+void LL_ADC_IT_Clr_Overrun(ADC_Instance *ADCx);
+
+void LL_ADC_IT_Clr_EndOfSeq(ADC_Instance *ADCx);
+
+void LL_ADC_IT_Clr_EndOfConv(ADC_Instance *ADCx);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_IER
+////// Desc: ADC interrupt enable register
+///////////////////////////////////////////////////////////////////////////////
+
+uint16_t LL_ADC_IT_EnabledStatus(ADC_Instance *ADCx);
+
+void LL_ADC_IT_AnaWatchDog_Enable(ADC_Instance *ADCx, bool en);
+
+bool LL_ADC_IT_IsAnaWatchDog_Enabled(ADC_Instance *ADCx);
+
+void LL_ADC_IT_Overrun_Enable(ADC_Instance *ADCx, bool en);
+
+bool LL_ADC_IT_IsOverrun_Enabled(ADC_Instance *ADCx);
+
+void LL_ADC_IT_EndOfSeq_Enable(ADC_Instance *ADCx, bool en);
+
+bool LL_ADC_IT_IsEndOfSeq_Enabled(ADC_Instance *ADCx);
+
+void LL_ADC_IT_EndOfConv_Enable(ADC_Instance *ADCx, uint8_t eoc_bitmap);
+
+uint8_t LL_ADC_IT_EndOfConv_EnabledStatus(ADC_Instance *ADCx);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_CR
+////// Desc: ADC control register
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief ADC stop conversion command.
+ *
+ * @param ADCx
+ */
+void LL_ADC_StopConv(ADC_Instance *ADCx);
+
+bool LL_ADC_IsStopped(ADC_Instance *ADCx);
+
+void LL_ADC_StartConv(ADC_Instance *ADCx);
+
+bool LL_ADC_IsStarted(ADC_Instance *ADCx);
+
+void LL_ADC_Enable(ADC_Instance *ADCx, bool en);
+
+bool LL_ADC_IsEnabled(ADC_Instance *ADCx);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_CFGR1
+////// Desc: ADC configuration register 1
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Select one channel monitored by AWD.
+ *
+ * The channel selected must be also set into the CHSELR register.
+ * @param ADCx
+ * @param awdch valid value is 0~7, for chan0~chan7.
+ */
+void LL_ADC_AnaWatchDogChan_Set(ADC_Instance *ADCx, uint8_t awdch);
+
+uint8_t LL_ADC_AnaWatchDogChan_Get(ADC_Instance *ADCx);
+
+void LL_ADC_AnaWatchDog_Enable(ADC_Instance *ADCx, bool en);
+
+bool LL_ADC_IsAnaWatchDog_Enabled(ADC_Instance *ADCx);
+
+/**
+ * @brief Enable the watchdog on a single channel or on all channels.
+ *
+ * @param ADCx
+ * @param en 0 for all channels; 1 for single channel.
+ */
+void LL_ADC_AnaWatchDog_SingleChan_Enable(ADC_Instance *ADCx, bool en);
+
+void LL_ADC_AutoOff_Enable(ADC_Instance *ADCx, bool en);
+
+void LL_ADC_WaitConvMode_Enable(ADC_Instance *ADCx, bool en);
+
+void LL_ADC_ContinuousMode_Enable(ADC_Instance *ADCx, bool en);
+
+/**
+ * @brief ADC data alignment.
+ *
+ * @param ADCx
+ * @param en 0 -- right alignment; 1 -- left alignment.
+ */
+void LL_ADC_DataAlignLeft_Enable(ADC_Instance *ADCx, bool en);
+
+/**
+ * @brief External trigger enable and polarity selection.
+ *
+ * @param ADCx
+ * @param extcfg valid values are:
+ * 0 -- hardware trigger detection disabled (conversions can be started by software)
+ * 1 -- hardware trigger detection on the rising edge
+ * 2 -- hardware trigger detection on the falling edge
+ * 3 -- hardware trigger detection on both rising and falling edges.
+ */
+void LL_ADC_ExtTrig_Cfg(ADC_Instance *ADCx, uint8_t extcfg);
+
+/**
+ * @brief External trigger selection
+ *
+ * @param ADCx
+ * @param extsel valid values are:
+ * 0 -- TRG0
+ * 1 -- TRG1
+ * 2 -- TRG2
+ * 3 -- TRG3
+ */
+void LL_ADC_ExtTrigSelect(ADC_Instance *ADCx, uint8_t extsel);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_CFGR2
+////// Desc: ADC configuration register 2
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Analog related.
+ *
+ * @param ADCx
+ * @param en
+ */
+void LL_ADC_InputBufBypass_Enable(ADC_Instance *ADCx, bool en);
+
+/**
+ * @brief Analog related.
+ *
+ * @param ADCx
+ * @param vset
+ */
+void LL_ADC_VSET_Cfg(ADC_Instance *ADCx, uint8_t vset);
+
+/**
+ * @brief Calibration enable. When set, CH0 input is connected to VREF and CH1
+ * input is connected to VCM.
+ *
+ * @param ADCx
+ * @param en
+ */
+void LL_ADC_CalibrateEnable(ADC_Instance *ADCx, bool en);
+
+/**
+ * @brief Stable time set.
+ *
+ * @param ADCx
+ * @param stab
+ * default value is 9, means 9*16 ADC clock time.
+ */
+void LL_ADC_StableTime_Set(ADC_Instance *ADCx, uint8_t stab);
+
+/**
+ * @brief AUXADC reference voltage select.
+ *
+ * @param ADCx
+ * @param vrefsel
+ * 0 -- internal reference
+ * 1 -- external reference
+ */
+void LL_ADC_Vrefsel_Set(ADC_Instance *ADCx, uint8_t vrefsel);
+
+/**
+ * @brief AUXADC input mode control.
+ *
+ * @param ADCx
+ * @param mode_sel
+ * 0 -- differential input
+ * 1 -- single end input
+ */
+void LL_ADC_InputModeSel_Set(ADC_Instance *ADCx, uint8_t mode_sel);
+
+/**
+ * @brief Set the number of oversampling ratio.
+ *
+ * @param ADCx
+ * @param ratio
+ * 0 -- 2x
+ * 1 -- 4x
+ * 2 -- 8x
+ * 3 -- 16x
+ * 4 -- 32x
+ * others -- 64x
+ */
+void LL_ADC_OverSampleRatio_Set(ADC_Instance *ADCx, uint8_t ratio);
+
+void LL_ADC_OverSampleChan_Cfg(ADC_Instance *ADCx, uint8_t chan_map);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_TR
+////// Desc: ADC watchdog threshold register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_ADC_AnaWatchDogThreshold_Cfg(ADC_Instance *ADCx, uint16_t high, uint16_t low);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_CHSELR
+////// Desc: ADC channel selection register
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Select which channels are part of the sequence of channels to be converted.
+ *
+ * @param ADCx
+ * @param chan_map one bit for one channel, 0 -- not selected; 1 -- selected.
+ */
+void LL_ADC_SeqChanSelect_Cfg(ADC_Instance *ADCx, uint8_t chan_map);
+
+uint8_t LL_ADC_SeqChanSelect_Get(ADC_Instance *ADCx);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_CCR
+////// Desc: ADC common configuration register
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief ADC prescaler.
+ * Set and cleared by software to select the frequency of the clock to the ADC.
+ * The clock is common for all the ADCs.
+ *
+ * @param ADCx
+ * @param presc
+ * 1 -- ADC clock divided by (1+1) * 2;
+ * 2 -- ADC clock divided by (2+1) * 2;
+ * 3 -- ADC clock divided by (3+1) * 2;
+ */
+void LL_ADC_Prescaler_Cfg(ADC_Instance *ADCx, uint8_t presc);
+
+///////////////////////////////////////////////////////////////////////////////
+////// Reg:  ADC_DR0-7
+////// Desc: ADC data register
+///////////////////////////////////////////////////////////////////////////////
+
+uint16_t LL_ADC_Data0_Get(ADC_Instance *ADCx);
+
+uint16_t LL_ADC_Data1_Get(ADC_Instance *ADCx);
+
+uint16_t LL_ADC_Data2_Get(ADC_Instance *ADCx);
+
+uint16_t LL_ADC_Data3_Get(ADC_Instance *ADCx);
+
+uint16_t LL_ADC_Data4_Get(ADC_Instance *ADCx);
+
+uint16_t LL_ADC_Data5_Get(ADC_Instance *ADCx);
+
+uint16_t LL_ADC_Data6_Get(ADC_Instance *ADCx);
+
+uint16_t LL_ADC_Data7_Get(ADC_Instance *ADCx);
+
+#ifdef __cplusplus
+    }
+#endif
+#endif // !__LL_ADC_LN882X_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_aes.h

@@ -0,0 +1,113 @@
+#ifndef __LL_AES_H__
+#define __LL_AES_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif /* __cplusplus */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "ln88xx.h"
+typedef void* AesInstance;
+/*----- AES Control Codes: Crypto Mode -----*/
+
+
+/*----- AES Control Codes: Mode Parameters: Key length -----*/
+
+
+/**
+ * @brief Set Opcode：00：encrypt 01:decrypt 11:key expand
+ *
+ * @param AES BASE ADDRSS
+ * @param opcode
+ * @return  NULL
+ */
+
+void LL_AES_Set_Opcode(AesInstance AESx, uint8_t opcode);
+/**
+ * @brief Set Endian 0:little Endian 1:big Endian
+ *
+ * @param AES BASE ADDRSS
+ * @param endian
+ * @return  NULL
+ */
+void LL_AES_Set_Endian(AesInstance AESx, bool endian);
+
+/**
+ * @brief Set Key length 00:128  01:192  10:256 11:reserved
+ *
+ * @param AES BASE ADDRSS
+ * @param keylength
+ * @return  NULL
+ */
+uint32_t LL_AES_Set_Keylen(AesInstance AESx, uint8_t keylength);
+
+/**
+ * @brief Set mode  0:ECB  1:CBC
+ *
+ * @param AES BASE ADDRSS
+ * @param mode
+ * @return  NULL
+ */
+void LL_AES_Set_mode(AesInstance AESx, bool mode);
+
+/**
+ * @brief Set start  0: disable AES  1:enable AES
+ *
+ * @param AES BASE ADDRSS
+ * @param start
+ * @return  NULL
+ */
+void LL_Aes_Enable(AesInstance AESx, bool start);
+
+/**
+ * @brief Set encrypt or decrypt finish Interrupt Enable  0: disable  1:enable
+ *
+ * @param AES BASE ADDRSS
+ * @param data_int_en
+ * @return  NULL
+ */
+void LL_Aes_Enable_Interrupt(AesInstance AESx, bool data_int_en);
+
+/**
+ * @brief Set key expand Interrupt Enable  0: disable  1:enable
+ *
+ * @param AES BASE ADDRSS
+ * @param key_int_en
+ * @return  NULL
+ */
+void LL_Aes_Key_Enable_Interrupt(AesInstance AESx, bool key_int_en);
+
+/**
+ * @brief write 0 clear key expand Interrupt status   
+ *
+ * @param AES BASE ADDRSS
+ * @param key_int_en is  0
+ * @return  NULL
+ */
+void LL_Aes_Clear_Key_Interrupt(AesInstance AESx, uint8_t key_int_flag);
+
+/**
+ * @brief write 0 clear encrypt or decrypt finish Interrupt status   
+ *
+ * @param AES BASE ADDRSS
+ * @param data_int_flag 
+ * @return  NULL
+ */
+void LL_Aes_Clear_Data_Interrupt_Key(AesInstance AESx, uint8_t data_int_flag);
+
+/**
+ * @brief get Interrupt status  AES_IT :  0x40: encrypt or decrypt Interrupt， 0x20：key expand Interrupt      
+ *
+ * @param AES BASE ADDRSS
+ * @param AES_IT   
+ * @return  1: Interrupt finish  0: no interrupt
+ */
+uint32_t LL_Aes_Get_Intstatus(AesInstance AESx, uint32_t AES_IT);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __LL_AES_H__ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_cache.h

@@ -0,0 +1,147 @@
+#ifndef __LL_CACHE_H__
+#define __LL_CACHE_H__
+
+#include "types.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/****************************  Data types and Macros  ************************/
+
+#define FLASH_QUAD_READ_CMD             0x6b
+#define FLASH_STANDARD_READ_CMD         0x03
+#define CACHE_LINE_SIZE_IN_BYTES        32
+
+typedef enum
+{
+    CACHE_STATE_IDLE = 0,
+    CACHE_STATE_FILLING
+} Cache_State_t;
+
+typedef enum
+{
+    CACHE_DISABLE = 0,
+    CACHE_ENABLE
+} Cache_Enable_t;
+
+typedef enum
+{
+    CACHE_FLUSH_DISABLE = 0,
+    CACHE_FLUSH_ENABLE
+} Cache_Flush_Enable_t;
+
+typedef enum
+{
+    CACHE_FLUSH_STATE_DONE = 0,
+    CACHE_FLUSH_STATE_INPROGRESS = 1,
+} Cache_Flush_State_t;
+
+typedef enum
+{
+	FLASH_LITTLE_ENDIAN =0,//!< LITTLE_ENDIAN
+	FLASH_BIG_ENDIAN       //!< BIG_ENDIAN
+} Flash_Output_Data_Format;
+
+typedef enum
+{
+	RIGHT_JUSTIFIED = 0,
+	LEFT_JUSTIFIED
+} Cmd_Addr_Alignment;
+
+/****************************  Function Declaratioin  ************************/
+
+/**
+ * @brief Get cache state.
+ *
+ * @return uint8_t cache state: 0 -- idle; 1 -- filling.
+ */
+uint8_t LL_CACHE_StateGet(void);
+
+/**
+ * @brief enable/disable cache function.
+ *
+ * @param enable 0 -- disable; 1 -- enable
+ */
+void LL_CACHE_Enable(uint8_t enable);
+
+/**
+ * @brief Set FLASH base address.
+ *
+ * @param addr
+ */
+void LL_CACHE_FlashBaseAddrSet(uint32_t addr);
+
+/**
+ * @brief Get FLASH base address.
+ *
+ * @return uint32_t
+ */
+uint32_t LL_CACHE_FlashBaseAddrGet(void);
+
+/**
+ * @brief Set QSPI DR register address.
+ *
+ * @param addr QSPI DR register address.
+ */
+void LL_CACHE_QspiDRAddrSet(uint32_t addr);
+
+/**
+ * @brief Get QSPI DR register address.
+ *
+ * @return uint32_t
+ */
+uint32_t LL_CACHE_QspiDRAddrGet(void);
+
+/**
+ * @brief Set FLASH cmd/data format.
+ *
+ * @param tagram_emaw tag ram parameter
+ * @param tagram_ema  tag ram parameter
+ * @param flash_rd_cmd_format 8bit read command format: 0 -- {24'd0, cmd}, 1 -- {cmd, 24'd0}
+ * @param flash_rd_data_format flash output data format: 0 -- little endian. 1 -- big endian.
+ * @param flash_rd_addr_format 24bit read address format: 0 -- {8'd0, addr}, 1 -- {addr, 8'd0}
+ * @param flash_rd_cmd SPI FLASH read command.
+ */
+void LL_CACHE_FlashCmdSet(uint8_t tagram_emaw, uint8_t tagram_ema, uint8_t flash_rd_cmd_format,
+                            uint8_t flash_rd_data_format, uint8_t flash_rd_addr_format, uint8_t flash_rd_cmd);
+
+/**
+ * @brief flush address LOW range
+ *
+ * @param addrl
+ */
+void LL_CACHE_FlushAddrLow(uint32_t addrl);
+
+/**
+ * @brief flush address high range
+ *
+ * @param addrh
+ */
+void LL_CACHE_FlushAddrHigh(uint32_t addrh);
+
+/**
+ * @brief flush all data in tag ram.
+ *
+ * @param isAll
+ */
+void LL_CACHE_FlushAll(uint8_t isAll);
+
+/**
+ * @brief Start flush the range of cache data or all the cache data.
+ *
+ * @param en
+ */
+void LL_CACHE_FlushEnable(uint8_t en);
+
+/**
+ * @brief Check if the flush operation is done or not.
+ *
+ * @return uint8_t 1 -- flush in progress; 0 -- flush done.
+ */
+uint8_t LL_CACHE_IsFlushing(void);
+
+#ifdef __cplusplus
+    }
+#endif // __cplusplus
+#endif // __LL_CACHE_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_common.h

@@ -0,0 +1,50 @@
+#ifndef __LL_H__
+#define __LL_H__
+
+#include <stdint.h>
+#include "ln88xx.h"
+
+/** @brief Enable interrupts globally in the system.
+ * This macro must be used when the initialization phase is over and the interrupts
+ * can start being handled by the system.
+ */
+
+#define GLOBAL_INT_START()  __enable_irq()
+
+/** @brief Disable interrupts globally in the system.
+ * This macro must be used when the system wants to disable all the interrupt
+ * it could handle.
+ */
+
+#define GLOBAL_INT_STOP()  __disable_irq()
+
+
+/** @brief Disable interrupts globally in the system.
+ * This macro must be used in conjunction with the @ref GLOBAL_INT_RESTORE macro since this
+ * last one will close the brace that the current macro opens.  This means that both
+ * macros must be located at the same scope level.
+ */
+
+#define GLOBAL_INT_DISABLE()					\
+	do{											\
+		uint32_t __irq_mask = __get_PRIMASK();	\
+		__disable_irq();
+
+
+
+/** @brief Restore interrupts from the previous global disable.
+ * @sa GLOBAL_INT_DISABLE
+ */
+
+#define GLOBAL_INT_RESTORE()					\
+		if(__irq_mask==0)	__enable_irq();		\
+	}while(0);
+
+/** @brief Invoke the wait for interrupt procedure of the processor.
+ *
+ * @warning It is suggested that this macro is called while the interrupts are disabled
+ * to have performed the checks necessary to decide to move to sleep mode.
+ *
+ */
+#define WFI()    			__WFI()
+#endif // __LL_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_dma.h

@@ -0,0 +1,644 @@
+#ifndef __LL_DMA_H_
+#define __LL_DMA_H_
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+//////////////////////////////  Data Types and Macros  ////////////////////////
+
+/**
+ * @brief enable/disable DMA controller.
+ * 
+ */
+#define LL_DMA_CONTROLLER_DISABLE       0
+#define LL_DMA_CONTROLLER_ENABLE        1
+
+/**
+ * @brief Set the DMA channel to operate.
+ * 
+ */
+#define LL_DMA_CHANNEL_0        0x01
+#define LL_DMA_CHANNEL_1        0x02
+#define LL_DMA_CHANNEL_2        0x04
+
+#define LL_DMA_CHANNEL_NUM      3
+
+
+/**
+ * @brief enable/disable DMA interrupt.
+ * 
+ */
+#define LL_DMA_INTERRUPT_DISABLE        0
+#define LL_DMA_INTERRUPT_ENABLE         1
+
+/**
+ * @brief Handshake ploarity.
+ * 
+ */
+#define LL_DMA_HANDSHAKE_POLARITY_ACTIVE_HIGH   0
+#define LL_DMA_HANDSHAKE_POLARITY_ACTIVE_LOW    1
+
+/**
+ * @brief Source Software or Hardware Handshaking Select.
+ * 
+ */
+#define LL_DMA_HANDSHAKE_SOURCE_HARDWARE        0
+#define LL_DMA_HANDSHAKE_SOURCE_SOFTWARE        1
+
+/**
+ * @brief Channel Suspend.
+ * 0 -- Not suspended.
+ * 1 -- Suspend DMA transfer from the source.
+ */
+#define LL_DMA_CHANNEL_SUSPEND_NO               0
+#define LL_DMA_CHANNEL_SUSPEND_YES              1
+
+/**
+ * @brief Channel priority.
+ * 0 is the lowest.
+ * 
+ */
+#define LL_DMA_CHANNEL_PRIORITY_0       0
+#define LL_DMA_CHANNEL_PRIORITY_1       1
+#define LL_DMA_CHANNEL_PRIORITY_2       2
+
+// FIXME: only support 8, 16, 32bits?
+/**
+ * @brief Transfer width of src/dst.
+ * 
+ */
+#define LL_DMA_TRANSFER_WIDTH_8_BITS    0
+#define LL_DMA_TRANSFER_WIDTH_16_BITS   1
+#define LL_DMA_TRANSFER_WIDTH_32_BITS   2
+#define LL_DMA_TRANSFER_WIDTH_64_BITS   3
+#define LL_DMA_TRANSFER_WIDTH_128_BITS  4
+#define LL_DMA_TRANSFER_WIDTH_256_BITS  5
+
+/**
+ * @brief Define the address increasement of source of destination device.
+ * when working in memory to memory, source and destination address are all set to INCREMENT;
+ * when working in memory to peripheral mode, source address is set to INCREMENT and destination address is set to UNCHANGE;
+ * when working in peripheral to memory to mode, destination address is set to INCREMENT and source address is set to UNCHANGE.
+ * 
+ */
+#define LL_DMA_ADDRESS_INCREMENT        0
+#define LL_DMA_ADDRESS_DECREMENT        1
+#define LL_DMA_ADDRESS_UNCHANGE         2
+
+// FIXME: only support burst transaction length 8, 16, 32bits?
+/**
+ * @brief Set the burst transaction length. The threshold to request of dma transfer in peripheral should be less than the length set here.
+ * Normally, the threshold = msize-1. For example, msize = LL_DMA_BURST_TRANSACTION_LENGTH_4, then the threshold should set to 3.
+ * 
+ */
+#define LL_DMA_BURST_TRANSACTION_LENGTH_1       0
+#define LL_DMA_BURST_TRANSACTION_LENGTH_4       1
+#define LL_DMA_BURST_TRANSACTION_LENGTH_8       2
+#define LL_DMA_BURST_TRANSACTION_LENGTH_16      3
+#define LL_DMA_BURST_TRANSACTION_LENGTH_32      4
+#define LL_DMA_BURST_TRANSACTION_LENGTH_64      5
+#define LL_DMA_BURST_TRANSACTION_LENGTH_128     6
+#define LL_DMA_BURST_TRANSACTION_LENGTH_256     7
+
+#define LL_DMA_MAX_TRANSFER_SIZE    4095
+
+/**
+ * @brief Set the DMA Transfer type and Flow Control.
+ * 
+ */
+#define LL_DMA_TRANS_TYPE_MEMORY_TO_MEMORY      0
+#define LL_DMA_TRANS_TYPE_MEMORY_TO_PERIPHERAL  1
+#define LL_DMA_TRANS_TYPE_PERIPHERAL_TO_MEMORY  2
+
+/**
+ * @brief Set the device type.
+ * 
+ */
+#define LL_DMA_DEV_TYPE_QSPI_RX     0
+#define LL_DMA_DEV_TYPE_QSPI_TX     1
+#define LL_DMA_DEV_TYPE_UART0_TX    2
+#define LL_DMA_DEV_TYPE_UART0_RX    3
+#define LL_DMA_DEV_TYPE_UART1_TX    4
+#define LL_DMA_DEV_TYPE_UART1_RX    5
+#define LL_DMA_DEV_TYPE_SPIM_TX     6
+#define LL_DMA_DEV_TYPE_SPIM_RX     7
+#define LL_DMA_DEV_TYPE_SPIS_TX     8
+#define LL_DMA_DEV_TYPE_SPIS_RX     9
+#define LL_DMA_DEV_TYPE_I2C0_TX     10
+#define LL_DMA_DEV_TYPE_I2C0_RX     11
+#define LL_DMA_DEV_TYPE_I2C1_TX     12
+#define LL_DMA_DEV_TYPE_I2C1_RX     13
+#define LL_DMA_DEV_TYPE_AUXADC      14
+
+/**
+ * @brief define the bitmap of DMA interrupt.
+ * 
+ */
+#define LL_DMA_INT_STATUS_TFR           0x01
+#define LL_DMA_INT_STATUS_BLOCK         0x02
+#define LL_DMA_INT_STATUS_SRCTRAN       0x04
+#define LL_DMA_INT_STATUS_DSTTRAN       0x08
+#define LL_DMA_INT_STATUS_ERR           0x10
+
+
+#define LL_DMA_I2C0_RW_ADDRESS          ((void *)0x40007010)
+#define LL_DMA_SPIM_RW_ADDRESS          ((void *)0x40005060)
+#define LL_DMA_UART0_RW_ADDRESS         ((void *)0x40002000)
+
+
+//////////////////////////////   Function Declaration  ////////////////////////
+
+/**
+ * @brief Enable/disalbe DMA controller, which must be done before 
+ * any channel activity can begin.
+ * 
+ * @param enable @see LL_DMA_CONTROLLER_ENABLE.
+ */
+void LL_DMA_Enable(bool enable);
+
+/**
+ * @brief Enable/disalbe the channel.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ */
+void LL_DMA_ChanEnable(uint8_t chanIndex);
+
+/**
+ * @brief Software can poll the channel bits to determine when these channl bits
+ * are free for a new DMA transfer.
+ * 
+ * @return uint8_t ORed value from these enabled channels.
+ */
+uint8_t LL_DMA_GetBusyChannel(void);
+
+/**
+ * @brief Maximum AMBA Burst Length Set/Get.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param maxAbrst
+ */
+void LL_DMA_MaxAbrstSet(uint8_t chanIndex, uint16_t maxAbrst);
+
+uint8_t LL_DMA_MaxAbrstGet(uint8_t chanIndex);
+
+/**
+ * @brief Source Handshaking Interface Polarity Set/Get.
+ * 
+ * @param chanIndex 
+ * @param src_hs_pol 
+ */
+void LL_DMA_SrcHandshakePolSet(uint8_t chanIndex, uint8_t src_hs_pol);
+
+uint8_t LL_DMA_SrcHandshakePolGet(uint8_t chanIndex);
+
+/**
+ * @brief Destination Handshaking interface Polarity Set/Get.
+ * 
+ * @param chanIndex 
+ * @param dst_hs_pol 
+ */
+void LL_DMA_DstHandShakePolSet(uint8_t chanIndex, uint8_t dst_hs_pol);
+
+uint8_t LL_DMA_DstHandShakePolGet(uint8_t chanIndex);
+
+/**
+ * @brief Source Software or Hardware Handshaking Select.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param hs_sel_src @see LL_DMA_HANDSHAKE_SOURCE_HARDWARE
+ */
+void LL_DMA_HandshakeSelectSrcSet(uint8_t chanIndex, uint8_t hs_sel_src);
+
+uint8_t LL_DMA_HandShakeSelectSrcGet(uint8_t chanIndex);
+
+/**
+ * @brief Destination Software or Hardware Handshaking Select.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param hs_sel_dst @see LL_DMA_HANDSHAKE_SOURCE_HARDWARE
+ */
+void LL_DMA_HandshakeSelectDstSet(uint8_t chanIndex, uint8_t hs_sel_dst);
+
+uint8_t LL_DMA_HandshakeSelectDstGet(uint8_t chanIndex);
+
+/**
+ * @brief Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param ch_susp @see LL_DMA_CHANNEL_SUSPEND_NO
+ */
+void LL_DMA_ChanSuspSet(uint8_t chanIndex, uint8_t ch_susp);
+
+uint8_t LL_DMA_ChanSuspGet(uint8_t chanIndex);
+
+/**
+ * @brief Channel priority.
+ * 0 is the lowest.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param ch_prior @see LL_DMA_CHANNEL_PRIORITY_0
+ */
+void LL_DMA_ChanPrioritySet(uint8_t chanIndex, uint8_t ch_prior);
+
+uint8_t LL_DMA_ChanPriorityGet(uint8_t chanIndex);
+
+/**
+ * @brief Assigns a hradware handshaking interface to the destination of this 
+ * channel if the channel handshake select destination is LL_DMA_HANDSHAKE_SOURCE_HARDWARE; 
+ * otherwise, this field is ignored.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0 
+ * @param dest_per @see LL_DMA_DEV_TYPE_QSPI_RX
+ */
+void LL_DMA_DestPeripheralSet(uint8_t chanIndex, uint8_t dest_per);
+
+uint8_t LL_DMA_DestPeripheralGet(uint8_t chanIndex);
+
+/**
+ * @brief Assigns a hardware handshakeing interface (0-15) to the source of 
+ * this channel if the chan handshake select srouce field is LL_DMA_HANDSHAKE_SOURCE_HARDWARE; 
+ * otherwise, this field is ignored.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param src_per @see LL_DMA_DEV_TYPE_QSPI_RX
+ */
+void LL_DMA_SrcPeripheralSet(uint8_t chanIndex, uint8_t src_per);
+
+uint8_t LL_DMA_SrcPeripheralGet(uint8_t chanIndex);
+
+// FIXME: not used by user.
+/**
+ * @brief Protection Control bits used to drive the AHB HPROT[3:1] bus.
+ * 
+ * @param chanIndex 
+ * @param protctl 
+ */
+void LL_DMA_ProtectionCtrlSet(uint8_t chanIndex, uint8_t protctl);
+
+uint8_t LL_DMA_ProtectionCtrlGet(uint8_t chanIndex);
+
+/**
+ * @brief FIFO Mode Select.
+ * Determines how much space or data needs to be available in the FIFO before 
+ * a burst transaction request is serviced.
+ * 
+ * @param chanIndex 
+ * @param fifo_mode 
+ */
+void LL_DMA_FifoModeSet(uint8_t chanIndex, uint8_t fifo_mode);
+
+uint8_t LL_DMA_FifoModeGet(uint8_t chanIndex);
+
+/**
+ * @brief Flow Control Mode.
+ * Determines when source transaction requests are serviced when the Destination
+ *  Peripheral is the flow controller.
+ * 
+ * 0 -- Source transaction reqeusts are serviced when they occur.
+ * 1 -- Source transaction requests are not serviced until a destination transaction
+ * request occurs.
+ * 
+ * @param chanIndex 
+ * @param fc_mode 
+ */
+void LL_DMA_FlowControlModeSet(uint8_t chanIndex, uint8_t fc_mode);
+
+uint8_t LL_DMA_FlowControlModeGet(uint8_t chanIndex);
+
+void LL_DMA_ChanConfigureLowReg(uint8_t chanIndex, 
+                                uint16_t max_abrst, 
+                                uint8_t src_hs_pol, 
+                                uint8_t dst_hs_pol, 
+                                uint8_t hs_sel_src,
+                                uint8_t hs_sel_dst,
+                                uint8_t ch_susp,
+                                uint8_t ch_prior);
+
+void LL_DMA_ChanConfigureHighReg(uint8_t chanIndex,
+                                uint8_t dest_per,
+                                uint8_t src_per,
+                                uint8_t protctl,
+                                uint8_t fifo_mode,
+                                uint8_t fc_mode);
+
+/**
+ * @brief Set Chan CFG register.
+ * 
+ * @param chanIndex 
+ * @param max_abrst 
+ * @param src_hs_pol 
+ * @param dst_hs_pol 
+ * @param hs_sel_src 
+ * @param hs_sel_dst 
+ * @param ch_susp 
+ * @param ch_prior 
+ * @param dest_per 
+ * @param src_per 
+ * @param protctl 
+ * @param fifo_mode 
+ * @param fc_mode 
+ */
+void LL_DMA_ChanConfigure(  uint8_t chanIndex,
+                            uint16_t max_abrst,
+                            uint8_t src_hs_pol,
+                            uint8_t dst_hs_pol,
+                            uint8_t hs_sel_src,
+                            uint8_t hs_sel_dst,
+                            uint8_t ch_susp,
+                            uint8_t ch_prior,
+                            uint8_t dest_per,
+                            uint8_t src_per,
+                            uint8_t protctl,
+                            uint8_t fifo_mode,
+                            uint8_t fc_mode );
+
+/**
+ * @brief Current Source Address of DMA transfer.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param src_addr source address.
+ */
+void LL_DMA_SrcAddrSet(uint8_t chanIndex, uint32_t src_addr);
+
+uint32_t LL_DAM_SrcAddrGet(uint8_t chanIndex);
+
+/**
+ * @brief Current Destination address of DMA transfer.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param dst_addr destination address.
+ */
+void LL_DMA_DstAddrSet(uint8_t chanIndex, uint32_t dst_addr);
+
+uint32_t LL_DMA_DstAddrGet(uint8_t chanIndex);
+
+/**
+ * @brief Transfer Type and Flow Contrl.
+ * The following transfer types are supported.
+ * - Memory to Memory
+ * - Memory to Peripheral
+ * - Peripheral to Memory
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param tt_fc @see LL_DMA_TRANS_TYPE_MEMORY_TO_MEMORY
+ */
+void LL_DMA_TranTypeFlowCtrlSet(uint8_t chanIndex, uint8_t tt_fc);
+
+uint8_t LL_DMA_TranTypeFlowCtrlGet(uint8_t chanIndex);
+
+/**
+ * @brief Source Burst Transaction Length.
+ * Number of data items, each of width src_tr_width, to be read from the source
+ * every time a source burst transaction request is made from either the corresponding
+ * hardware or software handshaking interface.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param src_msize @see LL_DMA_BURST_TRANSACTION_LENGTH_8
+ */
+void LL_DMA_SrcMsizeSet(uint8_t chanIndex, uint8_t src_msize);
+
+uint8_t LL_DMA_SrcMsizeGet(uint8_t chanIndex);
+
+/**
+ * @brief Destination Burst Transaction Length.
+ * Number of data items, each of width dst_tr_width, to be written to the destination
+ * every time a destination burst transaction request is made from either the 
+ * corresponding hardware or software handshaking interface.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param dest_msize @see LL_DMA_BURST_TRANSACTION_LENGTH_8
+ */
+void LL_DMA_DestMsizeSet(uint8_t chanIndex, uint8_t dest_msize);
+
+uint8_t LL_DMA_DestMsizeGet(uint8_t chanIndex);
+
+/**
+ * @brief Source Address Increment.
+ * Indicates whether to increment or decrement the source address on every source transfer.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param sinc @see LL_DMA_ADDRESS_INCREMENT
+ */
+void LL_DMA_SrcAddrIncSet(uint8_t chanIndex, uint8_t sinc);
+
+uint8_t LL_DMA_SrcAddrIncGet(uint8_t chanIndex);
+
+/**
+ * @brief Destination Address Increment.
+ * Indicates whether to increment or decrement the destination address on every
+ * destination transfer.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param dinc @see LL_DMA_ADDRESS_INCREMENT
+ */
+void LL_DMA_DestAddrIncSet(uint8_t chanIndex, uint8_t dinc);
+
+uint8_t LL_DMA_DestAddrIncGet(uint8_t chanIndex);
+
+/**
+ * @brief Source Transfer width.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param src_tr_width @see LL_DMA_TRANSFER_WIDTH_8_BITS
+ */
+void LL_DMA_SrcTrWidthSet(uint8_t chanIndex, uint8_t src_tr_width);
+
+uint8_t LL_DMA_SrcTrWidthGet(uint8_t chanIndex);
+
+/**
+ * @brief Destination Transfer width.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param dst_tr_width @see LL_DMA_TRANSFER_WIDTH_8_BITS
+ */
+void LL_DMA_DestTrWidthSet(uint8_t chanIndex, uint8_t dst_tr_width);
+
+uint8_t LL_DMA_DestTrWidthGet(uint8_t chanIndex);
+
+/**
+ * @brief Interrupt Enable.
+ * If set, then all interrupt-generating sources are enabled.
+ * Functions as a global mask bit for all interrupts for the channel;
+ * raw interrupt registers still assert if channel int_en is 0.
+ * 
+ * @param chanIndex 
+ * @param int_en 
+ */
+void LL_DMA_ChanIntEnSet(uint8_t chanIndex, uint8_t int_en);
+
+uint8_t LL_DMA_ChanIntEnGet(uint8_t chanIndex);
+
+/**
+ * @brief Done bit.
+ * If status write-back is enabled, the upper word of the control register, CTLX[63:32],
+ * is written to the control register location of the linked List Item ( LLI ) in 
+ * system memory at the end of the block transfer with the done bit set.
+ * 
+ * Software can poll the LLI CTLX.DONE bit to see when a block transfer is complete.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param done 
+ */
+void LL_DMA_ChanDoneSet(uint8_t chanIndex, uint8_t done);
+
+uint8_t LL_DMA_ChanDoneGet(uint8_t chanIndex);
+
+/**
+ * @brief Block Transfer Size.
+ * The number programmed into BLOCK_TS indicates the total number of single transactions
+ * to perform for every block transfer; a single transaction is mapped to a single AMBA beat.
+ * 
+ * @param chanIndex @see LL_DMA_CHANNEL_0
+ * @param block_ts 
+ */
+void LL_DMA_ChanBlockTranSizeSet(uint8_t chanIndex, uint32_t block_ts);
+
+uint32_t LL_DMA_ChanBlockTranSizeGet(uint8_t chanIndex);
+
+void LL_DMA_ChanCtrlLowReg(uint8_t chanIndex,
+                            uint8_t tt_fc,
+                            uint8_t src_msize,
+                            uint8_t dest_msize,
+                            uint8_t sinc,
+                            uint8_t dinc,
+                            uint8_t src_tr_width,
+                            uint8_t dst_tr_width,
+                            uint8_t int_en);
+
+void LL_DMA_ChanCtrlHighReg(uint8_t chanIndex,
+                            uint8_t done,
+                            uint16_t block_ts);
+
+/**
+ * @brief 
+ * 
+ * @param chanIndex 
+ * @param tt_fc 
+ * @param src_msize 
+ * @param dest_msize 
+ * @param sinc 
+ * @param dinc 
+ * @param src_tr_width 
+ * @param dst_tr_width 
+ * @param int_en 
+ * @param done 
+ * @param block_ts 
+ */
+void LL_DMA_ChanCtrl(uint8_t chanIndex, 
+                    uint8_t tt_fc,
+                    uint8_t src_msize,
+                    uint8_t dest_msize,
+                    uint8_t sinc,
+                    uint8_t dinc,
+                    uint8_t src_tr_width,
+                    uint8_t dst_tr_width,
+                    uint8_t int_en,
+                    uint8_t done,
+                    uint16_t block_ts);
+
+/**
+ * @brief Interrupt events are stored in these Raw Interrupt Status registers before masking.
+ * Each Raw Interrupt Status register has a bit allocated per channel; for example,
+ * RawTfr[2] is the Channel 2 raw transfer complete interrupt.
+ * 
+ * @return uint8_t 
+ */
+uint8_t LL_DMA_RawStatusBlock(void);
+
+uint8_t LL_DMA_RawStatusErr(void);
+
+uint8_t LL_DMA_RawStatusTfr(void);
+
+uint8_t LL_DMA_RawStatusDstTran(void);
+
+uint8_t LL_DMA_RawStatusSrcTran(void);
+
+/**
+ * @brief All interrupt events from all channles are stored in these Interrupt 
+ * Status registers after masking.
+ * Each Interrupt Status register has a bit allocated per channel: for example, 
+ * StatusTfr[2] is the Channel 2 status transfer complete interrupt.
+ * 
+ * @return uint8_t 
+ */
+uint8_t LL_DMA_StatusBlock(void);
+
+uint8_t LL_DMA_StatusErr(void);
+
+uint8_t LL_DMA_StatusTfr(void);
+
+uint8_t LL_DMA_StatusDstTran(void);
+
+uint8_t LL_DMA_StatusSrcTran(void);
+
+/**
+ * @brief The contents of the Raw Status registers are masked with the contents of the Mask registers.
+ * Each Interrupt Mask register has a bit allocated per channel: for example, MaksTfr[2] is the mask
+ * bit for the Channel 2 transfer complete interrupt.
+ * @param chanIndex 
+ */
+void LL_DMA_UnMaskBlock(uint8_t chanIndex);
+
+void LL_DMA_UnMaskErr(uint8_t chanIndex);
+
+void LL_DMA_UnMaskTfr(uint8_t chanIndex);
+
+void LL_DMA_UnMaskDstTran(uint8_t chanIndex);
+
+void LL_DMA_UnMaskSrcTran(uint8_t chanIndex);
+
+/**
+ * @brief Each Interrupt Clear register has a bit allocated per channel; for example, ClearTfr[2] 
+ * is the clear bit for the Channel 2 transfer complete interrupt.
+ * 
+ * @param chanIndex 
+ */
+void LL_DMA_ClearBlock(uint8_t chanIndex);
+
+void LL_DMA_ClearErr(uint8_t chanIndex);
+
+void LL_DMA_ClearTfr(uint8_t chanIndex);
+
+void LL_DMA_ClearDstTran(uint8_t chanIndex);
+
+void LL_DMA_ClearSrcTran(uint8_t chanIndex);
+
+/**
+ * @brief Combined Interrupt Status Register.
+ * 
+ * @return uint8_t The contents of each of teh five status registers is ORed to produce a single bit for
+ * each interrupt type in the Combined Status register.
+ */
+uint8_t LL_DMA_IntStatus(void);
+
+void LL_DMA_SWSrcTranRequest(uint8_t chanIndex);
+
+uint8_t LL_DMA_SWSrcTranRead(void);
+
+void LL_DMA_SWDstTranRequest(uint8_t chanIndex);
+
+uint8_t LL_DMA_SWDstTranRead(void);
+
+void LL_DMA_SingleSrcTranRequest(uint8_t chanIndex);
+
+uint8_t LL_DMA_SingleSrcTranRead(void);
+
+void LL_DMA_SingleDstTranRequest(uint8_t chanIndex);
+
+uint8_t LL_DMA_SingleDstTranRead(void);
+
+void LL_DMA_LastSrcTranRequest(uint8_t chanIndex);
+
+uint8_t LL_DMA_LastSrcTranRead(void);
+
+void LL_DMA_LastDstTranRequest(uint8_t chanIndex);
+
+uint8_t LL_DMA_LastDstTranRead(void);
+
+#ifdef __cplusplus
+    }
+#endif // __cplusplus
+
+#endif // __LL_DMA_H_

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_efuse.h

@@ -0,0 +1,36 @@
+#ifndef __LL_EFUSE_H__
+#define __LL_EFUSE_H__
+
+typedef     void        EFUSE_Instance;
+#define     EFUSE       ((EFUSE_Instance *) REG_EFUSE_BASE)
+
+void LL_EFUSE_WriteEnable(EFUSE_Instance * EFUSEx);
+
+/**
+ * @brief Write R0~R7.
+ *
+ * @param EFUSEx
+ * @param regIndex index, [0,7].
+ * @param regValue
+ */
+void LL_EFUSE_WriteShadowReg(EFUSE_Instance *EFUSEx, uint8_t regIndex, uint32_t regValue);
+
+/**
+ * @brief Read from shawdow register R0~R7.
+ *
+ * @param EFUSEx
+ * @param regIndex 0~7 is valid.
+ * @return uint32_t
+ */
+uint32_t LL_EFUSE_ReadShadowReg(EFUSE_Instance * EFUSEx, uint8_t regIndex);
+
+/**
+ * @brief The effective value is stored in correct registers.
+ *
+ * @param EFUSEx
+ * @param regIndex 0~7 is valid.
+ * @return uint32_t
+ */
+uint32_t LL_EFUSE_ReadCorrectReg(EFUSE_Instance * EFUSEx, uint8_t regIndex);
+
+#endif // !__LL_EFUSE_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_gpio.h

@@ -0,0 +1,244 @@
+#ifndef __LL_GPIO_H_
+#define __LL_GPIO_H_
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+#include "hal/syscon_types.h"
+
+//////////////////////////////  Data type and Macros  /////////////////////////
+
+
+/**
+ * @brief enum of GPIO Direction.
+ */
+typedef enum
+{
+    GPIO_INPUT  = 0,
+    GPIO_OUTPUT = 1,
+} GPIO_Direction;
+
+
+/**
+ * @brief enum of Trigger type
+ */
+typedef enum
+{
+	GPIO_TRIG_LOW_LEVEL    = 0,
+	GPIO_TRIG_HIGH_LEVEL   = 1,
+	GPIO_TRIG_FALLING_EDGE = 2,
+	GPIO_TRIG_RISING_EDGE  = 3,
+} GPIO_TrigType;
+
+
+/**
+ * @brief enum of gpio debounce. GPIO Debounce is only useful when gpio direction is input.
+ */
+typedef enum
+{
+    GPIO_DEBOUNCE_NO  = 0,
+    GPIO_DEBOUNCE_YES = 1,
+} GPIO_Debounce;
+
+
+/**
+ * @brief enum of gpio value.
+ */
+typedef enum
+{
+    GPIO_VALUE_LOW     = 0,
+    GPIO_VALUE_HIGH    = 1,
+    GPIO_VALUE_DEFAULT = GPIO_VALUE_LOW,
+} GPIO_Value;
+
+
+/**
+ * @brief enum of gpio irqlvl. Set whether gpio is level sensitive or edge sensitive.
+ */
+typedef enum
+{
+    GPIO_IRQLVL_LEVEL = 0,
+    GPIO_IRQLVL_EDGE  = 1,
+} GPIO_IrqLvl;
+
+
+/**
+ * @brief enum of gpio polarity.
+ */
+typedef enum
+{
+    GPIO_LOW_FALLING = 0,
+    GPIO_HIGH_RISING = 1,
+} GPIO_Polarity;
+
+
+//////////////////////////////  Function Declaration  /////////////////////////
+/**
+ * @brief Controls the type of interrupt that can occur on GPIO ranging from GPIOA_0 to GPIOA_20
+ * @param  num: the GPIO_Num to define which GPIO to operate. num can only choose from GPIOA_0 to GPIOA_20
+ * @param  irqLvl: it configures the interrupt type to be level-sensitive or edge-sensitive.
+ * @return This function has no return.
+ */
+void LL_GPIO_IrqLevelSet(GPIO_Num num, GPIO_IrqLvl irqLvl);
+
+/**
+ * @brief Controls the polarity of edge or level sensitivity that can occur on GPIO ranging from GPIOA_0 to GPIOA_20
+ * @param  num: the GPIO_Num to define which GPIO to operate. num can only choose from GPIOA_0 to GPIOA_20
+ * @param  ply: choose from enum GPIO_Polarity to configures the interrupt type to falling-edge or rising-edge.
+ * @return This function has no return.
+ */
+void LL_GPIO_PolaritySet(GPIO_Num num, GPIO_Polarity ply);
+
+/**
+ * @brief Set the GPIO to trigger a interrupt at both edge, rising and falling.
+ * @param  num: the GPIO_Num to define which GPIO to operate.
+ * @param  enable: enable or disable whether a gpio trigger an interrupt at both edge.
+ * @return This function has no return.
+ */
+void LL_GPIO_TrigBothEdge(GPIO_Num num, uint8_t enable);
+
+/**
+ * @brief Set GPIO Direction, Input or Output
+ * @param  num: the GPIO_Num to define which GPIO to operate.
+ * @param  dir: choose from GPIO_Direction, GPIO_INPUT or GPIO_OUTPUT
+ * @return This function has no return.
+ */
+void LL_GPIO_SetDir(GPIO_Num num, GPIO_Direction dir);
+
+/**
+ * @brief Get GPIO Direction, Input or Output
+ * @param  num: the GPIO_Num to define which GPIO to operate.
+ * @return return the direction of the specific gpio
+ */
+GPIO_Direction LL_GPIO_GetDir(GPIO_Num num);
+
+/**
+ * @brief Get signals value on the External Port A.
+ * 
+ * @return uint32_t Only lowest 21 bits are valid, one bit for one gpio.
+ */
+uint32_t LL_GPIO_ExtPortAValue(void);
+
+/**
+ * @brief Get signals value on the External Port B.
+ * 
+ * @return uint32_t Only lowest 14 bits are valid, one bit for one gpio.
+ */
+uint32_t LL_GPIO_ExtPortBValue(void);
+
+/**
+ * @brief Values written to this register are output on the I/O signals for
+ * Port A if the corresponding data direction bits for Port A are set
+ * to Output mode and the corresponding control bit for Port A is
+ * set to Software mode. The value read back is equal to the last
+ * value written to this register.
+ * 
+ * @param value 
+ */
+void LL_GPIO_PORTADataRegWrite(uint32_t value);
+
+/**
+ * @brief Values written to this register are output on the I/O signals for
+ * Port A if the corresponding data direction bits for Port A are set
+ * to Output mode and the corresponding control bit for Port A is
+ * set to Software mode. The value read back is equal to the last
+ * value written to this register.
+ * 
+ * @return uint32_t 
+ */
+uint32_t LL_GPIO_PORTADataRegRead(void);
+
+/**
+ * @brief Values written to this register are output on the I/O signals for
+ * Port B if the corresponding data direction bits for Port B are set
+ * to Output mode and the corresponding control bit for Port B is
+ * set to Software mode. The value read back is equal to the last
+ * value written to this register.
+ * 
+ * @param value 
+ */
+void LL_GPIO_PORTBDataRegWrite(uint32_t value);
+
+uint32_t LL_GPIO_PORTBDataRegRead(void);
+
+/**
+ * @brief When GPIO direction is input, read current gpio level.
+ * @param  num: the GPIO_Num to define which GPIO to operate.
+ * @return return the result of current gpio level.
+ */
+GPIO_Value LL_GPIO_ReadPin(GPIO_Num num);
+
+/**
+ * @brief When GPIO direction is output, write value to set gpio level.
+ * @param  num: the GPIO_Num to define which GPIO to operate.
+ * @param  value: value can be choose from GPIO_Value, GPIO_VALUE_LOW or GPIO_VALUE_HIGH
+ * @return This function has no return.
+ */
+void LL_GPIO_WritePin(GPIO_Num num, GPIO_Value value);
+
+/**
+ * @brief Toggle a gpio pin
+ * @param  num: the GPIO_Num to define which GPIO to operate.
+ * @return This function has no return.
+ */
+void LL_GPIO_TogglePin(GPIO_Num num);
+
+/**
+ * @brief Controls whether en external signal that is the source of an interrupt needs to be debounced to remove any spurious glitches.
+ * 
+ * @param num  The GPIO_Num to define which GPIO to operate.
+ * @param debounce enable/disable debounce.
+ */
+void LL_GPIO_SetDebounce(GPIO_Num num, GPIO_Debounce debounce);
+
+/**
+ * @brief Enable the interrupt of specific GPIO
+ * @param  num: the GPIO_Num to define which GPIO to operate. n can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void LL_GPIO_IntEnable(GPIO_Num num);
+
+/**
+ * @brief Disable the interrupt of specific GPIO
+ * @param  num: the GPIO_Num to define which GPIO to operate. num can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void LL_GPIO_IntDisable(GPIO_Num num);
+
+/**
+ * @brief Mask the interrupt of specific GPIO, when the interrupt is masked, no interrupt will trigger to CPU
+ * @param  num: the GPIO_Num to define which GPIO to operate. num can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void LL_GPIO_MaskIrq(GPIO_Num num);
+
+/**
+ * @brief Unmask the interrupt of specific GPIO, when the interrupt is unmasked, the interrupt will trigger to CPU
+ * @param  num: the GPIO_Num to define which GPIO to operate. num can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void LL_GPIO_UnmaskIrq(GPIO_Num num);
+
+/**
+ * @brief Interrupt status of PORT A. 
+ * Only 21 bits are valid, one bit for one GPIO.
+ * 
+ * @return uint32_t 
+ */
+uint32_t LL_GPIO_IntStatus(void);
+
+/**
+ * @brief Clear the interrupt of specific gpio
+ * @param  num: the GPIO_Num to define which GPIO to operate. num can only choose from GPIOA_0 to GPIOA_20
+ * @return This function has no return.
+ */
+void LL_GPIO_IrqClear(GPIO_Num num);
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __LL_GPIO_H_

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_i2c.h

@@ -0,0 +1,344 @@
+#ifndef __LL_I2C_H__
+#define __LL_I2C_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+#include "ln88xx.h"
+
+////////////////////////////////  Datatype and Macros  ////////////////////////
+typedef void I2CInstance;
+#define I2C0   ((I2CInstance *) REG_I2C0_BASE)
+#define I2C1   ((I2CInstance *) REG_I2C1_BASE)
+
+
+///////////////////////////////  Functioin Declarations ///////////////////////
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CON, I2C Control Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_SlaveDisable_Set(I2CInstance * i2c_instance, uint8_t flag);
+
+void LL_I2C_MasterMode_Set(I2CInstance * i2c_instance, uint8_t flag);
+
+uint8_t LL_I2C_MasterMode_Get(I2CInstance * i2c_instance);
+
+void LL_I2C_RestartMode_Enable(I2CInstance * i2c_instance, uint8_t en);
+
+void LL_I2C_Set7_10Addressing_Master(I2CInstance * i2c_instance, uint8_t address);
+
+void LL_I2C_Set7_10Addressing_Slave(I2CInstance * i2c_instance, uint8_t address);
+
+void LL_I2C_SetSpeed(I2CInstance * i2c_instance, uint8_t speed_mode);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_TAR, I2C Target Address Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_SetSpecialBit(I2CInstance * i2c_instance, uint8_t special);
+
+void LL_I2C_GeneralCall_Or_Start(I2CInstance *i2c_instance, uint8_t start);
+
+void LL_I2C_TarAddr_Set(I2CInstance * i2c_instance, uint16_t addr);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_SAR, I2C Slave Address Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_SlaveAddr_Set(I2CInstance * i2c_instance, uint16_t addr);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_HS_MADDR, I2C High Speed Master Mode Code Address Reg
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_HighSpeed_MasterAddr_Set(I2CInstance * i2c_instance, uint8_t maddr);
+
+uint8_t LL_I2C_HighSpeed_MasterCode_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_DATA_CMD, I2C Rx/Tx Data Buffer and Command Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_Data_Get(I2CInstance * i2c_instance);
+
+void LL_I2C_Data_Cmd_Pack(I2CInstance * i2c_instance, uint8_t restart, uint8_t stop, uint8_t cmd, uint8_t dat);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_SS_SCL_HCNT, Standard Speed I2C Clock SCL High Count
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_StandardSpeed_SCL_HighCount_Set(I2CInstance * i2c_instance, uint16_t hcnt);
+
+uint16_t LL_I2C_StandardSpeed_SCL_HighCount_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_SS_SCL_LCNT, Standard Speed I2C Clock SCL Low Count
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_StandardSpeed_SCL_LowCount_Set(I2CInstance * i2c_instance, uint16_t lcnt);
+
+uint16_t LL_I2C_StandardSpeed_SCL_LowCount_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_FS_SCL_HCNT, Fast Mode or Fast Mode Plus I2C Clock
+////                                 SCL High Count Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_FastSpeed_SCL_HighCount_Set(I2CInstance * i2c_instance, uint16_t hcnt);
+
+uint16_t LL_I2C_FastSpeed_SCL_HighCount_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_FS_SCL_LCNT, Fast Mode or Fast Mode Plus I2C Clock
+////                                 SCL Low Count Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_FastSpeed_SCL_LowCount_Set(I2CInstance * i2c_instance, uint16_t lcnt);
+
+uint16_t LL_I2C_FastSpeed_SCL_LowCount_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_HS_SCL_HCNT, High Speed I2C Clock SCL High Count Reg
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_HighSpeed_SCL_HighCount_Set(I2CInstance * i2c_instance, uint16_t hcnt);
+
+uint16_t LL_I2C_HighSpeed_SCL_HighCount_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_HS_SCL_LCNT, High Speed I2C Clock SCL Low Count Reg
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_HighSpeed_SCL_LowCount_Set(I2CInstance * i2c_instance, uint16_t lcnt);
+
+uint16_t LL_I2C_HighSpeed_SCL_LowCount_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_INTR_STAT, I2C Interrupt Status Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint16_t LL_I2C_IntStatus(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_INTR_MASK, I2C Interrupt Mask Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_IntMask_Set(I2CInstance * i2c_instance, uint16_t mask);
+
+uint16_t LL_I2C_IntMask_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_RAW_INTR_STAT, I2C Raw Interrupt Status Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint16_t LL_I2C_RawIntStatus(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_RX_TL, I2C Receive FIFO Threshold Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_Rx_Threshold_Set(I2CInstance * i2c_instance, uint8_t rx_tl);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_TX_TL, I2C Transmit FIFO Threshold Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_Tx_Threshold_Set(I2CInstance * i2c_instance, uint8_t tx_tl);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_INTR, Clear Combined and Individual Interrupt Reg
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_All(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_RX_UNDER, Clear RX_UNDER Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_RxUnder(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_RX_OVER, Clear RX_OVER Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_RxOver(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_TX_OVER, Clear TX_OVER Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_TxOver(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_RD_REQ, Clear RD_REQ Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_RdReq(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_TX_ABRT, CLear TX_ABRT Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_TxAbort(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_RX_DONE, Clear RX_DONE Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_RxDone(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_ACTIVITY, Clear ACTIVITY Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_Activity(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_STOP_DET, Clear STOP_DET Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_StopDet(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_START_DET, Clear START_DET Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_StartDet(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_GEN_CALL, Clear GEN_CALL Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_GenCall(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_ENABLE, I2C Enable Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_Enable(I2CInstance * i2c_instance, uint8_t en);
+
+void LL_I2C_Abort(I2CInstance * i2c_instance, uint8_t en);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_STATUS, I2C Status Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint32_t LL_I2C_IC_Status(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_TXFLR, I2C Transmit FIFO Level Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_Tx_FIFO_Level(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_RXFLR, I2C Receive FIFO Level Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_Rx_FIFO_Level(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_SDA_HOLD, I2C SDA Hold Time Length Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_SDA_RxHold_Set(I2CInstance * i2c_instance, uint8_t rx_hold);
+
+uint8_t LL_I2C_SDA_RxHold_Get(I2CInstance * i2c_instance);
+
+void LL_I2C_SDA_TxHold_Set(I2CInstance * i2c_instance, uint16_t tx_hold);
+
+uint16_t LL_I2C_Tx_Threshold_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_TX_ABRT_SOURCE, I2C Transmit Abort Source Register
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Get Tx abort source, each bit for one source, like abrt_device_slvaddr_noack.
+ *
+ * @param i2c_instance
+ * @return uint32_t
+ */
+uint32_t LL_I2C_TxAbortSource_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_SLV_DATA_NACK_ONLY, Generate Slave Data NACK Register
+///////////////////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_DMA_CR, DMA Control Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_DMACtrl(I2CInstance * i2c_instance, uint8_t tx_dma_en, uint8_t rx_dma_en);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_DMA_TDLR, DMA Transmit Data Level Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_DMA_DataLevel_Set(I2CInstance * i2c_instance, uint8_t tx_data_level, uint8_t rx_data_level);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_DMA_RDLR, I2C Receive Data Level Register
+///////////////////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_SDA_SETUP, I2C SDA Setup Register
+///////////////////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_ACK_GENERAL_CALL, I2C ACK General Call Register
+///////////////////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_ENABLE_STATUS, I2C Enable Status Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IC_Enable_Status(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_FS_SPKLEN, I2C SS and FS Spike Suppression Limit Reg
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_FastSpeed_SPKLEN_Set(I2CInstance * i2c_instance, uint8_t spklen);
+
+uint8_t LL_I2C_FastSpeed_SPKLEN_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_HS_SPKLEN, I2C HS Spike Suppression Limit Register
+///////////////////////////////////////////////////////////////////////////////
+
+void LL_I2C_HighSpeed_SPKLEN_Set(I2CInstance * i2c_instance, uint8_t spklen);
+
+uint8_t LL_I2C_HighSpeed_SPKLEN_Get(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_CLR_RESTART_DET, Clear RESTART_DET Interrupt Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint8_t LL_I2C_IntClr_RestartDet(I2CInstance * i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_COMP_PARAM_1, Component Parameter Register 1
+///////////////////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_COMP_VERSION, I2C Component Version Register
+///////////////////////////////////////////////////////////////////////////////
+
+uint32_t LL_I2C_CompVersion(I2CInstance *i2c_instance);
+
+///////////////////////////////////////////////////////////////////////////////
+////  Register Name: IC_COMP_TYPE, I2C Component Type Register
+///////////////////////////////////////////////////////////////////////////////
+
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_I2C_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_i2s.h

@@ -0,0 +1,198 @@
+#ifndef __LL_I2S_H__
+#define __LL_I2S_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/////////////////////////////  Data types and Macros  /////////////////////////
+
+#include "types.h"
+/**
+ * LN882x only support 1 channel i2s,
+ * so I2S_CHAN_1 is not support in fact.
+ **/
+typedef enum
+{
+    I2S_CHAN_0 = 0,
+    I2S_CHAN_1,
+} I2S_Chan_Enum_t;
+
+
+/////////////////////////////  Function Declarations  /////////////////////////
+
+/**
+ * @brief A disable on this bit overrides any other block or channel enables
+ * and flushes all FIFOs.
+ *
+ * @param en 1 -- enable; 0 -- disable.
+ */
+void LL_I2S_Enable(uint8_t en);
+
+/**
+ * @brief A disable on this bit overrides any individual receive channel enables.
+ *
+ * @param en 1 -- enable receiver; 0 -- disable.
+ */
+void LL_I2S_RxBlock_Enable(uint8_t en);
+
+/**
+ * @brief A disable on this bit overrides any individual transmit channel enables.
+ *
+ * @param en 1 -- enable transmitter; 0 -- disable.
+ */
+void LL_I2S_TxBlock_Enable(uint8_t en);
+
+/**
+ * @brief Put a data in the Left Receive Buffer Register.
+ *
+ * @param chan
+ * @param data
+ */
+void LL_I2S_LeftRxBuf_Set(I2S_Chan_Enum_t chan, uint32_t data);
+
+/**
+ * @brief Get a data from the Left Receive Buffer Register.
+ *
+ * @param chan
+ * @return uint32_t
+ */
+uint32_t LL_I2S_LeftRxBuf_Get(I2S_Chan_Enum_t chan);
+
+/**
+ * @brief Put a data in the Right Receive Buffer Register.
+ *
+ * @param chan
+ * @param data
+ */
+void LL_I2S_RightRxBuf_Set(I2S_Chan_Enum_t chan, uint32_t data);
+
+/**
+ * @brief Get a data from the Rigt Receive Buffer Register.
+ *
+ * @param chan
+ * @return uint32_t
+ */
+uint32_t LL_I2S_RightRxBuf_Get(I2S_Chan_Enum_t chan);
+
+/**
+ * @brief To enable/disable a receive channel, independently of all other channels.
+ *
+ * @param chan
+ * @param en 1 -- enable; 0 -- disable.
+ */
+void LL_I2S_Rx_Enable(I2S_Chan_Enum_t chan, uint8_t en);
+
+/**
+ * @brief Enable/disable a transmit channel, independently of all other channels.
+ * A global disable of IER[0] or Transmitter block ITER[0] overrides this value.
+ *
+ * @param chan
+ * @param en 1 -- enable; 0 -- disable.
+ */
+void LL_I2S_TX_Enable(I2S_Chan_Enum_t chan, uint8_t en);
+
+/**
+ * @brief To program the desired data resolution of the receiver and enables
+ * the LSB of the incoming left (or right) word to be placed in the LSB of the
+ * LRBRx (or RRBRx) register.
+ *
+ * @param chan
+ * @param resolution
+ */
+void LL_I2S_RxResolution_Set(I2S_Chan_Enum_t chan, uint8_t resolution);
+
+void LL_I2S_RxResolution_Get(I2S_Chan_Enum_t chan, uint8_t *resolution);
+
+void LL_I2S_TxResolution_Set(I2S_Chan_Enum_t chan, uint8_t resolution);
+
+void LL_I2S_TxResolution_Get(I2S_Chan_Enum_t chan, uint8_t *resolution);
+
+/**
+ * @brief Interrupt status of one channel.
+ *
+ * @param chan
+ * @return uint8_t
+ */
+uint8_t LL_I2S_IntStatus(I2S_Chan_Enum_t chan);
+
+void LL_I2S_IntMask_Set(I2S_Chan_Enum_t chan, uint8_t mask_map);
+uint8_t LL_I2S_IntMask_Get(I2S_Chan_Enum_t chan);
+
+uint8_t LL_I2S_IntClr_RxOverrun(I2S_Chan_Enum_t chan);
+
+uint8_t LL_I2S_IntClr_TxOverrun(I2S_Chan_Enum_t chan);
+
+/**
+ * @brief To set the trigger level in the RX FIFO at which the Received Data
+ * Available interrupt is generated.
+ *
+ * @param chan
+ * @param level
+ */
+void LL_I2S_RxFIFO_TrigLvl_Set(I2S_Chan_Enum_t chan, uint8_t level);
+
+/**
+ * @brief To set the trigger level in the TX FIFO at which the Empty Threshold
+ * Reached Interrupt is generated.
+ *
+ * @param chan
+ * @param level
+ */
+void LL_I2S_TxFIFO_TrigLvl_Set(I2S_Chan_Enum_t chan, uint8_t level);
+
+/**
+ * @brief Receive Channel FIFO Reset.
+ * Rx channel or block must be disabled prior to writing to this bit.
+ *
+ * @param chan
+ */
+void LL_I2S_RxFIFO_Flush(I2S_Chan_Enum_t chan);
+
+/**
+ * @brief Transmit Channel FIFO Reset.
+ * Tx channel or block must be disabled prior to writing to this bit.
+ *
+ * @param chan
+ */
+void LL_I2S_TxFIFO_Flush(I2S_Chan_Enum_t chan);
+
+/**
+ * @brief If you enabled chan-0 and chan-1, order of returned read data:
+ * 1. ch0 - left data
+ * 2. ch0 - right data
+ * 3. ch1 - left data
+ * 4. ch1 - right data
+ *
+ * 5. ch0 - left data
+ * 6. ch0 - right data
+ * 7. ch1 - left data
+ * 8. ch1 - right data
+ *
+ * @return uint32_t
+ */
+uint32_t LL_I2S_RxDMA_Get(void);
+
+/**
+ * @brief Reset Receiver Block DMA.
+ *
+ */
+void LL_I2S_Reset_RxDMA(void);
+
+/**
+ * @brief To cycle repeatedly through the enabled Transmit channels (from lowest
+ * numbered to highest) to allow writing stereo data pairs.
+ *
+ * @param data
+ */
+void LL_I2S_TxDMA_Set(uint32_t data);
+
+/**
+ * @brief Reset Transmitter Block DMA.
+ *
+ */
+void LL_I2S_Reset_TxDMA(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_I2S_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_pwm.h

@@ -0,0 +1,77 @@
+#ifndef __LL_PWM_H__
+#define __LL_PWM_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/**
+ * @brief Start PWM of one channel.
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ */
+void LL_PWM_Start(uint8_t pwm_chan_x);
+
+/**
+ * @brief Stop PWM of one channel
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ */
+void LL_PWM_Stop(uint8_t pwm_chan_x);
+
+/**
+ * @brief PWM output invert, active high.
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ * @param en
+ */
+void LL_PWM_Invert_Set(uint8_t pwm_chan_x, uint8_t en);
+
+/**
+ * @brief PWM count mode settting.
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ * @param mode valid value is 0~3.
+ * 0: count up, 0-->load, 0-->load, 0-->load
+ * 1: count down, load-->0, load-->0, load-->0
+ * 2/3: count up/down, 0-->load-->0-->load...
+ */
+void LL_PWM_CntMode_Set(uint8_t pwm_chan_x, uint8_t mode);
+
+/**
+ * @brief Set clock division of one channel.
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ * @param clk_div clock divide by 0:1, 1:2, ..., 63:64.
+ */
+void LL_PWM_Div_Set(uint8_t pwm_chan_x, uint8_t clk_div);
+
+uint8_t LL_PWM_Div_Get(uint8_t pwm_chan_x);
+
+/**
+ * @brief Set count load for PWM. It cann't be set on the fly.
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ * @param load
+ */
+void LL_PWM_Load_Set(uint8_t pwm_chan_x, uint16_t load);
+
+/**
+ * @brief Set channel compersion value.
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ * @param cmp
+ */
+void LL_PWM_Compare_Set(uint8_t pwm_chan_x, uint16_t cmp);
+
+/**
+ * @brief Read count value of one channel.
+ *
+ * @param pwm_chan_x channel index, valid value is 0~11.
+ * @return uint32_t
+ */
+uint32_t LL_PWM_Count_Read(uint8_t pwm_chan_x);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_PWM_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_qspi.h

@@ -0,0 +1,359 @@
+#ifndef __LL_QSPI_H__
+#define __LL_QSPI_H__
+
+#include "types.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+/***********************************  Macros  ********************************/
+
+// Bitmap for SR (Status Register)
+#define LL_QSPI_STATUS_DCOL    0x40
+#define LL_QSPI_STATUS_TXE     0x20
+#define LL_QSPI_STATUS_RFF     0x10
+#define LL_QSPI_STATUS_FRNE    0x08
+#define LL_QSPI_STATUS_TFE     0x04
+#define LL_QSPI_STATUS_TFNF    0x02
+#define LL_QSPI_STATUS_BUSY    0x01
+
+// Bitmap for IMR (Interrupt Mask Register)
+#define LL_QSPI_INT_MASK_MSTIM     0x20
+#define LL_QSPI_INT_MASK_RXFIM     0x10
+#define LL_QSPI_INT_MASK_RXOIM     0x08
+#define LL_QSPI_INT_MASK_RXUIM     0x04
+#define LL_QSPI_INT_MASK_TXOIM     0x02
+#define LL_QSPI_INT_MASK_TXEIM     0x01
+
+// Bitmap for ISR (Interrupt Status Register)
+#define LL_QSPI_INT_STATUS_MSTIS   0x20
+#define LL_QSPI_INT_STATUS_RXFIS   0x10
+#define LL_QSPI_INT_STATUS_RXOIS   0x08
+#define LL_QSPI_INT_STATUS_RXUIS   0x04
+#define LL_QSPI_INT_STATUS_TXOIS   0x02
+#define LL_QSPI_INT_STATUS_TXEIS   0x01
+
+// Bitmap for RISR (Raw Interrupt Status Register)
+#define LL_QSPI_RAWINT_STATUS_MSTIR    0x20
+#define LL_QSPI_RAWINT_STATUS_RXFIR    0x10
+#define LL_QSPI_RAWINT_STATUS_RXOIR    0x08
+#define LL_QSPI_RAWINT_STATUS_RXUIR    0x04
+#define LL_QSPI_RAWINT_STATUS_TXOIR    0x02
+#define LL_QSPI_RAWINT_STATUS_TXEIR    0x01
+
+// SPI_CTRLR0
+
+/**
+ * @brief Dual/Quad mode instruction length in bits.
+ */
+#define LL_QSPI_INSTRUCTION_LEN_0_BIT      0x00
+#define LL_QSPI_INSTRUCTION_LEN_4_BITS     0x01
+#define LL_QSPI_INSTRUCTION_LEN_8_BITS     0x02
+#define LL_QSPI_INSTRUCTION_LEN_16_BITS    0x03
+
+/**
+ * @brief Length of address to be transmitted.
+ */
+#define LL_QSPI_ADDR_LEN_0_BIT      0x00
+#define LL_QSPI_ADDR_LEN_4_BIT      0x01
+#define LL_QSPI_ADDR_LEN_8_BIT      0x02
+#define LL_QSPI_ADDR_LEN_12_BIT     0x03
+#define LL_QSPI_ADDR_LEN_16_BIT     0x04
+#define LL_QSPI_ADDR_LEN_20_BIT     0x05
+#define LL_QSPI_ADDR_LEN_24_BIT     0x06
+#define LL_QSPI_ADDR_LEN_28_BIT     0x07
+#define LL_QSPI_ADDR_LEN_32_BIT     0x08
+#define LL_QSPI_ADDR_LEN_36_BIT     0x09
+#define LL_QSPI_ADDR_LEN_40_BIT     0x0A
+#define LL_QSPI_ADDR_LEN_44_BIT     0x0B
+#define LL_QSPI_ADDR_LEN_48_BIT     0x0C
+#define LL_QSPI_ADDR_LEN_52_BIT     0x0D
+#define LL_QSPI_ADDR_LEN_56_BIT     0x0E
+#define LL_QSPI_ADDR_LEN_60_BIT     0x0F
+
+/**
+ * @brief SPI_CTRLR0_TRANS_TYPE
+ */
+#define LL_QSPI_BOTH_STANDARD_SPI_MODE                  0
+#define LL_QSPI_INSTRUCTION_STANDARD_ADDRESS_SPECIFIC   1
+#define LL_QSPI_BOTH_SPECIFIC_MODE                      2
+
+
+/***************************  Function Declarations  *************************/
+
+/**
+ * @brief Control the serial data transfer. It is impossible to write to this
+ * register when the QSPI controller is enabled.
+ *
+ * @param spi_frf SPI Frame Format. @see SPI_Format
+ * @param dfs Data Frame Size in 32-bit mode. @see SPI_DataFrame_Size
+ * @param cfs Control Frame Size. Selects the length of the control word for
+ *          the Microwire frame format. @see SPI_Controlframe_Size
+ * @param srl Shift Register Loop. Always set to zero.
+ * @param slv_oe Slave Output Enable. Only used when in serial-slave device.
+ * @param tmod Transfer Mode. Selects the mode of transfer for serial comunication.
+ *          Only indicates whether the receive or transmit data are valid. @see SPI_Transmit_Mode
+ * @param scpol Serial Clock Polarity. Valid when the frame format (FRF) is set
+ *          to Motorola SPI. @see SPI_Clock_Polarity.
+ * @param scph Serial Clock Phase. Valid when the frame format (FRF) is set to
+ *          Motorola SPI. @see SPI_Clock_Phase.
+ * @param frf Frame Format. Selects which serial protocol transfers the data.
+ *          @see SPI_Protocol_Type.
+ */
+void LL_QSPI_CtrlR0Set( uint8_t spi_frf, uint8_t dfs, uint8_t cfs,
+                        uint8_t srl, uint8_t slv_oe, uint8_t tmod,
+                        uint8_t scpol, uint8_t scph, uint8_t frf);
+
+
+/**
+ * @brief Control register 1 controls the end of serial transfers when in
+ * receive-only mode.
+ *
+ * @param ndf Number of Data Frames. When TMOD = 10 or 11, this register field
+ * sets the number of data frames to be continuously received.
+ */
+void LL_QSPI_CtrlR1Set(uint16_t ndf);
+
+/**
+ * @brief
+ *
+ * @param ndf
+ */
+void LL_QSPI_NumOfDataFrameSet(uint16_t ndf);
+
+uint16_t LL_QSPI_NumOfDataFrameGet(void);
+
+/**
+ * @brief SSI Enable.
+ * When disabled, all serial transfers are halted immediately. Transmit and receive
+ * FIFO buffers are cleared when the device is disabled. It is impossible to
+ * program some control registers when enabled.
+ *
+ * @param enable 0 for disable; 1 for enable.
+ */
+void LL_QSPI_Enable(uint8_t enable);
+
+/**
+ * @brief Microwire Control.
+ * Controls the direction of the data word for the half-duplex Microwire serial protocol.
+ *
+ * @param mhs Microwire Handshaking. 0 -- handshaking disabled; 1 -- handshaking enabled.
+ * @param mod Microwire Control. 0 -- receive data word; 1 -- send data word.
+ * @param mwmod Microwire Transfer Mode. 0 -- non-sequential; 1 -- sequential transfer.
+ */
+void LL_QSPI_MicrowireCtrl(uint8_t mhs, uint8_t mod, uint8_t mwmod);
+
+/**
+ * @brief Slave Select Enable Flag.
+ *
+ * @param slave_index 1bit for one slave; 0 -- not selected.
+ */
+void LL_QSPI_SlaveSelect(uint8_t slave_index);
+
+/**
+ * @brief SSI Clock Divider.
+ *
+ * @param sckdiv
+ */
+void LL_QSPI_SckDivSet(uint16_t sckdiv);
+
+/**
+ * @brief Transmit FIFO Threshold Level
+ * Controls the level of entries (or below) at which the transmit FIFO controller
+ * triggers an interrupt. The FIFO depth is configurable in the range 2~256.
+ *
+ * @param lvl
+ */
+void LL_QSPI_TxFIFOThresholdLvlSet(uint8_t lvl);
+
+/**
+ * @brief Receive FIFO Threshold Level
+ * Controls the level of entries (or above) at which the recieve FIFO controller
+ * triggers an interrupt. The FIFO depth is configurable in the range 2~256.
+ *
+ * @param lvl
+ */
+void LL_QSPI_RxFIFOThresholdLvlSet(uint8_t lvl);
+
+/**
+ * @brief Transmit FIFO Level
+ *
+ * @return uint8_t
+ */
+uint8_t LL_QSPI_TxFIFOLvlGet(void);
+
+/**
+ * @brief Receive FIFO Level
+ *
+ * @return uint8_t
+ */
+uint8_t LL_QSPI_RxFIFOLvlGet(void);
+
+/**
+ * @brief Indicates the current transfer status, FIFO status, and any transmission
+ * or reception errors that may have occured. The status register may be read at
+ * any time. None of the bits in this register request an interrupt.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_QSPI_Status(void);
+
+uint8_t LL_QSPI_IsDataCollision(void);
+
+uint8_t LL_QSPI_IsTxError(void);
+
+uint8_t LL_QSPI_IsRxFIFOFull(void);
+
+uint8_t LL_QSPI_IsRxFIFONotEmpty(void);
+
+uint8_t LL_QSPI_IsTxFIFOEmpty(void);
+
+uint8_t LL_QSPI_IsTxFIFONotFull(void);
+
+uint8_t LL_QSPI_IsBusy(void);
+
+/**
+ * @brief Disable all interruts.
+ *
+ */
+void LL_QSPI_IntMaskAll(void);
+
+/**
+ * @brief Enable all interrupts.
+ *
+ */
+void LL_QSPI_IntUnMaskAll(void);
+
+/**
+ * @brief Disable particular interrupt.
+ *
+ * @param intMaskBit @see LL_QSPI_INT_MASK_MSTIM
+ */
+void LL_QSPI_IntMask(uint8_t intMaskBit);
+
+/**
+ * @brief Enable particular interrupts.
+ *
+ * @param intMaskBit @see LL_QSPI_INT_MASK_MSTIM
+ */
+void LL_QSPI_IntUnMask(uint8_t intMaskBit);
+
+/**
+ * @brief Get Interrupt status.
+ *
+ * @return uint8_t interrupt status after they have been masked.
+ */
+uint8_t LL_QSPI_IntStatus(void);
+
+/**
+ * @brief Get raw interrupt status.
+ *
+ * @return uint8_t raw interrupts prior to masking.
+ */
+uint8_t LL_QSPI_RawIntStatus(void);
+
+/**
+ * @brief Clear Transmit FIFO Overflow Interrupt.
+ *
+ */
+void LL_QSPI_IntClearTxFIFOOverflow(void);
+
+/**
+ * @brief Clear Receive FIFO Overflow Interrupt.
+ *
+ */
+void LL_QSPI_IntClearRxFIFOOverflow(void);
+
+/**
+ * @brief Clear Receive FIFO Underflow Interrupt.
+ *
+ */
+void LL_QSPI_IntClearRxFIFOUnderflow(void);
+
+/**
+ * @brief Clear Multi-Master Contention Interrupt.
+ *
+ */
+void LL_QSPI_IntClearMultiMasterContention(void);
+
+/**
+ * @brief Clear Interrupts.
+ *
+ */
+void LL_QSPI_IntClearAll(void);
+
+/**
+ * @brief DMA Control
+ *
+ * @param tdmae Transmit DMA Enable
+ * @param rdmae Receive DMA Enable
+ */
+void LL_QSPI_DMACtrl(uint8_t tdmae, uint8_t rdmae);
+
+/**
+ * @brief DMA Transmit Data Level.
+ *
+ * @param level
+ */
+void LL_QSPI_DMATxDataLvlSet(uint8_t level);
+
+/**
+ * @brief DMA Receive Data Level.
+ *
+ * @param level
+ */
+void LL_QSPI_DMARxDataLvlSet(uint8_t level);
+
+/**
+ * @brief Data Register
+ *
+ * @return uint32_t
+ */
+uint32_t LL_QSPI_DataRegGet(void);
+
+void LL_QSPI_DataRegSet(uint32_t val);
+
+/**
+ * @brief Return DR register address.
+ * 
+ * @return uint32_t* address of DR register.
+ */
+uint32_t * LL_QSPI_DataRegAddrGet(void);
+
+/**
+ * @brief Get address of DR_Reversed Register.
+ *
+ * @return uint32_t*
+ */
+uint32_t * LL_QSPI_DRReversedAddrGet(void);
+
+void LL_QSPI_DRReversedSet(uint32_t val);
+
+uint32_t LL_QSPI_DRReversedGet(void);
+
+/**
+ * @brief Set Rx Sample Delay.
+ *
+ * @param rsd
+ */
+void LL_QSPI_RxSampleDlySet(uint8_t rsd);
+
+/**
+ * @brief Control the serial data transfer in SPI mode of operation.
+ *
+ * @param wait_cycles defines the wait cycles in dual/quad mode between control
+ *          frames transmit and data reception.
+ * @param inst_len Dual/Quad mode instruction length in bits. @see LL_QSPI_INST_LEN_0_BIT
+ * @param addr_len defines length of address to be transmitted. @see LL_QSPI_ADDR_LEN_0_BIT
+ * @param trans_type Address and instruction transfer format.
+ */
+void LL_QSPI_SPICtrl(uint8_t wait_cycles, uint8_t inst_len, uint8_t addr_len, uint8_t trans_type);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_QSPI_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_rtc.h

@@ -0,0 +1,103 @@
+#ifndef __LL_RTC_H_
+#define __LL_RTC_H_
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+//////////////////////////////  Data type and Macros  /////////////////////////
+#define LL_RTC_WRAP_DISABLE         0
+#define LL_RTC_WRAP_ENABLE          1
+
+#define LL_RTC_INT_UNMASK           0
+#define LL_RTC_INT_MASK             1
+
+#define LL_RTC_INT_DISABLE          0
+#define LL_RTC_INT_ENABLE           1
+
+#define LL_RTC_INT_STATUS_INACTIVE  0
+#define LL_RTC_INT_STATUS_ACTIVE    1
+
+#define LL_RTC_DISABLE              0
+#define LL_RTC_ENABLE               1
+
+
+//////////////////////////////  Function Declaration  /////////////////////////
+
+/**
+ * @brief  Get the current value of the internal counter.
+ * @return return the interal counter of rtc.
+ */
+uint32_t LL_RTC_GetCurValue(void);
+
+/**
+ * @brief  Set the match counter of rtc.
+ * @param  matchCounter: the match counter of rtc. 
+ *         The rtc counter always count forward. when the load counter reach the match counter an interrupt will trigger.
+ * @return This function has no return value.
+ */
+void LL_RTC_SetMatchCounter(uint32_t matchCounter);
+uint32_t LL_RTC_GetMatchCounter(void);
+
+/**
+ * @brief  Set the load counter of rtc.
+ * @param  loadCounter: the load counter of rtc. It is the value where rtc start counting forward
+ * @return This function has no return value.
+ */
+void LL_RTC_SetLoadCounter(uint32_t loadCounter);
+
+/**
+ * @brief  To force the counter to wrap when a match occurs
+ * @param  en: 1 to enable a wrap, 0 to disable a wrap
+ * @return This function has no return value.
+ */
+void LL_RTC_Wrap(uint8_t en);
+
+/**
+ * @brief  Enable the RTC counter.
+ * @param  en: 1 to enable the counter, 0 to disable the counter
+ * @return This function has no return value.
+ */
+void LL_RTC_Enable(uint8_t en);
+
+/**
+ * @brief  Set whether to mask the rtc interrupt or not
+ * @param  en: 1 to mask the interrupt, 0 to unmask the interrupt
+ * @return This function has no return value.
+ */
+void LL_RTC_IntMask(uint8_t en);
+
+/**
+ * @brief  Set whether to enable the rtc interrupt or not
+ * @param  en: 1 to enable the interrupt, 0 to disable the interrupt
+ * @return This function has no return value.
+ */
+void LL_RTC_IntEnable(uint8_t en);
+
+/**
+ * @brief  Get the status of rtc interrupt, after the mask
+ * @return The interrupt status after the int mask. 1 means interrupt is active, 0 means interrupt is inactive.
+ */
+uint8_t LL_RTC_IntStatus(void);
+
+/**
+ * @brief  Get the raw status of rtc interrupt, before the mask
+ * @return The interrupt status before the int mask. 1 means interrupt is active, 0 means interrupt is inactive.
+ */
+uint8_t LL_RTC_IntRawStatus(void);
+
+/**
+ * @brief  Clear rtc interrupt
+ * @return This function has no return value.
+ */
+void LL_RTC_ClearInt(void);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_RTC_H_

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_sdio.h

@@ -0,0 +1,194 @@
+#ifndef __LL_SDIO_H__
+#define __LL_SDIO_H__
+
+#include "types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+typedef enum {
+    SDIO_FUNC0 = 0,
+    SDIO_FUNC1,
+    SDIO_FUNC2,
+    SDIO_FUNC3,
+    SDIO_FUNC4,
+    SDIO_FUNC5,
+    SDIO_FUNC6,
+    SDIO_FUNC7
+} sdio_func_enum_t;
+
+enum {
+    Fn1_Write_Over_Interrupt_Disabled = 0,
+    Fn1_Write_Over_Interrupt_Enabled
+};
+enum {
+    Fn1_Read_Over_Interrupt_Disabled = 0,
+    Fn1_Read_Over_Interrupt_Enabled
+};
+enum {
+    Read_Error_Fn1_Interrupt_Disabled = 0,
+    Read_Error_Fn1_Interrupt_Enabled
+};
+enum {
+    Write_Error_Fn1_Interrupt_Disabled = 0,
+    Write_Error_Fn1_Interrupt_Enabled
+};
+enum {
+    Write_Abort_Fn1_Interrupt_Disabled = 0,
+    Write_Abort_Fn1_Interrupt_Enabled
+};
+enum {
+    Reset_Fn1_Interrupt_Disabled = 0,
+    Reset_Fn1_Interrupt_Enabled
+};
+enum {
+    Fn1_Enable_Interrupt_Disabled = 0,
+    Fn1_Enable_Interrupt_Enabled
+};
+enum {
+    Fn1_Status_Pcrrt_Interrupt_Disabled = 0,
+    Fn1_Status_Pcrrt_Interrupt_Enabled
+};
+enum {
+    Fn1_Status_Pcwrt_Interrupt_Disabled = 0,
+    Fn1_Status_Pcwrt_Interrupt_Enabled
+};
+enum {
+    Fn1_Rtc_Set_Interrupt_Disabled = 0,
+    Fn1_Rtc_Set_Interrupt_Enabled
+};
+enum {
+    Fn1_Clintrd_Interrupt_Disabled = 0,
+    Fn1_Clintrd_Interrupt_Enabled
+};
+enum {
+    Fn1_Int_En_Up_Interrupt_Disabled = 0,
+    Fn1_Int_En_Up_Interrupt_Enabled
+};
+enum {
+    Fn1_M2s_Int_Interrupt_Disabled = 0,
+    Fn1_M2s_Int_Interrupt_Enabled
+};
+enum {
+    SDIO_IO_Disabled = 0,
+    SDIO_IO_Enabled
+};
+enum {
+    Clr_Busy_SD_Disabled = 0,
+    Clr_Busy_SD_Enabled
+};
+enum {
+    Supp_High_Speed_Disabled = 0,
+    Supp_High_Speed_Enabled
+};
+enum {
+    Power_Selection_Disabled = 0,
+    Power_Selection_Enabled
+};
+
+#define CLEAR_BUSY_SD               (0)
+#define SET_BUSY_SD                 (1)
+#define FN1_CSA_SUPPORT             (1 << 0)
+#define FN2_CSA_SUPPORT             (1 << 1)
+#define FN3_CSA_SUPPORT             (1 << 2)
+#define FN4_CSA_SUPPORT             (1 << 3)
+#define FN5_CSA_SUPPORT             (1 << 4)
+#define FN6_CSA_SUPPORT             (1 << 5)
+#define FN7_CSA_SUPPORT             (1 << 6)
+
+#define  SDIO_CCCR_CAP_SCSI  (1 << 0)
+#define  SDIO_CCCR_CAP_SDC  (1 << 1)    /* can do CMD52 while data transfer */
+#define  SDIO_CCCR_CAP_SMB  (1 << 2)    /* can do multi-block xfers (CMD53) */
+#define  SDIO_CCCR_CAP_SRW  (1 << 3)    /* supports read-wait protocol */
+#define  SDIO_CCCR_CAP_SBS  (1 << 4)    /* supports suspend/resume */
+#define  SDIO_CCCR_CAP_S4MI (1 << 5)    /* interrupt during 4-bit CMD53 */
+#define  SDIO_CCCR_CAP_E4MI (1 << 6)    /* enable ints during 4-bit CMD53 */
+#define  SDIO_CCCR_CAP_LSC  (1 << 7)    /* low speed card */
+#define  SDIO_CCCR_CAP_4BLS (1 << 8)    /* 4 bit low speed card */
+
+#define  REVISION_REG_SD    (0x232)
+
+#define SDIO_IO_READY                   (1)
+#define SDIO_DEVICE_READY               (1 << 0)
+#define SDIO_CARD_READY                 (1 << 1)
+#define SDIO_CPU_IN_ACTIVE              (1 << 2)
+#define SDIO_FBR1_REG                   (0xFF)
+#define SDIO_INTERFACE_CODE             (0xF)
+#define SDIO_HOST_IIR_REG_CLEAR         (0)
+#define SDIO_HOST_IIR_REG_SET           (1)
+#define SDIO_SUPPORT_FUNC_NUM           (1 << 4)    //support 1 func
+
+#define FN1_WRITE_OVER_INTERRPT         (1 << 0)
+#define FN1_READ_OVER_INTERRPT          (1 << 1)
+#define READ_ERROR_FN1_INTERRPT         (1 << 2)
+#define WRITE_ERROR_FN1_INTERRPT        (1 << 3)
+#define WRITE_ABORT_FN1_INTERRPT        (1 << 4)
+#define RESET_FN1_INTERRPT              (1 << 5)
+#define FN1_ENABLE_INTERRPT             (1 << 6)
+#define FN1_STATUS_PCRRT_INTERRPT       (1 << 7)
+#define FN1_STATUS_PCWRT_INTERRPT       (1 << 8)
+#define FN1_RTC_SET_INTERRPT            (1 << 9)
+#define FN1_CLINTRD_INTERRPT            (1 << 10)
+#define FN1_INT_EN_UP_INTERRPT          (1 << 11)
+#define FN1_M2S_INT_INTERRPT            (1 << 20)
+
+#define SDIO_FUN_CIS_LENGTH_OFFSET          4
+#define SDIO_FUNC_CIS_CHECKSUM_OFFSET       6
+#define SDIO_FUNC_BLOCK_SIZE                512
+#define SET_CISTPL_CHECKSUM                 0   //If Host check CIS tuple checksum, set this to 1.
+
+typedef union {
+    uint32_t val;
+    struct {
+        uint32_t                     fn1_wr_ovr :  1; /* 0: 0,          interrupt enable bit */
+        uint32_t                     fn1_rd_ovr :  1; /* 1: 1,          interrupt enable bit */
+        uint32_t                     rd_err_fn1 :  1; /* 2: 2,          interrupt enable bit */
+        uint32_t                     wr_err_fn1 :  1; /* 3: 3,          interrupt enable bit */
+        uint32_t                   wr_abort_fn1 :  1; /* 4: 4,          interrupt enable bit */
+        uint32_t                        rst_fn1 :  1; /* 5: 5,          interrupt enable bit */
+        uint32_t                         fn1_en :  1; /* 6: 6,          interrupt enable bit */
+        uint32_t               fn1_status_pcrrt :  1; /* 7: 7,          interrupt enable bit */
+        uint32_t               fn1_status_pcwrt :  1; /* 8: 8,          interrupt enable bit */
+        uint32_t                    fn1_rtc_set :  1; /* 9: 9,          interrupt enable bit */
+        uint32_t                    fn1_clintrd :  1; /*10:10,          interrupt enable bit */
+        uint32_t                  fn1_int_en_up :  1; /*11:11,          interrupt enable bit */
+        uint32_t                     reserved_1 :  8; /*19:12,                             NA*/
+        uint32_t                    fn1_m2s_int :  1; /*20:20,          interrupt enable bit */
+        uint32_t                     reserved_0 : 11; /*31:21,                             NA*/
+    } bit_field;
+} sdio_interrupt_enable_ctrl_t;
+
+typedef struct {
+    uint8_t                         supp_func_num;
+    uint8_t                         clr_busy_sd;
+    uint8_t                         csa_support;
+    uint8_t                         supp_high_speed;
+    uint16_t                        card_cap_sd;
+    uint8_t                         *cis_fn0_base;
+    uint8_t                         *cis_fn1_base;
+    uint8_t                         *from_host_buffer;
+    sdio_interrupt_enable_ctrl_t    int_en_ctrl;
+} sdio_config_t;
+
+uint8_t *ll_sdio_cis_func_get(sdio_func_enum_t fn);
+bool ll_sdio_cis_fn_set(sdio_func_enum_t fn, uint32_t offset, uint8_t value);
+uint32_t *ll_sdio_receive_from_host_buffer_get(void);
+void ll_sdio_receive_from_host_buffer_set(uint8_t *addr);
+uint16_t ll_sdio_receive_from_host_buffer_size_get(void);
+uint32_t *ll_sdio_xfer_to_host_buffer_get(void);
+void ll_sdio_xfer_to_host_buffer_set(uint8_t *addr);
+void ll_sdio_xfer_to_host_buffer_size_set(uint32_t size);
+void ll_sdio_triggle_data1_interrupt_to_host(void);
+void ll_sdio_init(sdio_config_t *config);
+uint32_t ll_sdio_get_interrupt_status(void);
+void ll_sdio_set_interrupt_status(uint32_t st);
+void ll_sdio_clear_busy_sd(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __LL_SDIO_H__
+
+

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_sleep.h

@@ -0,0 +1,28 @@
+#ifndef __LL_SLEEP_H__
+#define __LL_SLEEP_H__
+
+#include "types.h"
+
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+typedef enum
+{
+    ACTIVE = 0,
+    LIGHT_SLEEP,
+    DEEP_SLEEP,
+    RETENTION_SLEEP,
+    FROZEN_SLEEP
+}sleep_mode_enum_t;
+
+void ll_pre_sleep_processing(sleep_mode_enum_t sleep_mode, uint8_t sram_powerdown);
+void ll_post_sleep_processing(sleep_mode_enum_t sleep_mode);
+
+#ifdef __cplusplus
+    }
+#endif // __cplusplus
+
+#endif // __LL_SLEEP_H__
+
+

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_spim.h

@@ -0,0 +1,479 @@
+#ifndef __LL_SPIM_H__
+#define __LL_SPIM_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  CTRLR0  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief
+ *
+ * @param dfs Data Frame Size in 32-bit mode.
+ * @param cfs Control Frame Size.
+ * @param srl Shift Register Loop.
+ * @param slv_oe NOT usued.
+ * @param tmod Transfer mode. Only indicates whether the receive or transmit data are valid.
+ * 00 -- Transmit & Receive
+ * 01 -- Transmit Only
+ * 10 -- Receive Only
+ * 11 -- EEPROM Read
+ * @param scpol Serial Clock Polarity.
+ * 0 -- Inactive state of serial clock is low.
+ * 1 -- Inactive state of serial clock is high.
+ * @param scph Serial Clock Phase.
+ * 0 -- Serial clock toggles in middle of first data bit.
+ * 1 -- Serial clock toggles at start of first data bit.
+ * @param frf Frame Format. Selects which serial protocol transfers the data.
+ * 00 -- Motorola SPI
+ * 01 -- Texas Instruments SSP
+ * 10 -- National Semiconductors Microwire
+ * 11 -- Reserved
+ */
+void LL_SPIM_CtrlR0(uint8_t dfs,uint8_t cfs,uint8_t srl,uint8_t slv_oe,uint8_t tmod,uint8_t scpol,uint8_t scph,uint8_t frf);
+
+/**
+ * @brief Data Frame Size in 32-bit mode.
+ *
+ * @param dfs
+ */
+void LL_SPIM_DataFrameSize_Set(uint8_t dfs);
+
+/**
+ * @brief Control Frame Size. Selects the length of the control word for the
+ * Microwire frame format.
+ *
+ * @param cfs
+ */
+void LL_SPIM_CtrlFrameSize_Set(uint8_t cfs);
+
+/**
+ * @brief Transfer Mode. Selects the mode of transfer for serial communication.
+ *
+ * @param tmod
+ * 00 -- Transmit & Receive
+ * 01 -- Transmit Only
+ * 10 -- Receive Only
+ * 11 -- EEPROM Read
+ */
+void LL_SPIM_TransferMode_Set(uint8_t tmod);
+
+/**
+ * @brief Serial Clock Polarity. Valid when the FRF is set to Motorola SPI.
+ *
+ * @param scpol
+ * 0 -- Inactive state of serial clock is low
+ * 1 -- Inactive state of serial clock is high
+ */
+void LL_SPIM_ClkPolarity_Set(uint8_t scpol);
+
+/**
+ * @brief Serial Clock Phase. Valid when the FRF is set to Motorola SPI.
+ *
+ * @param scph
+ * 0 -- Serial Clock toggles in middle of first data bit
+ * 1 -- Serial Clock toggles at start of first data bit
+ */
+void LL_SPIM_ClkPhase_Set(uint8_t scph);
+
+/**
+ * @brief Frame Format. Selects which serial protocol transfers the data.
+ *
+ * @param frf
+ * 00 -- Motorola SPI
+ * 01 -- Texas Instruments SSP
+ * 10 -- National Semeconductors Microwire
+ * 11 -- Reserved
+ */
+void LL_SPIM_FrameFormat_Set(uint8_t frf);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  CTRLR1  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief
+ *
+ * @param ndf Number of Data Frames. When TMOD = 10 or TMOD = 11, this register
+ * field sets the number of data frames to be continuously received by the SPIM
+ * controller.
+ */
+void LL_SPIM_CtrlR1(uint16_t ndf);
+
+/**
+ * @brief
+ *
+ * @param ndf Number of Data Frames. When TMOD = 10 or TMOD = 11, this register
+ * field sets the number of data frames to be continuously received by the SPIM
+ * controller.
+ */
+void LL_SPIM_NumDataFrame_Set(uint16_t ndf);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  SSIENR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Enable/Disable the SPIM controller.
+ *
+ * @param en 1--enable; 0--disable.
+ */
+void LL_SPIM_Enable(uint8_t en);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   MWCR   ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Microwire Setting.
+ *
+ * @param handshake_en Used to enable/disable the "busy/ready" handshaking interface
+ * for the Microwire protocol.
+ * 0 -- handshaking disabled;
+ * 1 -- handshaking enabled.
+ * @param mw_mod Microwire Control.
+ * 0 -- receive data word from external serial device.
+ * 1 -- Send data word to external serial device.
+ * @param mw_txmod Microwrie Transfer Mode. Defines whether the Microwire transfer is
+ * sequential or non-sequential.
+ * 0 -- non-sequential transfer.
+ * 1 -- sequential transfer.
+ */
+void LL_SPIM_Microwire_Setting(uint8_t handshake_en, uint8_t mw_mod, uint8_t mw_txmod);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   SER    ////////////////////////////////////
+//////////////////////////// Slave Select Enable //////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Slave Select. Each bit in this register corresponds to a slave select
+ * line from the SPIM controller. When a bit in this register is set(1), the
+ * corresponding slave select line is activated whena serial transfer begins.
+ *
+ * @param id slave id.
+ */
+void LL_SPIM_Slave_Select(uint8_t id);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   BAUDR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Clock Divider.
+ *
+ * @param div
+ */
+void LL_SPIM_CLK_Div(uint16_t div);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  TXFTLR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Transmit FIFO Threshold. Controls the level of entries (or below) at
+ * which the transmit FIFO controller triggers an interrupt.
+ *
+ * @param tx_thd valid range is 2~256.
+ */
+void LL_SPIM_TX_FIFO_Threshold_Set(uint8_t tx_thd);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  RXFTLR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Receive FIFO Threshold. Controls the level of entries (or above) at
+ * which the receive FIFO controller triggers an interrupt.
+ *
+ * @param rx_thd valid range is 2~256.
+ */
+void LL_SPIM_RX_FIFO_Threshold_Set(uint8_t rx_thd);
+
+/**
+ * @brief Set TX and RX FIFO threshold.
+ *
+ * @param tx_thd
+ * @param rx_thd
+ */
+void LL_SPIM_FIFO_Threshold_Set(uint8_t tx_thd, uint8_t rx_thd);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   TXFLR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Transmit FIFO Level. Contains the number of valid data entries in the TX FIFO.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Current_TxFIFO_Level(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   RXFLR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Receive FIFO Level. Contains the number of valid data entries in the RX FIFO.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Current_RxFIFO_Level(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////    SR    ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Status Register. Contains the following status:
+ * 0. Busy, indicates that a serial transfer is in progress
+ * 1. tfnf, Transmit FIFO Not Full
+ * 2. tfe, Transmit FIFO Empty
+ * 3. rfne, Receive FIFO Not Empty
+ * 4. rff, Receive FIFO Full
+ * 5. txe, Transmission Error
+ * 6. dcol, Data Collision Error
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Normal_Status(void);
+
+/**
+ * @brief Is SPIM Data collision?
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Is_DataColError(void);
+
+/**
+ * @brief Is SPIM Transmission Error?
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Is_TxError(void);
+
+/**
+ * @brief Is SPIM Rx FIFO full?
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Is_RxFIFOFull(void);
+
+/**
+ * @brief Is SPIM Rx FIFO not empty?
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Is_RxFIFONotEmpty(void);
+
+/**
+ * @brief Is SPIM Tx FIFO empty?
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Is_TxFIFOEmpty(void);
+
+/**
+ * @brief Is SPIM Tx FIFO not full?
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Is_TxFIFONotFull(void);
+
+/**
+ * @brief Is SPIM busy?
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_Is_Busy(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   IMR    ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Each bit represents an interrupt mask, write 0 to disable interrupt.
+ *
+ * @param mask
+ * 0 -- masked (disabled).
+ * 1 -- not masked (enabled).
+ */
+void LL_SPIM_IntMask_Set(uint8_t mask);
+
+uint8_t LL_SPIM_IntMask_Get(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   ISR    ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Get Interrupt Status after masked.
+ *
+ * @return uint8_t one bit for one interrupt.
+ * bit5 -- mstis, Multi-Master Contention Interrupt Status
+ * bit4 -- rxfis, Receive FIFO Full Interrupt Status
+ * bit3 -- rxois, Receive FIFO Overflow Interrupt Status
+ * bit2 -- rxuis, Receive FIFO Underflow Interrupt Status
+ * bit1 -- txois, Transmit FIFO Overflow Interrupt Status
+ * bit0 -- txeis, Transmit FIFO Empty Interrupt Status
+ */
+uint8_t LL_SPIM_Int_Status(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////   RISR    ///////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Return Raw Interrupt Status.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_RawInt_Status(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  TXOICR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Clear Transmit FIFO Overflow Interrupt, and return the interrupt status.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_IntClr_TxFIFOOverflow(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  RXOICR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Clear Receive FIFO Overflow Interrupt and return the interrupt status.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_IntClr_RxFIFOOverflow(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  RXUICR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Clear Receive FIFO Underflow Interrupt and return the interrupt status.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_IntClr_RxFIFOUnderflow(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  MSTICR  ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Clear Multi-Master Contention Interrupt and return the interrupt status.
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_IntClr_MultiMaster(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////    ICR   ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Clear Interrupts (txo, rxu, rxo, mst).
+ *
+ * @return uint8_t
+ */
+uint8_t LL_SPIM_IntClr_All(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  DMACR   ////////////////////////////////////
+//////////////////////// DMA Tx, Rx enable/disabel  ///////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Enable/Disable Transmit DMA.
+ *
+ * @param en 1--enable; 0--disable.
+ */
+void LL_SPIM_TxDMA_Enable(uint8_t en);
+
+/**
+ * @brief Enable/Disable Receive DMA.
+ *
+ * @param en 1--enable; 0--disable.
+ */
+void LL_SPIM_RxDMA_Enable(uint8_t en);
+
+/**
+ * @brief SPIM DMA Tx, Rx enable/disable.
+ *
+ * @param tx_en 0 -- disable; 1 -- enable.
+ * @param rx_en 0 -- disable; 1 -- enable.
+ */
+void LL_SPIM_DMA_Ctrl(uint8_t tx_en, uint8_t rx_en);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  DMATDLR ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief SPIM DMA Transmit Data Level.
+ *
+ * @param tx_lvl
+ */
+void LL_SPIM_DMA_TxLvl_Set(uint8_t tx_lvl);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////  DMARDLR ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief SPIM DMA Receive Data Level.
+ *
+ * @param rx_lvl
+ */
+void LL_SPIM_DMA_RxLvl_Set(uint8_t rx_lvl);
+
+/**
+ * @brief SPIM DMA Tx, Rx Data Level set.
+ *
+ * @param tx_lvl
+ * @param rx_lvl
+ */
+void LL_SPIM_DAM_DataLvl_Set(uint8_t tx_lvl, uint8_t rx_lvl);
+
+///////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////    DR    ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Write to Data Register.
+ *
+ * @param data
+ */
+void LL_SPIM_DataReg_Set(uint32_t data);
+
+/**
+ * @brief Get data from Data Register.
+ *
+ * @return uint32_t
+ */
+uint32_t LL_SPIM_DataReg_Get(void);
+
+///////////////////////////////////////////////////////////////////////////////
+//////////////////////////////  RXSAMPLE_DLY  /////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Set SPIM Rx sample delay.
+ *
+ * @param dly
+ */
+void LL_SPIM_RxSampleDly_Set(uint8_t dly);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_SPIM_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_spim2.h

@@ -0,0 +1,68 @@
+#ifndef __LL_SPIM2_H__
+#define __LL_SPIM2_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+void LL_SPIM2_MiscCfg(uint16_t val);
+
+void LL_SPIM2_TxInt_Enable(uint8_t en);
+
+void LL_SPIM2_RxInt_Enable(uint8_t en);
+
+void LL_SPIM2_OverflowInt_Enable(uint8_t en);
+
+void LL_SPIM2_ModefaultInt_Enable(uint8_t en);
+
+void LL_SPIM2_Enable(uint8_t en);
+
+void LL_SPIM2_BaudRate_Set(uint8_t baud_rate);
+        
+void LL_SPIM2_Master_Enable(uint8_t en);
+void LL_SPIM2_Clk_Polarity(uint8_t clk_polarity);
+void LL_SPIM2_Clk_Phase(uint8_t clk_phase);
+uint8_t LL_SPIM2_IsTxEmpty(void);
+
+
+/**
+ * @brief Mode Fault Enable bit.
+ *
+ * @param en
+ */
+void LL_SPIM2_ModeFault_Enable(uint8_t en);
+
+void LL_SPIM2_StartTransfer(void);
+
+/**
+ * @brief Set transfer direction. 1 for read, 0 for write.
+ *
+ * @param rw
+ */
+void LL_SPIM2_Set_ReadWriteDir(uint8_t rw);
+
+void LL_SPIM2_Set_AddrLength(uint8_t length);
+
+void LL_SPIM2_Set_DataLength(uint8_t length);
+
+void LL_SPIM2_TxData0_Set(uint32_t data0);
+
+void LL_SPIM2_TxData1_Set(uint32_t data1);
+
+uint32_t LL_SPIM2_RxData0_Get(void);
+
+uint32_t LL_SPIM2_RxData1_Get(void);
+
+uint8_t LL_SPIM2_RawInt_Status(void);
+
+uint8_t LL_SPIM2_Int_Status(void);
+
+void LL_SPIM2_IntClr(uint8_t int_map);
+
+void LL_SPIM2_IntClr_All(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_SPIM2_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_spis.h

@@ -0,0 +1,74 @@
+#ifndef __LL_SPIS_H__
+#define __LL_SPIS_H__
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+void LL_SPIS_CtrlR0(uint8_t dfs, uint8_t cfs, uint8_t srl, uint8_t slv_oe, uint8_t tmod, uint8_t scpol, uint8_t scph, uint8_t frf);
+
+void LL_SPIS_Enable(uint8_t en);
+
+void LL_SPIS_MW_HandShake_Enable(uint8_t en);
+
+void LL_SPIS_MW_Mode_Set(uint8_t mode);
+
+void LL_SPIS_MW_TxMode_Set(uint8_t transfer_mode);
+
+void LL_SPIS_TxFIFO_Threshold_Set(uint8_t tx_thd);
+
+void LL_SPIS_RxFIFO_Threshold_Set(uint8_t rx_thd);
+
+uint8_t LL_SPIS_Current_TxFIFO_Level(void);
+
+uint8_t LL_SPIS_Current_RxFIFO_Level(void);
+
+uint8_t LL_SPIS_Normal_Status(void);
+
+uint8_t LL_SPIS_Is_DataCollision(void);
+
+uint8_t LL_SPIS_Is_TxError(void);
+
+uint8_t LL_SPIS_Is_RxFIFO_Full(void);
+
+uint8_t LL_SPIS_Is_RxFIFO_NotEmpty(void);
+
+uint8_t LL_SPIS_Is_TxFIFO_Empty(void);
+
+uint8_t LL_SPIS_Is_TxFIFO_NotFull(void);
+
+uint8_t LL_SPIS_Is_Busy(void);
+
+void LL_SPIS_IntMask_Set(uint8_t mask_map);
+
+uint8_t LL_SPIS_IntMask_Get(void);
+
+uint8_t LL_SPIS_Int_Status(void);
+
+uint8_t LL_SPIS_RawInt_Status(void);
+
+uint8_t LL_SPIS_IntClr_TxOverflow(void);
+
+uint8_t LL_SPIS_IntClr_RxOverflow(void);
+
+uint8_t LL_SPIS_IntClr_RxUnderflow(void);
+
+uint8_t LL_SPIS_IntClr_MultiMaster(void);
+
+uint8_t LL_SPIS_IntClr_All(void);
+
+void LL_SPIS_DMA_Ctrl(uint8_t tx_dma_en, uint8_t rx_dma_en);
+
+void LL_SPIS_DMA_TxDataLevel(uint8_t tx_lvl);
+
+void LL_SPIS_DMA_RXDataLevel(uint8_t rx_lvl);
+
+void LL_SPIS_DataReg_Set(uint32_t data);
+
+uint32_t LL_SPIS_DataReg_Get(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_SPIS_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_syscon.h

@@ -0,0 +1,340 @@
+#ifndef __LL_SYSCON_H_
+#define __LL_SYSCON_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "types.h"
+#include "hal/syscon_types.h"
+
+/**
+ * @brief Real 32K period, can be used by SW to calculate PPM.
+ *
+ * @return uint16_t
+ */
+uint16_t LL_SYSCON_Get32KPeriodNs(void);
+
+/**
+ * @brief Enable of cal 32K, enable of update calibratioin result.
+ *
+ */
+void LL_SYSCON_32KCaliEnable(void);
+
+/**
+ * @brief Set CPU sleep duration time, unit: ns.
+ *
+ * @param n_ns CPU sleep duration time, unit is ns.
+ */
+void LL_SYSCON_CPUSleepDurationEnable(unsigned long long n_ns);
+
+/**
+ * @brief Disable CPU sleep.
+ *
+ */
+void LL_SYSCON_CPUSleepDurationDisable(void);
+
+/**
+ * @brief Get CPU real sleep time.
+ *
+ * @return uint64_t real sleep time, unit is ns.
+ */
+uint64_t LL_SYSCON_RealSleepTime(void);
+
+/**
+ * @brief Get always on idle reg value.
+ *
+ * @return uint32_t awo idle reg value
+ */
+uint32_t LL_SYSCON_IdleReg(void);
+
+/**
+ * @brief Calculate compensate time, unit is ns.
+ *
+ * @return uint32_t compensate time.
+ */
+uint32_t LL_SYSCON_CalculateCompensateNs(void);
+
+/**
+ * @brief Indicate a true lock after debounce logic.
+ *
+ * @return true locked.
+ * @return false not locked.
+ */
+bool LL_SYSCON_IsSysPllLocked(void);
+
+/**
+ * @brief Set lock signal parity, debounce delay.
+ *
+ * @param lock_polarity 1 bit.
+ * @param debounce_dly threshold to indicate a true lock.
+ */
+void LL_SYSCON_SysPllDebounceSet(uint8_t lock_polarity, uint8_t debounce_dly);
+
+/**
+ * @brief Select flash mode or mirror mode.
+ *
+ * @param mode 1 -- flash mode; 0 -- mirror mode.
+ */
+void LL_SYSCON_FlashOrMirrorMode(uint8_t mode);
+
+/**
+ * @brief Get boot mode.
+ *
+ * @return uint8_t  bootmode bit[0:2]
+ */
+uint8_t LL_SYSCON_GetBootMode(void);
+
+/**
+ * @brief Reset Core, only five options is valid: all, phy, rtc, wic, pmu.
+ *
+ * @param src one option of pmu, wic, rtc, phy, all.
+ */
+void LL_SYSCON_SoftwareResetCore(SYSCON_SwRst_Core src);
+
+/**
+ * @brief Select HCLK source to PLL.
+ *
+ */
+void LL_SYSCON_ClkSwitchToPll(void);
+
+/**
+ * @brief Select HCLK source to XTAL.
+ *
+ */
+void LL_SYSCON_ClkSwitchToXtal(void);
+
+/**
+ * @brief HCLK source select.
+ *
+ * @param src @see SYSTEM_CLOCK_SRC.
+ */
+void  LL_SYSCON_SelectSysClkSrc(SYSTEM_CLOCK_SRC src);
+
+/**
+ * @brief Set HCLK division.
+ *
+ * @param ahb_divider
+ */
+void LL_SYSCON_SetHclkDivision(uint8_t ahb_divider);
+
+/**
+ * @brief Set PCLK0 division.
+ *
+ * @param apb0_divider
+ */
+void LL_SYSCON_SetPclk0Division(uint8_t apb0_divider);
+
+/**
+ * @brief Set PCLK1 Division.
+ *
+ * @param apb1_divider
+ */
+void LL_SYSCON_SetPclk1Division(uint8_t apb1_divider);
+
+
+/**
+ * @brief Set hardware timer division.
+ *
+ * @param div clk pre-division, which is 8bits width.
+ */
+void LL_SYSCON_Timer1Division(uint8_t div);
+void LL_SYSCON_Timer2Division(uint8_t div);
+void LL_SYSCON_Timer3Division(uint8_t div);
+void LL_SYSCON_Timer4Division(uint8_t div);
+
+/**
+ * @brief Clock gate enable.
+ *
+ * @param src core clock src.
+ * @param ena 1 -- enable or 0 -- disable.
+ */
+void LL_SYSCON_CoreClockEnable(SYSCON_ClkGate_Core src, bool ena);
+
+/**
+ * @brief Get core clock enable status, 1 bit for 1 core clock.
+ *
+ * @return uint32_t ORed value, 1 bit for 1 core clock, @see SYSCON_ClkGate_Core.
+ */
+uint32_t LL_SYSCON_CoreClockStatus(void);
+
+/**
+ * @brief Peripheral clock enable.
+ * Note: call this function one time to enable one clock.
+ *
+ * @param src peripheral module.
+ * @param ena enable / disable.
+ */
+void LL_SYSCON_PeripheralClockEnable(SYSCON_ClkGate_Peripheral src, bool ena);
+
+/**
+ * @brief Get peripheral clock enable status.
+ *
+ * @return uint32_t ORed value, @see SYSCON_ClkGate_Peripheral.
+ */
+uint32_t LL_SYSCON_PeripheralClockStatus(void);
+
+/**
+ * @brief Reset peripheral module.
+ * Note: call this function one time to reset one peripheral module.
+ *
+ * @param peri @see SYSCON_SwRst_Peripheral.
+ */
+void LL_SYSCON_SoftwareResetPeripheral(SYSCON_SwRst_Peripheral peri);
+
+/**
+ * @brief Set IO function.
+ *
+ * @param af_type alternate function type, @see GPIO_AltFunctionType.
+ * @param af_io_index IO index, @see GPIO_AltFunctionIoIndex.
+ * @param en enable / disable.
+ */
+void LL_SYSCON_FuncIOSet(GPIO_AltFunctionType af_type, GPIO_AltFunctionIoIndex af_io_index, uint8_t en);
+
+/**
+ * @brief Disable all function on all configurable IO pad.
+ *
+ */
+void LL_SYSCON_FuncIODisableAll(void);
+
+/**
+ * @brief GPIO Pull Up
+ *
+ */
+void LL_SYSCON_GPIO_PullUp(GPIO_Num gpio_num);
+
+/**
+ * @brief GPIO Pull Down
+ *
+ */
+void LL_SYSCON_GPIO_PullDown(GPIO_Num gpio_num);
+
+
+/**
+ * @brief Select SPIS IO as pad.
+ *
+ * @param en 1 -- enable; 0 -- disable.
+ */
+void LL_SYSCON_SPIS_Enable(uint8_t en);
+
+/**
+ * @brief Select spim and csnX IO as pad.
+ *
+ * @param index @see SYSCON_SPIM_Index.
+ */
+void LL_SYSCON_SPIMEnable(SYSCON_SPIM_Index index);
+
+/**
+ * @brief Deselect SPIM and csnX IO as pad.
+ *
+ * @param index @see SYSCON_SPIM_Index
+ */
+void LL_SYSCON_SPIMDisable(SYSCON_SPIM_Index index);
+
+/**
+ * @brief Disable all SPIM.
+ *
+ */
+void LL_SYSCON_SPIMDisableAll(void);
+
+
+void LL_SYSCON_DigSel(uint16_t bitmap);
+
+/**
+ * @brief Select SDIO IO as pad.
+ *
+ */
+void LL_SYSCON_SDIOEnable(void);
+
+/**
+ * @brief Deselect SDIO IO as pad.
+ *
+ */
+void LL_SYSCON_SDIODisable(void);
+
+/**
+ * @brief Select SPIFlash IO as pad.
+ */
+void LL_SYSCON_SPIFlashEnable(void);
+
+/**
+ * @brief Deselect SPIFlash IO as pad.
+ */
+void LL_SYSCON_SPIFlashDisable(void);
+
+/**
+ * @brief Select I2S chnX IO as pad.
+ *
+ * @param index @see SYSCON_I2S_Index.
+ */
+void LL_SYSCON_I2SEnable(SYSCON_I2S_Index index);
+
+/**
+ * @brief Disable all I2S module.
+ *
+ */
+void LL_SYSCON_I2SDisableAll(void);
+
+/**
+ * @brief SWD enable.
+ *
+ */
+void LL_SYSCON_SWDEnable(void);
+
+/**
+ * @brief SWD disable.
+ *
+ */
+void LL_SYSCON_SWDDisable(void);
+
+/**
+ * @brief DBGH enable, set GPIO20, GPIO19 to debug host.
+ */
+void LL_SYSCON_DBGHEnable(void);
+
+/**
+ * @brief DBHG disable, set GPIO20, GPIO19 to GPIO.
+ */
+void LL_SYSCON_DBGHDisable(void);
+
+
+/**
+ * @brief Set CPU reset request mask.
+ *
+ * @param mask 1 -- mask, 0 -- not masked.
+ */
+void LL_SYSCON_CPUResetReqMask(uint8_t mask);
+
+/**
+ * @brief PHY must be reset after TxImgCal.
+ */
+void LL_SYSCON_PHY_Reset(void);
+
+
+void LL_SYSCON_RCO32K_Bitsel_Set(uint8_t bitsel);
+
+uint8_t LL_SYSCON_RCO32K_Bitsel_Get(void);
+
+void LL_SYSCON_RCO32K_Cbit_Set(uint8_t cbit);
+
+void LL_SYSCON_PMUReg_Set(uint32_t value);
+
+// FIXME: add to HAL layer.
+void LL_SYSCON_Xtal40MCap_Set(uint8_t cap);
+
+void LL_SYSCON_PMUCfg_Set(uint32_t value);
+
+void LL_SYSCON_PMUAvdd_Set(uint32_t value);
+
+void LL_SYSCON_Misc_Set(uint32_t value);
+void LL_SYSCON_EXT_INTR_Enable(SYSTEM_EXT_INT_Wakeup_Index ext_int_idx, bool enable);
+void LL_SYSCON_EXT_INTR_Set_Triggle_Condition(SYSTEM_EXT_INT_Wakeup_Index ext_int_idx, SYSTEM_EXT_INT_Triggle_Type triggle);
+uint8_t LL_SYSCON_EXT_INTR_Stat(void);
+uint8_t LL_SYSCON_EXT_INTR_Stat_Raw(void);
+void LL_SYSCON_EXT_INTR_Clear(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LL_SYSCON_H_ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_timer.h

@@ -0,0 +1,226 @@
+#ifndef __LL_TIMER_H_
+#define __LL_TIMER_H_
+
+#ifdef __cplusplus
+    extern "C" {
+#endif /* __cplusplus */
+
+#include "types.h"
+
+/**
+ * @brief Timer Index.
+ * 
+ */
+#define TIMER1  1
+#define TIMER2  2
+#define TIMER3  3
+#define TIMER4  4
+
+
+
+#define TIMER_ENABLE_BIT                _BIT(0)
+#define TIMER_MODE_BIT                  _BIT(1)
+#define TIMER_INTERRUPT_MASK_BIT        _BIT(2)
+#define TIMER_PWM_BIT                   _BIT(3)
+
+#define TIMER_ENABLE_YES                1
+#define TIMER_ENABLE_NO                 0
+
+// user-defined means "auto-reload"
+#define TIMER_MODE_USER_DEFINED         1
+// free-running means "single-shot"
+#define TIMER_MODE_FREE_RUNNING         0
+
+#define TIMER_INTERRUPT_MASK_YES        1
+#define TIMER_INTERRUPT_MASK_NO         0
+
+// FIXME: no description for Timer1PWM in the regmap?
+#define TIMER_PWM_ENABLE                1
+#define TIMER_PWM_DISABLE               0
+
+
+
+/***********************  function declaration  *****************************/
+/**
+ * @brief Get timer loadcount.
+ * 
+ * @param index timer index.
+ * @return uint32_t loadcount value.
+ */
+uint32_t LL_TIMER_LoadCount_Get(uint8_t index);
+
+
+/**
+ * @brief Set timer loadcount.
+ * 
+ * @param index timer index.
+ * @param loadcount loadcount value to be set.
+ */
+void LL_TIMER_LoadCount_Set(uint8_t index, uint32_t loadcount);
+
+
+/**
+ * @brief Get timer currentvlaue.
+ * 
+ * @param index timer index.
+ * @return uint32_t currentvalue.
+ */
+uint32_t LL_TIMER_CurrentValue_Get(uint8_t index);
+
+
+/**
+ * @brief Get timer control register value.
+ * 
+ * @param index timer index.
+ * @return uint32_t
+ */
+uint32_t LL_TIMER_Control_Get(uint8_t index);
+
+
+/**
+ * @brief Set timer control register.
+ * 
+ * @param index timer index.
+ * @param value 
+ */
+void LL_TIMER_Control_Set(uint8_t index, uint8_t value);
+
+
+/**
+ * @brief Enable/Disable timer.
+ * 
+ * @param index timer index.
+ * @param enable 
+ */
+void LL_TIMER_Enable(uint8_t index, bool enable);
+
+
+/**
+ * @brief Set timer mode, user-defined mode means "auto-reload", and free-running
+ *  mode means "singl-shot".
+ * 
+ * @param index timer index.
+ * @param mode 
+ */
+void LL_TIMER_Mode_Set(uint8_t index, uint8_t mode);
+
+
+/**
+ * @brief Set timer interrupt mask.
+ * 
+ * @param index timer index.
+ * @param mask 
+ */
+void LL_TIMER_IntMask_Set(uint8_t index, uint8_t mask);
+
+
+/**
+ * @brief Enable/Disable PWM function.
+ * 
+ * @param index
+ * @param enable 
+ */
+void LL_TIMER_PWM_Enable(uint8_t index, uint8_t enable);
+
+
+/**
+ * @brief Check whether timer is enabled or disabled.
+ * 
+ * @param index 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMER_EnableStat_Get(uint8_t index);
+
+
+/**
+ * @brief Check timer mode.
+ * 
+ * @param index 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMER_Mode_Get(uint8_t index);
+
+
+/**
+ * @brief Check timer interrupt mask.
+ * 
+ * @param index 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMER_IntMask_Get(uint8_t index);
+
+
+/**
+ * @brief Check whether timer enable PWM function or not.
+ * 
+ * @param index 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMER_PWMStat_Get(uint8_t index);
+
+
+/**
+ * @brief Clear timer interrupt.
+ * 
+ * @param index 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMER_INT_Clear(uint8_t index);
+
+
+/**
+ * @brief Get timer interrupt status.
+ * 
+ * @param index 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMER_IntStat_Get(uint8_t index);
+
+
+/**
+ * @brief Get all timer interrupt status, one bit for one timer.
+ * 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMERS_IntStat_Get( void );
+
+
+/**
+ * @brief Clear all timer interrupt.
+ * 
+ * @return uint8_t 
+ */
+void LL_TIMERS_INT_Clear( void );
+
+
+/**
+ * @brief Get the raw interrupt status of all timers.
+ * 
+ * @return uint8_t 
+ */
+uint8_t LL_TIMERS_RawIntStat_Get( void );
+
+
+/**
+ * @brief Set loadcount2 for the specified timer.
+ * 
+ * @param index timer index.
+ * @param loadcount2
+ */
+void LL_TIMER_LoadCount2_Set(uint8_t index, uint32_t loadcount2);
+
+
+/**
+ * @brief Get loadcount2 of the specified timer.
+ * 
+ * @param index timer index.
+ * @return uint32_t 
+ */
+uint32_t LL_TIMER_LoadCount2_Get(uint8_t index);
+
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __LL_TIMER_H_

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_trng.h

@@ -0,0 +1,123 @@
+#ifndef __LL_TRNG_H__
+#define __LL_TRNG_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include "types.h"
+#include "ln88xx.h"
+
+typedef     void    TRNG_Instance;
+#define     TRNG     ((TRNG_Instance *) REG_TRNG_BASE)
+
+///////////////////////////////////////////////////////////////////////////////
+//                                 TRNG_CONFIG                               //
+//                              Configuration Register                       //
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Select the length of the inverter chain in the ring oscillator.
+ *
+ * @param TRNGx
+ * @param src
+ * 0 -- shortest inverter chain length. (reset value)
+ * 1 -- short inverter chain length.
+ * 2 -- long inverter chain length.
+ * 3 -- longset inverter chain length.
+ */
+void LL_TRNG_SrcLengthCfg(TRNG_Instance *TRNGx, uint8_t srcLen);
+
+///////////////////////////////////////////////////////////////////////////////
+//                                 TRNG_VALID                                //
+//                                Valid Register                             //
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Check whether the EHR_DATA[0-5] registers contain 192 bits of valid data.
+ *
+ * @param TRNGx
+ * @return uint8_t
+ */
+uint8_t LL_TRNG_isDataReady(TRNG_Instance *TRNGx);
+
+///////////////////////////////////////////////////////////////////////////////
+//                                 EHR_DATA[0~5]                             //
+//                     Entropy Holding Register Data Registers               //
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Get TRNG data register value.
+ *
+ * @param TRNGx
+ * @param index valid index is 0~5.
+ * @return uint32_t
+ */
+uint32_t LL_TRNG_GetRandomNumber(TRNG_Instance * TRNGx, uint8_t index);
+
+///////////////////////////////////////////////////////////////////////////////
+//                               RND_SOURCE_ENABLE                           //
+//                         Random Source Enable Register                     //
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Choose the entropy source.
+ *
+ * @param TRNGx
+ * @param en
+ * 1 -- ring oscillator.
+ * 0 -- entropy source is disabled, this is the reset value.
+ */
+void LL_TRNG_Start(TRNG_Instance * TRNGx);
+
+void LL_TRNG_Stop(TRNG_Instance * TRNGx);
+
+///////////////////////////////////////////////////////////////////////////////
+//                                 SAMPLE_CNT1                               //
+//                             Sample Count Register                         //
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Config how often the TRNG samples the single output bit of the ring oscillator.
+ *
+ * @param TRNGx
+ * @param sample
+ */
+void LL_TRNG_SampleCnt_Cfg(TRNG_Instance *TRNGx, uint32_t sample);
+
+///////////////////////////////////////////////////////////////////////////////
+//                                 TRNG_SW_RESET                             //
+//                                 Reset Register                            //
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Requires an internal TRNG reset.
+ *
+ * @param TRNGx
+ */
+void LL_TRNG_Reset(TRNG_Instance *TRNGx);
+
+///////////////////////////////////////////////////////////////////////////////
+//                                 TRNG_BUSY                                 //
+//                                Busy Register                              //
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Indicates when the TRING is busy.
+ *
+ * @param TRNGx
+ * @return uint8_t
+ */
+uint8_t LL_TRNG_isBusy(TRNG_Instance *TRNGx);
+
+/**
+ * @brief [NOTE] This function must be called in order to behave normally.
+ *
+ * @param TRNGx
+ */
+void LL_TRNG_DebugDisable(TRNG_Instance *TRNGx);
+
+#ifdef __cplusplus
+    }
+#endif
+#endif // !__LL_TRNG_H__

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_uart.h

@@ -0,0 +1,463 @@
+#ifndef __LL_UART_H__
+#define __LL_UART_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif /* __cplusplus */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "ln88xx.h"
+
+typedef void UartInstance;
+#define UART0   ((UartInstance *) REG_UART0_BASE) 
+#define UART1   ((UartInstance *) REG_UART1_BASE)
+
+/////////// Do not modify this section/////////////
+#define UART_DLF_SIZE  (4)
+
+static inline uint16_t uart_divisor_integer(uint32_t bus_clk, uint32_t baudrate)
+{
+    return (uint16_t)((bus_clk/16u) / baudrate);
+}
+static inline uint8_t uart_dlf(uint32_t bus_clk, uint32_t baudrate)
+{
+    uint32_t integer1 = ((bus_clk/16u) / baudrate) * (1 << UART_DLF_SIZE);
+    float    integer2 = (float)(((float)bus_clk/16.0f)/((float)baudrate) * (1 << UART_DLF_SIZE));
+    float fractional =  integer2 - integer1;
+    return (uint8_t)(fractional + 0.5f);
+}
+////////////////////////////////////////////////////
+
+/**
+ * @brief Uart interrupt bit map
+ */
+#define LL_UART_INT_EN_RECEIVE_DATA_AVAILABLE       0x01
+#define LL_UART_INT_EN_TRANSMIT_HOLD_REG_EMPTY      0x02
+#define LL_UART_INT_EN_RECEIVER_LINE_STATUS         0x04
+#define LL_UART_INT_EN_MODEM_STATUS                 0x08
+#define LL_UART_INT_EN_PROGRAMMABLE_THRE            0x80
+
+/**
+ * @brief Rx trigger level. Above the trigger level, an uart rx interrupt will trigger. Uart Rx Fifo is 8 bytes.
+ * 
+ */
+#define LL_UART_RCVR_TRIGGER_LVL_HAS_ONE_CHARACTER     0x00
+#define LL_UART_RCVR_TRIGGER_LVL_ONE_QUARTER_FULL      0x01
+#define LL_UART_RCVR_TRIGGER_LVL_HALF_FULL             0x02
+#define LL_UART_RCVR_TRIGGER_LVL_TWO_LESS_THAN_FULL    0x03
+
+/**
+ * @brief Tx trigger level.Below the trigger level, an uart tx interrupt will trigger. Uart Tx Fifo is 8 bytes.
+ */
+#define LL_UART_TX_EMPTY_TRIGGER_LVL_EMPTY                     0x00
+#define LL_UART_TX_EMPTY_TRIGGER_LVL_TWO_CHAR_IN_FIFO          0x01
+#define LL_UART_TX_EMPTY_TRIGGER_LVL_ONE_QUARTER_FULL          0x02
+#define LL_UART_TX_EMPTY_TRIGGER_LVL_HALF_FULL                 0x03
+
+/**
+ * @brief Set Uart DMA mode
+ */
+#define LL_UART_DMA_MODE0   0x00
+#define LL_UART_DMA_MODE1   0x01
+
+/**
+ * @brief The status of the uart interrupt.
+ */
+#define LL_UART_INT_ID_MODEM_STATUS             0x00
+#define LL_UART_INT_ID_NO_INTERRUPT_PENDING     0x01
+#define LL_UART_INT_ID_THR_EMPTY                0x02
+#define LL_UART_INT_ID_RECV_DATA_AVAILABLE      0x04
+#define LL_UART_INT_ID_RECV_LINE_STATUS         0x06
+#define LL_UART_INT_ID_BUSY_DETECT              0x07
+#define LL_UART_INT_ID_CHAR_TIMEOUT             0x0C
+
+/**s
+ * @brief Data Length Select. The number of bits that may be selected are 5, 6, 7, 8bits
+ */
+#define LL_UART_DATALEN_5BIT                    0x00
+#define LL_UART_DATALEN_6BIT                    0x01
+#define LL_UART_DATALEN_7BIT                    0x02
+#define LL_UART_DATALEN_8BIT                    0x03
+
+/**
+ * @brief Select type of parity check.
+ */
+#define LL_UART_PARITY_NONE                     0x00
+#define LL_UART_PARITY_ODD                      0x01
+#define LL_UART_PARITY_EVEN                     0x02
+
+/**
+ * @brief Number of stop bits. 
+ * If set to stop_bit_1_5_OR_2 and the data bits are set to 5, one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted.
+ */
+#define LL_UART_STOP_BIT_1                      0x00
+//Note:When the UART_DATALEN is set to 5 bits, the stop bit is 1.5 bit;Otherwise,2 stop bits are transmitted. 
+#define LL_UART_STOP_BIT_1_5_OR_2               0x01
+
+
+/**
+ * @brief Select mode of flow control. When select hardware flow control, rts is controlled by hardware, otherwise controlled by software.
+ */
+#define LL_UART_FLOW_CONTROL_SOFTWARE           0x00
+#define LL_UART_FLOW_CONTROL_HARDWARE           0x01
+
+/**
+ * @brief Bitmap of line status.
+ */
+#define LL_UART_LSR_DATA_READY                  0x01
+#define LL_UART_LSR_OVERRUN_ERR                 0x02
+#define LL_UART_LSR_PARITY_ERR                  0x04
+#define LL_UART_LSR_FRAMING_ERR                 0x08
+#define LL_UART_LSR_BREAK_INT                   0x10
+#define LL_UART_LSR_TX_HOLDING_EMPTY            0x20
+#define LL_UART_LSR_TX_EMPTY                    0x40
+#define LL_UART_LSR_RECV_FIFO_ERR               0x80
+#define LL_UART_LSR_ADDR_RECEIVED               0x0100
+
+/**
+ * @brief Bitmap of Modem Status
+ */
+#define LL_UART_MODEM_STATUS_DELTA_CLEAR_TO_SEND            0x01
+#define LL_UART_MODEM_STATUS_DELTA_DATA_SET_READY           0x02
+#define LL_UART_MODEM_STATUS_TRAILING_EDGE_RING_INDICATOR   0x04
+#define LL_UART_MODEM_STATUS_DELTA_DATA_CARRIER_DETECT      0x08
+#define LL_UART_MODEM_STATUS_CLEAR_TO_SEND                  0x10
+#define LL_UART_MODEM_STATUS_DATA_SET_READY                 0x20
+#define LL_UART_MODEM_STATUS_RING_INDICATOR                 0x40
+#define LL_UART_MODEM_STATUS_DATA_CARRIER_DETECT            0x80
+
+/**
+ * @brief Bitmap of Uart normal Status
+ */
+#define LL_UART_STATUS_UART_BUSY                   0x01
+#define LL_UART_STATUS_TRANSMIT_FIFO_NOT_FULL      0x02
+#define LL_UART_STATUS_TRANSMIT_FIFO_EMPTY         0x04
+#define LL_UART_STATUS_RECEIVE_FIFO_NOT_EMPTY      0x08
+#define LL_UART_STATUS_RECEIVE_FIFO_FULL           0x10
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ * @brief Read one character from register. (not polling.)
+ * 
+ * @param UARTx 
+ * @return uint8_t the received character.
+ */
+uint8_t LL_UART_ReadChar(UartInstance *UARTx);
+
+/**
+ * @brief Send one character to register.
+ * 
+ * @param UARTx 
+ * @param ch The character to be transmitted.
+ */
+void LL_UART_WriteChar(UartInstance *UARTx, uint8_t ch);
+
+/**
+ * @brief Enbale/disable UART module
+ * 
+ * @param UARTx 
+ * @param 1:Enbale   0:disable.
+ */
+
+void LL_UART_En(UartInstance *UARTx, uint8_t value);
+
+/**
+ * @brief Set Divisor Latch Low
+ * 
+ * @param UARTx 
+ * @param value 
+ */
+void LL_UART_DLL_Set(UartInstance *UARTx, uint8_t value);
+
+/**
+ * @brief Set Divisor Latch High
+ * 
+ * @param UARTx 
+ * @param value 
+ */
+void LL_UART_DLH_Set(UartInstance *UARTx, uint8_t value);
+
+/**
+ * @brief Set Divisor Latch Fraction
+ * 
+ * @param UARTx 
+ * @param value 
+ */
+void LL_UART_DLF_Set(UartInstance *UARTx, uint8_t value);
+
+/**
+ * @brief Enalbe Received Data Available Interrupt and Character Timeout Interrupt.
+ * 
+ * @param UARTx 
+ * @param enable Enable/Disable
+ */
+void LL_UART_IT_Enable_ReceivedDataAvailable(UartInstance *UARTx, bool enable);
+
+/**
+ * @brief Enable Transmit Holding Register Empty Interrupt.
+ * 
+ * @param UARTx 
+ * @param enable 
+ */
+void LL_UART_IT_Enable_TransmitHoldingRegisterEmpty(UartInstance *UARTx, bool enable);
+
+/**
+ * @brief Enable Receiver Line Status Interrupt.
+ * 
+ * @param UARTx 
+ * @param enable 
+ */
+void LL_UART_IT_Enable_ReceiverLineStatus(UartInstance *UARTx, bool enable);
+
+/**
+ * @brief Enable Modem Status Interrupt.
+ * 
+ * @param UARTx 
+ * @param enable 
+ */
+void LL_UART_IT_Enable_ModemStatus(UartInstance *UARTx, bool enable);
+
+/**
+ * @brief Enable THRE Interrupt.
+ * 
+ * @param UARTx 
+ * @param enable 
+ */
+void LL_UART_IT_Enable_ProgramTransmitHoldingRegisterEmpty(UartInstance *UARTx, bool enable);
+
+/**
+ * @brief Enable multiple Interrupts at once.
+ * 
+ * @param UARTx 
+ * @param irq_map ORed bits, @see Uart_It_Enable
+ */
+void LL_UART_INT_Config(UartInstance *UARTx, uint8_t irq_map);
+
+/**
+ * @brief Get Interrupt ID.
+ * 
+ * @param UARTx 
+ * @return Uart_Int_Id 
+ */
+uint8_t LL_UART_GetInterruptId(UartInstance *UARTx);
+
+/**
+ * @brief Is FIFO enabled?
+ * 
+ * @param UARTx 
+ * @return true FIFO enabled.
+ * @return false FIFO disabled.
+ */
+bool LL_UART_IsFIFOEnable(UartInstance *UARTx);
+
+/**
+ * @brief FIFO control
+ * @param UARTx     [description]
+ * @param rxLvl      RCVR Trigger Level
+ * @param txLvl      TX Empty Trigger Level
+ * @param dma_mode   DMA mode
+ */
+void LL_UART_FIFO_Control(UartInstance *UARTx, uint8_t rxLvl, uint8_t txLvl, uint8_t dma_mode);
+
+/**
+ * @brief Set RX FIFO Triggler Level.
+ * 
+ * @param UARTx 
+ * @param rxLvl 
+ */
+void LL_UART_FIFO_Set_RX_TrigLvl(UartInstance *UARTx, uint8_t rxLvl);
+
+/**
+ * @brief Set TX FIFO Empty Trigger Level.
+ * 
+ * @param UARTx 
+ * @param txLvl
+ */
+void LL_UART_FIFO_Set_TX_Empty_TrigLvl(UartInstance *UARTx, uint8_t txLvl);
+
+/**
+ * Enable/Disable FIFO
+ * @param UARTx
+ * @param enable
+ */
+void LL_UART_FIFO_Enable(UartInstance *UARTx, bool enable);
+
+/**
+ * @brief Reset RX FIFO.
+ * 
+ * @param UARTx 
+ */
+void LL_UART_RX_FIFO_Reset(UartInstance *UARTx);
+
+/**
+ * @brief Reset TX FIFO.
+ * 
+ * @param UARTx 
+ */
+void LL_UART_TX_FIFO_Reset(UartInstance *UARTx);
+
+/**
+ * @brief Divisor Latch Bit set method.
+ * 
+ * @param UARTx 
+ * @param value 
+ * @return true set ok.
+ * @return false set faild.
+ */
+bool LL_UART_DLAB_Set(UartInstance *UARTx, uint8_t value);
+
+/**
+ * @brief Parity enable/disable
+ * 
+ * @param UARTx 
+ * @param enable 
+ */
+void LL_UART_Parity_Enable(UartInstance *UARTx, bool enable);
+
+/**
+ * @brief UART set Parity check even or odd.
+ * 
+ * @param UARTx 
+ * @param parity 
+ */
+void LL_UART_Parity_Set_EvenOdd(UartInstance *UARTx, uint8_t parity);
+
+/**
+ * @brief UART set stopbits.
+ * 
+ * @param UARTx 
+ * @param stopbit 
+ */
+void LL_UART_Stopbits_Set(UartInstance *UARTx, uint8_t stopbit);
+
+/**
+ * @brief UART set data length bits.
+ * 
+ * @param UARTx 
+ * @param length 
+ */
+void LL_UART_DataLenth_Set(UartInstance *UARTx, uint8_t length);
+
+/**
+ * @brief UART set auto flow control. (only UART0 supports Auto Flow Control)
+ * 
+ * @param UARTx 
+ * @param control 
+ */
+void LL_UART_FlowControl_Set(UartInstance *UARTx, uint8_t control);
+
+void LL_UART_Finish_Transfer(UartInstance *UARTx);
+
+/**
+ * @brief Get Uart Line Status. @see Uart_Line_Status.
+ * 
+ * @param UARTx 
+ * @return @see Uart_Line_Status 
+ */
+uint32_t LL_UART_GetLineStatus(UartInstance *UARTx);
+
+/**
+ * @brief Data ready in Receiver Buffer or RX FIFO.
+ * 
+ * @param UARTx 
+ * @return true  data ready.
+ * @return false data not ready.
+ */
+bool LL_UART_isDataReady(UartInstance *UARTx);
+
+/**
+ * @brief Get UART Modem Status
+ * 
+ * @param UARTx 
+ * @return uint8_t @see Uart_Modem_Status, ORed bits.
+ */
+uint8_t LL_UART_Get_Modem_Status(UartInstance *UARTx);
+
+/**
+ * @brief Set UART Low Power Divisor. (on UART0 supports Low Power)
+ * 
+ * @param UARTx 
+ * @param divisor 
+ */
+void LL_UART_Low_Power_Divisor_Set(UartInstance *UARTx, uint16_t divisor);
+
+/**
+ * @brief Get UART Low Power Divisor value. (only UART0 supports Low Power)
+ * 
+ * @param UARTx 
+ * @return uint16_t 
+ */
+uint16_t LL_UART_Low_Power_Divisor_Get(UartInstance *UARTx);
+
+/**
+ * @brief Get UART Status, value is ORed from enum Uart_Status.
+ * 
+ * @param UARTx 
+ * @return uint8_t @see Uart_Status.
+ */
+uint8_t LL_UART_Normal_Status(UartInstance *UARTx);
+
+/**
+ * @brief RX FIFO is full or not.
+ * 
+ * @param UARTx 
+ * @return true  RX FIFO is full.
+ * @return false RX FIFO is not full.
+ */
+bool LL_UART_IsRxFIFOFull(UartInstance *UARTx);
+
+/**
+ * @brief RX FIFO is not empty or not.
+ * 
+ * @param UARTx 
+ * @return true RX FIFO is not empty, has at least one character.
+ * @return false RX FIFO is empty.
+ */
+bool LL_UART_IsRxFIFONotEmpty(UartInstance *UARTx);
+
+/**
+ * @brief Transmit FIFO is empty or not.
+ * 
+ * @param UARTx 
+ * @return true TX FIFO is empty.
+ * @return false TX FIFO is not empty, has at least one character to send.
+ */
+bool LL_UART_IsTxFIFOEmpty(UartInstance *UARTx);
+
+/**
+ * @brief TX FIFO is not full.
+ * 
+ * @param UARTx 
+ * @return true TX FIFO is not full.
+ * @return false TX FIFO is full.
+ */
+bool LL_UART_IsTxFIFONotFull(UartInstance *UARTx);
+
+/**
+ * @brief UART is busy or not.
+ * 
+ * @param UARTx 
+ * @return true UART is busy.
+ * @return false UART is not busy.
+ */
+bool LL_UART_IsUARTBusy(UartInstance *UARTx);
+/**
+ * @brief Get UART RX FIFO Level.
+ * 
+ * @param UARTx 
+ * @return UART RX FIFO Level.
+ */
+
+uint8_t LL_UART_GetRxFIFOLevel(UartInstance *UARTx);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __LL_UART_H__ */

platform/vendor_bsp/LN/ln882x/include/driver_ln882x/ll/ll_wdt.h

@@ -0,0 +1,97 @@
+#ifndef __LL_WDT_H_
+#define __LL_WDT_H_
+#ifdef __cplusplus
+    extern "C" {
+#endif // __cplusplus
+
+#include "types.h"
+
+/******************************  Data Type and Macros  **********************/
+#define WDT_RESETMODE_DIRECT              0
+#define WDT_RESETMODE_IRQ                 1
+
+#define WDT_RESETPULSE_2PCLK_CYCLES       0x00
+#define WDT_RESETPULSE_4PCLK_CYCLES       0x01
+#define WDT_RESETPULSE_8PCLK_CYCLES       0x02
+#define WDT_RESETPULSE_16PCLK_CYCLES      0x03
+#define WDT_RESETPULSE_32PCLK_CYCLES      0x04
+#define WDT_RESETPULSE_64PCLK_CYCLES      0x05
+#define WDT_RESETPULSE_128PCLK_CYCLES     0x06
+#define WDT_RESETPULSE_256PCLK_CYCLES     0x07
+
+
+#define WDT_TIMEOUT_PERIOD_FF             0x00
+#define WDT_TIMEOUT_PERIOD_1FF            0x01
+#define WDT_TIMEOUT_PERIOD_3FF            0x02
+#define WDT_TIMEOUT_PERIOD_7FF            0x03
+#define WDT_TIMEOUT_PERIOD_1FFF           0x05
+#define WDT_TIMEOUT_PERIOD_3FFF           0x06
+#define WDT_TIMEOUT_PERIOD_7FFF           0x07
+#define WDT_TIMEOUT_PERIOD_FFFF           0x08
+#define WDT_TIMEOUT_PERIOD_1FFFF          0x09
+#define WDT_TIMEOUT_PERIOD_3FFFF          0x0A
+#define WDT_TIMEOUT_PERIOD_7FFFF          0x0B
+#define WDT_TIMEOUT_PERIOD_FFFFF          0x0C
+#define WDT_TIMEOUT_PERIOD_1FFFFF         0x0D
+#define WDT_TIMEOUT_PERIOD_3FFFFF         0x0E
+#define WDT_TIMEOUT_PERIOD_7FFFFF         0x0F
+
+
+/******************************  Function Declaration  **********************/
+/**
+ * @brief Enable the watch dog. Once enabled it cannot be disabled.
+ * @return This function has no return value.
+ */
+void LL_WDT_Enable(void);
+
+/**
+ * @brief Set the watch dog timeout period
+ * @param  period: the period to trigger an wdt interrupt. For example WDT_PERIOD_3FF means the period wdt int trigger is 0x3ff cycles
+ * @return This function has no return value.
+ */
+void LL_WDT_TimeoutPeriod(uint8_t period);
+
+/**
+ * @brief Clears the watchdog interrupt. This can be used to clear the interrupt without restarting the watchdog counter.
+ * @return return 1 when an interrupt is triggered.
+ */
+uint8_t LL_WDT_ClrIRQ(void);
+
+/**
+ * @brief Get the current value of the internal counter
+ * @return return the current value of the internal counter.
+ */
+uint16_t LL_WDT_CurrentCounter(void);
+
+/**
+ * @brief To restart the WDT counter (and clear WDT interrupt.)
+ * @return This function has no return value.
+ */
+void LL_WDT_Restart(void);
+
+/**
+ * @brief To get the interrupt status of the WDT.
+ * @return return the interrupt status. 0 means interrupt is inactive, 1 means interrupt is active.
+ */
+uint8_t LL_WDT_IntStatus(void);
+
+/**
+ * @brief Reset mode.
+ * 
+ * @param mode 
+ */
+void LL_WDT_ResetModeSet(uint8_t mode);
+
+/**
+ * @brief Reset pulse length.
+ * 
+ * @param pulse_width 
+ */
+void LL_WDT_ResetPulseWidthSet(uint8_t pulse_width);
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif /* __LL_WDT_H_ */
+

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_common.h

@@ -0,0 +1,76 @@
+/**
+ * @file   freertos_common.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_COMMON_H_
+#define _KERNEL_OS_FREERTOS_OS_COMMON_H_
+
+#include <stdint.h>
+#include "FreeRTOS.h"
+#include "ln88xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Thread priority definition
+ */
+typedef enum  {
+    OS_PRIORITY_IDLE            = 0,
+    OS_PRIORITY_LOW             = 1,
+    OS_PRIORITY_BELOW_NORMAL    = 2,
+    OS_PRIORITY_NORMAL          = 3,
+    OS_PRIORITY_ABOVE_NORMAL    = 4,
+    OS_PRIORITY_HIGH            = 5,
+    OS_PRIORITY_REAL_TIME       = 6
+} OS_Priority;
+
+/**
+ * @brief OS status definition
+ */
+typedef enum {
+    OS_OK           = 0,    /* success */
+    OS_FAIL         = -1,   /* general failure */
+    OS_E_NOMEM      = -2,   /* out of memory */
+    OS_E_PARAM      = -3,   /* invalid parameter */
+    OS_E_TIMEOUT    = -4,   /* operation timeout */
+    OS_E_ISR        = -5,   /* not allowed in ISR context */
+} OS_Status;
+
+/** @brief Type definition of OS time */
+typedef uint32_t OS_Time_t;
+
+#define OS_WAIT_FOREVER         0xffffffffU /* Wait forever timeout value */
+#define OS_SEMAPHORE_MAX_COUNT  0xffffffffU /* Maximum count value for semaphore */
+#define OS_INVALID_HANDLE       NULL        /* OS invalid handle */
+
+/* check if in ISR context or not */
+__STATIC_INLINE int OS_IsISRContext(void)
+{
+	return __get_IPSR();
+}
+
+/* memory */
+#include <stdlib.h>
+#define OS_Malloc(l)         pvPortMalloc(l)
+#define OS_Free(p)           vPortFree(p)
+
+#define OS_CPSR_ALLOC()
+#define OS_ENTER_CRITICAL()                       taskENTER_CRITICAL()
+#define OS_ENTER_CRITICAL_FROM_ISR()              taskENTER_CRITICAL_FROM_ISR()
+#define OS_EXIT_CRITICAL()                        taskEXIT_CRITICAL()
+#define OS_EXIT_CRITICAL_FROM_ISR(x)              taskEXIT_CRITICAL_FROM_ISR(x)
+#define OS_DISABLE_INTERRUPTS()                   taskDISABLE_INTERRUPTS()
+#define OS_ENABLE_INTERRUPTS()                    taskENABLE_INTERRUPTS()
+
+
+void OS_DefineHeapRegions(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_COMMON_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_cpuusage.h

@@ -0,0 +1,24 @@
+#ifndef _FREERTOS_CPUUSAGE_H__
+#define _FREERTOS_CPUUSAGE_H__
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#define CALCULATION_PERIOD    1000
+
+/* Exported functions ------------------------------------------------------- */
+uint16_t osGetCPUUsage (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FREERTOS_CPUUSAGE_H__ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_debug.h

@@ -0,0 +1,82 @@
+/**
+ * @file   freertos_debug.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _FREERTOS_DEBUG_H_
+#define _FREERTOS_DEBUG_H_
+
+#include <stdio.h>
+#include "utils/debug/log.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OS_DBG_ON       0
+#define OS_WARN_ON      1
+#define OS_ERR_ON       1
+#define OS_ABORT_ON     1
+
+#define OS_HANDLE_CHECK     1
+#define OS_RESOURCE_TRACE   0 /* trace OS resource or not */
+
+#if defined(__CC_ARM)
+  	
+	#define arch_fiq_enable()	    __enable_fiq()  /*Enable FIQs*/
+	#define arch_fiq_disable()	    __disable_fiq() /*Disable FIQs*/
+    #define arch_breakpoint(value)  __breakpoint(value)
+#elif defined(__GNUC__)
+	#define arch_fiq_enable()	    __asm volatile("cpsie f" : : : "memory", "cc")  /* Enable FIQs*/	
+	#define arch_fiq_disable()	    __asm volatile("cpsid f" : : : "memory", "cc")/* Disable FIQs*/
+    #define arch_breakpoint(value)  __asm volatile ("bkpt "#value)
+#endif
+
+#define sys_abort()         \
+    do {                    \
+        arch_fiq_disable(); \
+        arch_breakpoint(0); \
+    } while (0)
+
+#define OS_SYSLOG(fmt, arg...)    \
+    do {                          \
+        log_printf( fmt, ##arg);  \
+    } while (0)
+#define OS_ABORT()      sys_abort()
+#define OS_PANIC()      exception_panic(__FILE__, __func__, __LINE__)
+
+/* Define (sn)printf formatters for some types */
+#define OS_BASETYPE_F   "ld"
+#define OS_HANDLE_F     "p"
+#define OS_TIME_F       "u"
+
+#define OS_LOG(flags, fmt, arg...)  \
+    do {                            \
+        if (flags)                  \
+            OS_SYSLOG(fmt, ##arg);  \
+    } while (0)
+
+#define OS_DBG(fmt, arg...)     OS_LOG(OS_DBG_ON, "[os] "fmt, ##arg)
+#define OS_WARN(fmt, arg...)    OS_LOG(OS_WARN_ON, "[os WARN] "fmt, ##arg)
+#define OS_ERR(fmt, arg...)                         \
+    do {                                            \
+        OS_LOG(OS_ERR_ON, "[os ERR] %s():%d, "fmt,  \
+               __func__, __LINE__, ##arg);          \
+        if (OS_ABORT_ON)                            \
+            OS_ABORT();                             \
+    } while (0)
+
+#define OS_HANDLE_ASSERT(exp, handle)               \
+    if (OS_HANDLE_CHECK && !(exp)) {                \
+        OS_ERR("handle %"OS_HANDLE_F"\r\n", handle);\
+        return OS_E_PARAM;                          \
+    }
+
+extern void exception_panic(const char *file, const char *func, const int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FREERTOS_DEBUG_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_errno.h

@@ -0,0 +1,50 @@
+/**
+ * @file   freertos_errno.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_ERRNO_H_
+#define _KERNEL_OS_FREERTOS_OS_ERRNO_H_
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+#include "task.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Thread safe errno handling for FreeRTOS
+ */
+
+#if (configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0)
+
+#define OS_ERRNO_LOCATION_IDX		0
+
+/**
+ * @brief Get error number of the current thread
+ * @return Error number of the current thread
+ */
+__STATIC_INLINE int OS_GetErrno(void)
+{
+	return (int)pvTaskGetThreadLocalStoragePointer(NULL, OS_ERRNO_LOCATION_IDX);
+}
+
+/**
+ * @brief Set error number of the current thread
+ * @param[in] Error number to be set
+ * @return None
+ */
+__STATIC_INLINE void OS_SetErrno(int err)
+{
+	vTaskSetThreadLocalStoragePointer(NULL, OS_ERRNO_LOCATION_IDX, (void *)err);
+}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_ERRNO_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_mutex.h

@@ -0,0 +1,81 @@
+/**
+ * @file   freertos_mutex.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_MUTEX_H_
+#define _KERNEL_OS_FREERTOS_OS_MUTEX_H_
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+#include "./FreeRTOS_Adapter/freertos_time.h"
+#include "./FreeRTOS_Adapter/freertos_thread.h"
+#include "semphr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Mutex object definition
+ */
+typedef struct OS_Mutex {
+	SemaphoreHandle_t	handle;
+} OS_Mutex_t;
+
+OS_Status OS_MutexCreate(OS_Mutex_t *mutex);
+OS_Status OS_MutexDelete(OS_Mutex_t *mutex);
+OS_Status OS_MutexLock(OS_Mutex_t *mutex, OS_Time_t waitMS);
+OS_Status OS_MutexUnlock(OS_Mutex_t *mutex);
+
+OS_Status OS_RecursiveMutexCreate(OS_Mutex_t *mutex);
+OS_Status OS_RecursiveMutexLock(OS_Mutex_t *mutex, OS_Time_t waitMS);
+OS_Status OS_RecursiveMutexUnlock(OS_Mutex_t *mutex);
+
+/**
+ * @brief Delete the recursive mutex object
+ * @param[in] mutex Pointer to the recursive mutex object
+ * @retval OS_Status, OS_OK on success
+ */
+__STATIC_INLINE OS_Status OS_RecursiveMutexDelete(OS_Mutex_t *mutex)
+{
+	return OS_MutexDelete(mutex);
+}
+
+/**
+ * @brief Check whether the mutex object is valid or not
+ * @param[in] mutex Pointer to the mutex object
+ * @return 1 on valid, 0 on invalid
+ */
+__STATIC_INLINE int OS_MutexIsValid(OS_Mutex_t *mutex)
+{
+	return (mutex->handle != OS_INVALID_HANDLE);
+}
+
+/**
+ * @brief Set the mutex object to invalid state
+ * @param[in] mutex Pointer to the mutex object
+ * @return None
+ */
+__STATIC_INLINE void OS_MutexSetInvalid(OS_Mutex_t *mutex)
+{
+	mutex->handle = OS_INVALID_HANDLE;
+}
+
+/**
+ * @brief Get the mutex object's owner
+ * @note A mutex object's owner is a thread that locks the mutex
+ * @param[in] mutex Pointer to the mutex object
+ * @return The handle of the thread that locks the mutex object.
+ *         NULL when the mutex is not locked by any thread.
+ */
+__STATIC_INLINE OS_ThreadHandle_t OS_MutexGetOwner(OS_Mutex_t *mutex)
+{
+	return (OS_ThreadHandle_t)xSemaphoreGetMutexHolder(mutex->handle);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_MUTEX_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_queue.h

@@ -0,0 +1,111 @@
+/**
+ * @file freertos_queue.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_QUEUE_H_
+#define _KERNEL_OS_FREERTOS_OS_QUEUE_H_
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+#include "os_queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Queue object definition
+ */
+typedef struct OS_Queue {
+    QueueHandle_t   handle;
+} OS_Queue_t;
+
+OS_Status OS_QueueCreate(OS_Queue_t *queue, uint32_t queueLen, uint32_t itemSize);
+OS_Status OS_QueueDelete(OS_Queue_t *queue);
+OS_Status OS_QueueSend(OS_Queue_t *queue, const void *item, OS_Time_t waitMS);
+OS_Status OS_QueueReceive(OS_Queue_t *queue, void *item, OS_Time_t waitMS);
+OS_Status OS_QueueFlush(OS_Queue_t *queue);
+
+
+/**
+ * @brief Check whether the queue object is valid or not
+ * @param[in] queue Pointer to the queue object
+ * @return 1 on valid, 0 on invalid
+ */
+__STATIC_INLINE int OS_QueueIsValid(OS_Queue_t *queue)
+{
+	return (queue->handle != OS_INVALID_HANDLE);
+}
+
+/**
+ * @brief Set the queue object to invalid state
+ * @param[in] queue Pointer to the queue object
+ * @return None
+ */
+__STATIC_INLINE void OS_QueueSetInvalid(OS_Queue_t *queue)
+{
+	queue->handle = OS_INVALID_HANDLE;
+}
+
+/**
+ * @brief Create and initialize a message queue object
+ * @note A message queue is a queue with each data item can store a pointer.
+ *       The size of each data item (message) is equal to sizeof(void *).
+ * @param[in] queue Pointer to the message queue object
+ * @param[in] queueLen The maximum number of items that the message queue can
+ *                     hold at any one time.
+ * @retval OS_Status, OS_OK on success
+ */
+__STATIC_INLINE OS_Status OS_MsgQueueCreate(OS_Queue_t *queue, uint32_t queueLen)
+{
+	return OS_QueueCreate(queue, queueLen, sizeof(void *));
+}
+
+/**
+ * @brief Delete the message queue object
+ * @param[in] queue Pointer to the message queue object
+ * @retval OS_Status, OS_OK on success
+ */
+__STATIC_INLINE OS_Status OS_MsgQueueDelete(OS_Queue_t *queue)
+{
+	return OS_QueueDelete(queue);
+}
+
+/**
+ * @brief Send (write) a message to the back of the message queue
+ * @param[in] queue Pointer to the message queue object
+ * @param[in] msg A message, which is a pointer, to be copied into the queue
+ * @param[in] waitMS The maximum amount of time the thread should remain in the
+ *                   blocked state to wait for space to become available on the
+ *                   message queue, should the message queue already be full.
+ *                   HAL_WAIT_FOREVER for waiting forever, zero for no waiting.
+ * @retval OS_Status, OS_OK on success
+ */
+__STATIC_INLINE OS_Status OS_MsgQueueSend(OS_Queue_t *queue, void *msg, OS_Time_t waitMS)
+{
+	return OS_QueueSend(queue, &msg, waitMS);
+}
+
+/**
+ * @brief Receive (read) a message from the message queue
+ * @param[in] queue Pointer to the message queue object
+ * @param[in] msg Pointer to the message buffer into which the received message
+ *                will be copied. A message is a pointer.
+ * @param[in] waitMS The maximum amount of time the thread should remain in the
+ *                   blocked state to wait for message to become available on
+ *                   the message queue, should the message queue already be
+ *                   empty.
+ *                   HAL_WAIT_FOREVER for waiting forever, zero for no waiting.
+ * @retval OS_Status, OS_OK on success
+ */
+__STATIC_INLINE OS_Status OS_MsgQueueReceive(OS_Queue_t *queue, void **msg, OS_Time_t waitMS)
+{
+	return OS_QueueReceive(queue, msg, waitMS);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_QUEUE_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_semaphore.h

@@ -0,0 +1,55 @@
+/**
+ * @file   freertos_semaphore.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_SEMAPHORE_H_
+#define _KERNEL_OS_FREERTOS_OS_SEMAPHORE_H_
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+#include "semphr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Semaphore object definition
+ */
+typedef struct OS_Semaphore {
+    SemaphoreHandle_t   handle;
+} OS_Semaphore_t;
+
+OS_Status OS_SemaphoreCreate(OS_Semaphore_t *sem, uint32_t initCount, uint32_t maxCount);
+OS_Status OS_SemaphoreCreateBinary(OS_Semaphore_t *sem);
+OS_Status OS_SemaphoreDelete(OS_Semaphore_t *sem);
+OS_Status OS_SemaphoreWait(OS_Semaphore_t *sem, OS_Time_t waitMS);
+OS_Status OS_SemaphoreRelease(OS_Semaphore_t *sem);
+UBaseType_t OS_SemaphoreGetCount(OS_Semaphore_t *sem);
+
+/**
+ * @brief Check whether the semaphore object is valid or not
+ * @param[in] sem Pointer to the semaphore object
+ * @return 1 on valid, 0 on invalid
+ */
+__STATIC_INLINE int OS_SemaphoreIsValid(OS_Semaphore_t *sem)
+{
+	return (sem->handle != OS_INVALID_HANDLE);
+}
+
+/**
+ * @brief Set the semaphore object to invalid state
+ * @param[in] sem Pointer to the semaphore object
+ * @return None
+ */
+__STATIC_INLINE void OS_SemaphoreSetInvalid(OS_Semaphore_t *sem)
+{
+	sem->handle = OS_INVALID_HANDLE;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_SEMAPHORE_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_thread.h

@@ -0,0 +1,153 @@
+/**
+ * @file   freertos_thread.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_THREAD_H_
+#define _KERNEL_OS_FREERTOS_OS_THREAD_H_
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+#include "./FreeRTOS_Adapter/freertos_time.h"
+#include "task.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* thread priority */
+#define OS_THREAD_PRIO_SYS_CTRL OS_PRIORITY_ABOVE_NORMAL
+#define OS_THREAD_PRIO_LWIP     OS_PRIORITY_NORMAL
+#define OS_THREAD_PRIO_CONSOLE  OS_PRIORITY_REAL_TIME
+#define OS_THREAD_PRIO_APP      OS_PRIORITY_NORMAL
+
+/** @brief Thread entry definition, which is a pointer to a function */
+typedef TaskFunction_t OS_ThreadEntry_t;
+
+/** @brief Thread handle definition */
+typedef TaskHandle_t OS_ThreadHandle_t;
+
+/**
+ * @brief Thread object definition
+ */
+typedef struct OS_Thread {
+    OS_ThreadHandle_t   handle;
+} OS_Thread_t;
+
+OS_Status OS_ThreadCreate(OS_Thread_t *thread, const char *name,
+                          OS_ThreadEntry_t entry, void *arg,
+                          OS_Priority priority, uint32_t stackSize);
+OS_Status OS_ThreadDelete(OS_Thread_t *thread);
+
+/**
+ * @brief Check whether the thread object is valid or not
+ * @param[in] thread Pointer to the thread object
+ * @return 1 on valid, 0 on invalid
+ */
+__STATIC_INLINE int OS_ThreadIsValid(OS_Thread_t *thread)
+{
+	return (thread->handle != OS_INVALID_HANDLE);
+}
+
+/**
+ * @brief Set the thread object to invalid state
+ * @param[in] thread Pointer to the thread object
+ * @return None
+ */
+__STATIC_INLINE void OS_ThreadSetInvalid(OS_Thread_t *thread)
+{
+	thread->handle = OS_INVALID_HANDLE;
+}
+
+/**
+ * @brief Sleep for the given milliseconds
+ *
+ * This function causes the calling thread to sleep and block for the given
+ * milliseconds.
+ *
+ * @param[in] msec Milliseconds to sleep
+ * @return None
+ */
+__STATIC_INLINE void OS_ThreadSleep(OS_Time_t msec)
+{
+    vTaskDelay((TickType_t)OS_MSecsToTicks(msec));
+}
+
+/**
+ * @brief Yield to another thread of equal priority
+ *
+ * Yielding is where a thread volunteers to leave the running state, without
+ * being pre-empted, and before its time slice has been fully utilized.
+ *
+ * @return None
+ */
+__STATIC_INLINE void OS_ThreadYield(void)
+{
+	taskYIELD();
+}
+
+/**
+ * @brief Get the handle of the current running thread
+ * @return Handle of the current running thread
+ */
+__STATIC_INLINE OS_ThreadHandle_t OS_ThreadGetCurrentHandle(void)
+{
+	return (OS_ThreadHandle_t)xTaskGetCurrentTaskHandle();
+}
+
+/**
+ * @brief Start the thread scheduler running.
+ * @return None
+ */
+__STATIC_INLINE void OS_ThreadStartScheduler(void)
+{
+	vTaskStartScheduler();
+}
+
+/**
+ * @brief Suspend the thread scheduler
+ *
+ * Suspending the scheduler prevents a context switch from occurring but leaves
+ * interrupts enabled. If an interrupt requests a context switch while the
+ * scheduler is suspended, then the request is held pending and is performed
+ * only when the scheduler is resumed (un-suspended).
+ *
+ * @return None
+ */
+__STATIC_INLINE void OS_ThreadSuspendScheduler(void)
+{
+	vTaskSuspendAll();
+}
+
+/**
+ * @brief Resume the thread scheduler
+ *
+ * Resume scheduler activity, following a previous call to
+ * OS_ThreadSuspendScheduler(), by transitioning the scheduler into the
+ * active state from the suspended state.
+ *
+ * @return None
+ */
+__STATIC_INLINE void OS_ThreadResumeScheduler(void)
+{
+	xTaskResumeAll();
+}
+
+/**
+ * @brief Check whether the thread scheduler is running or not
+ * @return 1 on runing, 0 on not running
+ */
+__STATIC_INLINE int OS_ThreadIsSchedulerRunning(void)
+{
+	return (xTaskGetSchedulerState() == taskSCHEDULER_RUNNING);
+}
+
+#if INCLUDE_uxTaskGetStackHighWaterMark
+uint32_t OS_ThreadGetStackMinFreeSize(OS_Thread_t *thread);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_THREAD_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_time.h

@@ -0,0 +1,114 @@
+/**
+ * @file   freertos_time.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_TIME_H_
+#define _KERNEL_OS_FREERTOS_OS_TIME_H_
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+#include "task.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Parameters used to convert the time values */
+#define OS_MSEC_PER_SEC     1000U       /* milliseconds per second */
+#define OS_USEC_PER_MSEC    1000U       /* microseconds per millisecond */
+#define OS_USEC_PER_SEC     1000000U    /* microseconds per second */
+
+/* system clock's frequency, OS ticks per second */
+#define OS_HZ               configTICK_RATE_HZ
+
+/* microseconds per OS tick (1000000 / OS_HZ) */
+#define OS_TICK             (OS_USEC_PER_SEC / OS_HZ)
+
+/** @brief Get the number of ticks since OS start */
+/* Due to portTICK_TYPE_IS_ATOMIC is 1, calling xTaskGetTickCount() in ISR is
+ * safe also.
+ */
+#define OS_GetTicks()       ((uint32_t)xTaskGetTickCount())
+
+/** @brief Get the number of seconds since OS start */
+#define OS_GetTime()        (OS_GetTicks() / OS_HZ)
+
+/**
+ * @brief Macros used to convert various time units to each other
+ *     - Secs stand for seconds
+ *     - MSecs stand for milliseconds
+ *     - Ticks stand for OS ticks
+ *     - Jiffies stand for OS jiffies, which is a synonym for OS ticks
+ */
+#define OS_SecsToTicks(sec)     ((uint32_t)(sec) * OS_HZ)
+#define OS_MSecsToTicks(msec)   ((uint32_t)OS_SecsToTicks(msec) / 1000)
+#define OS_TicksToMSecs(t)      ((uint32_t)(t) / (OS_USEC_PER_MSEC / OS_TICK))
+#define OS_TicksToSecs(t)       ((uint32_t)(t) / (OS_USEC_PER_SEC / OS_TICK))
+
+#define OS_GetJiffies()         OS_GetTicks()
+#define OS_SecsToJiffies(sec)   OS_SecsToTicks(sec)
+#define OS_MSecsToJiffies(msec) OS_MSecsToTicks(msec)
+#define OS_JiffiesToMSecs(j)    OS_TicksToMSecs(j)
+#define OS_JiffiesToSecs(j)     OS_TicksToSecs(j)
+
+/**
+ * @brief Macros used to delay for the given time (milliseconds or seconds)
+ */
+#define OS_MsDelay(msec)         vTaskDelay((TickType_t)OS_MSecsToTicks(msec))
+#define OS_Delay(sec)            OS_MsDelay((sec) * OS_MSEC_PER_SEC)
+#define OS_SecDelay(sec)         OS_Delay(sec)
+
+/**s
+ * @brief Macros used to compare time values
+ *
+ *  These inlines deal with timer wrapping correctly. You are
+ *  strongly encouraged to use them
+ *  1. Because people otherwise forget
+ *  2. Because if the timer wrap changes in future you won't have to
+ *     alter your code.
+ *
+ * OS_TimeAfter(a,b) returns true if the time a is after time b.
+ *
+ * Do this with "<0" and ">=0" to only test the sign of the result. A
+ * good compiler would generate better code (and a really good compiler
+ * wouldn't care). Gcc is currently neither.
+ */
+#define OS_TimeAfter(a, b)              ((int32_t)(b) - (int32_t)(a) < 0)
+#define OS_TimeBefore(a, b)             OS_TimeAfter(b, a)
+#define OS_TimeAfterEqual(a, b)         ((int32_t)(a) - (int32_t)(b) >= 0)
+#define OS_TimeBeforeEqual(a, b)        OS_TimeAfterEqual(b, a)
+
+/** @brief Macros used to generate fake random 32-bit value */
+/* The fake random 32-bit value is generated by combining OS ticks and
+ * the value of SysTick current value register.
+ */
+#define OS_Rand32()                                                 \
+    ((uint32_t)(((*((volatile uint32_t *)0xE000E018)) & 0xffffff) | (OS_GetTicks() << 24)))
+
+__STATIC_INLINE TickType_t OS_CalcWaitTicks(OS_Time_t msec)
+{
+	TickType_t tick;
+	if (msec == OS_WAIT_FOREVER) 
+	{
+		tick = portMAX_DELAY;
+	} 
+	else if (msec != 0) 
+	{
+		tick = OS_MSecsToTicks(msec);
+		if (tick == 0){
+			tick = 1;
+		}			
+	}
+	else 
+	{
+		tick = 0;
+	}
+	return tick;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_TIME_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/FreeRTOS_Adapter/freertos_timer.h

@@ -0,0 +1,107 @@
+/**
+ * @file   freertos_timer.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_TIMER_H_
+#define _KERNEL_OS_FREERTOS_OS_TIMER_H_
+
+#include "./FreeRTOS_Adapter/freertos_common.h"
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (defined(configUSE_TIMER_ID_AS_CALLBACK_ARG) && configUSE_TIMER_ID_AS_CALLBACK_ARG == 1)
+  #define OS_TIMER_USE_FREERTOS_ORIG_CALLBACK	0
+#else
+  #define OS_TIMER_USE_FREERTOS_ORIG_CALLBACK	1
+#endif
+
+/**
+ * @brief Timer type definition
+ *     - one shot timer: Timer will be in the dormant state after it expires.
+ *     - periodic timer: Timer will auto-reload after it expires.
+ */
+typedef enum {
+    OS_TIMER_ONCE       = 0, /* one shot timer */
+    OS_TIMER_PERIODIC   = 1  /* periodic timer */
+} OS_TimerType;
+
+/** @brief Timer expire callback function definition */
+typedef void (*OS_TimerCallback_t)(void *arg);
+
+/** @brief Timer handle definition */
+typedef TimerHandle_t OS_TimerHandle_t;
+
+#if OS_TIMER_USE_FREERTOS_ORIG_CALLBACK
+/**
+ * @brief Timer expire callback data definition
+ */
+typedef struct OS_TimerCallbackData {
+    OS_TimerCallback_t  callback;   /* Timer expire callback function */
+    void                *argument;  /* Argument of timer expire callback function */
+} OS_TimerCallbackData_t;
+#endif
+
+/**
+ * @brief Timer object definition
+ */
+typedef struct OS_Timer {
+    TimerHandle_t           handle;
+#if OS_TIMER_USE_FREERTOS_ORIG_CALLBACK
+    OS_TimerCallbackData_t  *priv;	/* private data for internally usage */
+#endif
+} OS_Timer_t;
+
+
+OS_Status OS_TimerCreate(OS_Timer_t *timer, OS_TimerType type,
+                         OS_TimerCallback_t cb, void *arg, OS_Time_t periodMS);
+OS_Status OS_TimerDelete(OS_Timer_t *timer);
+OS_Status OS_TimerStart(OS_Timer_t *timer);
+OS_Status OS_TimerChangePeriod(OS_Timer_t *timer, OS_Time_t periodMS);
+OS_Status OS_TimerStop(OS_Timer_t *timer);
+
+/**
+ * @brief Check whether the timer object is valid or not
+ * @param[in] timer Pointer to the timer object
+ * @return 1 on valid, 0 on invalid
+ */
+__STATIC_INLINE int OS_TimerIsValid(OS_Timer_t *timer)
+{
+	return (timer->handle != OS_INVALID_HANDLE);
+}
+
+/**
+ * @brief Set the timer object to invalid state
+ * @param[in] timer Pointer to the timer object
+ * @return None
+ */
+__STATIC_INLINE void OS_TimerSetInvalid(OS_Timer_t *timer)
+{
+	timer->handle = OS_INVALID_HANDLE;
+}
+
+/**
+ * @brief Check whether the timer is active or not
+ *
+ * A timer is inactive when it is in one of the following cases:
+ *     - The timer has been created, but not started.
+ *     - The timer is a one shot timer that has not been restarted since it
+ *       expired.
+ *
+ * @param[in] timer Pointer to the timer object
+ * @return 1 on active, 0 on inactive
+ */
+__STATIC_INLINE int OS_TimerIsActive(OS_Timer_t *timer)
+{
+	return (xTimerIsTimerActive(timer->handle) != pdFALSE);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_TIMER_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_common.h

@@ -0,0 +1,79 @@
+/**
+ * @file   freertos_common.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_COMMON_H_
+#define _KERNEL_OS_FREERTOS_OS_COMMON_H_
+
+#include <stdint.h>
+//#include "compiler.h"
+#include "tos_k.h"
+#include "ln88xx.h"
+
+#define __always_inline	__forceinline
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Thread priority definition
+ */
+typedef enum  {
+    OS_PRIORITY_IDLE            = 6,
+    OS_PRIORITY_LOW             = 5,
+    OS_PRIORITY_BELOW_NORMAL    = 4,
+    OS_PRIORITY_NORMAL          = 3,
+    OS_PRIORITY_ABOVE_NORMAL    = 2,
+    OS_PRIORITY_HIGH            = 1,
+    OS_PRIORITY_REAL_TIME       = 0
+} OS_Priority;
+
+/**
+ * @brief OS status definition
+ */
+typedef enum {
+    OS_OK           = 0,    /* success */
+    OS_FAIL         = -1,   /* general failure */
+    OS_E_NOMEM      = -2,   /* out of memory */
+    OS_E_PARAM      = -3,   /* invalid parameter */
+    OS_E_TIMEOUT    = -4,   /* operation timeout */
+    OS_E_ISR        = -5,   /* not allowed in ISR context */
+} OS_Status;
+
+/** @brief Type definition of OS time */
+typedef uint32_t OS_Time_t;
+
+#define OS_WAIT_FOREVER         0xffffffffU /* Wait forever timeout value */
+#define OS_SEMAPHORE_MAX_COUNT  0xffffU /* Maximum count value for semaphore */
+
+/* check if in ISR context or not */
+static __always_inline int OS_IsISRContext(void)
+{
+	return __get_IPSR();
+}
+
+
+
+/* memory */
+#include <stdlib.h>
+void * OS_Malloc(size_t size);
+void OS_Free(void *p);
+
+//#define OS_Memcpy(d, s, l) 
+//#define OS_Memset(d, c, l) 
+//#define OS_Memcmp(a, b, l) 
+//#define OS_Memmove(d, s, n)
+
+void os_heap_mem_add_pool(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_COMMON_H_ */
+
+

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_cpuusage.h

@@ -0,0 +1,24 @@
+#ifndef _FREERTOS_CPUUSAGE_H__
+#define _FREERTOS_CPUUSAGE_H__
+
+#include "./TencentOS_Adapter/tos_common.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#define CALCULATION_PERIOD    1000
+
+/* Exported functions ------------------------------------------------------- */
+uint16_t osGetCPUUsage (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FREERTOS_CPUUSAGE_H__ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_debug.h

@@ -0,0 +1,85 @@
+/**
+ * @file   freertos_debug.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _FREERTOS_DEBUG_H_
+#define _FREERTOS_DEBUG_H_
+
+#include <stdio.h>
+//#include "compiler.h"
+#include "utils/debug/log.h"
+    
+#define __always_inline	__forceinline
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OS_DBG_ON       0
+#define OS_WARN_ON      1
+#define OS_ERR_ON       1
+#define OS_ABORT_ON     1
+
+#define OS_HANDLE_CHECK     1
+#define OS_RESOURCE_TRACE   0 /* trace OS resource or not */
+
+#if defined(__CC_ARM)
+  	
+	#define arch_fiq_enable()	    __enable_fiq()  /*Enable FIQs*/
+	#define arch_fiq_disable()	    __disable_fiq() /*Disable FIQs*/
+    #define arch_breakpoint(value)  __breakpoint(value)
+#elif defined(__GNUC__)
+	#define arch_fiq_enable()	    __asm volatile("cpsie f" : : : "memory", "cc")  /* Enable FIQs*/	
+	#define arch_fiq_disable()	    __asm volatile("cpsid f" : : : "memory", "cc")/* Disable FIQs*/
+    #define arch_breakpoint(value)  __asm volatile ("bkpt "#value)
+#endif
+
+#define sys_abort()         \
+    do {                    \
+        arch_fiq_disable(); \
+        arch_breakpoint(0); \
+    } while (0)
+
+#define OS_SYSLOG(fmt, arg...)    \
+    do {                          \
+        LOG(LOG_LVL_INFO, fmt, ##arg);  \
+    } while (0)
+#define OS_ABORT()      sys_abort()
+#define OS_PANIC()      exception_panic(__FILE__, __func__, __LINE__)
+
+/* Define (sn)printf formatters for some types */
+#define OS_BASETYPE_F   "ld"
+#define OS_HANDLE_F     "p"
+#define OS_TIME_F       "u"
+
+#define OS_LOG(flags, fmt, arg...)  \
+    do {                            \
+        if (flags)                  \
+            OS_SYSLOG(fmt, ##arg);  \
+    } while (0)
+
+#define OS_DBG(fmt, arg...)     OS_LOG(OS_DBG_ON, "[os] "fmt, ##arg)
+#define OS_WARN(fmt, arg...)    OS_LOG(OS_WARN_ON, "[os WARN] "fmt, ##arg)
+#define OS_ERR(fmt, arg...)                         \
+    do {                                            \
+        OS_LOG(OS_ERR_ON, "[os ERR] %s():%d, "fmt,  \
+               __func__, __LINE__, ##arg);          \
+        if (OS_ABORT_ON)                            \
+            OS_ABORT();                             \
+    } while (0)
+
+#define OS_HANDLE_ASSERT(exp, handle)               \
+    if (OS_HANDLE_CHECK && !(exp)) {                \
+        OS_ERR("handle %"OS_HANDLE_F"\r\n", handle);\
+        return OS_E_PARAM;                          \
+    }
+
+extern void exception_panic(const char *file, const char *func, const int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FREERTOS_DEBUG_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_errno.h

@@ -0,0 +1,42 @@
+/**
+ * @file   freertos_errno.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_ERRNO_H_
+#define _KERNEL_OS_FREERTOS_OS_ERRNO_H_
+
+#include "./TencentOS/adapter_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * @brief Get error number of the current thread
+ * @return Error number of the current thread
+ */
+static __always_inline int OS_GetErrno(void)
+{
+
+}
+
+/**
+ * @brief Set error number of the current thread
+ * @param[in] Error number to be set
+ * @return None
+ */
+static __always_inline void OS_SetErrno(int err)
+{
+
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_ERRNO_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_mutex.h

@@ -0,0 +1,64 @@
+/**
+ * @file   freertos_mutex.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_MUTEX_H_
+#define _KERNEL_OS_FREERTOS_OS_MUTEX_H_
+
+#include "./TencentOS_Adapter/TencentOS_common.h"
+#include "./TencentOS_Adapter/TencentOS_time.h"
+#include "./TencentOS_Adapter/TencentOS_thread.h"
+#include "tos_k.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef k_mutex_t * OS_MutexHandle;
+
+typedef struct OS_Mutex {
+	k_mutex_t * handle;
+} OS_Mutex_t;
+
+
+OS_Status OS_MutexCreate(OS_Mutex_t *mutex);
+OS_Status OS_MutexDelete(OS_Mutex_t *mutex);
+OS_Status OS_MutexLock(OS_Mutex_t *mutex, OS_Time_t waitMS);
+OS_Status OS_MutexUnlock(OS_Mutex_t *mutex);
+
+static __always_inline OS_Status OS_RecursiveMutexCreate(OS_Mutex_t *mutex){
+    return OS_MutexCreate(mutex);
+};
+static __always_inline OS_Status OS_RecursiveMutexDelete(OS_Mutex_t *mutex){
+	return OS_MutexDelete(mutex);
+};
+
+static __always_inline OS_Status OS_RecursiveMutexLock(OS_Mutex_t *mutex, OS_Time_t waitMS){
+    return OS_MutexLock(mutex,waitMS);
+};
+
+static __always_inline OS_Status OS_RecursiveMutexUnlock(OS_Mutex_t *mutex){
+    return OS_MutexUnlock(mutex);
+};
+
+OS_ThreadHandle  OS_MutexGetOwner(OS_Mutex_t *mutex);
+
+static __always_inline int OS_MutexIsValid(OS_Mutex_t *mutex)
+{
+	return ((mutex->handle != NULL) && (mutex->handle->knl_obj.type == KNL_OBJ_TYPE_MUTEX));
+}
+
+static __always_inline void OS_MutexSetInvalid(OS_Mutex_t *mutex)
+{
+	mutex->handle->knl_obj.type == KNL_OBJ_TYPE_NONE;
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_MUTEX_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_queue.h

@@ -0,0 +1,55 @@
+/**
+ * @file freertos_queue.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_QUEUE_H_
+#define _KERNEL_OS_FREERTOS_OS_QUEUE_H_
+
+#include "./TencentOS_Adapter/TencentOS_common.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef k_msg_q_t * OS_QueueHandle;
+    
+typedef struct OS_Queue {
+    k_mail_q_t * handle;
+} OS_Queue_t;
+
+typedef struct OS_MsgQueue {
+    k_msg_q_t * handle;
+} OS_MsgQueue_t;
+
+OS_Status OS_QueueCreate(OS_Queue_t *queue, uint32_t queueLen, uint32_t itemSize);
+OS_Status OS_QueueDelete(OS_Queue_t *queue);
+OS_Status OS_QueueSend(OS_Queue_t *queue, const void *item, OS_Time_t waitMS);
+OS_Status OS_QueueReceive(OS_Queue_t *queue, void *item, OS_Time_t waitMS);
+
+
+OS_Status OS_MsgQueueCreate(OS_MsgQueue_t *queue, uint32_t queueLen);
+OS_Status OS_MsgQueueDelete(OS_MsgQueue_t *queue);
+OS_Status OS_MsgQueueSend(OS_MsgQueue_t *queue, void *msg, OS_Time_t waitMS);
+OS_Status OS_MsgQueueReceive(OS_MsgQueue_t *queue, void **msg, OS_Time_t waitMS);
+
+
+static __always_inline int OS_MsgQueueIsValid(OS_MsgQueue_t *queue)
+{
+	return ((queue->handle != NULL) && (queue->handle->knl_obj.type == KNL_OBJ_TYPE_MESSAGE_QUEUE));
+}
+
+static __always_inline void OS_MsgQueueSetInvalid(OS_MsgQueue_t *queue)
+{
+	queue->handle->knl_obj.type = KNL_OBJ_TYPE_NONE;
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_QUEUE_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_semaphore.h

@@ -0,0 +1,45 @@
+/**
+ * @file   freertos_semaphore.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_SEMAPHORE_H_
+#define _KERNEL_OS_FREERTOS_OS_SEMAPHORE_H_
+
+#include "./TencentOS_Adapter/TencentOS_common.h"
+#include "tos_k.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef k_sem_t * OS_SemaphoreHandle;
+
+typedef struct OS_Semaphore {
+    k_sem_t * handle;
+} OS_Semaphore_t;
+
+OS_Status OS_SemaphoreCreate(OS_Semaphore_t *sem, uint32_t initCount, uint32_t maxCount);
+OS_Status OS_SemaphoreCreateBinary(OS_Semaphore_t *sem);
+OS_Status OS_SemaphoreDelete(OS_Semaphore_t *sem);
+OS_Status OS_SemaphoreWait(OS_Semaphore_t *sem, OS_Time_t waitMS);
+OS_Status OS_SemaphoreRelease(OS_Semaphore_t *sem);
+uint16_t  OS_SemaphoreGetCount(OS_Semaphore_t *sem);
+
+static __always_inline int OS_SemaphoreIsValid(OS_Semaphore_t *sem)
+{
+	return ((sem->handle != NULL) && (sem->handle->knl_obj.type == KNL_OBJ_TYPE_SEMAPHORE));
+}
+
+static __always_inline void OS_SemaphoreSetInvalid(OS_Semaphore_t *sem)
+{
+	sem->handle->knl_obj.type = KNL_OBJ_TYPE_NONE;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_SEMAPHORE_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_thread.h

@@ -0,0 +1,77 @@
+/**
+ * @file   freertos_thread.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_THREAD_H_
+#define _KERNEL_OS_FREERTOS_OS_THREAD_H_
+
+#include "./TencentOS_Adapter/TencentOS_common.h"
+#include "./TencentOS_Adapter/TencentOS_time.h"
+#include "tos_k.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* thread priority */
+#define OS_THREAD_PRIO_SYS_CTRL OS_PRIORITY_ABOVE_NORMAL
+#define OS_THREAD_PRIO_LWIP     OS_PRIORITY_NORMAL
+#define OS_THREAD_PRIO_CONSOLE  OS_PRIORITY_ABOVE_NORMAL
+#define OS_THREAD_PRIO_APP      OS_PRIORITY_NORMAL
+
+typedef k_task_entry_t OS_ThreadEntry_t;
+typedef k_task_t     * OS_ThreadHandle;
+
+typedef struct OS_Thread {
+    k_task_t * handle;
+} OS_Thread_t;
+
+
+OS_Status OS_ThreadCreateTimeslice(OS_Thread_t *thread, const char *name, OS_ThreadEntry_t entry, \
+                           void *arg, OS_Priority priority, uint32_t stackSize, uint32_t timeslice);
+
+static __always_inline  OS_Status OS_ThreadCreate(OS_Thread_t *thread, const char *name,
+                                                  OS_ThreadEntry_t entry, void *arg,
+                                                  OS_Priority priority, uint32_t stackSize)
+{
+    return OS_ThreadCreateTimeslice(thread,name,entry,arg,priority,stackSize,0u);
+}
+
+OS_Status OS_ThreadDelete(OS_Thread_t *thread);
+
+
+static __always_inline int OS_ThreadIsValid(OS_Thread_t *thread)
+{
+	return ((thread->handle != NULL) && (thread->handle->state != K_TASK_STATE_DELETED));
+}
+
+
+static __always_inline void OS_ThreadYield(void)
+{
+	tos_task_yield();
+}
+
+static __always_inline void OS_ThreadSuspendScheduler(void)
+{
+    tos_knl_sched_lock();
+}
+static __always_inline void OS_ThreadResumeScheduler(void)
+{
+    tos_knl_sched_unlock();
+}
+
+
+//0 = kernel is not running. Non-0  = kernel is running.
+static __always_inline int OS_ThreadIsSchedulerRunning(void)
+{
+	return tos_knl_is_running();
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_THREAD_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_time.h

@@ -0,0 +1,80 @@
+/**
+ * @file   freertos_time.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_TIME_H_
+#define _KERNEL_OS_FREERTOS_OS_TIME_H_
+
+#include "./TencentOS_Adapter/TencentOS_common.h"
+#include "tos_k.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef k_tick_t TickType_t;
+
+/* Parameters used to convert the time values */
+#define OS_MSEC_PER_SEC     1000U       /* milliseconds per second */
+#define OS_USEC_PER_MSEC    1000U       /* microseconds per millisecond */
+#define OS_USEC_PER_SEC     1000000U    /* microseconds per second */
+
+/* system clock's frequency, OS ticks per second */
+#define OS_HZ               TOS_CFG_CPU_TICK_PER_SECOND
+
+/* microseconds per OS tick (1000000 / OS_HZ) */
+#define OS_TICK             (OS_USEC_PER_SEC / OS_HZ)
+
+/** @brief Get the number of ticks since OS start */
+/* Due to portTICK_TYPE_IS_ATOMIC is 1, calling xTaskGetTickCount() in ISR is
+ * safe also.
+ */
+#define OS_GetTicks()       ((TickType_t)tos_systick_get())
+
+/** @brief Get the number of seconds since OS start */
+#define OS_GetTime()        (OS_GetTicks() / OS_HZ)
+
+
+#define OS_SecsToTicks(sec)     ((uint32_t)(sec) * OS_HZ)
+#define OS_MSecsToTicks(msec)   ((uint32_t)(msec) * (OS_USEC_PER_MSEC / OS_TICK))
+
+#define OS_TicksToMSecs(t)      ((TickType_t)((t) / (OS_USEC_PER_MSEC / OS_TICK)))
+#define OS_TicksToSecs(t)       ((TickType_t)((t) / (OS_USEC_PER_SEC  / OS_TICK)))
+
+
+#define OS_MsDelay(msec)         tos_task_delay((TickType_t)OS_MSecsToTicks(msec))
+#define OS_Delay(sec)            OS_MsDelay((sec) * OS_MSEC_PER_SEC)
+#define OS_SecDelay(sec)         OS_Delay(sec)
+
+
+#define OS_Rand32()  ((uint32_t)(((*((volatile uint32_t *)0xE000E018)) & 0xffffff) | (OS_GetTicks() << 24)))
+
+static __always_inline TickType_t OS_CalcWaitTicks(OS_Time_t msec)
+{
+	TickType_t tick;
+	if (msec == OS_WAIT_FOREVER) 
+	{
+		tick = TOS_TIME_FOREVER;
+	} 
+	else if (msec != 0) 
+	{
+		tick = OS_MSecsToTicks(msec);
+		if (tick == 0){
+			tick = 1;
+		}			
+	}
+	else 
+	{
+		tick = TOS_TIME_NOWAIT;
+	}
+	return tick;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_TIME_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/TencentOS_Adapter/TencentOS_timer.h

@@ -0,0 +1,43 @@
+/**
+ * @file   freertos_timer.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef _KERNEL_OS_FREERTOS_OS_TIMER_H_
+#define _KERNEL_OS_FREERTOS_OS_TIMER_H_
+
+#include "./TencentOS_Adapter/TencentOS_common.h"
+#include "tos_k.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    OS_TIMER_ONCE       = 0, /* one shot timer */
+    OS_TIMER_PERIODIC   = 1  /* periodic timer */
+} OS_TimerType;
+
+typedef k_timer_callback_t OS_TimerCallback_t;
+typedef k_timer_t        * OS_TimerHandle;
+
+typedef struct OS_Timer {
+    k_timer_t * handle;
+} OS_Timer_t;
+
+
+OS_Status OS_TimerCreate(OS_Timer_t *timer, OS_TimerType type,OS_TimerCallback_t cb, void *arg, OS_Time_t periodMS);
+OS_Status OS_TimerDelete(OS_Timer_t *timer);
+OS_Status OS_TimerStart(OS_Timer_t *timer);
+OS_Status OS_TimerChangeDelay( OS_Timer_t *timer, OS_Time_t periodMS);
+OS_Status OS_TimerChangePeriod(OS_Timer_t *timer, OS_Time_t periodMS);
+OS_Status OS_TimerStop(OS_Timer_t *timer);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _KERNEL_OS_FREERTOS_OS_TIMER_H_ */

platform/vendor_bsp/LN/ln882x/include/kernel/osal/osal.h

@@ -0,0 +1,37 @@
+/**
+ * @file   osal.h
+ * @author LightningSemi WLAN Team
+ * Copyright (C) 2018 LightningSemi Technology Co., Ltd. All rights reserved.
+ */
+
+#ifndef __OSAL_H__
+#define __OSAL_H__
+#include "proj_config.h"
+
+#if (__CONFIG_OS_KERNEL == RTOS_FREERTOS)
+  #include "./FreeRTOS/adapter_common.h"
+  #include "./FreeRTOS/adapter_cpuusage.h"
+  #include "./FreeRTOS/adapter_errno.h"
+  #include "./FreeRTOS/adapter_mutex.h"
+  #include "./FreeRTOS/adapter_queue.h"
+  #include "./FreeRTOS/adapter_semaphore.h"
+  #include "./FreeRTOS/adapter_thread.h"
+  #include "./FreeRTOS/adapter_time.h"
+  #include "./FreeRTOS/adapter_timer.h"
+#elif (__CONFIG_OS_KERNEL == RTOS_TENCENT_OS)
+  #include "./TencentOS_Adapter/TencentOS_common.h"
+//  #include "./TencentOS_Adapter/TencentOS_cpuusage.h"
+//  #include "./TencentOS_Adapter/TencentOS_errno.h"
+  #include "./TencentOS_Adapter/TencentOS_mutex.h"
+  #include "./TencentOS_Adapter/TencentOS_queue.h"
+  #include "./TencentOS_Adapter/TencentOS_semaphore.h"
+  #include "./TencentOS_Adapter/TencentOS_thread.h"
+  #include "./TencentOS_Adapter/TencentOS_time.h"
+  #include "./TencentOS_Adapter/TencentOS_timer.h"
+#elif (__CONFIG_OS_KERNEL == RTOS_RT_THREAD)
+  #error "No OS Kernel defined!"
+#else 
+  #error "No OS Kernel defined!"
+#endif
+
+#endif /* __OSAL_H__ */

platform/vendor_bsp/LN/ln882x/include/net/SmartConfig/sc_decode.h

@@ -0,0 +1,30 @@
+
+#ifndef __SC_DECODE_H__
+#define __SC_DECODE_H__
+
+#include "types.h"
+
+typedef enum {
+	SC_END     = 0,
+	SC_SEARCH_CHAN,
+	SC_LOCKED_CHAN,
+	SC_COMPLETED,
+} decode_status_enum_t;
+
+
+typedef struct {
+	int channel;
+	uint8_t lead_complete_flag;
+} sc_lead_code_t;
+
+
+typedef struct {
+	sc_lead_code_t   lead_code;
+	decode_status_enum_t sc_ctrl;
+	decode_status_enum_t Sc_Status;
+} sc_private_t;
+
+decode_status_enum_t packet_deoced(sc_private_t *sc_priv, uint8_t *data, uint16_t total_len);
+uint16_t sc_read_locked_channel(sc_private_t *sc_priv);
+
+#endif /* __SC_DECODE_H__ */

platform/vendor_bsp/LN/ln882x/include/net/SmartConfig/smartconfig.h

@@ -0,0 +1,32 @@
+
+#ifndef _WIFI_SMART_CONFIG_H
+#define _WIFI_SMART_CONFIG_H
+#include "types.h"
+
+/**
+ * @brief WLAN SSID and passphrase definition
+ */
+#define WLAN_SSID_MAX_LEN         32
+#define WLAN_PASSWORD_MIN_LEN     8
+#define WLAN_PASSWORD_MAX_LEN     63
+
+typedef enum {
+    SMART_CONFIG_SUCCESS =  0, /* success */
+    SMART_CONFIG_FAIL    = -1, /* general error */
+    SMART_CONFIG_TIMEOUT = -2, /* wait timeout */
+    SMART_CONFIG_INVALID = -3, /* invalid argument */
+} smartconfig_status_t;
+
+typedef struct{
+    uint8_t ssid[WLAN_SSID_MAX_LEN];
+    uint8_t ssid_len;
+    uint8_t passphrase[WLAN_PASSWORD_MAX_LEN + 1]; /* ASCII string ending with '\0' */
+    uint8_t random_num;
+} smartconfig_result_t;
+
+
+int wlan_smart_config_stop(void);
+
+
+#endif
+

platform/vendor_bsp/LN/ln882x/include/net/dflt_param_tab.h

@@ -0,0 +1,88 @@
+
+#ifndef _DFLT_PARAM_TAB_H_
+#define _DFLT_PARAM_TAB_H_
+#include "wifi/wifi.h"
+
+//TODO: Get these static parameters from flash.
+#define WIFI_MODE_DEFAULT               WIFI_MODE_STATION
+#define WIFI_AP_SSID_DEFAULT            "LN8826"
+#define WIFI_AP_PASSWORD_DEFAULT        "12345678"
+#define WIFI_AP_CHANNEL_DEFAULT         7
+#define WIFI_AP_AUTH_MODE_DEFAULT       WIFI_AUTH_OPEN
+#define WIFI_AP_SSID_HIDDEN_DEFAULT     0
+#define WIFI_AP_MAX_CONNECTION_DEFAULT  3
+#define WIFI_AP_BEACON_INTERVAL_DEFAULT 100
+
+
+/**<  Config sta modle network card default parameters*/
+/**<  static IP*/
+#define STA_IP_ADDR0         192
+#define STA_IP_ADDR1         168
+#define STA_IP_ADDR2         1
+#define STA_IP_ADDR3         20
+
+/**< Subnet mask*/
+#define STA_NETMASK_ADDR0    255
+#define STA_NETMASK_ADDR1    255
+#define STA_NETMASK_ADDR2    255
+#define STA_NETMASK_ADDR3    0
+
+/**<  GateWay*/
+#define STA_GW_ADDR0         192
+#define STA_GW_ADDR1         168
+#define STA_GW_ADDR2         1
+#define STA_GW_ADDR3         1
+
+/**<  MAC Addr*/
+#define STA_MAC_ADDR0        0x00
+#define STA_MAC_ADDR1        0x50
+#define STA_MAC_ADDR2        0xC2
+#define STA_MAC_ADDR3        0x5E
+#define STA_MAC_ADDR4        0x10
+#define STA_MAC_ADDR5        0x8D
+
+
+/**<  Config softAP modle network card default parameters*/
+/**<  static IP*/
+#define AP_IP_ADDR0          192
+#define AP_IP_ADDR1          168
+#define AP_IP_ADDR2          1
+#define AP_IP_ADDR3          1
+                             
+/**< Subnet mask*/           
+#define AP_NETMASK_ADDR0     255
+#define AP_NETMASK_ADDR1     255
+#define AP_NETMASK_ADDR2     255
+#define AP_NETMASK_ADDR3     0
+                             
+/**<  GateWay*/              
+#define AP_GW_ADDR0          192
+#define AP_GW_ADDR1          168
+#define AP_GW_ADDR2          1
+#define AP_GW_ADDR3          1
+                             
+/**<  MAC Addr*/             
+#define AP_MAC_ADDR0         STA_MAC_ADDR0
+#define AP_MAC_ADDR1         STA_MAC_ADDR1
+#define AP_MAC_ADDR2         STA_MAC_ADDR2
+#define AP_MAC_ADDR3         STA_MAC_ADDR3
+#define AP_MAC_ADDR4         STA_MAC_ADDR4
+#define AP_MAC_ADDR5         0x8B
+
+
+
+/* Config DHCP server default param*/
+#define DHCPD_IP_LEASE_TIME             (2880)
+#define DHCPD_IP_RENEW_TIME             (2880)
+#define DHCPD_LISTEN_PORT               (67)
+#define DHCPD_CLIENT_MAX                (WIFI_AP_MAX_CONNECTION_DEFAULT)
+#define DHCPD_IP_START                  ((100 << 24)|(AP_IP_ADDR2 << 16)|(AP_IP_ADDR1 << 8)|AP_IP_ADDR0)
+#define DHCPD_IP_END                    ((102 << 24)|(AP_IP_ADDR2 << 16)|(AP_IP_ADDR1 << 8)|AP_IP_ADDR0)
+
+
+#define STA_IFNAME                      "st"
+#define AP_IFNAME                       "ap"
+#define STA_HOSTNAME                    "wifi_sta"
+#define AP_HOSTNAME                     "wifi_ap"
+
+#endif

platform/vendor_bsp/LN/ln882x/include/net/dhcpd/dhcp_packet.h

@@ -0,0 +1,168 @@
+#ifndef __DHCP_PACKET_H__
+#define __DHCP_PACKET_H__
+/** DHCP BOOTP CODES **/
+#define BOOT_REQUEST	1
+#define BOOT_REPLY		2
+
+/** DHCP HTYPE CODE **/
+#define HTYPE_ETHER		1
+#define HTYPE_IEEE802	6
+#define HTYPE_FDDI		8
+#define HTYPE_IEEE1394	24
+
+/** DHCP MESSAGE CODES **/
+#define DHCP_DISCOVER			1
+#define DHCP_OFFER				2
+#define DHCP_REQUEST			3
+#define DHCP_DECLINE			4
+#define DHCP_ACK				5
+#define DHCP_NAK				6
+#define DHCP_RELEASE			7
+#define DHCP_INFORM				8
+#define DHCP_FORCE_RENEW		9
+#define DHCP_LEASE_QUERY		10
+#define DHCP_LEASE_UNASSIGNED	11
+#define DHCP_LEASE_UNKNOWN		12
+#define DHCP_LEASE_ACTIVE		13
+
+/**	DHCP OPTIONS CODE **/
+#define DHO_PAD								0
+#define DHO_SUBNET							1
+#define DHO_TIME_OFFSET						2
+#define DHO_ROUTERS							3
+#define DHO_TIME_SERVERS					4
+#define DHO_NAME_SERVERS					5
+#define DHO_DOMAIN_NAME_SERVERS				6
+#define DHO_LOG_SERVER						7
+#define DHO_COOKIE_SERVERS					8
+#define DHO_LPR_SERVERS						9
+#define DHO_IMPRESS_SERVER					10
+#define DHO_RESOURCE_LOCATION_SERVERS		11
+#define DHO_HOST_NAME						12
+#define DHO_BOOT_SIZE                      	13
+#define DHO_MERIT_DUMP                     	14
+#define DHO_DOMAIN_NAME                    	15
+#define DHO_SWAP_SERVER                    	16
+#define DHO_ROOT_PATH                      	17
+#define DHO_EXTENSIONS_PATH                	18
+#define DHO_IP_FORWARDING                  	19
+#define DHO_NON_LOCAL_SOURCE_ROUTING       	20
+#define DHO_POLICY_FILTER                  	21
+#define DHO_MAX_DGRAM_REASSEMBLY           	22
+#define DHO_DEFAULT_IP_TTL                 	23
+#define DHO_PATH_MTU_AGING_TIMEOUT         	24
+#define DHO_PATH_MTU_PLATEAU_TABLE         	25
+#define DHO_INTERFACE_MTU                  	26
+#define DHO_ALL_SUBNETS_LOCAL              	27
+#define DHO_BROADCAST_ADDRESS              	28
+#define DHO_PERFORM_MASK_DISCOVERY         	29
+#define DHO_MASK_SUPPLIER                  	30
+#define DHO_ROUTER_DISCOVERY               	31
+#define DHO_ROUTER_SOLICITATION_ADDRESS    	32
+#define DHO_STATIC_ROUTES                  	33
+#define DHO_TRAILER_ENCAPSULATION          	34
+#define DHO_ARP_CACHE_TIMEOUT              	35
+#define DHO_IEEE802_3_ENCAPSULATION        	36
+#define DHO_DEFAULT_TCP_TTL                	37
+#define DHO_TCP_KEEPALIVE_INTERVAL         	38
+#define DHO_TCP_KEEPALIVE_GARBAGE          	39
+#define DHO_NIS_SERVERS                    	41
+#define DHO_NTP_SERVERS                    	42
+#define DHO_VENDOR_ENCAPSULATED_OPTIONS    	43
+#define DHO_NETBIOS_NAME_SERVERS           	44
+#define DHO_NETBIOS_DD_SERVER              	45
+#define DHO_NETBIOS_NODE_TYPE              	46
+#define DHO_NETBIOS_SCOPE                  	47
+#define DHO_FONT_SERVERS                   	48
+#define DHO_X_DISPLAY_MANAGER              	49
+#define DHO_DHCP_REQUESTED_ADDRESS         	50
+#define DHO_DHCP_LEASE_TIME                	51
+#define DHO_DHCP_OPTION_OVERLOAD           	52
+#define DHO_DHCP_MESSAGE_TYPE              	53
+#define DHO_DHCP_SERVER_IDENTIFIER         	54
+#define DHO_DHCP_PARAMETER_REQUEST_LIST    	55
+#define DHO_DHCP_MESSAGE                   	56
+#define DHO_DHCP_MAX_MESSAGE_SIZE          	57
+#define DHO_DHCP_RENEWAL_TIME              	58
+#define DHO_DHCP_REBINDING_TIME            	59
+#define DHO_VENDOR_CLASS_IDENTIFIER        	60
+#define DHO_DHCP_CLIENT_IDENTIFIER         	61
+#define DHO_NWIP_DOMAIN_NAME               	62
+#define DHO_NWIP_SUBOPTIONS                	63
+#define DHO_NISPLUS_DOMAIN                 	64
+#define DHO_NISPLUS_SERVER                 	65
+#define DHO_TFTP_SERVER                    	66
+#define DHO_BOOTFILE                       	67
+#define DHO_MOBILE_IP_HOME_AGENT           	68
+#define DHO_SMTP_SERVER                    	69
+#define DHO_POP3_SERVER                    	70
+#define DHO_NNTP_SERVER                    	71
+#define DHO_WWW_SERVER                     	72
+#define DHO_FINGER_SERVER                  	73
+#define DHO_IRC_SERVER                     	74
+#define DHO_STREETTALK_SERVER              	75
+#define DHO_STDA_SERVER                    	76
+#define DHO_USER_CLASS                     	77
+#define DHO_FQDN                           	81
+#define DHO_DHCP_AGENT_OPTIONS             	82
+#define DHO_NDS_SERVERS                    	85
+#define DHO_NDS_TREE_NAME                  	86
+#define DHO_NDS_CONTEXT					   	87
+#define DHO_CLIENT_LAST_TRANSACTION_TIME   	91
+#define DHO_ASSOCIATED_IP				   	92
+#define DHO_USER_AUTHENTICATION_PROTOCOL   	98
+#define DHO_AUTO_CONFIGURE                	116
+#define DHO_NAME_SERVICE_SEARCH           	117
+#define DHO_SUBNET_SELECTION              	118
+#define DHO_DOMAIN_SEARCH	              	119
+#define DHO_CLASSLESS_ROUTE				  	121
+#define DHO_END                            	0xFF
+
+/** DHCP PACKET LENGTH **/
+#define BOOTP_ABSOLUTE_MIN_LEN	236
+#define DHCP_VEND_SIZE		64
+#define DHCP_MAX_MTU		800
+
+#ifdef __cplusplus /* If this is a C++ compiler, use C linkage */
+extern "C" {
+#endif
+
+struct dhcp_option
+{
+    char                code;
+    char                *value;
+    char                length;
+    struct dhcp_option   *next;
+};
+
+struct dhcp_packet
+{
+    char	op;
+    char 	htype;
+    char	hlen;
+    char	hops;
+    char	xid[4];
+    char	secs[2];
+    char	flags[2];
+    char	ciaddr[4];
+    char	yiaddr[4];
+    char	siaddr[4];
+    char	giaddr[4];
+    char	chaddr[16];
+    char	sname[64];
+    char	file[128];
+    struct dhcp_option	*options;
+    char	*padding;
+};
+
+struct dhcp_packet *dhcpd_marshall(char *buffer, int length, char *request_base);
+
+void dhcpd_packet_free(struct dhcp_packet *packet);
+
+int dhcpd_serialize(struct dhcp_packet *packet, char *buffer, int length);
+
+#ifdef __cplusplus /* If this is a C++ compiler, end C linkage */
+}
+#endif
+
+#endif

platform/vendor_bsp/LN/ln882x/include/net/dhcpd/dhcpd.h

@@ -0,0 +1,100 @@
+#ifndef __DHCPD_H__
+#define __DHCPD_H__
+
+#include <stdint.h>
+#include "lwip/sockets.h"
+#include "lwip/ip4_addr.h"
+#include "dhcpd/dhcp_packet.h"
+
+#define BOOTP_REPLAY_PORT    68
+#define DHCPD_IP_POOL_SIZE   3
+
+#ifdef __cplusplus /* If this is a C++ compiler, use C linkage */
+extern "C" {
+#endif
+
+typedef struct server_config {
+    ip4_addr_t          server;
+    uint16_t            port;
+    uint32_t            lease;
+    uint32_t            renew;
+    ip4_addr_t          ip_start;
+    ip4_addr_t          ip_end;
+    uint8_t             client_max;
+}server_config_t;
+
+typedef struct raw_msg {
+    char       *buff;
+    uint32_t    length;
+    struct sockaddr_in address;
+    int socket_fd;
+}raw_msg_t;
+
+typedef struct network_config {
+    char            hardware_address[6];
+    ip4_addr_t      ip_address;
+    ip4_addr_t      router;
+    ip4_addr_t      netmask;
+    ip4_addr_t      dns1;
+    ip4_addr_t      dns2;
+}network_config_t;
+
+struct dhcpd_ctrl;
+typedef struct dhcpd_ctrl dhcpd_ctrl_t;
+
+typedef int (*dhcpd_ip_allocator_t)(dhcpd_ctrl_t *, network_config_t *, bool pre_allocated);
+
+typedef struct{
+    bool                allocted;
+    char                sta_id[6];
+    ip4_addr_t          ip_addr;
+}dhcpd_ip_item_t;
+
+struct dhcpd_ctrl{
+    OS_Thread_t                 dhcpd_thr;
+    int                         dhcp_socket;
+    bool                        flag;
+    server_config_t             server_config;
+    dhcpd_ip_allocator_t        ip_allocator;
+    dhcpd_ip_item_t             ip_pool[DHCPD_IP_POOL_SIZE];
+    struct raw_msg              msg_receive;
+    char                        request_buff[DHCP_MAX_MTU];
+    char                        response_buff[DHCP_MAX_MTU];
+};
+struct dhcp_packet *do_discover(struct dhcp_packet *request);
+
+struct dhcp_packet *do_request(struct dhcp_packet *request);
+
+struct dhcp_packet *do_release(struct dhcp_packet *request);
+
+struct dhcp_packet *do_inform(struct dhcp_packet *request);
+
+struct dhcp_packet *do_decline(struct dhcp_packet *request);
+
+struct dhcp_packet_handler {
+    struct dhcp_packet *(*do_discover)(struct dhcp_packet *);
+    struct dhcp_packet *(*do_inform)(struct dhcp_packet *);
+    struct dhcp_packet *(*do_request)(struct dhcp_packet *);
+    struct dhcp_packet *(*do_release)(struct dhcp_packet *);
+    struct dhcp_packet *(*do_decline)(struct dhcp_packet *);
+};
+
+
+dhcpd_ctrl_t *dhcpd_get_handle(void);
+int dhcpd_start(void);
+int dhcpd_stop(void);
+bool dhcpd_is_running(void);
+void dhcpd_handle_msg(struct raw_msg *msg);
+struct dhcp_packet *dhcpd_dispatch(struct dhcp_packet *request);
+int dhcpd_ip_allocate(dhcpd_ctrl_t *dhcpd, network_config_t *network_config, bool pre_allocated);
+int dhcpd_ip_release(char *sta_id);
+void dhcpd_close_socket(int *dhcp_socket);
+bool wifi_softap_set_dhcpd_config(server_config_t *server_config, bool write_flash);
+bool wifi_softap_get_dhcpd_config(server_config_t *server_config, bool from_flash);
+bool wifi_softap_dhcpd_config_reset(bool cfg_from_flash);
+
+#ifdef __cplusplus /* If this is a C++ compiler, end C linkage */
+}
+#endif
+
+#endif