clean code

board/Sipeed_LonganNano/eclipse/nRF24L01/main.c

@@ -81,8 +81,8 @@ void main(void) {
 
 
     tos_sem_create(&sem_led, 1);
-    tos_task_create(&led_handle,     "led", task_led, NULL, 6,   led_stk,   LED_TASK_SIZE, 0);
+    tos_task_create(&led_handle,     "led", task_led, NULL, 3,   led_stk,   LED_TASK_SIZE, 0);
-    tos_task_create(&lcd_handle,     "lcd", task_lcd, NULL, 6,   lcd_stk,   LCD_TASK_SIZE, 0);
+    tos_task_create(&lcd_handle,     "lcd", task_lcd, NULL, 3,   lcd_stk,   LCD_TASK_SIZE, 0);
 
     tos_knl_start();
 

board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24.c

@@ -76,11 +76,16 @@ void nrf24l01_init() {
         nhi.csn_port= CSN_GPIO_PORT;
         nhi.csn_pin = CSN_PIN;
 
-        gpio_init(nhi.ce_port,  GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, nhi.ce_pin);
+        nrf_init_t ni = {
-        gpio_init(nhi.csn_port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, nhi.csn_pin);
+                .init		= nrf_hal_init,
-        gpio_bit_set(nhi.ce_port, nhi.ce_pin);
+				.ce			= nrf_hal_ce,
-        gpio_bit_set(nhi.csn_port, nhi.csn_pin);
+				.csn		= nrf_hal_csn,
-        nrf_init(&nhi);
+				.spi_recv	= nrf_hal_spi_recv,
+				.spi_send	= nrf_hal_spi_send,
+				.private	= &nhi,
+        };
+
+        nrf_init(&ni);
     }
 
     tos_task_create(&task_nrf24_handle, "task_nrf24", task_nrf24,  NULL, 5, task_nrf24_stk, TASK_SIZE, 0);
@@ -96,7 +101,7 @@ void EXTI5_9_IRQHandler(void)
             exti_interrupt_flag_clear(IRQ_PIN);
 
             uint8_t status = 0;
-            nrf_hal_read_reg_byte(REG_STATUS, &status);
+            nrf_read_reg_byte(REG_STATUS, &status);
 
             if(status & _BV(RX_DR)) {
                   tos_sem_post(&sem_nrf);

board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24.h

@@ -3,7 +3,7 @@
 
 #include "stdlib.h"
 #include "gd32vf103_gpio.h"
-#include "nrf24l01.h"
+#include "nrf24l01_hal.h"
 
 void nrf24l01_init();
 

board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01.c

@@ -1,48 +1,21 @@
 #include "nrf24l01.h"
 #include "tos_k.h"
 
-static int _nrf_clear_reg_bit(uint8_t reg, uint8_t bit) {
+static nrf_init_t g_nrf;
-    uint8_t v = 0;
 
-    if(0 != nrf_hal_read_reg_byte(reg, &v)) {
+int nrf_init(nrf_init_t *ni) {
-        return -1;
-    }
 
-    v &= ~_BV(bit);
+	memcpy(&g_nrf, ni, sizeof(nrf_init_t));
 
-    if(0 != nrf_hal_write_reg_byte(reg, v)) {
+	return g_nrf.init(g_nrf.private);
-        return -1;
-    }
-
-    return 0;
-}
-
-static int _nrf_set_reg_bit(uint8_t reg, uint8_t bit) {
-    uint8_t v = 0;
-
-    if(0 != nrf_hal_read_reg_byte(reg, &v)) {
-        return -1;
-    }
-
-    v |= _BV(bit);
-
-    if(0 != nrf_hal_write_reg_byte(reg, v)) {
-        return -1;
-    }
-
-    return 0;
-}
-
-int nrf_init(void *ni) {
-    return nrf_hal_init(ni);
 }
 
 void nrf_flush_rx() {
-	nrf_hal_write_cmd(CMD_FLUSH_RX);
+	nrf_write_cmd(CMD_FLUSH_RX);
 }
 
 void nrf_flush_tx() {
-	nrf_hal_write_cmd(CMD_FLUSH_TX);
+	nrf_write_cmd(CMD_FLUSH_TX);
 }
 
 
@@ -52,40 +25,40 @@ void nrf_delay(uint32_t delay) {
 
 
 int nrf_powerup() {
-	return _nrf_set_reg_bit(REG_CONFIG, PWR_UP);
+	return nrf_set_reg_bit(REG_CONFIG, PWR_UP);
 }
 
 int nrf_powerdown() {
-	return _nrf_clear_reg_bit(REG_CONFIG, PWR_UP);
+	return nrf_clear_reg_bit(REG_CONFIG, PWR_UP);
 }
 
 void nrf_enable_rx_irq() {
-	_nrf_clear_reg_bit(REG_CONFIG, MASK_RX_DR);
+	nrf_clear_reg_bit(REG_CONFIG, MASK_RX_DR);
 }
 
 void nrf_disable_rx_irq() {
-	_nrf_set_reg_bit(REG_CONFIG, MASK_RX_DR);
+	nrf_set_reg_bit(REG_CONFIG, MASK_RX_DR);
 }
 
 void nrf_enable_tx_irq() {
-	_nrf_clear_reg_bit(REG_CONFIG, MASK_TX_DS);
+	nrf_clear_reg_bit(REG_CONFIG, MASK_TX_DS);
 }
 
 void nrf_disable_tx_irq() {
-	_nrf_set_reg_bit(REG_CONFIG, MASK_TX_DS);
+	nrf_set_reg_bit(REG_CONFIG, MASK_TX_DS);
 }
 
 void nrf_enable_max_rt_irq() {
-	_nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
+	nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
 }
 
 void nrf_disable_max_rt_irq() {
-	_nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
+	nrf_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
 }
 
 void nrf_set_rf_channel(uint8_t channel) {
 	channel &= 0x7F;
-	nrf_hal_write_reg_byte(REG_RF_CH, channel);
+	nrf_write_reg_byte(REG_RF_CH, channel);
 }
 
 int nrf_set_rxaddr(uint8_t pipe, uint8_t *addr, uint8_t addrlen) {
@@ -100,13 +73,13 @@ int nrf_set_rxaddr(uint8_t pipe, uint8_t *addr, uint8_t addrlen) {
 	uint8_t reg = REG_RX_ADDR_P0 + pipe;
 
 
-	return nrf_hal_write_reg(reg, addr, addrlen);
+	return nrf_write_reg(reg, addr, addrlen);
 }
 
 int nrf_get_addrlen() {
     uint8_t v = 0;
     uint8_t addrlen = 0;
-    if(0 != nrf_hal_read_reg_byte(REG_SETUP_AW, &v)) {
+    if(0 != nrf_read_reg_byte(REG_SETUP_AW, &v)) {
         return 0;
     }
 
@@ -135,19 +108,19 @@ int nrf_get_rxaddr(uint8_t pipe, uint8_t *addr, uint8_t *addrlen) {
 
     uint8_t reg = REG_RX_ADDR_P0 + pipe;
 
-    return nrf_hal_read_reg(reg, addr, *addrlen);
+    return nrf_read_reg(reg, addr, *addrlen);
 }
 
 int nrf_get_txaddr(uint8_t *addr, uint8_t *addrlen) {
     *addrlen = nrf_get_addrlen();
-    return nrf_hal_read_reg(REG_TX_ADDR, addr, *addrlen);
+    return nrf_read_reg(REG_TX_ADDR, addr, *addrlen);
 }
 
 int nrf_set_txaddr(uint8_t *addr, uint8_t addrlen) {
 	if(addrlen >= 6) {
 		return -1;
 	}
-	return nrf_hal_write_reg(REG_TX_ADDR, addr, addrlen);
+	return nrf_write_reg(REG_TX_ADDR, addr, addrlen);
 }
 
 int nrf_enable_rxaddr(uint8_t pipe) {
@@ -155,57 +128,57 @@ int nrf_enable_rxaddr(uint8_t pipe) {
 		return -1;
 	}
 
-	_nrf_set_reg_bit(REG_EN_RXADDR, pipe);
+	nrf_set_reg_bit(REG_EN_RXADDR, pipe);
 
 	return 0;
 }
 
 void nrf_reset_registers() {
-	nrf_hal_write_reg_byte(REG_CONFIG,     _BV(EN_CRC));
+	nrf_write_reg_byte(REG_CONFIG,     _BV(EN_CRC));
-	nrf_hal_write_reg_byte(REG_EN_AA,      _BV(ENAA_P0) | _BV(ENAA_P1) | _BV(ENAA_P2) | _BV(ENAA_P3) | _BV(ENAA_P4) | _BV(ENAA_P5));
+	nrf_write_reg_byte(REG_EN_AA,      _BV(ENAA_P0) | _BV(ENAA_P1) | _BV(ENAA_P2) | _BV(ENAA_P3) | _BV(ENAA_P4) | _BV(ENAA_P5));
-	nrf_hal_write_reg_byte(REG_EN_RXADDR,  _BV(ERX_P0) | _BV(ERX_P1));
+	nrf_write_reg_byte(REG_EN_RXADDR,  _BV(ERX_P0) | _BV(ERX_P1));
-	nrf_hal_write_reg_byte(REG_SETUP_AW,   _VV(AW_5BYTES, AW));
+	nrf_write_reg_byte(REG_SETUP_AW,   _VV(AW_5BYTES, AW));
-	nrf_hal_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC));
+	nrf_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC));
-	nrf_hal_write_reg_byte(REG_RF_CH,		0b00000010);
+	nrf_write_reg_byte(REG_RF_CH,		0b00000010);
-	nrf_hal_write_reg_byte(REG_RF_SETUP,	_BV(RF_DR) | _VV(RF_PWR_0dBm, RF_PWR));
+	nrf_write_reg_byte(REG_RF_SETUP,	_BV(RF_DR) | _VV(RF_PWR_0dBm, RF_PWR));
 
 	uint8_t status = 0;
-	nrf_hal_read_reg_byte(REG_STATUS, &status);
+	nrf_read_reg_byte(REG_STATUS, &status);
 	if(status & _BV(RX_DR)) {
-		_nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
+		nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
 	}
 	if(status & _BV(TX_DS)) {
-		_nrf_set_reg_bit(REG_STATUS, _BV(TX_DS));
+		nrf_set_reg_bit(REG_STATUS, _BV(TX_DS));
 	}
 	if(status & _BV(MAX_RT)) {
-		_nrf_set_reg_bit(REG_STATUS, _BV(MAX_RT));
+		nrf_set_reg_bit(REG_STATUS, _BV(MAX_RT));
 	}
 
-	nrf_hal_write_reg_byte(REG_RX_PW_P0,	0);
+	nrf_write_reg_byte(REG_RX_PW_P0,	0);
-	nrf_hal_write_reg_byte(REG_RX_PW_P1,	0);
+	nrf_write_reg_byte(REG_RX_PW_P1,	0);
-	nrf_hal_write_reg_byte(REG_RX_PW_P2,	0);
+	nrf_write_reg_byte(REG_RX_PW_P2,	0);
-	nrf_hal_write_reg_byte(REG_RX_PW_P3,	0);
+	nrf_write_reg_byte(REG_RX_PW_P3,	0);
-	nrf_hal_write_reg_byte(REG_RX_PW_P4,	0);
+	nrf_write_reg_byte(REG_RX_PW_P4,	0);
-	nrf_hal_write_reg_byte(REG_RX_PW_P5,	0);
+	nrf_write_reg_byte(REG_RX_PW_P5,	0);
-	nrf_hal_write_reg_byte(REG_DYNPD,		0);
+	nrf_write_reg_byte(REG_DYNPD,		0);
-	nrf_hal_write_reg_byte(REG_FEATURE,	0);
+	nrf_write_reg_byte(REG_FEATURE,	0);
 
 	uint8_t addrp0[] = {0xE7, 0xE7, 0xE7, 0xE7, 0xE7};
 	uint8_t addrp1[] = {0xC2, 0xC2, 0xC2, 0xC2, 0xC2};
-	nrf_hal_write_reg(REG_TX_ADDR,    addrp0, 5);
+	nrf_write_reg(REG_TX_ADDR,    addrp0, 5);
-	nrf_hal_write_reg(REG_RX_ADDR_P0, addrp0, 5);
+	nrf_write_reg(REG_RX_ADDR_P0, addrp0, 5);
-	nrf_hal_write_reg(REG_RX_ADDR_P1, addrp1, 5);
+	nrf_write_reg(REG_RX_ADDR_P1, addrp1, 5);
-	nrf_hal_write_reg_byte(REG_RX_ADDR_P2, 0xC3);
+	nrf_write_reg_byte(REG_RX_ADDR_P2, 0xC3);
-	nrf_hal_write_reg_byte(REG_RX_ADDR_P3, 0xC4);
+	nrf_write_reg_byte(REG_RX_ADDR_P3, 0xC4);
-	nrf_hal_write_reg_byte(REG_RX_ADDR_P4, 0xC5);
+	nrf_write_reg_byte(REG_RX_ADDR_P4, 0xC5);
-	nrf_hal_write_reg_byte(REG_RX_ADDR_P5, 0xC6);
+	nrf_write_reg_byte(REG_RX_ADDR_P5, 0xC6);
 
 	nrf_flush_rx();
 	nrf_flush_tx();
 }
 
 void nrf_set_standby_mode() {
-	nrf_hal_ce(0);
+	nrf_ce(0);
 	nrf_powerdown();
 	nrf_reset_registers();
 	nrf_delay(10);
@@ -217,17 +190,17 @@ void nrf_set_standby_mode() {
 
 
 void nrf_set_receive_mode() {
-	_nrf_set_reg_bit(REG_CONFIG, PRIM_RX);
+	nrf_set_reg_bit(REG_CONFIG, PRIM_RX);
 
-	nrf_hal_ce(1);
+	nrf_ce(1);
 
 	nrf_delay(1); // 1ms > 120~130us
 }
 
 void nrf_set_send_mode() {
-	_nrf_clear_reg_bit(REG_CONFIG, PRIM_RX);
+	nrf_clear_reg_bit(REG_CONFIG, PRIM_RX);
 
-	nrf_hal_ce(1);
+	nrf_ce(1);
 
 	nrf_delay(1); // 1ms > 120~130us
 }
@@ -237,7 +210,7 @@ void nrf_enable_autoack(uint8_t pipe) {
 		return ;
 	}
 
-	_nrf_set_reg_bit(REG_EN_AA, pipe);
+	nrf_set_reg_bit(REG_EN_AA, pipe);
 }
 
 void nrf_disable_autoack(uint8_t pipe) {
@@ -245,7 +218,7 @@ void nrf_disable_autoack(uint8_t pipe) {
 		return ;
 	}
 
-	_nrf_clear_reg_bit(REG_EN_AA, pipe);
+	nrf_clear_reg_bit(REG_EN_AA, pipe);
 }
 
 
@@ -254,8 +227,8 @@ void nrf_set_datarate(uint8_t dr) {
 	if(NRF_1Mbps == dr) {
 		dr = 0;
 	} else if(NRF_2Mbps == dr) {
-		nrf_hal_write_reg_byte(REG_RF_SETUP,   0b00001110);
+		nrf_write_reg_byte(REG_RF_SETUP,   0b00001110);
-		nrf_hal_write_reg_byte(REG_SETUP_RETR, 0b00010011);
+		nrf_write_reg_byte(REG_SETUP_RETR, 0b00010011);
 	} else {
 
 	}
@@ -271,14 +244,14 @@ int nrf_enable_dynamic_payload(uint8_t pipe) {
 	uint8_t feature = 0;
 	uint8_t dynpd = 0;
 
-	nrf_hal_read_reg_byte(REG_FEATURE, &feature);
+	nrf_read_reg_byte(REG_FEATURE, &feature);
-	nrf_hal_read_reg_byte(REG_DYNPD, &dynpd);
+	nrf_read_reg_byte(REG_DYNPD, &dynpd);
 
 	feature |= _BV(EN_DPL);
 	dynpd   |= _BV(pipe);
 
-	nrf_hal_write_reg_byte(REG_DYNPD, dynpd);
+	nrf_write_reg_byte(REG_DYNPD, dynpd);
-	nrf_hal_write_reg_byte(REG_FEATURE, feature);
+	nrf_write_reg_byte(REG_FEATURE, feature);
 
 	return 0;
 }
@@ -286,17 +259,17 @@ int nrf_enable_dynamic_payload(uint8_t pipe) {
 int nrf_read_payload(uint8_t *buf, uint8_t *len, uint8_t *pipe) {
     // 读数据通道
     uint8_t status = 0;
-    nrf_hal_read_reg_byte(REG_STATUS, &status);
+    nrf_read_reg_byte(REG_STATUS, &status);
     *pipe = ((status>>1) & 0x07);
 
     // 读数据长度
-	nrf_hal_cmd_read_byte(CMD_R_RX_PL_WID, len);
+	nrf_cmd_read_byte(CMD_R_RX_PL_WID, len);
 
 	// 读数据
-	nrf_hal_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
+	nrf_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
 
 	// 清除数据标志位
-	_nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
+	nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
 
 	// 清空接收缓冲区
 	nrf_flush_rx();
@@ -313,7 +286,7 @@ int nrf_poll_read_payload(uint8_t *buf, uint8_t *len, uint8_t *pipe) {
     while(1) {
         // 读数据通道
         uint8_t status = 0;
-        nrf_hal_read_reg_byte(REG_STATUS, &status);
+        nrf_read_reg_byte(REG_STATUS, &status);
         if((status & _BV(RX_DR)) == 0) {
             nrf_delay(1);
             continue;
@@ -325,13 +298,13 @@ int nrf_poll_read_payload(uint8_t *buf, uint8_t *len, uint8_t *pipe) {
     }
 
     // 读数据长度
-    nrf_hal_cmd_read_byte(CMD_R_RX_PL_WID, len);
+    nrf_cmd_read_byte(CMD_R_RX_PL_WID, len);
 
     // 读数据
-    nrf_hal_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
+    nrf_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
 
     // 清除数据标志位
-    _nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
+    nrf_set_reg_bit(REG_STATUS, _BV(RX_DR));
 
     // 清空接收缓冲区
     nrf_flush_rx();
@@ -344,16 +317,16 @@ int nrf_poll_read_payload(uint8_t *buf, uint8_t *len, uint8_t *pipe) {
 }
 
 int nrf_write_payload(uint8_t *buf, uint8_t len) {
-	nrf_hal_cmd_write(CMD_W_TX_PAYLOAD_NOACK, buf, len);
+	nrf_write_cmd_and_data(CMD_W_TX_PAYLOAD_NOACK, buf, len);
 
     while(1) {
         uint8_t status = 0;
-        nrf_hal_read_reg_byte(REG_STATUS, &status);
+        nrf_read_reg_byte(REG_STATUS, &status);
         if(status &  _BV(TX_DS)) {
             nrf_delay(1);
         }
-        _nrf_set_reg_bit(REG_STATUS, _BV(MAX_RT));
+        nrf_set_reg_bit(REG_STATUS, _BV(MAX_RT));
-        _nrf_set_reg_bit(REG_STATUS, _BV(TX_DS));
+        nrf_set_reg_bit(REG_STATUS, _BV(TX_DS));
         break;
     }
 
@@ -362,9 +335,130 @@ int nrf_write_payload(uint8_t *buf, uint8_t len) {
 
 
 void nrf_ce(uint8_t mode) {
-    nrf_hal_ce(mode);
+    g_nrf.ce(mode);
 }
 
 void nrf_csn(uint8_t mode) {
-    nrf_hal_csn(mode);
+    g_nrf.csn(mode);
 }
+
+
+
+
+
+
+int nrf_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) {
+	uint8_t cmd  = CMD_R_REGISTER | reg;
+
+	nrf_csn(0);
+
+    g_nrf.spi_send(&cmd, 1);
+
+    g_nrf.spi_recv(buf, len);
+
+	nrf_csn(1);
+
+	return 0;
+}
+
+
+int nrf_write_reg(uint8_t reg, uint8_t *buf, uint8_t len)
+{
+	uint8_t cmd = CMD_W_REGISTER | reg;
+
+	nrf_csn(0);
+
+	g_nrf.spi_send(&cmd, 1);
+
+	g_nrf.spi_send(buf, len);
+
+	nrf_csn(1);
+
+	return 0;
+}
+
+
+int nrf_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len) {
+	nrf_csn(0);
+
+	g_nrf.spi_send(&cmd, 1);
+
+	g_nrf.spi_recv(data, len);
+
+	nrf_csn(1);
+
+	return 0;
+}
+
+int nrf_write_cmd_and_data(uint8_t cmd, uint8_t *data, uint8_t len) {
+	nrf_csn(0);
+
+	g_nrf.spi_send(&cmd, 1);
+
+	g_nrf.spi_send(data, len);
+
+	nrf_csn(1);
+
+	return 0;
+}
+
+
+int nrf_cmd_read_byte(uint8_t cmd, uint8_t *data) {
+	return nrf_cmd_read(cmd, data, 1);
+}
+
+int nrf_write_cmd(uint8_t cmd) {
+	nrf_csn(0);
+
+	g_nrf.spi_send(&cmd, 1);
+
+	nrf_csn(1);
+
+	return 0;
+}
+
+
+int nrf_read_reg_byte(uint8_t reg, uint8_t *v) {
+	return nrf_read_reg(reg, v, 1);
+}
+
+int nrf_write_reg_byte(uint8_t reg, uint8_t byte) {
+	return nrf_write_reg(reg, &byte, 1);
+}
+
+int nrf_clear_reg_bit(uint8_t reg, uint8_t bit) {
+    uint8_t v = 0;
+
+    if(0 != nrf_read_reg_byte(reg, &v)) {
+        return -1;
+    }
+
+    v &= ~_BV(bit);
+
+    if(0 != nrf_write_reg_byte(reg, v)) {
+        return -1;
+    }
+
+    return 0;
+}
+
+int nrf_set_reg_bit(uint8_t reg, uint8_t bit) {
+    uint8_t v = 0;
+
+    if(0 != nrf_read_reg_byte(reg, &v)) {
+        return -1;
+    }
+
+    v |= _BV(bit);
+
+    if(0 != nrf_write_reg_byte(reg, v)) {
+        return -1;
+    }
+
+    return 0;
+}
+
+
+
+
+

board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01.h

@@ -1,9 +1,14 @@
 #ifndef NRF24L01_H_
 #define NRF24L01_H_
 
-#include "nrf24l01_hal.h"
+#include "stdint.h"
 
 typedef struct {
+    int  (*init)(void *private);
+    void (*csn)(uint8_t mode);
+    void (*ce)(uint8_t mode);
+    void (*spi_send)(uint8_t *buf, uint8_t len);
+    void (*spi_recv)(uint8_t *buf, uint8_t len);
     void *private;
 } nrf_init_t;
 
@@ -292,7 +297,7 @@ typedef struct {
 #define _VV(v, n) ((v)<<(n))
 
 
-int nrf_init(void* ni);
+int nrf_init(nrf_init_t *ni);
 
 void nrf_flush_rx();
 
@@ -354,4 +359,17 @@ void nrf_ce(uint8_t mode);
 
 void nrf_csn(uint8_t mode);
 
+
+
+int nrf_read_reg(uint8_t reg, uint8_t *buf, uint8_t len);
+int nrf_read_reg_byte(uint8_t reg, uint8_t *v);
+int nrf_write_reg(uint8_t reg, uint8_t *buf, uint8_t len);
+int nrf_write_reg_byte(uint8_t reg, uint8_t byte);
+int nrf_clear_reg_bit(uint8_t reg, uint8_t bit);
+int nrf_set_reg_bit(uint8_t reg, uint8_t bit);
+
+int nrf_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len);
+int nrf_cmd_read_byte(uint8_t cmd, uint8_t *data);
+int nrf_write_cmd_and_data(uint8_t cmd, uint8_t *data, uint8_t len);
+int nrf_write_cmd(uint8_t cmd);
 #endif /* NRF24L01_H_ */

board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01_hal.c

@@ -1,27 +1,30 @@
-#include "nrf24l01.h"
+#include "nrf24l01_hal.h"
+#include "gd32vf103_gpio.h"
+#include <string.h>
 
+static nrf_hal_init_t g_nrf_hal;
 
-static nrf_hal_init_t nhi;
+int nrf_hal_init(void *private) {
 
+    memcpy(&g_nrf_hal, private, sizeof(nrf_hal_init_t));
 
-int nrf_hal_init(nrf_hal_init_t *private) {
+    gpio_init(g_nrf_hal.ce_port,  GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, g_nrf_hal.ce_pin);
-    if(private == 0) {
+    gpio_init(g_nrf_hal.csn_port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, g_nrf_hal.csn_pin);
-        return -1;
-    }
 
-    nhi = *private;
+    nrf_hal_ce(1);
+    nrf_hal_csn(1);
 
     return 0;
 }
 
 void nrf_hal_csn(uint8_t mode) {
-    //gpio_bit_write(nhi.csn_port, nhi.csn_pin, mode == 0 ? RESET : SET);
+    //gpio_bit_write(g_nrf_hal.csn_port, g_nrf_hal.csn_pin, mode == 0 ? RESET : SET);
-    mode == 0 ? gpio_bit_reset(nhi.csn_port, nhi.csn_pin) : gpio_bit_set(nhi.csn_port, nhi.csn_pin);
+    mode == 0 ? gpio_bit_reset(g_nrf_hal.csn_port, g_nrf_hal.csn_pin) : gpio_bit_set(g_nrf_hal.csn_port, g_nrf_hal.csn_pin);
 }
 
 void nrf_hal_ce(uint8_t mode) {
-	//gpio_bit_write(nhi.ce_port, nhi.ce_pin, mode == 0 ? RESET : SET);
+	//gpio_bit_write(g_nrf_hal.ce_port, g_nrf_hal.ce_pin, mode == 0 ? RESET : SET);
-    mode == 0 ? gpio_bit_reset(nhi.ce_port, nhi.ce_pin) : gpio_bit_set(nhi.ce_port, nhi.ce_pin);
+    mode == 0 ? gpio_bit_reset(g_nrf_hal.ce_port, g_nrf_hal.ce_pin) : gpio_bit_set(g_nrf_hal.ce_port, g_nrf_hal.ce_pin);
 }
 
 uint8_t _spi_transfer(uint32_t spi, uint8_t data) {
@@ -35,94 +38,13 @@ uint8_t _spi_transfer(uint32_t spi, uint8_t data) {
 }
 
 
-void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) {
+void nrf_hal_spi_send(uint8_t *buf, uint8_t len) {
     for(uint8_t i=0; i<len; i++) {
-        _spi_transfer(spi, buf[i]);
+        _spi_transfer(g_nrf_hal.spi, buf[i]);
     }
 }
-void _spi_recv(uint32_t spi, uint8_t *buf, uint8_t len) {
+void nrf_hal_spi_recv(uint8_t *buf, uint8_t len) {
     for(uint8_t i=0; i<len; i++) {
-        buf[i] = _spi_transfer(spi, 0xFF);
+        buf[i] = _spi_transfer(g_nrf_hal.spi, 0xFF);
     }
 }
-
-
-int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) {
-	uint8_t cmd  = CMD_R_REGISTER | reg;
-
-	nrf_hal_csn(0);
-
-    _spi_send(nhi.spi, &cmd, 1);
-
-    _spi_recv(nhi.spi, buf, len);
-
-	nrf_hal_csn(1);
-
-	return 0;
-}
-
-int nrf_hal_read_reg_byte(uint8_t reg, uint8_t *v) {
-	return nrf_hal_read_reg(reg, v, 1);
-}
-
-int nrf_hal_write_reg(uint8_t reg, uint8_t *buf, uint8_t len)
-{
-	uint8_t cmd = CMD_W_REGISTER | reg;
-
-	nrf_hal_csn(0);
-
-	_spi_send(nhi.spi, &cmd, 1);
-
-	_spi_send(nhi.spi, buf, len);
-
-	nrf_hal_csn(1);
-
-	return 0;
-}
-
-
-int nrf_hal_write_reg_byte(uint8_t reg, uint8_t byte)
-{
-	return nrf_hal_write_reg(reg, &byte, 1);
-}
-
-
-int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len) {
-	nrf_hal_csn(0);
-
-	_spi_send(nhi.spi, &cmd, 1);
-
-	_spi_recv(nhi.spi, data, len);
-
-	nrf_hal_csn(1);
-
-	return 0;
-}
-
-int nrf_hal_cmd_write(uint8_t cmd, uint8_t *data, uint8_t len) {
-	nrf_hal_csn(0);
-
-	_spi_send(nhi.spi, &cmd, 1);
-
-	_spi_send(nhi.spi, data, len);
-
-	nrf_hal_csn(1);
-
-	return 0;
-}
-
-
-int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data) {
-	return nrf_hal_cmd_read(cmd, data, 1);
-}
-
-int nrf_hal_write_cmd(uint8_t cmd) {
-	nrf_hal_csn(0);
-
-	_spi_send(nhi.spi, &cmd, 1);
-
-	nrf_hal_csn(1);
-
-	return 0;
-}
-

board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01_hal.h

@@ -1,7 +1,7 @@
 #ifndef NRF24L01_HAL_H_
 #define NRF24L01_HAL_H_
 
-#include "gd32vf103.h"
+#include "nrf24l01.h"
 
 typedef struct {
     uint32_t spi;
@@ -11,28 +11,14 @@ typedef struct {
     uint32_t ce_pin;
 } nrf_hal_init_t;
 
-int nrf_hal_init(nrf_hal_init_t *private);
+int  nrf_hal_init(void *nhi);
 
 void nrf_hal_csn(uint8_t mode);
 
 void nrf_hal_ce(uint8_t mode);
 
+void nrf_hal_spi_send(uint8_t *buf, uint8_t len);
 
-int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len);
+void nrf_hal_spi_recv(uint8_t *buf, uint8_t len);
-
-int nrf_hal_read_reg_byte(uint8_t reg, uint8_t *v);
-
-int nrf_hal_write_reg(uint8_t reg, uint8_t *buf, uint8_t len);
-
-int nrf_hal_write_reg_byte(uint8_t reg, uint8_t byte);
-
-int nrf_hal_cmd_read(uint8_t cmd, uint8_t *data, uint8_t len);
-
-int nrf_hal_cmd_read_byte(uint8_t cmd, uint8_t *data);
-
-int nrf_hal_cmd_write(uint8_t cmd, uint8_t *data, uint8_t len);
-
-int nrf_hal_write_cmd(uint8_t cmd);
-
 
 #endif /* NRF24L01_HAL_H_ */