add ring queue/message queue/mail queue, binary heap/priority queue/priority message queue/priority mail queue

1. remove the old msg queue and queue:
i. msg queue is not a common and reusable/flexible component(need user to config the msg pool size and this componet can only be used by tos_queue)
ii. tos_queue can only deliver the pointer message(cannot do a memory buffer deliver)

2. add ring queue(tos_ring_q) componet
rinq queue can be reused by tos_chr_fifi/tos_msg_q/tos_mail_q as the foundational data container

3. add message queue(tos_msg_q)
a little like the old queue mechanism, supply the capability to deliver a pointer message

4. add mail queue(tos_mail_q)
supply the capability to deliver a memory buffer

5. add binary heap(tos_bin_heap)
the basement componet to implement priority queue

6. add priority queue(tos_prio_q)
can be reused by the priority message/mail queue  as the foundational data container.

7. add priority message queue(tos_prio_msg_q)
a message(pointer) deliver mechanism, supply the capability of delivering the message with priority(message with higher priority comes faster to the pender than with lower)

8. add priority mail queue(tos_prio_mail_q)
a mail(memory buffer) deliver mechanism, supply the capability of delivering the mail with priority(mail with higher priority comes faster to the pender than with lower)

board/TencentOS_tiny_EVB_MX_Plus/KEIL/test/DebugConfig/TencentOS_tiny_STM32L431RCTx.dbgconf

@@ -0,0 +1,97 @@
+// File: STM32L43x_44x_45x_46x.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx Reference manual (RM0394)
+//       refer to STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//   <o0.2>    DBG_STANDBY
+//     <i> Debug Standby mode
+//     <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+//     <i> 1: (FCLK=On, HCLK=On) The digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.1>    DBG_STOP
+//     <i> Debug Stop mode
+//     <i> 0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). 
+//     <i> 1: (FCLK=On, HCLK=On) When entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode.
+//   <o0.0>    DBG_SLEEP
+//     <i> Debug Sleep mode
+//     <i> 0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled.
+//     <i> 1: (FCLK=On, HCLK=On) When entering Sleep mode, HCLK is fed by the same clock that is provided to FCLK (system clock as previously configured by the software).
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
+//   <o0.31>    DBG_LPTIM1_STOP
+//     <i> LPTIM1 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM1 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM1 is stopped when the core is halted
+//   <o0.25>    DBG_CAN_STOP
+//     <i> bxCAN1 stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The bxCAN1 receive registers are frozen
+//   <o0.23>    DBG_I2C3_STOP
+//     <i> I2C3 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C3 SMBus timeout is frozen
+//   <o0.22>    DBG_I2C2_STOP
+//     <i> I2C2 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C2 SMBus timeout is frozen
+//   <o0.21>    DBG_I2C1_STOP
+//     <i> I2C1 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C1 SMBus timeout is frozen
+//   <o0.12>    DBG_IWDG_STOP
+//     <i> Independent watchdog counter stopped when core is halted
+//     <i> 0: The independent watchdog counter clock continues even if the core is halted
+//     <i> 1: The independent watchdog counter clock is stopped when the core is halted
+//   <o0.11>    DBG_WWDG_STOP
+//     <i> Window watchdog counter stopped when core is halted
+//     <i> 0: The window watchdog counter clock continues even if the core is halted
+//     <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>    DBG_RTC_STOP
+//     <i> RTC counter stopped when core is halted
+//     <i> 0: The clock of the RTC counter is fed even if the core is halted
+//     <i> 1: The clock of the RTC counter is stopped when the core is halted
+//   <o0.5>    DBG_TIM7_STOP
+//     <i> TIM7 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM7 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM7 is stopped when the core is halted
+//   <o0.4>    DBG_TIM6_STOP
+//     <i> TIM6 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM6 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM6 is stopped when the core is halted
+//   <o0.0>    DBG_TIM2_STOP
+//     <i> TIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz1 = 0x00000000;
+
+// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
+//   <o0.5>    DBG_LPTIM2_STOP
+//     <i> LPTIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz2 = 0x00000000;
+
+// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
+//   <o0.17>    DBG_TIM16_STOP
+//     <i> TIM16 counter stopped when core is halted
+//     <i> 0: The clock of the TIM16 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM16 counter is stopped when the core is halted
+//   <o0.16>    DBG_TIM15_STOP
+//     <i> TIM15 counter stopped when core is halted
+//     <i> 0: The clock of the TIM15 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM15 counter is stopped when the core is halted
+//   <o0.11>    DBG_TIM1_STOP
+//     <i> TIM1 counter stopped when core is halted
+//     <i> 0: The clock of the TIM1 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM1 counter is stopped when the core is halted
+// </h>
+DbgMCU_APB2_Fz = 0x00000000;
+// </h>
+
+// <<< end of configuration section >>>