From d2f38a016e5df01a08514edb353739bb1bc3929c Mon Sep 17 00:00:00 2001
From: niannianyouyu <13212105191@163.com>
Date: Sun, 9 Feb 2020 21:55:31 +0800
Subject: [PATCH] Add NUCLEO_STM32F446RE BSP
---
board/NUCLEO_STM32F446RE/BSP/.mxproject | 14 +
board/NUCLEO_STM32F446RE/BSP/Inc/gpio.h | 57 +
board/NUCLEO_STM32F446RE/BSP/Inc/main.h | 71 +
.../BSP/Inc/stm32f4xx_hal_conf.h | 443 ++++
.../NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_it.h | 70 +
board/NUCLEO_STM32F446RE/BSP/Inc/sys.h | 56 +
board/NUCLEO_STM32F446RE/BSP/Inc/usart.h | 60 +
.../BSP/NUCLEO_STM32F446RE.ioc | 152 ++
board/NUCLEO_STM32F446RE/BSP/Src/gpio.c | 86 +
board/NUCLEO_STM32F446RE/BSP/Src/main.c | 230 ++
.../BSP/Src/stm32f4xx_hal_msp.c | 84 +
.../NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_it.c | 223 ++
board/NUCLEO_STM32F446RE/BSP/Src/sys.c | 37 +
.../BSP/Src/system_stm32f4xx.c | 743 +++++++
board/NUCLEO_STM32F446RE/BSP/Src/usart.c | 183 ++
.../NUCLEO_STM32F446RE_STM32F446RETx.dbgconf | 73 +
.../tencentos_STM32F446RETx.dbgconf | 73 +
.../KEIL/NUCLEO_STM32F446RE.uvguix.luc | 1860 +++++++++++++++++
.../KEIL/NUCLEO_STM32F446RE.uvoptx | 892 ++++++++
.../KEIL/NUCLEO_STM32F446RE.uvprojx | 707 +++++++
.../NUCLEO_STM32F446RE.build_log.htm | 111 +
.../NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.htm | 1696 +++++++++++++++
.../NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.sct | 16 +
.../KEIL/NUCLEO_STM32F446RE/tencentos.htm | 1696 +++++++++++++++
.../KEIL/NUCLEO_STM32F446RE/tencentos.sct | 16 +
.../KEIL/Nu_Link_Driver.ini | 828 ++++++++
.../RTE/_NUCLEO_STM32F446RE/RTE_Components.h | 21 +
.../KEIL/RTE/_tencentos/RTE_Components.h | 21 +
.../KEIL/startup_stm32f446xx.s | 460 ++++
.../NUCLEO_STM32F446RE.build_log.htm | 56 +
.../KEIL/tencentos/NUCLEO_STM32F446RE.htm | 1696 +++++++++++++++
.../KEIL/tencentos/NUCLEO_STM32F446RE.sct | 16 +
32 files changed, 12747 insertions(+)
create mode 100644 board/NUCLEO_STM32F446RE/BSP/.mxproject
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Inc/gpio.h
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Inc/main.h
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_hal_conf.h
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_it.h
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Inc/sys.h
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Inc/usart.h
create mode 100644 board/NUCLEO_STM32F446RE/BSP/NUCLEO_STM32F446RE.ioc
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Src/gpio.c
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Src/main.c
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_hal_msp.c
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_it.c
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Src/sys.c
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Src/system_stm32f4xx.c
create mode 100644 board/NUCLEO_STM32F446RE/BSP/Src/usart.c
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/DebugConfig/NUCLEO_STM32F446RE_STM32F446RETx.dbgconf
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/DebugConfig/tencentos_STM32F446RETx.dbgconf
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvguix.luc
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvoptx
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvprojx
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.build_log.htm
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.htm
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.sct
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.htm
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.sct
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/Nu_Link_Driver.ini
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/RTE/_NUCLEO_STM32F446RE/RTE_Components.h
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/RTE/_tencentos/RTE_Components.h
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/startup_stm32f446xx.s
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.build_log.htm
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.htm
create mode 100644 board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.sct
diff --git a/board/NUCLEO_STM32F446RE/BSP/.mxproject b/board/NUCLEO_STM32F446RE/BSP/.mxproject
new file mode 100644
index 00000000..2716734e
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/.mxproject
@@ -0,0 +1,14 @@
+[PreviousGenFiles]
+HeaderPath=G:/TencentOS/tencentos/Inc
+HeaderFiles=gpio.h;sys.h;usart.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h;
+SourcePath=G:/TencentOS/tencentos/Src
+SourceFiles=gpio.c;sys.c;usart.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;
+
+[PreviousLibFiles]
+LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[PreviousUsedKeilFiles]
+SourceFiles=..\Src\main.c;..\Src\gpio.c;..\Src\sys.c;..\Src\usart.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;;
+HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
+CDefines=USE_HAL_DRIVER;STM32F446xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
diff --git a/board/NUCLEO_STM32F446RE/BSP/Inc/gpio.h b/board/NUCLEO_STM32F446RE/BSP/Inc/gpio.h
new file mode 100644
index 00000000..1c7f4f49
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Inc/gpio.h
@@ -0,0 +1,57 @@
+/**
+ ******************************************************************************
+ * File Name : gpio.h
+ * Description : This file contains all the functions prototypes for
+ * the gpio
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __gpio_H
+#define __gpio_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_GPIO_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ pinoutConfig_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Inc/main.h b/board/NUCLEO_STM32F446RE/BSP/Inc/main.h
new file mode 100644
index 00000000..13e8db7d
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_hal_conf.h b/board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_hal_conf.h
new file mode 100644
index 00000000..25085531
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_hal_conf.h
@@ -0,0 +1,443 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f4xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+
+ /* #define HAL_ADC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_CAN_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+/* #define HAL_SD_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+/* #define HAL_TIM_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_DSI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_FMPI2C_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS 0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
+
+#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_it.h b/board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_it.h
new file mode 100644
index 00000000..70a12cce
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Inc/stm32f4xx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f4xx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Inc/sys.h b/board/NUCLEO_STM32F446RE/BSP/Inc/sys.h
new file mode 100644
index 00000000..64bea532
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Inc/sys.h
@@ -0,0 +1,56 @@
+/**
+ ******************************************************************************
+ * File Name : SYS.h
+ * Description : This file provides code for the configuration
+ * of the SYS instances.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __sys_H
+#define __sys_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_SYS_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ sys_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Inc/usart.h b/board/NUCLEO_STM32F446RE/BSP/Inc/usart.h
new file mode 100644
index 00000000..bf0be6fc
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Inc/usart.h
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * File Name : USART.h
+ * Description : This file provides code for the configuration
+ * of the USART instances.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __usart_H
+#define __usart_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern UART_HandleTypeDef huart1;
+extern UART_HandleTypeDef huart2;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_USART1_UART_Init(void);
+void MX_USART2_UART_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ usart_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/NUCLEO_STM32F446RE.ioc b/board/NUCLEO_STM32F446RE/BSP/NUCLEO_STM32F446RE.ioc
new file mode 100644
index 00000000..c4499ec7
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/NUCLEO_STM32F446RE.ioc
@@ -0,0 +1,152 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32F4
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART1
+Mcu.IP4=USART2
+Mcu.IPNb=5
+Mcu.Name=STM32F446R(C-E)Tx
+Mcu.Package=LQFP64
+Mcu.Pin0=PC13
+Mcu.Pin1=PC14-OSC32_IN
+Mcu.Pin10=PA10
+Mcu.Pin11=PB6
+Mcu.Pin12=VP_SYS_VS_Systick
+Mcu.Pin2=PC15-OSC32_OUT
+Mcu.Pin3=PH0-OSC_IN
+Mcu.Pin4=PH1-OSC_OUT
+Mcu.Pin5=PA2
+Mcu.Pin6=PA3
+Mcu.Pin7=PA5
+Mcu.Pin8=PB13
+Mcu.Pin9=PA9
+Mcu.PinsNb=13
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F446RETx
+MxCube.Version=5.4.0
+MxDb.Version=DB.5.0.40
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA2.Mode=Asynchronous
+PA2.Signal=USART2_TX
+PA3.Mode=Asynchronous
+PA3.Signal=USART2_RX
+PA5.Locked=true
+PA5.Signal=GPIO_Output
+PA9.GPIOParameters=PinState
+PA9.Locked=true
+PA9.PinState=GPIO_PIN_SET
+PA9.Signal=GPIO_Output
+PB13.Locked=true
+PB13.Signal=GPIO_Output
+PB6.Mode=Asynchronous
+PB6.Signal=USART1_TX
+PC13.Locked=true
+PC13.Signal=GPXTI13
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PCC.Checker=false
+PCC.Line=STM32F446
+PCC.MCU=STM32F446R(C-E)Tx
+PCC.PartNumber=STM32F446RETx
+PCC.Seq0=0
+PCC.Series=STM32F4
+PCC.Temperature=25
+PCC.Vdd=3.3
+PH0-OSC_IN.Mode=HSE-External-Oscillator
+PH0-OSC_IN.Signal=RCC_OSC_IN
+PH1-OSC_OUT.Mode=HSE-External-Oscillator
+PH1-OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=true
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F446RETx
+ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.24.2
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=tencentos.ioc
+ProjectManager.ProjectName=tencentos
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5.27
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true
+RCC.AHBCLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=32000000
+RCC.APB1Freq_Value=32000000
+RCC.APB1TimFreq_Value=32000000
+RCC.APB2Freq_Value=32000000
+RCC.APB2TimFreq_Value=32000000
+RCC.CECFreq_Value=32786.88524590164
+RCC.CortexFreq_Value=32000000
+RCC.FCLKCortexFreq_Value=32000000
+RCC.FMPI2C1Freq_Value=32000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=32000000
+RCC.IPParameters=AHBCLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,FMPI2C1Freq_Value,FamilyName,HCLKFreq_Value,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLRCLKFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PWRFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBFreq_Value,VCOI2SInputFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIInputFreq_Value,VCOSAIOutputFreq_Value
+RCC.MCO2PinFreq_Value=64000000
+RCC.PLLCLKFreq_Value=64000000
+RCC.PLLI2SPCLKFreq_Value=96000000
+RCC.PLLI2SQCLKFreq_Value=96000000
+RCC.PLLI2SRCLKFreq_Value=96000000
+RCC.PLLM=8
+RCC.PLLN=64
+RCC.PLLQCLKFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PLLSAIPCLKFreq_Value=96000000
+RCC.PLLSAIQCLKFreq_Value=96000000
+RCC.PWRFreq_Value=64000000
+RCC.SAIAFreq_Value=96000000
+RCC.SAIBFreq_Value=96000000
+RCC.SDIOFreq_Value=64000000
+RCC.SPDIFRXFreq_Value=64000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USBFreq_Value=64000000
+RCC.VCOI2SInputFreq_Value=1000000
+RCC.VCOI2SOutputFreq_Value=192000000
+RCC.VCOInputFreq_Value=2000000
+RCC.VCOOutputFreq_Value=128000000
+RCC.VCOSAIInputFreq_Value=1000000
+RCC.VCOSAIOutputFreq_Value=192000000
+SH.GPXTI13.0=GPIO_EXTI13
+SH.GPXTI13.ConfNb=1
+USART1.IPParameters=VirtualMode
+USART1.VirtualMode=VM_ASYNC
+USART2.IPParameters=VirtualMode
+USART2.VirtualMode=VM_ASYNC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/board/NUCLEO_STM32F446RE/BSP/Src/gpio.c b/board/NUCLEO_STM32F446RE/BSP/Src/gpio.c
new file mode 100644
index 00000000..3b1da0a8
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Src/gpio.c
@@ -0,0 +1,86 @@
+/**
+ ******************************************************************************
+ * File Name : gpio.c
+ * Description : This file provides code for the configuration
+ * of all used GPIO pins.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gpio.h"
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure GPIO */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/** Configure pins as
+ * Analog
+ * Input
+ * Output
+ * EVENT_OUT
+ * EXTI
+*/
+void MX_GPIO_Init(void)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
+
+ /*Configure GPIO pin : PC13 */
+ GPIO_InitStruct.Pin = GPIO_PIN_13;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /*Configure GPIO pins : PA5 PA9 */
+ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : PB13 */
+ GPIO_InitStruct.Pin = GPIO_PIN_13;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Src/main.c b/board/NUCLEO_STM32F446RE/BSP/Src/main.c
new file mode 100644
index 00000000..9c661030
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Src/main.c
@@ -0,0 +1,230 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "usart.h"
+#include "gpio.h"
+
+#include "cmsis_os.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+//task1
+ #define TASK1_STK_SIZE 256
+ void task1(void *pdata);
+ osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE);
+
+ //task2
+ #define TASK2_STK_SIZE 256
+ void task2(void *pdata);
+ osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);
+
+ void task1(void *pdata)
+ {
+ int count = 1;
+ while(1)
+ {
+ printf("\r\nHello world!\r\n###This is task1 ,count is %d \r\n", count++);
+ HAL_GPIO_TogglePin(GPIOA,GPIO_PIN_5);
+ osDelay(2000);
+ }
+ }
+ void task2(void *pdata)
+ {
+ int count = 1;
+ while(1)
+ {
+ printf("\r\nHello TencentOS !\r\n***This is task2 ,count is %d \r\n", count++);
+ osDelay(1000);
+ }
+ }
+
+ int fputc(int ch, FILE *f)
+ {
+ if (ch == '\n')
+ {
+ HAL_UART_Transmit(&huart2, (void *)"\r", 1,30000);
+ }
+ HAL_UART_Transmit(&huart2, (uint8_t *)&ch, 1, 0xFFFF);
+ return ch;
+ }
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* USER CODE BEGIN 1 */
+
+ /* USER CODE END 1 */
+
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_USART2_UART_Init();
+ MX_USART1_UART_Init();
+
+ osKernelInitialize(); //TOS Tiny kernel initialize
+ osThreadCreate(osThread(task1), NULL);// Create task1
+ osThreadCreate(osThread(task2), NULL);// Create task2
+ osKernelStart();//Start TOS Tiny
+ /* USER CODE BEGIN 2 */
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+ HAL_Delay(1000);
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+ RCC_OscInitStruct.PLL.PLLN = 64;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_hal_msp.c b/board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_hal_msp.c
new file mode 100644
index 00000000..db509885
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_hal_msp.c
@@ -0,0 +1,84 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name : stm32f4xx_hal_msp.c
+ * Description : This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_it.c b/board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_it.c
new file mode 100644
index 00000000..2c3d7ed7
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Src/stm32f4xx_it.c
@@ -0,0 +1,223 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f4xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+#include "tos_k.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex-M4 Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ /* USER CODE BEGIN SVCall_IRQn 0 */
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+__weak void PendSV_Handler(void)
+{
+ /* USER CODE BEGIN PendSV_IRQn 0 */
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+if (tos_knl_is_running())
+{
+ tos_knl_irq_enter();
+ tos_tick_handler();
+ tos_knl_irq_leave();
+}
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32f4xx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles USART1 global interrupt.
+ */
+void USART1_IRQHandler(void)
+{
+ /* USER CODE BEGIN USART1_IRQn 0 */
+
+ /* USER CODE END USART1_IRQn 0 */
+ HAL_UART_IRQHandler(&huart1);
+ /* USER CODE BEGIN USART1_IRQn 1 */
+
+ /* USER CODE END USART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Src/sys.c b/board/NUCLEO_STM32F446RE/BSP/Src/sys.c
new file mode 100644
index 00000000..f5ccd74b
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Src/sys.c
@@ -0,0 +1,37 @@
+/**
+ ******************************************************************************
+ * File Name : SYS.c
+ * Description : This file provides code for the configuration
+ * of the SYS instances.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "sys.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* SYS init function */
+void MX_SYS_Init(void)
+{
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Src/system_stm32f4xx.c b/board/NUCLEO_STM32F446RE/BSP/Src/system_stm32f4xx.c
new file mode 100644
index 00000000..90376044
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Src/system_stm32f4xx.c
@@ -0,0 +1,743 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+
+#include "stm32f4xx.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+ STM32F412Zx || STM32F412Vx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0x00;
+
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+ RCC->AHB1ENR |= 0x000001F8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration -------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001091;
+ FMC_Bank1->BTCR[3] = 0x00110212;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+ (void)(tmp);
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+ /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+ clock */
+ RCC->AHB1ENR |= 0x0000007D;
+#else
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+#if defined(STM32F446xx)
+ /* Connect PAx pins to FMC Alternate function */
+ GPIOA->AFR[0] |= 0xC0000000;
+ GPIOA->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOA->MODER |= 0x00008000;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOA->OSPEEDR |= 0x00008000;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOA->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOA->PUPDR |= 0x00000000;
+
+ /* Connect PCx pins to FMC Alternate function */
+ GPIOC->AFR[0] |= 0x00CC0000;
+ GPIOC->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOC->MODER |= 0x00000A00;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOC->OSPEEDR |= 0x00000A00;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOC->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOC->PUPDR |= 0x00000000;
+#endif /* STM32F446xx */
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/*-- FMC Configuration -------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+ /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else
+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x000000F3;
+#else
+ FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x00044014;
+#else
+ FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00085AAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000CAFFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001091;
+ FMC_Bank1->BTCR[3] = 0x00110212;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+ || defined(STM32F412Zx) || defined(STM32F412Vx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
+ (void)(tmp);
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/BSP/Src/usart.c b/board/NUCLEO_STM32F446RE/BSP/Src/usart.c
new file mode 100644
index 00000000..1574184c
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/BSP/Src/usart.c
@@ -0,0 +1,183 @@
+/**
+ ******************************************************************************
+ * File Name : USART.c
+ * Description : This file provides code for the configuration
+ * of the USART instances.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usart.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+UART_HandleTypeDef huart1;
+UART_HandleTypeDef huart2;
+
+/* USART1 init function */
+
+void MX_USART1_UART_Init(void)
+{
+
+ huart1.Instance = USART1;
+ huart1.Init.BaudRate = 115200;
+ huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ huart1.Init.StopBits = UART_STOPBITS_1;
+ huart1.Init.Parity = UART_PARITY_NONE;
+ huart1.Init.Mode = UART_MODE_TX_RX;
+ huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ if (HAL_UART_Init(&huart1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+}
+/* USART2 init function */
+
+void MX_USART2_UART_Init(void)
+{
+
+ huart2.Instance = USART2;
+ huart2.Init.BaudRate = 115200;
+ huart2.Init.WordLength = UART_WORDLENGTH_8B;
+ huart2.Init.StopBits = UART_STOPBITS_1;
+ huart2.Init.Parity = UART_PARITY_NONE;
+ huart2.Init.Mode = UART_MODE_TX_RX;
+ huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+ if (HAL_UART_Init(&huart2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+}
+
+void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(uartHandle->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspInit 0 */
+
+ /* USER CODE END USART1_MspInit 0 */
+ /* USART1 clock enable */
+ __HAL_RCC_USART1_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ /**USART1 GPIO Configuration
+ PA10 ------> USART1_RX
+ PB6 ------> USART1_TX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /* USART1 interrupt Init */
+ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(USART1_IRQn);
+ /* USER CODE BEGIN USART1_MspInit 1 */
+
+ /* USER CODE END USART1_MspInit 1 */
+ }
+ else if(uartHandle->Instance==USART2)
+ {
+ /* USER CODE BEGIN USART2_MspInit 0 */
+
+ /* USER CODE END USART2_MspInit 0 */
+ /* USART2 clock enable */
+ __HAL_RCC_USART2_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**USART2 GPIO Configuration
+ PA2 ------> USART2_TX
+ PA3 ------> USART2_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN USART2_MspInit 1 */
+
+ /* USER CODE END USART2_MspInit 1 */
+ }
+}
+
+void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
+{
+
+ if(uartHandle->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+ /* USER CODE END USART1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART1_CLK_DISABLE();
+
+ /**USART1 GPIO Configuration
+ PA10 ------> USART1_RX
+ PB6 ------> USART1_TX
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10);
+
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
+
+ /* USART1 interrupt Deinit */
+ HAL_NVIC_DisableIRQ(USART1_IRQn);
+ /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+ /* USER CODE END USART1_MspDeInit 1 */
+ }
+ else if(uartHandle->Instance==USART2)
+ {
+ /* USER CODE BEGIN USART2_MspDeInit 0 */
+
+ /* USER CODE END USART2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART2_CLK_DISABLE();
+
+ /**USART2 GPIO Configuration
+ PA2 ------> USART2_TX
+ PA3 ------> USART2_RX
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
+
+ /* USER CODE BEGIN USART2_MspDeInit 1 */
+
+ /* USER CODE END USART2_MspDeInit 1 */
+ }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/board/NUCLEO_STM32F446RE/KEIL/DebugConfig/NUCLEO_STM32F446RE_STM32F446RETx.dbgconf b/board/NUCLEO_STM32F446RE/KEIL/DebugConfig/NUCLEO_STM32F446RE_STM32F446RETx.dbgconf
new file mode 100644
index 00000000..46942545
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/DebugConfig/NUCLEO_STM32F446RE_STM32F446RETx.dbgconf
@@ -0,0 +1,73 @@
+// File: STM32F446.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32F446xx reference manual (RM0390)
+// refer to STM32F446xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Debug MCU configuration register (DBGMCU_CR)
+// DBG_STANDBY Debug Standby Mode
+// DBG_STOP Debug Stop Mode
+// DBG_SLEEP Debug Sleep Mode
+//
+DbgMCU_CR = 0x00000007;
+
+// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
+// Reserved bits must be kept at reset value
+// DBG_CAN2_STOP CAN2 stopped when core is halted
+// DBG_CAN1_STOP CAN2 stopped when core is halted
+// DBG_I2CFMP_SMBUS_TIMEOUT I2CFMP SMBUS timeout mode stopped when core is halted
+// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted
+// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted
+// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted
+// DBG_IWDG_STOP Independent watchdog stopped when core is halted
+// DBG_WWDG_STOP Window watchdog stopped when core is halted
+// DBG_RTC_STOP RTC stopped when core is halted
+// DBG_TIM14_STOP TIM14 counter stopped when core is halted
+// DBG_TIM13_STOP TIM13 counter stopped when core is halted
+// DBG_TIM12_STOP TIM12 counter stopped when core is halted
+// DBG_TIM7_STOP TIM7 counter stopped when core is halted
+// DBG_TIM6_STOP TIM6 counter stopped when core is halted
+// DBG_TIM5_STOP TIM5 counter stopped when core is halted
+// DBG_TIM4_STOP TIM4 counter stopped when core is halted
+// DBG_TIM3_STOP TIM3 counter stopped when core is halted
+// DBG_TIM2_STOP TIM2 counter stopped when core is halted
+//
+DbgMCU_APB1_Fz = 0x00000000;
+
+// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
+// Reserved bits must be kept at reset value
+// DBG_TIM11_STOP TIM11 counter stopped when core is halted
+// DBG_TIM10_STOP TIM10 counter stopped when core is halted
+// DBG_TIM9_STOP TIM9 counter stopped when core is halted
+// DBG_TIM8_STOP TIM8 counter stopped when core is halted
+// DBG_TIM1_STOP TIM1 counter stopped when core is halted
+//
+DbgMCU_APB2_Fz = 0x00000000;
+
+// TPIU Pin Routing (TRACECLK fixed on Pin PE2)
+// TRACECLK: Pin PE2
+// TRACED0
+// ETM Trace Data 0
+// <0x00040003=> Pin PE3
+// <0x00020008=> Pin PC8
+// TRACED1
+// ETM Trace Data 1
+// <0x00040004=> Pin PE4
+// <0x00030003=> Pin PD3
+// TRACED2
+// ETM Trace Data 2
+// <0x00040005=> Pin PE5
+// <0x0006000D=> Pin PG13
+// TRACED3
+// ETM Trace Data 3
+// <0x00040006=> Pin PE6
+// <0x0006000E=> Pin PG14
+//
+TraceClk_Pin = 0x00040002;
+TraceD0_Pin = 0x00040003;
+TraceD1_Pin = 0x00040004;
+TraceD2_Pin = 0x00040005;
+TraceD3_Pin = 0x00040006;
+
+// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/board/NUCLEO_STM32F446RE/KEIL/DebugConfig/tencentos_STM32F446RETx.dbgconf b/board/NUCLEO_STM32F446RE/KEIL/DebugConfig/tencentos_STM32F446RETx.dbgconf
new file mode 100644
index 00000000..46942545
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/DebugConfig/tencentos_STM32F446RETx.dbgconf
@@ -0,0 +1,73 @@
+// File: STM32F446.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32F446xx reference manual (RM0390)
+// refer to STM32F446xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Debug MCU configuration register (DBGMCU_CR)
+// DBG_STANDBY Debug Standby Mode
+// DBG_STOP Debug Stop Mode
+// DBG_SLEEP Debug Sleep Mode
+//
+DbgMCU_CR = 0x00000007;
+
+// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
+// Reserved bits must be kept at reset value
+// DBG_CAN2_STOP CAN2 stopped when core is halted
+// DBG_CAN1_STOP CAN2 stopped when core is halted
+// DBG_I2CFMP_SMBUS_TIMEOUT I2CFMP SMBUS timeout mode stopped when core is halted
+// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted
+// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted
+// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted
+// DBG_IWDG_STOP Independent watchdog stopped when core is halted
+// DBG_WWDG_STOP Window watchdog stopped when core is halted
+// DBG_RTC_STOP RTC stopped when core is halted
+// DBG_TIM14_STOP TIM14 counter stopped when core is halted
+// DBG_TIM13_STOP TIM13 counter stopped when core is halted
+// DBG_TIM12_STOP TIM12 counter stopped when core is halted
+// DBG_TIM7_STOP TIM7 counter stopped when core is halted
+// DBG_TIM6_STOP TIM6 counter stopped when core is halted
+// DBG_TIM5_STOP TIM5 counter stopped when core is halted
+// DBG_TIM4_STOP TIM4 counter stopped when core is halted
+// DBG_TIM3_STOP TIM3 counter stopped when core is halted
+// DBG_TIM2_STOP TIM2 counter stopped when core is halted
+//
+DbgMCU_APB1_Fz = 0x00000000;
+
+// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
+// Reserved bits must be kept at reset value
+// DBG_TIM11_STOP TIM11 counter stopped when core is halted
+// DBG_TIM10_STOP TIM10 counter stopped when core is halted
+// DBG_TIM9_STOP TIM9 counter stopped when core is halted
+// DBG_TIM8_STOP TIM8 counter stopped when core is halted
+// DBG_TIM1_STOP TIM1 counter stopped when core is halted
+//
+DbgMCU_APB2_Fz = 0x00000000;
+
+// TPIU Pin Routing (TRACECLK fixed on Pin PE2)
+// TRACECLK: Pin PE2
+// TRACED0
+// ETM Trace Data 0
+// <0x00040003=> Pin PE3
+// <0x00020008=> Pin PC8
+// TRACED1
+// ETM Trace Data 1
+// <0x00040004=> Pin PE4
+// <0x00030003=> Pin PD3
+// TRACED2
+// ETM Trace Data 2
+// <0x00040005=> Pin PE5
+// <0x0006000D=> Pin PG13
+// TRACED3
+// ETM Trace Data 3
+// <0x00040006=> Pin PE6
+// <0x0006000E=> Pin PG14
+//
+TraceClk_Pin = 0x00040002;
+TraceD0_Pin = 0x00040003;
+TraceD1_Pin = 0x00040004;
+TraceD2_Pin = 0x00040005;
+TraceD3_Pin = 0x00040006;
+
+// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvguix.luc b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvguix.luc
new file mode 100644
index 00000000..cfe876f3
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvguix.luc
@@ -0,0 +1,1860 @@
+
+
+
+ -6.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+
+
+
+
+
+
+ 38003
+ Registers
+ 115 45
+
+
+ 346
+ Code Coverage
+ 665 160
+
+
+ 204
+ Performance Analyzer
+ 825
+
+
+
+
+
+ 35141
+ Event Statistics
+
+ 200 50 700
+
+
+ 1506
+ Symbols
+
+ 56 56 56
+
+
+ 1936
+ Watch 1
+
+ 200 133 133
+
+
+ 1937
+ Watch 2
+
+ 200 133 133
+
+
+ 1935
+ Call Stack + Locals
+
+ 200 133 133
+
+
+ 2506
+ Trace Data
+
+ 75 135 130 95 70 230 200 150
+
+
+ 466
+ Source Browser
+ 500
+ 300
+
+
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ -1
+
+
+
+
+
+
+ 44
+ 2
+ 3
+
+ -32000
+ -32000
+
+
+ -1
+ -1
+
+
+ 78
+ 78
+ 1103
+ 603
+
+
+
+ 0
+
+ 60
+ 010000000400000001000000010000000100000001000000000000000200000000000000010000000100000000000000280000002800000000000000
+
+
+
+ 0
+ Build
+
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ AE0000004F000000F1030000B3000000
+
+
+ 16
+ AE00000066000000F1030000CA000000
+
+
+
+ 1005
+ 1005
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000F30000002D020000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 109
+ 109
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000F30000002D020000
+
+
+ 16
+ 7000000087000000390100000C020000
+
+
+
+ 1465
+ 1465
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1466
+ 1466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1467
+ 1467
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1468
+ 1468
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1506
+ 1506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 1913
+ 1913
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1935
+ 1935
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 1936
+ 1936
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 1937
+ 1937
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 1939
+ 1939
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1940
+ 1940
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1941
+ 1941
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 1942
+ 1942
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 195
+ 195
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000F30000002D020000
+
+
+ 16
+ 7000000087000000390100000C020000
+
+
+
+ 196
+ 196
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000F30000002D020000
+
+
+ 16
+ 7000000087000000390100000C020000
+
+
+
+ 197
+ 197
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 000000005E02000056050000AE020000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 198
+ 198
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 000000005E010000F1030000D3010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 199
+ 199
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000610200005305000095020000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 203
+ 203
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 204
+ 204
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 221
+ 221
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000000000000000000000000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 2506
+ 2506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 2507
+ 2507
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 343
+ 343
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 346
+ 346
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 35141
+ 35141
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35824
+ 35824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 35885
+ 35885
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35886
+ 35886
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35887
+ 35887
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35888
+ 35888
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35889
+ 35889
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35890
+ 35890
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35891
+ 35891
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35892
+ 35892
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35893
+ 35893
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35894
+ 35894
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35895
+ 35895
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35896
+ 35896
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35897
+ 35897
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35898
+ 35898
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35899
+ 35899
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35900
+ 35900
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35901
+ 35901
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35902
+ 35902
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35903
+ 35903
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35904
+ 35904
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 35905
+ 35905
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 38003
+ 38003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000A70000002D020000
+
+
+ 16
+ 7000000087000000390100000C020000
+
+
+
+ 38007
+ 38007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000610200005305000095020000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 436
+ 436
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000610200005305000095020000
+
+
+ 16
+ 7000000087000000390100000C020000
+
+
+
+ 437
+ 437
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 440
+ 440
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 463
+ 463
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000610200005305000095020000
+
+
+ 16
+ 7000000087000000390100000C020000
+
+
+
+ 466
+ 466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000610200005305000095020000
+
+
+ 16
+ 7000000087000000390100000C020000
+
+
+
+ 470
+ 470
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ B100000066000000EE0300009A000000
+
+
+ 16
+ 700000008700000068020000E8000000
+
+
+
+ 50000
+ 50000
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50001
+ 50001
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50002
+ 50002
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50003
+ 50003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50004
+ 50004
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50005
+ 50005
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50006
+ 50006
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50007
+ 50007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50008
+ 50008
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50009
+ 50009
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50010
+ 50010
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50011
+ 50011
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50012
+ 50012
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50013
+ 50013
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50014
+ 50014
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50015
+ 50015
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50016
+ 50016
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50017
+ 50017
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50018
+ 50018
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 50019
+ 50019
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 4A03000066000000EE03000052010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 59392
+ 59392
+ 1
+ 0
+ 0
+ 0
+ 966
+ 0
+ 8192
+ 0
+
+ 16
+ 0000000000000000D10300001C000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59393
+ 0
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000AE02000056050000C1020000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59399
+ 59399
+ 1
+ 0
+ 0
+ 0
+ 476
+ 0
+ 8192
+ 1
+
+ 16
+ 000000001C000000E701000038000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59400
+ 59400
+ 0
+ 0
+ 0
+ 0
+ 612
+ 0
+ 8192
+ 2
+
+ 16
+ 00000000380000006F02000054000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 824
+ 824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000075010000EE030000BA010000
+
+
+ 16
+ 70000000870000001A01000014010000
+
+
+
+ 3312
+ 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFAE000000B3000000F1030000B7000000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000AE00000066000000F1030000CA000000AE0000004F000000F1030000B30000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF430300004F000000470300006B010000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C30000018000400000000000004703000066000000F103000082010000470300004F000000F10300006B01000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFF60000004F000000FA000000460200000100000002000010040000000100000058FFFFFFA3040000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000AA0000005D020000000000004F000000F6000000460200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF000000005A010000F10300005E01000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB090000018000800000000000000000000075010000F1030000EA010000000000005E010000F1030000D301000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFF90100005E010000FD010000D301000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF0000000046020000560500004A020000010000000100001004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000001000000000000006102000056050000C5020000000000004A02000056050000AE0200000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000
+
+
+ 59392
+ File
+
+ 2550
+ 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000400020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000004000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000004000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000004000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000040000000000000000000000000000000000000100000001000000960000000200205000000000044E56494396000000000000000100044E56494300000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000004001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000400160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000
+
+
+
+ 59399
+ Build
+
+ 996
+ 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000004001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000000000000100000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA0000000000000000000000000000000000000000000000000100000001000000960000000300205000000000124E55434C454F5F53544D333246343436524596000000000000000100124E55434C454F5F53544D3332463434365245000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000
+
+
+
+ 59400
+ Debug
+
+ 2373
+ 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000
+
+
+
+ 0
+ 1366
+ 768
+
+
+
+
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvoptx b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvoptx
new file mode 100644
index 00000000..a6bd8b57
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvoptx
@@ -0,0 +1,892 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ NUCLEO_STM32F446RE
+ 0x4
+ ARM-ADS
+
+ 32000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 18
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 6
+
+
+
+
+
+
+
+
+
+
+ STLink\ST-LINKIII-KEIL_SWO.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F446RETx$CMSIS\Flash\STM32F4xx_512.FLM))
+
+
+ 0
+ ST-LINKIII-KEIL_SWO
+ -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F446RETx$CMSIS\Flash\STM32F4xx_512.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+ 1
+ 1
+ 0
+ 2
+ 10000000
+
+
+
+
+
+ Application/MDK-ARM
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 2
+ 0
+ 0
+ 0
+ startup_stm32f446xx.s
+ startup_stm32f446xx.s
+ 0
+ 0
+
+
+
+
+ Application/User
+ 1
+ 0
+ 0
+ 0
+
+ 2
+ 2
+ 1
+ 0
+ 0
+ 0
+ ../Src/main.c
+ main.c
+ 0
+ 0
+
+
+ 2
+ 3
+ 1
+ 0
+ 0
+ 0
+ ../Src/gpio.c
+ gpio.c
+ 0
+ 0
+
+
+ 2
+ 4
+ 1
+ 0
+ 0
+ 0
+ ../Src/sys.c
+ sys.c
+ 0
+ 0
+
+
+ 2
+ 5
+ 1
+ 0
+ 0
+ 0
+ ../Src/usart.c
+ usart.c
+ 0
+ 0
+
+
+ 2
+ 6
+ 1
+ 0
+ 0
+ 0
+ ../Src/stm32f4xx_it.c
+ stm32f4xx_it.c
+ 0
+ 0
+
+
+ 2
+ 7
+ 1
+ 0
+ 0
+ 0
+ ../Src/stm32f4xx_hal_msp.c
+ stm32f4xx_hal_msp.c
+ 0
+ 0
+
+
+
+
+ Drivers/STM32F4xx_HAL_Driver
+ 1
+ 0
+ 0
+ 0
+
+ 3
+ 8
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
+ stm32f4xx_hal_tim.c
+ 0
+ 0
+
+
+ 3
+ 9
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
+ stm32f4xx_hal_tim_ex.c
+ 0
+ 0
+
+
+ 3
+ 10
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
+ stm32f4xx_hal_uart.c
+ 0
+ 0
+
+
+ 3
+ 11
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
+ stm32f4xx_hal_rcc.c
+ 0
+ 0
+
+
+ 3
+ 12
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
+ stm32f4xx_hal_rcc_ex.c
+ 0
+ 0
+
+
+ 3
+ 13
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
+ stm32f4xx_hal_flash.c
+ 0
+ 0
+
+
+ 3
+ 14
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
+ stm32f4xx_hal_flash_ex.c
+ 0
+ 0
+
+
+ 3
+ 15
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
+ stm32f4xx_hal_flash_ramfunc.c
+ 0
+ 0
+
+
+ 3
+ 16
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
+ stm32f4xx_hal_gpio.c
+ 0
+ 0
+
+
+ 3
+ 17
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
+ stm32f4xx_hal_dma_ex.c
+ 0
+ 0
+
+
+ 3
+ 18
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
+ stm32f4xx_hal_dma.c
+ 0
+ 0
+
+
+ 3
+ 19
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
+ stm32f4xx_hal_pwr.c
+ 0
+ 0
+
+
+ 3
+ 20
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
+ stm32f4xx_hal_pwr_ex.c
+ 0
+ 0
+
+
+ 3
+ 21
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
+ stm32f4xx_hal_cortex.c
+ 0
+ 0
+
+
+ 3
+ 22
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
+ stm32f4xx_hal.c
+ 0
+ 0
+
+
+ 3
+ 23
+ 1
+ 0
+ 0
+ 0
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
+ stm32f4xx_hal_exti.c
+ 0
+ 0
+
+
+
+
+ Drivers/CMSIS
+ 0
+ 0
+ 0
+ 0
+
+ 4
+ 24
+ 1
+ 0
+ 0
+ 0
+ ../Src/system_stm32f4xx.c
+ system_stm32f4xx.c
+ 0
+ 0
+
+
+
+
+ tos/arch
+ 0
+ 0
+ 0
+ 0
+
+ 5
+ 25
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+ tos_cpu.c
+ 0
+ 0
+
+
+ 5
+ 26
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c
+ port_c.c
+ 0
+ 0
+
+
+ 5
+ 27
+ 2
+ 0
+ 0
+ 0
+ ..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S
+ port_s.S
+ 0
+ 0
+
+
+
+
+ tos/kernel
+ 0
+ 0
+ 0
+ 0
+
+ 6
+ 28
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_binary_heap.c
+ tos_binary_heap.c
+ 0
+ 0
+
+
+ 6
+ 29
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_char_fifo.c
+ tos_char_fifo.c
+ 0
+ 0
+
+
+ 6
+ 30
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_completion.c
+ tos_completion.c
+ 0
+ 0
+
+
+ 6
+ 31
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_countdownlatch.c
+ tos_countdownlatch.c
+ 0
+ 0
+
+
+ 6
+ 32
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_event.c
+ tos_event.c
+ 0
+ 0
+
+
+ 6
+ 33
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_global.c
+ tos_global.c
+ 0
+ 0
+
+
+ 6
+ 34
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_mail_queue.c
+ tos_mail_queue.c
+ 0
+ 0
+
+
+ 6
+ 35
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_message_queue.c
+ tos_message_queue.c
+ 0
+ 0
+
+
+ 6
+ 36
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_mmblk.c
+ tos_mmblk.c
+ 0
+ 0
+
+
+ 6
+ 37
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_mmheap.c
+ tos_mmheap.c
+ 0
+ 0
+
+
+ 6
+ 38
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_mutex.c
+ tos_mutex.c
+ 0
+ 0
+
+
+ 6
+ 39
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_pend.c
+ tos_pend.c
+ 0
+ 0
+
+
+ 6
+ 40
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_priority_mail_queue.c
+ tos_priority_mail_queue.c
+ 0
+ 0
+
+
+ 6
+ 41
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_priority_message_queue.c
+ tos_priority_message_queue.c
+ 0
+ 0
+
+
+ 6
+ 42
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_priority_queue.c
+ tos_priority_queue.c
+ 0
+ 0
+
+
+ 6
+ 43
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_ring_queue.c
+ tos_ring_queue.c
+ 0
+ 0
+
+
+ 6
+ 44
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_robin.c
+ tos_robin.c
+ 0
+ 0
+
+
+ 6
+ 45
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_sched.c
+ tos_sched.c
+ 0
+ 0
+
+
+ 6
+ 46
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_sem.c
+ tos_sem.c
+ 0
+ 0
+
+
+ 6
+ 47
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_sys.c
+ tos_sys.c
+ 0
+ 0
+
+
+ 6
+ 48
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_task.c
+ tos_task.c
+ 0
+ 0
+
+
+ 6
+ 49
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_tick.c
+ tos_tick.c
+ 0
+ 0
+
+
+ 6
+ 50
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_time.c
+ tos_time.c
+ 0
+ 0
+
+
+ 6
+ 51
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\kernel\core\tos_timer.c
+ tos_timer.c
+ 0
+ 0
+
+
+
+
+ tos/cmsis_os
+ 0
+ 0
+ 0
+ 0
+
+ 7
+ 52
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\osal\cmsis_os\cmsis_os.c
+ cmsis_os.c
+ 0
+ 0
+
+
+
+
+ TOS_CONFIG
+ 1
+ 0
+ 0
+ 0
+
+ 8
+ 53
+ 5
+ 0
+ 0
+ 0
+ ..\tos_config.h
+ tos_config.h
+ 0
+ 0
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvprojx b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvprojx
new file mode 100644
index 00000000..6f1c1e04
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvprojx
@@ -0,0 +1,707 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ NUCLEO_STM32F446RE
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 0
+
+
+ STM32F446RETx
+ STMicroelectronics
+ Keil.STM32F4xx_DFP.2.14.0
+ http://www.keil.com/pack/
+ IRAM(0x20000000-0x2001FFFF) IROM(0x8000000-0x807FFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4")
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ $$Device:STM32F446RETx$CMSIS\SVD\STM32F446x.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ tencentos\
+ NUCLEO_STM32F446RE
+ 1
+ 0
+ 1
+ 1
+ 1
+
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 0
+
+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4101
+
+ 1
+ STLink\ST-LINKIII-KEIL_SWO.dll
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M4"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 2
+ 0
+ 0
+ 0
+ 8
+ 1
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x20000
+
+
+ 1
+ 0x8000000
+ 0x80000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x8000000
+ 0x80000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x20000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 4
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+ USE_HAL_DRIVER,STM32F446xx
+
+ ../Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../../../arch/arm/arm-v7m/common/include;../../../arch/arm/arm-v7m/cortex-m4/armcc;../../../kernel/core/include;../../../kernel/pm/include;../../../osal/cmsis_os;../TOS_CONFIG
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Application/MDK-ARM
+
+
+ startup_stm32f446xx.s
+ 2
+ startup_stm32f446xx.s
+
+
+
+
+ Application/User
+
+
+ main.c
+ 1
+ ../Src/main.c
+
+
+ gpio.c
+ 1
+ ../Src/gpio.c
+
+
+ sys.c
+ 1
+ ../Src/sys.c
+
+
+ usart.c
+ 1
+ ../Src/usart.c
+
+
+ stm32f4xx_it.c
+ 1
+ ../Src/stm32f4xx_it.c
+
+
+ stm32f4xx_hal_msp.c
+ 1
+ ../Src/stm32f4xx_hal_msp.c
+
+
+
+
+ Drivers/STM32F4xx_HAL_Driver
+
+
+ stm32f4xx_hal_tim.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
+
+
+ stm32f4xx_hal_tim_ex.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
+
+
+ stm32f4xx_hal_uart.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
+
+
+ stm32f4xx_hal_rcc.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
+
+
+ stm32f4xx_hal_rcc_ex.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
+
+
+ stm32f4xx_hal_flash.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
+
+
+ stm32f4xx_hal_flash_ex.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
+
+
+ stm32f4xx_hal_flash_ramfunc.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
+
+
+ stm32f4xx_hal_gpio.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
+
+
+ stm32f4xx_hal_dma_ex.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
+
+
+ stm32f4xx_hal_dma.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
+
+
+ stm32f4xx_hal_pwr.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
+
+
+ stm32f4xx_hal_pwr_ex.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
+
+
+ stm32f4xx_hal_cortex.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
+
+
+ stm32f4xx_hal.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
+
+
+ stm32f4xx_hal_exti.c
+ 1
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
+
+
+
+
+ Drivers/CMSIS
+
+
+ system_stm32f4xx.c
+ 1
+ ../Src/system_stm32f4xx.c
+
+
+
+
+ tos/arch
+
+
+ tos_cpu.c
+ 1
+ ..\..\..\arch\arm\arm-v7m\common\tos_cpu.c
+
+
+ port_c.c
+ 1
+ ..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c
+
+
+ port_s.S
+ 2
+ ..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S
+
+
+
+
+ tos/kernel
+
+
+ tos_binary_heap.c
+ 1
+ ..\..\..\kernel\core\tos_binary_heap.c
+
+
+ tos_char_fifo.c
+ 1
+ ..\..\..\kernel\core\tos_char_fifo.c
+
+
+ tos_completion.c
+ 1
+ ..\..\..\kernel\core\tos_completion.c
+
+
+ tos_countdownlatch.c
+ 1
+ ..\..\..\kernel\core\tos_countdownlatch.c
+
+
+ tos_event.c
+ 1
+ ..\..\..\kernel\core\tos_event.c
+
+
+ tos_global.c
+ 1
+ ..\..\..\kernel\core\tos_global.c
+
+
+ tos_mail_queue.c
+ 1
+ ..\..\..\kernel\core\tos_mail_queue.c
+
+
+ tos_message_queue.c
+ 1
+ ..\..\..\kernel\core\tos_message_queue.c
+
+
+ tos_mmblk.c
+ 1
+ ..\..\..\kernel\core\tos_mmblk.c
+
+
+ tos_mmheap.c
+ 1
+ ..\..\..\kernel\core\tos_mmheap.c
+
+
+ tos_mutex.c
+ 1
+ ..\..\..\kernel\core\tos_mutex.c
+
+
+ tos_pend.c
+ 1
+ ..\..\..\kernel\core\tos_pend.c
+
+
+ tos_priority_mail_queue.c
+ 1
+ ..\..\..\kernel\core\tos_priority_mail_queue.c
+
+
+ tos_priority_message_queue.c
+ 1
+ ..\..\..\kernel\core\tos_priority_message_queue.c
+
+
+ tos_priority_queue.c
+ 1
+ ..\..\..\kernel\core\tos_priority_queue.c
+
+
+ tos_ring_queue.c
+ 1
+ ..\..\..\kernel\core\tos_ring_queue.c
+
+
+ tos_robin.c
+ 1
+ ..\..\..\kernel\core\tos_robin.c
+
+
+ tos_sched.c
+ 1
+ ..\..\..\kernel\core\tos_sched.c
+
+
+ tos_sem.c
+ 1
+ ..\..\..\kernel\core\tos_sem.c
+
+
+ tos_sys.c
+ 1
+ ..\..\..\kernel\core\tos_sys.c
+
+
+ tos_task.c
+ 1
+ ..\..\..\kernel\core\tos_task.c
+
+
+ tos_tick.c
+ 1
+ ..\..\..\kernel\core\tos_tick.c
+
+
+ tos_time.c
+ 1
+ ..\..\..\kernel\core\tos_time.c
+
+
+ tos_timer.c
+ 1
+ ..\..\..\kernel\core\tos_timer.c
+
+
+
+
+ tos/cmsis_os
+
+
+ cmsis_os.c
+ 1
+ ..\..\..\osal\cmsis_os\cmsis_os.c
+
+
+
+
+ TOS_CONFIG
+
+
+ tos_config.h
+ 5
+ ..\tos_config.h
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.build_log.htm b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.build_log.htm
new file mode 100644
index 00000000..e6ea9085
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.build_log.htm
@@ -0,0 +1,111 @@
+
+
+
+µVision Build Log
+Tool Versions:
+IDE-Version: ¦ÌVision V5.28.0.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: 1 luc, 1, LIC=UJWSB-2J7NB-JJ66S-LG5T2-3DTAU-TCK43
+
+Tool Versions:
+Toolchain: MDK-ARM Plus Version: 5.28.0.0
+Toolchain Path: E:\Keil_v5\ARM\ARMCC\Bin
+C Compiler: Armcc.exe V5.06 update 6 (build 750)
+Assembler: Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter: FromElf.exe V5.06 update 6 (build 750)
+CPU DLL: SARMCM3.DLL V5.28.0.0
+Dialog DLL: DCM.DLL V1.17.3.0
+Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.6.0
+Dialog DLL: TCM.DLL V1.36.2.0
+
+Project:
+G:\TencentOS\test1\board\STM32F446RE\MDK-ARM\tencentos.uvprojx
+Project File Date: 02/09/2020
+
+Output:
+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'E:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'NUCLEO_STM32F446RE'
+assembling startup_stm32f446xx.s...
+compiling sys.c...
+compiling gpio.c...
+compiling main.c...
+compiling stm32f4xx_hal_msp.c...
+compiling usart.c...
+compiling stm32f4xx_it.c...
+compiling stm32f4xx_hal_tim.c...
+compiling stm32f4xx_hal_tim_ex.c...
+compiling stm32f4xx_hal_uart.c...
+compiling stm32f4xx_hal_flash.c...
+compiling stm32f4xx_hal_rcc.c...
+compiling stm32f4xx_hal_rcc_ex.c...
+compiling stm32f4xx_hal_flash_ramfunc.c...
+compiling stm32f4xx_hal_flash_ex.c...
+compiling stm32f4xx_hal_gpio.c...
+compiling stm32f4xx_hal_pwr.c...
+compiling stm32f4xx_hal_dma.c...
+compiling stm32f4xx_hal_dma_ex.c...
+compiling stm32f4xx_hal.c...
+compiling stm32f4xx_hal_cortex.c...
+compiling stm32f4xx_hal_pwr_ex.c...
+compiling system_stm32f4xx.c...
+compiling stm32f4xx_hal_exti.c...
+assembling port_s.S...
+compiling tos_cpu.c...
+compiling port_c.c...
+compiling tos_binary_heap.c...
+compiling tos_char_fifo.c...
+compiling tos_completion.c...
+compiling tos_countdownlatch.c...
+compiling tos_event.c...
+compiling tos_global.c...
+compiling tos_message_queue.c...
+compiling tos_mail_queue.c...
+compiling tos_mmblk.c...
+compiling tos_mutex.c...
+compiling tos_mmheap.c...
+compiling tos_priority_message_queue.c...
+compiling tos_pend.c...
+compiling tos_priority_mail_queue.c...
+compiling tos_robin.c...
+compiling tos_priority_queue.c...
+compiling tos_ring_queue.c...
+compiling tos_sched.c...
+compiling tos_sem.c...
+compiling tos_sys.c...
+compiling tos_time.c...
+compiling tos_tick.c...
+compiling tos_task.c...
+compiling tos_timer.c...
+compiling cmsis_os.c...
+linking...
+Program Size: Code=9852 RO-data=596 RW-data=100 ZI-data=6092
+FromELF: creating hex file...
+"tencentos\NUCLEO_STM32F446RE.axf" - 0 Error(s), 0 Warning(s).
+
+Software Packages used:
+
+Package Vendor: ARM
+ http://www.keil.com/pack/ARM.CMSIS.5.5.1.pack
+ ARM.CMSIS.5.5.1
+ CMSIS (Cortex Microcontroller Software Interface Standard)
+ * Component: CORE Version: 5.2.0
+
+Package Vendor: Keil
+ http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.14.0.pack
+ Keil.STM32F4xx_DFP.2.14.0
+ STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
+
+Collection of Component include folders:
+ .\RTE\_NUCLEO_STM32F446RE
+ E:\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include
+ E:\Arm\Packs\Keil\STM32F4xx_DFP\2.14.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
+
+Collection of Component Files used:
+
+ * Component: ARM::CMSIS:CORE:5.2.0
+Build Time Elapsed: 00:03:13
+
+
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.htm b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.htm
new file mode 100644
index 00000000..9bf130e0
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.htm
@@ -0,0 +1,1696 @@
+
+
+Static Call Graph - [tencentos\NUCLEO_STM32F446RE.axf]
+
+Static Call Graph for image tencentos\NUCLEO_STM32F446RE.axf
+
#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Sun Feb 09 21:38:23 2020
+
+
Maximum Stack Usage = 168 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)
+Call chain for Maximum Stack Depth:
+main ⇒ SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
+Functions with no stack information
+
+
+
+
+Mutually Recursive functions
+
ADC_IRQHandler ⇒ ADC_IRQHandler
+ BusFault_Handler ⇒ BusFault_Handler
+ HardFault_Handler ⇒ HardFault_Handler
+ MemManage_Handler ⇒ MemManage_Handler
+ UsageFault_Handler ⇒ UsageFault_Handler
+ knl_idle_entry ⇒ knl_idle_entry
+
+
+
+Function Pointers
+
+ - ADC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- BusFault_Handler from stm32f4xx_it.o(i.BusFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_RX0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_TX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_RX0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_RX1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_SCE_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_TX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CEC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DCMI_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DebugMon_Handler from stm32f4xx_it.o(i.DebugMon_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI15_10_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI9_5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FLASH_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMPI2C1_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMPI2C1_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FPU_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- HardFault_Handler from stm32f4xx_it.o(i.HardFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- I2C1_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C1_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C2_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C2_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C3_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C3_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- MemManage_Handler from stm32f4xx_it.o(i.MemManage_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- NMI_Handler from stm32f4xx_it.o(i.NMI_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_FS_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_FS_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_EP1_IN_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_EP1_OUT_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- PVD_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- PendSV_Handler from port_s.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- QUADSPI_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RCC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RTC_Alarm_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RTC_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- Reset_Handler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SAI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SAI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SDIO_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPDIF_RX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SVC_Handler from stm32f4xx_it.o(i.SVC_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- SysTick_Handler from stm32f4xx_it.o(i.SysTick_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- SystemInit from system_stm32f4xx.o(i.SystemInit) referenced from startup_stm32f446xx.o(.text)
+
- TAMP_STAMP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_BRK_TIM9_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_CC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_TRG_COM_TIM11_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_UP_TIM10_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM6_DAC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_BRK_TIM12_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_CC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_TRG_COM_TIM14_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_UP_TIM13_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART_DMAAbortOnError from stm32f4xx_hal_uart.o(i.UART_DMAAbortOnError) referenced from stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler)
+
- USART1_IRQHandler from stm32f4xx_it.o(i.USART1_IRQHandler) referenced from startup_stm32f446xx.o(RESET)
+
- USART2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- USART3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- USART6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UsageFault_Handler from stm32f4xx_it.o(i.UsageFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- WWDG_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f446xx.o(.text)
+
- fputc from main.o(i.fputc) referenced from printf5.o(i.__0printf$5)
+
- knl_idle_entry from tos_sys.o(i.knl_idle_entry) referenced from tos_sys.o(i.knl_idle_init)
+
- main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
+
- task1 from main.o(i.task1) referenced from main.o(.constdata)
+
- task2 from main.o(i.task2) referenced from main.o(.constdata)
+
- task_exit from tos_task.o(i.task_exit) referenced from tos_task.o(i.tos_task_create)
+
+
+
+Global Symbols
+
+__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(.text)
+
+_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
+
+
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Calls]
+
+__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Called By]
+
+_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
+
+
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
+
+
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
+
+
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
+
+
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
+
+
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMPI2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMPI2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+QUADSPI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SAI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SAI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPDIF_RX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_UP_TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+port_int_disable (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text), UNUSED)
+
+
port_int_enable (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text), UNUSED)
+
+
port_cpsr_save (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_cpsr_restore (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
- >> tos_cpu_cpsr_restore
+
+
+port_clz (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_sched_start (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_context_switch (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_irq_context_switch (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
- >> cpu_irq_context_switch
+
+
+PendSV_Handler (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+__aeabi_uldivmod (Thumb, 98 bytes, Stack size 40 bytes, uldiv.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = __aeabi_uldivmod
+
+
[Calls]- >> __aeabi_llsr
+
- >> __aeabi_llsl
+
+
[Called By]- >> UART_SetConfig
+
- >> HAL_RCC_GetSysClockFreq
+
- >> cpu_init
+
- >> tos_millisec2tick
+
- >> _printf_core
+
+
+__aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
[Called By]
- >> _memset$wrapper
+
- >> __aeabi_memclr
+
+
+__aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
__aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
__aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
[Calls]
+
+__aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
+
[Called By]
- >> HAL_UART_MspInit
+
- >> MX_GPIO_Init
+
- >> SystemClock_Config
+
+
+__aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
_memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
+
[Calls]
+
+__aeabi_llsl (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
+
[Called By]
+
+_ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
+
+
__aeabi_llsr (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
+
[Called By]
+
+_ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
+
+
__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
+
[Calls]
- >> __main_after_scatterload
+
+
[Called By]
+
+__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
+
+
BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.BusFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.DebugMon_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+Error_Handler (Thumb, 2 bytes, Stack size 0 bytes, main.o(i.Error_Handler))
+
[Called By]
- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
+
+HAL_DMA_Abort_IT (Thumb, 36 bytes, Stack size 0 bytes, stm32f4xx_hal_dma.o(i.HAL_DMA_Abort_IT))
+
[Called By]
+
+HAL_Delay (Thumb, 32 bytes, Stack size 16 bytes, stm32f4xx_hal.o(i.HAL_Delay))
+
[Stack]
- Max Depth = 16
- Call Chain = HAL_Delay
+
+
[Calls]
+
[Called By]
+
+HAL_GPIO_Init (Thumb, 384 bytes, Stack size 40 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_Init))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_GPIO_Init
+
+
[Called By]- >> HAL_UART_MspInit
+
- >> MX_GPIO_Init
+
+
+HAL_GPIO_TogglePin (Thumb, 14 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_TogglePin))
+
[Called By]
+
+HAL_GPIO_WritePin (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_WritePin))
+
[Called By]
+
+HAL_GetTick (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_hal.o(i.HAL_GetTick))
+
[Called By]
- >> UART_WaitOnFlagUntilTimeout
+
- >> HAL_UART_Transmit
+
- >> HAL_RCC_ClockConfig
+
- >> HAL_Delay
+
- >> HAL_RCC_OscConfig
+
+
+HAL_IncTick (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_hal.o(i.HAL_IncTick))
+
[Called By]
+
+HAL_Init (Thumb, 48 bytes, Stack size 8 bytes, stm32f4xx_hal.o(i.HAL_Init))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_Init ⇒ HAL_InitTick ⇒ HAL_NVIC_SetPriority
+
+
[Calls]- >> HAL_MspInit
+
- >> HAL_InitTick
+
- >> HAL_NVIC_SetPriorityGrouping
+
+
[Called By]
+
+HAL_InitTick (Thumb, 54 bytes, Stack size 16 bytes, stm32f4xx_hal.o(i.HAL_InitTick))
+
[Stack]
- Max Depth = 32
- Call Chain = HAL_InitTick ⇒ HAL_NVIC_SetPriority
+
+
[Calls]- >> HAL_NVIC_SetPriority
+
- >> HAL_SYSTICK_Config
+
+
[Called By]- >> HAL_RCC_ClockConfig
+
- >> HAL_Init
+
+
+HAL_MspInit (Thumb, 42 bytes, Stack size 8 bytes, stm32f4xx_hal_msp.o(i.HAL_MspInit))
+
[Stack]
- Max Depth = 8
- Call Chain = HAL_MspInit
+
+
[Called By]
+
+HAL_NVIC_EnableIRQ (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_EnableIRQ))
+
[Called By]
+
+HAL_NVIC_SetPriority (Thumb, 60 bytes, Stack size 16 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_SetPriority))
+
[Stack]
- Max Depth = 16
- Call Chain = HAL_NVIC_SetPriority
+
+
[Calls]
+
[Called By]- >> HAL_UART_MspInit
+
- >> HAL_InitTick
+
+
+HAL_NVIC_SetPriorityGrouping (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_SetPriorityGrouping))
+
[Called By]
+
+HAL_RCC_ClockConfig (Thumb, 288 bytes, Stack size 32 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_ClockConfig))
+
[Stack]
- Max Depth = 80
- Call Chain = HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_GetSysClockFreq
+
- >> HAL_InitTick
+
- >> HAL_GetTick
+
+
[Called By]
+
+HAL_RCC_GetPCLK1Freq (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_GetPCLK1Freq))
+
[Called By]
+
+HAL_RCC_GetPCLK2Freq (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_GetPCLK2Freq))
+
[Called By]
+
+HAL_RCC_GetSysClockFreq (Thumb, 140 bytes, Stack size 8 bytes, stm32f4xx_hal_rcc_ex.o(i.HAL_RCC_GetSysClockFreq))
+
[Stack]
- Max Depth = 48
- Call Chain = HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]
+
[Called By]
+
+HAL_RCC_OscConfig (Thumb, 814 bytes, Stack size 40 bytes, stm32f4xx_hal_rcc_ex.o(i.HAL_RCC_OscConfig))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_RCC_OscConfig
+
+
[Calls]
+
[Called By]
+
+HAL_SYSTICK_Config (Thumb, 40 bytes, Stack size 8 bytes, stm32f4xx_hal_cortex.o(i.HAL_SYSTICK_Config))
+
[Stack]
- Max Depth = 8
- Call Chain = HAL_SYSTICK_Config
+
+
[Calls]
+
[Called By]
+
+HAL_UART_ErrorCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_ErrorCallback))
+
[Called By]
- >> UART_DMAAbortOnError
+
- >> HAL_UART_IRQHandler
+
+
+HAL_UART_IRQHandler (Thumb, 270 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler))
+
[Stack]
- Max Depth = 24
- Call Chain = HAL_UART_IRQHandler ⇒ UART_Receive_IT
+
+
[Calls]- >> UART_Transmit_IT
+
- >> UART_Receive_IT
+
- >> UART_EndRxTransfer
+
- >> HAL_UART_TxCpltCallback
+
- >> HAL_UART_ErrorCallback
+
- >> HAL_DMA_Abort_IT
+
+
[Called By]
+
+HAL_UART_Init (Thumb, 98 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_Init))
+
[Stack]
- Max Depth = 104
- Call Chain = HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> UART_SetConfig
+
- >> HAL_UART_MspInit
+
+
[Called By]- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
+
+HAL_UART_MspInit (Thumb, 188 bytes, Stack size 48 bytes, usart.o(i.HAL_UART_MspInit))
+
[Stack]
- Max Depth = 88
- Call Chain = HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_NVIC_SetPriority
+
- >> HAL_NVIC_EnableIRQ
+
- >> HAL_GPIO_Init
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+HAL_UART_RxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_RxCpltCallback))
+
[Called By]
+
+HAL_UART_Transmit (Thumb, 186 bytes, Stack size 32 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_Transmit))
+
[Stack]
- Max Depth = 56
- Call Chain = HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout
+
+
[Calls]- >> UART_WaitOnFlagUntilTimeout
+
- >> HAL_GetTick
+
+
[Called By]
+
+HAL_UART_TxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_TxCpltCallback))
+
[Called By]
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.HardFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+MX_GPIO_Init (Thumb, 182 bytes, Stack size 48 bytes, gpio.o(i.MX_GPIO_Init))
+
[Stack]
- Max Depth = 88
- Call Chain = MX_GPIO_Init ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_GPIO_WritePin
+
- >> HAL_GPIO_Init
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+MX_USART1_UART_Init (Thumb, 48 bytes, Stack size 8 bytes, usart.o(i.MX_USART1_UART_Init))
+
[Stack]
- Max Depth = 112
- Call Chain = MX_USART1_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_UART_Init
+
- >> Error_Handler
+
+
[Called By]
+
+MX_USART2_UART_Init (Thumb, 48 bytes, Stack size 8 bytes, usart.o(i.MX_USART2_UART_Init))
+
[Stack]
- Max Depth = 112
- Call Chain = MX_USART2_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_UART_Init
+
- >> Error_Handler
+
+
[Called By]
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.MemManage_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.NMI_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.SVC_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SysTick_Handler (Thumb, 32 bytes, Stack size 8 bytes, stm32f4xx_it.o(i.SysTick_Handler))
+
[Stack]
- Max Depth = 76 + Unknown Stack Size
+
- Call Chain = SysTick_Handler ⇒ tos_tick_handler ⇒ tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_tick_handler
+
- >> tos_knl_is_running
+
- >> tos_knl_irq_leave
+
- >> tos_knl_irq_enter
+
- >> HAL_IncTick
+
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+SystemClock_Config (Thumb, 124 bytes, Stack size 88 bytes, main.o(i.SystemClock_Config))
+
[Stack]
- Max Depth = 168
- Call Chain = SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_ClockConfig
+
- >> HAL_RCC_OscConfig
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+SystemInit (Thumb, 22 bytes, Stack size 0 bytes, system_stm32f4xx.o(i.SystemInit))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(.text)
+
+USART1_IRQHandler (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.USART1_IRQHandler))
+
[Stack]
- Max Depth = 24
- Call Chain = USART1_IRQHandler ⇒ HAL_UART_IRQHandler ⇒ UART_Receive_IT
+
+
[Calls]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.UsageFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+__0printf$5 (Thumb, 22 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5), UNUSED)
+
[Calls]
+
+__1printf$5 (Thumb, 0 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5), UNUSED)
+
+
__2printf (Thumb, 0 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5))
+
[Stack]
- Max Depth = 24
- Call Chain = __2printf
+
+
[Called By]
+
+__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
+
+
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
+
+
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
+
+
cpu_context_switch (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_context_switch))
+
[Calls]
+
[Called By]
+
+cpu_init (Thumb, 30 bytes, Stack size 8 bytes, tos_cpu.o(i.cpu_init))
+
[Stack]
- Max Depth = 48
- Call Chain = cpu_init ⇒ __aeabi_uldivmod
+
+
[Calls]- >> cpu_systick_init
+
- >> __aeabi_uldivmod
+
+
[Called By]
+
+cpu_irq_context_switch (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_irq_context_switch))
+
[Calls]
- >> port_irq_context_switch
+
+
[Called By]
+
+cpu_sched_start (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_sched_start))
+
[Calls]
+
[Called By]
+
+cpu_systick_init (Thumb, 20 bytes, Stack size 8 bytes, tos_cpu.o(i.cpu_systick_init))
+
[Stack]
- Max Depth = 16
- Call Chain = cpu_systick_init ⇒ port_systick_config
+
+
[Calls]- >> port_systick_priority_set
+
- >> port_systick_config
+
+
[Called By]
+
+cpu_task_stk_init (Thumb, 144 bytes, Stack size 12 bytes, tos_cpu.o(i.cpu_task_stk_init))
+
[Stack]
- Max Depth = 12
- Call Chain = cpu_task_stk_init
+
+
[Called By]
+
+fputc (Thumb, 40 bytes, Stack size 16 bytes, main.o(i.fputc))
+
[Stack]
- Max Depth = 72
- Call Chain = fputc ⇒ HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout
+
+
[Calls]
+
[Address Reference Count : 1]- printf5.o(i.__0printf$5)
+
+knl_idle_init (Thumb, 32 bytes, Stack size 24 bytes, tos_sys.o(i.knl_idle_init))
+
[Stack]
- Max Depth = 92 + Unknown Stack Size
+
- Call Chain = knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Called By]
+
+knl_is_idle (Thumb, 14 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_idle))
+
[Called By]
- >> task_do_destroy
+
- >> tos_task_create
+
+
+knl_is_inirq (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_inirq))
+
[Called By]
- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_destroy
+
- >> tos_task_delay
+
- >> tos_task_create
+
+
+knl_is_sched_locked (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_sched_locked))
+
[Called By]
- >> tos_task_destroy
+
- >> tos_task_delay
+
+
+knl_is_self (Thumb, 16 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_self))
+
[Called By]
- >> tos_task_prio_change
+
- >> tos_task_destroy
+
+
+knl_sched (Thumb, 64 bytes, Stack size 8 bytes, tos_sys.o(i.knl_sched))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = knl_sched
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_context_switch
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> tos_knl_sched_unlock
+
+
+main (Thumb, 58 bytes, Stack size 0 bytes, main.o(i.main))
+
[Stack]
- Max Depth = 168 + Unknown Stack Size
+
- Call Chain = main ⇒ SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> osThreadCreate
+
- >> osKernelStart
+
- >> osKernelInitialize
+
- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
- >> MX_GPIO_Init
+
- >> HAL_Init
+
- >> HAL_Delay
+
- >> SystemClock_Config
+
+
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
+
+mmheap_init_with_pool (Thumb, 22 bytes, Stack size 16 bytes, tos_mmheap.o(i.mmheap_init_with_pool))
+
[Stack]
- Max Depth = 80 + Unknown Stack Size
+
- Call Chain = mmheap_init_with_pool ⇒ tos_mmheap_pool_add ⇒ blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> mmheap_ctl_init
+
- >> tos_mmheap_pool_add
+
+
[Called By]
+
+mutex_release (Thumb, 20 bytes, Stack size 8 bytes, tos_mutex.o(i.mutex_release))
+
[Stack]
- Max Depth = 76 + Unknown Stack Size
+
- Call Chain = mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> pend_wakeup_all
+
- >> mutex_old_owner_release
+
+
[Called By]
+
+osDelay (Thumb, 32 bytes, Stack size 8 bytes, cmsis_os.o(i.osDelay))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_millisec2tick
+
- >> tos_task_delay
+
+
[Called By]
+
+osKernelInitialize (Thumb, 14 bytes, Stack size 8 bytes, cmsis_os.o(i.osKernelInitialize))
+
[Stack]
- Max Depth = 108 + Unknown Stack Size
+
- Call Chain = osKernelInitialize ⇒ tos_knl_init ⇒ knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_knl_init
+
+
[Called By]
+
+osKernelStart (Thumb, 14 bytes, Stack size 8 bytes, cmsis_os.o(i.osKernelStart))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = osKernelStart ⇒ tos_knl_start
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_knl_start
+
+
[Called By]
+
+osThreadCreate (Thumb, 50 bytes, Stack size 32 bytes, cmsis_os.o(i.osThreadCreate))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = osThreadCreate ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> priority_cmsis2knl
+
- >> tos_task_create
+
+
[Called By]
+
+pend_highest_pending_prio_get (Thumb, 18 bytes, Stack size 0 bytes, tos_pend.o(i.pend_highest_pending_prio_get))
+
[Called By]
- >> tos_task_prio_change
+
+
+pend_list_adjust (Thumb, 14 bytes, Stack size 0 bytes, tos_pend.o(i.pend_list_adjust))
+
[Stack]
- Max Depth = 8
- Call Chain = pend_list_adjust ⇒ pend_list_add
+
+
[Calls]
+
[Called By]- >> tos_task_prio_change
+
+
+pend_list_remove (Thumb, 22 bytes, Stack size 0 bytes, tos_pend.o(i.pend_list_remove))
+
[Called By]
- >> pend_task_wakeup
+
- >> task_do_destroy
+
+
+pend_task_wakeup (Thumb, 50 bytes, Stack size 8 bytes, tos_pend.o(i.pend_task_wakeup))
+
[Stack]
- Max Depth = 36 + Unknown Stack Size
+
- Call Chain = pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tick_list_remove
+
- >> readyqueue_add
+
- >> pend_list_remove
+
+
[Called By]- >> pend_wakeup_all
+
- >> tick_update
+
+
+pend_wakeup_all (Thumb, 36 bytes, Stack size 16 bytes, tos_pend.o(i.pend_wakeup_all))
+
[Stack]
- Max Depth = 52 + Unknown Stack Size
+
- Call Chain = pend_wakeup_all ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Called By]
+
+port_systick_config (Thumb, 34 bytes, Stack size 8 bytes, port_c.o(i.port_systick_config))
+
[Stack]
- Max Depth = 8
- Call Chain = port_systick_config
+
+
[Calls]
+
[Called By]
+
+port_systick_priority_set (Thumb, 10 bytes, Stack size 0 bytes, port_c.o(i.port_systick_priority_set))
+
[Calls]
+
[Called By]
+
+readyqueue_add (Thumb, 20 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_add))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
+
[Called By]
+
+readyqueue_add_head (Thumb, 36 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_add_head))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add_head ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add
+
- >> tos_task_prio_change
+
+
+readyqueue_add_tail (Thumb, 36 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_add_tail))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add
+
- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_create
+
+
+readyqueue_highest_ready_task_get (Thumb, 14 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_highest_ready_task_get))
+
[Called By]
- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_start
+
+
+readyqueue_init (Thumb, 48 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_init))
+
[Called By]
+
+readyqueue_remove (Thumb, 90 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_remove))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = readyqueue_remove
+
+
[Calls]
+
[Called By]- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
+
+task1 (Thumb, 34 bytes, Stack size 0 bytes, main.o(i.task1))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = task1 ⇒ osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> osDelay
+
- >> HAL_GPIO_TogglePin
+
- >> __2printf
+
+
[Address Reference Count : 1]
+task2 (Thumb, 24 bytes, Stack size 0 bytes, main.o(i.task2))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = task2 ⇒ osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> osDelay
+
- >> __2printf
+
+
[Address Reference Count : 1]
+task_free_all (Thumb, 56 bytes, Stack size 16 bytes, tos_task.o(i.task_free_all))
+
[Stack]
- Max Depth = 96 + Unknown Stack Size
+
- Call Chain = task_free_all ⇒ task_free ⇒ tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> task_free
+
+
[Called By]
+
+tick_list_add (Thumb, 18 bytes, Stack size 8 bytes, tos_tick.o(i.tick_list_add))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = tick_list_add ⇒ tick_task_place
+
+
[Calls]
+
[Called By]
+
+tick_list_remove (Thumb, 110 bytes, Stack size 24 bytes, tos_tick.o(i.tick_list_remove))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = tick_list_remove
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> tos_list_empty
+
+
[Called By]- >> pend_task_wakeup
+
- >> task_do_destroy
+
+
+tick_update (Thumb, 114 bytes, Stack size 24 bytes, tos_tick.o(i.tick_update))
+
[Stack]
- Max Depth = 60 + Unknown Stack Size
+
- Call Chain = tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> pend_task_wakeup
+
+
[Called By]
+
+timer_init (Thumb, 4 bytes, Stack size 0 bytes, tos_timer.o(i.timer_init))
+
[Called By]
+
+timer_update (Thumb, 118 bytes, Stack size 24 bytes, tos_timer.o(i.timer_update))
+
[Stack]
- Max Depth = 48 + Unknown Stack Size
+
- Call Chain = timer_update ⇒ timer_place
+
+
[Calls]- >> tos_knl_sched_lock
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tos_knl_sched_unlock
+
+
[Called By]
+
+tos_cpu_clz (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_clz))
+
[Calls]
+
[Called By]- >> __fls
+
- >> readyqueue_remove
+
+
+tos_cpu_cpsr_restore (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_cpsr_restore))
+
[Calls]
+
[Called By]- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_sched_lock
+
- >> tick_list_remove
+
- >> tos_task_prio_change
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tick_update
+
- >> tick_task_place
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> task_free_all
+
- >> tos_knl_sched_unlock
+
+
+tos_cpu_cpsr_save (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_cpsr_save))
+
[Calls]
+
[Called By]- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_sched_lock
+
- >> tick_list_remove
+
- >> tos_task_prio_change
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tick_update
+
- >> tick_task_place
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> task_free_all
+
- >> tos_knl_sched_unlock
+
+
+tos_knl_init (Thumb, 42 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_init))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = tos_knl_init ⇒ knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> cpu_init
+
- >> readyqueue_init
+
- >> mmheap_init_with_pool
+
- >> timer_init
+
- >> knl_idle_init
+
+
[Called By]
+
+tos_knl_irq_enter (Thumb, 22 bytes, Stack size 0 bytes, tos_sys.o(i.tos_knl_irq_enter))
+
[Called By]
+
+tos_knl_irq_leave (Thumb, 70 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_irq_leave))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_irq_leave
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_irq_context_switch
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]
+
+tos_knl_is_running (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.tos_knl_is_running))
+
[Called By]
- >> tos_tick_handler
+
- >> SysTick_Handler
+
- >> tos_task_create
+
+
+tos_knl_sched_lock (Thumb, 60 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_sched_lock))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_sched_lock
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+tos_knl_sched_unlock (Thumb, 62 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_sched_unlock))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = tos_knl_sched_unlock ⇒ knl_sched
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
+
[Called By]
+
+tos_knl_start (Thumb, 40 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_start))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_start
+
+
[Calls]- >> cpu_sched_start
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]
+
+tos_millisec2tick (Thumb, 18 bytes, Stack size 8 bytes, tos_time.o(i.tos_millisec2tick))
+
[Stack]
- Max Depth = 48
- Call Chain = tos_millisec2tick ⇒ __aeabi_uldivmod
+
+
[Calls]
+
[Called By]
+
+tos_mmheap_free (Thumb, 56 bytes, Stack size 16 bytes, tos_mmheap.o(i.tos_mmheap_free))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> blk_remove
+
- >> blk_merge_next
+
- >> blk_mark_as_free
+
- >> blk_insert
+
- >> blk_absorb
+
+
[Called By]
+
+tos_mmheap_pool_add (Thumb, 124 bytes, Stack size 16 bytes, tos_mmheap.o(i.tos_mmheap_pool_add))
+
[Stack]
- Max Depth = 64 + Unknown Stack Size
+
- Call Chain = tos_mmheap_pool_add ⇒ blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> mmheap_pool_is_exist
+
- >> blk_link_next
+
- >> blk_insert
+
+
[Called By]- >> mmheap_init_with_pool
+
+
+tos_task_create (Thumb, 188 bytes, Stack size 40 bytes, tos_task.o(i.tos_task_create))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_knl_is_running
+
- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_task_stk_init
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> task_reset
+
- >> knl_is_idle
+
+
[Called By]- >> osThreadCreate
+
- >> knl_idle_init
+
+
+tos_task_delay (Thumb, 92 bytes, Stack size 16 bytes, tos_task.o(i.tos_task_delay))
+
[Stack]
- Max Depth = 60 + Unknown Stack Size
+
- Call Chain = tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_sched_locked
+
- >> knl_is_inirq
+
- >> tick_list_add
+
- >> readyqueue_remove
+
- >> tos_task_yield
+
+
[Called By]
+
+tos_task_destroy (Thumb, 82 bytes, Stack size 8 bytes, tos_task.o(i.tos_task_destroy))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = tos_task_destroy ⇒ task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> knl_is_sched_locked
+
- >> knl_is_inirq
+
- >> knl_is_self
+
- >> task_do_destroy
+
+
[Called By]
+
+tos_task_prio_change (Thumb, 186 bytes, Stack size 24 bytes, tos_task.o(i.tos_task_prio_change))
+
[Stack]
- Max Depth = 52 + Unknown Stack Size
+
- Call Chain = tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
- >> readyqueue_remove
+
- >> pend_list_adjust
+
- >> pend_highest_pending_prio_get
+
- >> knl_is_self
+
+
[Called By]- >> mutex_old_owner_release
+
+
+tos_task_yield (Thumb, 46 bytes, Stack size 16 bytes, tos_task.o(i.tos_task_yield))
+
[Stack]
- Max Depth = 44 + Unknown Stack Size
+
- Call Chain = tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> readyqueue_remove
+
+
[Called By]
+
+tos_tick_handler (Thumb, 28 bytes, Stack size 8 bytes, tos_tick.o(i.tos_tick_handler))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = tos_tick_handler ⇒ tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_knl_is_running
+
- >> timer_update
+
- >> tick_update
+
+
[Called By]
+
+
+Local Symbols
+
+UART_DMAAbortOnError (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(i.UART_DMAAbortOnError))
+
[Stack]
- Max Depth = 8
- Call Chain = UART_DMAAbortOnError
+
+
[Calls]- >> HAL_UART_ErrorCallback
+
+
[Address Reference Count : 1]- stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler)
+
+UART_EndRxTransfer (Thumb, 28 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.UART_EndRxTransfer))
+
[Called By]
+
+UART_Receive_IT (Thumb, 150 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(i.UART_Receive_IT))
+
[Stack]
- Max Depth = 8
- Call Chain = UART_Receive_IT
+
+
[Calls]- >> HAL_UART_RxCpltCallback
+
+
[Called By]
+
+UART_SetConfig (Thumb, 286 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(i.UART_SetConfig))
+
[Stack]
- Max Depth = 64
- Call Chain = UART_SetConfig ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_GetPCLK2Freq
+
- >> HAL_RCC_GetPCLK1Freq
+
- >> __aeabi_uldivmod
+
+
[Called By]
+
+UART_Transmit_IT (Thumb, 98 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.UART_Transmit_IT))
+
[Called By]
+
+UART_WaitOnFlagUntilTimeout (Thumb, 100 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(i.UART_WaitOnFlagUntilTimeout))
+
[Stack]
- Max Depth = 24
- Call Chain = UART_WaitOnFlagUntilTimeout
+
+
[Calls]
+
[Called By]
+
+__NVIC_SetPriority (Thumb, 32 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.__NVIC_SetPriority))
+
[Called By]
- >> HAL_NVIC_SetPriority
+
- >> HAL_SYSTICK_Config
+
+
+__NVIC_SetPriority (Thumb, 32 bytes, Stack size 0 bytes, port_c.o(i.__NVIC_SetPriority))
+
[Called By]
- >> port_systick_priority_set
+
- >> port_systick_config
+
+
+__fls (Thumb, 12 bytes, Stack size 8 bytes, tos_mmheap.o(i.__fls))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __fls
+
+
[Calls]
+
[Called By]
+
+blk_absorb (Thumb, 28 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_absorb))
+
[Stack]
- Max Depth = 16
- Call Chain = blk_absorb ⇒ blk_link_next
+
+
[Calls]
+
[Called By]- >> blk_merge_next
+
- >> tos_mmheap_free
+
+
+blk_insert (Thumb, 74 bytes, Stack size 24 bytes, tos_mmheap.o(i.blk_insert))
+
[Stack]
- Max Depth = 48 + Unknown Stack Size
+
- Call Chain = blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]- >> tos_mmheap_free
+
- >> tos_mmheap_pool_add
+
+
+blk_link_next (Thumb, 12 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_link_next))
+
[Stack]
- Max Depth = 8
- Call Chain = blk_link_next
+
+
[Calls]
+
[Called By]- >> blk_mark_as_free
+
- >> blk_absorb
+
- >> tos_mmheap_pool_add
+
+
+blk_mark_as_free (Thumb, 26 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_mark_as_free))
+
[Stack]
- Max Depth = 16
- Call Chain = blk_mark_as_free ⇒ blk_link_next
+
+
[Calls]
+
[Called By]
+
+blk_merge_next (Thumb, 36 bytes, Stack size 16 bytes, tos_mmheap.o(i.blk_merge_next))
+
[Stack]
- Max Depth = 56 + Unknown Stack Size
+
- Call Chain = blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> blk_remove
+
- >> blk_next
+
- >> blk_absorb
+
+
[Called By]
+
+blk_next (Thumb, 16 bytes, Stack size 0 bytes, tos_mmheap.o(i.blk_next))
+
[Called By]
- >> blk_merge_next
+
- >> blk_link_next
+
+
+blk_remove (Thumb, 30 bytes, Stack size 16 bytes, tos_mmheap.o(i.blk_remove))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> remove_free_block
+
- >> mapping_insert
+
+
[Called By]- >> blk_merge_next
+
- >> tos_mmheap_free
+
+
+mapping_insert (Thumb, 44 bytes, Stack size 16 bytes, tos_mmheap.o(i.mapping_insert))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]- >> blk_remove
+
- >> blk_insert
+
+
+mmheap_ctl_init (Thumb, 70 bytes, Stack size 16 bytes, tos_mmheap.o(i.mmheap_ctl_init))
+
[Stack]
- Max Depth = 16
- Call Chain = mmheap_ctl_init
+
+
[Called By]- >> mmheap_init_with_pool
+
+
+mmheap_pool_is_exist (Thumb, 36 bytes, Stack size 8 bytes, tos_mmheap.o(i.mmheap_pool_is_exist))
+
[Stack]
- Max Depth = 8
- Call Chain = mmheap_pool_is_exist
+
+
[Called By]
+
+remove_free_block (Thumb, 68 bytes, Stack size 16 bytes, tos_mmheap.o(i.remove_free_block))
+
[Stack]
- Max Depth = 16
- Call Chain = remove_free_block
+
+
[Called By]
+
+mutex_old_owner_release (Thumb, 60 bytes, Stack size 16 bytes, tos_mutex.o(i.mutex_old_owner_release))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_task_prio_change
+
+
[Called By]
+
+pend_list_add (Thumb, 56 bytes, Stack size 8 bytes, tos_pend.o(i.pend_list_add))
+
[Stack]
- Max Depth = 8
- Call Chain = pend_list_add
+
+
[Called By]
+
+readyqueue_prio_mark (Thumb, 42 bytes, Stack size 12 bytes, tos_sched.o(i.readyqueue_prio_mark))
+
[Stack]
- Max Depth = 12
- Call Chain = readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
+
+knl_idle_entry (Thumb, 6 bytes, Stack size 0 bytes, tos_sys.o(i.knl_idle_entry))
+
[Stack]
- Max Depth = 96 + Unknown Stack Size
+ + In Cycle
+
- Call Chain = knl_idle_entry ⇒ knl_idle_entry (Cycle)
+
+
[Calls]- >> task_free_all
+
- >> knl_idle_entry
+
+
[Called By]
+
[Address Reference Count : 1]- tos_sys.o(i.knl_idle_init)
+
+task_do_destroy (Thumb, 122 bytes, Stack size 16 bytes, tos_task.o(i.task_do_destroy))
+
[Stack]
- Max Depth = 92 + Unknown Stack Size
+
- Call Chain = task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> tick_list_remove
+
- >> readyqueue_remove
+
- >> pend_list_remove
+
- >> mutex_release
+
- >> task_reset
+
- >> knl_is_idle
+
+
[Called By]
+
+task_exit (Thumb, 6 bytes, Stack size 0 bytes, tos_task.o(i.task_exit))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = task_exit ⇒ tos_task_destroy ⇒ task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Address Reference Count : 1]- tos_task.o(i.tos_task_create)
+
+task_free (Thumb, 20 bytes, Stack size 8 bytes, tos_task.o(i.task_free))
+
[Stack]
- Max Depth = 80 + Unknown Stack Size
+
- Call Chain = task_free ⇒ tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]
+
+task_reset (Thumb, 58 bytes, Stack size 0 bytes, tos_task.o(i.task_reset))
+
[Called By]
- >> task_do_destroy
+
- >> tos_task_create
+
+
+tick_task_place (Thumb, 150 bytes, Stack size 32 bytes, tos_tick.o(i.tick_task_place))
+
[Stack]
- Max Depth = 32 + Unknown Stack Size
+
- Call Chain = tick_task_place
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+tos_list_empty (Thumb, 14 bytes, Stack size 0 bytes, tos_tick.o(i.tos_list_empty))
+
[Called By]
+
+timer_place (Thumb, 100 bytes, Stack size 24 bytes, tos_timer.o(i.timer_place))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = timer_place
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+timer_takeoff (Thumb, 68 bytes, Stack size 16 bytes, tos_timer.o(i.timer_takeoff))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = timer_takeoff
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+errno_knl2cmsis (Thumb, 8 bytes, Stack size 0 bytes, cmsis_os.o(i.errno_knl2cmsis))
+
[Called By]
- >> osKernelStart
+
- >> osKernelInitialize
+
- >> osDelay
+
+
+priority_cmsis2knl (Thumb, 16 bytes, Stack size 0 bytes, cmsis_os.o(i.priority_cmsis2knl))
+
[Called By]
+
+_printf_core (Thumb, 658 bytes, Stack size 104 bytes, printf5.o(i._printf_core), UNUSED)
+
[Calls]
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.sct b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.sct
new file mode 100644
index 00000000..eab6f579
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/NUCLEO_STM32F446RE.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.htm b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.htm
new file mode 100644
index 00000000..13612ec4
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.htm
@@ -0,0 +1,1696 @@
+
+
+Static Call Graph - [tencentos\tencentos.axf]
+
+Static Call Graph for image tencentos\tencentos.axf
+
#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Tue Jan 28 00:06:54 2020
+
+
Maximum Stack Usage = 168 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)
+Call chain for Maximum Stack Depth:
+main ⇒ SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
+Functions with no stack information
+
+
+
+
+Mutually Recursive functions
+
ADC_IRQHandler ⇒ ADC_IRQHandler
+ BusFault_Handler ⇒ BusFault_Handler
+ HardFault_Handler ⇒ HardFault_Handler
+ MemManage_Handler ⇒ MemManage_Handler
+ UsageFault_Handler ⇒ UsageFault_Handler
+ knl_idle_entry ⇒ knl_idle_entry
+
+
+
+Function Pointers
+
+ - ADC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- BusFault_Handler from stm32f4xx_it.o(i.BusFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_RX0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_TX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_RX0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_RX1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_SCE_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_TX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CEC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DCMI_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DebugMon_Handler from stm32f4xx_it.o(i.DebugMon_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI15_10_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI9_5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FLASH_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMPI2C1_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMPI2C1_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FPU_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- HardFault_Handler from stm32f4xx_it.o(i.HardFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- I2C1_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C1_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C2_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C2_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C3_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C3_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- MemManage_Handler from stm32f4xx_it.o(i.MemManage_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- NMI_Handler from stm32f4xx_it.o(i.NMI_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_FS_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_FS_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_EP1_IN_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_EP1_OUT_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- PVD_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- PendSV_Handler from port_s.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- QUADSPI_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RCC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RTC_Alarm_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RTC_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- Reset_Handler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SAI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SAI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SDIO_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPDIF_RX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SVC_Handler from stm32f4xx_it.o(i.SVC_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- SysTick_Handler from stm32f4xx_it.o(i.SysTick_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- SystemInit from system_stm32f4xx.o(i.SystemInit) referenced from startup_stm32f446xx.o(.text)
+
- TAMP_STAMP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_BRK_TIM9_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_CC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_TRG_COM_TIM11_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_UP_TIM10_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM6_DAC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_BRK_TIM12_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_CC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_TRG_COM_TIM14_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_UP_TIM13_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART_DMAAbortOnError from stm32f4xx_hal_uart.o(i.UART_DMAAbortOnError) referenced from stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler)
+
- USART1_IRQHandler from stm32f4xx_it.o(i.USART1_IRQHandler) referenced from startup_stm32f446xx.o(RESET)
+
- USART2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- USART3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- USART6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UsageFault_Handler from stm32f4xx_it.o(i.UsageFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- WWDG_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f446xx.o(.text)
+
- fputc from main.o(i.fputc) referenced from printf5.o(i.__0printf$5)
+
- knl_idle_entry from tos_sys.o(i.knl_idle_entry) referenced from tos_sys.o(i.knl_idle_init)
+
- main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
+
- task1 from main.o(i.task1) referenced from main.o(.constdata)
+
- task2 from main.o(i.task2) referenced from main.o(.constdata)
+
- task_exit from tos_task.o(i.task_exit) referenced from tos_task.o(i.tos_task_create)
+
+
+
+Global Symbols
+
+__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(.text)
+
+_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
+
+
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Calls]
+
+__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Called By]
+
+_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
+
+
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
+
+
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
+
+
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
+
+
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
+
+
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMPI2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMPI2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+QUADSPI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SAI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SAI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPDIF_RX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_UP_TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+port_int_disable (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text), UNUSED)
+
+
port_int_enable (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text), UNUSED)
+
+
port_cpsr_save (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_cpsr_restore (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
- >> tos_cpu_cpsr_restore
+
+
+port_clz (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_sched_start (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_context_switch (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_irq_context_switch (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
- >> cpu_irq_context_switch
+
+
+PendSV_Handler (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+__aeabi_uldivmod (Thumb, 98 bytes, Stack size 40 bytes, uldiv.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = __aeabi_uldivmod
+
+
[Calls]- >> __aeabi_llsr
+
- >> __aeabi_llsl
+
+
[Called By]- >> UART_SetConfig
+
- >> HAL_RCC_GetSysClockFreq
+
- >> cpu_init
+
- >> tos_millisec2tick
+
- >> _printf_core
+
+
+__aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
[Called By]
- >> _memset$wrapper
+
- >> __aeabi_memclr
+
+
+__aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
__aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
__aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
[Calls]
+
+__aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
+
[Called By]
- >> HAL_UART_MspInit
+
- >> MX_GPIO_Init
+
- >> SystemClock_Config
+
+
+__aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
_memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
+
[Calls]
+
+__aeabi_llsl (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
+
[Called By]
+
+_ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
+
+
__aeabi_llsr (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
+
[Called By]
+
+_ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
+
+
__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
+
[Calls]
- >> __main_after_scatterload
+
+
[Called By]
+
+__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
+
+
BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.BusFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.DebugMon_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+Error_Handler (Thumb, 2 bytes, Stack size 0 bytes, main.o(i.Error_Handler))
+
[Called By]
- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
+
+HAL_DMA_Abort_IT (Thumb, 36 bytes, Stack size 0 bytes, stm32f4xx_hal_dma.o(i.HAL_DMA_Abort_IT))
+
[Called By]
+
+HAL_Delay (Thumb, 32 bytes, Stack size 16 bytes, stm32f4xx_hal.o(i.HAL_Delay))
+
[Stack]
- Max Depth = 16
- Call Chain = HAL_Delay
+
+
[Calls]
+
[Called By]
+
+HAL_GPIO_Init (Thumb, 384 bytes, Stack size 40 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_Init))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_GPIO_Init
+
+
[Called By]- >> HAL_UART_MspInit
+
- >> MX_GPIO_Init
+
+
+HAL_GPIO_TogglePin (Thumb, 14 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_TogglePin))
+
[Called By]
+
+HAL_GPIO_WritePin (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_WritePin))
+
[Called By]
+
+HAL_GetTick (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_hal.o(i.HAL_GetTick))
+
[Called By]
- >> UART_WaitOnFlagUntilTimeout
+
- >> HAL_UART_Transmit
+
- >> HAL_RCC_ClockConfig
+
- >> HAL_Delay
+
- >> HAL_RCC_OscConfig
+
+
+HAL_IncTick (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_hal.o(i.HAL_IncTick))
+
[Called By]
+
+HAL_Init (Thumb, 48 bytes, Stack size 8 bytes, stm32f4xx_hal.o(i.HAL_Init))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_Init ⇒ HAL_InitTick ⇒ HAL_NVIC_SetPriority
+
+
[Calls]- >> HAL_MspInit
+
- >> HAL_InitTick
+
- >> HAL_NVIC_SetPriorityGrouping
+
+
[Called By]
+
+HAL_InitTick (Thumb, 54 bytes, Stack size 16 bytes, stm32f4xx_hal.o(i.HAL_InitTick))
+
[Stack]
- Max Depth = 32
- Call Chain = HAL_InitTick ⇒ HAL_NVIC_SetPriority
+
+
[Calls]- >> HAL_NVIC_SetPriority
+
- >> HAL_SYSTICK_Config
+
+
[Called By]- >> HAL_RCC_ClockConfig
+
- >> HAL_Init
+
+
+HAL_MspInit (Thumb, 42 bytes, Stack size 8 bytes, stm32f4xx_hal_msp.o(i.HAL_MspInit))
+
[Stack]
- Max Depth = 8
- Call Chain = HAL_MspInit
+
+
[Called By]
+
+HAL_NVIC_EnableIRQ (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_EnableIRQ))
+
[Called By]
+
+HAL_NVIC_SetPriority (Thumb, 60 bytes, Stack size 16 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_SetPriority))
+
[Stack]
- Max Depth = 16
- Call Chain = HAL_NVIC_SetPriority
+
+
[Calls]
+
[Called By]- >> HAL_UART_MspInit
+
- >> HAL_InitTick
+
+
+HAL_NVIC_SetPriorityGrouping (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_SetPriorityGrouping))
+
[Called By]
+
+HAL_RCC_ClockConfig (Thumb, 288 bytes, Stack size 32 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_ClockConfig))
+
[Stack]
- Max Depth = 80
- Call Chain = HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_GetSysClockFreq
+
- >> HAL_InitTick
+
- >> HAL_GetTick
+
+
[Called By]
+
+HAL_RCC_GetPCLK1Freq (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_GetPCLK1Freq))
+
[Called By]
+
+HAL_RCC_GetPCLK2Freq (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_GetPCLK2Freq))
+
[Called By]
+
+HAL_RCC_GetSysClockFreq (Thumb, 140 bytes, Stack size 8 bytes, stm32f4xx_hal_rcc_ex.o(i.HAL_RCC_GetSysClockFreq))
+
[Stack]
- Max Depth = 48
- Call Chain = HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]
+
[Called By]
+
+HAL_RCC_OscConfig (Thumb, 814 bytes, Stack size 40 bytes, stm32f4xx_hal_rcc_ex.o(i.HAL_RCC_OscConfig))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_RCC_OscConfig
+
+
[Calls]
+
[Called By]
+
+HAL_SYSTICK_Config (Thumb, 40 bytes, Stack size 8 bytes, stm32f4xx_hal_cortex.o(i.HAL_SYSTICK_Config))
+
[Stack]
- Max Depth = 8
- Call Chain = HAL_SYSTICK_Config
+
+
[Calls]
+
[Called By]
+
+HAL_UART_ErrorCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_ErrorCallback))
+
[Called By]
- >> UART_DMAAbortOnError
+
- >> HAL_UART_IRQHandler
+
+
+HAL_UART_IRQHandler (Thumb, 270 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler))
+
[Stack]
- Max Depth = 24
- Call Chain = HAL_UART_IRQHandler ⇒ UART_Receive_IT
+
+
[Calls]- >> UART_Transmit_IT
+
- >> UART_Receive_IT
+
- >> UART_EndRxTransfer
+
- >> HAL_UART_TxCpltCallback
+
- >> HAL_UART_ErrorCallback
+
- >> HAL_DMA_Abort_IT
+
+
[Called By]
+
+HAL_UART_Init (Thumb, 98 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_Init))
+
[Stack]
- Max Depth = 104
- Call Chain = HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> UART_SetConfig
+
- >> HAL_UART_MspInit
+
+
[Called By]- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
+
+HAL_UART_MspInit (Thumb, 188 bytes, Stack size 48 bytes, usart.o(i.HAL_UART_MspInit))
+
[Stack]
- Max Depth = 88
- Call Chain = HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_NVIC_SetPriority
+
- >> HAL_NVIC_EnableIRQ
+
- >> HAL_GPIO_Init
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+HAL_UART_RxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_RxCpltCallback))
+
[Called By]
+
+HAL_UART_Transmit (Thumb, 186 bytes, Stack size 32 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_Transmit))
+
[Stack]
- Max Depth = 56
- Call Chain = HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout
+
+
[Calls]- >> UART_WaitOnFlagUntilTimeout
+
- >> HAL_GetTick
+
+
[Called By]
+
+HAL_UART_TxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_TxCpltCallback))
+
[Called By]
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.HardFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+MX_GPIO_Init (Thumb, 182 bytes, Stack size 48 bytes, gpio.o(i.MX_GPIO_Init))
+
[Stack]
- Max Depth = 88
- Call Chain = MX_GPIO_Init ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_GPIO_WritePin
+
- >> HAL_GPIO_Init
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+MX_USART1_UART_Init (Thumb, 48 bytes, Stack size 8 bytes, usart.o(i.MX_USART1_UART_Init))
+
[Stack]
- Max Depth = 112
- Call Chain = MX_USART1_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_UART_Init
+
- >> Error_Handler
+
+
[Called By]
+
+MX_USART2_UART_Init (Thumb, 48 bytes, Stack size 8 bytes, usart.o(i.MX_USART2_UART_Init))
+
[Stack]
- Max Depth = 112
- Call Chain = MX_USART2_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_UART_Init
+
- >> Error_Handler
+
+
[Called By]
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.MemManage_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.NMI_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.SVC_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SysTick_Handler (Thumb, 32 bytes, Stack size 8 bytes, stm32f4xx_it.o(i.SysTick_Handler))
+
[Stack]
- Max Depth = 76 + Unknown Stack Size
+
- Call Chain = SysTick_Handler ⇒ tos_tick_handler ⇒ tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_tick_handler
+
- >> tos_knl_is_running
+
- >> tos_knl_irq_leave
+
- >> tos_knl_irq_enter
+
- >> HAL_IncTick
+
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+SystemClock_Config (Thumb, 124 bytes, Stack size 88 bytes, main.o(i.SystemClock_Config))
+
[Stack]
- Max Depth = 168
- Call Chain = SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_ClockConfig
+
- >> HAL_RCC_OscConfig
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+SystemInit (Thumb, 22 bytes, Stack size 0 bytes, system_stm32f4xx.o(i.SystemInit))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(.text)
+
+USART1_IRQHandler (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.USART1_IRQHandler))
+
[Stack]
- Max Depth = 24
- Call Chain = USART1_IRQHandler ⇒ HAL_UART_IRQHandler ⇒ UART_Receive_IT
+
+
[Calls]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.UsageFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+__0printf$5 (Thumb, 22 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5), UNUSED)
+
[Calls]
+
+__1printf$5 (Thumb, 0 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5), UNUSED)
+
+
__2printf (Thumb, 0 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5))
+
[Stack]
- Max Depth = 24
- Call Chain = __2printf
+
+
[Called By]
+
+__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
+
+
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
+
+
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
+
+
cpu_context_switch (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_context_switch))
+
[Calls]
+
[Called By]
+
+cpu_init (Thumb, 30 bytes, Stack size 8 bytes, tos_cpu.o(i.cpu_init))
+
[Stack]
- Max Depth = 48
- Call Chain = cpu_init ⇒ __aeabi_uldivmod
+
+
[Calls]- >> cpu_systick_init
+
- >> __aeabi_uldivmod
+
+
[Called By]
+
+cpu_irq_context_switch (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_irq_context_switch))
+
[Calls]
- >> port_irq_context_switch
+
+
[Called By]
+
+cpu_sched_start (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_sched_start))
+
[Calls]
+
[Called By]
+
+cpu_systick_init (Thumb, 20 bytes, Stack size 8 bytes, tos_cpu.o(i.cpu_systick_init))
+
[Stack]
- Max Depth = 16
- Call Chain = cpu_systick_init ⇒ port_systick_config
+
+
[Calls]- >> port_systick_priority_set
+
- >> port_systick_config
+
+
[Called By]
+
+cpu_task_stk_init (Thumb, 144 bytes, Stack size 12 bytes, tos_cpu.o(i.cpu_task_stk_init))
+
[Stack]
- Max Depth = 12
- Call Chain = cpu_task_stk_init
+
+
[Called By]
+
+fputc (Thumb, 40 bytes, Stack size 16 bytes, main.o(i.fputc))
+
[Stack]
- Max Depth = 72
- Call Chain = fputc ⇒ HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout
+
+
[Calls]
+
[Address Reference Count : 1]- printf5.o(i.__0printf$5)
+
+knl_idle_init (Thumb, 32 bytes, Stack size 24 bytes, tos_sys.o(i.knl_idle_init))
+
[Stack]
- Max Depth = 92 + Unknown Stack Size
+
- Call Chain = knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Called By]
+
+knl_is_idle (Thumb, 14 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_idle))
+
[Called By]
- >> task_do_destroy
+
- >> tos_task_create
+
+
+knl_is_inirq (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_inirq))
+
[Called By]
- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_destroy
+
- >> tos_task_delay
+
- >> tos_task_create
+
+
+knl_is_sched_locked (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_sched_locked))
+
[Called By]
- >> tos_task_destroy
+
- >> tos_task_delay
+
+
+knl_is_self (Thumb, 16 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_self))
+
[Called By]
- >> tos_task_prio_change
+
- >> tos_task_destroy
+
+
+knl_sched (Thumb, 64 bytes, Stack size 8 bytes, tos_sys.o(i.knl_sched))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = knl_sched
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_context_switch
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> tos_knl_sched_unlock
+
+
+main (Thumb, 58 bytes, Stack size 0 bytes, main.o(i.main))
+
[Stack]
- Max Depth = 168 + Unknown Stack Size
+
- Call Chain = main ⇒ SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> osThreadCreate
+
- >> osKernelStart
+
- >> osKernelInitialize
+
- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
- >> MX_GPIO_Init
+
- >> HAL_Init
+
- >> HAL_Delay
+
- >> SystemClock_Config
+
+
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
+
+mmheap_init_with_pool (Thumb, 22 bytes, Stack size 16 bytes, tos_mmheap.o(i.mmheap_init_with_pool))
+
[Stack]
- Max Depth = 80 + Unknown Stack Size
+
- Call Chain = mmheap_init_with_pool ⇒ tos_mmheap_pool_add ⇒ blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> mmheap_ctl_init
+
- >> tos_mmheap_pool_add
+
+
[Called By]
+
+mutex_release (Thumb, 20 bytes, Stack size 8 bytes, tos_mutex.o(i.mutex_release))
+
[Stack]
- Max Depth = 76 + Unknown Stack Size
+
- Call Chain = mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> pend_wakeup_all
+
- >> mutex_old_owner_release
+
+
[Called By]
+
+osDelay (Thumb, 32 bytes, Stack size 8 bytes, cmsis_os.o(i.osDelay))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_millisec2tick
+
- >> tos_task_delay
+
+
[Called By]
+
+osKernelInitialize (Thumb, 14 bytes, Stack size 8 bytes, cmsis_os.o(i.osKernelInitialize))
+
[Stack]
- Max Depth = 108 + Unknown Stack Size
+
- Call Chain = osKernelInitialize ⇒ tos_knl_init ⇒ knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_knl_init
+
+
[Called By]
+
+osKernelStart (Thumb, 14 bytes, Stack size 8 bytes, cmsis_os.o(i.osKernelStart))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = osKernelStart ⇒ tos_knl_start
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_knl_start
+
+
[Called By]
+
+osThreadCreate (Thumb, 50 bytes, Stack size 32 bytes, cmsis_os.o(i.osThreadCreate))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = osThreadCreate ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> priority_cmsis2knl
+
- >> tos_task_create
+
+
[Called By]
+
+pend_highest_pending_prio_get (Thumb, 18 bytes, Stack size 0 bytes, tos_pend.o(i.pend_highest_pending_prio_get))
+
[Called By]
- >> tos_task_prio_change
+
+
+pend_list_adjust (Thumb, 14 bytes, Stack size 0 bytes, tos_pend.o(i.pend_list_adjust))
+
[Stack]
- Max Depth = 8
- Call Chain = pend_list_adjust ⇒ pend_list_add
+
+
[Calls]
+
[Called By]- >> tos_task_prio_change
+
+
+pend_list_remove (Thumb, 22 bytes, Stack size 0 bytes, tos_pend.o(i.pend_list_remove))
+
[Called By]
- >> pend_task_wakeup
+
- >> task_do_destroy
+
+
+pend_task_wakeup (Thumb, 50 bytes, Stack size 8 bytes, tos_pend.o(i.pend_task_wakeup))
+
[Stack]
- Max Depth = 36 + Unknown Stack Size
+
- Call Chain = pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tick_list_remove
+
- >> readyqueue_add
+
- >> pend_list_remove
+
+
[Called By]- >> pend_wakeup_all
+
- >> tick_update
+
+
+pend_wakeup_all (Thumb, 36 bytes, Stack size 16 bytes, tos_pend.o(i.pend_wakeup_all))
+
[Stack]
- Max Depth = 52 + Unknown Stack Size
+
- Call Chain = pend_wakeup_all ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Called By]
+
+port_systick_config (Thumb, 34 bytes, Stack size 8 bytes, port_c.o(i.port_systick_config))
+
[Stack]
- Max Depth = 8
- Call Chain = port_systick_config
+
+
[Calls]
+
[Called By]
+
+port_systick_priority_set (Thumb, 10 bytes, Stack size 0 bytes, port_c.o(i.port_systick_priority_set))
+
[Calls]
+
[Called By]
+
+readyqueue_add (Thumb, 20 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_add))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
+
[Called By]
+
+readyqueue_add_head (Thumb, 36 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_add_head))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add_head ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add
+
- >> tos_task_prio_change
+
+
+readyqueue_add_tail (Thumb, 36 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_add_tail))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add
+
- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_create
+
+
+readyqueue_highest_ready_task_get (Thumb, 14 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_highest_ready_task_get))
+
[Called By]
- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_start
+
+
+readyqueue_init (Thumb, 48 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_init))
+
[Called By]
+
+readyqueue_remove (Thumb, 90 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_remove))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = readyqueue_remove
+
+
[Calls]
+
[Called By]- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
+
+task1 (Thumb, 34 bytes, Stack size 0 bytes, main.o(i.task1))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = task1 ⇒ osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> osDelay
+
- >> HAL_GPIO_TogglePin
+
- >> __2printf
+
+
[Address Reference Count : 1]
+task2 (Thumb, 24 bytes, Stack size 0 bytes, main.o(i.task2))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = task2 ⇒ osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> osDelay
+
- >> __2printf
+
+
[Address Reference Count : 1]
+task_free_all (Thumb, 56 bytes, Stack size 16 bytes, tos_task.o(i.task_free_all))
+
[Stack]
- Max Depth = 96 + Unknown Stack Size
+
- Call Chain = task_free_all ⇒ task_free ⇒ tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> task_free
+
+
[Called By]
+
+tick_list_add (Thumb, 18 bytes, Stack size 8 bytes, tos_tick.o(i.tick_list_add))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = tick_list_add ⇒ tick_task_place
+
+
[Calls]
+
[Called By]
+
+tick_list_remove (Thumb, 110 bytes, Stack size 24 bytes, tos_tick.o(i.tick_list_remove))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = tick_list_remove
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> tos_list_empty
+
+
[Called By]- >> pend_task_wakeup
+
- >> task_do_destroy
+
+
+tick_update (Thumb, 114 bytes, Stack size 24 bytes, tos_tick.o(i.tick_update))
+
[Stack]
- Max Depth = 60 + Unknown Stack Size
+
- Call Chain = tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> pend_task_wakeup
+
+
[Called By]
+
+timer_init (Thumb, 4 bytes, Stack size 0 bytes, tos_timer.o(i.timer_init))
+
[Called By]
+
+timer_update (Thumb, 118 bytes, Stack size 24 bytes, tos_timer.o(i.timer_update))
+
[Stack]
- Max Depth = 48 + Unknown Stack Size
+
- Call Chain = timer_update ⇒ timer_place
+
+
[Calls]- >> tos_knl_sched_lock
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tos_knl_sched_unlock
+
+
[Called By]
+
+tos_cpu_clz (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_clz))
+
[Calls]
+
[Called By]- >> __fls
+
- >> readyqueue_remove
+
+
+tos_cpu_cpsr_restore (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_cpsr_restore))
+
[Calls]
+
[Called By]- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_sched_lock
+
- >> tick_list_remove
+
- >> tos_task_prio_change
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tick_update
+
- >> tick_task_place
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> task_free_all
+
- >> tos_knl_sched_unlock
+
+
+tos_cpu_cpsr_save (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_cpsr_save))
+
[Calls]
+
[Called By]- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_sched_lock
+
- >> tick_list_remove
+
- >> tos_task_prio_change
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tick_update
+
- >> tick_task_place
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> task_free_all
+
- >> tos_knl_sched_unlock
+
+
+tos_knl_init (Thumb, 42 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_init))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = tos_knl_init ⇒ knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> cpu_init
+
- >> readyqueue_init
+
- >> mmheap_init_with_pool
+
- >> timer_init
+
- >> knl_idle_init
+
+
[Called By]
+
+tos_knl_irq_enter (Thumb, 22 bytes, Stack size 0 bytes, tos_sys.o(i.tos_knl_irq_enter))
+
[Called By]
+
+tos_knl_irq_leave (Thumb, 70 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_irq_leave))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_irq_leave
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_irq_context_switch
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]
+
+tos_knl_is_running (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.tos_knl_is_running))
+
[Called By]
- >> tos_tick_handler
+
- >> SysTick_Handler
+
- >> tos_task_create
+
+
+tos_knl_sched_lock (Thumb, 60 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_sched_lock))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_sched_lock
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+tos_knl_sched_unlock (Thumb, 62 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_sched_unlock))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = tos_knl_sched_unlock ⇒ knl_sched
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
+
[Called By]
+
+tos_knl_start (Thumb, 40 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_start))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_start
+
+
[Calls]- >> cpu_sched_start
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]
+
+tos_millisec2tick (Thumb, 18 bytes, Stack size 8 bytes, tos_time.o(i.tos_millisec2tick))
+
[Stack]
- Max Depth = 48
- Call Chain = tos_millisec2tick ⇒ __aeabi_uldivmod
+
+
[Calls]
+
[Called By]
+
+tos_mmheap_free (Thumb, 56 bytes, Stack size 16 bytes, tos_mmheap.o(i.tos_mmheap_free))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> blk_remove
+
- >> blk_merge_next
+
- >> blk_mark_as_free
+
- >> blk_insert
+
- >> blk_absorb
+
+
[Called By]
+
+tos_mmheap_pool_add (Thumb, 124 bytes, Stack size 16 bytes, tos_mmheap.o(i.tos_mmheap_pool_add))
+
[Stack]
- Max Depth = 64 + Unknown Stack Size
+
- Call Chain = tos_mmheap_pool_add ⇒ blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> mmheap_pool_is_exist
+
- >> blk_link_next
+
- >> blk_insert
+
+
[Called By]- >> mmheap_init_with_pool
+
+
+tos_task_create (Thumb, 188 bytes, Stack size 40 bytes, tos_task.o(i.tos_task_create))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_knl_is_running
+
- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_task_stk_init
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> task_reset
+
- >> knl_is_idle
+
+
[Called By]- >> osThreadCreate
+
- >> knl_idle_init
+
+
+tos_task_delay (Thumb, 92 bytes, Stack size 16 bytes, tos_task.o(i.tos_task_delay))
+
[Stack]
- Max Depth = 60 + Unknown Stack Size
+
- Call Chain = tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_sched_locked
+
- >> knl_is_inirq
+
- >> tick_list_add
+
- >> readyqueue_remove
+
- >> tos_task_yield
+
+
[Called By]
+
+tos_task_destroy (Thumb, 82 bytes, Stack size 8 bytes, tos_task.o(i.tos_task_destroy))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = tos_task_destroy ⇒ task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> knl_is_sched_locked
+
- >> knl_is_inirq
+
- >> knl_is_self
+
- >> task_do_destroy
+
+
[Called By]
+
+tos_task_prio_change (Thumb, 186 bytes, Stack size 24 bytes, tos_task.o(i.tos_task_prio_change))
+
[Stack]
- Max Depth = 52 + Unknown Stack Size
+
- Call Chain = tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
- >> readyqueue_remove
+
- >> pend_list_adjust
+
- >> pend_highest_pending_prio_get
+
- >> knl_is_self
+
+
[Called By]- >> mutex_old_owner_release
+
+
+tos_task_yield (Thumb, 46 bytes, Stack size 16 bytes, tos_task.o(i.tos_task_yield))
+
[Stack]
- Max Depth = 44 + Unknown Stack Size
+
- Call Chain = tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> readyqueue_remove
+
+
[Called By]
+
+tos_tick_handler (Thumb, 28 bytes, Stack size 8 bytes, tos_tick.o(i.tos_tick_handler))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = tos_tick_handler ⇒ tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_knl_is_running
+
- >> timer_update
+
- >> tick_update
+
+
[Called By]
+
+
+Local Symbols
+
+UART_DMAAbortOnError (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(i.UART_DMAAbortOnError))
+
[Stack]
- Max Depth = 8
- Call Chain = UART_DMAAbortOnError
+
+
[Calls]- >> HAL_UART_ErrorCallback
+
+
[Address Reference Count : 1]- stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler)
+
+UART_EndRxTransfer (Thumb, 28 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.UART_EndRxTransfer))
+
[Called By]
+
+UART_Receive_IT (Thumb, 150 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(i.UART_Receive_IT))
+
[Stack]
- Max Depth = 8
- Call Chain = UART_Receive_IT
+
+
[Calls]- >> HAL_UART_RxCpltCallback
+
+
[Called By]
+
+UART_SetConfig (Thumb, 286 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(i.UART_SetConfig))
+
[Stack]
- Max Depth = 64
- Call Chain = UART_SetConfig ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_GetPCLK2Freq
+
- >> HAL_RCC_GetPCLK1Freq
+
- >> __aeabi_uldivmod
+
+
[Called By]
+
+UART_Transmit_IT (Thumb, 98 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.UART_Transmit_IT))
+
[Called By]
+
+UART_WaitOnFlagUntilTimeout (Thumb, 100 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(i.UART_WaitOnFlagUntilTimeout))
+
[Stack]
- Max Depth = 24
- Call Chain = UART_WaitOnFlagUntilTimeout
+
+
[Calls]
+
[Called By]
+
+__NVIC_SetPriority (Thumb, 32 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.__NVIC_SetPriority))
+
[Called By]
- >> HAL_NVIC_SetPriority
+
- >> HAL_SYSTICK_Config
+
+
+__NVIC_SetPriority (Thumb, 32 bytes, Stack size 0 bytes, port_c.o(i.__NVIC_SetPriority))
+
[Called By]
- >> port_systick_priority_set
+
- >> port_systick_config
+
+
+__fls (Thumb, 12 bytes, Stack size 8 bytes, tos_mmheap.o(i.__fls))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __fls
+
+
[Calls]
+
[Called By]
+
+blk_absorb (Thumb, 28 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_absorb))
+
[Stack]
- Max Depth = 16
- Call Chain = blk_absorb ⇒ blk_link_next
+
+
[Calls]
+
[Called By]- >> blk_merge_next
+
- >> tos_mmheap_free
+
+
+blk_insert (Thumb, 74 bytes, Stack size 24 bytes, tos_mmheap.o(i.blk_insert))
+
[Stack]
- Max Depth = 48 + Unknown Stack Size
+
- Call Chain = blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]- >> tos_mmheap_free
+
- >> tos_mmheap_pool_add
+
+
+blk_link_next (Thumb, 12 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_link_next))
+
[Stack]
- Max Depth = 8
- Call Chain = blk_link_next
+
+
[Calls]
+
[Called By]- >> blk_mark_as_free
+
- >> blk_absorb
+
- >> tos_mmheap_pool_add
+
+
+blk_mark_as_free (Thumb, 26 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_mark_as_free))
+
[Stack]
- Max Depth = 16
- Call Chain = blk_mark_as_free ⇒ blk_link_next
+
+
[Calls]
+
[Called By]
+
+blk_merge_next (Thumb, 36 bytes, Stack size 16 bytes, tos_mmheap.o(i.blk_merge_next))
+
[Stack]
- Max Depth = 56 + Unknown Stack Size
+
- Call Chain = blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> blk_remove
+
- >> blk_next
+
- >> blk_absorb
+
+
[Called By]
+
+blk_next (Thumb, 16 bytes, Stack size 0 bytes, tos_mmheap.o(i.blk_next))
+
[Called By]
- >> blk_merge_next
+
- >> blk_link_next
+
+
+blk_remove (Thumb, 30 bytes, Stack size 16 bytes, tos_mmheap.o(i.blk_remove))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> remove_free_block
+
- >> mapping_insert
+
+
[Called By]- >> blk_merge_next
+
- >> tos_mmheap_free
+
+
+mapping_insert (Thumb, 44 bytes, Stack size 16 bytes, tos_mmheap.o(i.mapping_insert))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]- >> blk_remove
+
- >> blk_insert
+
+
+mmheap_ctl_init (Thumb, 70 bytes, Stack size 16 bytes, tos_mmheap.o(i.mmheap_ctl_init))
+
[Stack]
- Max Depth = 16
- Call Chain = mmheap_ctl_init
+
+
[Called By]- >> mmheap_init_with_pool
+
+
+mmheap_pool_is_exist (Thumb, 36 bytes, Stack size 8 bytes, tos_mmheap.o(i.mmheap_pool_is_exist))
+
[Stack]
- Max Depth = 8
- Call Chain = mmheap_pool_is_exist
+
+
[Called By]
+
+remove_free_block (Thumb, 68 bytes, Stack size 16 bytes, tos_mmheap.o(i.remove_free_block))
+
[Stack]
- Max Depth = 16
- Call Chain = remove_free_block
+
+
[Called By]
+
+mutex_old_owner_release (Thumb, 60 bytes, Stack size 16 bytes, tos_mutex.o(i.mutex_old_owner_release))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_task_prio_change
+
+
[Called By]
+
+pend_list_add (Thumb, 56 bytes, Stack size 8 bytes, tos_pend.o(i.pend_list_add))
+
[Stack]
- Max Depth = 8
- Call Chain = pend_list_add
+
+
[Called By]
+
+readyqueue_prio_mark (Thumb, 42 bytes, Stack size 12 bytes, tos_sched.o(i.readyqueue_prio_mark))
+
[Stack]
- Max Depth = 12
- Call Chain = readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
+
+knl_idle_entry (Thumb, 6 bytes, Stack size 0 bytes, tos_sys.o(i.knl_idle_entry))
+
[Stack]
- Max Depth = 96 + Unknown Stack Size
+ + In Cycle
+
- Call Chain = knl_idle_entry ⇒ knl_idle_entry (Cycle)
+
+
[Calls]- >> task_free_all
+
- >> knl_idle_entry
+
+
[Called By]
+
[Address Reference Count : 1]- tos_sys.o(i.knl_idle_init)
+
+task_do_destroy (Thumb, 122 bytes, Stack size 16 bytes, tos_task.o(i.task_do_destroy))
+
[Stack]
- Max Depth = 92 + Unknown Stack Size
+
- Call Chain = task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> tick_list_remove
+
- >> readyqueue_remove
+
- >> pend_list_remove
+
- >> mutex_release
+
- >> task_reset
+
- >> knl_is_idle
+
+
[Called By]
+
+task_exit (Thumb, 6 bytes, Stack size 0 bytes, tos_task.o(i.task_exit))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = task_exit ⇒ tos_task_destroy ⇒ task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Address Reference Count : 1]- tos_task.o(i.tos_task_create)
+
+task_free (Thumb, 20 bytes, Stack size 8 bytes, tos_task.o(i.task_free))
+
[Stack]
- Max Depth = 80 + Unknown Stack Size
+
- Call Chain = task_free ⇒ tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]
+
+task_reset (Thumb, 58 bytes, Stack size 0 bytes, tos_task.o(i.task_reset))
+
[Called By]
- >> task_do_destroy
+
- >> tos_task_create
+
+
+tick_task_place (Thumb, 150 bytes, Stack size 32 bytes, tos_tick.o(i.tick_task_place))
+
[Stack]
- Max Depth = 32 + Unknown Stack Size
+
- Call Chain = tick_task_place
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+tos_list_empty (Thumb, 14 bytes, Stack size 0 bytes, tos_tick.o(i.tos_list_empty))
+
[Called By]
+
+timer_place (Thumb, 100 bytes, Stack size 24 bytes, tos_timer.o(i.timer_place))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = timer_place
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+timer_takeoff (Thumb, 68 bytes, Stack size 16 bytes, tos_timer.o(i.timer_takeoff))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = timer_takeoff
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+errno_knl2cmsis (Thumb, 8 bytes, Stack size 0 bytes, cmsis_os.o(i.errno_knl2cmsis))
+
[Called By]
- >> osKernelStart
+
- >> osKernelInitialize
+
- >> osDelay
+
+
+priority_cmsis2knl (Thumb, 16 bytes, Stack size 0 bytes, cmsis_os.o(i.priority_cmsis2knl))
+
[Called By]
+
+_printf_core (Thumb, 658 bytes, Stack size 104 bytes, printf5.o(i._printf_core), UNUSED)
+
[Calls]
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.sct b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.sct
new file mode 100644
index 00000000..eab6f579
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/Nu_Link_Driver.ini b/board/NUCLEO_STM32F446RE/KEIL/Nu_Link_Driver.ini
new file mode 100644
index 00000000..6e70b290
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/Nu_Link_Driver.ini
@@ -0,0 +1,828 @@
+[Version]
+Nu_LinkVersion=V5.6
+[Process]
+ProcessID=0x00000000
+ProcessCreationTime_L=0x00000000
+ProcessCreationTime_H=0x00000000
+NuLinkID=0x00000000
+[ChipSelect]
+;ChipName=
+ChipName=NUC1xx
+[NUC505]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=NUC505_SPIFLASH.FLM
+[NUC4xx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=NUC400_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x014fb180
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[NUC2xx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NUC200_AP_128.FLM
+[NUC126]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=NUC126_AP_256.FLM
+[NUC121]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NUC121_AP_32.FLM
+[NUC1xx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NUC100_AP_128.FLM
+[NUC029]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NUC029_AP_16.FLM
+[NM1820]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1820_AP_17_5.FLM
+[NM1810]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1810_AP_29_5.FLM
+[NM1500]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1500_AP_128.FLM
+[NM1330]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1330_AP_64.FLM
+[NM1320]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1320_AP_32.FLM
+[NM1230]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1230_AP_64.FLM
+[NM1200]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1200_AP_8.FLM
+[NM1120]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1120_AP_29_5.FLM
+[TF5100]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=TF5100_AP_64.FLM
+[NDA102]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NDA102_AP_29_5.FLM
+[Nano103]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=Nano103_AP_64.FLM
+[Nano100]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=Nano100_AP_64.FLM
+[N576]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N576_AP_145.FLM
+[N575]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N575_AP_145.FLM
+[N572]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=N572Fxxx.FLM
+[N571]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=N571E000.FLM
+[N570]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N570_AP_64.FLM
+[N569]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N569_AP_64.FLM
+[N512]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N512_AP_64.FLM
+[Mini57]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=Mini57_AP_29_5.FLM
+[Mini51]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=Mini51_AP_16.FLM
+[M481]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M481_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[M480LD]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M480LD_AP_256.FLM
+[M451]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M451_AP_256.FLM
+[M251]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=M251_AP_192.FLM
+[M2351]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M2351_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[M261]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M261_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[M0564]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=M0564_AP_256.FLM
+[M0519]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=M0519_AP_128.FLM
+[M0518]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=M0518_AP_64.FLM
+[M05x]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=M0516_AP_64.FLM
+[M031]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=M031_AP_128.FLM
+[NPCX]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=NPCX_AP_512.FLM
+[I94000]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=I94000_AP_512.FLM
+[ISD9300]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=ISD9300_AP_145.FLM
+[I9200]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=I9200_AP_128.FLM
+[ISD9xxx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=ISD9100_AP_145.FLM
+[ISD9000]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=ISD9000_AP_64.FLM
+[AU9xxx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=AU9100_AP_145.FLM
+[General]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=
\ No newline at end of file
diff --git a/board/NUCLEO_STM32F446RE/KEIL/RTE/_NUCLEO_STM32F446RE/RTE_Components.h b/board/NUCLEO_STM32F446RE/KEIL/RTE/_NUCLEO_STM32F446RE/RTE_Components.h
new file mode 100644
index 00000000..1911d453
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/RTE/_NUCLEO_STM32F446RE/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'NUCLEO_STM32F446RE'
+ * Target: 'NUCLEO_STM32F446RE'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f4xx.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/board/NUCLEO_STM32F446RE/KEIL/RTE/_tencentos/RTE_Components.h b/board/NUCLEO_STM32F446RE/KEIL/RTE/_tencentos/RTE_Components.h
new file mode 100644
index 00000000..83fc9bec
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/RTE/_tencentos/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'NUCLEO_STM32F446RE'
+ * Target: 'tencentos'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "stm32f4xx.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/board/NUCLEO_STM32F446RE/KEIL/startup_stm32f446xx.s b/board/NUCLEO_STM32F446RE/KEIL/startup_stm32f446xx.s
new file mode 100644
index 00000000..a7cc4578
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/startup_stm32f446xx.s
@@ -0,0 +1,460 @@
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name : startup_stm32f446xx.s
+;* Author : MCD Application Team
+;* Description : STM32F446x devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI4_IRQHandler ; SPI4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SAI1_IRQHandler ; SAI1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QuadSPI
+ DCD CEC_IRQHandler ; CEC
+ DCD SPDIF_RX_IRQHandler ; SPDIF RX
+ DCD FMPI2C1_EV_IRQHandler ; FMPI2C Event
+ DCD FMPI2C1_ER_IRQHandler ; FMPI2C Error
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX0_IRQHandler [WEAK]
+ EXPORT CAN2_RX1_IRQHandler [WEAK]
+ EXPORT CAN2_SCE_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT FMPI2C1_EV_IRQHandler [WEAK]
+ EXPORT FMPI2C1_ER_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM9_IRQHandler
+TIM1_UP_TIM10_IRQHandler
+TIM1_TRG_COM_TIM11_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+FPU_IRQHandler
+SPI4_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+CEC_IRQHandler
+SPDIF_RX_IRQHandler
+FMPI2C1_EV_IRQHandler
+FMPI2C1_ER_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.build_log.htm b/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.build_log.htm
new file mode 100644
index 00000000..34d50351
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.build_log.htm
@@ -0,0 +1,56 @@
+
+
+
+µVision Build Log
+Tool Versions:
+IDE-Version: ¦ÌVision V5.28.0.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: 1 luc, 1, LIC=UJWSB-2J7NB-JJ66S-LG5T2-3DTAU-TCK43
+
+Tool Versions:
+Toolchain: MDK-ARM Plus Version: 5.28.0.0
+Toolchain Path: E:\Keil_v5\ARM\ARMCC\Bin
+C Compiler: Armcc.exe V5.06 update 6 (build 750)
+Assembler: Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter: FromElf.exe V5.06 update 6 (build 750)
+CPU DLL: SARMCM3.DLL V5.28.0.0
+Dialog DLL: DCM.DLL V1.17.3.0
+Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.6.0
+Dialog DLL: TCM.DLL V1.36.2.0
+
+Project:
+G:\TencentOS\test1\board\STM32F446RE\MDK-ARM\NUCLEO_STM32F446RE.uvprojx
+Project File Date: 02/09/2020
+
+Output:
+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'E:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'NUCLEO_STM32F446RE'
+"tencentos\NUCLEO_STM32F446RE.axf" - 0 Error(s), 0 Warning(s).
+
+Software Packages used:
+
+Package Vendor: ARM
+ http://www.keil.com/pack/ARM.CMSIS.5.5.1.pack
+ ARM.CMSIS.5.5.1
+ CMSIS (Cortex Microcontroller Software Interface Standard)
+ * Component: CORE Version: 5.2.0
+
+Package Vendor: Keil
+ http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.14.0.pack
+ Keil.STM32F4xx_DFP.2.14.0
+ STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
+
+Collection of Component include folders:
+ .\RTE\_NUCLEO_STM32F446RE
+ E:\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include
+ E:\Arm\Packs\Keil\STM32F4xx_DFP\2.14.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
+
+Collection of Component Files used:
+
+ * Component: ARM::CMSIS:CORE:5.2.0
+Build Time Elapsed: 00:00:00
+
+
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.htm b/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.htm
new file mode 100644
index 00000000..fbf01c50
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.htm
@@ -0,0 +1,1696 @@
+
+
+Static Call Graph - [tencentos\NUCLEO_STM32F446RE.axf]
+
+Static Call Graph for image tencentos\NUCLEO_STM32F446RE.axf
+
#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Sun Feb 09 21:48:24 2020
+
+
Maximum Stack Usage = 168 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)
+Call chain for Maximum Stack Depth:
+main ⇒ SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
+Functions with no stack information
+
+
+
+
+Mutually Recursive functions
+
ADC_IRQHandler ⇒ ADC_IRQHandler
+ BusFault_Handler ⇒ BusFault_Handler
+ HardFault_Handler ⇒ HardFault_Handler
+ MemManage_Handler ⇒ MemManage_Handler
+ UsageFault_Handler ⇒ UsageFault_Handler
+ knl_idle_entry ⇒ knl_idle_entry
+
+
+
+Function Pointers
+
+ - ADC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- BusFault_Handler from stm32f4xx_it.o(i.BusFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_RX0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN1_TX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_RX0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_RX1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_SCE_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CAN2_TX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- CEC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DCMI_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA1_Stream7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DMA2_Stream7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- DebugMon_Handler from stm32f4xx_it.o(i.DebugMon_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI0_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI15_10_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- EXTI9_5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FLASH_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMPI2C1_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FMPI2C1_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- FPU_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- HardFault_Handler from stm32f4xx_it.o(i.HardFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- I2C1_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C1_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C2_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C2_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C3_ER_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- I2C3_EV_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- MemManage_Handler from stm32f4xx_it.o(i.MemManage_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- NMI_Handler from stm32f4xx_it.o(i.NMI_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_FS_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_FS_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_EP1_IN_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_EP1_OUT_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- OTG_HS_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- PVD_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- PendSV_Handler from port_s.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- QUADSPI_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RCC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RTC_Alarm_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- RTC_WKUP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- Reset_Handler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SAI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SAI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SDIO_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPDIF_RX_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI1_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SPI4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- SVC_Handler from stm32f4xx_it.o(i.SVC_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- SysTick_Handler from stm32f4xx_it.o(i.SysTick_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- SystemInit from system_stm32f4xx.o(i.SystemInit) referenced from startup_stm32f446xx.o(.text)
+
- TAMP_STAMP_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_BRK_TIM9_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_CC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_TRG_COM_TIM11_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM1_UP_TIM10_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM6_DAC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM7_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_BRK_TIM12_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_CC_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_TRG_COM_TIM14_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- TIM8_UP_TIM13_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART4_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART5_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UART_DMAAbortOnError from stm32f4xx_hal_uart.o(i.UART_DMAAbortOnError) referenced from stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler)
+
- USART1_IRQHandler from stm32f4xx_it.o(i.USART1_IRQHandler) referenced from startup_stm32f446xx.o(RESET)
+
- USART2_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- USART3_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- USART6_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- UsageFault_Handler from stm32f4xx_it.o(i.UsageFault_Handler) referenced from startup_stm32f446xx.o(RESET)
+
- WWDG_IRQHandler from startup_stm32f446xx.o(.text) referenced from startup_stm32f446xx.o(RESET)
+
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f446xx.o(.text)
+
- fputc from main.o(i.fputc) referenced from printf5.o(i.__0printf$5)
+
- knl_idle_entry from tos_sys.o(i.knl_idle_entry) referenced from tos_sys.o(i.knl_idle_init)
+
- main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
+
- task1 from main.o(i.task1) referenced from main.o(.constdata)
+
- task2 from main.o(i.task2) referenced from main.o(.constdata)
+
- task_exit from tos_task.o(i.task_exit) referenced from tos_task.o(i.tos_task_create)
+
+
+
+Global Symbols
+
+__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(.text)
+
+_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
+
+
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Calls]
+
+__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+
[Called By]
+
+_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
+
+
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
+
+
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
+
+
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
+
+
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
+
+
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMPI2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FMPI2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+QUADSPI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SAI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SAI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPDIF_RX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SPI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+TIM8_UP_TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f446xx.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+port_int_disable (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text), UNUSED)
+
+
port_int_enable (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text), UNUSED)
+
+
port_cpsr_save (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_cpsr_restore (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
- >> tos_cpu_cpsr_restore
+
+
+port_clz (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_sched_start (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_context_switch (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
+
+port_irq_context_switch (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Called By]
- >> cpu_irq_context_switch
+
+
+PendSV_Handler (Thumb, 0 bytes, Stack size unknown bytes, port_s.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+__aeabi_uldivmod (Thumb, 98 bytes, Stack size 40 bytes, uldiv.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = __aeabi_uldivmod
+
+
[Calls]- >> __aeabi_llsr
+
- >> __aeabi_llsl
+
+
[Called By]- >> UART_SetConfig
+
- >> HAL_RCC_GetSysClockFreq
+
- >> cpu_init
+
- >> tos_millisec2tick
+
- >> _printf_core
+
+
+__aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
[Called By]
- >> _memset$wrapper
+
- >> __aeabi_memclr
+
+
+__aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
__aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
__aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
[Calls]
+
+__aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
+
[Called By]
- >> HAL_UART_MspInit
+
- >> MX_GPIO_Init
+
- >> SystemClock_Config
+
+
+__aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
_memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
+
[Calls]
+
+__aeabi_llsl (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
+
[Called By]
+
+_ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
+
+
__aeabi_llsr (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
+
[Called By]
+
+_ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
+
+
__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
+
[Calls]
- >> __main_after_scatterload
+
+
[Called By]
+
+__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
+
+
BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.BusFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.DebugMon_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+Error_Handler (Thumb, 2 bytes, Stack size 0 bytes, main.o(i.Error_Handler))
+
[Called By]
- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
+
+HAL_DMA_Abort_IT (Thumb, 36 bytes, Stack size 0 bytes, stm32f4xx_hal_dma.o(i.HAL_DMA_Abort_IT))
+
[Called By]
+
+HAL_Delay (Thumb, 32 bytes, Stack size 16 bytes, stm32f4xx_hal.o(i.HAL_Delay))
+
[Stack]
- Max Depth = 16
- Call Chain = HAL_Delay
+
+
[Calls]
+
[Called By]
+
+HAL_GPIO_Init (Thumb, 384 bytes, Stack size 40 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_Init))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_GPIO_Init
+
+
[Called By]- >> HAL_UART_MspInit
+
- >> MX_GPIO_Init
+
+
+HAL_GPIO_TogglePin (Thumb, 14 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_TogglePin))
+
[Called By]
+
+HAL_GPIO_WritePin (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(i.HAL_GPIO_WritePin))
+
[Called By]
+
+HAL_GetTick (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_hal.o(i.HAL_GetTick))
+
[Called By]
- >> UART_WaitOnFlagUntilTimeout
+
- >> HAL_UART_Transmit
+
- >> HAL_RCC_ClockConfig
+
- >> HAL_Delay
+
- >> HAL_RCC_OscConfig
+
+
+HAL_IncTick (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_hal.o(i.HAL_IncTick))
+
[Called By]
+
+HAL_Init (Thumb, 48 bytes, Stack size 8 bytes, stm32f4xx_hal.o(i.HAL_Init))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_Init ⇒ HAL_InitTick ⇒ HAL_NVIC_SetPriority
+
+
[Calls]- >> HAL_MspInit
+
- >> HAL_InitTick
+
- >> HAL_NVIC_SetPriorityGrouping
+
+
[Called By]
+
+HAL_InitTick (Thumb, 54 bytes, Stack size 16 bytes, stm32f4xx_hal.o(i.HAL_InitTick))
+
[Stack]
- Max Depth = 32
- Call Chain = HAL_InitTick ⇒ HAL_NVIC_SetPriority
+
+
[Calls]- >> HAL_NVIC_SetPriority
+
- >> HAL_SYSTICK_Config
+
+
[Called By]- >> HAL_RCC_ClockConfig
+
- >> HAL_Init
+
+
+HAL_MspInit (Thumb, 42 bytes, Stack size 8 bytes, stm32f4xx_hal_msp.o(i.HAL_MspInit))
+
[Stack]
- Max Depth = 8
- Call Chain = HAL_MspInit
+
+
[Called By]
+
+HAL_NVIC_EnableIRQ (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_EnableIRQ))
+
[Called By]
+
+HAL_NVIC_SetPriority (Thumb, 60 bytes, Stack size 16 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_SetPriority))
+
[Stack]
- Max Depth = 16
- Call Chain = HAL_NVIC_SetPriority
+
+
[Calls]
+
[Called By]- >> HAL_UART_MspInit
+
- >> HAL_InitTick
+
+
+HAL_NVIC_SetPriorityGrouping (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.HAL_NVIC_SetPriorityGrouping))
+
[Called By]
+
+HAL_RCC_ClockConfig (Thumb, 288 bytes, Stack size 32 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_ClockConfig))
+
[Stack]
- Max Depth = 80
- Call Chain = HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_GetSysClockFreq
+
- >> HAL_InitTick
+
- >> HAL_GetTick
+
+
[Called By]
+
+HAL_RCC_GetPCLK1Freq (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_GetPCLK1Freq))
+
[Called By]
+
+HAL_RCC_GetPCLK2Freq (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_hal_rcc.o(i.HAL_RCC_GetPCLK2Freq))
+
[Called By]
+
+HAL_RCC_GetSysClockFreq (Thumb, 140 bytes, Stack size 8 bytes, stm32f4xx_hal_rcc_ex.o(i.HAL_RCC_GetSysClockFreq))
+
[Stack]
- Max Depth = 48
- Call Chain = HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]
+
[Called By]
+
+HAL_RCC_OscConfig (Thumb, 814 bytes, Stack size 40 bytes, stm32f4xx_hal_rcc_ex.o(i.HAL_RCC_OscConfig))
+
[Stack]
- Max Depth = 40
- Call Chain = HAL_RCC_OscConfig
+
+
[Calls]
+
[Called By]
+
+HAL_SYSTICK_Config (Thumb, 40 bytes, Stack size 8 bytes, stm32f4xx_hal_cortex.o(i.HAL_SYSTICK_Config))
+
[Stack]
- Max Depth = 8
- Call Chain = HAL_SYSTICK_Config
+
+
[Calls]
+
[Called By]
+
+HAL_UART_ErrorCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_ErrorCallback))
+
[Called By]
- >> UART_DMAAbortOnError
+
- >> HAL_UART_IRQHandler
+
+
+HAL_UART_IRQHandler (Thumb, 270 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler))
+
[Stack]
- Max Depth = 24
- Call Chain = HAL_UART_IRQHandler ⇒ UART_Receive_IT
+
+
[Calls]- >> UART_Transmit_IT
+
- >> UART_Receive_IT
+
- >> UART_EndRxTransfer
+
- >> HAL_UART_TxCpltCallback
+
- >> HAL_UART_ErrorCallback
+
- >> HAL_DMA_Abort_IT
+
+
[Called By]
+
+HAL_UART_Init (Thumb, 98 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_Init))
+
[Stack]
- Max Depth = 104
- Call Chain = HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> UART_SetConfig
+
- >> HAL_UART_MspInit
+
+
[Called By]- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
+
+HAL_UART_MspInit (Thumb, 188 bytes, Stack size 48 bytes, usart.o(i.HAL_UART_MspInit))
+
[Stack]
- Max Depth = 88
- Call Chain = HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_NVIC_SetPriority
+
- >> HAL_NVIC_EnableIRQ
+
- >> HAL_GPIO_Init
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+HAL_UART_RxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_RxCpltCallback))
+
[Called By]
+
+HAL_UART_Transmit (Thumb, 186 bytes, Stack size 32 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_Transmit))
+
[Stack]
- Max Depth = 56
- Call Chain = HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout
+
+
[Calls]- >> UART_WaitOnFlagUntilTimeout
+
- >> HAL_GetTick
+
+
[Called By]
+
+HAL_UART_TxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.HAL_UART_TxCpltCallback))
+
[Called By]
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.HardFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+MX_GPIO_Init (Thumb, 182 bytes, Stack size 48 bytes, gpio.o(i.MX_GPIO_Init))
+
[Stack]
- Max Depth = 88
- Call Chain = MX_GPIO_Init ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_GPIO_WritePin
+
- >> HAL_GPIO_Init
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+MX_USART1_UART_Init (Thumb, 48 bytes, Stack size 8 bytes, usart.o(i.MX_USART1_UART_Init))
+
[Stack]
- Max Depth = 112
- Call Chain = MX_USART1_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_UART_Init
+
- >> Error_Handler
+
+
[Called By]
+
+MX_USART2_UART_Init (Thumb, 48 bytes, Stack size 8 bytes, usart.o(i.MX_USART2_UART_Init))
+
[Stack]
- Max Depth = 112
- Call Chain = MX_USART2_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init
+
+
[Calls]- >> HAL_UART_Init
+
- >> Error_Handler
+
+
[Called By]
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.MemManage_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.NMI_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.SVC_Handler))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(RESET)
+
+SysTick_Handler (Thumb, 32 bytes, Stack size 8 bytes, stm32f4xx_it.o(i.SysTick_Handler))
+
[Stack]
- Max Depth = 76 + Unknown Stack Size
+
- Call Chain = SysTick_Handler ⇒ tos_tick_handler ⇒ tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_tick_handler
+
- >> tos_knl_is_running
+
- >> tos_knl_irq_leave
+
- >> tos_knl_irq_enter
+
- >> HAL_IncTick
+
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+SystemClock_Config (Thumb, 124 bytes, Stack size 88 bytes, main.o(i.SystemClock_Config))
+
[Stack]
- Max Depth = 168
- Call Chain = SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_ClockConfig
+
- >> HAL_RCC_OscConfig
+
- >> __aeabi_memclr4
+
+
[Called By]
+
+SystemInit (Thumb, 22 bytes, Stack size 0 bytes, system_stm32f4xx.o(i.SystemInit))
+
[Address Reference Count : 1]
- startup_stm32f446xx.o(.text)
+
+USART1_IRQHandler (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.USART1_IRQHandler))
+
[Stack]
- Max Depth = 24
- Call Chain = USART1_IRQHandler ⇒ HAL_UART_IRQHandler ⇒ UART_Receive_IT
+
+
[Calls]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.UsageFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f446xx.o(RESET)
+
+__0printf$5 (Thumb, 22 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5), UNUSED)
+
[Calls]
+
+__1printf$5 (Thumb, 0 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5), UNUSED)
+
+
__2printf (Thumb, 0 bytes, Stack size 24 bytes, printf5.o(i.__0printf$5))
+
[Stack]
- Max Depth = 24
- Call Chain = __2printf
+
+
[Called By]
+
+__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
+
+
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
+
+
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
+
+
cpu_context_switch (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_context_switch))
+
[Calls]
+
[Called By]
+
+cpu_init (Thumb, 30 bytes, Stack size 8 bytes, tos_cpu.o(i.cpu_init))
+
[Stack]
- Max Depth = 48
- Call Chain = cpu_init ⇒ __aeabi_uldivmod
+
+
[Calls]- >> cpu_systick_init
+
- >> __aeabi_uldivmod
+
+
[Called By]
+
+cpu_irq_context_switch (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_irq_context_switch))
+
[Calls]
- >> port_irq_context_switch
+
+
[Called By]
+
+cpu_sched_start (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.cpu_sched_start))
+
[Calls]
+
[Called By]
+
+cpu_systick_init (Thumb, 20 bytes, Stack size 8 bytes, tos_cpu.o(i.cpu_systick_init))
+
[Stack]
- Max Depth = 16
- Call Chain = cpu_systick_init ⇒ port_systick_config
+
+
[Calls]- >> port_systick_priority_set
+
- >> port_systick_config
+
+
[Called By]
+
+cpu_task_stk_init (Thumb, 144 bytes, Stack size 12 bytes, tos_cpu.o(i.cpu_task_stk_init))
+
[Stack]
- Max Depth = 12
- Call Chain = cpu_task_stk_init
+
+
[Called By]
+
+fputc (Thumb, 40 bytes, Stack size 16 bytes, main.o(i.fputc))
+
[Stack]
- Max Depth = 72
- Call Chain = fputc ⇒ HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout
+
+
[Calls]
+
[Address Reference Count : 1]- printf5.o(i.__0printf$5)
+
+knl_idle_init (Thumb, 32 bytes, Stack size 24 bytes, tos_sys.o(i.knl_idle_init))
+
[Stack]
- Max Depth = 92 + Unknown Stack Size
+
- Call Chain = knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Called By]
+
+knl_is_idle (Thumb, 14 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_idle))
+
[Called By]
- >> task_do_destroy
+
- >> tos_task_create
+
+
+knl_is_inirq (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_inirq))
+
[Called By]
- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_destroy
+
- >> tos_task_delay
+
- >> tos_task_create
+
+
+knl_is_sched_locked (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_sched_locked))
+
[Called By]
- >> tos_task_destroy
+
- >> tos_task_delay
+
+
+knl_is_self (Thumb, 16 bytes, Stack size 0 bytes, tos_sys.o(i.knl_is_self))
+
[Called By]
- >> tos_task_prio_change
+
- >> tos_task_destroy
+
+
+knl_sched (Thumb, 64 bytes, Stack size 8 bytes, tos_sys.o(i.knl_sched))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = knl_sched
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_context_switch
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> tos_knl_sched_unlock
+
+
+main (Thumb, 58 bytes, Stack size 0 bytes, main.o(i.main))
+
[Stack]
- Max Depth = 168 + Unknown Stack Size
+
- Call Chain = main ⇒ SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod
+
+
[Calls]- >> osThreadCreate
+
- >> osKernelStart
+
- >> osKernelInitialize
+
- >> MX_USART2_UART_Init
+
- >> MX_USART1_UART_Init
+
- >> MX_GPIO_Init
+
- >> HAL_Init
+
- >> HAL_Delay
+
- >> SystemClock_Config
+
+
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
+
+mmheap_init_with_pool (Thumb, 22 bytes, Stack size 16 bytes, tos_mmheap.o(i.mmheap_init_with_pool))
+
[Stack]
- Max Depth = 80 + Unknown Stack Size
+
- Call Chain = mmheap_init_with_pool ⇒ tos_mmheap_pool_add ⇒ blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> mmheap_ctl_init
+
- >> tos_mmheap_pool_add
+
+
[Called By]
+
+mutex_release (Thumb, 20 bytes, Stack size 8 bytes, tos_mutex.o(i.mutex_release))
+
[Stack]
- Max Depth = 76 + Unknown Stack Size
+
- Call Chain = mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> pend_wakeup_all
+
- >> mutex_old_owner_release
+
+
[Called By]
+
+osDelay (Thumb, 32 bytes, Stack size 8 bytes, cmsis_os.o(i.osDelay))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_millisec2tick
+
- >> tos_task_delay
+
+
[Called By]
+
+osKernelInitialize (Thumb, 14 bytes, Stack size 8 bytes, cmsis_os.o(i.osKernelInitialize))
+
[Stack]
- Max Depth = 108 + Unknown Stack Size
+
- Call Chain = osKernelInitialize ⇒ tos_knl_init ⇒ knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_knl_init
+
+
[Called By]
+
+osKernelStart (Thumb, 14 bytes, Stack size 8 bytes, cmsis_os.o(i.osKernelStart))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = osKernelStart ⇒ tos_knl_start
+
+
[Calls]- >> errno_knl2cmsis
+
- >> tos_knl_start
+
+
[Called By]
+
+osThreadCreate (Thumb, 50 bytes, Stack size 32 bytes, cmsis_os.o(i.osThreadCreate))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = osThreadCreate ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> priority_cmsis2knl
+
- >> tos_task_create
+
+
[Called By]
+
+pend_highest_pending_prio_get (Thumb, 18 bytes, Stack size 0 bytes, tos_pend.o(i.pend_highest_pending_prio_get))
+
[Called By]
- >> tos_task_prio_change
+
+
+pend_list_adjust (Thumb, 14 bytes, Stack size 0 bytes, tos_pend.o(i.pend_list_adjust))
+
[Stack]
- Max Depth = 8
- Call Chain = pend_list_adjust ⇒ pend_list_add
+
+
[Calls]
+
[Called By]- >> tos_task_prio_change
+
+
+pend_list_remove (Thumb, 22 bytes, Stack size 0 bytes, tos_pend.o(i.pend_list_remove))
+
[Called By]
- >> pend_task_wakeup
+
- >> task_do_destroy
+
+
+pend_task_wakeup (Thumb, 50 bytes, Stack size 8 bytes, tos_pend.o(i.pend_task_wakeup))
+
[Stack]
- Max Depth = 36 + Unknown Stack Size
+
- Call Chain = pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tick_list_remove
+
- >> readyqueue_add
+
- >> pend_list_remove
+
+
[Called By]- >> pend_wakeup_all
+
- >> tick_update
+
+
+pend_wakeup_all (Thumb, 36 bytes, Stack size 16 bytes, tos_pend.o(i.pend_wakeup_all))
+
[Stack]
- Max Depth = 52 + Unknown Stack Size
+
- Call Chain = pend_wakeup_all ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Called By]
+
+port_systick_config (Thumb, 34 bytes, Stack size 8 bytes, port_c.o(i.port_systick_config))
+
[Stack]
- Max Depth = 8
- Call Chain = port_systick_config
+
+
[Calls]
+
[Called By]
+
+port_systick_priority_set (Thumb, 10 bytes, Stack size 0 bytes, port_c.o(i.port_systick_priority_set))
+
[Calls]
+
[Called By]
+
+readyqueue_add (Thumb, 20 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_add))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
+
[Called By]
+
+readyqueue_add_head (Thumb, 36 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_add_head))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add_head ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add
+
- >> tos_task_prio_change
+
+
+readyqueue_add_tail (Thumb, 36 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_add_tail))
+
[Stack]
- Max Depth = 28
- Call Chain = readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add
+
- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_create
+
+
+readyqueue_highest_ready_task_get (Thumb, 14 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_highest_ready_task_get))
+
[Called By]
- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_start
+
+
+readyqueue_init (Thumb, 48 bytes, Stack size 0 bytes, tos_sched.o(i.readyqueue_init))
+
[Called By]
+
+readyqueue_remove (Thumb, 90 bytes, Stack size 16 bytes, tos_sched.o(i.readyqueue_remove))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = readyqueue_remove
+
+
[Calls]
+
[Called By]- >> tos_task_prio_change
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
+
+task1 (Thumb, 34 bytes, Stack size 0 bytes, main.o(i.task1))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = task1 ⇒ osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> osDelay
+
- >> HAL_GPIO_TogglePin
+
- >> __2printf
+
+
[Address Reference Count : 1]
+task2 (Thumb, 24 bytes, Stack size 0 bytes, main.o(i.task2))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = task2 ⇒ osDelay ⇒ tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> osDelay
+
- >> __2printf
+
+
[Address Reference Count : 1]
+task_free_all (Thumb, 56 bytes, Stack size 16 bytes, tos_task.o(i.task_free_all))
+
[Stack]
- Max Depth = 96 + Unknown Stack Size
+
- Call Chain = task_free_all ⇒ task_free ⇒ tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> task_free
+
+
[Called By]
+
+tick_list_add (Thumb, 18 bytes, Stack size 8 bytes, tos_tick.o(i.tick_list_add))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = tick_list_add ⇒ tick_task_place
+
+
[Calls]
+
[Called By]
+
+tick_list_remove (Thumb, 110 bytes, Stack size 24 bytes, tos_tick.o(i.tick_list_remove))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = tick_list_remove
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> tos_list_empty
+
+
[Called By]- >> pend_task_wakeup
+
- >> task_do_destroy
+
+
+tick_update (Thumb, 114 bytes, Stack size 24 bytes, tos_tick.o(i.tick_update))
+
[Stack]
- Max Depth = 60 + Unknown Stack Size
+
- Call Chain = tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> pend_task_wakeup
+
+
[Called By]
+
+timer_init (Thumb, 4 bytes, Stack size 0 bytes, tos_timer.o(i.timer_init))
+
[Called By]
+
+timer_update (Thumb, 118 bytes, Stack size 24 bytes, tos_timer.o(i.timer_update))
+
[Stack]
- Max Depth = 48 + Unknown Stack Size
+
- Call Chain = timer_update ⇒ timer_place
+
+
[Calls]- >> tos_knl_sched_lock
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tos_knl_sched_unlock
+
+
[Called By]
+
+tos_cpu_clz (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_clz))
+
[Calls]
+
[Called By]- >> __fls
+
- >> readyqueue_remove
+
+
+tos_cpu_cpsr_restore (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_cpsr_restore))
+
[Calls]
+
[Called By]- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_sched_lock
+
- >> tick_list_remove
+
- >> tos_task_prio_change
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tick_update
+
- >> tick_task_place
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> task_free_all
+
- >> tos_knl_sched_unlock
+
+
+tos_cpu_cpsr_save (Thumb, 4 bytes, Stack size 0 bytes, tos_cpu.o(i.tos_cpu_cpsr_save))
+
[Calls]
+
[Called By]- >> tos_knl_irq_leave
+
- >> knl_sched
+
- >> tos_knl_sched_lock
+
- >> tick_list_remove
+
- >> tos_task_prio_change
+
- >> timer_takeoff
+
- >> timer_place
+
- >> tick_update
+
- >> tick_task_place
+
- >> tos_task_yield
+
- >> tos_task_delay
+
- >> task_do_destroy
+
- >> tos_task_create
+
- >> task_free_all
+
- >> tos_knl_sched_unlock
+
+
+tos_knl_init (Thumb, 42 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_init))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = tos_knl_init ⇒ knl_idle_init ⇒ tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> cpu_init
+
- >> readyqueue_init
+
- >> mmheap_init_with_pool
+
- >> timer_init
+
- >> knl_idle_init
+
+
[Called By]
+
+tos_knl_irq_enter (Thumb, 22 bytes, Stack size 0 bytes, tos_sys.o(i.tos_knl_irq_enter))
+
[Called By]
+
+tos_knl_irq_leave (Thumb, 70 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_irq_leave))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_irq_leave
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_irq_context_switch
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]
+
+tos_knl_is_running (Thumb, 12 bytes, Stack size 0 bytes, tos_sys.o(i.tos_knl_is_running))
+
[Called By]
- >> tos_tick_handler
+
- >> SysTick_Handler
+
- >> tos_task_create
+
+
+tos_knl_sched_lock (Thumb, 60 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_sched_lock))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_sched_lock
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+tos_knl_sched_unlock (Thumb, 62 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_sched_unlock))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = tos_knl_sched_unlock ⇒ knl_sched
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
+
[Called By]
+
+tos_knl_start (Thumb, 40 bytes, Stack size 8 bytes, tos_sys.o(i.tos_knl_start))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = tos_knl_start
+
+
[Calls]- >> cpu_sched_start
+
- >> readyqueue_highest_ready_task_get
+
+
[Called By]
+
+tos_millisec2tick (Thumb, 18 bytes, Stack size 8 bytes, tos_time.o(i.tos_millisec2tick))
+
[Stack]
- Max Depth = 48
- Call Chain = tos_millisec2tick ⇒ __aeabi_uldivmod
+
+
[Calls]
+
[Called By]
+
+tos_mmheap_free (Thumb, 56 bytes, Stack size 16 bytes, tos_mmheap.o(i.tos_mmheap_free))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> blk_remove
+
- >> blk_merge_next
+
- >> blk_mark_as_free
+
- >> blk_insert
+
- >> blk_absorb
+
+
[Called By]
+
+tos_mmheap_pool_add (Thumb, 124 bytes, Stack size 16 bytes, tos_mmheap.o(i.tos_mmheap_pool_add))
+
[Stack]
- Max Depth = 64 + Unknown Stack Size
+
- Call Chain = tos_mmheap_pool_add ⇒ blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> mmheap_pool_is_exist
+
- >> blk_link_next
+
- >> blk_insert
+
+
[Called By]- >> mmheap_init_with_pool
+
+
+tos_task_create (Thumb, 188 bytes, Stack size 40 bytes, tos_task.o(i.tos_task_create))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = tos_task_create ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_knl_is_running
+
- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> cpu_task_stk_init
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> task_reset
+
- >> knl_is_idle
+
+
[Called By]- >> osThreadCreate
+
- >> knl_idle_init
+
+
+tos_task_delay (Thumb, 92 bytes, Stack size 16 bytes, tos_task.o(i.tos_task_delay))
+
[Stack]
- Max Depth = 60 + Unknown Stack Size
+
- Call Chain = tos_task_delay ⇒ tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_sched_locked
+
- >> knl_is_inirq
+
- >> tick_list_add
+
- >> readyqueue_remove
+
- >> tos_task_yield
+
+
[Called By]
+
+tos_task_destroy (Thumb, 82 bytes, Stack size 8 bytes, tos_task.o(i.tos_task_destroy))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = tos_task_destroy ⇒ task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> knl_is_sched_locked
+
- >> knl_is_inirq
+
- >> knl_is_self
+
- >> task_do_destroy
+
+
[Called By]
+
+tos_task_prio_change (Thumb, 186 bytes, Stack size 24 bytes, tos_task.o(i.tos_task_prio_change))
+
[Stack]
- Max Depth = 52 + Unknown Stack Size
+
- Call Chain = tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
- >> readyqueue_remove
+
- >> pend_list_adjust
+
- >> pend_highest_pending_prio_get
+
- >> knl_is_self
+
+
[Called By]- >> mutex_old_owner_release
+
+
+tos_task_yield (Thumb, 46 bytes, Stack size 16 bytes, tos_task.o(i.tos_task_yield))
+
[Stack]
- Max Depth = 44 + Unknown Stack Size
+
- Call Chain = tos_task_yield ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> knl_is_inirq
+
- >> readyqueue_add_tail
+
- >> readyqueue_remove
+
+
[Called By]
+
+tos_tick_handler (Thumb, 28 bytes, Stack size 8 bytes, tos_tick.o(i.tos_tick_handler))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = tos_tick_handler ⇒ tick_update ⇒ pend_task_wakeup ⇒ readyqueue_add ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_knl_is_running
+
- >> timer_update
+
- >> tick_update
+
+
[Called By]
+
+
+Local Symbols
+
+UART_DMAAbortOnError (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(i.UART_DMAAbortOnError))
+
[Stack]
- Max Depth = 8
- Call Chain = UART_DMAAbortOnError
+
+
[Calls]- >> HAL_UART_ErrorCallback
+
+
[Address Reference Count : 1]- stm32f4xx_hal_uart.o(i.HAL_UART_IRQHandler)
+
+UART_EndRxTransfer (Thumb, 28 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.UART_EndRxTransfer))
+
[Called By]
+
+UART_Receive_IT (Thumb, 150 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(i.UART_Receive_IT))
+
[Stack]
- Max Depth = 8
- Call Chain = UART_Receive_IT
+
+
[Calls]- >> HAL_UART_RxCpltCallback
+
+
[Called By]
+
+UART_SetConfig (Thumb, 286 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(i.UART_SetConfig))
+
[Stack]
- Max Depth = 64
- Call Chain = UART_SetConfig ⇒ __aeabi_uldivmod
+
+
[Calls]- >> HAL_RCC_GetPCLK2Freq
+
- >> HAL_RCC_GetPCLK1Freq
+
- >> __aeabi_uldivmod
+
+
[Called By]
+
+UART_Transmit_IT (Thumb, 98 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(i.UART_Transmit_IT))
+
[Called By]
+
+UART_WaitOnFlagUntilTimeout (Thumb, 100 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(i.UART_WaitOnFlagUntilTimeout))
+
[Stack]
- Max Depth = 24
- Call Chain = UART_WaitOnFlagUntilTimeout
+
+
[Calls]
+
[Called By]
+
+__NVIC_SetPriority (Thumb, 32 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(i.__NVIC_SetPriority))
+
[Called By]
- >> HAL_NVIC_SetPriority
+
- >> HAL_SYSTICK_Config
+
+
+__NVIC_SetPriority (Thumb, 32 bytes, Stack size 0 bytes, port_c.o(i.__NVIC_SetPriority))
+
[Called By]
- >> port_systick_priority_set
+
- >> port_systick_config
+
+
+__fls (Thumb, 12 bytes, Stack size 8 bytes, tos_mmheap.o(i.__fls))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __fls
+
+
[Calls]
+
[Called By]
+
+blk_absorb (Thumb, 28 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_absorb))
+
[Stack]
- Max Depth = 16
- Call Chain = blk_absorb ⇒ blk_link_next
+
+
[Calls]
+
[Called By]- >> blk_merge_next
+
- >> tos_mmheap_free
+
+
+blk_insert (Thumb, 74 bytes, Stack size 24 bytes, tos_mmheap.o(i.blk_insert))
+
[Stack]
- Max Depth = 48 + Unknown Stack Size
+
- Call Chain = blk_insert ⇒ mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]- >> tos_mmheap_free
+
- >> tos_mmheap_pool_add
+
+
+blk_link_next (Thumb, 12 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_link_next))
+
[Stack]
- Max Depth = 8
- Call Chain = blk_link_next
+
+
[Calls]
+
[Called By]- >> blk_mark_as_free
+
- >> blk_absorb
+
- >> tos_mmheap_pool_add
+
+
+blk_mark_as_free (Thumb, 26 bytes, Stack size 8 bytes, tos_mmheap.o(i.blk_mark_as_free))
+
[Stack]
- Max Depth = 16
- Call Chain = blk_mark_as_free ⇒ blk_link_next
+
+
[Calls]
+
[Called By]
+
+blk_merge_next (Thumb, 36 bytes, Stack size 16 bytes, tos_mmheap.o(i.blk_merge_next))
+
[Stack]
- Max Depth = 56 + Unknown Stack Size
+
- Call Chain = blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> blk_remove
+
- >> blk_next
+
- >> blk_absorb
+
+
[Called By]
+
+blk_next (Thumb, 16 bytes, Stack size 0 bytes, tos_mmheap.o(i.blk_next))
+
[Called By]
- >> blk_merge_next
+
- >> blk_link_next
+
+
+blk_remove (Thumb, 30 bytes, Stack size 16 bytes, tos_mmheap.o(i.blk_remove))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]- >> remove_free_block
+
- >> mapping_insert
+
+
[Called By]- >> blk_merge_next
+
- >> tos_mmheap_free
+
+
+mapping_insert (Thumb, 44 bytes, Stack size 16 bytes, tos_mmheap.o(i.mapping_insert))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]- >> blk_remove
+
- >> blk_insert
+
+
+mmheap_ctl_init (Thumb, 70 bytes, Stack size 16 bytes, tos_mmheap.o(i.mmheap_ctl_init))
+
[Stack]
- Max Depth = 16
- Call Chain = mmheap_ctl_init
+
+
[Called By]- >> mmheap_init_with_pool
+
+
+mmheap_pool_is_exist (Thumb, 36 bytes, Stack size 8 bytes, tos_mmheap.o(i.mmheap_pool_is_exist))
+
[Stack]
- Max Depth = 8
- Call Chain = mmheap_pool_is_exist
+
+
[Called By]
+
+remove_free_block (Thumb, 68 bytes, Stack size 16 bytes, tos_mmheap.o(i.remove_free_block))
+
[Stack]
- Max Depth = 16
- Call Chain = remove_free_block
+
+
[Called By]
+
+mutex_old_owner_release (Thumb, 60 bytes, Stack size 16 bytes, tos_mutex.o(i.mutex_old_owner_release))
+
[Stack]
- Max Depth = 68 + Unknown Stack Size
+
- Call Chain = mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_task_prio_change
+
+
[Called By]
+
+pend_list_add (Thumb, 56 bytes, Stack size 8 bytes, tos_pend.o(i.pend_list_add))
+
[Stack]
- Max Depth = 8
- Call Chain = pend_list_add
+
+
[Called By]
+
+readyqueue_prio_mark (Thumb, 42 bytes, Stack size 12 bytes, tos_sched.o(i.readyqueue_prio_mark))
+
[Stack]
- Max Depth = 12
- Call Chain = readyqueue_prio_mark
+
+
[Called By]- >> readyqueue_add_tail
+
- >> readyqueue_add_head
+
+
+knl_idle_entry (Thumb, 6 bytes, Stack size 0 bytes, tos_sys.o(i.knl_idle_entry))
+
[Stack]
- Max Depth = 96 + Unknown Stack Size
+ + In Cycle
+
- Call Chain = knl_idle_entry ⇒ knl_idle_entry (Cycle)
+
+
[Calls]- >> task_free_all
+
- >> knl_idle_entry
+
+
[Called By]
+
[Address Reference Count : 1]- tos_sys.o(i.knl_idle_init)
+
+task_do_destroy (Thumb, 122 bytes, Stack size 16 bytes, tos_task.o(i.task_do_destroy))
+
[Stack]
- Max Depth = 92 + Unknown Stack Size
+
- Call Chain = task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
- >> knl_sched
+
- >> tick_list_remove
+
- >> readyqueue_remove
+
- >> pend_list_remove
+
- >> mutex_release
+
- >> task_reset
+
- >> knl_is_idle
+
+
[Called By]
+
+task_exit (Thumb, 6 bytes, Stack size 0 bytes, tos_task.o(i.task_exit))
+
[Stack]
- Max Depth = 100 + Unknown Stack Size
+
- Call Chain = task_exit ⇒ tos_task_destroy ⇒ task_do_destroy ⇒ mutex_release ⇒ mutex_old_owner_release ⇒ tos_task_prio_change ⇒ readyqueue_add_tail ⇒ readyqueue_prio_mark
+
+
[Calls]
+
[Address Reference Count : 1]- tos_task.o(i.tos_task_create)
+
+task_free (Thumb, 20 bytes, Stack size 8 bytes, tos_task.o(i.task_free))
+
[Stack]
- Max Depth = 80 + Unknown Stack Size
+
- Call Chain = task_free ⇒ tos_mmheap_free ⇒ blk_merge_next ⇒ blk_remove ⇒ mapping_insert ⇒ __fls
+
+
[Calls]
+
[Called By]
+
+task_reset (Thumb, 58 bytes, Stack size 0 bytes, tos_task.o(i.task_reset))
+
[Called By]
- >> task_do_destroy
+
- >> tos_task_create
+
+
+tick_task_place (Thumb, 150 bytes, Stack size 32 bytes, tos_tick.o(i.tick_task_place))
+
[Stack]
- Max Depth = 32 + Unknown Stack Size
+
- Call Chain = tick_task_place
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+tos_list_empty (Thumb, 14 bytes, Stack size 0 bytes, tos_tick.o(i.tos_list_empty))
+
[Called By]
+
+timer_place (Thumb, 100 bytes, Stack size 24 bytes, tos_timer.o(i.timer_place))
+
[Stack]
- Max Depth = 24 + Unknown Stack Size
+
- Call Chain = timer_place
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+timer_takeoff (Thumb, 68 bytes, Stack size 16 bytes, tos_timer.o(i.timer_takeoff))
+
[Stack]
- Max Depth = 16 + Unknown Stack Size
+
- Call Chain = timer_takeoff
+
+
[Calls]- >> tos_cpu_cpsr_save
+
- >> tos_cpu_cpsr_restore
+
+
[Called By]
+
+errno_knl2cmsis (Thumb, 8 bytes, Stack size 0 bytes, cmsis_os.o(i.errno_knl2cmsis))
+
[Called By]
- >> osKernelStart
+
- >> osKernelInitialize
+
- >> osDelay
+
+
+priority_cmsis2knl (Thumb, 16 bytes, Stack size 0 bytes, cmsis_os.o(i.priority_cmsis2knl))
+
[Called By]
+
+_printf_core (Thumb, 658 bytes, Stack size 104 bytes, printf5.o(i._printf_core), UNUSED)
+
[Calls]
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git a/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.sct b/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.sct
new file mode 100644
index 00000000..eab6f579
--- /dev/null
+++ b/board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+