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fix spi bug when read/write gd32v peripherals

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This commit is contained in:
acevest
2020-04-14 09:49:06 +08:00
parent 81cf6f0c23
commit dde50162fb
18 changed files with 1898 additions and 33 deletions
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2
board/Sipeed_LonganNano/BSP/Src/mcu_init.c
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@@ -3,7 +3,6 @@
void board_init() {
SystemInit();
#if 0
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOC);
@@ -15,6 +14,7 @@ void board_init() {
gpio_bit_set(LEDG_GPIO_PORT, LEDG_PIN);
gpio_bit_set(LEDB_GPIO_PORT, LEDB_PIN);
#if 1
LCD_Init(); // init LCD
LCD_Clear(BLACK);
#endif

10
board/Sipeed_LonganNano/eclipse/nRF24L01/main.c
View File

@@ -85,15 +85,7 @@ void task_led(void *arg)
}
void main(void) {
//board_init();
SystemInit();
nrf24l01_init();
nrf_hal_test_rx();
while(1) { }
board_init();
usart0_init(115200);

23
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24.c
View File

@@ -38,28 +38,35 @@ void nrf24l01_init() {
spi_i2s_deinit(SPIx);
spi_struct_para_init(&spi_init_struct);
/* spi parameter config */
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_MASTER;
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
spi_init_struct.nss = SPI_NSS_SOFT;
spi_init_struct.prescale = SPI_PSC_16;
spi_init_struct.prescale = SPI_PSC_8;
spi_init_struct.endian = SPI_ENDIAN_MSB;
spi_init(SPIx, &spi_init_struct);
//spi_i2s_data_frame_format_config(SPIx, SPI_FRAMESIZE_8BIT);
spi_ti_mode_disable(SPIx); // use motorola mode
spi_crc_off(SPIx);
spi_crc_polynomial_set(SPIx,7);
//spi_crc_on(SPIx);
//spi_ti_mode_disable(SPIx); // use motorola mode
//spi_nssp_mode_enable(SPIx);
spi_nssp_mode_enable(SPIx);
//spi_i2s_data_frame_format_config(SPIx, SPI_FRAMESIZE_8BIT);
//spi_i2s_data_frame_format_config(SPIx, SPI_FRAMESIZE_8BIT);
//spi_i2s_interrupt_disable(SPIx, SPI_I2S_INT_TBE);
//spi_i2s_interrupt_disable(SPIx, SPI_I2S_INT_RBNE);
//spi_i2s_interrupt_disable(SPIx, SPI_I2S_INT_ERR);
spi_enable(SPIx);
spi_enable(SPIx);
nrf_init(&nhi);

7
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01.c
View File

@@ -247,13 +247,13 @@ uint8_t nrf_hal_test_rx() {
nrf_hal_ce(0);
nrf_delay(200);
#if 0
while(1) {
nrf_hal_write_reg_byte(REG_CONFIG, _BV(EN_CRC));
nrf_hal_write_reg_byte(REG_CONFIG, _BV(EN_CRC) | _BV(CRCO));
nrf_hal_read_reg_byte(REG_CONFIG, &data);
nrf_delay(100);
}
#endif
nrf_set_standby_mode();
@@ -261,7 +261,6 @@ uint8_t nrf_hal_test_rx() {
nrf_set_receive_mode();
nrf_disable_rx_irq();
nrf_set_rf_channel(64);
nrf_set_datarate(NRF_2Mbps);
uint8_t rxaddr[] = { 1, 2, 3, 4, 1 };

47
board/Sipeed_LonganNano/eclipse/nRF24L01/nrf24l01_hal.c
View File

@@ -24,30 +24,55 @@ void nrf_hal_ce(uint8_t mode) {
mode == 0 ? gpio_bit_reset(nhi.ce_port, nhi.ce_pin) : gpio_bit_set(nhi.ce_port, nhi.ce_pin);
}
uint8_t _spi_transfer(uint32_t spi, uint8_t data) {
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_TBE));
spi_i2s_data_transmit(spi, data);
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_RBNE));
data = spi_i2s_data_receive(spi);
return data;
}
#if 1
void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) {
for(uint8_t i=0; i<len; i++) {
_spi_transfer(spi, buf[i]);
}
}
void _spi_recv(uint32_t spi, uint8_t *buf, uint8_t len) {
for(uint8_t i=0; i<len; i++) {
buf[i] = _spi_transfer(spi, 0xFF);
}
}
#else
void _spi_send(uint32_t spi, uint8_t *buf, uint8_t len) {
int cnt = 0;
while(cnt < len) {
if(RESET == spi_i2s_flag_get(spi, SPI_FLAG_TBE)) {
continue;
}
//while(cnt < len) {
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_TBE));
spi_i2s_data_transmit(spi, buf[cnt]);
cnt++;
}
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_RBNE));
spi_i2s_data_receive(spi);
//}
}
void _spi_recv(uint32_t spi, uint8_t *buf, uint8_t len) {
int cnt = 0;
while(cnt < len) {
if(RESET == spi_i2s_flag_get(spi, SPI_FLAG_RBNE)) {
continue;
}
//while(cnt < len) {
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_TBE));
spi_i2s_data_transmit(spi, 0xFF);
while(RESET == spi_i2s_flag_get(spi, SPI_FLAG_RBNE));
buf[cnt] = (uint8_t)spi_i2s_data_receive(spi);
cnt++;
}
//}
}
#endif
int nrf_hal_read_reg(uint8_t reg, uint8_t *buf, uint8_t len) {
uint8_t cmd = CMD_R_REGISTER | reg;