replace multiple instructions with macro SAVE_CONTEXT and RESTORE_CONTEXT
This commit is contained in:
@@ -12,6 +12,10 @@
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.global port_context_switch
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.global port_irq_context_switch
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.extern k_curr_task
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.extern k_next_task
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#include "riscv_encoding.h"
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.text
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@@ -55,115 +59,188 @@ port_systick_pending_reset:
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csrc mip, t0
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ret
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#define REGBYTES 4
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#define LOAD lw
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#define STORE sw
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.extern k_curr_task
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.macro SAVE_CONTEXT
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addi sp, sp, -32*REGBYTES
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sw x1, 2*REGBYTES(sp)
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sw x3, 3*REGBYTES(sp)
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sw x4, 4*REGBYTES(sp)
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sw x5, 5*REGBYTES(sp)
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sw x6, 6*REGBYTES(sp)
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sw x7, 7*REGBYTES(sp)
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sw x8, 8*REGBYTES(sp)
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sw x9, 9*REGBYTES(sp)
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sw x10, 10*REGBYTES(sp)
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sw x11, 11*REGBYTES(sp)
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sw x12, 12*REGBYTES(sp)
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sw x13, 13*REGBYTES(sp)
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sw x14, 14*REGBYTES(sp)
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sw x15, 15*REGBYTES(sp)
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sw x16, 16*REGBYTES(sp)
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sw x17, 17*REGBYTES(sp)
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sw x18, 18*REGBYTES(sp)
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sw x19, 19*REGBYTES(sp)
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sw x20, 20*REGBYTES(sp)
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sw x21, 21*REGBYTES(sp)
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sw x22, 22*REGBYTES(sp)
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sw x23, 23*REGBYTES(sp)
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sw x24, 24*REGBYTES(sp)
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sw x25, 25*REGBYTES(sp)
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sw x26, 26*REGBYTES(sp)
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sw x27, 27*REGBYTES(sp)
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sw x28, 28*REGBYTES(sp)
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sw x29, 29*REGBYTES(sp)
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sw x30, 30*REGBYTES(sp)
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sw x31, 31*REGBYTES(sp)
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.endm
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.macro RESTORE_CONTEXT
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lw t0, 0*REGBYTES(sp)
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csrw mepc, t0
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lw t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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lw x1, 2*REGBYTES(sp)
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lw x3, 3*REGBYTES(sp)
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lw x4, 4*REGBYTES(sp)
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lw x5, 5*REGBYTES(sp)
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lw x6, 6*REGBYTES(sp)
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lw x7, 7*REGBYTES(sp)
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lw x8, 8*REGBYTES(sp)
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lw x9, 9*REGBYTES(sp)
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lw x10, 10*REGBYTES(sp)
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lw x11, 11*REGBYTES(sp)
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lw x12, 12*REGBYTES(sp)
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lw x13, 13*REGBYTES(sp)
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lw x14, 14*REGBYTES(sp)
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lw x15, 15*REGBYTES(sp)
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lw x16, 16*REGBYTES(sp)
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lw x17, 17*REGBYTES(sp)
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lw x18, 18*REGBYTES(sp)
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lw x19, 19*REGBYTES(sp)
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lw x20, 20*REGBYTES(sp)
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lw x21, 21*REGBYTES(sp)
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lw x22, 22*REGBYTES(sp)
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lw x23, 23*REGBYTES(sp)
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lw x24, 24*REGBYTES(sp)
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lw x25, 25*REGBYTES(sp)
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lw x26, 26*REGBYTES(sp)
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lw x27, 27*REGBYTES(sp)
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lw x28, 28*REGBYTES(sp)
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lw x29, 29*REGBYTES(sp)
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lw x30, 30*REGBYTES(sp)
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lw x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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.endm
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.align 2
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context_switch_return:
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irq_context_return:
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ret
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.align 2
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.type port_sched_start, %function
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port_sched_start:
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// enable timer interrupt
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li t0, MIE_MTIE
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csrs mie, t0
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// load sp from k_curr_task->sp
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la t0, k_curr_task // t0 = &k_curr_task
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LOAD t0, (t0) // t0 = &(k_curr_task->sp)
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LOAD sp, (t0) // k_curr_task->sp = sp
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lw t0, (t0) // t0 = &(k_curr_task->sp)
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lw sp, (t0) // sp = k_curr_task->sp
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// save sp
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// save sp to stack
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addi t1, sp, 32*REGBYTES
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STORE t1, (t0)
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sw t1, (t0)
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LOAD t0, 0*REGBYTES(sp)
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csrw mepc, t0
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LOAD t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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LOAD x1, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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RESTORE_CONTEXT
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mret
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.align 2
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.type port_context_switch, %function
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port_context_switch:
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SAVE_CONTEXT
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// return from port_context_switch as return from a function
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la t0, context_switch_return
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sw t0, 0*REGBYTES(sp)
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csrr t0, mstatus
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li t1, MSTATUS_MPP
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or t0, t0, t1
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sw t0, 1*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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lw t1, (t0)
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sw sp, (t1)
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// switch task
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// k_curr_task = k_next_task
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la t1, k_next_task // t1 = &k_next_task
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lw t1, (t1) // t1 = k_next_task
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sw t1, (t0)
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// load new task sp
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lw sp, (t1)
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RESTORE_CONTEXT
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mret
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.align 2
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.type port_irq_context_switch, %function
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port_irq_context_switch:
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SAVE_CONTEXT
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la t0, irq_context_return
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sw t0, 0*REGBYTES(sp)
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li t0, MSTATUS_MPP
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sw t0, 1*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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lw t1, (t0)
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sw sp, (t1)
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// switch task
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// k_curr_task = k_next_task
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la t1, k_next_task // t1 = &k_next_task
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lw t1, (t1) // t1 = k_next_task
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sw t1, (t0)
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// load new task sp
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lw sp, (t1)
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RESTORE_CONTEXT
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mret
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.align 2
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.global machine_trap_entry
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machine_trap_entry:
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addi sp, sp, -32*REGBYTES
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STORE x1, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x29, 29*REGBYTES(sp)
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STORE x30, 30*REGBYTES(sp)
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STORE x31, 31*REGBYTES(sp)
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SAVE_CONTEXT
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csrr t0, mepc
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sw t0, 0*REGBYTES(sp)
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#if 1
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//li t0, MSTATUS_MPP | MSTATUS_MPIE // acutally MPIE is not need
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csrr t0, mstatus
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STORE t0, 1*REGBYTES(sp)
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csrr t0, mepc // just save information for handler
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STORE t0, 0*REGBYTES(sp)
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sw t0, 1*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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LOAD t1, (t0)
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STORE sp, (t1)
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lw t1, (t0)
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sw sp, (t1)
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csrr a0, mcause
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mv a1, sp
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@@ -175,257 +252,7 @@ irq:
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srli a0, a0, 1
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call cpu_irq_entry
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restore:
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LOAD t0, 0*REGBYTES(sp)
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csrw mepc, t0
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LOAD t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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#else
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// for debug timer interrupt only
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csrr a0, mcause
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slli a0, a0, 1
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srli a0, a0, 1
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call cpu_irq_entry
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#endif
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LOAD x1, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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RESTORE_CONTEXT
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mret
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.align 2
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.type port_context_switch, %function
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port_context_switch:
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nop
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nop
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addi sp, sp, -32*REGBYTES
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STORE x1, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x29, 29*REGBYTES(sp)
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STORE x30, 30*REGBYTES(sp)
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STORE x31, 31*REGBYTES(sp)
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li t0, MSTATUS_MPP // force use machine mode
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csrr t1, mstatus
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and t1, t1, MSTATUS_MIE
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beqz t1, save_mstatus
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or t0, t0, MSTATUS_MPIE
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save_mstatus:
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STORE t0, 1*REGBYTES(sp)
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la t0, port_context_switch_return // just save information for handler
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STORE t0, 0*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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LOAD t1, (t0)
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STORE sp, (t1)
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// k_curr_task = k_next_task
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la t1, k_next_task // t1 = &k_next_task
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LOAD t1, (t1) // t1 = k_next_task
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STORE t1, (t0)
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// load sp from k_next_task.sp
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LOAD sp, (t1)
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LOAD t0, 0*REGBYTES(sp)
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csrw mepc, t0
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LOAD t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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LOAD x1, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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|
||||
addi sp, sp, 32*REGBYTES
|
||||
|
||||
mret
|
||||
|
||||
.align 2
|
||||
port_context_switch_return:
|
||||
ret
|
||||
|
||||
|
||||
.align 2
|
||||
.type port_irq_context_switch, %function
|
||||
port_irq_context_switch:
|
||||
addi sp, sp, -32*REGBYTES
|
||||
STORE x1, 2*REGBYTES(sp)
|
||||
STORE x3, 3*REGBYTES(sp)
|
||||
STORE x4, 4*REGBYTES(sp)
|
||||
STORE x5, 5*REGBYTES(sp)
|
||||
STORE x6, 6*REGBYTES(sp)
|
||||
STORE x7, 7*REGBYTES(sp)
|
||||
STORE x8, 8*REGBYTES(sp)
|
||||
STORE x9, 9*REGBYTES(sp)
|
||||
STORE x10, 10*REGBYTES(sp)
|
||||
STORE x11, 11*REGBYTES(sp)
|
||||
STORE x12, 12*REGBYTES(sp)
|
||||
STORE x13, 13*REGBYTES(sp)
|
||||
STORE x14, 14*REGBYTES(sp)
|
||||
STORE x15, 15*REGBYTES(sp)
|
||||
STORE x16, 16*REGBYTES(sp)
|
||||
STORE x17, 17*REGBYTES(sp)
|
||||
STORE x18, 18*REGBYTES(sp)
|
||||
STORE x19, 19*REGBYTES(sp)
|
||||
STORE x20, 20*REGBYTES(sp)
|
||||
STORE x21, 21*REGBYTES(sp)
|
||||
STORE x22, 22*REGBYTES(sp)
|
||||
STORE x23, 23*REGBYTES(sp)
|
||||
STORE x24, 24*REGBYTES(sp)
|
||||
STORE x25, 25*REGBYTES(sp)
|
||||
STORE x26, 26*REGBYTES(sp)
|
||||
STORE x27, 27*REGBYTES(sp)
|
||||
STORE x28, 28*REGBYTES(sp)
|
||||
STORE x29, 29*REGBYTES(sp)
|
||||
STORE x30, 30*REGBYTES(sp)
|
||||
STORE x31, 31*REGBYTES(sp)
|
||||
|
||||
li t0, MSTATUS_MPP
|
||||
STORE t0, 1*REGBYTES(sp)
|
||||
la t0, irq_context_return
|
||||
STORE t0, 0*REGBYTES(sp)
|
||||
|
||||
// save sp to k_curr_task.sp
|
||||
la t0, k_curr_task // t0 = &k_curr_task
|
||||
LOAD t1, (t0)
|
||||
STORE sp, (t1)
|
||||
|
||||
// k_curr_task = k_next_task
|
||||
la t1, k_next_task // t1 = &k_next_task
|
||||
LOAD t1, (t1) // t1 = k_next_task
|
||||
STORE t1, (t0)
|
||||
|
||||
// load sp from k_next_task.sp
|
||||
LOAD sp, (t1)
|
||||
|
||||
LOAD t0, 1*REGBYTES(sp)
|
||||
csrw mstatus, t0
|
||||
|
||||
LOAD t0, 0*REGBYTES(sp)
|
||||
csrw mepc, t0
|
||||
|
||||
LOAD x1, 2*REGBYTES(sp)
|
||||
LOAD x3, 3*REGBYTES(sp)
|
||||
LOAD x4, 4*REGBYTES(sp)
|
||||
LOAD x5, 5*REGBYTES(sp)
|
||||
LOAD x6, 6*REGBYTES(sp)
|
||||
LOAD x7, 7*REGBYTES(sp)
|
||||
LOAD x8, 8*REGBYTES(sp)
|
||||
LOAD x9, 9*REGBYTES(sp)
|
||||
LOAD x10, 10*REGBYTES(sp)
|
||||
LOAD x11, 11*REGBYTES(sp)
|
||||
LOAD x12, 12*REGBYTES(sp)
|
||||
LOAD x13, 13*REGBYTES(sp)
|
||||
LOAD x14, 14*REGBYTES(sp)
|
||||
LOAD x15, 15*REGBYTES(sp)
|
||||
LOAD x16, 16*REGBYTES(sp)
|
||||
LOAD x17, 17*REGBYTES(sp)
|
||||
LOAD x18, 18*REGBYTES(sp)
|
||||
LOAD x19, 19*REGBYTES(sp)
|
||||
LOAD x20, 20*REGBYTES(sp)
|
||||
LOAD x21, 21*REGBYTES(sp)
|
||||
LOAD x22, 22*REGBYTES(sp)
|
||||
LOAD x23, 23*REGBYTES(sp)
|
||||
LOAD x24, 24*REGBYTES(sp)
|
||||
LOAD x25, 25*REGBYTES(sp)
|
||||
LOAD x26, 26*REGBYTES(sp)
|
||||
LOAD x27, 27*REGBYTES(sp)
|
||||
LOAD x28, 28*REGBYTES(sp)
|
||||
LOAD x29, 29*REGBYTES(sp)
|
||||
LOAD x30, 30*REGBYTES(sp)
|
||||
LOAD x31, 31*REGBYTES(sp)
|
||||
|
||||
|
||||
addi sp, sp, 32*REGBYTES
|
||||
|
||||
mret
|
||||
|
||||
|
||||
irq_context_return:
|
||||
ret
|
||||
|
||||
|
||||
|
@@ -125,16 +125,18 @@
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.293419375" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/TencentOS_tiny/arch/risc-v/rv32i}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/TencentOS_tiny/arch/risc-v/common}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/TencentOS_tiny/kernel/core/include}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/TencentOS_tiny/kernel/pm/include}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/TencentOS_tiny/arch/risc-v/common}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/TencentOS_tiny/arch/risc-v/rv32i}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/Inc}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/hello_world/TOS-CONFIG}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.905374687" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input"/>
|
||||
@@ -211,9 +213,7 @@
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry excluding="TencentOS_tiny|Src" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
|
||||
<entry excluding="TencentOS_tiny|Srcs" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="TencentOS_tiny"/>
|
||||
|
||||
@@ -369,9 +369,7 @@
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry excluding="Src" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
|
||||
<entry excluding="Srcs" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
|
||||
</sourceEntries>
|
||||
|
||||
|
@@ -24,6 +24,21 @@
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>Inc</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/Inc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>Src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/Src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>TOS-CONFIG</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/TOS-CONFIG</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>TencentOS_tiny</name>
|
||||
<type>2</type>
|
||||
|
@@ -11,7 +11,7 @@
|
||||
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1380923165007189689" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1296816921559833178" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
|
||||
|
Reference in New Issue
Block a user