fix board compile for kernel change
This commit is contained in:
supowang
@@ -1,97 +0,0 @@
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// File: STM32L43x_44x_45x_46x.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx Reference manual (RM0394)
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// refer to STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o0.2> DBG_STANDBY
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// <i> Debug Standby mode
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// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
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// <i> 1: (FCLK=On, HCLK=On) The digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.1> DBG_STOP
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// <i> Debug Stop mode
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// <i> 0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK).
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// <i> 1: (FCLK=On, HCLK=On) When entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode.
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// <o0.0> DBG_SLEEP
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// <i> Debug Sleep mode
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// <i> 0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled.
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// <i> 1: (FCLK=On, HCLK=On) When entering Sleep mode, HCLK is fed by the same clock that is provided to FCLK (system clock as previously configured by the software).
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
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// <o0.31> DBG_LPTIM1_STOP
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// <i> LPTIM1 counter stopped when core is halted
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// <i> 0: The counter clock of LPTIM1 is fed even if the core is halted
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// <i> 1: The counter clock of LPTIM1 is stopped when the core is halted
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// <o0.25> DBG_CAN_STOP
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// <i> bxCAN1 stopped when core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The bxCAN1 receive registers are frozen
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// <o0.23> DBG_I2C3_STOP
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// <i> I2C3 SMBUS timeout counter stopped when core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The I2C3 SMBus timeout is frozen
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// <o0.22> DBG_I2C2_STOP
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// <i> I2C2 SMBUS timeout counter stopped when core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The I2C2 SMBus timeout is frozen
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// <o0.21> DBG_I2C1_STOP
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// <i> I2C1 SMBUS timeout counter stopped when core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The I2C1 SMBus timeout is frozen
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// <o0.12> DBG_IWDG_STOP
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// <i> Independent watchdog counter stopped when core is halted
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// <i> 0: The independent watchdog counter clock continues even if the core is halted
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// <i> 1: The independent watchdog counter clock is stopped when the core is halted
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// <o0.11> DBG_WWDG_STOP
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// <i> Window watchdog counter stopped when core is halted
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// <i> 0: The window watchdog counter clock continues even if the core is halted
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// <i> 1: The window watchdog counter clock is stopped when the core is halted
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// <o0.10> DBG_RTC_STOP
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// <i> RTC counter stopped when core is halted
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// <i> 0: The clock of the RTC counter is fed even if the core is halted
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// <i> 1: The clock of the RTC counter is stopped when the core is halted
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// <o0.5> DBG_TIM7_STOP
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// <i> TIM7 counter stopped when core is halted
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// <i> 0: The counter clock of TIM7 is fed even if the core is halted
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// <i> 1: The counter clock of TIM7 is stopped when the core is halted
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// <o0.4> DBG_TIM6_STOP
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// <i> TIM6 counter stopped when core is halted
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// <i> 0: The counter clock of TIM6 is fed even if the core is halted
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// <i> 1: The counter clock of TIM6 is stopped when the core is halted
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// <o0.0> DBG_TIM2_STOP
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// <i> TIM2 counter stopped when core is halted
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// <i> 0: The counter clock of TIM2 is fed even if the core is halted
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// <i> 1: The counter clock of TIM2 is stopped when the core is halted
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// </h>
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DbgMCU_APB1_Fz1 = 0x00000000;
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// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
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// <o0.5> DBG_LPTIM2_STOP
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// <i> LPTIM2 counter stopped when core is halted
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// <i> 0: The counter clock of LPTIM2 is fed even if the core is halted
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// <i> 1: The counter clock of LPTIM2 is stopped when the core is halted
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// </h>
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DbgMCU_APB1_Fz2 = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
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// <o0.17> DBG_TIM16_STOP
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// <i> TIM16 counter stopped when core is halted
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// <i> 0: The clock of the TIM16 counter is fed even if the core is halted
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// <i> 1: The clock of the TIM16 counter is stopped when the core is halted
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// <o0.16> DBG_TIM15_STOP
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// <i> TIM15 counter stopped when core is halted
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// <i> 0: The clock of the TIM15 counter is fed even if the core is halted
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// <i> 1: The clock of the TIM15 counter is stopped when the core is halted
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// <o0.11> DBG_TIM1_STOP
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// <i> TIM1 counter stopped when core is halted
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// <i> 0: The clock of the TIM1 counter is fed even if the core is halted
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// <i> 1: The clock of the TIM1 counter is stopped when the core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// </h>
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// <<< end of configuration section >>>
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@@ -1,20 +0,0 @@
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/*
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* Auto generated Run-Time-Environment Component Configuration File
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* *** Do not modify ! ***
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*
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* Project: 'TencentOS_tiny'
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* Target: 'TencentOS_tiny'
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*/
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#ifndef RTE_COMPONENTS_H
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#define RTE_COMPONENTS_H
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/*
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* Define the Device Header File:
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*/
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#define CMSIS_device_header "stm32l4xx.h"
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#endif /* RTE_COMPONENTS_H */
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@@ -16,7 +16,7 @@
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<TargetCommonOption>
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<Device>STM32L431RCTx</Device>
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<Vendor>STMicroelectronics</Vendor>
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<PackID>Keil.STM32L4xx_DFP.2.0.0</PackID>
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<PackID>Keil.STM32L4xx_DFP.2.2.0</PackID>
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<PackURL>http://www.keil.com/pack</PackURL>
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<Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")</Cpu>
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<FlashUtilSpec></FlashUtilSpec>
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@@ -1,143 +0,0 @@
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<html>
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<body>
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<pre>
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<h1><EFBFBD>Vision Build Log</h1>
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<h2>Tool Versions:</h2>
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IDE-Version: <20><>Vision V5.26.2.0
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Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
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License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
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Tool Versions:
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Toolchain: MDK-ARM Professional Version: 5.26.2.0
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Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
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C Compiler: Armcc.exe V5.06 update 6 (build 750)
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Assembler: Armasm.exe V5.06 update 6 (build 750)
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Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
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Library Manager: ArmAr.exe V5.06 update 6 (build 750)
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Hex Converter: FromElf.exe V5.06 update 6 (build 750)
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CPU DLL: SARMCM3.DLL V5.26.2.0
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Dialog DLL: DCM.DLL V1.17.2.0
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Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
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Dialog DLL: TCM.DLL V1.36.1.0
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<h2>Project:</h2>
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D:\github\master\TencentOS-tiny\board\TencentOS_tiny_EVB_MX_Plus\KEIL\test\TencentOS_tiny.uvprojx
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Project File Date: 10/28/2019
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<h2>Output:</h2>
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*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
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Rebuild target 'TencentOS_tiny'
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assembling startup_stm32l431xx.s...
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compiling gpio.c...
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compiling mcu_init.c...
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compiling stm32l4xx_hal_msp.c...
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compiling adc.c...
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compiling usart.c...
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compiling stm32l4xx_it.c...
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compiling main.c...
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compiling spi.c...
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compiling i2c.c...
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compiling dac.c...
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compiling stm32l4xx_hal_tim_ex.c...
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compiling stm32l4xx_hal_uart_ex.c...
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compiling stm32l4xx_hal_tim.c...
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compiling stm32l4xx_hal_uart.c...
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compiling stm32l4xx_hal.c...
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compiling stm32l4xx_hal_i2c_ex.c...
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compiling stm32l4xx_hal_i2c.c...
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compiling stm32l4xx_hal_rcc_ex.c...
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compiling stm32l4xx_hal_rcc.c...
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compiling stm32l4xx_hal_flash.c...
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compiling stm32l4xx_hal_flash_ex.c...
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compiling stm32l4xx_hal_flash_ramfunc.c...
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compiling stm32l4xx_hal_gpio.c...
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compiling stm32l4xx_hal_pwr_ex.c...
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compiling stm32l4xx_hal_dma.c...
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compiling stm32l4xx_hal_dma_ex.c...
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compiling stm32l4xx_hal_pwr.c...
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compiling stm32l4xx_hal_cortex.c...
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compiling stm32l4xx_hal_adc.c...
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compiling stm32l4xx_hal_adc_ex.c...
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compiling stm32l4xx_hal_dac_ex.c...
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compiling stm32l4xx_hal_spi_ex.c...
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compiling system_stm32l4xx.c...
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compiling stm32l4xx_hal_dac.c...
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compiling DHT11_BUS.c...
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compiling stm32l4xx_hal_spi.c...
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compiling oled.c...
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compiling tos_mmblk.c...
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compiling tos_mutex.c...
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compiling tos_mmheap.c...
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compiling tos_sched.c...
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compiling tos_sem.c...
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compiling tos_task.c...
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compiling tos_sys.c...
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compiling tos_tick.c...
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compiling tos_timer.c...
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compiling tos_time.c...
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compiling tos_event.c...
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compiling tos_pend.c...
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compiling tos_global.c...
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compiling tos_robin.c...
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compiling tos_binary_heap.c...
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compiling tos_char_fifo.c...
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compiling tos_countdownlatch.c...
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compiling tos_completion.c...
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compiling tos_message_queue.c...
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compiling tos_mail_queue.c...
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compiling tos_priority_mail_queue.c...
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compiling tos_priority_message_queue.c...
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assembling port_s.S...
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compiling tos_priority_queue.c...
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compiling tos_ring_queue.c...
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compiling tos_cpu.c...
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compiling port_c.c...
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compiling cmsis_os.c...
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compiling suit_event.c...
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compiling suit_mmheap.c...
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compiling suit_mmblk.c...
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compiling suit_mutex.c...
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compiling suit_robin.c...
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compiling suit_task.c...
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compiling suit_sem.c...
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compiling suit_timer.c...
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compiling test_main.c...
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compiling test_utils.c...
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compiling suit_binary_heap.c...
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compiling suit_char_fifo.c...
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compiling suit_mail_queue.c...
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compiling suit_message_queue.c...
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compiling suit_priority_mail_queue.c...
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compiling suit_priority_message_queue.c...
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compiling suit_priority_queue.c...
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compiling suit_ring_queue.c...
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linking...
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Program Size: Code=109768 RO-data=5824 RW-data=336 ZI-data=47544
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FromELF: creating hex file...
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".\obj\TencentOS_tiny.axf" - 0 Error(s), 0 Warning(s).
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<h2>Software Packages used:</h2>
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Package Vendor: ARM
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http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
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ARM.CMSIS.5.6.0
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CMSIS (Cortex Microcontroller Software Interface Standard)
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* Component: CORE Version: 5.3.0
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Package Vendor: Keil
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http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack
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Keil.STM32L4xx_DFP.2.0.0
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STMicroelectronics STM32L4 Series Device Support, Drivers and Examples
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<h2>Collection of Component include folders:</h2>
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.\RTE\_TencentOS_tiny
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C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
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C:\Keil_v5\ARM\PACK\Keil\STM32L4xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32L4xx\Include
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<h2>Collection of Component Files used:</h2>
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* Component: ARM::CMSIS:CORE:5.3.0
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Build Time Elapsed: 00:00:16
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</pre>
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</body>
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</html>
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File diff suppressed because it is too large
Load Diff
@@ -1,16 +0,0 @@
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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LR_IROM1 0x08000000 0x00040000 { ; load region size_region
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ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+XO)
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}
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RW_IRAM1 0x20000000 0x00010000 { ; RW data
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.ANY (+RW +ZI)
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}
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}
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