first commit for opensource

first commit for opensource

arch/arm/arm-v7m/common/include/tos_cpu.h

@@ -0,0 +1,124 @@
+#ifndef _TOS_CPU_H_
+#define  _TOS_CPU_H_
+
+typedef struct cpu_context_st {
+    cpu_data_t      _R4;
+    cpu_data_t      _R5;
+    cpu_data_t      _R6;
+    cpu_data_t      _R7;
+    cpu_data_t      _R8;
+    cpu_data_t      _R9;
+    cpu_data_t      _R10;
+    cpu_data_t      _R11;
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+    cpu_data_t      EXC_RETURN;
+#endif
+    cpu_data_t      _R0;
+    cpu_data_t      _R1;
+    cpu_data_t      _R2;
+    cpu_data_t      _R3;
+    cpu_data_t      _R12;
+    cpu_data_t      _R14;
+    cpu_data_t      _PC;
+    cpu_data_t      _xPSR;
+} cpu_context_t;
+
+__API__ uint32_t        tos_cpu_clz(uint32_t val);
+
+__API__ void            tos_cpu_int_disable(void);
+
+__API__ void            tos_cpu_int_enable(void);
+
+__API__ cpu_cpsr_t      tos_cpu_cpsr_save(void);
+
+__API__ void            tos_cpu_cpsr_restore(cpu_cpsr_t cpsr);
+
+#if (TOS_CFG_CPU_HRTIMER_EN > 0u)
+
+__API__ void            tos_cpu_hrtimer_init(void);
+
+__API__ cpu_hrtimer_t   tos_cpu_hrtimer_read(void);
+
+#endif
+
+__KERNEL__ void         cpu_init(void);
+
+__KERNEL__ void         cpu_reset(void);
+
+__KERNEL__ void         cpu_systick_init(k_cycle_t cycle_per_tick);
+
+__KERNEL__ void         cpu_sched_start(void);
+
+__KERNEL__ void         cpu_context_switch(void);
+
+__KERNEL__ void         cpu_irq_context_switch(void);
+
+#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u
+
+__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth);
+
+#endif
+
+__KERNEL__ k_stack_t   *cpu_task_stk_init(void *entry,
+                                                          void *arg,
+                                                          void *exit,
+                                                          k_stack_t *stk_base,
+                                                          size_t stk_size);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__KERNEL__ void         cpu_systick_resume(void);
+
+__KERNEL__ void         cpu_systick_suspend(void);
+
+__KERNEL__ void         cpu_systick_reload_reset(void);
+
+__KERNEL__ void         cpu_systick_pending_reset(void);
+
+__KERNEL__ k_time_t     cpu_systick_max_delay_millisecond(void);
+
+__KERNEL__ void         cpu_systick_expires_set(k_time_t millisecond);
+
+__KERNEL__ void         cpu_systick_reset(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__KERNEL__ void cpu_sleep_mode_enter(void);
+
+__KERNEL__ void cpu_stop_mode_enter(void);
+
+__KERNEL__ void cpu_standby_mode_enter(void);
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+
+__KERNEL__ void         cpu_flush_fpu(void);
+
+#endif /* TOS_CFG_CPU_ARM_FPU_EN */
+
+__KERNEL__ void         cpu_fault_diagnosis(void);
+
+#endif
+
+/* Allocates CPU status register word. */
+#define TOS_CPU_CPSR_ALLOC()    cpu_cpsr_t cpu_cpsr = (cpu_cpsr_t)0u
+
+/* Save CPU status word & disable interrupts.*/
+#define TOS_CPU_INT_DISABLE() \
+    do { \
+        cpu_cpsr = tos_cpu_cpsr_save(); \
+    } while (0)
+
+/* Restore CPU status word.                     */
+#define  TOS_CPU_INT_ENABLE() \
+    do { \
+        tos_cpu_cpsr_restore(cpu_cpsr); \
+    } while (0)
+
+#endif /* _TOS_CPU_H_ */
+

arch/arm/arm-v7m/common/include/tos_cpu_def.h

@@ -0,0 +1,17 @@
+#ifndef _TOS_CPU_DEF_H_
+#define  _TOS_CPU_DEF_H_
+
+enum CPU_WORD_SIZE {
+    CPU_WORD_SIZE_08,
+    CPU_WORD_SIZE_16,
+    CPU_WORD_SIZE_32,
+    CPU_WORD_SIZE_64,
+};
+
+enum CPU_STK_GROWTH {
+    CPU_STK_GROWTH_ASCENDING,
+    CPU_STK_GROWTH_DESCENDING,
+};
+
+#endif /* _TOS_CPU_DEF_H_ */
+

arch/arm/arm-v7m/common/include/tos_cpu_types.h

@@ -0,0 +1,40 @@
+#ifndef _TOS_CPU_TYPES_H_
+#define  _TOS_CPU_TYPES_H_
+
+/* CPU address type based on address bus size.          */
+#if     (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_32)
+typedef uint32_t    cpu_addr_t;
+#elif   (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_16)
+typedef uint16_t    cpu_addr_t;
+#else
+typedef uint8_t     cpu_addr_t;
+#endif
+
+/* CPU data type based on data bus size.          */
+#if     (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_32)
+typedef uint32_t    cpu_data_t;
+#elif   (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_16)
+typedef uint16_t    cpu_data_t;
+#else
+typedef uint8_t     cpu_data_t;
+#endif
+
+#if     (TOS_CFG_CPU_HRTIMER_EN > 0)
+#if     (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_08)
+typedef uint8_t     cpu_hrtimer_t;
+#elif   (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_16)
+typedef uint16_t    cpu_hrtimer_t;
+#elif   (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_64)
+typedef uint64_t    cpu_hrtimer_t;
+#else
+typedef uint32_t    cpu_hrtimer_t;
+#endif
+#else
+typedef uint32_t    cpu_hrtimer_t;
+#endif
+
+//typedef cpu_addr_t  size_t;
+typedef cpu_addr_t  cpu_cpsr_t;
+
+#endif
+

arch/arm/arm-v7m/common/include/tos_fault.h

@@ -0,0 +1,219 @@
+#ifndef _TOS_FAULT_H_
+#define  _TOS_FAULT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+
+typedef int (*k_fault_log_writer_t)(const char *format, ...);
+
+#define K_FAULT_STACK_DUMP_DEPTH                10u
+
+#define K_FAULT_CALL_STACK_BACKTRACE_DEPTH          5u
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+typedef struct fault_fpu_frame_st {
+    cpu_data_t s0;
+    cpu_data_t s1;
+    cpu_data_t s2;
+    cpu_data_t s3;
+    cpu_data_t s4;
+    cpu_data_t s5;
+    cpu_data_t s6;
+    cpu_data_t s7;
+    cpu_data_t s8;
+    cpu_data_t s9;
+    cpu_data_t s10;
+    cpu_data_t s11;
+    cpu_data_t s12;
+    cpu_data_t s13;
+    cpu_data_t s14;
+    cpu_data_t s15;
+    cpu_data_t fpscr;
+} fault_fpu_frame_t;
+#endif
+
+typedef struct fault_cpu_frame_st {
+    cpu_data_t r0;
+    cpu_data_t r1;
+    cpu_data_t r2;
+    cpu_data_t r3;
+    cpu_data_t r12;
+    cpu_data_t lr;
+    cpu_data_t pc;
+    cpu_data_t spsr;
+} fault_cpu_frame_t;
+
+typedef struct fault_exc_frame_st {
+    fault_cpu_frame_t cpu_frame;
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+    fault_fpu_frame_t fpu_frame;
+#endif
+} fault_exc_frame_t;
+
+/**
+ * information we need to do fault backtrace
+ */
+typedef struct fault_information_st {
+    int is_thumb : 1;           /**< whether it is thumb we use when we fall into fault? */
+    int is_on_task : 1;         /**< whether we are on a task when fall into fault? */
+    int is_stk_ovrf : 1;        /**< whether we get a stack overflow */
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+    int is_ext_stk_frm : 1;     /**< whether it is a extended stack frame?(whether the cpu has pushed fpu registers onto the stack) */
+#endif
+
+    cpu_addr_t pc;              /**< just where fault happens */
+
+    cpu_addr_t sp_before_fault; /**< original sp just before the cpu push the fault exception frame */
+
+    /**
+     * we need main_stack_start & main_stack_limit to do call stack backtrace
+     * when we fall into fault during a task, we should do the call stack backtrace on the task's stack
+     * but if not, which means we are in kernel, we should do the call stack backtrace on the main stack
+     * in arm v7-m, this should be the MSP's start and limit
+     * in arm v7-a, call stack backtrace is another story(much more elegant because we have FP).
+     */
+    cpu_addr_t stack_start;     /**< current sp start address we use. if on task, it'll be the task's stack, otherwise it'll be the msp */
+    cpu_addr_t stack_limit;     /**< current sp limit address */
+    cpu_addr_t code_start;      /**< current code start address */
+    cpu_addr_t code_limit;      /**< current code limit address */
+} fault_info_t;
+
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+
+#define DEFAULT_CODE_SECTION_NAME       ER_IROM1
+#define DEFAULT_CSTACK_SECTION_NAME     STACK
+
+#define SECTION_START(_name_)                _name_##$$Base
+#define SECTION_END(_name_)                  _name_##$$Limit
+#define IMAGE_SECTION_START(_name_)          Image$$##_name_##$$Base
+#define IMAGE_SECTION_END(_name_)            Image$$##_name_##$$Limit
+#define CSTACK_BLOCK_START(_name_)           SECTION_START(_name_)
+#define CSTACK_BLOCK_END(_name_)             SECTION_END(_name_)
+#define CODE_SECTION_START(_name_)           IMAGE_SECTION_START(_name_)
+#define CODE_SECTION_END(_name_)             IMAGE_SECTION_END(_name_)
+
+extern const int CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME);
+extern const int CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME);
+extern const int CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME);
+extern const int CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME);
+
+__STATIC_INLINE__ cpu_addr_t fault_code_start(void)
+{
+    return (cpu_addr_t)&CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME);
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_code_limit(void)
+{
+    return (cpu_addr_t)&CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME);
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_msp_start(void)
+{
+    return (cpu_addr_t)&CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME);
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void)
+{
+    return (cpu_addr_t)&CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME);
+}
+
+#elif defined(__ICCARM__)
+
+#define DEFAULT_CODE_SECTION_NAME       ".text"
+#define DEFAULT_CSTACK_SECTION_NAME     "CSTACK"
+
+#pragma section=DEFAULT_CSTACK_SECTION_NAME
+#pragma section=DEFAULT_CODE_SECTION_NAME
+
+__STATIC_INLINE__ cpu_addr_t fault_code_start(void)
+{
+    return (cpu_addr_t)__section_begin(DEFAULT_CODE_SECTION_NAME);
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_code_limit(void)
+{
+    return (cpu_addr_t)__section_end(DEFAULT_CODE_SECTION_NAME);
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_msp_start(void)
+{
+    return (cpu_addr_t)__section_begin(DEFAULT_CSTACK_SECTION_NAME);
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void)
+{
+    return (cpu_addr_t)__section_end(DEFAULT_CSTACK_SECTION_NAME);
+}
+
+#elif defined(__GNUC__)
+
+/**
+ * if we are using keil(armcc) or mdk(iccarm), we probably use the defult link script supplied by the IDE.
+ * the way to locate the text/stack section start and limit is to find them in default link script.
+ * but if we build our project by makefile(or something like scons, cmake, etc), we probably need to write
+ * our own link scrpit, if so, we should do like this(just a demo):
+ *
+    _stext = .;
+    .text : {
+        *(.text.startup)
+        *(.text)
+        *(.text.*)
+    }
+    _etext = .;
+
+     __bss_start = .;
+    .bss : {
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        _sstack = .;
+        *(.cstack)
+        _estack = .;
+    }
+    __bss_end = .;
+ * by this, we can locate text/stack section start and limit by _stext/_etext and _sstack/_estack
+ */
+#define DEFAULT_CODE_SECTION_START      _stext
+#define DEFAULT_CODE_SECTION_END        _etext
+#define DEFAULT_CSTACK_SECTION_START    _sstack
+#define DEFAULT_CSTACK_SECTION_END      _estack
+
+extern const int DEFAULT_CODE_SECTION_START;
+extern const int DEFAULT_CODE_SECTION_END;
+
+extern const int DEFAULT_CSTACK_SECTION_START;
+extern const int DEFAULT_CSTACK_SECTION_END;
+
+__STATIC_INLINE__ cpu_addr_t fault_code_start(void)
+{
+    return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_START));
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_code_limit(void)
+{
+    return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_END));
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_msp_start(void)
+{
+    return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_START));
+}
+
+__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void)
+{
+    return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_END));
+}
+
+#endif
+
+__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer);
+
+__KERNEL__ int fault_default_log_writer(const char *format, ...);
+
+__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame);
+
+#endif
+
+#endif /* _TOS_FAULT_H_ */
+

arch/arm/arm-v7m/common/tos_cpu.c

@@ -0,0 +1,276 @@
+#include <tos.h>
+
+__API__ uint32_t tos_cpu_clz(uint32_t val)
+{
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 0u)
+    uint32_t nbr_lead_zeros = 0;
+
+    if (!(val & 0XFFFF0000)) {
+        val <<= 16;
+        nbr_lead_zeros += 16;
+    }
+
+    if (!(val & 0XFF000000)) {
+        val <<= 8;
+        nbr_lead_zeros += 8;
+    }
+
+    if (!(val & 0XF0000000)) {
+        val <<= 4;
+        nbr_lead_zeros += 4;
+    }
+
+    if (!(val & 0XC0000000)) {
+        val <<= 2;
+        nbr_lead_zeros += 2;
+    }
+
+    if (!(val & 0X80000000)) {
+        nbr_lead_zeros += 1;
+    }
+
+    if (!val) {
+        nbr_lead_zeros += 1;
+    }
+
+    return (nbr_lead_zeros);
+#else
+    return port_clz(val);
+#endif
+}
+
+__API__ void tos_cpu_int_disable(void)
+{
+    port_int_disable();
+}
+
+__API__ void tos_cpu_int_enable(void)
+{
+    port_int_enable();
+}
+
+__API__ cpu_cpsr_t tos_cpu_cpsr_save(void)
+{
+    return port_cpsr_save();
+}
+
+__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr)
+{
+    port_cpsr_restore(cpsr);
+}
+
+__KERNEL__ void cpu_init(void)
+{
+    k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second;
+    cpu_systick_init(k_cpu_cycle_per_tick);
+
+#if (TOS_CFG_CPU_HRTIMER_EN > 0)
+    tos_cpu_hrtimer_init();
+#endif
+}
+
+__KERNEL__ void cpu_reset(void)
+{
+    port_cpu_reset();
+}
+
+__KERNEL__ void cpu_sched_start(void)
+{
+    port_sched_start();
+}
+
+__KERNEL__ void cpu_context_switch(void)
+{
+    port_context_switch();
+}
+
+__KERNEL__ void cpu_irq_context_switch(void)
+{
+    port_irq_context_switch();
+}
+
+__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
+{
+    port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO);
+    port_systick_config(cycle_per_tick);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+/**
+ * @brief Set value to systick reload value register
+ *
+ * @param cycles The value set to register
+ *
+ * @return None
+ */
+__STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick)
+{
+    port_systick_reload(cycle_per_tick);
+}
+
+/**
+ * @brief Enable systick interrupt
+ *
+ * @return None
+ */
+__KERNEL__ void cpu_systick_resume(void)
+{
+    port_systick_resume();
+}
+
+/**
+ * @brief Disable systick interrupt
+ *
+ * @return None
+ */
+__KERNEL__ void cpu_systick_suspend(void)
+{
+    port_systick_suspend();
+}
+
+__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void)
+{
+    return port_systick_max_delay_millisecond();
+}
+
+__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond)
+{
+    k_cycle_t cycles;
+
+    cycles = (k_cycle_t)((uint64_t)millisecond * TOS_CFG_CPU_CLOCK / K_TIME_MILLISEC_PER_SEC); /* CLOCK means cycle per second */
+
+    cpu_systick_reload(cycles - 12); /* interrupt delay */
+}
+
+__KERNEL__ void cpu_systick_pending_reset(void)
+{
+    port_systick_pending_reset();
+}
+
+__KERNEL__ void cpu_systick_reset(void)
+{
+    cpu_systick_reload(k_cpu_cycle_per_tick);
+}
+
+#endif /* TOS_CFG_TICKLESS_EN */
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__KERNEL__ void cpu_sleep_mode_enter(void)
+{
+    port_sleep_mode_enter();
+}
+
+__KERNEL__ void cpu_stop_mode_enter(void)
+{
+    port_stop_mode_enter();
+}
+
+__KERNEL__ void cpu_standby_mode_enter(void)
+{
+    port_standby_mode_enter();
+}
+
+#endif /* TOS_CFG_PWR_MGR_EN */
+
+__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry,
+                                              void *arg,
+                                              void *exit,
+                                              k_stack_t *stk_base,
+                                              size_t stk_size)
+{
+    cpu_data_t *sp;
+
+    sp = (cpu_data_t *)&stk_base[stk_size];
+    sp = (cpu_data_t *)((cpu_addr_t)sp & 0xFFFFFFF8);
+
+#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u
+    uint8_t *slot = (uint8_t *)&stk_base[0];
+    for (; slot < (uint8_t *)sp; ++slot) {
+        *slot = 0xCC;
+    }
+#endif
+
+    /* auto-saved on exception(pendSV) by hardware */
+    *--sp = (cpu_data_t)0x01000000u;    /* xPSR     */
+    *--sp = (cpu_data_t)entry;          /* entry    */
+    *--sp = (cpu_data_t)exit;           /* R14 (LR) */
+    *--sp = (cpu_data_t)0x12121212u;    /* R12      */
+    *--sp = (cpu_data_t)0x03030303u;    /* R3       */
+    *--sp = (cpu_data_t)0x02020202u;    /* R2       */
+    *--sp = (cpu_data_t)0x01010101u;    /* R1       */
+    *--sp = (cpu_data_t)arg;            /* R0: arg  */
+
+    /* Remaining registers saved on process stack */
+    /* EXC_RETURN = 0xFFFFFFFDL
+       Initial state: Thread mode +  non-floating-point state + PSP
+       31 - 28 : EXC_RETURN flag, 0xF
+       27 -  5 : reserved, 0xFFFFFE
+       4       : 1, basic stack frame; 0, extended stack frame
+       3       : 1, return to Thread mode; 0, return to Handler mode
+       2       : 1, return to PSP; 0, return to MSP
+       1       : reserved, 0
+       0       : reserved, 1
+     */
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+    *--sp = (cpu_data_t)0xFFFFFFFDL;
+#endif
+
+    *--sp = (cpu_data_t)0x11111111u;    /* R11      */
+    *--sp = (cpu_data_t)0x10101010u;    /* R10      */
+    *--sp = (cpu_data_t)0x09090909u;    /* R9       */
+    *--sp = (cpu_data_t)0x08080808u;    /* R8       */
+    *--sp = (cpu_data_t)0x07070707u;    /* R7       */
+    *--sp = (cpu_data_t)0x06060606u;    /* R6       */
+    *--sp = (cpu_data_t)0x05050505u;    /* R5       */
+    *--sp = (cpu_data_t)0x04040404u;    /* R4       */
+
+    return (k_stack_t *)sp;
+}
+
+#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u
+
+__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth)
+{
+    uint8_t *slot;
+    uint8_t *sp, *bp;
+    int the_depth = 0;
+
+    bp = (uint8_t *)&stk_base[0];
+
+    sp = &stk_base[stk_size];
+    sp = (uint8_t *)((cpu_addr_t)sp & 0xFFFFFFF8);
+
+    for (slot = sp - 1; slot >= bp; --slot) {
+        if (*slot != 0xCC) {
+            the_depth = sp - slot;
+        }
+    }
+
+    *depth = the_depth;
+    if (the_depth == stk_size) {
+        return K_ERR_TASK_STK_OVERFLOW;
+    }
+
+    return K_ERR_NONE;
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+__KERNEL__ void cpu_flush_fpu(void)
+{
+    (void)__get_FPSCR();
+}
+#endif
+
+__KERNEL__ void cpu_fault_diagnosis(void)
+{
+    port_fault_diagnosis();
+}
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/common/tos_fault.c

@@ -0,0 +1,251 @@
+#include "tos.h"
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+
+__STATIC_INLINE__ void fault_spin(void)
+{
+    tos_knl_sched_lock();
+    tos_cpu_int_disable();
+    while (K_TRUE) {
+        ;
+    }
+}
+
+/* EXC_RETURN:
+   31 - 28 : EXC_RETURN flag
+   27 -  5 : reserved
+   4       : 1, basic stack frame; 0, extended stack frame
+   3       : 1, return to Thread mode; 0, return to Handler mode
+   2       : 1, return to PSP; 0, return to MSP
+   1       : reserved, 0
+   0       : reserved, 1
+ */
+__STATIC_INLINE__ int fault_is_on_task(cpu_data_t lr)
+{
+    return (lr & (1u << 2)) != 0;
+}
+
+__STATIC_INLINE__ int fault_is_thumb(cpu_data_t psr)
+{
+    return (psr & (1u << 24)) != 0;
+}
+
+__STATIC_INLINE__ int fault_is_code(fault_info_t *info, cpu_data_t value)
+{
+    return value >= info->code_start && value <= info->code_limit;
+}
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+__STATIC_INLINE__ int fault_is_extended_stack_frame(cpu_data_t lr)
+{
+    return (lr & (1u << 4)) == 0;
+}
+
+__STATIC__ void fault_dump_fpu_frame(fault_fpu_frame_t *fpu_frame)
+{
+    /*
+     * As known, v7-m has a feature named "LAZY PUSH", for the reason we do not do any float
+     * operation in fault_backtrace, cpu will not do the real fpu register push to the stack.
+     * that means the value we dump in fault_dump_fpu_frame will not be the correct value of
+     * each FPU register.
+     * We define a function here which access to FPSCR, if this function involved, cpu will do
+     * the real FPU register push so we will get the correct dump.
+     * I know it's ugly, but it works. If you know a better way, please tell me.
+     */
+    cpu_flush_fpu();
+
+    k_fault_log_writer("\n\n====================== FPU Registers =======================\n");
+    k_fault_log_writer("  %s: %08x\n", "FPSCR", fpu_frame->fpscr);
+    k_fault_log_writer("  %s: %08x  %s: %08x  %s: %08x  %s: %08x\n",
+                                            "S0 ", fpu_frame->s0,
+                                            "S1 ", fpu_frame->s1,
+                                            "S2 ", fpu_frame->s2,
+                                            "S3 ", fpu_frame->s3);
+    k_fault_log_writer("  %s: %08x  %s: %08x  %s: %08x  %s: %08x\n",
+                                            "S4 ", fpu_frame->s4,
+                                            "S5 ", fpu_frame->s5,
+                                            "S6 ", fpu_frame->s6,
+                                            "S7 ", fpu_frame->s7);
+    k_fault_log_writer("  %s: %08x  %s: %08x  %s: %08x  %s: %08x\n",
+                                            "S8 ", fpu_frame->s8,
+                                            "S9 ", fpu_frame->s9,
+                                            "S10", fpu_frame->s10,
+                                            "S11", fpu_frame->s11);
+    k_fault_log_writer("  %s: %08x  %s: %08x  %s: %08x  %s: %08x\n",
+                                            "S12", fpu_frame->s12,
+                                            "S13", fpu_frame->s13,
+                                            "S14", fpu_frame->s14,
+                                            "S15", fpu_frame->s15);
+}
+
+#endif
+
+__STATIC__ void fault_dump_cpu_frame(fault_cpu_frame_t *cpu_frame)
+{
+    k_fault_log_writer("\n\n====================== CPU Registers =======================\n");
+    k_fault_log_writer("  %s: %08x  %s: %08x  %s: %08x  %s: %08x\n",
+                                                        "R0 ", cpu_frame->r0,
+                                                        "R1 ", cpu_frame->r1,
+                                                        "R2 ", cpu_frame->r2,
+                                                        "R3 ", cpu_frame->r3);
+    k_fault_log_writer("  %s: %08x  %s: %08x  %s: %08x  %s: %08x\n",
+                                                        "R12", cpu_frame->r12,
+                                                        "LR ", cpu_frame->lr,
+                                                        "PC ", cpu_frame->pc,
+                                                        "PSR", cpu_frame->spsr);
+}
+
+__STATIC__ void fault_dump_stack(fault_info_t *info, size_t depth)
+{
+    cpu_addr_t sp = info->sp_before_fault;;
+
+    k_fault_log_writer("\nTASK STACK DUMP:\n");
+    while (sp <= info->stack_limit && depth--) {
+        k_fault_log_writer("  addr: %08x  data: %08x\n", sp, (cpu_data_t)*(cpu_data_t *)sp);
+        sp += sizeof(cpu_addr_t);
+    }
+}
+
+__STATIC__ void fault_call_stack_backtrace(fault_info_t *info, size_t depth)
+{
+    cpu_data_t value;
+    cpu_addr_t sp = info->sp_before_fault;
+
+    if (info->is_stk_ovrf) {
+        return;
+    }
+
+    k_fault_log_writer("\n\n====================== Dump Call Stack =====================\n");
+
+    k_fault_log_writer("  %x\n", info->pc);
+
+    /* walk through the stack, check every content on stack whether is a instruction(code) */
+    for (; sp < info->stack_limit && depth; sp += sizeof(cpu_addr_t)) {
+        value = *((cpu_addr_t *)sp) - sizeof(cpu_addr_t);
+
+        /* if thumb, a instruction's first bit must be 1 */
+        if (info->is_thumb && !(value & 1)) {
+            continue;
+        }
+
+        if (fault_is_code(info, value)) {
+            k_fault_log_writer("  %x\n", value);
+            --depth;
+        }
+    }
+}
+
+__STATIC__ void fault_dump_task(fault_info_t *info)
+{
+    k_task_t *task;
+
+    if (!info->is_on_task) {
+        return;
+    }
+
+    task = k_curr_task;
+    k_fault_log_writer("\n\n====================== Fault on task =======================\n");
+    k_fault_log_writer("  TASK NAME:  %s\n", task->name);
+    k_fault_log_writer("  STK BASE:   %x\n", info->stack_start);
+    k_fault_log_writer("  STK SIZE:   %x\n", task->stk_size * sizeof(k_stack_t));
+    k_fault_log_writer("  STK LIMIT:  %x\n", info->stack_limit);
+
+    if (!info->is_stk_ovrf) {
+        fault_dump_stack(info, K_FAULT_STACK_DUMP_DEPTH);
+    }
+}
+
+__STATIC__ void fault_dump_information(fault_info_t *info)
+{
+    k_fault_log_writer("\n\n================== Dump Fault Information ==================\n");
+    k_fault_log_writer("  THUMB:     %s\n", info->is_thumb ? "TRUE" : "FALSE");
+    k_fault_log_writer("  ON TASK:   %s\n", info->is_on_task? "TRUE" : "FALSE");
+    k_fault_log_writer("  STK OVRF:  %s\n", info->is_stk_ovrf? "TRUE" : "FALSE");
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+    k_fault_log_writer("  EXT STK:   %s\n", info->is_ext_stk_frm? "TRUE" : "FALSE");
+#endif
+
+    k_fault_log_writer("  PC:        %08x\n", info->pc);
+    k_fault_log_writer("  SP:        %08x\n", info->sp_before_fault);
+    k_fault_log_writer("  STK START: %08x\n", info->stack_start);
+    k_fault_log_writer("  STK LIMIT: %08x\n", info->stack_limit);
+    k_fault_log_writer("  COD START: %08x\n", info->code_start);
+    k_fault_log_writer("  COD LIMIT: %08x\n", info->code_limit);
+}
+
+__STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame, fault_info_t *info)
+{
+    info->is_thumb = fault_is_thumb(frame->cpu_frame.spsr);
+    info->is_on_task = fault_is_on_task(lr);
+
+    info->pc = frame->cpu_frame.pc;
+
+    info->sp_before_fault = (cpu_addr_t)frame + sizeof(fault_cpu_frame_t);
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+    info->is_ext_stk_frm = fault_is_extended_stack_frame(lr);
+
+    if (info->is_ext_stk_frm) {
+        info->sp_before_fault += sizeof(fault_fpu_frame_t);
+    }
+#endif
+
+    info->code_start = fault_code_start();
+    info->code_limit = fault_code_limit();
+
+    if (info->is_on_task) {
+        info->stack_start = (cpu_addr_t)k_curr_task->stk_base;
+        info->stack_limit = info->stack_start + k_curr_task->stk_size * sizeof(k_task_t);
+    } else {
+        info->stack_start = fault_msp_start();
+        info->stack_limit = fault_msp_limit();
+    }
+
+    info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit);
+}
+
+__KERNEL__ int fault_default_log_writer(const char *format, ...)
+{
+    int len;
+    va_list ap;
+
+    va_start(ap, format);
+    len = vprintf(format, ap);
+    va_end(ap);
+
+    return len;
+}
+
+__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer)
+{
+    k_fault_log_writer = log_writer;
+}
+
+__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame)
+{
+    fault_info_t info;
+
+    fault_gather_information(lr, frame, &info);
+
+    fault_dump_information(&info);
+
+    fault_dump_task(&info);
+
+    fault_dump_cpu_frame(&frame->cpu_frame);
+
+#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
+    if (info.is_ext_stk_frm) {
+        fault_dump_fpu_frame(&frame->fpu_frame);
+    }
+#endif
+
+    fault_call_stack_backtrace(&info, K_FAULT_CALL_STACK_BACKTRACE_DEPTH);
+
+    cpu_fault_diagnosis();
+
+    fault_spin();
+}
+
+#endif
+

arch/arm/arm-v7m/cortex-m0+/armcc/port.h

@@ -0,0 +1,73 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m0+/armcc/port_c.c

@@ -0,0 +1,128 @@
+#include "tos.h"
+#include "core_cm0plus.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__PORT__ void port_fault_diagnosis(void)
+{
+    k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n");
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m0+/armcc/port_config.h

@@ -0,0 +1,29 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  0u
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m0+/armcc/port_s.S

@@ -0,0 +1,137 @@
+    EXPORT  port_int_disable
+    EXPORT  port_int_enable
+
+    EXPORT  port_cpsr_save
+    EXPORT  port_cpsr_restore
+
+    EXPORT  port_sched_start
+    EXPORT  port_context_switch
+    EXPORT  port_irq_context_switch
+
+    EXPORT  PendSV_Handler
+
+    IMPORT  k_curr_task
+    IMPORT  k_next_task
+
+
+NVIC_INT_CTRL   EQU     0xE000ED04                              ; Interrupt control state register.
+NVIC_SYSPRI14   EQU     0xE000ED20                              ; System priority register (priority 14).
+NVIC_PENDSV_PRI EQU     0x00FF0000                              ; PendSV priority value (lowest).
+NVIC_PENDSVSET  EQU     0x10000000                              ; Value to trigger PendSV exception.
+
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    GLOBAL port_int_disable
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_int_enable
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_save
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_restore
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+    GLOBAL port_sched_start
+port_sched_start
+    LDR     R0, =NVIC_SYSPRI14
+    LDR     R1, =NVIC_PENDSV_PRI
+    STR     R1, [R0]
+
+    MOVS    R0, #0
+    MSR     PSP, R0
+
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+
+    CPSIE   I
+
+__unreachable
+    B       __unreachable
+
+
+    GLOBAL port_context_switch
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL port_irq_context_switch
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL PendSV_Handler
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+    CMP     R0, #0
+    BEQ     PendSVHandler_nosave
+
+    SUBS    R0, R0, #0x20
+    STMIA   R0!, {R4 - R7}
+    MOV     R4, R8                
+    MOV     R5, R9
+    MOV     R6, R10
+    MOV     R7, R11
+    STMIA   R0!, {R4-R7}
+    SUBS    R0, R0, #0x20
+
+    LDR     R1, =k_curr_task
+    LDR     R1, [R1]
+    STR     R0, [R1]
+
+PendSVHandler_nosave
+    LDR     R0, =k_curr_task
+    LDR     R1, =k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    LDR     R0, [R2]
+
+    LDMIA   R0!, {R4 - R7}
+    LDMIA   R0!, {R2 - R3}
+    MOV     R8, R2       
+    MOV     R9, R3
+    LDMIA   R0!, {R2 - R3}          
+    MOV     R10, R2                 
+    MOV     R11, R3 
+    MSR     PSP, R0
+
+    MOV     R0, R14
+    MOVS    R1, #0x04
+    ORRS    R0, R1
+    MOV     R14, R0
+
+    CPSIE   I
+
+    BX      LR
+
+    ALIGN
+
+    END
+

arch/arm/arm-v7m/cortex-m0+/gcc/port.h

@@ -0,0 +1,73 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m0+/gcc/port_c.c

@@ -0,0 +1,128 @@
+#include "tos.h"
+#include "core_cm0plus.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__PORT__ void port_fault_diagnosis(void)
+{
+    k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n");
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m0+/gcc/port_config.h

@@ -0,0 +1,29 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  0u
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m0+/gcc/port_s.S

@@ -0,0 +1,143 @@
+    .global  port_int_disable
+    .global  port_int_enable
+
+    .global  port_cpsr_save
+    .global  port_cpsr_restore
+
+    .global  port_sched_start
+    .global  port_context_switch
+    .global  port_irq_context_switch
+
+    .global  PendSV_Handler
+
+    .global  k_curr_task
+    .global  k_next_task
+
+
+.equ NVIC_INT_CTRL   ,     0xE000ED04                              @Interrupt control state register.
+.equ NVIC_SYSPRI14   ,     0xE000ED20                              @System priority register (priority 14).
+.equ NVIC_PENDSV_PRI ,     0x00FF0000                              @ PendSV priority value (lowest).
+.equ NVIC_PENDSVSET  ,     0x10000000                              @ Value to trigger PendSV exception.
+
+
+   .text
+   .align 2
+   .thumb
+   .syntax unified
+
+.type port_int_disable, %function
+port_int_disable:
+    CPSID   I
+    BX      LR
+
+
+.type port_int_enable, %function
+port_int_enable:
+    CPSIE   I
+    BX      LR
+
+
+.type port_cpsr_save, %function
+port_cpsr_save:
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+.type port_cpsr_restore, %function
+port_cpsr_restore:
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+.thumb_func
+.type port_sched_start, %function
+port_sched_start:
+    LDR     R0, =NVIC_SYSPRI14
+
+
+    LDR     R1, =NVIC_PENDSV_PRI
+
+	
+    STR    R1, [R0]
+
+    MOVS    R0, #0
+    MSR     PSP, R0
+
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+
+    CPSIE   I
+
+__unreachable:
+    B       __unreachable
+
+
+.thumb_func
+.type port_context_switch, %function
+port_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type port_irq_context_switch, %function
+port_irq_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type PendSV_Handler, %function
+PendSV_Handler:
+    CPSID   I
+    MRS     R0, PSP
+    CMP     R0, #0
+    BEQ     PendSVHandler_nosave
+
+    SUBS    R0, R0, #0x20
+    STMIA   R0!, {R4 - R7}
+    MOV     R4, R8                
+    MOV     R5, R9
+    MOV     R6, R10
+    MOV     R7, R11
+    STMIA   R0!, {R4-R7}
+    SUBS    R0, R0, #0x20
+
+    LDR     R1, =k_curr_task
+    LDR     R1, [R1]
+    STR     R0, [R1]
+
+PendSVHandler_nosave:
+    LDR     R0, =k_curr_task
+    LDR     R1, =k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    LDR     R0, [R2]
+
+    LDMIA   R0!, {R4 - R7}
+    LDMIA   R0!, {R2 - R3}
+    MOV     R8, R2       
+    MOV     R9, R3
+    LDMIA   R0!, {R2 - R3}          
+    MOV     R10, R2                 
+    MOV     R11, R3 
+    MSR     PSP, R0
+
+    MOV     R0, R14
+    MOVS    R1, #0x04
+    ORRS    R0, R1
+    MOV     R14, R0
+
+    CPSIE   I
+
+    BX      LR
+
+.end
+

arch/arm/arm-v7m/cortex-m0+/iccarm/port.h

@@ -0,0 +1,73 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m0+/iccarm/port_c.c

@@ -0,0 +1,128 @@
+#include "tos.h"
+#include "core_cm0plus.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__PORT__ void port_fault_diagnosis(void)
+{
+    k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n");
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m0+/iccarm/port_config.h

@@ -0,0 +1,29 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  0u
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m0+/iccarm/port_s.S

@@ -0,0 +1,126 @@
+    PUBLIC  port_int_disable
+    PUBLIC  port_int_enable
+
+    PUBLIC  port_cpsr_save
+    PUBLIC  port_cpsr_restore
+
+    PUBLIC  port_sched_start
+    PUBLIC  port_context_switch
+    PUBLIC  port_irq_context_switch
+
+    PUBLIC  PendSV_Handler
+
+    EXTERN  k_curr_task
+    EXTERN  k_next_task
+
+
+NVIC_INT_CTRL   EQU     0xE000ED04                              ; Interrupt control state register.
+NVIC_SYSPRI14   EQU     0xE000ED20                              ; System priority register (priority 14).
+NVIC_PENDSV_PRI EQU     0x00FF0000                              ; PendSV priority value (lowest).
+NVIC_PENDSVSET  EQU     0x10000000                              ; Value to trigger PendSV exception.
+
+
+    RSEG CODE:CODE:NOROOT(2)
+    THUMB
+
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+port_sched_start
+    LDR     R0, =NVIC_SYSPRI14
+    LDR     R1, =NVIC_PENDSV_PRI
+    STR     R1, [R0]
+
+    MOVS    R0, #0
+    MSR     PSP, R0
+
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+
+    CPSIE   I
+
+__unreachable
+    B       __unreachable
+
+
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+    CMP     R0, #0
+    BEQ     PendSVHandler_nosave
+
+    SUBS    R0, R0, #0x20
+    STMIA   R0!, {R4 - R7}
+    MOV     R4, R8                
+    MOV     R5, R9
+    MOV     R6, R10
+    MOV     R7, R11
+    STMIA   R0!, {R4-R7}
+    SUBS    R0, R0, #0x20
+
+    LDR     R1, =k_curr_task
+    LDR     R1, [R1]
+    STR     R0, [R1]
+
+PendSVHandler_nosave
+    LDR     R0, =k_curr_task
+    LDR     R1, =k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    LDR     R0, [R2]
+
+    LDMIA   R0!, {R4 - R7}
+    LDMIA   R0!, {R2 - R3}
+    MOV     R8, R2       
+    MOV     R9, R3
+    LDMIA   R0!, {R2 - R3}          
+    MOV     R10, R2                 
+    MOV     R11, R3 
+    MSR     PSP, R0
+
+    MOV     R0, R14
+    MOVS    R1, #0x04
+    ORRS    R0, R1
+    MOV     R14, R0
+
+    CPSIE   I
+
+    BX      LR
+
+
+    END
+

arch/arm/arm-v7m/cortex-m3/armcc/port.h

@@ -0,0 +1,311 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m3/armcc/port_c.c

@@ -0,0 +1,269 @@
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos.h"
+#include "core_cm3.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m3/armcc/port_config.h

@@ -0,0 +1,29 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m3/armcc/port_s.S

@@ -0,0 +1,125 @@
+    EXPORT  port_int_disable
+    EXPORT  port_int_enable
+
+    EXPORT  port_cpsr_save
+    EXPORT  port_cpsr_restore
+
+    EXPORT  port_sched_start
+    EXPORT  port_context_switch
+    EXPORT  port_irq_context_switch
+
+    EXPORT  port_clz
+
+    EXPORT  PendSV_Handler
+
+    IMPORT  k_curr_task
+    IMPORT  k_next_task
+
+
+NVIC_INT_CTRL   EQU     0xE000ED04
+NVIC_SYSPRI14   EQU     0xE000ED22
+NVIC_PENDSV_PRI EQU           0xFF
+NVIC_PENDSVSET  EQU     0x10000000
+
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+
+    GLOBAL port_int_disable
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_int_enable
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_save
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_restore
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+    GLOBAL port_clz
+port_clz
+    CLZ     R0, R0
+    BX      LR
+
+
+    GLOBAL port_sched_start
+port_sched_start
+    LDR     R0, =NVIC_SYSPRI14
+    LDR     R1, =NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    MOVS    R0, #0
+    MSR     PSP, R0
+
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+
+    CPSIE   I
+
+__unreachable
+    B       __unreachable
+
+
+    GLOBAL port_context_switch
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL port_irq_context_switch
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL PendSV_Handler
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+    CBZ     R0, PendSVHandler_nosave
+
+    SUBS    R0, R0, #0x20
+    STM     R0, {R4 - R11}
+
+    LDR     R1, =k_curr_task
+    LDR     R1, [R1]
+    STR     R0, [R1]
+
+PendSVHandler_nosave
+    LDR     R0, =k_curr_task
+    LDR     R1, =k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    LDR     R0, [R2]
+    LDM     R0, {R4 - R11}
+    ADDS    R0, R0, #0x20
+    MSR     PSP, R0
+    ORR     LR, LR, #0x04
+    CPSIE   I
+    BX      LR
+    NOP
+    END
+

arch/arm/arm-v7m/cortex-m3/gcc/port.h

@@ -0,0 +1,311 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m3/gcc/port_c.c

@@ -0,0 +1,245 @@
+#include "tos.h"
+#include "core_cm3.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m3/gcc/port_config.h

@@ -0,0 +1,29 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m3/gcc/port_s.S

@@ -0,0 +1,129 @@
+    .global  port_int_disable
+    .global  port_int_enable
+
+    .global  port_cpsr_save
+    .global  port_cpsr_restore
+
+    .global  port_sched_start
+    .global  port_context_switch
+    .global  port_irq_context_switch
+
+    .global  port_clz
+
+    .global  PendSV_Handler
+
+    .global  k_curr_task
+    .global  k_next_task
+
+
+.equ NVIC_INT_CTRL   ,     0xE000ED04                              @Interrupt control state register.
+.equ NVIC_SYSPRI14   ,     0xE000ED22                              @System priority register (priority 14).
+.equ NVIC_PENDSV_PRI ,     0x000000FF                              @ PendSV priority value (lowest).
+.equ NVIC_PENDSVSET  ,     0x10000000                              @ Value to trigger PendSV exception.
+
+
+   .text
+   .align 2
+   .thumb
+   .syntax unified
+
+.type port_int_disable, %function
+port_int_disable:
+    CPSID   I
+    BX      LR
+
+
+.type port_int_enable, %function
+port_int_enable:
+    CPSIE   I
+    BX      LR
+
+
+.type port_cpsr_save, %function
+port_cpsr_save:
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+.type port_cpsr_restore, %function
+port_cpsr_restore:
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+.type port_clz, %function
+port_clz:
+    CLZ     R0, R0
+    BX      LR
+
+
+.thumb_func
+.type port_sched_start, %function
+port_sched_start:
+    LDR     R0, =NVIC_SYSPRI14
+    LDR     R1, =NVIC_PENDSV_PRI
+    STR    R1, [R0]
+
+    MOVS    R0, #0
+    MSR     PSP, R0
+
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+
+    CPSIE   I
+
+__unreachable:
+    B       __unreachable
+
+
+.thumb_func
+.type port_context_switch, %function
+port_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type port_irq_context_switch, %function
+port_irq_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type PendSV_Handler, %function
+PendSV_Handler:
+    CPSID   I
+    MRS     R0, PSP
+    CBZ     R0, PendSVHandler_nosave
+
+    SUBS    R0, R0, #0x20
+    STM     R0, {R4 - R11}
+
+
+    LDR     R1, =k_curr_task
+    LDR     R1, [R1]
+    STR     R0, [R1]
+
+PendSVHandler_nosave:
+    LDR     R0, =k_curr_task
+    LDR     R1, =k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    LDR     R0, [R2]
+    LDM     R0, {R4 - R11}
+    ADDS    R0, R0, #0x20
+    MSR     PSP, R0
+    ORR     LR, LR, #0x04
+    CPSIE   I
+    BX      LR
+    NOP
+.end
+

arch/arm/arm-v7m/cortex-m4/armcc/port.h

@@ -0,0 +1,312 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m4/armcc/port_c.c

@@ -0,0 +1,274 @@
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos.h"
+#include "core_cm4.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
+{
+    return SysTick_LOAD_RELOAD_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m4/armcc/port_config.h

@@ -0,0 +1,35 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#ifndef __TARGET_FPU_SOFTVFP
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m4/armcc/port_s.S

@@ -0,0 +1,188 @@
+	EXPORT  port_int_disable
+    EXPORT  port_int_enable
+
+    EXPORT  port_cpsr_save
+    EXPORT  port_cpsr_restore
+
+    EXPORT  port_sched_start
+    EXPORT  port_context_switch
+    EXPORT  port_irq_context_switch
+
+    EXPORT  port_clz
+
+    EXPORT  PendSV_Handler
+
+    IMPORT  k_curr_task
+    IMPORT  k_next_task
+
+SCB_VTOR        EQU     0xE000ED08
+NVIC_INT_CTRL   EQU     0xE000ED04
+NVIC_SYSPRI14   EQU     0xE000ED22
+NVIC_PENDSV_PRI EQU     0xFF
+NVIC_PENDSVSET  EQU     0x10000000
+
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+
+	GLOBAL port_int_disable
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_int_enable
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_save
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_restore
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+    GLOBAL port_clz
+port_clz
+    CLZ     R0, R0
+    BX      LR
+
+
+    GLOBAL port_sched_start
+port_sched_start
+    CPSID   I
+
+    ; set pendsv priority lowest
+    ; otherwise trigger pendsv in port_irq_context_switch will cause a context swich in irq
+    ; that would be a disaster
+    MOV32   R0, NVIC_SYSPRI14
+    MOV32   R1, NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    ; k_curr_task = k_next_task
+    MOV32   R0, k_curr_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    ; sp = k_next_task->sp
+    LDR     R0, [R2]
+    ; PSP = sp
+    MSR     PSP, R0
+
+    ; using PSP
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    ; restore r4-11 from new process stack
+    LDMFD   SP!, {R4 - R11}
+
+    IF {FPU} != "SoftVFP"
+    ; ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    ENDIF
+
+    ; restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    ; load R12 and LR
+    LDMFD    SP!, {R12, LR}
+    ; load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+    GLOBAL port_context_switch
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL port_irq_context_switch
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL PendSV_Handler
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save
+    ; R0-R3, R12, LR, PC, xPSR is saved automatically here
+    IF {FPU} != "SoftVFP"
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    ; S0 - S16, FPSCR saved automatically here
+
+    ; save EXC_RETURN
+    STMFD   R0!, {LR}
+    ENDIF
+
+    ; save remaining regs r4-11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    ; k_curr_task->sp = PSP
+    MOV32   R5, k_curr_task
+    LDR     R6, [R5]
+    ; R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore
+    ; k_curr_task = k_next_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    ; R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    ; restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    IF {FPU} != "SoftVFP"
+    ; restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    ENDIF
+
+    ; Load PSP with new process SP
+    MSR     PSP, R0
+    CPSIE   I
+    ; R0-R3, R12, LR, PC, xPSR restored automatically here
+    ; S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+    ALIGN
+    END
+

arch/arm/arm-v7m/cortex-m4/gcc/port.h

@@ -0,0 +1,311 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m4/gcc/port_c.c

@@ -0,0 +1,248 @@
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos.h"
+#include "core_cm4.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m4/gcc/port_config.h

@@ -0,0 +1,35 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m4/gcc/port_s.S

@@ -0,0 +1,202 @@
+    .global port_int_disable
+    .global port_int_enable
+
+    .global port_cpsr_save
+    .global port_cpsr_restore
+
+    .global port_sched_start
+    .global port_context_switch
+    .global port_irq_context_switch
+
+    .global port_clz
+
+    .global PendSV_Handler
+
+    .extern k_curr_task
+    .extern k_next_task
+
+
+.equ SCB_VTOR,              0xE000ED08
+.equ NVIC_INT_CTRL,         0xE000ED04
+.equ NVIC_SYSPRI14,         0xE000ED22
+.equ NVIC_PENDSV_PRI,       0xFF
+.equ NVIC_PENDSVSET,        0x10000000
+
+
+   .text
+   .align 2
+   .thumb
+   .syntax unified
+
+
+.type port_int_disable, %function
+port_int_disable:
+    CPSID   I
+    BX      LR
+
+
+.type port_int_enable, %function
+port_int_enable:
+    CPSIE   I
+    BX      LR
+
+
+.type port_cpsr_save, %function
+port_cpsr_save:
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+.type port_cpsr_restore, %function
+port_cpsr_restore:
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+.type port_clz, %function
+port_clz:
+    CLZ     R0, R0
+    BX      LR
+
+
+.thumb_func
+.type port_sched_start, %function
+port_sched_start:
+    CPSID   I
+
+    @ set pendsv priority lowest
+    @ otherwise trigger pendsv in port_irq_context_switch will cause a context swich in irq
+    @ that would be a disaster
+    MOVW    R0, #:lower16:NVIC_SYSPRI14
+    MOVT    R0, #:upper16:NVIC_SYSPRI14
+
+    MOVW    R1, #:lower16:NVIC_PENDSV_PRI
+    MOVT    R1, #:upper16:NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    MOVW    R0, #:lower16:SCB_VTOR
+    MOVT    R0, #:upper16:SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    MOVW    R0, #:lower16:k_curr_task
+    MOVT    R0, #:upper16:k_curr_task
+
+    @ k_curr_task = k_next_task;
+    MOVW    R1, #:lower16:k_next_task
+    MOVT    R1, #:upper16:k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    @ sp = k_next_task->sp
+    LDR     R0, [R2]
+    @ PSP = sp
+    MSR     PSP, R0
+
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    @ restore r4-11 from new process stack
+    LDMFD    SP!, {R4 - R11}
+
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    #endif
+
+    @ restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    @ load R12 and LR
+    LDMFD    SP!, {R12, LR}    
+    @ load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+.thumb_func
+.type port_context_switch, %function
+port_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type port_irq_context_switch, %function
+port_irq_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type PendSV_Handler, %function
+PendSV_Handler:
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save:
+    @ R0-R3, R12, LR, PC, xPSR is saved automatically here
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    @ S0 - S16, FPSCR saved automatically here
+
+    @ save EXC_RETURN
+    STMFD   R0!, {LR}
+    #endif
+
+    @ save remaining regs r4 - 11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    @ k_curr_task->sp = PSP;
+    MOVW    R5, #:lower16:k_curr_task
+    MOVT    R5, #:upper16:k_curr_task
+    LDR     R6, [R5]
+    @ R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore:
+    @ k_curr_task = k_next_task;
+    MOVW    R1, #:lower16:k_next_task
+    MOVT    R1, #:upper16:k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    @ R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    @ restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    @ is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    #endif
+
+    @ Load PSP with new process SP
+    MSR     PSP, R0
+    
+    CPSIE   I
+
+    @ R0-R3, R12, LR, PC, xPSR restored automatically here
+    @ S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+.end
+

arch/arm/arm-v7m/cortex-m4/iccarm/port.h

@@ -0,0 +1,312 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m4/iccarm/port_c.c

@@ -0,0 +1,274 @@
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos.h"
+#include "core_cm4.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
+{
+    return SysTick_LOAD_RELOAD_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m4/iccarm/port_config.h

@@ -0,0 +1,35 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#ifndef __ARMVFP__
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m4/iccarm/port_s.S

@@ -0,0 +1,176 @@
+    PUBLIC  port_int_disable
+    PUBLIC  port_int_enable
+
+    PUBLIC  port_cpsr_save
+    PUBLIC  port_cpsr_restore
+
+    PUBLIC  port_sched_start
+    PUBLIC  port_context_switch
+    PUBLIC  port_irq_context_switch
+
+    PUBLIC  port_clz
+
+    PUBLIC  PendSV_Handler
+
+    EXTERN  k_curr_task
+    EXTERN  k_next_task
+
+SCB_VTOR        EQU     0xE000ED08
+NVIC_INT_CTRL   EQU     0xE000ED04
+NVIC_SYSPRI14   EQU     0xE000ED22
+NVIC_PENDSV_PRI EQU     0xFF
+NVIC_PENDSVSET  EQU     0x10000000
+
+
+    RSEG CODE:CODE:NOROOT(2)
+    THUMB
+
+
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+port_clz
+    CLZ     R0, R0
+    BX      LR
+
+
+port_sched_start
+    CPSID   I
+
+    ; set pendsv priority lowest
+    ; otherwise trigger pendsv in port_irq_context_switch will cause a context swich in irq
+    ; that would be a disaster
+    MOV32   R0, NVIC_SYSPRI14
+    MOV32   R1, NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    ; k_curr_task = k_next_task
+    MOV32   R0, k_curr_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    ; sp = k_next_task->sp
+    LDR     R0, [R2]
+    ; PSP = sp
+    MSR     PSP, R0
+
+    ; using PSP
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    ; restore r4-11 from new process stack
+    LDMFD   SP!, {R4 - R11}
+
+    #if defined(__ARMVFP__)
+    ; ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    #endif
+
+    ; restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    ; load R12 and LR
+    LDMFD    SP!, {R12, LR}
+    ; load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save
+    ; R0-R3, R12, LR, PC, xPSR is saved automatically here
+    #if defined(__ARMVFP__)
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    ; S0 - S16, FPSCR saved automatically here
+
+    ; save EXC_RETURN
+    STMFD   R0!, {LR}
+    #endif
+
+    ; save remaining regs r4-11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    ; k_curr_task->sp = PSP
+    MOV32   R5, k_curr_task
+    LDR     R6, [R5]
+    ; R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore
+    ; k_curr_task = k_next_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    ; R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    ; restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    #if defined(__ARMVFP__)
+    ; restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    #endif
+
+    ; Load PSP with new process SP
+    MSR     PSP, R0
+    CPSIE   I
+    ; R0-R3, R12, LR, PC, xPSR restored automatically here
+    ; S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+    END
+

arch/arm/arm-v7m/cortex-m7/armcc/port.h

@@ -0,0 +1,311 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m7/armcc/port_c.c

@@ -0,0 +1,269 @@
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos.h"
+#include "core_cm7.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m7/armcc/port_config.h

@@ -0,0 +1,35 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#ifndef __TARGET_FPU_SOFTVFP
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m7/armcc/port_s.S

@@ -0,0 +1,188 @@
+    EXPORT  port_int_disable
+    EXPORT  port_int_enable
+
+    EXPORT  port_cpsr_save
+    EXPORT  port_cpsr_restore
+
+    EXPORT  port_sched_start
+    EXPORT  port_context_switch
+    EXPORT  port_irq_context_switch
+    EXPORT  port_clz
+
+    EXPORT  PendSV_Handler
+
+    IMPORT  k_curr_task
+    IMPORT  k_next_task
+
+
+SCB_VTOR        EQU     0xE000ED08
+NVIC_INT_CTRL   EQU     0xE000ED04
+NVIC_SYSPRI14   EQU     0xE000ED22
+NVIC_PENDSV_PRI EQU     0xFF
+NVIC_PENDSVSET  EQU     0x10000000
+
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+
+    GLOBAL port_int_disable
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_int_enable
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_save
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_restore
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+    GLOBAL port_clz
+port_clz
+    CLZ     R0, R0
+    BX      LR
+
+
+	GLOBAL port_sched_start
+port_sched_start
+    CPSID   I
+
+    ; set pendsv priority lowest
+    ; otherwise trigger pendsv in port_irq_context_switch will cause a context swich in irq
+    ; that would be a disaster
+    MOV32   R0, NVIC_SYSPRI14
+    MOV32   R1, NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    ; k_curr_task = k_next_task
+    MOV32   R0, k_curr_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    ; sp = k_next_task->sp
+    LDR     R0, [R2]
+    ; PSP = sp
+    MSR     PSP, R0
+
+    ; using PSP
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    ; restore r4-11 from new process stack
+    LDMFD   SP!, {R4 - R11}
+
+    IF {FPU} != "SoftVFP"
+    ; ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    ENDIF
+
+    ; restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    ; load R12 and LR
+    LDMFD    SP!, {R12, LR}
+    ; load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+    GLOBAL port_context_switch
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL port_irq_context_switch
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL PendSV_Handler
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save
+    ; R0-R3, R12, LR, PC, xPSR is saved automatically here
+    IF {FPU} != "SoftVFP"
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    ; S0 - S16, FPSCR saved automatically here
+
+    ; save EXC_RETURN
+    STMFD   R0!, {LR}
+    ENDIF
+
+    ; save remaining regs r4 - 11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    ; k_curr_task->sp = PSP
+    MOV32   R5, k_curr_task
+    LDR     R6, [R5]
+    ; R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore
+    ; k_curr_task = k_next_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    ; R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    ; restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    IF {FPU} != "SoftVFP"
+    ; restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    ENDIF
+
+    ; Load PSP with new process SP
+    MSR     PSP, R0
+    CPSIE   I
+    ; R0-R3, R12, LR, PC, xPSR restored automatically here
+    ; S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+    ALIGN
+    END
+

arch/arm/arm-v7m/cortex-m7/gcc/port.h

@@ -0,0 +1,311 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m7/gcc/port_c.c

@@ -0,0 +1,248 @@
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos.h"
+#include "core_cm7.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m7/gcc/port_config.h

@@ -0,0 +1,35 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m7/gcc/port_s.S

@@ -0,0 +1,202 @@
+    .global port_int_disable
+    .global port_int_enable
+
+    .global port_cpsr_save
+    .global port_cpsr_restore
+
+    .global port_sched_start
+    .global port_context_switch
+    .global port_irq_context_switch
+
+    .global port_clz
+
+    .global PendSV_Handler
+
+    .extern k_curr_task
+    .extern k_next_task
+
+
+.equ SCB_VTOR,              0xE000ED08
+.equ NVIC_INT_CTRL,         0xE000ED04
+.equ NVIC_SYSPRI14,         0xE000ED22
+.equ NVIC_PENDSV_PRI,       0xFF
+.equ NVIC_PENDSVSET,        0x10000000
+
+
+   .text
+   .align 2
+   .thumb
+   .syntax unified
+
+
+.type port_int_disable, %function
+port_int_disable:
+    CPSID   I
+    BX      LR
+
+
+.type port_int_enable, %function
+port_int_enable:
+    CPSIE   I
+    BX      LR
+
+
+.type port_cpsr_save, %function
+port_cpsr_save:
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+.type port_cpsr_restore, %function
+port_cpsr_restore:
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+.type port_clz, %function
+port_clz:
+    CLZ     R0, R0
+    BX      LR
+
+
+.thumb_func
+.type port_sched_start, %function
+port_sched_start:
+    CPSID   I
+
+    @ set pendsv priority lowest
+    @ otherwise trigger pendsv in port_irq_context_switch will cause a context swich in irq
+    @ that would be a disaster
+    MOVW    R0, #:lower16:NVIC_SYSPRI14
+    MOVT    R0, #:upper16:NVIC_SYSPRI14
+
+    MOVW    R1, #:lower16:NVIC_PENDSV_PRI
+    MOVT    R1, #:upper16:NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    MOVW    R0, #:lower16:SCB_VTOR
+    MOVT    R0, #:upper16:SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    MOVW    R0, #:lower16:k_curr_task
+    MOVT    R0, #:upper16:k_curr_task
+
+    @ k_curr_task = k_next_task;
+    MOVW    R1, #:lower16:k_next_task
+    MOVT    R1, #:upper16:k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    @ sp = k_next_task->sp
+    LDR     R0, [R2]
+    @ PSP = sp
+    MSR     PSP, R0
+
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    @ restore r4-11 from new process stack
+    LDMFD    SP!, {R4 - R11}
+
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    #endif
+
+    @ restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    @ load R12 and LR
+    LDMFD    SP!, {R12, LR}    
+    @ load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+.thumb_func
+.type port_context_switch, %function
+port_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type port_irq_context_switch, %function
+port_irq_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type PendSV_Handler, %function
+PendSV_Handler:
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save:
+    @ R0-R3, R12, LR, PC, xPSR is saved automatically here
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    @ S0 - S16, FPSCR saved automatically here
+
+    @ save EXC_RETURN
+    STMFD   R0!, {LR}
+    #endif
+
+    @ save remaining regs r4 - 11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    @ k_curr_task->sp = PSP;
+    MOVW    R5, #:lower16:k_curr_task
+    MOVT    R5, #:upper16:k_curr_task
+    LDR     R6, [R5]
+    @ R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore:
+    @ k_curr_task = k_next_task;
+    MOVW    R1, #:lower16:k_next_task
+    MOVT    R1, #:upper16:k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    @ R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    @ restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    @ is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    #endif
+
+    @ Load PSP with new process SP
+    MSR     PSP, R0
+    
+    CPSIE   I
+
+    @ R0-R3, R12, LR, PC, xPSR restored automatically here
+    @ S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+.end
+

arch/arm/arm-v7m/cortex-m7/iccarm/port.h

@@ -0,0 +1,312 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v7m/cortex-m7/iccarm/port_c.c

@@ -0,0 +1,269 @@
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos.h"
+#include "core_cm7.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+
+    if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
+        SysTick->LOAD = max_cycle;
+    } else {
+        SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
+    }
+
+    SysTick->VAL = 0;
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v7m/cortex-m7/iccarm/port_config.h

@@ -0,0 +1,35 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE               CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH              CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN               0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT  1u
+
+#ifndef __ARMVFP__
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v7m/cortex-m7/iccarm/port_s.S

@@ -0,0 +1,176 @@
+    PUBLIC  port_int_disable
+    PUBLIC  port_int_enable
+
+    PUBLIC  port_cpsr_save
+    PUBLIC  port_cpsr_restore
+
+    PUBLIC  port_sched_start
+    PUBLIC  port_context_switch
+    PUBLIC  port_irq_context_switch
+
+    PUBLIC  port_clz
+
+    PUBLIC  PendSV_Handler
+
+    EXTERN  k_curr_task
+    EXTERN  k_next_task
+
+SCB_VTOR        EQU     0xE000ED08
+NVIC_INT_CTRL   EQU     0xE000ED04
+NVIC_SYSPRI14   EQU     0xE000ED22
+NVIC_PENDSV_PRI EQU     0xFF
+NVIC_PENDSVSET  EQU     0x10000000
+
+
+    RSEG CODE:CODE:NOROOT(2)
+    THUMB
+
+
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+port_clz
+    CLZ     R0, R0
+    BX      LR
+
+
+port_sched_start
+    CPSID   I
+
+    ; set pendsv priority lowest
+    ; otherwise trigger pendsv in port_irq_context_switch will cause a context swich in irq
+    ; that would be a disaster
+    MOV32   R0, NVIC_SYSPRI14
+    MOV32   R1, NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    ; k_curr_task = k_next_task
+    MOV32   R0, k_curr_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    ; sp = k_next_task->sp
+    LDR     R0, [R2]
+    ; PSP = sp
+    MSR     PSP, R0
+
+    ; using PSP
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    ; restore r4-11 from new process stack
+    LDMFD   SP!, {R4 - R11}
+
+    #if defined(__ARMVFP__)
+    ; ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    #endif
+
+    ; restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    ; load R12 and LR
+    LDMFD    SP!, {R12, LR}
+    ; load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save
+    ; R0-R3, R12, LR, PC, xPSR is saved automatically here
+    #if defined(__ARMVFP__)
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    ; S0 - S16, FPSCR saved automatically here
+
+    ; save EXC_RETURN
+    STMFD   R0!, {LR}
+    #endif
+
+    ; save remaining regs r4-11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    ; k_curr_task->sp = PSP
+    MOV32   R5, k_curr_task
+    LDR     R6, [R5]
+    ; R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore
+    ; k_curr_task = k_next_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    ; R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    ; restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    #if defined(__ARMVFP__)
+    ; restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    #endif
+
+    ; Load PSP with new process SP
+    MSR     PSP, R0
+    CPSIE   I
+    ; R0-R3, R12, LR, PC, xPSR restored automatically here
+    ; S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+    END
+