first commit for opensource
first commit for opensource
This commit is contained in:
supowang
88
board/NXP_Kinetis_K64/BSP/Src/main.c
Normal file
88
board/NXP_Kinetis_K64/BSP/Src/main.c
Normal file
@@ -0,0 +1,88 @@
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#include "gpio.h"
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#include "common.h"
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#include "uart.h"
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#include "cmsis_os.h"
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/* CH Kinetis<69>̼<EFBFBD><CCBC><EFBFBD> V2.50 <20>汾 */
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/* <20><EFBFBD><DEB8><EFBFBD>Ƶ <20><>ʹ<EFBFBD><CAB9> CMSIS<49><53><EFBFBD>ļ<EFBFBD> system_MKxxxx.c <20>е<EFBFBD> CLOCK_SETUP <20><> */
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/* UART <20><><EFBFBD>ٳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD>ṹ<EFBFBD><E1B9B9>֧<EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD>* ʹ<><CAB9>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>Ƽ<EFBFBD><C6BC><EFBFBD><EFBFBD><D7BC>ʼ<EFBFBD><CABC> */
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/*
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UART1_RX_PE01_TX_PE00
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UART0_RX_PF17_TX_PF18
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UART3_RX_PE05_TX_PE04
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UART5_RX_PF19_TX_PF20
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UART5_RX_PE09_TX_PE08
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UART2_RX_PE17_TX_PE16
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UART4_RX_PE25_TX_PE24
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UART0_RX_PA01_TX_PA02
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UART0_RX_PA15_TX_PA14
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UART3_RX_PB10_TX_PB11
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UART0_RX_PB16_TX_PB17
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UART1_RX_PC03_TX_PC04
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UART4_RX_PC14_TX_PC15
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UART3_RX_PC16_TX_PC17
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UART2_RX_PD02_TX_PD03
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UART0_RX_PD06_TX_PD07
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UART2_RX_PF13_TX_PF14
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UART5_RX_PD08_TX_PD09
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*/
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#define APPLICATION_TASK_STK_SIZE 1024
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extern void application_entry(void *arg);
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osThreadDef(application_entry, osPriorityNormal, 1, APPLICATION_TASK_STK_SIZE);
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#define TASK1_STK_SIZE 512
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void task1(void *arg);
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osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE);
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#define TASK2_STK_SIZE 512
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void task2(void *arg);
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osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);
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void SysTick_Handler(void)
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{
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if(tos_knl_is_running()) //OS<4F><53>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>,<2C><>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵ<EFBFBD><C4B5>ȴ<EFBFBD><C8B4><EFBFBD>
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{
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tos_knl_irq_enter(); //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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tos_tick_handler(); //<2F><><EFBFBD><EFBFBD>TencentOS tiny<6E><79>ʱ<EFBFBD>ӷ<EFBFBD><D3B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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tos_knl_irq_leave(); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD>ж<EFBFBD>
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}
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}
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void task1(void *arg)
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{
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int count = 1;
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while (1) {
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printf("###This is task1, %d\r\n", count++);
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osDelay(2000);
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}
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}
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void task2(void *arg)
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{
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int count = 1;
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while (1) {
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printf("***This is task2, %d\r\n", count++);
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osDelay(1000);
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}
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}
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void application_entry(void *arg)
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{
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osThreadCreate(osThread(task1), NULL); // Create task1
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osThreadCreate(osThread(task2), NULL); // Create task2
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}
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int main(void)
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{
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DelayInit();
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/* <20><>ʼ<EFBFBD><CABC>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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GPIO_QuickInit(HW_GPIOE, 6, kGPIO_Mode_OPP);
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/* <20><>ʼ<EFBFBD><CABC>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ʹ<><CAB9>UART0<54>˿ڵ<CBBF>PTD6<44><36><EFBFBD>ź<EFBFBD>PTD7<44><37><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>պͷ<D5BA><CDB7>ͣ<EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> baud 115200 */
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UART_QuickInit(UART0_RX_PD06_TX_PD07, 115200);
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printf("Welcome to TencentOS tiny\r\n");
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osKernelInitialize();
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osThreadCreate(osThread(application_entry), NULL);
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osKernelStart();
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}
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837
board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvoptx
Normal file
837
board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvoptx
Normal file
@@ -0,0 +1,837 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
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<SchemaVersion>1.0</SchemaVersion>
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<Header>### uVision Project, (C) Keil Software</Header>
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<Extensions>
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<cExt>*.c</cExt>
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<aExt>*.s*; *.src; *.a*</aExt>
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<oExt>*.obj; *.o</oExt>
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<lExt>*.lib</lExt>
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<tExt>*.txt; *.h; *.inc</tExt>
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<pExt>*.plm</pExt>
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<CppX>*.cpp</CppX>
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<nMigrate>0</nMigrate>
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</Extensions>
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<DaveTm>
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<dwLowDateTime>0</dwLowDateTime>
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<dwHighDateTime>0</dwHighDateTime>
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</DaveTm>
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<Target>
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<TargetName>TencentOS_tiny_K64</TargetName>
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<ToolsetNumber>0x4</ToolsetNumber>
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<ToolsetName>ARM-ADS</ToolsetName>
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<TargetOption>
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<CLKADS>12000000</CLKADS>
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<OPTTT>
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<gFlags>1</gFlags>
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||||
<BeepAtEnd>1</BeepAtEnd>
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||||
<RunSim>0</RunSim>
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<RunTarget>1</RunTarget>
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<RunAbUc>0</RunAbUc>
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</OPTTT>
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<OPTHX>
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<HexSelection>1</HexSelection>
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<FlashByte>65535</FlashByte>
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<HexRangeLowAddress>0</HexRangeLowAddress>
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<HexRangeHighAddress>0</HexRangeHighAddress>
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<HexOffset>0</HexOffset>
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</OPTHX>
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<OPTLEX>
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<PageWidth>79</PageWidth>
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<PageLength>66</PageLength>
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<TabStop>8</TabStop>
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<ListingPath>.\Listings\</ListingPath>
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</OPTLEX>
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<ListingPage>
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<CreateCListing>1</CreateCListing>
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<CreateAListing>1</CreateAListing>
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<CreateLListing>1</CreateLListing>
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||||
<CreateIListing>0</CreateIListing>
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||||
<AsmCond>1</AsmCond>
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||||
<AsmSymb>1</AsmSymb>
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||||
<AsmXref>0</AsmXref>
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||||
<CCond>1</CCond>
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||||
<CCode>0</CCode>
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||||
<CListInc>0</CListInc>
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<CSymb>0</CSymb>
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<LinkerCodeListing>0</LinkerCodeListing>
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</ListingPage>
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<OPTXL>
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<LMap>1</LMap>
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||||
<LComments>1</LComments>
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||||
<LGenerateSymbols>1</LGenerateSymbols>
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||||
<LLibSym>1</LLibSym>
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||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
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||||
</OPTXL>
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||||
<OPTFL>
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||||
<tvExp>1</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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||||
<IsCurrentTarget>1</IsCurrentTarget>
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||||
</OPTFL>
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||||
<CpuCode>8</CpuCode>
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<DebugOpt>
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<uSim>0</uSim>
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<uTrg>1</uTrg>
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<sLdApp>1</sLdApp>
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||||
<sGomain>1</sGomain>
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||||
<sRbreak>1</sRbreak>
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||||
<sRwatch>1</sRwatch>
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||||
<sRmem>1</sRmem>
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||||
<sRfunc>1</sRfunc>
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||||
<sRbox>1</sRbox>
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||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
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||||
<tRbreak>1</tRbreak>
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||||
<tRwatch>1</tRwatch>
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||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
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||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
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||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
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||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>4</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>Segger\JL2CM3.dll</pMon>
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||||
</DebugOpt>
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||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MK_P1M0 -FL0100000 -FS00 -FP0($$Device:MK64FN1M0xxx12$Flash\MK_P1M0.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U29999997 -O14 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000 -FP0($$Device:MK64FN1M0xxx12$Flash\MK_P1M0.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>startup</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\startup_MK64F12.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_MK64F12.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\CH-K-Lib\startup\DeviceSupport\system_MK64F12.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_MK64F12.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>drivers</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\CH-K-Lib\drivers\K\src\adc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>adc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\CH-K-Lib\drivers\K\src\can.c</PathWithFileName>
|
||||
<FilenameWithoutPath>can.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\CH-K-Lib\drivers\K\src\cmp.c</PathWithFileName>
|
||||
<FilenameWithoutPath>cmp.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\CH-K-Lib\drivers\K\src\common.c</PathWithFileName>
|
||||
<FilenameWithoutPath>common.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\CH-K-Lib\drivers\K\src\cpuidy.c</PathWithFileName>
|
||||
<FilenameWithoutPath>cpuidy.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>8</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\CH-K-Lib\drivers\K\src\crc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>crc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>9</FileNumber>
|
||||
<FileType>1</FileType>
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|
||||
<FileNumber>41</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_pend.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_pend.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>42</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_queue.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_queue.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>43</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_robin.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_robin.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>44</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_sched.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_sched.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>45</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_sem.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_sem.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>46</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_sys.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_sys.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>47</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_task.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_task.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>48</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_tick.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_tick.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>49</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_time.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_time.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>50</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_timer.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_timer.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>tos/cmsis</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>51</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\osal\cmsis_os\cmsis_os.c</PathWithFileName>
|
||||
<FilenameWithoutPath>cmsis_os.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
690
board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvprojx
Normal file
690
board/NXP_Kinetis_K64/KEIL/hello_world/TencentOS_tiny.uvprojx
Normal file
@@ -0,0 +1,690 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>TencentOS_tiny_K64</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MK64FN1M0xxx12</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>Keil.Kinetis_K60_DFP.1.4.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x30000) IRAM2(0x1FFF0000,0x10000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000 -FP0($$Device:MK64FN1M0xxx12$Flash\MK_P1M0.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:MK64FN1M0xxx12$Device\Include\MK64F12.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:MK64FN1M0xxx12$SVD\MK64F12.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>TencentOS_tiny</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x100000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
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|
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
772
board/NXP_Kinetis_K64/KEIL/hello_world/startup_MK60D10.s
Normal file
772
board/NXP_Kinetis_K64/KEIL/hello_world/startup_MK60D10.s
Normal file
@@ -0,0 +1,772 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_MK60D10.s
|
||||
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
|
||||
; * MK60D10
|
||||
; * @version: 1.3
|
||||
; * @date: 2012-10-29
|
||||
; *
|
||||
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
;*
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00001000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
|
||||
DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
|
||||
DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
|
||||
DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
|
||||
DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
|
||||
DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
|
||||
DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
|
||||
DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
|
||||
DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
|
||||
DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
|
||||
DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
|
||||
DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
|
||||
DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
|
||||
DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
|
||||
DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
|
||||
DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
|
||||
DCD DMA_Error_IRQHandler ; DMA Error Interrupt
|
||||
DCD MCM_IRQHandler ; Normal Interrupt
|
||||
DCD FTFL_IRQHandler ; FTFL Interrupt
|
||||
DCD Read_Collision_IRQHandler ; Read Collision Interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD Watchdog_IRQHandler ; WDOG Interrupt
|
||||
DCD RNG_IRQHandler ; RNGB Interrupt
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 interrupt
|
||||
DCD SPI0_IRQHandler ; SPI0 Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
|
||||
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
|
||||
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
|
||||
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
|
||||
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
|
||||
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
|
||||
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
|
||||
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
|
||||
DCD CAN1_ORed_Message_buffer_IRQHandler ; CAN1 OR'd message buffers interrupt
|
||||
DCD CAN1_Bus_Off_IRQHandler ; CAN1 bus off interrupt
|
||||
DCD CAN1_Error_IRQHandler ; CAN1 error interrupt
|
||||
DCD CAN1_Tx_Warning_IRQHandler ; CAN1 Tx warning interrupt
|
||||
DCD CAN1_Rx_Warning_IRQHandler ; CAN1 Rx warning interrupt
|
||||
DCD CAN1_Wake_Up_IRQHandler ; CAN1 wake up interrupt
|
||||
DCD Reserved59_IRQHandler ; Reserved interrupt 59
|
||||
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
|
||||
DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
|
||||
DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
|
||||
DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
|
||||
DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
|
||||
DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
|
||||
DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
|
||||
DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
|
||||
DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
|
||||
DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
|
||||
DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
|
||||
DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
|
||||
DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD CMP1_IRQHandler ; CMP1 interrupt
|
||||
DCD CMP2_IRQHandler ; CMP2 interrupt
|
||||
DCD FTM0_IRQHandler ; FTM0 fault, overflow and chls interrupt
|
||||
DCD FTM1_IRQHandler ; FTM1 fault, overflow and chls interrupt
|
||||
DCD FTM2_IRQHandler ; FTM2 fault, overflow and chls interrupt
|
||||
DCD CMT_IRQHandler ; CMT interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT0_IRQHandler ; PIT timer chl 0 interrupt
|
||||
DCD PIT1_IRQHandler ; PIT timer chl 1 interrupt
|
||||
DCD PIT2_IRQHandler ; PIT timer chl 2 interrupt
|
||||
DCD PIT3_IRQHandler ; PIT timer chl 3 interrupt
|
||||
DCD PDB0_IRQHandler ; PDB0 Interrupt
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD USBDCD_IRQHandler ; USBDCD Interrupt
|
||||
DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
|
||||
DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
|
||||
DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
|
||||
DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
|
||||
DCD Reserved95_IRQHandler ; Reserved interrupt 95
|
||||
DCD SDHC_IRQHandler ; SDHC Interrupt
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 interrupt
|
||||
DCD TSI0_IRQHandler ; TSI0 Interrupt
|
||||
DCD MCG_IRQHandler ; MCG Interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD Reserved102_IRQHandler ; Reserved interrupt 102
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTB_IRQHandler ; Port B interrupt
|
||||
DCD PORTC_IRQHandler ; Port C interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
DCD PORTE_IRQHandler ; Port E interrupt
|
||||
DCD Reserved108_IRQHandler ; Reserved interrupt 108
|
||||
DCD Reserved109_IRQHandler ; Reserved interrupt 109
|
||||
DCD SWI_IRQHandler ; Software interrupt
|
||||
DCD Reserved111_IRQHandler ; Reserved interrupt 111
|
||||
DCD Reserved112_IRQHandler ; Reserved interrupt 112
|
||||
DCD Reserved113_IRQHandler ; Reserved interrupt 113
|
||||
DCD Reserved114_IRQHandler ; Reserved interrupt 114
|
||||
DCD Reserved115_IRQHandler ; Reserved interrupt 115
|
||||
DCD Reserved116_IRQHandler ; Reserved interrupt 116
|
||||
DCD Reserved117_IRQHandler ; Reserved interrupt 117
|
||||
DCD Reserved118_IRQHandler ; Reserved interrupt 118
|
||||
DCD Reserved119_IRQHandler ; Reserved interrupt 119
|
||||
DCD DefaultISR ; 120
|
||||
DCD DefaultISR ; 121
|
||||
DCD DefaultISR ; 122
|
||||
DCD DefaultISR ; 123
|
||||
DCD DefaultISR ; 124
|
||||
DCD DefaultISR ; 125
|
||||
DCD DefaultISR ; 126
|
||||
DCD DefaultISR ; 127
|
||||
DCD DefaultISR ; 128
|
||||
DCD DefaultISR ; 129
|
||||
DCD DefaultISR ; 130
|
||||
DCD DefaultISR ; 131
|
||||
DCD DefaultISR ; 132
|
||||
DCD DefaultISR ; 133
|
||||
DCD DefaultISR ; 134
|
||||
DCD DefaultISR ; 135
|
||||
DCD DefaultISR ; 136
|
||||
DCD DefaultISR ; 137
|
||||
DCD DefaultISR ; 138
|
||||
DCD DefaultISR ; 139
|
||||
DCD DefaultISR ; 140
|
||||
DCD DefaultISR ; 141
|
||||
DCD DefaultISR ; 142
|
||||
DCD DefaultISR ; 143
|
||||
DCD DefaultISR ; 144
|
||||
DCD DefaultISR ; 145
|
||||
DCD DefaultISR ; 146
|
||||
DCD DefaultISR ; 147
|
||||
DCD DefaultISR ; 148
|
||||
DCD DefaultISR ; 149
|
||||
DCD DefaultISR ; 150
|
||||
DCD DefaultISR ; 151
|
||||
DCD DefaultISR ; 152
|
||||
DCD DefaultISR ; 153
|
||||
DCD DefaultISR ; 154
|
||||
DCD DefaultISR ; 155
|
||||
DCD DefaultISR ; 156
|
||||
DCD DefaultISR ; 157
|
||||
DCD DefaultISR ; 158
|
||||
DCD DefaultISR ; 159
|
||||
DCD DefaultISR ; 160
|
||||
DCD DefaultISR ; 161
|
||||
DCD DefaultISR ; 162
|
||||
DCD DefaultISR ; 163
|
||||
DCD DefaultISR ; 164
|
||||
DCD DefaultISR ; 165
|
||||
DCD DefaultISR ; 166
|
||||
DCD DefaultISR ; 167
|
||||
DCD DefaultISR ; 168
|
||||
DCD DefaultISR ; 169
|
||||
DCD DefaultISR ; 170
|
||||
DCD DefaultISR ; 171
|
||||
DCD DefaultISR ; 172
|
||||
DCD DefaultISR ; 173
|
||||
DCD DefaultISR ; 174
|
||||
DCD DefaultISR ; 175
|
||||
DCD DefaultISR ; 176
|
||||
DCD DefaultISR ; 177
|
||||
DCD DefaultISR ; 178
|
||||
DCD DefaultISR ; 179
|
||||
DCD DefaultISR ; 180
|
||||
DCD DefaultISR ; 181
|
||||
DCD DefaultISR ; 182
|
||||
DCD DefaultISR ; 183
|
||||
DCD DefaultISR ; 184
|
||||
DCD DefaultISR ; 185
|
||||
DCD DefaultISR ; 186
|
||||
DCD DefaultISR ; 187
|
||||
DCD DefaultISR ; 188
|
||||
DCD DefaultISR ; 189
|
||||
DCD DefaultISR ; 190
|
||||
DCD DefaultISR ; 191
|
||||
DCD DefaultISR ; 192
|
||||
DCD DefaultISR ; 193
|
||||
DCD DefaultISR ; 194
|
||||
DCD DefaultISR ; 195
|
||||
DCD DefaultISR ; 196
|
||||
DCD DefaultISR ; 197
|
||||
DCD DefaultISR ; 198
|
||||
DCD DefaultISR ; 199
|
||||
DCD DefaultISR ; 200
|
||||
DCD DefaultISR ; 201
|
||||
DCD DefaultISR ; 202
|
||||
DCD DefaultISR ; 203
|
||||
DCD DefaultISR ; 204
|
||||
DCD DefaultISR ; 205
|
||||
DCD DefaultISR ; 206
|
||||
DCD DefaultISR ; 207
|
||||
DCD DefaultISR ; 208
|
||||
DCD DefaultISR ; 209
|
||||
DCD DefaultISR ; 210
|
||||
DCD DefaultISR ; 211
|
||||
DCD DefaultISR ; 212
|
||||
DCD DefaultISR ; 213
|
||||
DCD DefaultISR ; 214
|
||||
DCD DefaultISR ; 215
|
||||
DCD DefaultISR ; 216
|
||||
DCD DefaultISR ; 217
|
||||
DCD DefaultISR ; 218
|
||||
DCD DefaultISR ; 219
|
||||
DCD DefaultISR ; 220
|
||||
DCD DefaultISR ; 221
|
||||
DCD DefaultISR ; 222
|
||||
DCD DefaultISR ; 223
|
||||
DCD DefaultISR ; 224
|
||||
DCD DefaultISR ; 225
|
||||
DCD DefaultISR ; 226
|
||||
DCD DefaultISR ; 227
|
||||
DCD DefaultISR ; 228
|
||||
DCD DefaultISR ; 229
|
||||
DCD DefaultISR ; 230
|
||||
DCD DefaultISR ; 231
|
||||
DCD DefaultISR ; 232
|
||||
DCD DefaultISR ; 233
|
||||
DCD DefaultISR ; 234
|
||||
DCD DefaultISR ; 235
|
||||
DCD DefaultISR ; 236
|
||||
DCD DefaultISR ; 237
|
||||
DCD DefaultISR ; 238
|
||||
DCD DefaultISR ; 239
|
||||
DCD DefaultISR ; 240
|
||||
DCD DefaultISR ; 241
|
||||
DCD DefaultISR ; 242
|
||||
DCD DefaultISR ; 243
|
||||
DCD DefaultISR ; 244
|
||||
DCD DefaultISR ; 245
|
||||
DCD DefaultISR ; 246
|
||||
DCD DefaultISR ; 247
|
||||
DCD DefaultISR ; 248
|
||||
DCD DefaultISR ; 249
|
||||
DCD DefaultISR ; 250
|
||||
DCD DefaultISR ; 251
|
||||
DCD DefaultISR ; 252
|
||||
DCD DefaultISR ; 253
|
||||
DCD DefaultISR ; 254
|
||||
DCD DefaultISR ; 255
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
; <h> Flash Configuration
|
||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
; <h> Backdoor Comparison Key
|
||||
; <o0> Backdoor Key 0 <0x0-0xFF:2>
|
||||
; <o1> Backdoor Key 1 <0x0-0xFF:2>
|
||||
; <o2> Backdoor Key 2 <0x0-0xFF:2>
|
||||
; <o3> Backdoor Key 3 <0x0-0xFF:2>
|
||||
; <o4> Backdoor Key 4 <0x0-0xFF:2>
|
||||
; <o5> Backdoor Key 5 <0x0-0xFF:2>
|
||||
; <o6> Backdoor Key 6 <0x0-0xFF:2>
|
||||
; <o7> Backdoor Key 7 <0x0-0xFF:2>
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
; </h>
|
||||
; <h> Program flash protection bytes (FPROT)
|
||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
||||
; <h> FPROT0
|
||||
; <i> Program flash protection bytes
|
||||
; <i> 1/32 - 8/32 region
|
||||
; <o.0> FPROT0.0
|
||||
; <o.1> FPROT0.1
|
||||
; <o.2> FPROT0.2
|
||||
; <o.3> FPROT0.3
|
||||
; <o.4> FPROT0.4
|
||||
; <o.5> FPROT0.5
|
||||
; <o.6> FPROT0.6
|
||||
; <o.7> FPROT0.7
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT1
|
||||
; <i> Program Flash Region Protect Register 1
|
||||
; <i> 9/32 - 16/32 region
|
||||
; <o.0> FPROT1.0
|
||||
; <o.1> FPROT1.1
|
||||
; <o.2> FPROT1.2
|
||||
; <o.3> FPROT1.3
|
||||
; <o.4> FPROT1.4
|
||||
; <o.5> FPROT1.5
|
||||
; <o.6> FPROT1.6
|
||||
; <o.7> FPROT1.7
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT2
|
||||
; <i> Program Flash Region Protect Register 2
|
||||
; <i> 17/32 - 24/32 region
|
||||
; <o.0> FPROT2.0
|
||||
; <o.1> FPROT2.1
|
||||
; <o.2> FPROT2.2
|
||||
; <o.3> FPROT2.3
|
||||
; <o.4> FPROT2.4
|
||||
; <o.5> FPROT2.5
|
||||
; <o.6> FPROT2.6
|
||||
; <o.7> FPROT2.7
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT3
|
||||
; <i> Program Flash Region Protect Register 3
|
||||
; <i> 25/32 - 32/32 region
|
||||
; <o.0> FPROT3.0
|
||||
; <o.1> FPROT3.1
|
||||
; <o.2> FPROT3.2
|
||||
; <o.3> FPROT3.3
|
||||
; <o.4> FPROT3.4
|
||||
; <o.5> FPROT3.5
|
||||
; <o.6> FPROT3.6
|
||||
; <o.7> FPROT3.7
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Data flash protection byte (FDPROT)
|
||||
; <i> Each bit protects a 1/8 region of the data flash memory.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FDPROT.0
|
||||
; <o.1> FDPROT.1
|
||||
; <o.2> FDPROT.2
|
||||
; <o.3> FDPROT.3
|
||||
; <o.4> FDPROT.4
|
||||
; <o.5> FDPROT.5
|
||||
; <o.6> FDPROT.6
|
||||
; <o.7> FDPROT.7
|
||||
nFDPROT EQU 0x00
|
||||
FDPROT EQU nFDPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> EEPROM protection byte (FEPROT)
|
||||
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FEPROT.0
|
||||
; <o.1> FEPROT.1
|
||||
; <o.2> FEPROT.2
|
||||
; <o.3> FEPROT.3
|
||||
; <o.4> FEPROT.4
|
||||
; <o.5> FEPROT.5
|
||||
; <o.6> FEPROT.6
|
||||
; <o.7> FEPROT.7
|
||||
nFEPROT EQU 0x00
|
||||
FEPROT EQU nFEPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> Flash nonvolatile option byte (FOPT)
|
||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||
; <o.0> LPBOOT
|
||||
; <0=> Low-power boot
|
||||
; <1=> normal boot
|
||||
; <o.1> EZPORT_DIS
|
||||
; <0=> EzPort operation is enabled
|
||||
; <1=> EzPort operation is disabled
|
||||
FOPT EQU 0xFF
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.2..3> FSLACC
|
||||
; <2=> Freescale factory access denied
|
||||
; <3=> Freescale factory access granted
|
||||
; <i> Freescale Failure Analysis Access Code
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.4..5> MEEN
|
||||
; <2=> Mass erase is disabled
|
||||
; <3=> Mass erase is enabled
|
||||
; <i> Mass Erase Enable Bits
|
||||
; <i> Enables and disables mass erase capability of the FTFL module
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor key Security Enable
|
||||
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
; </h>
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
IF :LNOT::DEF:BOOTLOADER
|
||||
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||
ENDIF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT DMA0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_IRQHandler [WEAK]
|
||||
EXPORT DMA3_IRQHandler [WEAK]
|
||||
EXPORT DMA4_IRQHandler [WEAK]
|
||||
EXPORT DMA5_IRQHandler [WEAK]
|
||||
EXPORT DMA6_IRQHandler [WEAK]
|
||||
EXPORT DMA7_IRQHandler [WEAK]
|
||||
EXPORT DMA8_IRQHandler [WEAK]
|
||||
EXPORT DMA9_IRQHandler [WEAK]
|
||||
EXPORT DMA10_IRQHandler [WEAK]
|
||||
EXPORT DMA11_IRQHandler [WEAK]
|
||||
EXPORT DMA12_IRQHandler [WEAK]
|
||||
EXPORT DMA13_IRQHandler [WEAK]
|
||||
EXPORT DMA14_IRQHandler [WEAK]
|
||||
EXPORT DMA15_IRQHandler [WEAK]
|
||||
EXPORT DMA_Error_IRQHandler [WEAK]
|
||||
EXPORT MCM_IRQHandler [WEAK]
|
||||
EXPORT FTFL_IRQHandler [WEAK]
|
||||
EXPORT Read_Collision_IRQHandler [WEAK]
|
||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||
EXPORT LLW_IRQHandler [WEAK]
|
||||
EXPORT Watchdog_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Error_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
|
||||
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
||||
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
||||
EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Bus_Off_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Error_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Tx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Rx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Wake_Up_IRQHandler [WEAK]
|
||||
EXPORT Reserved59_IRQHandler [WEAK]
|
||||
EXPORT UART0_LON_IRQHandler [WEAK]
|
||||
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART0_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART1_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART2_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART3_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART3_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART4_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART4_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART5_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART5_ERR_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT CMP0_IRQHandler [WEAK]
|
||||
EXPORT CMP1_IRQHandler [WEAK]
|
||||
EXPORT CMP2_IRQHandler [WEAK]
|
||||
EXPORT FTM0_IRQHandler [WEAK]
|
||||
EXPORT FTM1_IRQHandler [WEAK]
|
||||
EXPORT FTM2_IRQHandler [WEAK]
|
||||
EXPORT CMT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||
EXPORT PIT0_IRQHandler [WEAK]
|
||||
EXPORT PIT1_IRQHandler [WEAK]
|
||||
EXPORT PIT2_IRQHandler [WEAK]
|
||||
EXPORT PIT3_IRQHandler [WEAK]
|
||||
EXPORT PDB0_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USBDCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_1588_Timer_IRQHandler [WEAK]
|
||||
EXPORT ENET_Transmit_IRQHandler [WEAK]
|
||||
EXPORT ENET_Receive_IRQHandler [WEAK]
|
||||
EXPORT ENET_Error_IRQHandler [WEAK]
|
||||
EXPORT Reserved95_IRQHandler [WEAK]
|
||||
EXPORT SDHC_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT TSI0_IRQHandler [WEAK]
|
||||
EXPORT MCG_IRQHandler [WEAK]
|
||||
EXPORT LPTimer_IRQHandler [WEAK]
|
||||
EXPORT Reserved102_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTB_IRQHandler [WEAK]
|
||||
EXPORT PORTC_IRQHandler [WEAK]
|
||||
EXPORT PORTD_IRQHandler [WEAK]
|
||||
EXPORT PORTE_IRQHandler [WEAK]
|
||||
EXPORT Reserved108_IRQHandler [WEAK]
|
||||
EXPORT Reserved109_IRQHandler [WEAK]
|
||||
EXPORT SWI_IRQHandler [WEAK]
|
||||
EXPORT Reserved111_IRQHandler [WEAK]
|
||||
EXPORT Reserved112_IRQHandler [WEAK]
|
||||
EXPORT Reserved113_IRQHandler [WEAK]
|
||||
EXPORT Reserved114_IRQHandler [WEAK]
|
||||
EXPORT Reserved115_IRQHandler [WEAK]
|
||||
EXPORT Reserved116_IRQHandler [WEAK]
|
||||
EXPORT Reserved117_IRQHandler [WEAK]
|
||||
EXPORT Reserved118_IRQHandler [WEAK]
|
||||
EXPORT Reserved119_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
DMA4_IRQHandler
|
||||
DMA5_IRQHandler
|
||||
DMA6_IRQHandler
|
||||
DMA7_IRQHandler
|
||||
DMA8_IRQHandler
|
||||
DMA9_IRQHandler
|
||||
DMA10_IRQHandler
|
||||
DMA11_IRQHandler
|
||||
DMA12_IRQHandler
|
||||
DMA13_IRQHandler
|
||||
DMA14_IRQHandler
|
||||
DMA15_IRQHandler
|
||||
DMA_Error_IRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFL_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
Watchdog_IRQHandler
|
||||
RNG_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
CAN0_ORed_Message_buffer_IRQHandler
|
||||
CAN0_Bus_Off_IRQHandler
|
||||
CAN0_Error_IRQHandler
|
||||
CAN0_Tx_Warning_IRQHandler
|
||||
CAN0_Rx_Warning_IRQHandler
|
||||
CAN0_Wake_Up_IRQHandler
|
||||
I2S0_Tx_IRQHandler
|
||||
I2S0_Rx_IRQHandler
|
||||
CAN1_ORed_Message_buffer_IRQHandler
|
||||
CAN1_Bus_Off_IRQHandler
|
||||
CAN1_Error_IRQHandler
|
||||
CAN1_Tx_Warning_IRQHandler
|
||||
CAN1_Rx_Warning_IRQHandler
|
||||
CAN1_Wake_Up_IRQHandler
|
||||
Reserved59_IRQHandler
|
||||
UART0_LON_IRQHandler
|
||||
UART0_RX_TX_IRQHandler
|
||||
UART0_ERR_IRQHandler
|
||||
UART1_RX_TX_IRQHandler
|
||||
UART1_ERR_IRQHandler
|
||||
UART2_RX_TX_IRQHandler
|
||||
UART2_ERR_IRQHandler
|
||||
UART3_RX_TX_IRQHandler
|
||||
UART3_ERR_IRQHandler
|
||||
UART4_RX_TX_IRQHandler
|
||||
UART4_ERR_IRQHandler
|
||||
UART5_RX_TX_IRQHandler
|
||||
UART5_ERR_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
CMP2_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT0_IRQHandler
|
||||
PIT1_IRQHandler
|
||||
PIT2_IRQHandler
|
||||
PIT3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
ENET_1588_Timer_IRQHandler
|
||||
ENET_Transmit_IRQHandler
|
||||
ENET_Receive_IRQHandler
|
||||
ENET_Error_IRQHandler
|
||||
Reserved95_IRQHandler
|
||||
SDHC_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
Reserved102_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
Reserved108_IRQHandler
|
||||
Reserved109_IRQHandler
|
||||
SWI_IRQHandler
|
||||
Reserved111_IRQHandler
|
||||
Reserved112_IRQHandler
|
||||
Reserved113_IRQHandler
|
||||
Reserved114_IRQHandler
|
||||
Reserved115_IRQHandler
|
||||
Reserved116_IRQHandler
|
||||
Reserved117_IRQHandler
|
||||
Reserved118_IRQHandler
|
||||
Reserved119_IRQHandler
|
||||
DefaultISR
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
735
board/NXP_Kinetis_K64/KEIL/hello_world/startup_MK64F12.s
Normal file
735
board/NXP_Kinetis_K64/KEIL/hello_world/startup_MK64F12.s
Normal file
@@ -0,0 +1,735 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_MK64F12.s
|
||||
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
|
||||
; * MK64F12
|
||||
; * @version: 1.0
|
||||
; * @date: 2013-8-12
|
||||
; *
|
||||
; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
;*
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
|
||||
DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
|
||||
DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
|
||||
DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
|
||||
DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
|
||||
DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
|
||||
DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
|
||||
DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
|
||||
DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
|
||||
DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
|
||||
DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
|
||||
DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
|
||||
DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
|
||||
DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
|
||||
DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
|
||||
DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
|
||||
DCD DMA_Error_IRQHandler ; DMA Error Interrupt
|
||||
DCD MCM_IRQHandler ; Normal Interrupt
|
||||
DCD FTFE_IRQHandler ; FTFE Command complete interrupt
|
||||
DCD Read_Collision_IRQHandler ; Read Collision Interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD Watchdog_IRQHandler ; WDOG Interrupt
|
||||
DCD RNG_IRQHandler ; RNG Interrupt
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 interrupt
|
||||
DCD SPI0_IRQHandler ; SPI0 Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
|
||||
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
|
||||
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
|
||||
DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
|
||||
DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
|
||||
DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
|
||||
DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
|
||||
DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
|
||||
DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
|
||||
DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
|
||||
DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD CMP1_IRQHandler ; CMP1 interrupt
|
||||
DCD FTM0_IRQHandler ; FTM0 fault, overflow and chls interrupt
|
||||
DCD FTM1_IRQHandler ; FTM1 fault, overflow and chls interrupt
|
||||
DCD FTM2_IRQHandler ; FTM2 fault, overflow and chls interrupt
|
||||
DCD CMT_IRQHandler ; CMT interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT0_IRQHandler ; PIT timer chl 0 interrupt
|
||||
DCD PIT1_IRQHandler ; PIT timer chl 1 interrupt
|
||||
DCD PIT2_IRQHandler ; PIT timer chl 2 interrupt
|
||||
DCD PIT3_IRQHandler ; PIT timer chl 3 interrupt
|
||||
DCD PDB0_IRQHandler ; PDB0 Interrupt
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD USBDCD_IRQHandler ; USBDCD Interrupt
|
||||
DCD Reserved71_IRQHandler ; Reserved interrupt 71
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD MCG_IRQHandler ; MCG Interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTB_IRQHandler ; Port B interrupt
|
||||
DCD PORTC_IRQHandler ; Port C interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
DCD PORTE_IRQHandler ; Port E interrupt
|
||||
DCD SWI_IRQHandler ; Software interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
|
||||
DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
|
||||
DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
|
||||
DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
|
||||
DCD CMP2_IRQHandler ; CMP2 interrupt
|
||||
DCD FTM3_IRQHandler ; FTM3 fault, overflow and chls interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 interrupt
|
||||
DCD I2C2_IRQHandler ; I2C2 interrupt
|
||||
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
|
||||
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
|
||||
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
|
||||
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
|
||||
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
|
||||
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
|
||||
DCD SDHC_IRQHandler ; SDHC interrupt
|
||||
DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
|
||||
DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
|
||||
DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
|
||||
DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
|
||||
DCD DefaultISR ; 102
|
||||
DCD DefaultISR ; 103
|
||||
DCD DefaultISR ; 104
|
||||
DCD DefaultISR ; 105
|
||||
DCD DefaultISR ; 106
|
||||
DCD DefaultISR ; 107
|
||||
DCD DefaultISR ; 108
|
||||
DCD DefaultISR ; 109
|
||||
DCD DefaultISR ; 110
|
||||
DCD DefaultISR ; 111
|
||||
DCD DefaultISR ; 112
|
||||
DCD DefaultISR ; 113
|
||||
DCD DefaultISR ; 114
|
||||
DCD DefaultISR ; 115
|
||||
DCD DefaultISR ; 116
|
||||
DCD DefaultISR ; 117
|
||||
DCD DefaultISR ; 118
|
||||
DCD DefaultISR ; 119
|
||||
DCD DefaultISR ; 120
|
||||
DCD DefaultISR ; 121
|
||||
DCD DefaultISR ; 122
|
||||
DCD DefaultISR ; 123
|
||||
DCD DefaultISR ; 124
|
||||
DCD DefaultISR ; 125
|
||||
DCD DefaultISR ; 126
|
||||
DCD DefaultISR ; 127
|
||||
DCD DefaultISR ; 128
|
||||
DCD DefaultISR ; 129
|
||||
DCD DefaultISR ; 130
|
||||
DCD DefaultISR ; 131
|
||||
DCD DefaultISR ; 132
|
||||
DCD DefaultISR ; 133
|
||||
DCD DefaultISR ; 134
|
||||
DCD DefaultISR ; 135
|
||||
DCD DefaultISR ; 136
|
||||
DCD DefaultISR ; 137
|
||||
DCD DefaultISR ; 138
|
||||
DCD DefaultISR ; 139
|
||||
DCD DefaultISR ; 140
|
||||
DCD DefaultISR ; 141
|
||||
DCD DefaultISR ; 142
|
||||
DCD DefaultISR ; 143
|
||||
DCD DefaultISR ; 144
|
||||
DCD DefaultISR ; 145
|
||||
DCD DefaultISR ; 146
|
||||
DCD DefaultISR ; 147
|
||||
DCD DefaultISR ; 148
|
||||
DCD DefaultISR ; 149
|
||||
DCD DefaultISR ; 150
|
||||
DCD DefaultISR ; 151
|
||||
DCD DefaultISR ; 152
|
||||
DCD DefaultISR ; 153
|
||||
DCD DefaultISR ; 154
|
||||
DCD DefaultISR ; 155
|
||||
DCD DefaultISR ; 156
|
||||
DCD DefaultISR ; 157
|
||||
DCD DefaultISR ; 158
|
||||
DCD DefaultISR ; 159
|
||||
DCD DefaultISR ; 160
|
||||
DCD DefaultISR ; 161
|
||||
DCD DefaultISR ; 162
|
||||
DCD DefaultISR ; 163
|
||||
DCD DefaultISR ; 164
|
||||
DCD DefaultISR ; 165
|
||||
DCD DefaultISR ; 166
|
||||
DCD DefaultISR ; 167
|
||||
DCD DefaultISR ; 168
|
||||
DCD DefaultISR ; 169
|
||||
DCD DefaultISR ; 170
|
||||
DCD DefaultISR ; 171
|
||||
DCD DefaultISR ; 172
|
||||
DCD DefaultISR ; 173
|
||||
DCD DefaultISR ; 174
|
||||
DCD DefaultISR ; 175
|
||||
DCD DefaultISR ; 176
|
||||
DCD DefaultISR ; 177
|
||||
DCD DefaultISR ; 178
|
||||
DCD DefaultISR ; 179
|
||||
DCD DefaultISR ; 180
|
||||
DCD DefaultISR ; 181
|
||||
DCD DefaultISR ; 182
|
||||
DCD DefaultISR ; 183
|
||||
DCD DefaultISR ; 184
|
||||
DCD DefaultISR ; 185
|
||||
DCD DefaultISR ; 186
|
||||
DCD DefaultISR ; 187
|
||||
DCD DefaultISR ; 188
|
||||
DCD DefaultISR ; 189
|
||||
DCD DefaultISR ; 190
|
||||
DCD DefaultISR ; 191
|
||||
DCD DefaultISR ; 192
|
||||
DCD DefaultISR ; 193
|
||||
DCD DefaultISR ; 194
|
||||
DCD DefaultISR ; 195
|
||||
DCD DefaultISR ; 196
|
||||
DCD DefaultISR ; 197
|
||||
DCD DefaultISR ; 198
|
||||
DCD DefaultISR ; 199
|
||||
DCD DefaultISR ; 200
|
||||
DCD DefaultISR ; 201
|
||||
DCD DefaultISR ; 202
|
||||
DCD DefaultISR ; 203
|
||||
DCD DefaultISR ; 204
|
||||
DCD DefaultISR ; 205
|
||||
DCD DefaultISR ; 206
|
||||
DCD DefaultISR ; 207
|
||||
DCD DefaultISR ; 208
|
||||
DCD DefaultISR ; 209
|
||||
DCD DefaultISR ; 210
|
||||
DCD DefaultISR ; 211
|
||||
DCD DefaultISR ; 212
|
||||
DCD DefaultISR ; 213
|
||||
DCD DefaultISR ; 214
|
||||
DCD DefaultISR ; 215
|
||||
DCD DefaultISR ; 216
|
||||
DCD DefaultISR ; 217
|
||||
DCD DefaultISR ; 218
|
||||
DCD DefaultISR ; 219
|
||||
DCD DefaultISR ; 220
|
||||
DCD DefaultISR ; 221
|
||||
DCD DefaultISR ; 222
|
||||
DCD DefaultISR ; 223
|
||||
DCD DefaultISR ; 224
|
||||
DCD DefaultISR ; 225
|
||||
DCD DefaultISR ; 226
|
||||
DCD DefaultISR ; 227
|
||||
DCD DefaultISR ; 228
|
||||
DCD DefaultISR ; 229
|
||||
DCD DefaultISR ; 230
|
||||
DCD DefaultISR ; 231
|
||||
DCD DefaultISR ; 232
|
||||
DCD DefaultISR ; 233
|
||||
DCD DefaultISR ; 234
|
||||
DCD DefaultISR ; 235
|
||||
DCD DefaultISR ; 236
|
||||
DCD DefaultISR ; 237
|
||||
DCD DefaultISR ; 238
|
||||
DCD DefaultISR ; 239
|
||||
DCD DefaultISR ; 240
|
||||
DCD DefaultISR ; 241
|
||||
DCD DefaultISR ; 242
|
||||
DCD DefaultISR ; 243
|
||||
DCD DefaultISR ; 244
|
||||
DCD DefaultISR ; 245
|
||||
DCD DefaultISR ; 246
|
||||
DCD DefaultISR ; 247
|
||||
DCD DefaultISR ; 248
|
||||
DCD DefaultISR ; 249
|
||||
DCD DefaultISR ; 250
|
||||
DCD DefaultISR ; 251
|
||||
DCD DefaultISR ; 252
|
||||
DCD DefaultISR ; 253
|
||||
DCD DefaultISR ; 254
|
||||
DCD DefaultISR ; 255
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
; <h> Flash Configuration
|
||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
; <h> Backdoor Comparison Key
|
||||
; <o0> Backdoor Key 0 <0x0-0xFF:2>
|
||||
; <o1> Backdoor Key 1 <0x0-0xFF:2>
|
||||
; <o2> Backdoor Key 2 <0x0-0xFF:2>
|
||||
; <o3> Backdoor Key 3 <0x0-0xFF:2>
|
||||
; <o4> Backdoor Key 4 <0x0-0xFF:2>
|
||||
; <o5> Backdoor Key 5 <0x0-0xFF:2>
|
||||
; <o6> Backdoor Key 6 <0x0-0xFF:2>
|
||||
; <o7> Backdoor Key 7 <0x0-0xFF:2>
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
; </h>
|
||||
; <h> Program flash protection bytes (FPROT)
|
||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
||||
; <h> FPROT0
|
||||
; <i> Program flash protection bytes
|
||||
; <i> 1/32 - 8/32 region
|
||||
; <o.0> FPROT0.0
|
||||
; <o.1> FPROT0.1
|
||||
; <o.2> FPROT0.2
|
||||
; <o.3> FPROT0.3
|
||||
; <o.4> FPROT0.4
|
||||
; <o.5> FPROT0.5
|
||||
; <o.6> FPROT0.6
|
||||
; <o.7> FPROT0.7
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT1
|
||||
; <i> Program Flash Region Protect Register 1
|
||||
; <i> 9/32 - 16/32 region
|
||||
; <o.0> FPROT1.0
|
||||
; <o.1> FPROT1.1
|
||||
; <o.2> FPROT1.2
|
||||
; <o.3> FPROT1.3
|
||||
; <o.4> FPROT1.4
|
||||
; <o.5> FPROT1.5
|
||||
; <o.6> FPROT1.6
|
||||
; <o.7> FPROT1.7
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT2
|
||||
; <i> Program Flash Region Protect Register 2
|
||||
; <i> 17/32 - 24/32 region
|
||||
; <o.0> FPROT2.0
|
||||
; <o.1> FPROT2.1
|
||||
; <o.2> FPROT2.2
|
||||
; <o.3> FPROT2.3
|
||||
; <o.4> FPROT2.4
|
||||
; <o.5> FPROT2.5
|
||||
; <o.6> FPROT2.6
|
||||
; <o.7> FPROT2.7
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT3
|
||||
; <i> Program Flash Region Protect Register 3
|
||||
; <i> 25/32 - 32/32 region
|
||||
; <o.0> FPROT3.0
|
||||
; <o.1> FPROT3.1
|
||||
; <o.2> FPROT3.2
|
||||
; <o.3> FPROT3.3
|
||||
; <o.4> FPROT3.4
|
||||
; <o.5> FPROT3.5
|
||||
; <o.6> FPROT3.6
|
||||
; <o.7> FPROT3.7
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Data flash protection byte (FDPROT)
|
||||
; <i> Each bit protects a 1/8 region of the data flash memory.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FDPROT.0
|
||||
; <o.1> FDPROT.1
|
||||
; <o.2> FDPROT.2
|
||||
; <o.3> FDPROT.3
|
||||
; <o.4> FDPROT.4
|
||||
; <o.5> FDPROT.5
|
||||
; <o.6> FDPROT.6
|
||||
; <o.7> FDPROT.7
|
||||
nFDPROT EQU 0x00
|
||||
FDPROT EQU nFDPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> EEPROM protection byte (FEPROT)
|
||||
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FEPROT.0
|
||||
; <o.1> FEPROT.1
|
||||
; <o.2> FEPROT.2
|
||||
; <o.3> FEPROT.3
|
||||
; <o.4> FEPROT.4
|
||||
; <o.5> FEPROT.5
|
||||
; <o.6> FEPROT.6
|
||||
; <o.7> FEPROT.7
|
||||
nFEPROT EQU 0x00
|
||||
FEPROT EQU nFEPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> Flash nonvolatile option byte (FOPT)
|
||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||
; <o.0> LPBOOT
|
||||
; <0=> Low-power boot
|
||||
; <1=> normal boot
|
||||
; <o.1> EZPORT_DIS
|
||||
; <0=> EzPort operation is enabled
|
||||
; <1=> EzPort operation is disabled
|
||||
FOPT EQU 0xFF
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.2..3> FSLACC
|
||||
; <2=> Freescale factory access denied
|
||||
; <3=> Freescale factory access granted
|
||||
; <i> Freescale Failure Analysis Access Code
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.4..5> MEEN
|
||||
; <2=> Mass erase is disabled
|
||||
; <3=> Mass erase is enabled
|
||||
; <i> Mass Erase Enable Bits
|
||||
; <i> Enables and disables mass erase capability of the FTFL module
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor key Security Enable
|
||||
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
; </h>
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
IF :LNOT::DEF:BOOTLOADER
|
||||
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||
ENDIF
|
||||
ENDIF
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT DMA0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_IRQHandler [WEAK]
|
||||
EXPORT DMA3_IRQHandler [WEAK]
|
||||
EXPORT DMA4_IRQHandler [WEAK]
|
||||
EXPORT DMA5_IRQHandler [WEAK]
|
||||
EXPORT DMA6_IRQHandler [WEAK]
|
||||
EXPORT DMA7_IRQHandler [WEAK]
|
||||
EXPORT DMA8_IRQHandler [WEAK]
|
||||
EXPORT DMA9_IRQHandler [WEAK]
|
||||
EXPORT DMA10_IRQHandler [WEAK]
|
||||
EXPORT DMA11_IRQHandler [WEAK]
|
||||
EXPORT DMA12_IRQHandler [WEAK]
|
||||
EXPORT DMA13_IRQHandler [WEAK]
|
||||
EXPORT DMA14_IRQHandler [WEAK]
|
||||
EXPORT DMA15_IRQHandler [WEAK]
|
||||
EXPORT DMA_Error_IRQHandler [WEAK]
|
||||
EXPORT MCM_IRQHandler [WEAK]
|
||||
EXPORT FTFE_IRQHandler [WEAK]
|
||||
EXPORT Read_Collision_IRQHandler [WEAK]
|
||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||
EXPORT LLW_IRQHandler [WEAK]
|
||||
EXPORT Watchdog_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
||||
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
||||
EXPORT UART0_LON_IRQHandler [WEAK]
|
||||
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART0_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART1_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART2_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART3_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART3_ERR_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT CMP0_IRQHandler [WEAK]
|
||||
EXPORT CMP1_IRQHandler [WEAK]
|
||||
EXPORT FTM0_IRQHandler [WEAK]
|
||||
EXPORT FTM1_IRQHandler [WEAK]
|
||||
EXPORT FTM2_IRQHandler [WEAK]
|
||||
EXPORT CMT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||
EXPORT PIT0_IRQHandler [WEAK]
|
||||
EXPORT PIT1_IRQHandler [WEAK]
|
||||
EXPORT PIT2_IRQHandler [WEAK]
|
||||
EXPORT PIT3_IRQHandler [WEAK]
|
||||
EXPORT PDB0_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USBDCD_IRQHandler [WEAK]
|
||||
EXPORT Reserved71_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT MCG_IRQHandler [WEAK]
|
||||
EXPORT LPTimer_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTB_IRQHandler [WEAK]
|
||||
EXPORT PORTC_IRQHandler [WEAK]
|
||||
EXPORT PORTD_IRQHandler [WEAK]
|
||||
EXPORT PORTE_IRQHandler [WEAK]
|
||||
EXPORT SWI_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART4_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART4_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART5_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART5_ERR_IRQHandler [WEAK]
|
||||
EXPORT CMP2_IRQHandler [WEAK]
|
||||
EXPORT FTM3_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT I2C2_IRQHandler [WEAK]
|
||||
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Error_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
|
||||
EXPORT SDHC_IRQHandler [WEAK]
|
||||
EXPORT ENET_1588_Timer_IRQHandler [WEAK]
|
||||
EXPORT ENET_Transmit_IRQHandler [WEAK]
|
||||
EXPORT ENET_Receive_IRQHandler [WEAK]
|
||||
EXPORT ENET_Error_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
DMA4_IRQHandler
|
||||
DMA5_IRQHandler
|
||||
DMA6_IRQHandler
|
||||
DMA7_IRQHandler
|
||||
DMA8_IRQHandler
|
||||
DMA9_IRQHandler
|
||||
DMA10_IRQHandler
|
||||
DMA11_IRQHandler
|
||||
DMA12_IRQHandler
|
||||
DMA13_IRQHandler
|
||||
DMA14_IRQHandler
|
||||
DMA15_IRQHandler
|
||||
DMA_Error_IRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFE_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
Watchdog_IRQHandler
|
||||
RNG_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
I2S0_Tx_IRQHandler
|
||||
I2S0_Rx_IRQHandler
|
||||
UART0_LON_IRQHandler
|
||||
UART0_RX_TX_IRQHandler
|
||||
UART0_ERR_IRQHandler
|
||||
UART1_RX_TX_IRQHandler
|
||||
UART1_ERR_IRQHandler
|
||||
UART2_RX_TX_IRQHandler
|
||||
UART2_ERR_IRQHandler
|
||||
UART3_RX_TX_IRQHandler
|
||||
UART3_ERR_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT0_IRQHandler
|
||||
PIT1_IRQHandler
|
||||
PIT2_IRQHandler
|
||||
PIT3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
Reserved71_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
SWI_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART4_RX_TX_IRQHandler
|
||||
UART4_ERR_IRQHandler
|
||||
UART5_RX_TX_IRQHandler
|
||||
UART5_ERR_IRQHandler
|
||||
CMP2_IRQHandler
|
||||
FTM3_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
CAN0_ORed_Message_buffer_IRQHandler
|
||||
CAN0_Bus_Off_IRQHandler
|
||||
CAN0_Error_IRQHandler
|
||||
CAN0_Tx_Warning_IRQHandler
|
||||
CAN0_Rx_Warning_IRQHandler
|
||||
CAN0_Wake_Up_IRQHandler
|
||||
SDHC_IRQHandler
|
||||
ENET_1588_Timer_IRQHandler
|
||||
ENET_Transmit_IRQHandler
|
||||
ENET_Receive_IRQHandler
|
||||
ENET_Error_IRQHandler
|
||||
DefaultISR
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
51
board/NXP_Kinetis_K64/TOS_CONFIG/tos_config.h
Normal file
51
board/NXP_Kinetis_K64/TOS_CONFIG/tos_config.h
Normal file
@@ -0,0 +1,51 @@
|
||||
#ifndef _TOS_CONFIG_H_
|
||||
#define _TOS_CONFIG_H_
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define TOS_CFG_TASK_PRIO_MAX 10u
|
||||
|
||||
#define TOS_CFG_ROUND_ROBIN_EN 1u
|
||||
|
||||
#define TOS_CFG_OBJECT_VERIFY_EN 0u
|
||||
|
||||
#define TOS_CFG_EVENT_EN 1u
|
||||
|
||||
#define TOS_CFG_MMBLK_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_POOL_SIZE 0x100
|
||||
|
||||
#define TOS_CFG_MUTEX_EN 1u
|
||||
|
||||
#define TOS_CFG_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_TIMER_EN 1u
|
||||
|
||||
#define TOS_CFG_PWR_MGR_EN 0u
|
||||
|
||||
#define TOS_CFG_TICKLESS_EN 0u
|
||||
|
||||
#define TOS_CFG_SEM_EN 1u
|
||||
|
||||
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
|
||||
|
||||
#if (TOS_CFG_QUEUE_EN > 0u)
|
||||
#define TOS_CFG_MSG_EN 1u
|
||||
#else
|
||||
#define TOS_CFG_MSG_EN 0u
|
||||
#endif
|
||||
|
||||
#define TOS_CFG_MSG_POOL_SIZE 3u
|
||||
|
||||
#define TOS_CFG_IDLE_TASK_STK_SIZE 512u
|
||||
|
||||
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
|
||||
|
||||
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
|
||||
|
||||
#define TOS_CFG_TIMER_AS_PROC 1u
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user