risc-v support all irq handler

arch/risc-v/bumblebee/gcc/riscv_port.h

@@ -36,10 +36,4 @@
 // EXCCODE          11:0        exception code
 #define MCAUSE_EXP_CODE_MASK    0x00000FFF
 
-#ifndef __ASSEMBLER__
-void port_cpu_init();
-
-void port_systick_priority_set(uint32_t priority);
-#endif
-
 #endif // _RISCV_PORT_H_

arch/risc-v/bumblebee/gcc/riscv_port_c.c

@@ -108,8 +108,15 @@ static void eclic_set_irq_priority(uint32_t source, uint8_t priority) {
     eclic_set_intctrl(CLIC_INT_TMR, intctrl_val);
 }
 
+void rv32_exception_entry();
 __PORT__ void port_cpu_init() {
 
+    __ASM__ __VOLATILE__("csrw mtvec, %0"::"r"(rv32_exception_entry));
+
+    // MTVT2: 0x7EC
+    // use mtvec as entry of irq and other trap
+    __ASM__ __VOLATILE__("csrc 0x7EC, 0x1");
+
     eclic_enable_interrupt(CLIC_INT_TMR);
 
     eclic_set_irq_level(CLIC_INT_TMR, 0);
@@ -119,3 +126,13 @@ __PORT__ void port_cpu_init() {
 __PORT__ void port_systick_priority_set(uint32_t priority) {
     eclic_set_irq_priority(CLIC_INT_TMR, priority);
 }
+
+
+__PORT__ void *port_get_irq_vector_table() {
+    void *base = 0;
+
+    // MTVT:  0x307
+    __ASM__ __VOLATILE__("csrr %0, 0x307":"=r"(base));
+
+    return base;
+}

arch/risc-v/bumblebee/gcc/riscv_port_s.S

@@ -15,15 +15,31 @@
  * within TencentOS.
  *---------------------------------------------------------------------------*/
 
+.global eclic_mtip_handler
 .global irq_entry
 .global trap_entry
 
-.extern rv32_exception_entry
+.extern SysTick_IRQHandler
+
+.align 2
+eclic_mtip_handler:
+	/* normal code */
+    // add sp, sp, -4
+    // sw ra, (sp)
+    // call SysTick_IRQHandler
+    // lw ra, (sp)
+    // add sp, sp, 4
+    // ret
+
+	/* the most efficient code */
+	j SysTick_IRQHandler
+	// the code will return to caller directly from SysTick_IRQHandler
 
 .align 2
 irq_entry:
-    j rv32_exception_entry
+    j irq_entry
 
 .align 2
 trap_entry:
-    j rv32_exception_entry
+    j trap_entry
+