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risc-v support all irq handler

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This commit is contained in:
acevest
2019-10-16 18:10:03 +08:00
parent 7983b07386
commit f41e287c2a
15 changed files with 126 additions and 37 deletions
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17
arch/risc-v/bumblebee/gcc/riscv_port_c.c
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@@ -108,8 +108,15 @@ static void eclic_set_irq_priority(uint32_t source, uint8_t priority) {
eclic_set_intctrl(CLIC_INT_TMR, intctrl_val);
}
void rv32_exception_entry();
__PORT__ void port_cpu_init() {
__ASM__ __VOLATILE__("csrw mtvec, %0"::"r"(rv32_exception_entry));
// MTVT2: 0x7EC
// use mtvec as entry of irq and other trap
__ASM__ __VOLATILE__("csrc 0x7EC, 0x1");
eclic_enable_interrupt(CLIC_INT_TMR);
eclic_set_irq_level(CLIC_INT_TMR, 0);
@@ -119,3 +126,13 @@ __PORT__ void port_cpu_init() {
__PORT__ void port_systick_priority_set(uint32_t priority) {
eclic_set_irq_priority(CLIC_INT_TMR, priority);
}
__PORT__ void *port_get_irq_vector_table() {
void *base = 0;
// MTVT: 0x307
__ASM__ __VOLATILE__("csrr %0, 0x307":"=r"(base));
return base;
}