diff --git a/arch/risc-v/bumblebee/gcc/riscv_port.h b/arch/risc-v/bumblebee/gcc/riscv_port.h
index 9484a704..fca00a56 100644
--- a/arch/risc-v/bumblebee/gcc/riscv_port.h
+++ b/arch/risc-v/bumblebee/gcc/riscv_port.h
@@ -24,8 +24,22 @@
#define CLINT_MTIMECMP 0x0008
#define CLINT_MTIME 0x0000
+// the bumblebee mstatus register is different
+// name bit detail
+// INTERRUPT 31 0: exception or nmi, 1 irq
+// MINHV 30 reading irq vector table
+// MPP 29:28 == mstatus.MPP
+// MPIE 27 == mstatus.MPIE
+// Reserved 26:24 0
+// MPIL 23:16 previous interrupt level
+// Reserved 15:12 0
+// EXCCODE 11:0 exception code
+#define SOC_MCAUSE_EXP_MASK 0x00000FFF
+
+#ifndef __ASSEMBLER__
void port_cpu_init();
void port_systick_priority_set(uint32_t priority);
+#endif
#endif // _RISCV_PORT_H_
diff --git a/arch/risc-v/bumblebee/gcc/riscv_port_s.S b/arch/risc-v/bumblebee/gcc/riscv_port_s.S
new file mode 100644
index 00000000..1683a0b6
--- /dev/null
+++ b/arch/risc-v/bumblebee/gcc/riscv_port_s.S
@@ -0,0 +1,12 @@
+.global irq_entry
+.global trap_entry
+
+.extern rv32_exception_entry
+
+.align 2
+irq_entry:
+ j rv32_exception_entry
+
+.align 6
+trap_entry:
+ j rv32_exception_entry
diff --git a/arch/risc-v/common/include/tos_cpu.h b/arch/risc-v/common/include/tos_cpu.h
index 75695178..0ee8abbb 100644
--- a/arch/risc-v/common/include/tos_cpu.h
+++ b/arch/risc-v/common/include/tos_cpu.h
@@ -1,9 +1,8 @@
#ifndef _TOS_CPU_H_
#define _TOS_CPU_H_
-
typedef struct cpu_context_st {
- cpu_data_t epc;
+ cpu_data_t mepc;
cpu_data_t mstatus;
union { cpu_data_t x1, ra; };
union { cpu_data_t x3, gp; };
@@ -37,6 +36,7 @@ typedef struct cpu_context_st {
union { cpu_data_t x31, t6; };
} cpu_context_t;
+
__API__ uint32_t tos_cpu_clz(uint32_t val);
__API__ void tos_cpu_int_disable(void);
@@ -115,4 +115,5 @@ __KERNEL__ void cpu_standby_mode_enter(void);
tos_cpu_cpsr_restore(cpu_cpsr); \
} while (0)
+
#endif /* _TOS_CPU_H_ */
diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c
index d841eef6..3ae8f0ef 100644
--- a/arch/risc-v/common/tos_cpu.c
+++ b/arch/risc-v/common/tos_cpu.c
@@ -32,7 +32,7 @@ __KERNEL__ void cpu_context_switch(void)
__KERNEL__ void cpu_irq_context_switch(void)
{
- port_irq_context_switch();
+ // DO NOTHING
}
__KERNEL__ void cpu_sched_start(void)
@@ -74,7 +74,7 @@ Inx Offset Register
03 012 x3 gp
02 008 x1 ra
01 004 mstatus
-00 000 epc
+00 000 mepc
*/
@@ -107,7 +107,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry,
regs->a0 = (cpu_data_t)arg; // a0: argument
regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address
regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt
- regs->epc = (cpu_data_t)entry;
+ regs->mepc = (cpu_data_t)entry;
return (k_stack_t*)sp;
@@ -129,7 +129,7 @@ void SysTick_IRQHandler() {
}
}
-void cpu_irq_entry(cpu_data_t irq, cpu_context_t *regs)
+void cpu_irq_entry(cpu_data_t irq)
{
if (irq != 7) {
return;
@@ -172,3 +172,5 @@ __API__ uint32_t tos_cpu_clz(uint32_t val)
return (nbr_lead_zeros);
}
+
+
diff --git a/arch/risc-v/rv32i/gcc/port.h b/arch/risc-v/rv32i/gcc/port.h
index a3da86ea..66772bd0 100644
--- a/arch/risc-v/rv32i/gcc/port.h
+++ b/arch/risc-v/rv32i/gcc/port.h
@@ -18,6 +18,8 @@
#ifndef _PORT_H_
#define _PORT_H_
+#ifndef __ASSEMBLER__
+
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
@@ -69,4 +71,9 @@ __PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
+#endif /* __ASSEMBLER__ */
+
+
+#define REGBYTES 4
+
#endif /* _PORT_H_ */
diff --git a/arch/risc-v/rv32i/gcc/port_c.c b/arch/risc-v/rv32i/gcc/port_c.c
index ef0de3f9..c53a1f80 100644
--- a/arch/risc-v/rv32i/gcc/port_c.c
+++ b/arch/risc-v/rv32i/gcc/port_c.c
@@ -31,11 +31,3 @@ __PORT__ void port_systick_config(uint32_t cycle_per_tick)
*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF & (mtimecmp >> 32);
*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF & (mtimecmp >> 0);
}
-
-
-
-int k_task_irq_switch_flag = 0;
-__PORT__ void port_irq_context_switch()
-{
- k_task_irq_switch_flag = 1;
-}
diff --git a/arch/risc-v/rv32i/gcc/port_s.S b/arch/risc-v/rv32i/gcc/port_s.S
index dc4b9b27..278cc199 100644
--- a/arch/risc-v/rv32i/gcc/port_s.S
+++ b/arch/risc-v/rv32i/gcc/port_s.S
@@ -1,3 +1,5 @@
+#include "riscv_port.h"
+
.global port_int_disable
.global port_int_enable
@@ -10,10 +12,10 @@
.global port_sched_start
.global port_context_switch
+.global rv32_exception_entry
.extern k_curr_task
.extern k_next_task
-.extern k_task_irq_switch_flag
.equ MSTATUS_MIE, 0x00000008
.equ MSTATUS_MPP, 0x00001800
@@ -22,8 +24,6 @@
.equ MIP_MTIP, (1 << 7) // machine mode timer interrupt pending
-.equ REGBYTES, 4
-
.text
.align 2
@@ -66,80 +66,73 @@ port_systick_pending_reset:
ret
-.macro SAVE_CONTEXT
- addi sp, sp, -32*REGBYTES
- sw x1, 2*REGBYTES(sp)
- sw x3, 3*REGBYTES(sp)
- sw x4, 4*REGBYTES(sp)
- sw x5, 5*REGBYTES(sp)
- sw x6, 6*REGBYTES(sp)
- sw x7, 7*REGBYTES(sp)
- sw x8, 8*REGBYTES(sp)
- sw x9, 9*REGBYTES(sp)
- sw x10, 10*REGBYTES(sp)
- sw x11, 11*REGBYTES(sp)
- sw x12, 12*REGBYTES(sp)
- sw x13, 13*REGBYTES(sp)
- sw x14, 14*REGBYTES(sp)
- sw x15, 15*REGBYTES(sp)
- sw x16, 16*REGBYTES(sp)
- sw x17, 17*REGBYTES(sp)
- sw x18, 18*REGBYTES(sp)
- sw x19, 19*REGBYTES(sp)
- sw x20, 20*REGBYTES(sp)
- sw x21, 21*REGBYTES(sp)
- sw x22, 22*REGBYTES(sp)
- sw x23, 23*REGBYTES(sp)
- sw x24, 24*REGBYTES(sp)
- sw x25, 25*REGBYTES(sp)
- sw x26, 26*REGBYTES(sp)
- sw x27, 27*REGBYTES(sp)
- sw x28, 28*REGBYTES(sp)
- sw x29, 29*REGBYTES(sp)
- sw x30, 30*REGBYTES(sp)
- sw x31, 31*REGBYTES(sp)
-.endm
+#define __reg_mepc_OFFSET 0x00
+#define __reg_mstatus_OFFSET 0x04
+#define __reg_x1_OFFSET 0x08
+#define __reg_x3_OFFSET 0x0C
+#define __reg_x4_OFFSET 0x10
+#define __reg_x5_OFFSET 0x14
+#define __reg_x6_OFFSET 0x18
+#define __reg_x7_OFFSET 0x1C
+#define __reg_x8_OFFSET 0x20
+#define __reg_x9_OFFSET 0x24
+#define __reg_x10_OFFSET 0x28
+#define __reg_x11_OFFSET 0x2C
+#define __reg_x12_OFFSET 0x30
+#define __reg_x13_OFFSET 0x34
+#define __reg_x14_OFFSET 0x38
+#define __reg_x15_OFFSET 0x3C
+#define __reg_x16_OFFSET 0x40
+#define __reg_x17_OFFSET 0x44
+#define __reg_x18_OFFSET 0x48
+#define __reg_x19_OFFSET 0x4C
+#define __reg_x20_OFFSET 0x50
+#define __reg_x21_OFFSET 0x54
+#define __reg_x22_OFFSET 0x58
+#define __reg_x23_OFFSET 0x5C
+#define __reg_x24_OFFSET 0x60
+#define __reg_x25_OFFSET 0x64
+#define __reg_x26_OFFSET 0x68
+#define __reg_x27_OFFSET 0x6C
+#define __reg_x28_OFFSET 0x70
+#define __reg_x29_OFFSET 0x74
+#define __reg_x30_OFFSET 0x78
+#define __reg_x31_OFFSET 0x7C
-.macro RESTORE_CONTEXT
- lw t0, 0*REGBYTES(sp)
- csrw mepc, t0
+#define __reg_mepc__OFFSET __reg_mepc_OFFSET
+#define __reg_mstatus__OFFSET __reg_mstatus_OFFSET
+#define __reg_ra__OFFSET __reg_x1_OFFSET
+#define __reg_gp__OFFSET __reg_x3_OFFSET
+#define __reg_tp__OFFSET __reg_x4_OFFSET
+#define __reg_t0__OFFSET __reg_x5_OFFSET
+#define __reg_t1__OFFSET __reg_x6_OFFSET
+#define __reg_t2__OFFSET __reg_x7_OFFSET
+#define __reg_s0__OFFSET __reg_x8_OFFSET
+#define __reg_fp__OFFSET __reg_x8_OFFSET
+#define __reg_s1__OFFSET __reg_x9_OFFSET
+#define __reg_a0__OFFSET __reg_x10_OFFSET
+#define __reg_a1__OFFSET __reg_x11_OFFSET
+#define __reg_a2__OFFSET __reg_x12_OFFSET
+#define __reg_a3__OFFSET __reg_x13_OFFSET
+#define __reg_a4__OFFSET __reg_x14_OFFSET
+#define __reg_a5__OFFSET __reg_x15_OFFSET
+#define __reg_a6__OFFSET __reg_x16_OFFSET
+#define __reg_a7__OFFSET __reg_x17_OFFSET
+#define __reg_s2__OFFSET __reg_x18_OFFSET
+#define __reg_s3__OFFSET __reg_x19_OFFSET
+#define __reg_s4__OFFSET __reg_x20_OFFSET
+#define __reg_s5__OFFSET __reg_x21_OFFSET
+#define __reg_s6__OFFSET __reg_x22_OFFSET
+#define __reg_s7__OFFSET __reg_x23_OFFSET
+#define __reg_s8__OFFSET __reg_x24_OFFSET
+#define __reg_s9__OFFSET __reg_x25_OFFSET
+#define __reg_s10__OFFSET __reg_x26_OFFSET
+#define __reg_s11__OFFSET __reg_x27_OFFSET
+#define __reg_t3__OFFSET __reg_x28_OFFSET
+#define __reg_t4__OFFSET __reg_x29_OFFSET
+#define __reg_t5__OFFSET __reg_x30_OFFSET
+#define __reg_t6__OFFSET __reg_x31_OFFSET
- lw t0, 1*REGBYTES(sp)
- csrw mstatus, t0
-
- lw x1, 2*REGBYTES(sp)
- lw x3, 3*REGBYTES(sp)
- lw x4, 4*REGBYTES(sp)
- lw x5, 5*REGBYTES(sp)
- lw x6, 6*REGBYTES(sp)
- lw x7, 7*REGBYTES(sp)
- lw x8, 8*REGBYTES(sp)
- lw x9, 9*REGBYTES(sp)
- lw x10, 10*REGBYTES(sp)
- lw x11, 11*REGBYTES(sp)
- lw x12, 12*REGBYTES(sp)
- lw x13, 13*REGBYTES(sp)
- lw x14, 14*REGBYTES(sp)
- lw x15, 15*REGBYTES(sp)
- lw x16, 16*REGBYTES(sp)
- lw x17, 17*REGBYTES(sp)
- lw x18, 18*REGBYTES(sp)
- lw x19, 19*REGBYTES(sp)
- lw x20, 20*REGBYTES(sp)
- lw x21, 21*REGBYTES(sp)
- lw x22, 22*REGBYTES(sp)
- lw x23, 23*REGBYTES(sp)
- lw x24, 24*REGBYTES(sp)
- lw x25, 25*REGBYTES(sp)
- lw x26, 26*REGBYTES(sp)
- lw x27, 27*REGBYTES(sp)
- lw x28, 28*REGBYTES(sp)
- lw x29, 29*REGBYTES(sp)
- lw x30, 30*REGBYTES(sp)
- lw x31, 31*REGBYTES(sp)
-
- addi sp, sp, 32*REGBYTES
-.endm
.align 2
.type port_sched_start, %function
@@ -154,10 +147,47 @@ port_sched_start:
lw sp, (t0) // sp = k_curr_task->sp
// save sp to stack
- addi t1, sp, 32*REGBYTES
+ addi t1, sp, 128
sw t1, (t0)
- RESTORE_CONTEXT
+ // restore context
+ lw t0, __reg_mepc__OFFSET(sp)
+ csrw mepc, t0
+
+ lw t0, __reg_mstatus__OFFSET(sp)
+ csrw mstatus, t0
+
+ lw x3, __reg_x3_OFFSET(sp)
+ lw x4, __reg_x4_OFFSET(sp)
+ lw x5, __reg_x5_OFFSET(sp)
+ lw x6, __reg_x6_OFFSET(sp)
+ lw x7, __reg_x7_OFFSET(sp)
+ lw x8, __reg_x8_OFFSET(sp)
+ lw x9, __reg_x9_OFFSET(sp)
+ lw x10, __reg_x10_OFFSET(sp)
+ lw x11, __reg_x11_OFFSET(sp)
+ lw x12, __reg_x12_OFFSET(sp)
+ lw x13, __reg_x13_OFFSET(sp)
+ lw x14, __reg_x14_OFFSET(sp)
+ lw x15, __reg_x15_OFFSET(sp)
+ lw x16, __reg_x16_OFFSET(sp)
+ lw x17, __reg_x17_OFFSET(sp)
+ lw x18, __reg_x18_OFFSET(sp)
+ lw x19, __reg_x19_OFFSET(sp)
+ lw x20, __reg_x20_OFFSET(sp)
+ lw x21, __reg_x21_OFFSET(sp)
+ lw x22, __reg_x22_OFFSET(sp)
+ lw x23, __reg_x23_OFFSET(sp)
+ lw x24, __reg_x24_OFFSET(sp)
+ lw x25, __reg_x25_OFFSET(sp)
+ lw x26, __reg_x26_OFFSET(sp)
+ lw x27, __reg_x27_OFFSET(sp)
+ lw x28, __reg_x28_OFFSET(sp)
+ lw x29, __reg_x29_OFFSET(sp)
+ lw x30, __reg_x30_OFFSET(sp)
+ lw x31, __reg_x31_OFFSET(sp)
+
+ addi sp, sp, 128
mret
@@ -165,14 +195,44 @@ port_sched_start:
.align 2
.type port_context_switch, %function
port_context_switch:
- SAVE_CONTEXT
+ addi sp, sp, -128
+ sw x3, __reg_x3_OFFSET(sp)
+ sw x4, __reg_x4_OFFSET(sp)
+ sw x5, __reg_x5_OFFSET(sp)
+ sw x6, __reg_x6_OFFSET(sp)
+ sw x7, __reg_x7_OFFSET(sp)
+ sw x8, __reg_x8_OFFSET(sp)
+ sw x9, __reg_x9_OFFSET(sp)
+ sw x10, __reg_x10_OFFSET(sp)
+ sw x11, __reg_x11_OFFSET(sp)
+ sw x12, __reg_x12_OFFSET(sp)
+ sw x13, __reg_x13_OFFSET(sp)
+ sw x14, __reg_x14_OFFSET(sp)
+ sw x15, __reg_x15_OFFSET(sp)
+ sw x16, __reg_x16_OFFSET(sp)
+ sw x17, __reg_x17_OFFSET(sp)
+ sw x18, __reg_x18_OFFSET(sp)
+ sw x19, __reg_x19_OFFSET(sp)
+ sw x20, __reg_x20_OFFSET(sp)
+ sw x21, __reg_x21_OFFSET(sp)
+ sw x22, __reg_x22_OFFSET(sp)
+ sw x23, __reg_x23_OFFSET(sp)
+ sw x24, __reg_x24_OFFSET(sp)
+ sw x25, __reg_x25_OFFSET(sp)
+ sw x26, __reg_x26_OFFSET(sp)
+ sw x27, __reg_x27_OFFSET(sp)
+ sw x28, __reg_x28_OFFSET(sp)
+ sw x29, __reg_x29_OFFSET(sp)
+ sw x30, __reg_x30_OFFSET(sp)
+ sw x31, __reg_x31_OFFSET(sp)
- sw ra, 0*REGBYTES(sp)
+
+ sw ra, __reg_mepc_OFFSET(sp)
csrr t0, mstatus
li t1, MSTATUS_MPP
or t0, t0, t1
- sw t0, 1*REGBYTES(sp)
+ sw t0, __reg_mstatus_OFFSET(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
@@ -188,59 +248,154 @@ port_context_switch:
// load new task sp
lw sp, (t1)
- RESTORE_CONTEXT
+ // restore context
+ lw t0, __reg_mepc_OFFSET(sp)
+ csrw mepc, t0
+
+ lw t0, __reg_mstatus_OFFSET(sp)
+ csrw mstatus, t0
+
+ lw x3, __reg_x3_OFFSET(sp)
+ lw x4, __reg_x4_OFFSET(sp)
+ lw x5, __reg_x5_OFFSET(sp)
+ lw x6, __reg_x6_OFFSET(sp)
+ lw x7, __reg_x7_OFFSET(sp)
+ lw x8, __reg_x8_OFFSET(sp)
+ lw x9, __reg_x9_OFFSET(sp)
+ lw x10, __reg_x10_OFFSET(sp)
+ lw x11, __reg_x11_OFFSET(sp)
+ lw x12, __reg_x12_OFFSET(sp)
+ lw x13, __reg_x13_OFFSET(sp)
+ lw x14, __reg_x14_OFFSET(sp)
+ lw x15, __reg_x15_OFFSET(sp)
+ lw x16, __reg_x16_OFFSET(sp)
+ lw x17, __reg_x17_OFFSET(sp)
+ lw x18, __reg_x18_OFFSET(sp)
+ lw x19, __reg_x19_OFFSET(sp)
+ lw x20, __reg_x20_OFFSET(sp)
+ lw x21, __reg_x21_OFFSET(sp)
+ lw x22, __reg_x22_OFFSET(sp)
+ lw x23, __reg_x23_OFFSET(sp)
+ lw x24, __reg_x24_OFFSET(sp)
+ lw x25, __reg_x25_OFFSET(sp)
+ lw x26, __reg_x26_OFFSET(sp)
+ lw x27, __reg_x27_OFFSET(sp)
+ lw x28, __reg_x28_OFFSET(sp)
+ lw x29, __reg_x29_OFFSET(sp)
+ lw x30, __reg_x30_OFFSET(sp)
+ lw x31, __reg_x31_OFFSET(sp)
+
+ addi sp, sp, 128
mret
+
.align 2
-.global trap_entry
-.global irq_entry
-trap_entry:
-irq_entry:
- SAVE_CONTEXT
+.global rv32_exception_entry
+rv32_exception_entry:
+ addi sp, sp, -128
+
+ sw ra, __reg_ra__OFFSET(sp)
+ sw gp, __reg_gp__OFFSET(sp)
+ sw tp, __reg_tp__OFFSET(sp)
+ sw t0, __reg_t0__OFFSET(sp)
+ sw t1, __reg_t1__OFFSET(sp)
+ sw t2, __reg_t2__OFFSET(sp)
+ sw t3, __reg_t3__OFFSET(sp)
+ sw t4, __reg_t4__OFFSET(sp)
+ sw t5, __reg_t5__OFFSET(sp)
+ sw t6, __reg_t6__OFFSET(sp)
+ sw a0, __reg_a0__OFFSET(sp)
+ sw a1, __reg_a1__OFFSET(sp)
+ sw a2, __reg_a2__OFFSET(sp)
+ sw a3, __reg_a3__OFFSET(sp)
+ sw a4, __reg_a4__OFFSET(sp)
+ sw a5, __reg_a5__OFFSET(sp)
+ sw a6, __reg_a6__OFFSET(sp)
+ sw a7, __reg_a7__OFFSET(sp)
csrr t0, mepc
- sw t0, 0*REGBYTES(sp)
+ sw t0, __reg_mepc__OFFSET(sp)
csrr t0, mstatus
- sw t0, 1*REGBYTES(sp)
-
- // save sp to k_curr_task.sp
- la t0, k_curr_task // t0 = &k_curr_task
- lw t1, (t0)
- sw sp, (t1)
+ sw t0, __reg_mstatus__OFFSET(sp)
+ // get irq num and call irq handler
+ li t0, SOC_MCAUSE_EXP_MASK
csrr a0, mcause
- mv a1, sp
- bltz a0, irq
- call cpu_trap_entry
- j irq_restore
-
-irq:
- slli a0, a0, 16
- srli a0, a0, 16
+ and a0, a0, t0
call cpu_irq_entry
- la t0, k_task_irq_switch_flag
- lw t1, (t0)
- beqz t1, irq_restore
- sw zero,(t0)
+ la t0, k_curr_task
+ la t1, k_next_task
+
+ beq t0, t1, irq_restore
+
+ sw s0, __reg_s0__OFFSET(sp)
+ sw s1, __reg_s1__OFFSET(sp)
+ sw s2, __reg_s2__OFFSET(sp)
+ sw s3, __reg_s3__OFFSET(sp)
+ sw s4, __reg_s4__OFFSET(sp)
+ sw s5, __reg_s5__OFFSET(sp)
+ sw s6, __reg_s6__OFFSET(sp)
+ sw s7, __reg_s7__OFFSET(sp)
+ sw s8, __reg_s8__OFFSET(sp)
+ sw s9, __reg_s9__OFFSET(sp)
+ sw s10, __reg_s10__OFFSET(sp)
+ sw s11, __reg_s11__OFFSET(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
- lw t1, (t0)
- sw sp, (t1)
+ lw t2, (t0) // t2 = k_curr_task->sp
+ sw sp, (t2) // k_curr_task->sp = sp
// switch task
- // k_curr_task = k_next_task
- la t1, k_next_task // t1 = &k_next_task
- lw t1, (t1) // t1 = k_next_task
- sw t1, (t0)
+ lw t1, (t1) // t1 = k_next_task
+ sw t1, (t0) // k_curr_task = k_next_task
// load new task sp
lw sp, (t1)
+ lw s0, __reg_s0__OFFSET(sp)
+ lw s1, __reg_s1__OFFSET(sp)
+ lw s2, __reg_s2__OFFSET(sp)
+ lw s3, __reg_s3__OFFSET(sp)
+ lw s4, __reg_s4__OFFSET(sp)
+ lw s5, __reg_s5__OFFSET(sp)
+ lw s6, __reg_s6__OFFSET(sp)
+ lw s7, __reg_s7__OFFSET(sp)
+ lw s8, __reg_s8__OFFSET(sp)
+ lw s9, __reg_s9__OFFSET(sp)
+ lw s10, __reg_s10__OFFSET(sp)
+ lw s11, __reg_s11__OFFSET(sp)
+
irq_restore:
- RESTORE_CONTEXT
+ lw t0, __reg_mepc_OFFSET(sp)
+ csrw mepc, t0
+
+ lw t0, __reg_mstatus_OFFSET(sp)
+ csrw mstatus, t0
+
+ lw ra, __reg_ra__OFFSET(sp)
+ lw gp, __reg_gp__OFFSET(sp)
+ lw tp, __reg_tp__OFFSET(sp)
+ lw t0, __reg_t0__OFFSET(sp)
+ lw t1, __reg_t1__OFFSET(sp)
+ lw t2, __reg_t2__OFFSET(sp)
+ lw t3, __reg_t3__OFFSET(sp)
+ lw t4, __reg_t4__OFFSET(sp)
+ lw t5, __reg_t5__OFFSET(sp)
+ lw t6, __reg_t6__OFFSET(sp)
+ lw a0, __reg_a0__OFFSET(sp)
+ lw a1, __reg_a1__OFFSET(sp)
+ lw a2, __reg_a2__OFFSET(sp)
+ lw a3, __reg_a3__OFFSET(sp)
+ lw a4, __reg_a4__OFFSET(sp)
+ lw a5, __reg_a5__OFFSET(sp)
+ lw a6, __reg_a6__OFFSET(sp)
+ lw a7, __reg_a7__OFFSET(sp)
+ addi sp, sp, 128
mret
+
+
diff --git a/arch/risc-v/spike/gcc/riscv_port.h b/arch/risc-v/spike/gcc/riscv_port.h
index 0e5d2f17..383199b7 100644
--- a/arch/risc-v/spike/gcc/riscv_port.h
+++ b/arch/risc-v/spike/gcc/riscv_port.h
@@ -23,8 +23,12 @@
#define CLINT_MTIMECMP 0x4000
#define CLINT_MTIME 0xBFF8
+#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
+
+#ifndef __ASSEMBLER__
void port_cpu_init();
void port_systick_priority_set(uint32_t priority);
+#endif /* __ASSEMBLER__ */
-#endif // _RISCV_PORT_H_
+#endif /* _RISCV_PORT_H_ */
diff --git a/board/GD32VF103C_START/eclipse/hello_world/.cproject b/board/GD32VF103C_START/eclipse/hello_world/.cproject
index 33bcd505..da3ae3b1 100644
--- a/board/GD32VF103C_START/eclipse/hello_world/.cproject
+++ b/board/GD32VF103C_START/eclipse/hello_world/.cproject
@@ -104,6 +104,8 @@
+
+
diff --git a/board/GD32VF103C_START/eclipse/hello_world/main.c b/board/GD32VF103C_START/eclipse/hello_world/main.c
index d3e3cbe5..7e362a6a 100644
--- a/board/GD32VF103C_START/eclipse/hello_world/main.c
+++ b/board/GD32VF103C_START/eclipse/hello_world/main.c
@@ -27,7 +27,7 @@ void task2(void *pdata)
share++;
for(int i=0; i<5; i++) {
printf("hello world from %s cnt: %08x\n", __func__, task_cnt2--);
- tos_task_delay(10);
+ tos_task_delay(50);
}
tos_sem_post(&sem);
}
diff --git a/board/QEMU_Spike/GCC/demo/Makefile b/board/QEMU_Spike/GCC/demo/Makefile
index bd74800b..6d015d6b 100644
--- a/board/QEMU_Spike/GCC/demo/Makefile
+++ b/board/QEMU_Spike/GCC/demo/Makefile
@@ -53,7 +53,7 @@ HAL_DRIVER_SRC = \
ASM_SOURCES =
ASM_SOURCES_S = \
-$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \
+$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \
start.S
diff --git a/board/QEMU_Spike/GCC/demo/start.S b/board/QEMU_Spike/GCC/demo/start.S
index 727ce1d1..4704d0ed 100644
--- a/board/QEMU_Spike/GCC/demo/start.S
+++ b/board/QEMU_Spike/GCC/demo/start.S
@@ -1,15 +1,13 @@
-// See LICENSE for license details.
-
-#include "riscv_encoding.h"
-
+.extern rv32_exception_entry
+.align 2
.section .text.entry
.globl _start
.type _start,@function
_start:
- csrc mstatus, MSTATUS_MIE
+ csrc mstatus, 0x00000008
csrw mie, 0
- la t0, trap_entry
+ la t0, rv32_exception_entry
csrw mtvec, t0
la sp, _stack_top
diff --git a/board/QEMU_Spike/eclipse/demo/.cproject b/board/QEMU_Spike/eclipse/demo/.cproject
index a892e24a..cad83a20 100644
--- a/board/QEMU_Spike/eclipse/demo/.cproject
+++ b/board/QEMU_Spike/eclipse/demo/.cproject
@@ -111,7 +111,7 @@
-
+
diff --git a/board/QEMU_Spike/eclipse/demo/start.S b/board/QEMU_Spike/eclipse/demo/start.S
index 727ce1d1..435fc6c6 100644
--- a/board/QEMU_Spike/eclipse/demo/start.S
+++ b/board/QEMU_Spike/eclipse/demo/start.S
@@ -1,15 +1,14 @@
-// See LICENSE for license details.
-
-#include "riscv_encoding.h"
+.extern rv32_exception_entry
+.align 2
.section .text.entry
.globl _start
.type _start,@function
_start:
- csrc mstatus, MSTATUS_MIE
+ csrc mstatus, 0x00000008
csrw mie, 0
- la t0, trap_entry
+ la t0, rv32_exception_entry
csrw mtvec, t0
la sp, _stack_top