From 2d419440f37aaa5051d773dd7a08cf2dc3b532fc Mon Sep 17 00:00:00 2001 From: acevest Date: Sat, 5 Oct 2019 15:48:45 +0800 Subject: [PATCH 1/6] divide bumblebee and spike irq trap entry code --- arch/risc-v/bumblebee/gcc/riscv_port_s.S | 167 +++++++++++++++ arch/risc-v/rv32i/gcc/port.h | 7 + arch/risc-v/rv32i/gcc/port_s.S | 194 ++++++++---------- arch/risc-v/spike/gcc/riscv_port_s.S | 120 +++++++++++ .../eclipse/hello_world/.cproject | 2 + .../eclipse/hello_world/main.c | 2 +- board/QEMU_Spike/GCC/demo/Makefile | 3 +- board/QEMU_Spike/GCC/demo/start.S | 9 +- board/QEMU_Spike/eclipse/demo/start.S | 9 +- 9 files changed, 392 insertions(+), 121 deletions(-) create mode 100644 arch/risc-v/bumblebee/gcc/riscv_port_s.S create mode 100644 arch/risc-v/spike/gcc/riscv_port_s.S diff --git a/arch/risc-v/bumblebee/gcc/riscv_port_s.S b/arch/risc-v/bumblebee/gcc/riscv_port_s.S new file mode 100644 index 00000000..4cf01539 --- /dev/null +++ b/arch/risc-v/bumblebee/gcc/riscv_port_s.S @@ -0,0 +1,167 @@ +#include "port.h" + +.global irq_entry +.global trap_entry + +.extern k_curr_task +.extern k_next_task +.extern k_task_irq_switch_flag + +.align 2 +irq_entry: + addi sp, sp, -32*REGBYTES + sw x1, 2*REGBYTES(sp) + sw x3, 3*REGBYTES(sp) + sw x4, 4*REGBYTES(sp) + sw x5, 5*REGBYTES(sp) + sw x6, 6*REGBYTES(sp) + sw x7, 7*REGBYTES(sp) + sw x8, 8*REGBYTES(sp) + sw x9, 9*REGBYTES(sp) + sw x10, 10*REGBYTES(sp) + sw x11, 11*REGBYTES(sp) + sw x12, 12*REGBYTES(sp) + sw x13, 13*REGBYTES(sp) + sw x14, 14*REGBYTES(sp) + sw x15, 15*REGBYTES(sp) + sw x16, 16*REGBYTES(sp) + sw x17, 17*REGBYTES(sp) + sw x18, 18*REGBYTES(sp) + sw x19, 19*REGBYTES(sp) + sw x20, 20*REGBYTES(sp) + sw x21, 21*REGBYTES(sp) + sw x22, 22*REGBYTES(sp) + sw x23, 23*REGBYTES(sp) + sw x24, 24*REGBYTES(sp) + sw x25, 25*REGBYTES(sp) + sw x26, 26*REGBYTES(sp) + sw x27, 27*REGBYTES(sp) + sw x28, 28*REGBYTES(sp) + sw x29, 29*REGBYTES(sp) + sw x30, 30*REGBYTES(sp) + sw x31, 31*REGBYTES(sp) + + csrr t0, mepc + sw t0, 0*REGBYTES(sp) + + csrr t0, mstatus + sw t0, 1*REGBYTES(sp) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) + + csrr a0, mcause + mv a1, sp + + slli a0, a0, 16 + srli a0, a0, 16 + call cpu_irq_entry + + la t0, k_task_irq_switch_flag + lw t1, (t0) + beqz t1, irq_restore + sw zero,(t0) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) + + // switch task + // k_curr_task = k_next_task + la t1, k_next_task // t1 = &k_next_task + lw t1, (t1) // t1 = k_next_task + sw t1, (t0) + + // load new task sp + lw sp, (t1) + +irq_restore: + // restore context + lw t0, 0*REGBYTES(sp) + csrw mepc, t0 + + lw t0, 1*REGBYTES(sp) + csrw mstatus, t0 + + lw x1, 2*REGBYTES(sp) + lw x3, 3*REGBYTES(sp) + lw x4, 4*REGBYTES(sp) + lw x5, 5*REGBYTES(sp) + lw x6, 6*REGBYTES(sp) + lw x7, 7*REGBYTES(sp) + lw x8, 8*REGBYTES(sp) + lw x9, 9*REGBYTES(sp) + lw x10, 10*REGBYTES(sp) + lw x11, 11*REGBYTES(sp) + lw x12, 12*REGBYTES(sp) + lw x13, 13*REGBYTES(sp) + lw x14, 14*REGBYTES(sp) + lw x15, 15*REGBYTES(sp) + lw x16, 16*REGBYTES(sp) + lw x17, 17*REGBYTES(sp) + lw x18, 18*REGBYTES(sp) + lw x19, 19*REGBYTES(sp) + lw x20, 20*REGBYTES(sp) + lw x21, 21*REGBYTES(sp) + lw x22, 22*REGBYTES(sp) + lw x23, 23*REGBYTES(sp) + lw x24, 24*REGBYTES(sp) + lw x25, 25*REGBYTES(sp) + lw x26, 26*REGBYTES(sp) + lw x27, 27*REGBYTES(sp) + lw x28, 28*REGBYTES(sp) + lw x29, 29*REGBYTES(sp) + lw x30, 30*REGBYTES(sp) + lw x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + + mret + + +.align 2 +trap_entry: + addi sp, sp, -32*REGBYTES + sw x1, 2*REGBYTES(sp) + sw x3, 3*REGBYTES(sp) + sw x4, 4*REGBYTES(sp) + sw x5, 5*REGBYTES(sp) + sw x6, 6*REGBYTES(sp) + sw x7, 7*REGBYTES(sp) + sw x8, 8*REGBYTES(sp) + sw x9, 9*REGBYTES(sp) + sw x10, 10*REGBYTES(sp) + sw x11, 11*REGBYTES(sp) + sw x12, 12*REGBYTES(sp) + sw x13, 13*REGBYTES(sp) + sw x14, 14*REGBYTES(sp) + sw x15, 15*REGBYTES(sp) + sw x16, 16*REGBYTES(sp) + sw x17, 17*REGBYTES(sp) + sw x18, 18*REGBYTES(sp) + sw x19, 19*REGBYTES(sp) + sw x20, 20*REGBYTES(sp) + sw x21, 21*REGBYTES(sp) + sw x22, 22*REGBYTES(sp) + sw x23, 23*REGBYTES(sp) + sw x24, 24*REGBYTES(sp) + sw x25, 25*REGBYTES(sp) + sw x26, 26*REGBYTES(sp) + sw x27, 27*REGBYTES(sp) + sw x28, 28*REGBYTES(sp) + sw x29, 29*REGBYTES(sp) + sw x30, 30*REGBYTES(sp) + sw x31, 31*REGBYTES(sp) + + csrr t0, mepc + sw t0, 0*REGBYTES(sp) + + csrr t0, mstatus + sw t0, 1*REGBYTES(sp) + + call cpu_trap_entry +1: + j 1b diff --git a/arch/risc-v/rv32i/gcc/port.h b/arch/risc-v/rv32i/gcc/port.h index a3da86ea..66772bd0 100644 --- a/arch/risc-v/rv32i/gcc/port.h +++ b/arch/risc-v/rv32i/gcc/port.h @@ -18,6 +18,8 @@ #ifndef _PORT_H_ #define _PORT_H_ +#ifndef __ASSEMBLER__ + __PORT__ void port_int_disable(void); __PORT__ void port_int_enable(void); @@ -69,4 +71,9 @@ __PORT__ void HardFault_Handler(void); __PORT__ void port_fault_diagnosis(void); #endif +#endif /* __ASSEMBLER__ */ + + +#define REGBYTES 4 + #endif /* _PORT_H_ */ diff --git a/arch/risc-v/rv32i/gcc/port_s.S b/arch/risc-v/rv32i/gcc/port_s.S index dc4b9b27..c0e729ba 100644 --- a/arch/risc-v/rv32i/gcc/port_s.S +++ b/arch/risc-v/rv32i/gcc/port_s.S @@ -65,42 +65,23 @@ port_systick_pending_reset: csrc mip, t0 ret +.align 2 +.type port_sched_start, %function +port_sched_start: + // enable timer interrupt + li t0, MIE_MTIE + csrs mie, t0 -.macro SAVE_CONTEXT - addi sp, sp, -32*REGBYTES - sw x1, 2*REGBYTES(sp) - sw x3, 3*REGBYTES(sp) - sw x4, 4*REGBYTES(sp) - sw x5, 5*REGBYTES(sp) - sw x6, 6*REGBYTES(sp) - sw x7, 7*REGBYTES(sp) - sw x8, 8*REGBYTES(sp) - sw x9, 9*REGBYTES(sp) - sw x10, 10*REGBYTES(sp) - sw x11, 11*REGBYTES(sp) - sw x12, 12*REGBYTES(sp) - sw x13, 13*REGBYTES(sp) - sw x14, 14*REGBYTES(sp) - sw x15, 15*REGBYTES(sp) - sw x16, 16*REGBYTES(sp) - sw x17, 17*REGBYTES(sp) - sw x18, 18*REGBYTES(sp) - sw x19, 19*REGBYTES(sp) - sw x20, 20*REGBYTES(sp) - sw x21, 21*REGBYTES(sp) - sw x22, 22*REGBYTES(sp) - sw x23, 23*REGBYTES(sp) - sw x24, 24*REGBYTES(sp) - sw x25, 25*REGBYTES(sp) - sw x26, 26*REGBYTES(sp) - sw x27, 27*REGBYTES(sp) - sw x28, 28*REGBYTES(sp) - sw x29, 29*REGBYTES(sp) - sw x30, 30*REGBYTES(sp) - sw x31, 31*REGBYTES(sp) -.endm + // load sp from k_curr_task->sp + la t0, k_curr_task // t0 = &k_curr_task + lw t0, (t0) // t0 = &(k_curr_task->sp) + lw sp, (t0) // sp = k_curr_task->sp -.macro RESTORE_CONTEXT + // save sp to stack + addi t1, sp, 32*REGBYTES + sw t1, (t0) + + // restore context lw t0, 0*REGBYTES(sp) csrw mepc, t0 @@ -139,25 +120,6 @@ port_systick_pending_reset: lw x31, 31*REGBYTES(sp) addi sp, sp, 32*REGBYTES -.endm - -.align 2 -.type port_sched_start, %function -port_sched_start: - // enable timer interrupt - li t0, MIE_MTIE - csrs mie, t0 - - // load sp from k_curr_task->sp - la t0, k_curr_task // t0 = &k_curr_task - lw t0, (t0) // t0 = &(k_curr_task->sp) - lw sp, (t0) // sp = k_curr_task->sp - - // save sp to stack - addi t1, sp, 32*REGBYTES - sw t1, (t0) - - RESTORE_CONTEXT mret @@ -165,7 +127,38 @@ port_sched_start: .align 2 .type port_context_switch, %function port_context_switch: - SAVE_CONTEXT + addi sp, sp, -32*REGBYTES + sw x1, 2*REGBYTES(sp) + sw x3, 3*REGBYTES(sp) + sw x4, 4*REGBYTES(sp) + sw x5, 5*REGBYTES(sp) + sw x6, 6*REGBYTES(sp) + sw x7, 7*REGBYTES(sp) + sw x8, 8*REGBYTES(sp) + sw x9, 9*REGBYTES(sp) + sw x10, 10*REGBYTES(sp) + sw x11, 11*REGBYTES(sp) + sw x12, 12*REGBYTES(sp) + sw x13, 13*REGBYTES(sp) + sw x14, 14*REGBYTES(sp) + sw x15, 15*REGBYTES(sp) + sw x16, 16*REGBYTES(sp) + sw x17, 17*REGBYTES(sp) + sw x18, 18*REGBYTES(sp) + sw x19, 19*REGBYTES(sp) + sw x20, 20*REGBYTES(sp) + sw x21, 21*REGBYTES(sp) + sw x22, 22*REGBYTES(sp) + sw x23, 23*REGBYTES(sp) + sw x24, 24*REGBYTES(sp) + sw x25, 25*REGBYTES(sp) + sw x26, 26*REGBYTES(sp) + sw x27, 27*REGBYTES(sp) + sw x28, 28*REGBYTES(sp) + sw x29, 29*REGBYTES(sp) + sw x30, 30*REGBYTES(sp) + sw x31, 31*REGBYTES(sp) + sw ra, 0*REGBYTES(sp) @@ -188,59 +181,44 @@ port_context_switch: // load new task sp lw sp, (t1) - RESTORE_CONTEXT - - mret - -.align 2 -.global trap_entry -.global irq_entry -trap_entry: -irq_entry: - SAVE_CONTEXT - - csrr t0, mepc - sw t0, 0*REGBYTES(sp) - - csrr t0, mstatus - sw t0, 1*REGBYTES(sp) - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - lw t1, (t0) - sw sp, (t1) - - csrr a0, mcause - mv a1, sp - bltz a0, irq - call cpu_trap_entry - j irq_restore - -irq: - slli a0, a0, 16 - srli a0, a0, 16 - call cpu_irq_entry - - la t0, k_task_irq_switch_flag - lw t1, (t0) - beqz t1, irq_restore - sw zero,(t0) - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - lw t1, (t0) - sw sp, (t1) - - // switch task - // k_curr_task = k_next_task - la t1, k_next_task // t1 = &k_next_task - lw t1, (t1) // t1 = k_next_task - sw t1, (t0) - - // load new task sp - lw sp, (t1) - -irq_restore: - RESTORE_CONTEXT + // restore context + lw t0, 0*REGBYTES(sp) + csrw mepc, t0 + + lw t0, 1*REGBYTES(sp) + csrw mstatus, t0 + + lw x1, 2*REGBYTES(sp) + lw x3, 3*REGBYTES(sp) + lw x4, 4*REGBYTES(sp) + lw x5, 5*REGBYTES(sp) + lw x6, 6*REGBYTES(sp) + lw x7, 7*REGBYTES(sp) + lw x8, 8*REGBYTES(sp) + lw x9, 9*REGBYTES(sp) + lw x10, 10*REGBYTES(sp) + lw x11, 11*REGBYTES(sp) + lw x12, 12*REGBYTES(sp) + lw x13, 13*REGBYTES(sp) + lw x14, 14*REGBYTES(sp) + lw x15, 15*REGBYTES(sp) + lw x16, 16*REGBYTES(sp) + lw x17, 17*REGBYTES(sp) + lw x18, 18*REGBYTES(sp) + lw x19, 19*REGBYTES(sp) + lw x20, 20*REGBYTES(sp) + lw x21, 21*REGBYTES(sp) + lw x22, 22*REGBYTES(sp) + lw x23, 23*REGBYTES(sp) + lw x24, 24*REGBYTES(sp) + lw x25, 25*REGBYTES(sp) + lw x26, 26*REGBYTES(sp) + lw x27, 27*REGBYTES(sp) + lw x28, 28*REGBYTES(sp) + lw x29, 29*REGBYTES(sp) + lw x30, 30*REGBYTES(sp) + lw x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES mret diff --git a/arch/risc-v/spike/gcc/riscv_port_s.S b/arch/risc-v/spike/gcc/riscv_port_s.S new file mode 100644 index 00000000..b32e8d82 --- /dev/null +++ b/arch/risc-v/spike/gcc/riscv_port_s.S @@ -0,0 +1,120 @@ +.equ REGBYTES, 4 + +.align 2 +.global rv32_trap_entry +rv32_trap_entry: + addi sp, sp, -32*REGBYTES + sw x1, 2*REGBYTES(sp) + sw x3, 3*REGBYTES(sp) + sw x4, 4*REGBYTES(sp) + sw x5, 5*REGBYTES(sp) + sw x6, 6*REGBYTES(sp) + sw x7, 7*REGBYTES(sp) + sw x8, 8*REGBYTES(sp) + sw x9, 9*REGBYTES(sp) + sw x10, 10*REGBYTES(sp) + sw x11, 11*REGBYTES(sp) + sw x12, 12*REGBYTES(sp) + sw x13, 13*REGBYTES(sp) + sw x14, 14*REGBYTES(sp) + sw x15, 15*REGBYTES(sp) + sw x16, 16*REGBYTES(sp) + sw x17, 17*REGBYTES(sp) + sw x18, 18*REGBYTES(sp) + sw x19, 19*REGBYTES(sp) + sw x20, 20*REGBYTES(sp) + sw x21, 21*REGBYTES(sp) + sw x22, 22*REGBYTES(sp) + sw x23, 23*REGBYTES(sp) + sw x24, 24*REGBYTES(sp) + sw x25, 25*REGBYTES(sp) + sw x26, 26*REGBYTES(sp) + sw x27, 27*REGBYTES(sp) + sw x28, 28*REGBYTES(sp) + sw x29, 29*REGBYTES(sp) + sw x30, 30*REGBYTES(sp) + sw x31, 31*REGBYTES(sp) + + csrr t0, mepc + sw t0, 0*REGBYTES(sp) + + csrr t0, mstatus + sw t0, 1*REGBYTES(sp) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) + + csrr a0, mcause + mv a1, sp + bltz a0, handle_irq + call cpu_trap_entry + j irq_restore + +handle_irq: + slli a0, a0, 16 + srli a0, a0, 16 + call cpu_irq_entry + + la t0, k_task_irq_switch_flag + lw t1, (t0) + beqz t1, irq_restore + sw zero,(t0) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) + + // switch task + // k_curr_task = k_next_task + la t1, k_next_task // t1 = &k_next_task + lw t1, (t1) // t1 = k_next_task + sw t1, (t0) + + // load new task sp + lw sp, (t1) + +irq_restore: + // restore context + lw t0, 0*REGBYTES(sp) + csrw mepc, t0 + + lw t0, 1*REGBYTES(sp) + csrw mstatus, t0 + + lw x1, 2*REGBYTES(sp) + lw x3, 3*REGBYTES(sp) + lw x4, 4*REGBYTES(sp) + lw x5, 5*REGBYTES(sp) + lw x6, 6*REGBYTES(sp) + lw x7, 7*REGBYTES(sp) + lw x8, 8*REGBYTES(sp) + lw x9, 9*REGBYTES(sp) + lw x10, 10*REGBYTES(sp) + lw x11, 11*REGBYTES(sp) + lw x12, 12*REGBYTES(sp) + lw x13, 13*REGBYTES(sp) + lw x14, 14*REGBYTES(sp) + lw x15, 15*REGBYTES(sp) + lw x16, 16*REGBYTES(sp) + lw x17, 17*REGBYTES(sp) + lw x18, 18*REGBYTES(sp) + lw x19, 19*REGBYTES(sp) + lw x20, 20*REGBYTES(sp) + lw x21, 21*REGBYTES(sp) + lw x22, 22*REGBYTES(sp) + lw x23, 23*REGBYTES(sp) + lw x24, 24*REGBYTES(sp) + lw x25, 25*REGBYTES(sp) + lw x26, 26*REGBYTES(sp) + lw x27, 27*REGBYTES(sp) + lw x28, 28*REGBYTES(sp) + lw x29, 29*REGBYTES(sp) + lw x30, 30*REGBYTES(sp) + lw x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + + mret diff --git a/board/GD32VF103C_START/eclipse/hello_world/.cproject b/board/GD32VF103C_START/eclipse/hello_world/.cproject index 33bcd505..75158d6b 100644 --- a/board/GD32VF103C_START/eclipse/hello_world/.cproject +++ b/board/GD32VF103C_START/eclipse/hello_world/.cproject @@ -104,6 +104,8 @@ + + diff --git a/board/GD32VF103C_START/eclipse/hello_world/main.c b/board/GD32VF103C_START/eclipse/hello_world/main.c index d3e3cbe5..7e362a6a 100644 --- a/board/GD32VF103C_START/eclipse/hello_world/main.c +++ b/board/GD32VF103C_START/eclipse/hello_world/main.c @@ -27,7 +27,7 @@ void task2(void *pdata) share++; for(int i=0; i<5; i++) { printf("hello world from %s cnt: %08x\n", __func__, task_cnt2--); - tos_task_delay(10); + tos_task_delay(50); } tos_sem_post(&sem); } diff --git a/board/QEMU_Spike/GCC/demo/Makefile b/board/QEMU_Spike/GCC/demo/Makefile index bd74800b..703b6eaa 100644 --- a/board/QEMU_Spike/GCC/demo/Makefile +++ b/board/QEMU_Spike/GCC/demo/Makefile @@ -53,7 +53,8 @@ HAL_DRIVER_SRC = \ ASM_SOURCES = ASM_SOURCES_S = \ -$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \ +$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \ +$(TOP_DIR)/arch/risc-v/spike/gcc/riscv_port_s.S \ start.S diff --git a/board/QEMU_Spike/GCC/demo/start.S b/board/QEMU_Spike/GCC/demo/start.S index 727ce1d1..b4f89008 100644 --- a/board/QEMU_Spike/GCC/demo/start.S +++ b/board/QEMU_Spike/GCC/demo/start.S @@ -1,15 +1,12 @@ -// See LICENSE for license details. - -#include "riscv_encoding.h" - +.align 2 .section .text.entry .globl _start .type _start,@function _start: - csrc mstatus, MSTATUS_MIE + csrc mstatus, 0x00000008 csrw mie, 0 - la t0, trap_entry + la t0, rv32_trap_entry csrw mtvec, t0 la sp, _stack_top diff --git a/board/QEMU_Spike/eclipse/demo/start.S b/board/QEMU_Spike/eclipse/demo/start.S index 727ce1d1..4a18fd96 100644 --- a/board/QEMU_Spike/eclipse/demo/start.S +++ b/board/QEMU_Spike/eclipse/demo/start.S @@ -1,15 +1,14 @@ -// See LICENSE for license details. - -#include "riscv_encoding.h" +.extern rv32_trap_entry +.align 2 .section .text.entry .globl _start .type _start,@function _start: - csrc mstatus, MSTATUS_MIE + csrc mstatus, 0x00000008 csrw mie, 0 - la t0, trap_entry + la t0, rv32_trap_entry csrw mtvec, t0 la sp, _stack_top From 2fdc9f600cc7e3b603e32823cb488e69105e8236 Mon Sep 17 00:00:00 2001 From: acevest Date: Sat, 5 Oct 2019 15:50:03 +0800 Subject: [PATCH 2/6] fix bumblebee trap_entry memory address alignment problem --- arch/risc-v/bumblebee/gcc/riscv_port_s.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/risc-v/bumblebee/gcc/riscv_port_s.S b/arch/risc-v/bumblebee/gcc/riscv_port_s.S index 4cf01539..9ec8b570 100644 --- a/arch/risc-v/bumblebee/gcc/riscv_port_s.S +++ b/arch/risc-v/bumblebee/gcc/riscv_port_s.S @@ -122,7 +122,7 @@ irq_restore: mret -.align 2 +.align 6 trap_entry: addi sp, sp, -32*REGBYTES sw x1, 2*REGBYTES(sp) From 44f0ac6579629beda8723d318c0a053f979068cc Mon Sep 17 00:00:00 2001 From: acevest Date: Sat, 5 Oct 2019 18:23:15 +0800 Subject: [PATCH 3/6] irq context switch do not use flag variable anymore --- arch/risc-v/bumblebee/gcc/riscv_port_s.S | 33 ++++++++++++++---------- arch/risc-v/common/tos_cpu.c | 2 +- arch/risc-v/rv32i/gcc/port_c.c | 8 ------ arch/risc-v/spike/gcc/riscv_port_s.S | 22 +++++++--------- 4 files changed, 31 insertions(+), 34 deletions(-) diff --git a/arch/risc-v/bumblebee/gcc/riscv_port_s.S b/arch/risc-v/bumblebee/gcc/riscv_port_s.S index 9ec8b570..ef6c9352 100644 --- a/arch/risc-v/bumblebee/gcc/riscv_port_s.S +++ b/arch/risc-v/bumblebee/gcc/riscv_port_s.S @@ -5,7 +5,6 @@ .extern k_curr_task .extern k_next_task -.extern k_task_irq_switch_flag .align 2 irq_entry: @@ -55,25 +54,33 @@ irq_entry: csrr a0, mcause mv a1, sp - slli a0, a0, 16 - srli a0, a0, 16 + // the bumblebee mstatus register is different + // name bit detail + // INTERRUPT 31 0: exception or nmi, 1 irq + // MINHV 30 reading irq vector table + // MPP 29:28 == mstatus.MPP + // MPIE 27 == mstatus.MPIE + // Reserved 26:24 0 + // MPIL 23:16 previous interrupt level + // Reserved 15:12 0 + // EXCCODE 11:0 exception code + slli a0, a0, 20 + srli a0, a0, 20 call cpu_irq_entry - la t0, k_task_irq_switch_flag - lw t1, (t0) - beqz t1, irq_restore - sw zero,(t0) + la t0, k_curr_task + la t1, k_next_task + + beq t0, t1, irq_restore // save sp to k_curr_task.sp la t0, k_curr_task // t0 = &k_curr_task - lw t1, (t0) - sw sp, (t1) + lw t2, (t0) // t2 = k_curr_task->sp + sw sp, (t2) // k_curr_task->sp = sp // switch task - // k_curr_task = k_next_task - la t1, k_next_task // t1 = &k_next_task - lw t1, (t1) // t1 = k_next_task - sw t1, (t0) + lw t1, (t1) // t1 = k_next_task + sw t1, (t0) // k_curr_task = k_next_task // load new task sp lw sp, (t1) diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c index d841eef6..0791b0e6 100644 --- a/arch/risc-v/common/tos_cpu.c +++ b/arch/risc-v/common/tos_cpu.c @@ -32,7 +32,7 @@ __KERNEL__ void cpu_context_switch(void) __KERNEL__ void cpu_irq_context_switch(void) { - port_irq_context_switch(); + // DO NOTHING } __KERNEL__ void cpu_sched_start(void) diff --git a/arch/risc-v/rv32i/gcc/port_c.c b/arch/risc-v/rv32i/gcc/port_c.c index ef0de3f9..c53a1f80 100644 --- a/arch/risc-v/rv32i/gcc/port_c.c +++ b/arch/risc-v/rv32i/gcc/port_c.c @@ -31,11 +31,3 @@ __PORT__ void port_systick_config(uint32_t cycle_per_tick) *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF & (mtimecmp >> 32); *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF & (mtimecmp >> 0); } - - - -int k_task_irq_switch_flag = 0; -__PORT__ void port_irq_context_switch() -{ - k_task_irq_switch_flag = 1; -} diff --git a/arch/risc-v/spike/gcc/riscv_port_s.S b/arch/risc-v/spike/gcc/riscv_port_s.S index b32e8d82..925889eb 100644 --- a/arch/risc-v/spike/gcc/riscv_port_s.S +++ b/arch/risc-v/spike/gcc/riscv_port_s.S @@ -1,4 +1,4 @@ -.equ REGBYTES, 4 +#include "port.h" .align 2 .global rv32_trap_entry @@ -53,25 +53,23 @@ rv32_trap_entry: j irq_restore handle_irq: - slli a0, a0, 16 - srli a0, a0, 16 + slli a0, a0, 1 + srli a0, a0, 1 call cpu_irq_entry - la t0, k_task_irq_switch_flag - lw t1, (t0) - beqz t1, irq_restore - sw zero,(t0) + la t0, k_curr_task + la t1, k_next_task + + beq t0, t1, irq_restore // save sp to k_curr_task.sp la t0, k_curr_task // t0 = &k_curr_task - lw t1, (t0) - sw sp, (t1) + lw t2, (t0) + sw sp, (t2) // switch task - // k_curr_task = k_next_task - la t1, k_next_task // t1 = &k_next_task lw t1, (t1) // t1 = k_next_task - sw t1, (t0) + sw t1, (t0) // k_curr_task = k_next_task // load new task sp lw sp, (t1) From e5e905e9bb11b019738b94f797c10a6526993f0b Mon Sep 17 00:00:00 2001 From: acevest Date: Sun, 6 Oct 2019 15:27:40 +0800 Subject: [PATCH 4/6] adjust the order of registers on the stack --- arch/risc-v/bumblebee/gcc/riscv_port.h | 14 + arch/risc-v/bumblebee/gcc/riscv_port_s.S | 168 +-------- arch/risc-v/common/include/tos_cpu.h | 69 ++-- arch/risc-v/common/tos_cpu.c | 2 + arch/risc-v/rv32i/gcc/port_s.S | 321 ++++++++++++------ arch/risc-v/spike/gcc/riscv_port.h | 6 +- .../eclipse/hello_world/.cproject | 2 +- 7 files changed, 288 insertions(+), 294 deletions(-) diff --git a/arch/risc-v/bumblebee/gcc/riscv_port.h b/arch/risc-v/bumblebee/gcc/riscv_port.h index 9484a704..fca00a56 100644 --- a/arch/risc-v/bumblebee/gcc/riscv_port.h +++ b/arch/risc-v/bumblebee/gcc/riscv_port.h @@ -24,8 +24,22 @@ #define CLINT_MTIMECMP 0x0008 #define CLINT_MTIME 0x0000 +// the bumblebee mstatus register is different +// name bit detail +// INTERRUPT 31 0: exception or nmi, 1 irq +// MINHV 30 reading irq vector table +// MPP 29:28 == mstatus.MPP +// MPIE 27 == mstatus.MPIE +// Reserved 26:24 0 +// MPIL 23:16 previous interrupt level +// Reserved 15:12 0 +// EXCCODE 11:0 exception code +#define SOC_MCAUSE_EXP_MASK 0x00000FFF + +#ifndef __ASSEMBLER__ void port_cpu_init(); void port_systick_priority_set(uint32_t priority); +#endif #endif // _RISCV_PORT_H_ diff --git a/arch/risc-v/bumblebee/gcc/riscv_port_s.S b/arch/risc-v/bumblebee/gcc/riscv_port_s.S index ef6c9352..1683a0b6 100644 --- a/arch/risc-v/bumblebee/gcc/riscv_port_s.S +++ b/arch/risc-v/bumblebee/gcc/riscv_port_s.S @@ -1,174 +1,12 @@ -#include "port.h" - .global irq_entry .global trap_entry -.extern k_curr_task -.extern k_next_task +.extern rv32_exception_entry .align 2 irq_entry: - addi sp, sp, -32*REGBYTES - sw x1, 2*REGBYTES(sp) - sw x3, 3*REGBYTES(sp) - sw x4, 4*REGBYTES(sp) - sw x5, 5*REGBYTES(sp) - sw x6, 6*REGBYTES(sp) - sw x7, 7*REGBYTES(sp) - sw x8, 8*REGBYTES(sp) - sw x9, 9*REGBYTES(sp) - sw x10, 10*REGBYTES(sp) - sw x11, 11*REGBYTES(sp) - sw x12, 12*REGBYTES(sp) - sw x13, 13*REGBYTES(sp) - sw x14, 14*REGBYTES(sp) - sw x15, 15*REGBYTES(sp) - sw x16, 16*REGBYTES(sp) - sw x17, 17*REGBYTES(sp) - sw x18, 18*REGBYTES(sp) - sw x19, 19*REGBYTES(sp) - sw x20, 20*REGBYTES(sp) - sw x21, 21*REGBYTES(sp) - sw x22, 22*REGBYTES(sp) - sw x23, 23*REGBYTES(sp) - sw x24, 24*REGBYTES(sp) - sw x25, 25*REGBYTES(sp) - sw x26, 26*REGBYTES(sp) - sw x27, 27*REGBYTES(sp) - sw x28, 28*REGBYTES(sp) - sw x29, 29*REGBYTES(sp) - sw x30, 30*REGBYTES(sp) - sw x31, 31*REGBYTES(sp) - - csrr t0, mepc - sw t0, 0*REGBYTES(sp) - - csrr t0, mstatus - sw t0, 1*REGBYTES(sp) - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - lw t1, (t0) - sw sp, (t1) - - csrr a0, mcause - mv a1, sp - - // the bumblebee mstatus register is different - // name bit detail - // INTERRUPT 31 0: exception or nmi, 1 irq - // MINHV 30 reading irq vector table - // MPP 29:28 == mstatus.MPP - // MPIE 27 == mstatus.MPIE - // Reserved 26:24 0 - // MPIL 23:16 previous interrupt level - // Reserved 15:12 0 - // EXCCODE 11:0 exception code - slli a0, a0, 20 - srli a0, a0, 20 - call cpu_irq_entry - - la t0, k_curr_task - la t1, k_next_task - - beq t0, t1, irq_restore - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - lw t2, (t0) // t2 = k_curr_task->sp - sw sp, (t2) // k_curr_task->sp = sp - - // switch task - lw t1, (t1) // t1 = k_next_task - sw t1, (t0) // k_curr_task = k_next_task - - // load new task sp - lw sp, (t1) - -irq_restore: - // restore context - lw t0, 0*REGBYTES(sp) - csrw mepc, t0 - - lw t0, 1*REGBYTES(sp) - csrw mstatus, t0 - - lw x1, 2*REGBYTES(sp) - lw x3, 3*REGBYTES(sp) - lw x4, 4*REGBYTES(sp) - lw x5, 5*REGBYTES(sp) - lw x6, 6*REGBYTES(sp) - lw x7, 7*REGBYTES(sp) - lw x8, 8*REGBYTES(sp) - lw x9, 9*REGBYTES(sp) - lw x10, 10*REGBYTES(sp) - lw x11, 11*REGBYTES(sp) - lw x12, 12*REGBYTES(sp) - lw x13, 13*REGBYTES(sp) - lw x14, 14*REGBYTES(sp) - lw x15, 15*REGBYTES(sp) - lw x16, 16*REGBYTES(sp) - lw x17, 17*REGBYTES(sp) - lw x18, 18*REGBYTES(sp) - lw x19, 19*REGBYTES(sp) - lw x20, 20*REGBYTES(sp) - lw x21, 21*REGBYTES(sp) - lw x22, 22*REGBYTES(sp) - lw x23, 23*REGBYTES(sp) - lw x24, 24*REGBYTES(sp) - lw x25, 25*REGBYTES(sp) - lw x26, 26*REGBYTES(sp) - lw x27, 27*REGBYTES(sp) - lw x28, 28*REGBYTES(sp) - lw x29, 29*REGBYTES(sp) - lw x30, 30*REGBYTES(sp) - lw x31, 31*REGBYTES(sp) - - addi sp, sp, 32*REGBYTES - - mret - + j rv32_exception_entry .align 6 trap_entry: - addi sp, sp, -32*REGBYTES - sw x1, 2*REGBYTES(sp) - sw x3, 3*REGBYTES(sp) - sw x4, 4*REGBYTES(sp) - sw x5, 5*REGBYTES(sp) - sw x6, 6*REGBYTES(sp) - sw x7, 7*REGBYTES(sp) - sw x8, 8*REGBYTES(sp) - sw x9, 9*REGBYTES(sp) - sw x10, 10*REGBYTES(sp) - sw x11, 11*REGBYTES(sp) - sw x12, 12*REGBYTES(sp) - sw x13, 13*REGBYTES(sp) - sw x14, 14*REGBYTES(sp) - sw x15, 15*REGBYTES(sp) - sw x16, 16*REGBYTES(sp) - sw x17, 17*REGBYTES(sp) - sw x18, 18*REGBYTES(sp) - sw x19, 19*REGBYTES(sp) - sw x20, 20*REGBYTES(sp) - sw x21, 21*REGBYTES(sp) - sw x22, 22*REGBYTES(sp) - sw x23, 23*REGBYTES(sp) - sw x24, 24*REGBYTES(sp) - sw x25, 25*REGBYTES(sp) - sw x26, 26*REGBYTES(sp) - sw x27, 27*REGBYTES(sp) - sw x28, 28*REGBYTES(sp) - sw x29, 29*REGBYTES(sp) - sw x30, 30*REGBYTES(sp) - sw x31, 31*REGBYTES(sp) - - csrr t0, mepc - sw t0, 0*REGBYTES(sp) - - csrr t0, mstatus - sw t0, 1*REGBYTES(sp) - - call cpu_trap_entry -1: - j 1b + j rv32_exception_entry diff --git a/arch/risc-v/common/include/tos_cpu.h b/arch/risc-v/common/include/tos_cpu.h index 75695178..783672ca 100644 --- a/arch/risc-v/common/include/tos_cpu.h +++ b/arch/risc-v/common/include/tos_cpu.h @@ -1,40 +1,46 @@ #ifndef _TOS_CPU_H_ #define _TOS_CPU_H_ - typedef struct cpu_context_st { + union { cpu_data_t s0, x8, fp; }; + union { cpu_data_t s1, x9; }; + union { cpu_data_t s2, x18; }; + union { cpu_data_t s3, x19; }; + union { cpu_data_t s4, x20; }; + union { cpu_data_t s5, x21; }; + union { cpu_data_t s6, x22; }; + union { cpu_data_t s7, x23; }; + union { cpu_data_t s8, x24; }; + union { cpu_data_t s9, x25; }; + union { cpu_data_t s10,x26; }; + union { cpu_data_t s11,x27; }; + + // caller save + union { cpu_data_t ra, x1; }; + + union { cpu_data_t gp, x3; }; + union { cpu_data_t tp, x4; }; + + union { cpu_data_t t0, x5; }; + union { cpu_data_t t1, x6; }; + union { cpu_data_t t2, x7; }; + union { cpu_data_t t3, x28; }; + union { cpu_data_t t4, x29; }; + union { cpu_data_t t5, x30; }; + union { cpu_data_t t6, x31; }; + + union { cpu_data_t a0, x10; }; + union { cpu_data_t a1, x11; }; + + union { cpu_data_t a2, x12; }; + union { cpu_data_t a3, x13; }; + union { cpu_data_t a4, x14; }; + union { cpu_data_t a5, x15; }; + union { cpu_data_t a6, x16; }; + union { cpu_data_t a7, x17; }; + cpu_data_t epc; cpu_data_t mstatus; - union { cpu_data_t x1, ra; }; - union { cpu_data_t x3, gp; }; - union { cpu_data_t x4, tp; }; - union { cpu_data_t x5, t0; }; - union { cpu_data_t x6, t1; }; - union { cpu_data_t x7, t2; }; - union { cpu_data_t x8, s0, fp; }; - union { cpu_data_t x9, s1; }; - union { cpu_data_t x10, a0; }; - union { cpu_data_t x11, a1; }; - union { cpu_data_t x12, a2; }; - union { cpu_data_t x13, a3; }; - union { cpu_data_t x14, a4; }; - union { cpu_data_t x15, a5; }; - union { cpu_data_t x16, a6; }; - union { cpu_data_t x17, a7; }; - union { cpu_data_t x18, s2; }; - union { cpu_data_t x19, s3; }; - union { cpu_data_t x20, s4; }; - union { cpu_data_t x21, s5; }; - union { cpu_data_t x22, s6; }; - union { cpu_data_t x23, s7; }; - union { cpu_data_t x24, s8; }; - union { cpu_data_t x25, s9; }; - union { cpu_data_t x26, s10; }; - union { cpu_data_t x27, s11; }; - union { cpu_data_t x28, t3; }; - union { cpu_data_t x29, t4; }; - union { cpu_data_t x30, t5; }; - union { cpu_data_t x31, t6; }; } cpu_context_t; __API__ uint32_t tos_cpu_clz(uint32_t val); @@ -115,4 +121,5 @@ __KERNEL__ void cpu_standby_mode_enter(void); tos_cpu_cpsr_restore(cpu_cpsr); \ } while (0) + #endif /* _TOS_CPU_H_ */ diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c index 0791b0e6..63b16389 100644 --- a/arch/risc-v/common/tos_cpu.c +++ b/arch/risc-v/common/tos_cpu.c @@ -172,3 +172,5 @@ __API__ uint32_t tos_cpu_clz(uint32_t val) return (nbr_lead_zeros); } + + diff --git a/arch/risc-v/rv32i/gcc/port_s.S b/arch/risc-v/rv32i/gcc/port_s.S index c0e729ba..821f4510 100644 --- a/arch/risc-v/rv32i/gcc/port_s.S +++ b/arch/risc-v/rv32i/gcc/port_s.S @@ -1,3 +1,5 @@ +#include "riscv_port.h" + .global port_int_disable .global port_int_enable @@ -82,42 +84,45 @@ port_sched_start: sw t1, (t0) // restore context - lw t0, 0*REGBYTES(sp) + lw t0, 30*REGBYTES(sp) csrw mepc, t0 - lw t0, 1*REGBYTES(sp) + lw t0, 31*REGBYTES(sp) csrw mstatus, t0 - lw x1, 2*REGBYTES(sp) - lw x3, 3*REGBYTES(sp) - lw x4, 4*REGBYTES(sp) - lw x5, 5*REGBYTES(sp) - lw x6, 6*REGBYTES(sp) - lw x7, 7*REGBYTES(sp) - lw x8, 8*REGBYTES(sp) - lw x9, 9*REGBYTES(sp) - lw x10, 10*REGBYTES(sp) - lw x11, 11*REGBYTES(sp) - lw x12, 12*REGBYTES(sp) - lw x13, 13*REGBYTES(sp) - lw x14, 14*REGBYTES(sp) - lw x15, 15*REGBYTES(sp) - lw x16, 16*REGBYTES(sp) - lw x17, 17*REGBYTES(sp) - lw x18, 18*REGBYTES(sp) - lw x19, 19*REGBYTES(sp) - lw x20, 20*REGBYTES(sp) - lw x21, 21*REGBYTES(sp) - lw x22, 22*REGBYTES(sp) - lw x23, 23*REGBYTES(sp) - lw x24, 24*REGBYTES(sp) - lw x25, 25*REGBYTES(sp) - lw x26, 26*REGBYTES(sp) - lw x27, 27*REGBYTES(sp) - lw x28, 28*REGBYTES(sp) - lw x29, 29*REGBYTES(sp) - lw x30, 30*REGBYTES(sp) - lw x31, 31*REGBYTES(sp) + lw s0, 0*REGBYTES(sp) + lw s1, 1*REGBYTES(sp) + lw s2, 2*REGBYTES(sp) + lw s3, 3*REGBYTES(sp) + lw s4, 4*REGBYTES(sp) + lw s5, 5*REGBYTES(sp) + lw s6, 6*REGBYTES(sp) + lw s7, 7*REGBYTES(sp) + lw s8, 8*REGBYTES(sp) + lw s9, 9*REGBYTES(sp) + lw s10, 10*REGBYTES(sp) + lw s11, 11*REGBYTES(sp) + + // caller save + lw ra, 12*REGBYTES(sp) + lw gp, 13*REGBYTES(sp) + lw tp, 14*REGBYTES(sp) + lw t0, 15*REGBYTES(sp) + lw t1, 16*REGBYTES(sp) + lw t2, 17*REGBYTES(sp) + lw t3, 18*REGBYTES(sp) + lw t4, 19*REGBYTES(sp) + lw t5, 20*REGBYTES(sp) + lw t6, 21*REGBYTES(sp) + lw a0, 22*REGBYTES(sp) + lw a1, 23*REGBYTES(sp) + lw a2, 24*REGBYTES(sp) + lw a3, 25*REGBYTES(sp) + lw a4, 26*REGBYTES(sp) + lw a5, 27*REGBYTES(sp) + lw a6, 28*REGBYTES(sp) + lw a7, 29*REGBYTES(sp) + addi sp, sp, 32*REGBYTES @@ -128,44 +133,46 @@ port_sched_start: .type port_context_switch, %function port_context_switch: addi sp, sp, -32*REGBYTES - sw x1, 2*REGBYTES(sp) - sw x3, 3*REGBYTES(sp) - sw x4, 4*REGBYTES(sp) - sw x5, 5*REGBYTES(sp) - sw x6, 6*REGBYTES(sp) - sw x7, 7*REGBYTES(sp) - sw x8, 8*REGBYTES(sp) - sw x9, 9*REGBYTES(sp) - sw x10, 10*REGBYTES(sp) - sw x11, 11*REGBYTES(sp) - sw x12, 12*REGBYTES(sp) - sw x13, 13*REGBYTES(sp) - sw x14, 14*REGBYTES(sp) - sw x15, 15*REGBYTES(sp) - sw x16, 16*REGBYTES(sp) - sw x17, 17*REGBYTES(sp) - sw x18, 18*REGBYTES(sp) - sw x19, 19*REGBYTES(sp) - sw x20, 20*REGBYTES(sp) - sw x21, 21*REGBYTES(sp) - sw x22, 22*REGBYTES(sp) - sw x23, 23*REGBYTES(sp) - sw x24, 24*REGBYTES(sp) - sw x25, 25*REGBYTES(sp) - sw x26, 26*REGBYTES(sp) - sw x27, 27*REGBYTES(sp) - sw x28, 28*REGBYTES(sp) - sw x29, 29*REGBYTES(sp) - sw x30, 30*REGBYTES(sp) - sw x31, 31*REGBYTES(sp) + sw s0, 0*REGBYTES(sp) + sw s1, 1*REGBYTES(sp) + sw s2, 2*REGBYTES(sp) + sw s3, 3*REGBYTES(sp) + sw s4, 4*REGBYTES(sp) + sw s5, 5*REGBYTES(sp) + sw s6, 6*REGBYTES(sp) + sw s7, 7*REGBYTES(sp) + sw s8, 8*REGBYTES(sp) + sw s9, 9*REGBYTES(sp) + sw s10, 10*REGBYTES(sp) + sw s11, 11*REGBYTES(sp) - sw ra, 0*REGBYTES(sp) + // caller save + sw ra, 12*REGBYTES(sp) + sw gp, 13*REGBYTES(sp) + sw tp, 14*REGBYTES(sp) + sw t0, 15*REGBYTES(sp) + sw t1, 16*REGBYTES(sp) + sw t2, 17*REGBYTES(sp) + sw t3, 18*REGBYTES(sp) + sw t4, 19*REGBYTES(sp) + sw t5, 20*REGBYTES(sp) + sw t6, 21*REGBYTES(sp) + sw a0, 22*REGBYTES(sp) + sw a1, 23*REGBYTES(sp) + sw a2, 24*REGBYTES(sp) + sw a3, 25*REGBYTES(sp) + sw a4, 26*REGBYTES(sp) + sw a5, 27*REGBYTES(sp) + sw a6, 28*REGBYTES(sp) + sw a7, 29*REGBYTES(sp) + + sw ra, 30*REGBYTES(sp) csrr t0, mstatus li t1, MSTATUS_MPP or t0, t0, t1 - sw t0, 1*REGBYTES(sp) + sw t0, 31*REGBYTES(sp) // save sp to k_curr_task.sp la t0, k_curr_task // t0 = &k_curr_task @@ -182,43 +189,165 @@ port_context_switch: lw sp, (t1) // restore context - lw t0, 0*REGBYTES(sp) + lw t0, 30*REGBYTES(sp) csrw mepc, t0 - lw t0, 1*REGBYTES(sp) + lw t0, 31*REGBYTES(sp) csrw mstatus, t0 - lw x1, 2*REGBYTES(sp) - lw x3, 3*REGBYTES(sp) - lw x4, 4*REGBYTES(sp) - lw x5, 5*REGBYTES(sp) - lw x6, 6*REGBYTES(sp) - lw x7, 7*REGBYTES(sp) - lw x8, 8*REGBYTES(sp) - lw x9, 9*REGBYTES(sp) - lw x10, 10*REGBYTES(sp) - lw x11, 11*REGBYTES(sp) - lw x12, 12*REGBYTES(sp) - lw x13, 13*REGBYTES(sp) - lw x14, 14*REGBYTES(sp) - lw x15, 15*REGBYTES(sp) - lw x16, 16*REGBYTES(sp) - lw x17, 17*REGBYTES(sp) - lw x18, 18*REGBYTES(sp) - lw x19, 19*REGBYTES(sp) - lw x20, 20*REGBYTES(sp) - lw x21, 21*REGBYTES(sp) - lw x22, 22*REGBYTES(sp) - lw x23, 23*REGBYTES(sp) - lw x24, 24*REGBYTES(sp) - lw x25, 25*REGBYTES(sp) - lw x26, 26*REGBYTES(sp) - lw x27, 27*REGBYTES(sp) - lw x28, 28*REGBYTES(sp) - lw x29, 29*REGBYTES(sp) - lw x30, 30*REGBYTES(sp) - lw x31, 31*REGBYTES(sp) + lw s0, 0*REGBYTES(sp) + lw s1, 1*REGBYTES(sp) + lw s2, 2*REGBYTES(sp) + lw s3, 3*REGBYTES(sp) + lw s4, 4*REGBYTES(sp) + lw s5, 5*REGBYTES(sp) + lw s6, 6*REGBYTES(sp) + lw s7, 7*REGBYTES(sp) + lw s8, 8*REGBYTES(sp) + lw s9, 9*REGBYTES(sp) + lw s10, 10*REGBYTES(sp) + lw s11, 11*REGBYTES(sp) + + // caller save + lw ra, 12*REGBYTES(sp) + lw gp, 13*REGBYTES(sp) + lw tp, 14*REGBYTES(sp) + lw t0, 15*REGBYTES(sp) + lw t1, 16*REGBYTES(sp) + lw t2, 17*REGBYTES(sp) + lw t3, 18*REGBYTES(sp) + lw t4, 19*REGBYTES(sp) + lw t5, 20*REGBYTES(sp) + lw t6, 21*REGBYTES(sp) + lw a0, 22*REGBYTES(sp) + lw a1, 23*REGBYTES(sp) + lw a2, 24*REGBYTES(sp) + lw a3, 25*REGBYTES(sp) + lw a4, 26*REGBYTES(sp) + lw a5, 27*REGBYTES(sp) + lw a6, 28*REGBYTES(sp) + lw a7, 29*REGBYTES(sp) addi sp, sp, 32*REGBYTES mret + + +.align 2 +.global rv32_exception_entry +rv32_exception_entry: + addi sp, sp, -32*REGBYTES + sw s0, 0*REGBYTES(sp) + sw s1, 1*REGBYTES(sp) + sw s2, 2*REGBYTES(sp) + sw s3, 3*REGBYTES(sp) + sw s4, 4*REGBYTES(sp) + sw s5, 5*REGBYTES(sp) + sw s6, 6*REGBYTES(sp) + sw s7, 7*REGBYTES(sp) + sw s8, 8*REGBYTES(sp) + sw s9, 9*REGBYTES(sp) + sw s10, 10*REGBYTES(sp) + sw s11, 11*REGBYTES(sp) + + // caller save + sw ra, 12*REGBYTES(sp) + sw gp, 13*REGBYTES(sp) + sw tp, 14*REGBYTES(sp) + sw t0, 15*REGBYTES(sp) + sw t1, 16*REGBYTES(sp) + sw t2, 17*REGBYTES(sp) + sw t3, 18*REGBYTES(sp) + sw t4, 19*REGBYTES(sp) + sw t5, 20*REGBYTES(sp) + sw t6, 21*REGBYTES(sp) + sw a0, 22*REGBYTES(sp) + sw a1, 23*REGBYTES(sp) + sw a2, 24*REGBYTES(sp) + sw a3, 25*REGBYTES(sp) + sw a4, 26*REGBYTES(sp) + sw a5, 27*REGBYTES(sp) + sw a6, 28*REGBYTES(sp) + sw a7, 29*REGBYTES(sp) + + csrr t0, mepc + sw t0, 30*REGBYTES(sp) + + csrr t0, mstatus + sw t0, 31*REGBYTES(sp) + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t1, (t0) + sw sp, (t1) + + csrr a0, mcause + mv a1, sp + + li t0, SOC_MCAUSE_EXP_MASK + and a0, a0, t0 + call cpu_irq_entry + + la t0, k_curr_task + la t1, k_next_task + + beq t0, t1, irq_restore + + // save sp to k_curr_task.sp + la t0, k_curr_task // t0 = &k_curr_task + lw t2, (t0) // t2 = k_curr_task->sp + sw sp, (t2) // k_curr_task->sp = sp + + // switch task + lw t1, (t1) // t1 = k_next_task + sw t1, (t0) // k_curr_task = k_next_task + + // load new task sp + lw sp, (t1) + +irq_restore: + // restore context + lw t0, 30*REGBYTES(sp) + csrw mepc, t0 + + lw t0, 31*REGBYTES(sp) + csrw mstatus, t0 + + + lw s0, 0*REGBYTES(sp) + lw s1, 1*REGBYTES(sp) + lw s2, 2*REGBYTES(sp) + lw s3, 3*REGBYTES(sp) + lw s4, 4*REGBYTES(sp) + lw s5, 5*REGBYTES(sp) + lw s6, 6*REGBYTES(sp) + lw s7, 7*REGBYTES(sp) + lw s8, 8*REGBYTES(sp) + lw s9, 9*REGBYTES(sp) + lw s10, 10*REGBYTES(sp) + lw s11, 11*REGBYTES(sp) + + // caller save + lw ra, 12*REGBYTES(sp) + lw gp, 13*REGBYTES(sp) + lw tp, 14*REGBYTES(sp) + lw t0, 15*REGBYTES(sp) + lw t1, 16*REGBYTES(sp) + lw t2, 17*REGBYTES(sp) + lw t3, 18*REGBYTES(sp) + lw t4, 19*REGBYTES(sp) + lw t5, 20*REGBYTES(sp) + lw t6, 21*REGBYTES(sp) + lw a0, 22*REGBYTES(sp) + lw a1, 23*REGBYTES(sp) + lw a2, 24*REGBYTES(sp) + lw a3, 25*REGBYTES(sp) + lw a4, 26*REGBYTES(sp) + lw a5, 27*REGBYTES(sp) + lw a6, 28*REGBYTES(sp) + lw a7, 29*REGBYTES(sp) + addi sp, sp, 32*REGBYTES + + mret + + diff --git a/arch/risc-v/spike/gcc/riscv_port.h b/arch/risc-v/spike/gcc/riscv_port.h index 0e5d2f17..383199b7 100644 --- a/arch/risc-v/spike/gcc/riscv_port.h +++ b/arch/risc-v/spike/gcc/riscv_port.h @@ -23,8 +23,12 @@ #define CLINT_MTIMECMP 0x4000 #define CLINT_MTIME 0xBFF8 +#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF + +#ifndef __ASSEMBLER__ void port_cpu_init(); void port_systick_priority_set(uint32_t priority); +#endif /* __ASSEMBLER__ */ -#endif // _RISCV_PORT_H_ +#endif /* _RISCV_PORT_H_ */ diff --git a/board/GD32VF103C_START/eclipse/hello_world/.cproject b/board/GD32VF103C_START/eclipse/hello_world/.cproject index 75158d6b..da3ae3b1 100644 --- a/board/GD32VF103C_START/eclipse/hello_world/.cproject +++ b/board/GD32VF103C_START/eclipse/hello_world/.cproject @@ -105,7 +105,7 @@ - + From b147d060fb8c477b326e98396b289fefcf90ace1 Mon Sep 17 00:00:00 2001 From: acevest Date: Sun, 6 Oct 2019 15:51:34 +0800 Subject: [PATCH 5/6] save 48bytes when no need to switch task in interrupt handler --- arch/risc-v/common/tos_cpu.c | 2 +- arch/risc-v/rv32i/gcc/port_s.S | 140 +++++++++++------------- arch/risc-v/spike/gcc/riscv_port_s.S | 118 -------------------- board/QEMU_Spike/GCC/demo/Makefile | 1 - board/QEMU_Spike/GCC/demo/start.S | 3 +- board/QEMU_Spike/eclipse/demo/.cproject | 2 +- board/QEMU_Spike/eclipse/demo/start.S | 4 +- 7 files changed, 72 insertions(+), 198 deletions(-) delete mode 100644 arch/risc-v/spike/gcc/riscv_port_s.S diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c index 63b16389..276c85f3 100644 --- a/arch/risc-v/common/tos_cpu.c +++ b/arch/risc-v/common/tos_cpu.c @@ -129,7 +129,7 @@ void SysTick_IRQHandler() { } } -void cpu_irq_entry(cpu_data_t irq, cpu_context_t *regs) +void cpu_irq_entry(cpu_data_t irq) { if (irq != 7) { return; diff --git a/arch/risc-v/rv32i/gcc/port_s.S b/arch/risc-v/rv32i/gcc/port_s.S index 821f4510..2f25139a 100644 --- a/arch/risc-v/rv32i/gcc/port_s.S +++ b/arch/risc-v/rv32i/gcc/port_s.S @@ -12,10 +12,10 @@ .global port_sched_start .global port_context_switch +.global rv32_exception_entry .extern k_curr_task .extern k_next_task -.extern k_task_irq_switch_flag .equ MSTATUS_MIE, 0x00000008 .equ MSTATUS_MPP, 0x00001800 @@ -236,7 +236,43 @@ port_context_switch: .align 2 .global rv32_exception_entry rv32_exception_entry: - addi sp, sp, -32*REGBYTES + addi sp, sp, -20*REGBYTES + sw ra, (12-12)*REGBYTES(sp) + sw gp, (13-12)*REGBYTES(sp) + sw tp, (14-12)*REGBYTES(sp) + sw t0, (15-12)*REGBYTES(sp) + sw t1, (16-12)*REGBYTES(sp) + sw t2, (17-12)*REGBYTES(sp) + sw t3, (18-12)*REGBYTES(sp) + sw t4, (19-12)*REGBYTES(sp) + sw t5, (20-12)*REGBYTES(sp) + sw t6, (21-12)*REGBYTES(sp) + sw a0, (22-12)*REGBYTES(sp) + sw a1, (23-12)*REGBYTES(sp) + sw a2, (24-12)*REGBYTES(sp) + sw a3, (25-12)*REGBYTES(sp) + sw a4, (26-12)*REGBYTES(sp) + sw a5, (27-12)*REGBYTES(sp) + sw a6, (28-12)*REGBYTES(sp) + sw a7, (29-12)*REGBYTES(sp) + + csrr t0, mepc + sw t0, (30-12)*REGBYTES(sp) + + csrr t0, mstatus + sw t0, (31-12)*REGBYTES(sp) + + // get irq num and call irq handler + li t0, SOC_MCAUSE_EXP_MASK + csrr a0, mcause + and a0, a0, t0 + call cpu_irq_entry + + la t0, k_curr_task + la t1, k_next_task + + beq t0, t1, irq_restore + addi sp, sp, -12*REGBYTES sw s0, 0*REGBYTES(sp) sw s1, 1*REGBYTES(sp) sw s2, 2*REGBYTES(sp) @@ -250,49 +286,6 @@ rv32_exception_entry: sw s10, 10*REGBYTES(sp) sw s11, 11*REGBYTES(sp) - // caller save - sw ra, 12*REGBYTES(sp) - sw gp, 13*REGBYTES(sp) - sw tp, 14*REGBYTES(sp) - sw t0, 15*REGBYTES(sp) - sw t1, 16*REGBYTES(sp) - sw t2, 17*REGBYTES(sp) - sw t3, 18*REGBYTES(sp) - sw t4, 19*REGBYTES(sp) - sw t5, 20*REGBYTES(sp) - sw t6, 21*REGBYTES(sp) - sw a0, 22*REGBYTES(sp) - sw a1, 23*REGBYTES(sp) - sw a2, 24*REGBYTES(sp) - sw a3, 25*REGBYTES(sp) - sw a4, 26*REGBYTES(sp) - sw a5, 27*REGBYTES(sp) - sw a6, 28*REGBYTES(sp) - sw a7, 29*REGBYTES(sp) - - csrr t0, mepc - sw t0, 30*REGBYTES(sp) - - csrr t0, mstatus - sw t0, 31*REGBYTES(sp) - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - lw t1, (t0) - sw sp, (t1) - - csrr a0, mcause - mv a1, sp - - li t0, SOC_MCAUSE_EXP_MASK - and a0, a0, t0 - call cpu_irq_entry - - la t0, k_curr_task - la t1, k_next_task - - beq t0, t1, irq_restore - // save sp to k_curr_task.sp la t0, k_curr_task // t0 = &k_curr_task lw t2, (t0) // t2 = k_curr_task->sp @@ -305,15 +298,6 @@ rv32_exception_entry: // load new task sp lw sp, (t1) -irq_restore: - // restore context - lw t0, 30*REGBYTES(sp) - csrw mepc, t0 - - lw t0, 31*REGBYTES(sp) - csrw mstatus, t0 - - lw s0, 0*REGBYTES(sp) lw s1, 1*REGBYTES(sp) lw s2, 2*REGBYTES(sp) @@ -326,27 +310,35 @@ irq_restore: lw s9, 9*REGBYTES(sp) lw s10, 10*REGBYTES(sp) lw s11, 11*REGBYTES(sp) + addi sp, sp, 12*REGBYTES - // caller save - lw ra, 12*REGBYTES(sp) - lw gp, 13*REGBYTES(sp) - lw tp, 14*REGBYTES(sp) - lw t0, 15*REGBYTES(sp) - lw t1, 16*REGBYTES(sp) - lw t2, 17*REGBYTES(sp) - lw t3, 18*REGBYTES(sp) - lw t4, 19*REGBYTES(sp) - lw t5, 20*REGBYTES(sp) - lw t6, 21*REGBYTES(sp) - lw a0, 22*REGBYTES(sp) - lw a1, 23*REGBYTES(sp) - lw a2, 24*REGBYTES(sp) - lw a3, 25*REGBYTES(sp) - lw a4, 26*REGBYTES(sp) - lw a5, 27*REGBYTES(sp) - lw a6, 28*REGBYTES(sp) - lw a7, 29*REGBYTES(sp) - addi sp, sp, 32*REGBYTES +irq_restore: + // restore context + lw t0, (30-12)*REGBYTES(sp) + csrw mepc, t0 + + lw t0, (31-12)*REGBYTES(sp) + csrw mstatus, t0 + + lw ra, (12-12)*REGBYTES(sp) + lw gp, (13-12)*REGBYTES(sp) + lw tp, (14-12)*REGBYTES(sp) + lw t0, (15-12)*REGBYTES(sp) + lw t1, (16-12)*REGBYTES(sp) + lw t2, (17-12)*REGBYTES(sp) + lw t3, (18-12)*REGBYTES(sp) + lw t4, (19-12)*REGBYTES(sp) + lw t5, (20-12)*REGBYTES(sp) + lw t6, (21-12)*REGBYTES(sp) + lw a0, (22-12)*REGBYTES(sp) + lw a1, (23-12)*REGBYTES(sp) + lw a2, (24-12)*REGBYTES(sp) + lw a3, (25-12)*REGBYTES(sp) + lw a4, (26-12)*REGBYTES(sp) + lw a5, (27-12)*REGBYTES(sp) + lw a6, (28-12)*REGBYTES(sp) + lw a7, (29-12)*REGBYTES(sp) + addi sp, sp, 20*REGBYTES mret diff --git a/arch/risc-v/spike/gcc/riscv_port_s.S b/arch/risc-v/spike/gcc/riscv_port_s.S deleted file mode 100644 index 925889eb..00000000 --- a/arch/risc-v/spike/gcc/riscv_port_s.S +++ /dev/null @@ -1,118 +0,0 @@ -#include "port.h" - -.align 2 -.global rv32_trap_entry -rv32_trap_entry: - addi sp, sp, -32*REGBYTES - sw x1, 2*REGBYTES(sp) - sw x3, 3*REGBYTES(sp) - sw x4, 4*REGBYTES(sp) - sw x5, 5*REGBYTES(sp) - sw x6, 6*REGBYTES(sp) - sw x7, 7*REGBYTES(sp) - sw x8, 8*REGBYTES(sp) - sw x9, 9*REGBYTES(sp) - sw x10, 10*REGBYTES(sp) - sw x11, 11*REGBYTES(sp) - sw x12, 12*REGBYTES(sp) - sw x13, 13*REGBYTES(sp) - sw x14, 14*REGBYTES(sp) - sw x15, 15*REGBYTES(sp) - sw x16, 16*REGBYTES(sp) - sw x17, 17*REGBYTES(sp) - sw x18, 18*REGBYTES(sp) - sw x19, 19*REGBYTES(sp) - sw x20, 20*REGBYTES(sp) - sw x21, 21*REGBYTES(sp) - sw x22, 22*REGBYTES(sp) - sw x23, 23*REGBYTES(sp) - sw x24, 24*REGBYTES(sp) - sw x25, 25*REGBYTES(sp) - sw x26, 26*REGBYTES(sp) - sw x27, 27*REGBYTES(sp) - sw x28, 28*REGBYTES(sp) - sw x29, 29*REGBYTES(sp) - sw x30, 30*REGBYTES(sp) - sw x31, 31*REGBYTES(sp) - - csrr t0, mepc - sw t0, 0*REGBYTES(sp) - - csrr t0, mstatus - sw t0, 1*REGBYTES(sp) - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - lw t1, (t0) - sw sp, (t1) - - csrr a0, mcause - mv a1, sp - bltz a0, handle_irq - call cpu_trap_entry - j irq_restore - -handle_irq: - slli a0, a0, 1 - srli a0, a0, 1 - call cpu_irq_entry - - la t0, k_curr_task - la t1, k_next_task - - beq t0, t1, irq_restore - - // save sp to k_curr_task.sp - la t0, k_curr_task // t0 = &k_curr_task - lw t2, (t0) - sw sp, (t2) - - // switch task - lw t1, (t1) // t1 = k_next_task - sw t1, (t0) // k_curr_task = k_next_task - - // load new task sp - lw sp, (t1) - -irq_restore: - // restore context - lw t0, 0*REGBYTES(sp) - csrw mepc, t0 - - lw t0, 1*REGBYTES(sp) - csrw mstatus, t0 - - lw x1, 2*REGBYTES(sp) - lw x3, 3*REGBYTES(sp) - lw x4, 4*REGBYTES(sp) - lw x5, 5*REGBYTES(sp) - lw x6, 6*REGBYTES(sp) - lw x7, 7*REGBYTES(sp) - lw x8, 8*REGBYTES(sp) - lw x9, 9*REGBYTES(sp) - lw x10, 10*REGBYTES(sp) - lw x11, 11*REGBYTES(sp) - lw x12, 12*REGBYTES(sp) - lw x13, 13*REGBYTES(sp) - lw x14, 14*REGBYTES(sp) - lw x15, 15*REGBYTES(sp) - lw x16, 16*REGBYTES(sp) - lw x17, 17*REGBYTES(sp) - lw x18, 18*REGBYTES(sp) - lw x19, 19*REGBYTES(sp) - lw x20, 20*REGBYTES(sp) - lw x21, 21*REGBYTES(sp) - lw x22, 22*REGBYTES(sp) - lw x23, 23*REGBYTES(sp) - lw x24, 24*REGBYTES(sp) - lw x25, 25*REGBYTES(sp) - lw x26, 26*REGBYTES(sp) - lw x27, 27*REGBYTES(sp) - lw x28, 28*REGBYTES(sp) - lw x29, 29*REGBYTES(sp) - lw x30, 30*REGBYTES(sp) - lw x31, 31*REGBYTES(sp) - - addi sp, sp, 32*REGBYTES - - mret diff --git a/board/QEMU_Spike/GCC/demo/Makefile b/board/QEMU_Spike/GCC/demo/Makefile index 703b6eaa..6d015d6b 100644 --- a/board/QEMU_Spike/GCC/demo/Makefile +++ b/board/QEMU_Spike/GCC/demo/Makefile @@ -54,7 +54,6 @@ ASM_SOURCES = ASM_SOURCES_S = \ $(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \ -$(TOP_DIR)/arch/risc-v/spike/gcc/riscv_port_s.S \ start.S diff --git a/board/QEMU_Spike/GCC/demo/start.S b/board/QEMU_Spike/GCC/demo/start.S index b4f89008..4704d0ed 100644 --- a/board/QEMU_Spike/GCC/demo/start.S +++ b/board/QEMU_Spike/GCC/demo/start.S @@ -1,3 +1,4 @@ +.extern rv32_exception_entry .align 2 .section .text.entry .globl _start @@ -6,7 +7,7 @@ _start: csrc mstatus, 0x00000008 csrw mie, 0 - la t0, rv32_trap_entry + la t0, rv32_exception_entry csrw mtvec, t0 la sp, _stack_top diff --git a/board/QEMU_Spike/eclipse/demo/.cproject b/board/QEMU_Spike/eclipse/demo/.cproject index a892e24a..cad83a20 100644 --- a/board/QEMU_Spike/eclipse/demo/.cproject +++ b/board/QEMU_Spike/eclipse/demo/.cproject @@ -111,7 +111,7 @@ - + diff --git a/board/QEMU_Spike/eclipse/demo/start.S b/board/QEMU_Spike/eclipse/demo/start.S index 4a18fd96..435fc6c6 100644 --- a/board/QEMU_Spike/eclipse/demo/start.S +++ b/board/QEMU_Spike/eclipse/demo/start.S @@ -1,4 +1,4 @@ -.extern rv32_trap_entry +.extern rv32_exception_entry .align 2 .section .text.entry @@ -8,7 +8,7 @@ _start: csrc mstatus, 0x00000008 csrw mie, 0 - la t0, rv32_trap_entry + la t0, rv32_exception_entry csrw mtvec, t0 la sp, _stack_top From 41ad2d711e09ad28c8da02e20cc2657d3d306f82 Mon Sep 17 00:00:00 2001 From: acevest Date: Tue, 8 Oct 2019 14:42:58 +0800 Subject: [PATCH 6/6] adjust the order of registers on the stack --- arch/risc-v/common/include/tos_cpu.h | 70 +++-- arch/risc-v/common/tos_cpu.c | 4 +- arch/risc-v/rv32i/gcc/port_s.S | 412 +++++++++++++++------------ 3 files changed, 268 insertions(+), 218 deletions(-) diff --git a/arch/risc-v/common/include/tos_cpu.h b/arch/risc-v/common/include/tos_cpu.h index 783672ca..0ee8abbb 100644 --- a/arch/risc-v/common/include/tos_cpu.h +++ b/arch/risc-v/common/include/tos_cpu.h @@ -2,47 +2,41 @@ #define _TOS_CPU_H_ typedef struct cpu_context_st { - union { cpu_data_t s0, x8, fp; }; - union { cpu_data_t s1, x9; }; - union { cpu_data_t s2, x18; }; - union { cpu_data_t s3, x19; }; - union { cpu_data_t s4, x20; }; - union { cpu_data_t s5, x21; }; - union { cpu_data_t s6, x22; }; - union { cpu_data_t s7, x23; }; - union { cpu_data_t s8, x24; }; - union { cpu_data_t s9, x25; }; - union { cpu_data_t s10,x26; }; - union { cpu_data_t s11,x27; }; - - // caller save - union { cpu_data_t ra, x1; }; - - union { cpu_data_t gp, x3; }; - union { cpu_data_t tp, x4; }; - - union { cpu_data_t t0, x5; }; - union { cpu_data_t t1, x6; }; - union { cpu_data_t t2, x7; }; - union { cpu_data_t t3, x28; }; - union { cpu_data_t t4, x29; }; - union { cpu_data_t t5, x30; }; - union { cpu_data_t t6, x31; }; - - union { cpu_data_t a0, x10; }; - union { cpu_data_t a1, x11; }; - - union { cpu_data_t a2, x12; }; - union { cpu_data_t a3, x13; }; - union { cpu_data_t a4, x14; }; - union { cpu_data_t a5, x15; }; - union { cpu_data_t a6, x16; }; - union { cpu_data_t a7, x17; }; - - cpu_data_t epc; + cpu_data_t mepc; cpu_data_t mstatus; + union { cpu_data_t x1, ra; }; + union { cpu_data_t x3, gp; }; + union { cpu_data_t x4, tp; }; + union { cpu_data_t x5, t0; }; + union { cpu_data_t x6, t1; }; + union { cpu_data_t x7, t2; }; + union { cpu_data_t x8, s0, fp; }; + union { cpu_data_t x9, s1; }; + union { cpu_data_t x10, a0; }; + union { cpu_data_t x11, a1; }; + union { cpu_data_t x12, a2; }; + union { cpu_data_t x13, a3; }; + union { cpu_data_t x14, a4; }; + union { cpu_data_t x15, a5; }; + union { cpu_data_t x16, a6; }; + union { cpu_data_t x17, a7; }; + union { cpu_data_t x18, s2; }; + union { cpu_data_t x19, s3; }; + union { cpu_data_t x20, s4; }; + union { cpu_data_t x21, s5; }; + union { cpu_data_t x22, s6; }; + union { cpu_data_t x23, s7; }; + union { cpu_data_t x24, s8; }; + union { cpu_data_t x25, s9; }; + union { cpu_data_t x26, s10; }; + union { cpu_data_t x27, s11; }; + union { cpu_data_t x28, t3; }; + union { cpu_data_t x29, t4; }; + union { cpu_data_t x30, t5; }; + union { cpu_data_t x31, t6; }; } cpu_context_t; + __API__ uint32_t tos_cpu_clz(uint32_t val); __API__ void tos_cpu_int_disable(void); diff --git a/arch/risc-v/common/tos_cpu.c b/arch/risc-v/common/tos_cpu.c index 276c85f3..3ae8f0ef 100644 --- a/arch/risc-v/common/tos_cpu.c +++ b/arch/risc-v/common/tos_cpu.c @@ -74,7 +74,7 @@ Inx Offset Register 03 012 x3 gp 02 008 x1 ra 01 004 mstatus -00 000 epc +00 000 mepc */ @@ -107,7 +107,7 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, regs->a0 = (cpu_data_t)arg; // a0: argument regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt - regs->epc = (cpu_data_t)entry; + regs->mepc = (cpu_data_t)entry; return (k_stack_t*)sp; diff --git a/arch/risc-v/rv32i/gcc/port_s.S b/arch/risc-v/rv32i/gcc/port_s.S index 2f25139a..278cc199 100644 --- a/arch/risc-v/rv32i/gcc/port_s.S +++ b/arch/risc-v/rv32i/gcc/port_s.S @@ -24,8 +24,6 @@ .equ MIP_MTIP, (1 << 7) // machine mode timer interrupt pending -.equ REGBYTES, 4 - .text .align 2 @@ -67,6 +65,75 @@ port_systick_pending_reset: csrc mip, t0 ret + +#define __reg_mepc_OFFSET 0x00 +#define __reg_mstatus_OFFSET 0x04 +#define __reg_x1_OFFSET 0x08 +#define __reg_x3_OFFSET 0x0C +#define __reg_x4_OFFSET 0x10 +#define __reg_x5_OFFSET 0x14 +#define __reg_x6_OFFSET 0x18 +#define __reg_x7_OFFSET 0x1C +#define __reg_x8_OFFSET 0x20 +#define __reg_x9_OFFSET 0x24 +#define __reg_x10_OFFSET 0x28 +#define __reg_x11_OFFSET 0x2C +#define __reg_x12_OFFSET 0x30 +#define __reg_x13_OFFSET 0x34 +#define __reg_x14_OFFSET 0x38 +#define __reg_x15_OFFSET 0x3C +#define __reg_x16_OFFSET 0x40 +#define __reg_x17_OFFSET 0x44 +#define __reg_x18_OFFSET 0x48 +#define __reg_x19_OFFSET 0x4C +#define __reg_x20_OFFSET 0x50 +#define __reg_x21_OFFSET 0x54 +#define __reg_x22_OFFSET 0x58 +#define __reg_x23_OFFSET 0x5C +#define __reg_x24_OFFSET 0x60 +#define __reg_x25_OFFSET 0x64 +#define __reg_x26_OFFSET 0x68 +#define __reg_x27_OFFSET 0x6C +#define __reg_x28_OFFSET 0x70 +#define __reg_x29_OFFSET 0x74 +#define __reg_x30_OFFSET 0x78 +#define __reg_x31_OFFSET 0x7C + +#define __reg_mepc__OFFSET __reg_mepc_OFFSET +#define __reg_mstatus__OFFSET __reg_mstatus_OFFSET +#define __reg_ra__OFFSET __reg_x1_OFFSET +#define __reg_gp__OFFSET __reg_x3_OFFSET +#define __reg_tp__OFFSET __reg_x4_OFFSET +#define __reg_t0__OFFSET __reg_x5_OFFSET +#define __reg_t1__OFFSET __reg_x6_OFFSET +#define __reg_t2__OFFSET __reg_x7_OFFSET +#define __reg_s0__OFFSET __reg_x8_OFFSET +#define __reg_fp__OFFSET __reg_x8_OFFSET +#define __reg_s1__OFFSET __reg_x9_OFFSET +#define __reg_a0__OFFSET __reg_x10_OFFSET +#define __reg_a1__OFFSET __reg_x11_OFFSET +#define __reg_a2__OFFSET __reg_x12_OFFSET +#define __reg_a3__OFFSET __reg_x13_OFFSET +#define __reg_a4__OFFSET __reg_x14_OFFSET +#define __reg_a5__OFFSET __reg_x15_OFFSET +#define __reg_a6__OFFSET __reg_x16_OFFSET +#define __reg_a7__OFFSET __reg_x17_OFFSET +#define __reg_s2__OFFSET __reg_x18_OFFSET +#define __reg_s3__OFFSET __reg_x19_OFFSET +#define __reg_s4__OFFSET __reg_x20_OFFSET +#define __reg_s5__OFFSET __reg_x21_OFFSET +#define __reg_s6__OFFSET __reg_x22_OFFSET +#define __reg_s7__OFFSET __reg_x23_OFFSET +#define __reg_s8__OFFSET __reg_x24_OFFSET +#define __reg_s9__OFFSET __reg_x25_OFFSET +#define __reg_s10__OFFSET __reg_x26_OFFSET +#define __reg_s11__OFFSET __reg_x27_OFFSET +#define __reg_t3__OFFSET __reg_x28_OFFSET +#define __reg_t4__OFFSET __reg_x29_OFFSET +#define __reg_t5__OFFSET __reg_x30_OFFSET +#define __reg_t6__OFFSET __reg_x31_OFFSET + + .align 2 .type port_sched_start, %function port_sched_start: @@ -80,51 +147,47 @@ port_sched_start: lw sp, (t0) // sp = k_curr_task->sp // save sp to stack - addi t1, sp, 32*REGBYTES + addi t1, sp, 128 sw t1, (t0) // restore context - lw t0, 30*REGBYTES(sp) + lw t0, __reg_mepc__OFFSET(sp) csrw mepc, t0 - lw t0, 31*REGBYTES(sp) + lw t0, __reg_mstatus__OFFSET(sp) csrw mstatus, t0 - lw s0, 0*REGBYTES(sp) - lw s1, 1*REGBYTES(sp) - lw s2, 2*REGBYTES(sp) - lw s3, 3*REGBYTES(sp) - lw s4, 4*REGBYTES(sp) - lw s5, 5*REGBYTES(sp) - lw s6, 6*REGBYTES(sp) - lw s7, 7*REGBYTES(sp) - lw s8, 8*REGBYTES(sp) - lw s9, 9*REGBYTES(sp) - lw s10, 10*REGBYTES(sp) - lw s11, 11*REGBYTES(sp) + lw x3, __reg_x3_OFFSET(sp) + lw x4, __reg_x4_OFFSET(sp) + lw x5, __reg_x5_OFFSET(sp) + lw x6, __reg_x6_OFFSET(sp) + lw x7, __reg_x7_OFFSET(sp) + lw x8, __reg_x8_OFFSET(sp) + lw x9, __reg_x9_OFFSET(sp) + lw x10, __reg_x10_OFFSET(sp) + lw x11, __reg_x11_OFFSET(sp) + lw x12, __reg_x12_OFFSET(sp) + lw x13, __reg_x13_OFFSET(sp) + lw x14, __reg_x14_OFFSET(sp) + lw x15, __reg_x15_OFFSET(sp) + lw x16, __reg_x16_OFFSET(sp) + lw x17, __reg_x17_OFFSET(sp) + lw x18, __reg_x18_OFFSET(sp) + lw x19, __reg_x19_OFFSET(sp) + lw x20, __reg_x20_OFFSET(sp) + lw x21, __reg_x21_OFFSET(sp) + lw x22, __reg_x22_OFFSET(sp) + lw x23, __reg_x23_OFFSET(sp) + lw x24, __reg_x24_OFFSET(sp) + lw x25, __reg_x25_OFFSET(sp) + lw x26, __reg_x26_OFFSET(sp) + lw x27, __reg_x27_OFFSET(sp) + lw x28, __reg_x28_OFFSET(sp) + lw x29, __reg_x29_OFFSET(sp) + lw x30, __reg_x30_OFFSET(sp) + lw x31, __reg_x31_OFFSET(sp) - // caller save - lw ra, 12*REGBYTES(sp) - lw gp, 13*REGBYTES(sp) - lw tp, 14*REGBYTES(sp) - lw t0, 15*REGBYTES(sp) - lw t1, 16*REGBYTES(sp) - lw t2, 17*REGBYTES(sp) - lw t3, 18*REGBYTES(sp) - lw t4, 19*REGBYTES(sp) - lw t5, 20*REGBYTES(sp) - lw t6, 21*REGBYTES(sp) - lw a0, 22*REGBYTES(sp) - lw a1, 23*REGBYTES(sp) - lw a2, 24*REGBYTES(sp) - lw a3, 25*REGBYTES(sp) - lw a4, 26*REGBYTES(sp) - lw a5, 27*REGBYTES(sp) - lw a6, 28*REGBYTES(sp) - lw a7, 29*REGBYTES(sp) - - - addi sp, sp, 32*REGBYTES + addi sp, sp, 128 mret @@ -132,47 +195,44 @@ port_sched_start: .align 2 .type port_context_switch, %function port_context_switch: - addi sp, sp, -32*REGBYTES + addi sp, sp, -128 + sw x3, __reg_x3_OFFSET(sp) + sw x4, __reg_x4_OFFSET(sp) + sw x5, __reg_x5_OFFSET(sp) + sw x6, __reg_x6_OFFSET(sp) + sw x7, __reg_x7_OFFSET(sp) + sw x8, __reg_x8_OFFSET(sp) + sw x9, __reg_x9_OFFSET(sp) + sw x10, __reg_x10_OFFSET(sp) + sw x11, __reg_x11_OFFSET(sp) + sw x12, __reg_x12_OFFSET(sp) + sw x13, __reg_x13_OFFSET(sp) + sw x14, __reg_x14_OFFSET(sp) + sw x15, __reg_x15_OFFSET(sp) + sw x16, __reg_x16_OFFSET(sp) + sw x17, __reg_x17_OFFSET(sp) + sw x18, __reg_x18_OFFSET(sp) + sw x19, __reg_x19_OFFSET(sp) + sw x20, __reg_x20_OFFSET(sp) + sw x21, __reg_x21_OFFSET(sp) + sw x22, __reg_x22_OFFSET(sp) + sw x23, __reg_x23_OFFSET(sp) + sw x24, __reg_x24_OFFSET(sp) + sw x25, __reg_x25_OFFSET(sp) + sw x26, __reg_x26_OFFSET(sp) + sw x27, __reg_x27_OFFSET(sp) + sw x28, __reg_x28_OFFSET(sp) + sw x29, __reg_x29_OFFSET(sp) + sw x30, __reg_x30_OFFSET(sp) + sw x31, __reg_x31_OFFSET(sp) - sw s0, 0*REGBYTES(sp) - sw s1, 1*REGBYTES(sp) - sw s2, 2*REGBYTES(sp) - sw s3, 3*REGBYTES(sp) - sw s4, 4*REGBYTES(sp) - sw s5, 5*REGBYTES(sp) - sw s6, 6*REGBYTES(sp) - sw s7, 7*REGBYTES(sp) - sw s8, 8*REGBYTES(sp) - sw s9, 9*REGBYTES(sp) - sw s10, 10*REGBYTES(sp) - sw s11, 11*REGBYTES(sp) - // caller save - sw ra, 12*REGBYTES(sp) - sw gp, 13*REGBYTES(sp) - sw tp, 14*REGBYTES(sp) - sw t0, 15*REGBYTES(sp) - sw t1, 16*REGBYTES(sp) - sw t2, 17*REGBYTES(sp) - sw t3, 18*REGBYTES(sp) - sw t4, 19*REGBYTES(sp) - sw t5, 20*REGBYTES(sp) - sw t6, 21*REGBYTES(sp) - sw a0, 22*REGBYTES(sp) - sw a1, 23*REGBYTES(sp) - sw a2, 24*REGBYTES(sp) - sw a3, 25*REGBYTES(sp) - sw a4, 26*REGBYTES(sp) - sw a5, 27*REGBYTES(sp) - sw a6, 28*REGBYTES(sp) - sw a7, 29*REGBYTES(sp) - - sw ra, 30*REGBYTES(sp) + sw ra, __reg_mepc_OFFSET(sp) csrr t0, mstatus li t1, MSTATUS_MPP or t0, t0, t1 - sw t0, 31*REGBYTES(sp) + sw t0, __reg_mstatus_OFFSET(sp) // save sp to k_curr_task.sp la t0, k_curr_task // t0 = &k_curr_task @@ -189,46 +249,43 @@ port_context_switch: lw sp, (t1) // restore context - lw t0, 30*REGBYTES(sp) + lw t0, __reg_mepc_OFFSET(sp) csrw mepc, t0 - lw t0, 31*REGBYTES(sp) + lw t0, __reg_mstatus_OFFSET(sp) csrw mstatus, t0 + lw x3, __reg_x3_OFFSET(sp) + lw x4, __reg_x4_OFFSET(sp) + lw x5, __reg_x5_OFFSET(sp) + lw x6, __reg_x6_OFFSET(sp) + lw x7, __reg_x7_OFFSET(sp) + lw x8, __reg_x8_OFFSET(sp) + lw x9, __reg_x9_OFFSET(sp) + lw x10, __reg_x10_OFFSET(sp) + lw x11, __reg_x11_OFFSET(sp) + lw x12, __reg_x12_OFFSET(sp) + lw x13, __reg_x13_OFFSET(sp) + lw x14, __reg_x14_OFFSET(sp) + lw x15, __reg_x15_OFFSET(sp) + lw x16, __reg_x16_OFFSET(sp) + lw x17, __reg_x17_OFFSET(sp) + lw x18, __reg_x18_OFFSET(sp) + lw x19, __reg_x19_OFFSET(sp) + lw x20, __reg_x20_OFFSET(sp) + lw x21, __reg_x21_OFFSET(sp) + lw x22, __reg_x22_OFFSET(sp) + lw x23, __reg_x23_OFFSET(sp) + lw x24, __reg_x24_OFFSET(sp) + lw x25, __reg_x25_OFFSET(sp) + lw x26, __reg_x26_OFFSET(sp) + lw x27, __reg_x27_OFFSET(sp) + lw x28, __reg_x28_OFFSET(sp) + lw x29, __reg_x29_OFFSET(sp) + lw x30, __reg_x30_OFFSET(sp) + lw x31, __reg_x31_OFFSET(sp) - lw s0, 0*REGBYTES(sp) - lw s1, 1*REGBYTES(sp) - lw s2, 2*REGBYTES(sp) - lw s3, 3*REGBYTES(sp) - lw s4, 4*REGBYTES(sp) - lw s5, 5*REGBYTES(sp) - lw s6, 6*REGBYTES(sp) - lw s7, 7*REGBYTES(sp) - lw s8, 8*REGBYTES(sp) - lw s9, 9*REGBYTES(sp) - lw s10, 10*REGBYTES(sp) - lw s11, 11*REGBYTES(sp) - - // caller save - lw ra, 12*REGBYTES(sp) - lw gp, 13*REGBYTES(sp) - lw tp, 14*REGBYTES(sp) - lw t0, 15*REGBYTES(sp) - lw t1, 16*REGBYTES(sp) - lw t2, 17*REGBYTES(sp) - lw t3, 18*REGBYTES(sp) - lw t4, 19*REGBYTES(sp) - lw t5, 20*REGBYTES(sp) - lw t6, 21*REGBYTES(sp) - lw a0, 22*REGBYTES(sp) - lw a1, 23*REGBYTES(sp) - lw a2, 24*REGBYTES(sp) - lw a3, 25*REGBYTES(sp) - lw a4, 26*REGBYTES(sp) - lw a5, 27*REGBYTES(sp) - lw a6, 28*REGBYTES(sp) - lw a7, 29*REGBYTES(sp) - addi sp, sp, 32*REGBYTES + addi sp, sp, 128 mret @@ -236,31 +293,32 @@ port_context_switch: .align 2 .global rv32_exception_entry rv32_exception_entry: - addi sp, sp, -20*REGBYTES - sw ra, (12-12)*REGBYTES(sp) - sw gp, (13-12)*REGBYTES(sp) - sw tp, (14-12)*REGBYTES(sp) - sw t0, (15-12)*REGBYTES(sp) - sw t1, (16-12)*REGBYTES(sp) - sw t2, (17-12)*REGBYTES(sp) - sw t3, (18-12)*REGBYTES(sp) - sw t4, (19-12)*REGBYTES(sp) - sw t5, (20-12)*REGBYTES(sp) - sw t6, (21-12)*REGBYTES(sp) - sw a0, (22-12)*REGBYTES(sp) - sw a1, (23-12)*REGBYTES(sp) - sw a2, (24-12)*REGBYTES(sp) - sw a3, (25-12)*REGBYTES(sp) - sw a4, (26-12)*REGBYTES(sp) - sw a5, (27-12)*REGBYTES(sp) - sw a6, (28-12)*REGBYTES(sp) - sw a7, (29-12)*REGBYTES(sp) + addi sp, sp, -128 + + sw ra, __reg_ra__OFFSET(sp) + sw gp, __reg_gp__OFFSET(sp) + sw tp, __reg_tp__OFFSET(sp) + sw t0, __reg_t0__OFFSET(sp) + sw t1, __reg_t1__OFFSET(sp) + sw t2, __reg_t2__OFFSET(sp) + sw t3, __reg_t3__OFFSET(sp) + sw t4, __reg_t4__OFFSET(sp) + sw t5, __reg_t5__OFFSET(sp) + sw t6, __reg_t6__OFFSET(sp) + sw a0, __reg_a0__OFFSET(sp) + sw a1, __reg_a1__OFFSET(sp) + sw a2, __reg_a2__OFFSET(sp) + sw a3, __reg_a3__OFFSET(sp) + sw a4, __reg_a4__OFFSET(sp) + sw a5, __reg_a5__OFFSET(sp) + sw a6, __reg_a6__OFFSET(sp) + sw a7, __reg_a7__OFFSET(sp) csrr t0, mepc - sw t0, (30-12)*REGBYTES(sp) + sw t0, __reg_mepc__OFFSET(sp) csrr t0, mstatus - sw t0, (31-12)*REGBYTES(sp) + sw t0, __reg_mstatus__OFFSET(sp) // get irq num and call irq handler li t0, SOC_MCAUSE_EXP_MASK @@ -272,19 +330,19 @@ rv32_exception_entry: la t1, k_next_task beq t0, t1, irq_restore - addi sp, sp, -12*REGBYTES - sw s0, 0*REGBYTES(sp) - sw s1, 1*REGBYTES(sp) - sw s2, 2*REGBYTES(sp) - sw s3, 3*REGBYTES(sp) - sw s4, 4*REGBYTES(sp) - sw s5, 5*REGBYTES(sp) - sw s6, 6*REGBYTES(sp) - sw s7, 7*REGBYTES(sp) - sw s8, 8*REGBYTES(sp) - sw s9, 9*REGBYTES(sp) - sw s10, 10*REGBYTES(sp) - sw s11, 11*REGBYTES(sp) + + sw s0, __reg_s0__OFFSET(sp) + sw s1, __reg_s1__OFFSET(sp) + sw s2, __reg_s2__OFFSET(sp) + sw s3, __reg_s3__OFFSET(sp) + sw s4, __reg_s4__OFFSET(sp) + sw s5, __reg_s5__OFFSET(sp) + sw s6, __reg_s6__OFFSET(sp) + sw s7, __reg_s7__OFFSET(sp) + sw s8, __reg_s8__OFFSET(sp) + sw s9, __reg_s9__OFFSET(sp) + sw s10, __reg_s10__OFFSET(sp) + sw s11, __reg_s11__OFFSET(sp) // save sp to k_curr_task.sp la t0, k_curr_task // t0 = &k_curr_task @@ -298,47 +356,45 @@ rv32_exception_entry: // load new task sp lw sp, (t1) - lw s0, 0*REGBYTES(sp) - lw s1, 1*REGBYTES(sp) - lw s2, 2*REGBYTES(sp) - lw s3, 3*REGBYTES(sp) - lw s4, 4*REGBYTES(sp) - lw s5, 5*REGBYTES(sp) - lw s6, 6*REGBYTES(sp) - lw s7, 7*REGBYTES(sp) - lw s8, 8*REGBYTES(sp) - lw s9, 9*REGBYTES(sp) - lw s10, 10*REGBYTES(sp) - lw s11, 11*REGBYTES(sp) - addi sp, sp, 12*REGBYTES + lw s0, __reg_s0__OFFSET(sp) + lw s1, __reg_s1__OFFSET(sp) + lw s2, __reg_s2__OFFSET(sp) + lw s3, __reg_s3__OFFSET(sp) + lw s4, __reg_s4__OFFSET(sp) + lw s5, __reg_s5__OFFSET(sp) + lw s6, __reg_s6__OFFSET(sp) + lw s7, __reg_s7__OFFSET(sp) + lw s8, __reg_s8__OFFSET(sp) + lw s9, __reg_s9__OFFSET(sp) + lw s10, __reg_s10__OFFSET(sp) + lw s11, __reg_s11__OFFSET(sp) irq_restore: - // restore context - lw t0, (30-12)*REGBYTES(sp) + lw t0, __reg_mepc_OFFSET(sp) csrw mepc, t0 - lw t0, (31-12)*REGBYTES(sp) + lw t0, __reg_mstatus_OFFSET(sp) csrw mstatus, t0 - lw ra, (12-12)*REGBYTES(sp) - lw gp, (13-12)*REGBYTES(sp) - lw tp, (14-12)*REGBYTES(sp) - lw t0, (15-12)*REGBYTES(sp) - lw t1, (16-12)*REGBYTES(sp) - lw t2, (17-12)*REGBYTES(sp) - lw t3, (18-12)*REGBYTES(sp) - lw t4, (19-12)*REGBYTES(sp) - lw t5, (20-12)*REGBYTES(sp) - lw t6, (21-12)*REGBYTES(sp) - lw a0, (22-12)*REGBYTES(sp) - lw a1, (23-12)*REGBYTES(sp) - lw a2, (24-12)*REGBYTES(sp) - lw a3, (25-12)*REGBYTES(sp) - lw a4, (26-12)*REGBYTES(sp) - lw a5, (27-12)*REGBYTES(sp) - lw a6, (28-12)*REGBYTES(sp) - lw a7, (29-12)*REGBYTES(sp) - addi sp, sp, 20*REGBYTES + lw ra, __reg_ra__OFFSET(sp) + lw gp, __reg_gp__OFFSET(sp) + lw tp, __reg_tp__OFFSET(sp) + lw t0, __reg_t0__OFFSET(sp) + lw t1, __reg_t1__OFFSET(sp) + lw t2, __reg_t2__OFFSET(sp) + lw t3, __reg_t3__OFFSET(sp) + lw t4, __reg_t4__OFFSET(sp) + lw t5, __reg_t5__OFFSET(sp) + lw t6, __reg_t6__OFFSET(sp) + lw a0, __reg_a0__OFFSET(sp) + lw a1, __reg_a1__OFFSET(sp) + lw a2, __reg_a2__OFFSET(sp) + lw a3, __reg_a3__OFFSET(sp) + lw a4, __reg_a4__OFFSET(sp) + lw a5, __reg_a5__OFFSET(sp) + lw a6, __reg_a6__OFFSET(sp) + lw a7, __reg_a7__OFFSET(sp) + addi sp, sp, 128 mret