Jingru
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f7b5b43b90
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arch: arc fix build error
* add and set TOS_CFG_CPU_BYTE_ORDER
* exclude cmsis_os2.c from CMSIS_SRC
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-07-13 20:47:34 +08:00 |
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Jingru
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f8c58778bd
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arch：arc: use FLS instruction to get clz
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-25 17:25:52 +08:00 |
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Jingru
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204d269794
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arch: arc: update the ARC port
* remove unused codes and definition
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-07 15:09:42 +08:00 |
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Wayne Ren
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86375271fc
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arch: arc: update the ARC port
* bug fix
* remove unused codes and definition
* optimize some codes
Signed-off-by: Wayne Ren <wren@synopsys.com>
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2020-05-06 20:23:07 +08:00 |
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Jingru
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8c2af057f4
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arch: arc: remove unused codes and definition
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-06 20:21:21 +08:00 |
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Jingru
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e64869280b
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arch: arc: fix jump instruction and remove unused codes
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-06 20:18:19 +08:00 |
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Jingru
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a0eca8f6eb
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board: nsim: remove wrong definition
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-06 20:14:57 +08:00 |
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Watson Zeng
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0d4593ee5e
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arch: arc: update the ARC port
* add basic synopsys arc em processor support
* add basic arc nsim em virtual board support
* add basic arc mwdt toolchain support
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
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2020-05-06 17:59:22 +08:00 |
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Jingru
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bfe3ee1964
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board: nsim: add nsim.props and fix libraries
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-06 17:56:42 +08:00 |
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Jingru
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ddd2d53f06
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boarc: nsim: add source code to initialize board and start os
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-06 17:54:28 +08:00 |
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Jingru
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65f55e73e5
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arch :arc: add the ARC port
Signed-off-by: Jingru <jingru@synopsys.com>
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2020-05-06 17:53:27 +08:00 |
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