4 Commits

Author SHA1 Message Date
smithdeng
c205a460ab 移植js的duktape引擎 2020-11-15 17:29:17 +08:00
Supowang
4b694b3b87 Merge pull request #237 from tommytim0515/fix_markdown2
Fix TOC and insertion error.
2020-10-15 15:02:49 +08:00
tommytim0515
cba4d6c021 Fix TOC and insertion error. 2020-10-15 01:34:25 +08:00
mculover666
122fa9fd03 add support for multi sal devices concurrently 2020-08-13 17:51:05 +08:00
1962 changed files with 102884 additions and 836748 deletions

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README.md
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@@ -9,7 +9,7 @@
# 一、TencentOS Tiny 简介
[TencentOS tiny](https://cloud.tencent.com/product/tos-tiny) 是腾讯面向物联网领域开发的实时操作系统具有低功耗低资源占用模块化安全可靠等特点可有效提升物联网终端产品开发效率。TencentOS tiny 提供精简的 RTOS 内核,内核组件可裁剪可配置,可快速移植到多种主流 MCU (如 STM32 全系列)及模组芯片上。而且,基于 RTOS 内核提供了丰富的物联网组件,内部集成主流物联网协议栈(如 CoAP/MQTT/TLS/DTLS/LoRaWAN/NB-IoT 等),可助力物联网终端设备及业务快速接入腾讯云物联网平台。
[TencentOS tiny](https://cloud.tencent.com/product/tos-tiny)是腾讯面向物联网领域开发的实时操作系统具有低功耗低资源占用模块化安全可靠等特点可有效提升物联网终端产品开发效率。TencentOS tiny 提供精简的 RTOS 内核,内核组件可裁剪可配置,可快速移植到多种主流 MCU (如STM32全系列)及模组芯片上。而且基于RTOS内核提供了丰富的物联网组件内部集成主流物联网协议栈如 CoAP/MQTT/TLS/DTLS/LoRaWAN/NB-IoT 等),可助力物联网终端设备及业务快速接入腾讯云物联网平台。
## 1、TencentOS tiny整体架构
@@ -18,13 +18,13 @@
TencentOS tiny 主体架构图,从下到上主要包括:
**CPU 库** TencentOS tiny 支持的 CPU IP 核架构,当前主要支持 ARM Cortex M0/3/4/7Cortex A7RISC-V、MSP430、AVR、STM8 等。
**CPU 库** TencentOS tiny 支持的 CPU IP 核架构,当前主要支持 ARM Cortex M0/3/4/7Cortex A7RISC-V、MSP430、AVR、STM8等。
**驱动管理层** 包括板级支持包BSP主要由 MCU 芯片厂家开发与维护)、硬件抽象HAL主要由 TencentOS tiny 提供方便不同芯片的适配与移植、设备驱动Drivers例如 Wi-Fi、GPRS、LoRa 等模块的驱动程序)。
**驱动管理层** 包括板级支持包BSP主要由 MCU 芯片厂家开发与维护、硬件抽象HAL主要由 TencentOS tiny提供方便不同芯片的适配与移植、设备驱动Drivers例如 Wi-Fi、GPRS、LoRa 等模块的驱动程序)。
**内核** TencentOS tiny 实时内核包括任务管理、实时调度、时间管理、中断管理、内存管理、异常处理、软件定时器、链表、消息队列、信号量、互斥锁、事件标志等模块。
**IoT 协议栈**TencentOS tiny 提供 lwip、AT Adapter、SAL 层,支持不同的网络硬件,例如以太网、串口 Wi-Fi、GPRS、NB-IoT、4G 等通信模块。TCP/IP 网络协议栈上提供常用的物联网协议栈,例如 CoAP、MQTT支撑终端业务快速接入腾讯云。
**IoT 协议栈**TencentOS tiny 提供 lwip、AT Adapter、SAL 层,支持不同的网络硬件,例如以太网、串口 Wi-Fi、GPRS、NB-IoT、4G等通信模块。TCP/IP 网络协议栈上提供常用的物联网协议栈,例如 CoAP、MQTT支撑终端业务快速接入腾讯云。
**安全框架**TencentOS tiny 为了确保物联网终端数据传输安全以及设备认证安全,提供了完整的安全解决方案。安全框架提供的 DTLS 和 TLS 安全协议,加固了 COAP 及 MQTT 的传输层,可确保物联网终端在对接腾讯云时实现安全认证和数据加密;另外针对低资源的终端硬件,安全框架还提供与腾讯云 IoTHub 配套的密钥认证方案,确保资源受限设备也能在一定程度上实现设备安全认证。
@@ -34,19 +34,19 @@ TencentOS tiny 主体架构图,从下到上主要包括:
**示例应用**TencentOS tiny 提供的示例代码,模块测试代码等,方便用户参考使用。
## 2、TencentOS tiny 优势
## 2、TencentOS tiny优势
### (1).小体积
最小内核RAM 0.6KBROM 1.8KB
典型 LoraWAN 及传感器应用RAM 3.3KBROM 12KB
典型LoraWAN及传感器应用RAM 3.3KBROM 12KB
### (2).低功耗
休眠最低功耗低至 2uA
休眠最低功耗低至2 uA
支持外设功耗管理框架
### (3).丰富的 IoT 组件
集成主流 IoT 协议栈
### (3).丰富的IoT组件
集成主流IoT协议栈
多种通信模组SAL层适配框架
支持 OTA 升级
提供简单易用端云 API加速用户业务接入腾讯云
支持OTA升级
提供简单易用端云API加速用户业务接入腾讯云
### (4).可靠的安全框架
多样化的安全分级方案
均衡安全需求&成本控制
@@ -61,136 +61,133 @@ TencentOS tiny 主体架构图,从下到上主要包括:
![](./doc/image/introduction/Partners.png)
TencentOS tiny 自开源发布以来也在努力发展合作伙伴,期待合作共赢,共同扩展 IoT 应用生态。目前已经与多家 MCU/IP 核厂家达成了合作包括意法半导体、恩智浦半导体、兆易半导体、ARM、华大半导体、芯来科技等也与无线 SOC 和模组厂家达成了广泛的合作关系包括瑞兴恒方、国民技术、Nordic 蓝牙、亮牛半导体、有人物联网等,
TencentOS tiny自开源发布以来也在努力发展合作伙伴期待合作共赢共同扩展IoT应用生态。目前已经与多家MCU/IP核厂家达成了合作包括意法半导体、恩智浦半导体、兆易半导体、ARM、华大半导体、芯来科技等也与无线SOC和模组厂家达成了广泛的合作关系包括瑞兴恒方、国民技术、Nordic蓝牙、亮牛半导体、有人物联网等
除了MCU和模组外TencentOS tiny 也积极推进终端产品及项目的落地目前已经形成了AI智慧农业、智能货柜、智慧会议室等方案并且在腾讯内部与 AI 平台部、腾讯微瓴、QQ family 达成内部合作共同扩展行业生态同时也开始积极发展外部客户目前与深圳光合显示科技的墨水屏零售标签、鑫悦购充电桩等达成业务合作。TencentOS tiny 将携手合作伙伴为物联网终端厂家提供更优质的 IoT 终端软件解决方案,方便各种物联网设备快速接入腾讯云,共同扩展 IoT 生态,更好地支撑智慧城市、智能水表、智能家居、智能穿戴、车联网等多种行业应用。
除了MCU和模组外TencentOS tiny也积极推进终端产品及项目的落地目前已经形成了AI智慧农业、智能货柜、智慧会议室等方案并且在腾讯内部与AI 平台部、腾讯微瓴、QQ family达成内部合作共同扩展行业生态同时也开始积极发展外部客户目前与深圳光合显示科技的墨水屏零售标签、鑫悦购充电桩等达成业务合作。TencentOS tiny 将携手合作伙伴为物联网终端厂家提供更优质的IoT终端软件解决方案方便各种物联网设备快速接入腾讯云共同扩展IoT生态更好地支撑智慧城市、智能水表、智能家居、智能穿戴、车联网等多种行业应用。
欢迎 IoT 相关项目合作,有合作需求的请邮件联系 TencentOS tiny 官方工作人员,邮箱地址 supowang@tencent.com
欢迎IoT相关项目合作有合作需求的请邮件联系TencentOS tiny官方工作人员邮箱地址 supowang@tencent.com
# 二、TencentOS tiny 代码目录
- [TencentOS tiny 代码目录说明](./doc/09.Code_Directories.md)
- [TencentOS tiny代码目录说明](./doc/09.Code_Directories.md)
# 三、TencentOS tiny 参考文档
## 1、移植指南
- [TencentOS tiny 移植指南KEIL 版本)](./doc/10.Porting_Manual_for_KEIL.md)
- [TencentOS tiny 移植指南IAR 版本)](./doc/11.Porting_Manual_for_IAR.md)
- [TencentOS tiny 移植指南GCC 版本)](./doc/12.Porting_Manual_for_GCC.md)
- [TencentOS tiny移植指南KEIL版本](./doc/10.Porting_Manual_for_KEIL.md)
- [TencentOS tiny移植指南IAR版本](./doc/11.Porting_Manual_for_IAR.md)
- [TencentOS tiny移植指南GCC版本](./doc/12.Porting_Manual_for_GCC.md)
## 2、TencentOS tiny 开发指南
- [TencentOS tiny 内核开发指南](./doc/04.Development_Manual.md)
- [TencentOS tiny API 参考](./doc/05.SDK_Manual.md)
- [TencentOS tiny 对接腾讯云 IoTHub 开发指南](./doc/08.QCloud_IoTHub_Quick_Start.md)
## 3、TencentOS tiny 腾讯云大学视频教程
- [TencentOS tiny 端侧开发实践课](https://cloud.tencent.com/edu/paths/series/IoT)
- [TencentOS tiny内核开发指南](./doc/04.Development_Manual.md)
- [TencentOS tiny API参考](./doc/05.SDK_Manual.md)
- [TencentOS tiny对接腾讯云IoTHub开发指南](./doc/08.QCloud_IoTHub_Quick_Start.md)
# 四、TencentOS tiny 开源协议
* TencentOS tiny 遵循 [BSD-3 开源许可协议](LICENSE)
* TencentOS tiny 遵循 [BSD-3开源许可协议](LICENSE)
# 五、TencentOS tiny 支持的物联网平台
TencentOS tiny 能支持物联网终端设备和业务快速接入[腾讯云物联网平台 IoT Explorer](https://cloud.tencent.com/product/iotexplorer)。
TencentOS tiny能支持物联网终端设备和业务快速接入[腾讯云物联网平台IoT Explorer](https://cloud.tencent.com/product/iotexplorer)。
TencentOS tiny 结合腾讯云物联网开发平台 IoT Explorer已经构筑起连接通讯芯片到云开发的能力加上已经建设完成的国内最大规模 LoRa 网络腾讯彻底打通从芯片通讯开发、网络支撑服务物理设备定义管理数据分析和多场景应用开发等全链条IoT云开发服务能力重新定义了物联网开发模式助力亿级设备多方式多模式低门槛接入腾讯云服务。作为物联网基础设施建设服务者腾讯将持续打造开放的物联网生态体系促进物联网生态良性发展。
TencentOS tiny结合腾讯云物联网开发平台IoT Explorer已经构筑起连接通讯芯片到云开发的能力加上已经建设完成的国内最大规模LoRa网络腾讯彻底打通从芯片通讯开发、网络支撑服务物理设备定义管理数据分析和多场景应用开发等全链条IoT云开发服务能力重新定义了物联网开发模式助力亿级设备多方式多模式低门槛接入腾讯云服务。作为物联网基础设施建设服务者腾讯将持续打造开放的物联网生态体系促进物联网生态良性发展。
# 六、TencentOS tiny 快速入门参考
TencentOS tiny 联合合作伙伴(南京厚德物联网)设计了定制开发板,如下图:
TencentOS tiny联合合作伙伴(南京厚德物联网)设计了定制开发板,如下图:
![](./doc/image/introduction/EVB_MX.png)
- [TencentOS tiny 定制开发板介绍页](http://www.holdiot.com/product/showproduct.php?id=8),开发者可以基于定制开发板进行快速入门学习,点击下载参考文档
- [TencentOS-tiny 定制开发板入门指南](./doc/15.TencentOS_tiny_EVB_MX_Plus_Quick_Start.md)
- [TencentOS tiny定制开发板介绍页](http://www.holdiot.com/product/showproduct.php?id=8),开发者可以基于定制开发板进行快速入门学习,点击下载参考文档
- [TencentOS-tiny定制开发板入门指南](./doc/15.TencentOS_tiny_EVB_MX_Plus_Quick_Start.md)
# 七、贡献代码
* 1. 在您自己的 GitHub 账户下 Fork TencentOS tiny 开源项目;
* 2. 根据您的需求在本地 clone 一份 TencentOS tiny 代码;
* 3. 您修改或者新增功能后push 到您 fork 的远程分支;
* 4. 创建 pull request TencentOS tiny 官方开发分支提交合入请求;
* 5. TencentOS tiny 研发团队会定期 review 代码,通过测试后合入。
* 1. 在您自己的GitHub账户下Fork TencentOS tiny 开源项目;
* 2. 根据您的需求在本地clone 一份TencentOS tiny 代码;
* 3. 您修改或者新增功能后push 到您fork的远程分支
* 4. 创建 pull request向TencentOS tiny官方开发分支提交合入请求
* 5. TencentOS tiny研发团队会定期review代码通过测试后合入。
# 八、加入TencentOS tiny官方QQ技术交流群
扫码加群,请备注 TencentOS tiny 开发者,工作人员会根据备注进行审核:
扫码加群请备注TencentOS tiny开发者工作人员会根据备注进行审核
![](./doc/image/introduction/qq.png)
# 九、第三方开发者评测
1.基于 TencentOS tiny 的环境监测实战项目
1.基于TencentOS tiny 的环境监测实战项目
[【TencentOS tiny】环境监测实战项目最终完整版](https://www.bilibili.com/video/av73782956?from=search&seid=4421984671929108231)
感谢阿正的贡献
2.基于野火 stm32f103 开发板上移植的 TencentOS tiny 例程、源码剖析、视频讲解。
感谢 CSDN 博客专家杰杰的贡献
2.基于野火stm32f103开发板上移植的TencentOS tiny 例程、源码剖析、视频讲解。
感谢CSDN博客专家杰杰的贡献
## 简单上手:
- [超详细的 TencentOS tiny 移植到 STM32F103 全教程](https://blog.csdn.net/jiejiemcu/article/details/101034426)
- [超详细的 TencentOS tiny 移植到STM32F103全教程](https://blog.csdn.net/jiejiemcu/article/details/101034426)
## 深度源码分析:
- [【TencentOS tiny 学习】源码分析1——task](https://blog.csdn.net/jiejiemcu/article/details/99618912)
- [【TencentOS tiny学习】源码分析1——task](https://blog.csdn.net/jiejiemcu/article/details/99618912)
- [【TencentOS tiny 学习】源码分析2——调度器](https://blog.csdn.net/jiejiemcu/article/details/99665883)
- [【TencentOS tiny学习】源码分析2——调度器](https://blog.csdn.net/jiejiemcu/article/details/99665883)
- [【TencentOS tiny 学习】源码分析3——队列](https://blog.csdn.net/jiejiemcu/article/details/99687678)
- [【TencentOS tiny学习】源码分析3——队列](https://blog.csdn.net/jiejiemcu/article/details/99687678)
- [【TencentOS tiny 学习】源码分析4——消息队列](https://blog.csdn.net/jiejiemcu/article/details/99781093)
- [【TencentOS tiny学习】源码分析4——消息队列](https://blog.csdn.net/jiejiemcu/article/details/99781093)
- [【TencentOS tiny 学习】源码分析5——信号量](https://blog.csdn.net/jiejiemcu/article/details/100052643)
- [【TencentOS tiny学习】源码分析5——信号量](https://blog.csdn.net/jiejiemcu/article/details/100052643)
- [【TencentOS tiny 学习】源码分析6——互斥锁](https://blog.csdn.net/jiejiemcu/article/details/100056641)
- [【TencentOS tiny学习】源码分析6——互斥锁](https://blog.csdn.net/jiejiemcu/article/details/100056641)
- [【TencentOS tiny 学习】源码分析7——事件](https://blog.csdn.net/jiejiemcu/article/details/100492219)
- [【TencentOS tiny学习】源码分析7——事件](https://blog.csdn.net/jiejiemcu/article/details/100492219)
- [【TencentOS tiny 学习】源码分析8——软件定时器](https://blog.csdn.net/jiejiemcu/article/details/101846089)
- [【TencentOS tiny学习】源码分析8——软件定时器](https://blog.csdn.net/jiejiemcu/article/details/101846089)
## 配套例程:
- [【TencentOS tiny 学习】例程0——hello world](https://github.com/jiejieTop/TencentOS-Demo/tree/master/hello-world)
- [【TencentOS tiny学习】例程0——hello world](https://github.com/jiejieTop/TencentOS-Demo/tree/master/hello-world)
- [【TencentOS tiny 学习】例程1——task](https://github.com/jiejieTop/TencentOS-Demo/tree/master/01-task)
- [【TencentOS tiny学习】例程1——task](https://github.com/jiejieTop/TencentOS-Demo/tree/master/01-task)
- [【TencentOS tiny 学习】例程2——队列](https://github.com/jiejieTop/TencentOS-Demo/tree/master/02-queue)
- [【TencentOS tiny学习】例程2——队列](https://github.com/jiejieTop/TencentOS-Demo/tree/master/02-queue)
- [【TencentOS tiny 学习】例程3——消息队列](https://github.com/jiejieTop/TencentOS-Demo/tree/master/03-msg_queue)
- [【TencentOS tiny学习】例程3——消息队列](https://github.com/jiejieTop/TencentOS-Demo/tree/master/03-msg_queue)
- [【TencentOS tiny 学习】例程4——信号量](https://github.com/jiejieTop/TencentOS-Demo/tree/master/04-sem)
- [【TencentOS tiny学习】例程4——信号量](https://github.com/jiejieTop/TencentOS-Demo/tree/master/04-sem)
- [【TencentOS tiny 学习】例程5——互斥锁](https://github.com/jiejieTop/TencentOS-Demo/tree/master/05-mutex)
- [【TencentOS tiny学习】例程5——互斥锁](https://github.com/jiejieTop/TencentOS-Demo/tree/master/05-mutex)
- [【TencentOS tiny 学习】例程6——事件](https://github.com/jiejieTop/TencentOS-Demo/tree/master/06-event)
- [【TencentOS tiny学习】例程6——事件](https://github.com/jiejieTop/TencentOS-Demo/tree/master/06-event)
- [【TencentOS tiny 学习】例程7——软件定时器](https://github.com/jiejieTop/TencentOS-Demo/tree/master/07-timer)
- [【TencentOS tiny学习】例程7——软件定时器](https://github.com/jiejieTop/TencentOS-Demo/tree/master/07-timer)
- [【TencentOS tiny 学习】例程8——内存池](https://github.com/jiejieTop/TencentOS-Demo/tree/master/08-mmblk)
- [【TencentOS tiny学习】例程8——内存池](https://github.com/jiejieTop/TencentOS-Demo/tree/master/08-mmblk)
- [【TencentOS tiny 学习】例程9——内存堆](https://github.com/jiejieTop/TencentOS-Demo/tree/master/09-mmheap)
- [【TencentOS tiny学习】例程9——内存堆](https://github.com/jiejieTop/TencentOS-Demo/tree/master/09-mmheap)
## 视频教程:
- [【TencentOS tiny 学习】视频汇总](https://www.bilibili.com/video/av70478596?from=search&seid=10160676184801585522)
- [【视频】01-初识 TencentOS tiny](https://www.bilibili.com/video/av70478596/?p=1)
- [【视频】02-TencentOS tiny 基础知识](https://www.bilibili.com/video/av70478596/?p=2)
- [【视频】03-TencentOS tiny 移植](https://www.bilibili.com/video/av70478596/?p=3)
- [【视频】04-TencentOS tiny 任务-1](https://www.bilibili.com/video/av70478596/?p=4)
- [【视频】05-TencentOS tiny 任务-2](https://www.bilibili.com/video/av70478596/?p=5)
- [【视频】06-TencentOS tiny 队列-1](https://www.bilibili.com/video/av70478596/?p=6)
- [【视频】07-TencentOS tiny 队列-2](https://www.bilibili.com/video/av70478596/?p=7)
- [【视频】08-TencentOS tiny 消息队列](https://www.bilibili.com/video/av70478596/?p=8)
- [【视频】09-TencentOS tiny 信号量-1](https://www.bilibili.com/video/av70478596/?p=9)
- [【视频】10-TencentOS tiny 信号量-2](https://www.bilibili.com/video/av70478596/?p=10)
- [【视频】11-TencentOS tiny 互斥锁-1](https://www.bilibili.com/video/av70478596/?p=11)
- [【视频】12-TencentOS tiny 互斥锁-2](https://www.bilibili.com/video/av70478596/?p=12)
- [【视频】13-TencentOS tiny 互斥锁-3](https://www.bilibili.com/video/av70478596/?p=13)
- [【视频】14-TencentOS tiny 事件-1](https://www.bilibili.com/video/av70478596/?p=14)
- [【视频】15-TencentOS tiny 事件-2](https://www.bilibili.com/video/av70478596/?p=15)
- [【视频】16-TencentOS tiny 软件定时器-1](https://www.bilibili.com/video/av70478596/?p=16)
- [【视频】17-TencentOS tiny 软件定时器-2](https://www.bilibili.com/video/av70478596/?p=11)
- [【视频】18-TencentOS tiny 软件定时器-3](https://www.bilibili.com/video/av70478596/?p=18)
- [【TencentOS tiny学习】视频汇总](https://www.bilibili.com/video/av70478596?from=search&seid=10160676184801585522)
- [【视频】01-初识TencentOS tiny](https://www.bilibili.com/video/av70478596/?p=1)
- [【视频】02-TencentOS tiny基础知识](https://www.bilibili.com/video/av70478596/?p=2)
- [【视频】03-TencentOS tiny移植](https://www.bilibili.com/video/av70478596/?p=3)
- [【视频】04-TencentOS tiny任务-1](https://www.bilibili.com/video/av70478596/?p=4)
- [【视频】05-TencentOS tiny任务-2](https://www.bilibili.com/video/av70478596/?p=5)
- [【视频】06-TencentOS tiny队列-1](https://www.bilibili.com/video/av70478596/?p=6)
- [【视频】07-TencentOS tiny队列-2](https://www.bilibili.com/video/av70478596/?p=7)
- [【视频】08-TencentOS tiny消息队列](https://www.bilibili.com/video/av70478596/?p=8)
- [【视频】09-TencentOS tiny信号量-1](https://www.bilibili.com/video/av70478596/?p=9)
- [【视频】10-TencentOS tiny信号量-2](https://www.bilibili.com/video/av70478596/?p=10)
- [【视频】11-TencentOS tiny互斥锁-1](https://www.bilibili.com/video/av70478596/?p=11)
- [【视频】12-TencentOS tiny互斥锁-2](https://www.bilibili.com/video/av70478596/?p=12)
- [【视频】13-TencentOS tiny互斥锁-3](https://www.bilibili.com/video/av70478596/?p=13)
- [【视频】14-TencentOS tiny事件-1](https://www.bilibili.com/video/av70478596/?p=14)
- [【视频】15-TencentOS tiny事件-2](https://www.bilibili.com/video/av70478596/?p=15)
- [【视频】16-TencentOS tiny软件定时器-1](https://www.bilibili.com/video/av70478596/?p=16)
- [【视频】17-TencentOS tiny软件定时器-2](https://www.bilibili.com/video/av70478596/?p=11)
- [【视频】18-TencentOS tiny软件定时器-3](https://www.bilibili.com/video/av70478596/?p=18)
## 相关PPT资料
- [【TencentOS tiny 学习】视频 PPT](https://github.com/jiejieTop/TencentOS-Demo/tree/master/PPT)
- [【TencentOS tiny学习】视频PPT](https://github.com/jiejieTop/TencentOS-Demo/tree/master/PPT)

View File

@@ -20,7 +20,7 @@ TencentOS tiny main architecture diagram, from bottom to top, mainly includes:
**CPU libs** The CPU IP core architecture supported by TencentOS tiny,currently supports ARM Cortex M0/3/4/7.
**Drive management** Including board support package (BSP, mainly developed and maintained by MCU chip manufacturers), hardware abstraction layer (HAL, mainly provided by TencentOS tiny, to facilitate adaptation and porting of different chips), device drivers (Drivers, such as Wi-Fi, GPRS Drivers for modules such as LoRa).
**Drive management** Including board support package (BSP, mainly developed and maintained by MCU chip manufacturers), hardware abstraction (HAL, mainly provided by TencentOS tiny, to facilitate adaptation and porting of different chips), device drivers (Drivers, such as Wi-Fi, GPRS Drivers for modules such as LoRa).
**kernel** The TencentOS tiny real-time kernel includes tasks management, real-time scheduling, time management, interrupt management, memory management, exception handling, software timers, linked lists, message queues, semaphores, mutex locks, event flags, and more.

View File

@@ -213,7 +213,7 @@ __STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame
if (info->is_on_task) {
info->stack_start = (cpu_addr_t)k_curr_task->stk_base;
info->stack_limit = info->stack_start + k_curr_task->stk_size// * sizeof(k_task_t);
info->stack_limit = info->stack_start + k_curr_task->stk_size * sizeof(k_task_t);
} else {
info->stack_start = fault_msp_start();
info->stack_limit = fault_msp_limit();

View File

@@ -1,312 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _PORT_H_
#define _PORT_H_
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
typedef struct port_fault_regs {
union {
/* System Handler Control and State Register (0xE000ED24) */
uint32_t value;
struct {
/* Read as 1 if memory management fault is active */
uint32_t MEMFAULTACT : 1;
/* Read as 1 if bus fault exception is active */
uint32_t BUSFAULTACT : 1;
uint32_t UnusedBits1 : 1;
/* Read as 1 if usage fault exception is active */
uint32_t USGFAULTACT : 1;
uint32_t UnusedBits2 : 3;
/* Read as 1 if SVC exception is active */
uint32_t SVCALLACT : 1;
/* Read as 1 if debug monitor exception is active */
uint32_t MONITORACT : 1;
uint32_t UnusedBits3 : 1;
/* Read as 1 if PendSV exception is active */
uint32_t PENDSVACT : 1;
/* Read as 1 if SYSTICK exception is active */
uint32_t SYSTICKACT : 1;
/* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
uint32_t USGFAULTPENDED : 1;
/* Memory management fault pended; memory management fault started but was replaced by a
higher-priority exception */
uint32_t MEMFAULTPENDED : 1;
/* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
exception */
uint32_t BUSFAULTPENDED : 1;
/* SVC pended; SVC was started but was replaced by a higher-priority exception */
uint32_t SVCALLPENDED : 1;
/* Memory management fault handler enable */
uint32_t MEMFAULTENA : 1;
/* Bus fault handler enable */
uint32_t BUSFAULTENA : 1;
/* Usage fault handler enable */
uint32_t USGFAULTENA : 1;
} bits;
} syshndctrl;
union {
uint32_t value;
struct {
union {
/* Memory Management Fault Status Register (0xE000ED28) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IACCVIOL : 1;
/* Data access violation */
uint8_t DACCVIOL : 1;
uint8_t UnusedBits : 1;
/* Unstacking error */
uint8_t MUNSTKERR : 1;
/* Stacking error */
uint8_t MSTKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t MLSPERR : 1;
uint8_t UnusedBits2 : 1;
/* Indicates the MMAR is valid */
uint8_t MMARVALID : 1;
} bits;
} mfsr;
union {
/* Bus Fault Status Register (0xE000ED29) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IBUSERR : 1;
/* Precise data access violation */
uint8_t PRECISERR : 1;
/* Imprecise data access violation */
uint8_t IMPREISERR : 1;
/* Unstacking error */
uint8_t UNSTKERR : 1;
/* Stacking error */
uint8_t STKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t LSPERR : 1;
uint8_t UnusedBits : 1;
/* Indicates BFAR is valid */
uint8_t BFARVALID : 1;
} bits;
} bfsr;
union {
/* Usage Fault Status Register (0xE000ED2A) */
uint16_t value;
struct {
/* Attempts to execute an undefined instruction */
uint16_t UNDEFINSTR : 1;
/* Attempts to switch to an invalid state (e.g., ARM) */
uint16_t INVSTATE : 1;
/* Attempts to do an exception with a bad value in the EXC_RETURN number */
uint16_t INVPC : 1;
/* Attempts to execute a coprocessor instruction */
uint16_t NOCP : 1;
uint16_t UnusedBits : 4;
/* Indicates that an unaligned access fault has taken place */
uint16_t UNALIGNED : 1;
/* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
uint16_t DIVBYZERO0 : 1;
} bits;
} ufsr;
} part;
} cfsr;
/* Memory Management Fault Address Register (0xE000ED34) */
uint32_t mmar;
/* Bus Fault Manage Address Register (0xE000ED38) */
uint32_t bfar;
union {
/* Hard Fault Status Register (0xE000ED2C) */
uint32_t value;
struct {
uint32_t UnusedBits : 1;
/* Indicates hard fault is caused by failed vector fetch */
uint32_t VECTBL : 1;
uint32_t UnusedBits2 : 28;
/* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
uint32_t FORCED : 1;
/* Indicates hard fault is triggered by debug event */
uint32_t DEBUGEVT : 1;
} bits;
} hfsr;
union {
/* Debug Fault Status Register (0xE000ED30) */
uint32_t value;
struct {
/* Halt requested in NVIC */
uint32_t HALTED : 1;
/* BKPT instruction executed */
uint32_t BKPT : 1;
/* DWT match occurred */
uint32_t DWTTRAP : 1;
/* Vector fetch occurred */
uint32_t VCATCH : 1;
/* EDBGRQ signal asserted */
uint32_t EXTERNAL : 1;
} bits;
} dfsr;
/* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
uint32_t afsr;
} port_fault_regs_t;
enum fault_info {
FAULT_INFO_ASSERT_ON_THREAD,
FAULT_INFO_HFSR_VECTBL,
FAULT_INFO_MFSR_IACCVIOL,
FAULT_INFO_MFSR_DACCVIOL,
FAULT_INFO_MFSR_MUNSTKERR,
FAULT_INFO_MFSR_MSTKERR,
FAULT_INFO_MFSR_MLSPERR,
FAULT_INFO_BFSR_IBUSERR,
FAULT_INFO_BFSR_PRECISERR,
FAULT_INFO_BFSR_IMPREISERR,
FAULT_INFO_BFSR_UNSTKERR,
FAULT_INFO_BFSR_STKERR,
FAULT_INFO_BFSR_LSPERR,
FAULT_INFO_UFSR_UNDEFINSTR,
FAULT_INFO_UFSR_INVSTATE,
FAULT_INFO_UFSR_INVPC,
FAULT_INFO_UFSR_NOCP,
FAULT_INFO_UFSR_UNALIGNED,
FAULT_INFO_UFSR_DIVBYZERO0,
FAULT_INFO_DFSR_HALTED,
FAULT_INFO_DFSR_BKPT,
FAULT_INFO_DFSR_DWTTRAP,
FAULT_INFO_DFSR_VCATCH,
FAULT_INFO_DFSR_EXTERNAL,
FAULT_INFO_MMAR,
FAULT_INFO_BFAR,
};
static const char *const fault_msg[] = {
[FAULT_INFO_ASSERT_ON_THREAD] = "Assert on thread %s\n",
[FAULT_INFO_HFSR_VECTBL] = "Hard fault is caused by failed vector fetch\n",
[FAULT_INFO_MFSR_IACCVIOL] = "Memory management fault: instruction access violation\n",
[FAULT_INFO_MFSR_DACCVIOL] = "Memory management fault: data access violation\n",
[FAULT_INFO_MFSR_MUNSTKERR] = "Memory management fault: unstacking error\n",
[FAULT_INFO_MFSR_MSTKERR] = "Memory management fault: stacking error\n",
[FAULT_INFO_MFSR_MLSPERR] = "Memory management fault: floating-point lazy state preservation\n",
[FAULT_INFO_BFSR_IBUSERR] = "Bus fault: instruction access violation\n",
[FAULT_INFO_BFSR_PRECISERR] = "Bus fault: precise data access violation\n",
[FAULT_INFO_BFSR_IMPREISERR] = "Bus fault: imprecise data access violation\n",
[FAULT_INFO_BFSR_UNSTKERR] = "Bus fault: unstacking error\n",
[FAULT_INFO_BFSR_STKERR] = "Bus fault: stacking error\n",
[FAULT_INFO_BFSR_LSPERR] = "Bus fault: floating-point lazy state preservation\n",
[FAULT_INFO_UFSR_UNDEFINSTR] = "Usage fault: undefined instruction\n",
[FAULT_INFO_UFSR_INVSTATE] = "Usage fault: invalid state (e.g., ARM)\n",
[FAULT_INFO_UFSR_INVPC] = "Usage fault: invalid EXC_RETURN\n",
[FAULT_INFO_UFSR_NOCP] = "Usage fault: coprocessor instruction\n",
[FAULT_INFO_UFSR_UNALIGNED] = "Usage fault: unaligned access\n",
[FAULT_INFO_UFSR_DIVBYZERO0] = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
[FAULT_INFO_DFSR_HALTED] = "Debug fault: halt requested in NVIC\n",
[FAULT_INFO_DFSR_BKPT] = "Debug fault: BKPT instruction executed\n",
[FAULT_INFO_DFSR_DWTTRAP] = "Debug fault: DWT match occurred\n",
[FAULT_INFO_DFSR_VCATCH] = "Debug fault: Vector fetch occurred\n",
[FAULT_INFO_DFSR_EXTERNAL] = "Debug fault: EDBGRQ signal asserted\n",
[FAULT_INFO_MMAR] = "The memory management fault occurred address is %08x\n",
[FAULT_INFO_BFAR] = "The bus fault occurred address is %08x\n",
};
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
__PORT__ uint32_t port_clz(uint32_t val);
#endif
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#endif /* _PORT_H_ */

View File

@@ -1,281 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "tos_k.h"
#include "core_cm33.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
(void)SysTick_Config(cycle_per_tick);
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTick_IRQn, prio);
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
{
return SysTick_LOAD_RELOAD_Msk;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
port_systick_config(cycle_per_tick);
}
__PORT__ void port_systick_pending_reset(void)
{
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
#if 1
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#endif
}
__PORT__ void port_stop_mode_enter(void)
{
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
HAL_PWR_EnterSTANDBYMode();
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
{
k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
if (regs->hfsr.bits.VECTBL) {
k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
}
if (regs->hfsr.bits.FORCED) {
/* Memory Management Fault */
if (regs->cfsr.part.mfsr.value) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MLSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
}
if (regs->cfsr.part.mfsr.bits.MMARVALID) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
}
}
}
/* Bus Fault */
if (regs->cfsr.part.bfsr.value) {
if (regs->cfsr.part.bfsr.bits.IBUSERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
}
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
}
if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
}
if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
}
if (regs->cfsr.part.bfsr.bits.STKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
}
if (regs->cfsr.part.bfsr.bits.LSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
}
if (regs->cfsr.part.bfsr.bits.BFARVALID) {
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
}
}
}
/* Usage Fault */
if (regs->cfsr.part.ufsr.value) {
if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
}
if (regs->cfsr.part.ufsr.bits.INVSTATE) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
}
if (regs->cfsr.part.ufsr.bits.INVPC) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
}
if (regs->cfsr.part.ufsr.bits.NOCP) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
}
if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
}
if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
}
}
}
/* Debug Fault */
if (regs->hfsr.bits.DEBUGEVT) {
if (regs->dfsr.value) {
if (regs->dfsr.bits.HALTED) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
}
if (regs->dfsr.bits.BKPT) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
}
if (regs->dfsr.bits.DWTTRAP) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
}
if (regs->dfsr.bits.VCATCH) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
}
if (regs->dfsr.bits.EXTERNAL) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
}
}
}
}
__PORT__ void port_fault_diagnosis(void)
{
port_fault_regs_t regs;
regs.syshndctrl.value = SCB->SHCSR;
regs.cfsr.value = SCB->CFSR;
regs.mmar = SCB->MMFAR;
regs.bfar = SCB->BFAR;
regs.hfsr.value = SCB->HFSR;
regs.dfsr.value = SCB->DFSR;
regs.afsr = SCB->AFSR;
port_fault_do_diagnosis(&regs);
}
/*------------------ RealView Compiler -----------------*/
/* V5 */
#if defined(__CC_ARM)
__PORT__ __ASM__ void HardFault_Handler(void)
{
IMPORT fault_backtrace
MOV r0, lr
TST lr, #0x04
ITE EQ
MRSEQ r1, MSP
MRSNE r1, PSP
BL fault_backtrace
}
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
__PORT__ void __NAKED__ HardFault_Handler(void)
{
__ASM__ __VOLATILE__ (
"MOV r0, lr\n\t"
"TST lr, #0x04\n\t"
"ITE EQ\n\t"
"MRSEQ r1, MSP\n\t"
"MRSNE r1, PSP\n\t"
"BL fault_backtrace\n\t"
);
}
#endif /* ARMCC VERSION */
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

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@@ -1,37 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 1u
#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN
#if (defined(ARMCC_V5) && !defined(__TARGET_FPU_SOFTVFP)) || \
(defined(ARMCC_V6) && defined(__ARM_PCS_VFP))
#define TOS_CFG_CPU_ARM_FPU_EN 1u
#else
#define TOS_CFG_CPU_ARM_FPU_EN 0u
#endif
#endif /* _PORT_CONFIG_H_ */

View File

@@ -1,188 +0,0 @@
EXPORT port_int_disable
EXPORT port_int_enable
EXPORT port_cpsr_save
EXPORT port_cpsr_restore
EXPORT port_sched_start
EXPORT port_context_switch
EXPORT port_irq_context_switch
EXPORT port_clz
EXPORT PendSV_Handler
IMPORT k_curr_task
IMPORT k_next_task
SCB_VTOR EQU 0xE000ED08
NVIC_INT_CTRL EQU 0xE000ED04
NVIC_SYSPRI14 EQU 0xE000ED22
NVIC_PENDSV_PRI EQU 0xFF
NVIC_PENDSVSET EQU 0x10000000
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
GLOBAL port_int_disable
port_int_disable
CPSID I
BX LR
GLOBAL port_int_enable
port_int_enable
CPSIE I
BX LR
GLOBAL port_cpsr_save
port_cpsr_save
MRS R0, PRIMASK
CPSID I
BX LR
GLOBAL port_cpsr_restore
port_cpsr_restore
MSR PRIMASK, R0
BX LR
GLOBAL port_clz
port_clz
CLZ R0, R0
BX LR
GLOBAL port_sched_start
port_sched_start
CPSID I
; set pendsv priority lowest
; otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
; that would be a disaster
MOV32 R0, NVIC_SYSPRI14
MOV32 R1, NVIC_PENDSV_PRI
STRB R1, [R0]
LDR R0, =SCB_VTOR
LDR R0, [R0]
LDR R0, [R0]
MSR MSP, R0
; k_curr_task = k_next_task
MOV32 R0, k_curr_task
MOV32 R1, k_next_task
LDR R2, [R1]
STR R2, [R0]
; sp = k_next_task->sp
LDR R0, [R2]
; PSP = sp
MSR PSP, R0
; using PSP
MRS R0, CONTROL
ORR R0, R0, #2
MSR CONTROL, R0
ISB
; restore r4-11 from new process stack
LDMFD SP!, {R4 - R11}
IF {FPU} != "SoftVFP"
; ignore EXC_RETURN the first switch
LDMFD SP!, {R0}
ENDIF
; restore r0, r3
LDMFD SP!, {R0 - R3}
; load R12 and LR
LDMFD SP!, {R12, LR}
; load PC and discard xPSR
LDMFD SP!, {R1, R2}
CPSIE I
BX R1
GLOBAL port_context_switch
port_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
GLOBAL port_irq_context_switch
port_irq_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
GLOBAL PendSV_Handler
PendSV_Handler
CPSID I
MRS R0, PSP
_context_save
; R0-R3, R12, LR, PC, xPSR is saved automatically here
IF {FPU} != "SoftVFP"
; is it extended frame?
TST LR, #0x10
IT EQ
VSTMDBEQ R0!, {S16 - S31}
; S0 - S16, FPSCR saved automatically here
; save EXC_RETURN
STMFD R0!, {LR}
ENDIF
; save remaining regs r4-11 on process stack
STMFD R0!, {R4 - R11}
; k_curr_task->sp = PSP
MOV32 R5, k_curr_task
LDR R6, [R5]
; R0 is SP of process being switched out
STR R0, [R6]
_context_restore
; k_curr_task = k_next_task
MOV32 R1, k_next_task
LDR R2, [R1]
STR R2, [R5]
; R0 = k_next_task->sp
LDR R0, [R2]
; restore R4 - R11
LDMFD R0!, {R4 - R11}
IF {FPU} != "SoftVFP"
; restore EXC_RETURN
LDMFD R0!, {LR}
; is it extended frame?
TST LR, #0x10
IT EQ
VLDMIAEQ R0!, {S16 - S31}
ENDIF
; Load PSP with new process SP
MSR PSP, R0
CPSIE I
; R0-R3, R12, LR, PC, xPSR restored automatically here
; S0 - S16, FPSCR restored automatically here if FPCA = 1
BX LR
ALIGN
END

View File

@@ -1,311 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _PORT_H_
#define _PORT_H_
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
typedef struct port_fault_regs {
union {
/* System Handler Control and State Register (0xE000ED24) */
uint32_t value;
struct {
/* Read as 1 if memory management fault is active */
uint32_t MEMFAULTACT : 1;
/* Read as 1 if bus fault exception is active */
uint32_t BUSFAULTACT : 1;
uint32_t UnusedBits1 : 1;
/* Read as 1 if usage fault exception is active */
uint32_t USGFAULTACT : 1;
uint32_t UnusedBits2 : 3;
/* Read as 1 if SVC exception is active */
uint32_t SVCALLACT : 1;
/* Read as 1 if debug monitor exception is active */
uint32_t MONITORACT : 1;
uint32_t UnusedBits3 : 1;
/* Read as 1 if PendSV exception is active */
uint32_t PENDSVACT : 1;
/* Read as 1 if SYSTICK exception is active */
uint32_t SYSTICKACT : 1;
/* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
uint32_t USGFAULTPENDED : 1;
/* Memory management fault pended; memory management fault started but was replaced by a
higher-priority exception */
uint32_t MEMFAULTPENDED : 1;
/* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
exception */
uint32_t BUSFAULTPENDED : 1;
/* SVC pended; SVC was started but was replaced by a higher-priority exception */
uint32_t SVCALLPENDED : 1;
/* Memory management fault handler enable */
uint32_t MEMFAULTENA : 1;
/* Bus fault handler enable */
uint32_t BUSFAULTENA : 1;
/* Usage fault handler enable */
uint32_t USGFAULTENA : 1;
} bits;
} syshndctrl;
union {
uint32_t value;
struct {
union {
/* Memory Management Fault Status Register (0xE000ED28) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IACCVIOL : 1;
/* Data access violation */
uint8_t DACCVIOL : 1;
uint8_t UnusedBits : 1;
/* Unstacking error */
uint8_t MUNSTKERR : 1;
/* Stacking error */
uint8_t MSTKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t MLSPERR : 1;
uint8_t UnusedBits2 : 1;
/* Indicates the MMAR is valid */
uint8_t MMARVALID : 1;
} bits;
} mfsr;
union {
/* Bus Fault Status Register (0xE000ED29) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IBUSERR : 1;
/* Precise data access violation */
uint8_t PRECISERR : 1;
/* Imprecise data access violation */
uint8_t IMPREISERR : 1;
/* Unstacking error */
uint8_t UNSTKERR : 1;
/* Stacking error */
uint8_t STKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t LSPERR : 1;
uint8_t UnusedBits : 1;
/* Indicates BFAR is valid */
uint8_t BFARVALID : 1;
} bits;
} bfsr;
union {
/* Usage Fault Status Register (0xE000ED2A) */
uint16_t value;
struct {
/* Attempts to execute an undefined instruction */
uint16_t UNDEFINSTR : 1;
/* Attempts to switch to an invalid state (e.g., ARM) */
uint16_t INVSTATE : 1;
/* Attempts to do an exception with a bad value in the EXC_RETURN number */
uint16_t INVPC : 1;
/* Attempts to execute a coprocessor instruction */
uint16_t NOCP : 1;
uint16_t UnusedBits : 4;
/* Indicates that an unaligned access fault has taken place */
uint16_t UNALIGNED : 1;
/* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
uint16_t DIVBYZERO0 : 1;
} bits;
} ufsr;
} part;
} cfsr;
/* Memory Management Fault Address Register (0xE000ED34) */
uint32_t mmar;
/* Bus Fault Manage Address Register (0xE000ED38) */
uint32_t bfar;
union {
/* Hard Fault Status Register (0xE000ED2C) */
uint32_t value;
struct {
uint32_t UnusedBits : 1;
/* Indicates hard fault is caused by failed vector fetch */
uint32_t VECTBL : 1;
uint32_t UnusedBits2 : 28;
/* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
uint32_t FORCED : 1;
/* Indicates hard fault is triggered by debug event */
uint32_t DEBUGEVT : 1;
} bits;
} hfsr;
union {
/* Debug Fault Status Register (0xE000ED30) */
uint32_t value;
struct {
/* Halt requested in NVIC */
uint32_t HALTED : 1;
/* BKPT instruction executed */
uint32_t BKPT : 1;
/* DWT match occurred */
uint32_t DWTTRAP : 1;
/* Vector fetch occurred */
uint32_t VCATCH : 1;
/* EDBGRQ signal asserted */
uint32_t EXTERNAL : 1;
} bits;
} dfsr;
/* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
uint32_t afsr;
} port_fault_regs_t;
enum fault_info {
FAULT_INFO_ASSERT_ON_THREAD,
FAULT_INFO_HFSR_VECTBL,
FAULT_INFO_MFSR_IACCVIOL,
FAULT_INFO_MFSR_DACCVIOL,
FAULT_INFO_MFSR_MUNSTKERR,
FAULT_INFO_MFSR_MSTKERR,
FAULT_INFO_MFSR_MLSPERR,
FAULT_INFO_BFSR_IBUSERR,
FAULT_INFO_BFSR_PRECISERR,
FAULT_INFO_BFSR_IMPREISERR,
FAULT_INFO_BFSR_UNSTKERR,
FAULT_INFO_BFSR_STKERR,
FAULT_INFO_BFSR_LSPERR,
FAULT_INFO_UFSR_UNDEFINSTR,
FAULT_INFO_UFSR_INVSTATE,
FAULT_INFO_UFSR_INVPC,
FAULT_INFO_UFSR_NOCP,
FAULT_INFO_UFSR_UNALIGNED,
FAULT_INFO_UFSR_DIVBYZERO0,
FAULT_INFO_DFSR_HALTED,
FAULT_INFO_DFSR_BKPT,
FAULT_INFO_DFSR_DWTTRAP,
FAULT_INFO_DFSR_VCATCH,
FAULT_INFO_DFSR_EXTERNAL,
FAULT_INFO_MMAR,
FAULT_INFO_BFAR,
};
static const char *const fault_msg[] = {
[FAULT_INFO_ASSERT_ON_THREAD] = "Assert on thread %s\n",
[FAULT_INFO_HFSR_VECTBL] = "Hard fault is caused by failed vector fetch\n",
[FAULT_INFO_MFSR_IACCVIOL] = "Memory management fault: instruction access violation\n",
[FAULT_INFO_MFSR_DACCVIOL] = "Memory management fault: data access violation\n",
[FAULT_INFO_MFSR_MUNSTKERR] = "Memory management fault: unstacking error\n",
[FAULT_INFO_MFSR_MSTKERR] = "Memory management fault: stacking error\n",
[FAULT_INFO_MFSR_MLSPERR] = "Memory management fault: floating-point lazy state preservation\n",
[FAULT_INFO_BFSR_IBUSERR] = "Bus fault: instruction access violation\n",
[FAULT_INFO_BFSR_PRECISERR] = "Bus fault: precise data access violation\n",
[FAULT_INFO_BFSR_IMPREISERR] = "Bus fault: imprecise data access violation\n",
[FAULT_INFO_BFSR_UNSTKERR] = "Bus fault: unstacking error\n",
[FAULT_INFO_BFSR_STKERR] = "Bus fault: stacking error\n",
[FAULT_INFO_BFSR_LSPERR] = "Bus fault: floating-point lazy state preservation\n",
[FAULT_INFO_UFSR_UNDEFINSTR] = "Usage fault: undefined instruction\n",
[FAULT_INFO_UFSR_INVSTATE] = "Usage fault: invalid state (e.g., ARM)\n",
[FAULT_INFO_UFSR_INVPC] = "Usage fault: invalid EXC_RETURN\n",
[FAULT_INFO_UFSR_NOCP] = "Usage fault: coprocessor instruction\n",
[FAULT_INFO_UFSR_UNALIGNED] = "Usage fault: unaligned access\n",
[FAULT_INFO_UFSR_DIVBYZERO0] = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
[FAULT_INFO_DFSR_HALTED] = "Debug fault: halt requested in NVIC\n",
[FAULT_INFO_DFSR_BKPT] = "Debug fault: BKPT instruction executed\n",
[FAULT_INFO_DFSR_DWTTRAP] = "Debug fault: DWT match occurred\n",
[FAULT_INFO_DFSR_VCATCH] = "Debug fault: Vector fetch occurred\n",
[FAULT_INFO_DFSR_EXTERNAL] = "Debug fault: EDBGRQ signal asserted\n",
[FAULT_INFO_MMAR] = "The memory management fault occurred address is %08x\n",
[FAULT_INFO_BFAR] = "The bus fault occurred address is %08x\n",
};
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
__PORT__ uint32_t port_clz(uint32_t val);
#endif
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#endif /* _PORT_H_ */

View File

@@ -1,255 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "tos_k.h"
#include "core_cm33.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
(void)SysTick_Config(cycle_per_tick);
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTick_IRQn, prio);
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
port_systick_config(cycle_per_tick);
}
__PORT__ void port_systick_pending_reset(void)
{
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
#if 1
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#endif
}
__PORT__ void port_stop_mode_enter(void)
{
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
HAL_PWR_EnterSTANDBYMode();
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
{
k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
if (regs->hfsr.bits.VECTBL) {
k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
}
if (regs->hfsr.bits.FORCED) {
/* Memory Management Fault */
if (regs->cfsr.part.mfsr.value) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MLSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
}
if (regs->cfsr.part.mfsr.bits.MMARVALID) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
}
}
}
/* Bus Fault */
if (regs->cfsr.part.bfsr.value) {
if (regs->cfsr.part.bfsr.bits.IBUSERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
}
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
}
if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
}
if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
}
if (regs->cfsr.part.bfsr.bits.STKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
}
if (regs->cfsr.part.bfsr.bits.LSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
}
if (regs->cfsr.part.bfsr.bits.BFARVALID) {
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
}
}
}
/* Usage Fault */
if (regs->cfsr.part.ufsr.value) {
if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
}
if (regs->cfsr.part.ufsr.bits.INVSTATE) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
}
if (regs->cfsr.part.ufsr.bits.INVPC) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
}
if (regs->cfsr.part.ufsr.bits.NOCP) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
}
if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
}
if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
}
}
}
/* Debug Fault */
if (regs->hfsr.bits.DEBUGEVT) {
if (regs->dfsr.value) {
if (regs->dfsr.bits.HALTED) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
}
if (regs->dfsr.bits.BKPT) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
}
if (regs->dfsr.bits.DWTTRAP) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
}
if (regs->dfsr.bits.VCATCH) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
}
if (regs->dfsr.bits.EXTERNAL) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
}
}
}
}
__PORT__ void port_fault_diagnosis(void)
{
port_fault_regs_t regs;
regs.syshndctrl.value = SCB->SHCSR;
regs.cfsr.value = SCB->CFSR;
regs.mmar = SCB->MMFAR;
regs.bfar = SCB->BFAR;
regs.hfsr.value = SCB->HFSR;
regs.dfsr.value = SCB->DFSR;
regs.afsr = SCB->AFSR;
port_fault_do_diagnosis(&regs);
}
__PORT__ void __NAKED__ HardFault_Handler(void)
{
__ASM__ __VOLATILE__ (
"MOV r0, lr\n\t"
"TST lr, #0x04\n\t"
"ITE EQ\n\t"
"MRSEQ r1, MSP\n\t"
"MRSNE r1, PSP\n\t"
"BL fault_backtrace\n\t"
);
}
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

View File

@@ -1,36 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 1u
#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
#define TOS_CFG_CPU_ARM_FPU_EN 1u
#else
#define TOS_CFG_CPU_ARM_FPU_EN 0u
#endif
#endif /* _PORT_CONFIG_H_ */

View File

@@ -1,202 +0,0 @@
.global port_int_disable
.global port_int_enable
.global port_cpsr_save
.global port_cpsr_restore
.global port_sched_start
.global port_context_switch
.global port_irq_context_switch
.global port_clz
.global PendSV_Handler
.extern k_curr_task
.extern k_next_task
.equ SCB_VTOR, 0xE000ED08
.equ NVIC_INT_CTRL, 0xE000ED04
.equ NVIC_SYSPRI14, 0xE000ED22
.equ NVIC_PENDSV_PRI, 0xFF
.equ NVIC_PENDSVSET, 0x10000000
.text
.align 2
.thumb
.syntax unified
.type port_int_disable, %function
port_int_disable:
CPSID I
BX LR
.type port_int_enable, %function
port_int_enable:
CPSIE I
BX LR
.type port_cpsr_save, %function
port_cpsr_save:
MRS R0, PRIMASK
CPSID I
BX LR
.type port_cpsr_restore, %function
port_cpsr_restore:
MSR PRIMASK, R0
BX LR
.type port_clz, %function
port_clz:
CLZ R0, R0
BX LR
.thumb_func
.type port_sched_start, %function
port_sched_start:
CPSID I
@ set pendsv priority lowest
@ otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
@ that would be a disaster
MOVW R0, #:lower16:NVIC_SYSPRI14
MOVT R0, #:upper16:NVIC_SYSPRI14
MOVW R1, #:lower16:NVIC_PENDSV_PRI
MOVT R1, #:upper16:NVIC_PENDSV_PRI
STRB R1, [R0]
MOVW R0, #:lower16:SCB_VTOR
MOVT R0, #:upper16:SCB_VTOR
LDR R0, [R0]
LDR R0, [R0]
MSR MSP, R0
MOVW R0, #:lower16:k_curr_task
MOVT R0, #:upper16:k_curr_task
@ k_curr_task = k_next_task;
MOVW R1, #:lower16:k_next_task
MOVT R1, #:upper16:k_next_task
LDR R2, [R1]
STR R2, [R0]
@ sp = k_next_task->sp
LDR R0, [R2]
@ PSP = sp
MSR PSP, R0
MRS R0, CONTROL
ORR R0, R0, #2
MSR CONTROL, R0
ISB
@ restore r4-11 from new process stack
LDMFD SP!, {R4 - R11}
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@ ignore EXC_RETURN the first switch
LDMFD SP!, {R0}
#endif
@ restore r0, r3
LDMFD SP!, {R0 - R3}
@ load R12 and LR
LDMFD SP!, {R12, LR}
@ load PC and discard xPSR
LDMFD SP!, {R1, R2}
CPSIE I
BX R1
.thumb_func
.type port_context_switch, %function
port_context_switch:
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
.thumb_func
.type port_irq_context_switch, %function
port_irq_context_switch:
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
.thumb_func
.type PendSV_Handler, %function
PendSV_Handler:
CPSID I
MRS R0, PSP
_context_save:
@ R0-R3, R12, LR, PC, xPSR is saved automatically here
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@ is it extended frame?
TST LR, #0x10
IT EQ
VSTMDBEQ R0!, {S16 - S31}
@ S0 - S16, FPSCR saved automatically here
@ save EXC_RETURN
STMFD R0!, {LR}
#endif
@ save remaining regs r4 - 11 on process stack
STMFD R0!, {R4 - R11}
@ k_curr_task->sp = PSP;
MOVW R5, #:lower16:k_curr_task
MOVT R5, #:upper16:k_curr_task
LDR R6, [R5]
@ R0 is SP of process being switched out
STR R0, [R6]
_context_restore:
@ k_curr_task = k_next_task;
MOVW R1, #:lower16:k_next_task
MOVT R1, #:upper16:k_next_task
LDR R2, [R1]
STR R2, [R5]
@ R0 = k_next_task->sp
LDR R0, [R2]
@ restore R4 - R11
LDMFD R0!, {R4 - R11}
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@ restore EXC_RETURN
LDMFD R0!, {LR}
@ is it extended frame?
TST LR, #0x10
IT EQ
VLDMIAEQ R0!, {S16 - S31}
#endif
@ Load PSP with new process SP
MSR PSP, R0
CPSIE I
@ R0-R3, R12, LR, PC, xPSR restored automatically here
@ S0 - S16, FPSCR restored automatically here if FPCA = 1
BX LR
.end

View File

@@ -1,312 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _PORT_H_
#define _PORT_H_
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
typedef struct port_fault_regs {
union {
/* System Handler Control and State Register (0xE000ED24) */
uint32_t value;
struct {
/* Read as 1 if memory management fault is active */
uint32_t MEMFAULTACT : 1;
/* Read as 1 if bus fault exception is active */
uint32_t BUSFAULTACT : 1;
uint32_t UnusedBits1 : 1;
/* Read as 1 if usage fault exception is active */
uint32_t USGFAULTACT : 1;
uint32_t UnusedBits2 : 3;
/* Read as 1 if SVC exception is active */
uint32_t SVCALLACT : 1;
/* Read as 1 if debug monitor exception is active */
uint32_t MONITORACT : 1;
uint32_t UnusedBits3 : 1;
/* Read as 1 if PendSV exception is active */
uint32_t PENDSVACT : 1;
/* Read as 1 if SYSTICK exception is active */
uint32_t SYSTICKACT : 1;
/* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
uint32_t USGFAULTPENDED : 1;
/* Memory management fault pended; memory management fault started but was replaced by a
higher-priority exception */
uint32_t MEMFAULTPENDED : 1;
/* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
exception */
uint32_t BUSFAULTPENDED : 1;
/* SVC pended; SVC was started but was replaced by a higher-priority exception */
uint32_t SVCALLPENDED : 1;
/* Memory management fault handler enable */
uint32_t MEMFAULTENA : 1;
/* Bus fault handler enable */
uint32_t BUSFAULTENA : 1;
/* Usage fault handler enable */
uint32_t USGFAULTENA : 1;
} bits;
} syshndctrl;
union {
uint32_t value;
struct {
union {
/* Memory Management Fault Status Register (0xE000ED28) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IACCVIOL : 1;
/* Data access violation */
uint8_t DACCVIOL : 1;
uint8_t UnusedBits : 1;
/* Unstacking error */
uint8_t MUNSTKERR : 1;
/* Stacking error */
uint8_t MSTKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t MLSPERR : 1;
uint8_t UnusedBits2 : 1;
/* Indicates the MMAR is valid */
uint8_t MMARVALID : 1;
} bits;
} mfsr;
union {
/* Bus Fault Status Register (0xE000ED29) */
uint8_t value;
struct {
/* Instruction access violation */
uint8_t IBUSERR : 1;
/* Precise data access violation */
uint8_t PRECISERR : 1;
/* Imprecise data access violation */
uint8_t IMPREISERR : 1;
/* Unstacking error */
uint8_t UNSTKERR : 1;
/* Stacking error */
uint8_t STKERR : 1;
/* Floating-point lazy state preservation (M4/M7) */
uint8_t LSPERR : 1;
uint8_t UnusedBits : 1;
/* Indicates BFAR is valid */
uint8_t BFARVALID : 1;
} bits;
} bfsr;
union {
/* Usage Fault Status Register (0xE000ED2A) */
uint16_t value;
struct {
/* Attempts to execute an undefined instruction */
uint16_t UNDEFINSTR : 1;
/* Attempts to switch to an invalid state (e.g., ARM) */
uint16_t INVSTATE : 1;
/* Attempts to do an exception with a bad value in the EXC_RETURN number */
uint16_t INVPC : 1;
/* Attempts to execute a coprocessor instruction */
uint16_t NOCP : 1;
uint16_t UnusedBits : 4;
/* Indicates that an unaligned access fault has taken place */
uint16_t UNALIGNED : 1;
/* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
uint16_t DIVBYZERO0 : 1;
} bits;
} ufsr;
} part;
} cfsr;
/* Memory Management Fault Address Register (0xE000ED34) */
uint32_t mmar;
/* Bus Fault Manage Address Register (0xE000ED38) */
uint32_t bfar;
union {
/* Hard Fault Status Register (0xE000ED2C) */
uint32_t value;
struct {
uint32_t UnusedBits : 1;
/* Indicates hard fault is caused by failed vector fetch */
uint32_t VECTBL : 1;
uint32_t UnusedBits2 : 28;
/* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
uint32_t FORCED : 1;
/* Indicates hard fault is triggered by debug event */
uint32_t DEBUGEVT : 1;
} bits;
} hfsr;
union {
/* Debug Fault Status Register (0xE000ED30) */
uint32_t value;
struct {
/* Halt requested in NVIC */
uint32_t HALTED : 1;
/* BKPT instruction executed */
uint32_t BKPT : 1;
/* DWT match occurred */
uint32_t DWTTRAP : 1;
/* Vector fetch occurred */
uint32_t VCATCH : 1;
/* EDBGRQ signal asserted */
uint32_t EXTERNAL : 1;
} bits;
} dfsr;
/* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
uint32_t afsr;
} port_fault_regs_t;
enum fault_info {
FAULT_INFO_ASSERT_ON_THREAD,
FAULT_INFO_HFSR_VECTBL,
FAULT_INFO_MFSR_IACCVIOL,
FAULT_INFO_MFSR_DACCVIOL,
FAULT_INFO_MFSR_MUNSTKERR,
FAULT_INFO_MFSR_MSTKERR,
FAULT_INFO_MFSR_MLSPERR,
FAULT_INFO_BFSR_IBUSERR,
FAULT_INFO_BFSR_PRECISERR,
FAULT_INFO_BFSR_IMPREISERR,
FAULT_INFO_BFSR_UNSTKERR,
FAULT_INFO_BFSR_STKERR,
FAULT_INFO_BFSR_LSPERR,
FAULT_INFO_UFSR_UNDEFINSTR,
FAULT_INFO_UFSR_INVSTATE,
FAULT_INFO_UFSR_INVPC,
FAULT_INFO_UFSR_NOCP,
FAULT_INFO_UFSR_UNALIGNED,
FAULT_INFO_UFSR_DIVBYZERO0,
FAULT_INFO_DFSR_HALTED,
FAULT_INFO_DFSR_BKPT,
FAULT_INFO_DFSR_DWTTRAP,
FAULT_INFO_DFSR_VCATCH,
FAULT_INFO_DFSR_EXTERNAL,
FAULT_INFO_MMAR,
FAULT_INFO_BFAR,
};
static const char *const fault_msg[] = {
[FAULT_INFO_ASSERT_ON_THREAD] = "Assert on thread %s\n",
[FAULT_INFO_HFSR_VECTBL] = "Hard fault is caused by failed vector fetch\n",
[FAULT_INFO_MFSR_IACCVIOL] = "Memory management fault: instruction access violation\n",
[FAULT_INFO_MFSR_DACCVIOL] = "Memory management fault: data access violation\n",
[FAULT_INFO_MFSR_MUNSTKERR] = "Memory management fault: unstacking error\n",
[FAULT_INFO_MFSR_MSTKERR] = "Memory management fault: stacking error\n",
[FAULT_INFO_MFSR_MLSPERR] = "Memory management fault: floating-point lazy state preservation\n",
[FAULT_INFO_BFSR_IBUSERR] = "Bus fault: instruction access violation\n",
[FAULT_INFO_BFSR_PRECISERR] = "Bus fault: precise data access violation\n",
[FAULT_INFO_BFSR_IMPREISERR] = "Bus fault: imprecise data access violation\n",
[FAULT_INFO_BFSR_UNSTKERR] = "Bus fault: unstacking error\n",
[FAULT_INFO_BFSR_STKERR] = "Bus fault: stacking error\n",
[FAULT_INFO_BFSR_LSPERR] = "Bus fault: floating-point lazy state preservation\n",
[FAULT_INFO_UFSR_UNDEFINSTR] = "Usage fault: undefined instruction\n",
[FAULT_INFO_UFSR_INVSTATE] = "Usage fault: invalid state (e.g., ARM)\n",
[FAULT_INFO_UFSR_INVPC] = "Usage fault: invalid EXC_RETURN\n",
[FAULT_INFO_UFSR_NOCP] = "Usage fault: coprocessor instruction\n",
[FAULT_INFO_UFSR_UNALIGNED] = "Usage fault: unaligned access\n",
[FAULT_INFO_UFSR_DIVBYZERO0] = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
[FAULT_INFO_DFSR_HALTED] = "Debug fault: halt requested in NVIC\n",
[FAULT_INFO_DFSR_BKPT] = "Debug fault: BKPT instruction executed\n",
[FAULT_INFO_DFSR_DWTTRAP] = "Debug fault: DWT match occurred\n",
[FAULT_INFO_DFSR_VCATCH] = "Debug fault: Vector fetch occurred\n",
[FAULT_INFO_DFSR_EXTERNAL] = "Debug fault: EDBGRQ signal asserted\n",
[FAULT_INFO_MMAR] = "The memory management fault occurred address is %08x\n",
[FAULT_INFO_BFAR] = "The bus fault occurred address is %08x\n",
};
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
__PORT__ uint32_t port_clz(uint32_t val);
#endif
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#endif /* _PORT_H_ */

View File

@@ -1,261 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
/*
* The MIT License (MIT)
*
* Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* 'Software'), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "tos_k.h"
#include "core_cm33.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
(void)SysTick_Config(cycle_per_tick);
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTick_IRQn, prio);
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
{
return SysTick_LOAD_RELOAD_Msk;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
port_systick_config(cycle_per_tick);
}
__PORT__ void port_systick_pending_reset(void)
{
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
#if 1
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#endif
}
__PORT__ void port_stop_mode_enter(void)
{
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
HAL_PWR_EnterSTANDBYMode();
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
{
k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
if (regs->hfsr.bits.VECTBL) {
k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
}
if (regs->hfsr.bits.FORCED) {
/* Memory Management Fault */
if (regs->cfsr.part.mfsr.value) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
}
if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
}
if (regs->cfsr.part.mfsr.bits.MLSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
}
if (regs->cfsr.part.mfsr.bits.MMARVALID) {
if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
}
}
}
/* Bus Fault */
if (regs->cfsr.part.bfsr.value) {
if (regs->cfsr.part.bfsr.bits.IBUSERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
}
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
}
if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
}
if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
}
if (regs->cfsr.part.bfsr.bits.STKERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
}
if (regs->cfsr.part.bfsr.bits.LSPERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
}
if (regs->cfsr.part.bfsr.bits.BFARVALID) {
if (regs->cfsr.part.bfsr.bits.PRECISERR) {
k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
}
}
}
/* Usage Fault */
if (regs->cfsr.part.ufsr.value) {
if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
}
if (regs->cfsr.part.ufsr.bits.INVSTATE) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
}
if (regs->cfsr.part.ufsr.bits.INVPC) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
}
if (regs->cfsr.part.ufsr.bits.NOCP) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
}
if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
}
if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
}
}
}
/* Debug Fault */
if (regs->hfsr.bits.DEBUGEVT) {
if (regs->dfsr.value) {
if (regs->dfsr.bits.HALTED) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
}
if (regs->dfsr.bits.BKPT) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
}
if (regs->dfsr.bits.DWTTRAP) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
}
if (regs->dfsr.bits.VCATCH) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
}
if (regs->dfsr.bits.EXTERNAL) {
k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
}
}
}
}
__PORT__ void port_fault_diagnosis(void)
{
port_fault_regs_t regs;
regs.syshndctrl.value = SCB->SHCSR;
regs.cfsr.value = SCB->CFSR;
regs.mmar = SCB->MMFAR;
regs.bfar = SCB->BFAR;
regs.hfsr.value = SCB->HFSR;
regs.dfsr.value = SCB->DFSR;
regs.afsr = SCB->AFSR;
port_fault_do_diagnosis(&regs);
}
__PORT__ void __NAKED__ HardFault_Handler(void)
{
__ASM__ __VOLATILE__ (
"MOV r0, lr\n\t"
"TST lr, #0x04\n\t"
"ITE EQ\n\t"
"MRSEQ r1, MSP\n\t"
"MRSNE r1, PSP\n\t"
"LDR r2, =fault_backtrace\n\t"
"BX r2\n\t"
);
}
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

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@@ -1,36 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 1u
#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN
#ifndef __ARMVFP__
#define TOS_CFG_CPU_ARM_FPU_EN 0u
#else
#define TOS_CFG_CPU_ARM_FPU_EN 1u
#endif
#endif /* _PORT_CONFIG_H_ */

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@@ -1,176 +0,0 @@
PUBLIC port_int_disable
PUBLIC port_int_enable
PUBLIC port_cpsr_save
PUBLIC port_cpsr_restore
PUBLIC port_sched_start
PUBLIC port_context_switch
PUBLIC port_irq_context_switch
PUBLIC port_clz
PUBLIC PendSV_Handler
EXTERN k_curr_task
EXTERN k_next_task
SCB_VTOR EQU 0xE000ED08
NVIC_INT_CTRL EQU 0xE000ED04
NVIC_SYSPRI14 EQU 0xE000ED22
NVIC_PENDSV_PRI EQU 0xFF
NVIC_PENDSVSET EQU 0x10000000
RSEG CODE:CODE:NOROOT(2)
THUMB
port_int_disable
CPSID I
BX LR
port_int_enable
CPSIE I
BX LR
port_cpsr_save
MRS R0, PRIMASK
CPSID I
BX LR
port_cpsr_restore
MSR PRIMASK, R0
BX LR
port_clz
CLZ R0, R0
BX LR
port_sched_start
CPSID I
; set pendsv priority lowest
; otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
; that would be a disaster
MOV32 R0, NVIC_SYSPRI14
MOV32 R1, NVIC_PENDSV_PRI
STRB R1, [R0]
LDR R0, =SCB_VTOR
LDR R0, [R0]
LDR R0, [R0]
MSR MSP, R0
; k_curr_task = k_next_task
MOV32 R0, k_curr_task
MOV32 R1, k_next_task
LDR R2, [R1]
STR R2, [R0]
; sp = k_next_task->sp
LDR R0, [R2]
; PSP = sp
MSR PSP, R0
; using PSP
MRS R0, CONTROL
ORR R0, R0, #2
MSR CONTROL, R0
ISB
; restore r4-11 from new process stack
LDMFD SP!, {R4 - R11}
#if defined(__ARMVFP__)
; ignore EXC_RETURN the first switch
LDMFD SP!, {R0}
#endif
; restore r0, r3
LDMFD SP!, {R0 - R3}
; load R12 and LR
LDMFD SP!, {R12, LR}
; load PC and discard xPSR
LDMFD SP!, {R1, R2}
CPSIE I
BX R1
port_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
port_irq_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
PendSV_Handler
CPSID I
MRS R0, PSP
_context_save
; R0-R3, R12, LR, PC, xPSR is saved automatically here
#if defined(__ARMVFP__)
; is it extended frame?
TST LR, #0x10
IT EQ
VSTMDBEQ R0!, {S16 - S31}
; S0 - S16, FPSCR saved automatically here
; save EXC_RETURN
STMFD R0!, {LR}
#endif
; save remaining regs r4-11 on process stack
STMFD R0!, {R4 - R11}
; k_curr_task->sp = PSP
MOV32 R5, k_curr_task
LDR R6, [R5]
; R0 is SP of process being switched out
STR R0, [R6]
_context_restore
; k_curr_task = k_next_task
MOV32 R1, k_next_task
LDR R2, [R1]
STR R2, [R5]
; R0 = k_next_task->sp
LDR R0, [R2]
; restore R4 - R11
LDMFD R0!, {R4 - R11}
#if defined(__ARMVFP__)
; restore EXC_RETURN
LDMFD R0!, {LR}
; is it extended frame?
TST LR, #0x10
IT EQ
VLDMIAEQ R0!, {S16 - S31}
#endif
; Load PSP with new process SP
MSR PSP, R0
CPSIE I
; R0-R3, R12, LR, PC, xPSR restored automatically here
; S0 - S16, FPSCR restored automatically here if FPCA = 1
BX LR
END

File diff suppressed because one or more lines are too long

View File

@@ -1,544 +0,0 @@
#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
ADC1.master=1
Dma.Request0=SDMMC1_RX
Dma.Request1=SDMMC1_TX
Dma.RequestsNb=2
Dma.SDMMC1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.SDMMC1_RX.0.Instance=DMA2_Channel4
Dma.SDMMC1_RX.0.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.SDMMC1_RX.0.MemInc=DMA_MINC_ENABLE
Dma.SDMMC1_RX.0.Mode=DMA_NORMAL
Dma.SDMMC1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDMMC1_RX.0.PeriphInc=DMA_PINC_DISABLE
Dma.SDMMC1_RX.0.Priority=DMA_PRIORITY_LOW
Dma.SDMMC1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.SDMMC1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
Dma.SDMMC1_TX.1.Instance=DMA2_Channel5
Dma.SDMMC1_TX.1.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.SDMMC1_TX.1.MemInc=DMA_MINC_ENABLE
Dma.SDMMC1_TX.1.Mode=DMA_NORMAL
Dma.SDMMC1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDMMC1_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.SDMMC1_TX.1.Priority=DMA_PRIORITY_LOW
Dma.SDMMC1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
File.Version=6
I2C2.IPParameters=Timing
I2C2.Timing=0x20303E5D
I2C3.I2C_Speed_Mode=I2C_Fast
I2C3.IPParameters=Timing,I2C_Speed_Mode
I2C3.Timing=0x2010091A
IWDG.IPParameters=Prescaler,Reload
IWDG.Prescaler=IWDG_PRESCALER_256
IWDG.Reload=3999
KeepUserPlacement=false
Mcu.Family=STM32L4
Mcu.IP0=ADC1
Mcu.IP1=DAC1
Mcu.IP10=SDMMC1
Mcu.IP11=SPI2
Mcu.IP12=SYS
Mcu.IP13=TIM2
Mcu.IP14=UART4
Mcu.IP15=USART1
Mcu.IP16=USART2
Mcu.IP17=USART3
Mcu.IP18=USB_HOST
Mcu.IP19=USB_OTG_FS
Mcu.IP2=DMA
Mcu.IP3=I2C2
Mcu.IP4=I2C3
Mcu.IP5=IWDG
Mcu.IP6=LPUART1
Mcu.IP7=NVIC
Mcu.IP8=RCC
Mcu.IP9=SAI2
Mcu.IPNb=20
Mcu.Name=STM32L496V(E-G)Tx
Mcu.Package=LQFP100
Mcu.Pin0=PE2
Mcu.Pin1=PE3
Mcu.Pin10=PC1
Mcu.Pin11=PC2
Mcu.Pin12=PA0
Mcu.Pin13=PA1
Mcu.Pin14=PA2
Mcu.Pin15=PA3
Mcu.Pin16=PA4
Mcu.Pin17=PA5
Mcu.Pin18=PA6
Mcu.Pin19=PC4
Mcu.Pin2=PE5
Mcu.Pin20=PC5
Mcu.Pin21=PB0
Mcu.Pin22=PB1
Mcu.Pin23=PB2
Mcu.Pin24=PE7
Mcu.Pin25=PE8
Mcu.Pin26=PE9
Mcu.Pin27=PE11
Mcu.Pin28=PE12
Mcu.Pin29=PE13
Mcu.Pin3=PE6
Mcu.Pin30=PE14
Mcu.Pin31=PE15
Mcu.Pin32=PB10
Mcu.Pin33=PB11
Mcu.Pin34=PB12
Mcu.Pin35=PB13
Mcu.Pin36=PB14
Mcu.Pin37=PB15
Mcu.Pin38=PD8
Mcu.Pin39=PD9
Mcu.Pin4=PC13
Mcu.Pin40=PD10
Mcu.Pin41=PD11
Mcu.Pin42=PD12
Mcu.Pin43=PD13
Mcu.Pin44=PD15
Mcu.Pin45=PC6
Mcu.Pin46=PC7
Mcu.Pin47=PC8
Mcu.Pin48=PC9
Mcu.Pin49=PA8
Mcu.Pin5=PC14-OSC32_IN (PC14)
Mcu.Pin50=PA9
Mcu.Pin51=PA11
Mcu.Pin52=PA12
Mcu.Pin53=PC10
Mcu.Pin54=PC11
Mcu.Pin55=PC12
Mcu.Pin56=PD0
Mcu.Pin57=PD1
Mcu.Pin58=PD2
Mcu.Pin59=PD3
Mcu.Pin6=PC15-OSC32_OUT (PC15)
Mcu.Pin60=PD4
Mcu.Pin61=PD5
Mcu.Pin62=PD6
Mcu.Pin63=PD7
Mcu.Pin64=PB5
Mcu.Pin65=PB6
Mcu.Pin66=PB7
Mcu.Pin67=PB8
Mcu.Pin68=PB9
Mcu.Pin69=PE0
Mcu.Pin7=PH0-OSC_IN (PH0)
Mcu.Pin70=PE1
Mcu.Pin71=VP_IWDG_VS_IWDG
Mcu.Pin72=VP_SAI2_VP_$IpInstance_SAIA_SAI_BASIC
Mcu.Pin73=VP_SYS_VS_Systick
Mcu.Pin74=VP_TIM2_VS_ClockSourceINT
Mcu.Pin75=VP_USB_HOST_VS_USB_HOST_CDC_FS
Mcu.Pin8=PH1-OSC_OUT (PH1)
Mcu.Pin9=PC0
Mcu.PinsNb=76
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32L496VGTx
MxCube.Version=4.26.0
MxDb.Version=DB.4.0.260
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DMA2_Channel4_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DMA2_Channel5_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SDMMC1_IRQn=true\:0\:0\:false\:false\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:true
NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true
NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false
PA0.Locked=true
PA0.Mode=Asynchronous
PA0.Signal=UART4_TX
PA1.Locked=true
PA1.Mode=Asynchronous
PA1.Signal=UART4_RX
PA11.Mode=Host_Only
PA11.Signal=USB_OTG_FS_DM
PA12.Mode=Host_Only
PA12.Signal=USB_OTG_FS_DP
PA2.Locked=true
PA2.Mode=Asynchronous
PA2.Signal=USART2_TX
PA3.Locked=true
PA3.Mode=Asynchronous
PA3.Signal=USART2_RX
PA4.Locked=true
PA4.Signal=COMP_DAC11_group
PA5.Locked=true
PA5.Signal=SPI1_SCK
PA6.Locked=true
PA6.Signal=SPI1_MISO
PA8.GPIOParameters=PinState,GPIO_Label
PA8.GPIO_Label=PCIE_RST
PA8.Locked=true
PA8.PinState=GPIO_PIN_SET
PA8.Signal=GPIO_Output
PA9.GPIOParameters=GPIO_Label
PA9.GPIO_Label=PCIE_EN
PA9.Locked=true
PA9.Signal=GPIO_Output
PB0.Locked=true
PB0.Signal=SPI1_NSS
PB1.GPIOParameters=GPIO_Label
PB1.GPIO_Label=GPS_ON
PB1.Locked=true
PB1.Signal=GPIO_Output
PB10.Locked=true
PB10.Mode=Asynchronous
PB10.Signal=LPUART1_RX
PB11.Locked=true
PB11.Mode=Asynchronous
PB11.Signal=LPUART1_TX
PB12.GPIOParameters=GPIO_Label
PB12.GPIO_Label=OLED_RST
PB12.Locked=true
PB12.Signal=GPIO_Output
PB13.Locked=true
PB13.Mode=I2C
PB13.Signal=I2C2_SCL
PB14.Mode=I2C
PB14.Signal=I2C2_SDA
PB15.GPIOParameters=GPIO_Label
PB15.GPIO_Label=OLED_EN
PB15.Locked=true
PB15.Signal=GPIO_Output
PB2.GPIOParameters=GPIO_Label
PB2.GPIO_Label=BD_EN
PB2.Locked=true
PB2.Signal=GPIO_Output
PB5.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
PB5.GPIO_Label=LED4
PB5.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PB5.Locked=true
PB5.PinState=GPIO_PIN_SET
PB5.Signal=GPIO_Output
PB6.Locked=true
PB6.Mode=Asynchronous
PB6.Signal=USART1_TX
PB7.Mode=Asynchronous
PB7.Signal=USART1_RX
PB8.GPIOParameters=GPIO_Label
PB8.GPIO_Label=LED3
PB8.Locked=true
PB8.Signal=GPIO_Output
PB9.GPIOParameters=GPIO_Label
PB9.GPIO_Label=IR_OUT
PB9.Locked=true
PB9.Signal=GPIO_Output
PC0.Mode=I2C
PC0.Signal=I2C3_SCL
PC1.Mode=I2C
PC1.Signal=I2C3_SDA
PC10.Mode=SD_4_bits_Wide_bus
PC10.Signal=SDMMC1_D2
PC11.Mode=SD_4_bits_Wide_bus
PC11.Signal=SDMMC1_D3
PC12.Mode=SD_4_bits_Wide_bus
PC12.Signal=SDMMC1_CK
PC13.GPIOParameters=GPIO_Label
PC13.GPIO_Label=SENSOR_INT2
PC13.Locked=true
PC13.Signal=GPXTI13
PC14-OSC32_IN\ (PC14).Locked=true
PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (PC15).Locked=true
PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
PC2.Locked=true
PC2.Signal=ADCx_IN3
PC4.Locked=true
PC4.Mode=Asynchronous
PC4.Signal=USART3_TX
PC5.Mode=Asynchronous
PC5.Signal=USART3_RX
PC6.GPIOParameters=GPIO_Label
PC6.GPIO_Label=CHARGE_STATE
PC6.Locked=true
PC6.Signal=GPIO_Input
PC7.GPIOParameters=GPIO_Label
PC7.GPIO_Label=CARD_EN
PC7.Locked=true
PC7.Signal=GPIO_Output
PC8.Mode=SD_4_bits_Wide_bus
PC8.Signal=SDMMC1_D0
PC9.Mode=SD_4_bits_Wide_bus
PC9.Signal=SDMMC1_D1
PCC.Checker=true
PCC.Line=STM32L4x6
PCC.MCU=STM32L496V(E-G)Tx
PCC.PartNumber=STM32L496VGTx
PCC.Seq0=0
PCC.Series=STM32L4
PCC.Temperature=25
PCC.Vdd=null
PD0.Locked=true
PD0.Mode=NSS_Signal_Hard_Output
PD0.Signal=SPI2_NSS
PD1.Locked=true
PD1.Mode=Full_Duplex_Master
PD1.Signal=SPI2_SCK
PD10.Locked=true
PD10.Mode=SAI_A_MasterWithClock
PD10.Signal=SAI2_SCK_A
PD11.Locked=true
PD11.Mode=SAI_A_MasterWithClock
PD11.Signal=SAI2_SD_A
PD12.Locked=true
PD12.Mode=SAI_A_MasterWithClock
PD12.Signal=SAI2_FS_A
PD13.GPIOParameters=GPIO_Label
PD13.GPIO_Label=AU_RST
PD13.Locked=true
PD13.Signal=GPIO_Output
PD15.GPIOParameters=GPIO_Label
PD15.GPIO_Label=AU_EN
PD15.Locked=true
PD15.Signal=GPIO_Output
PD2.Mode=SD_4_bits_Wide_bus
PD2.Signal=SDMMC1_CMD
PD3.Mode=Full_Duplex_Master
PD3.Signal=SPI2_MISO
PD4.Locked=true
PD4.Mode=Full_Duplex_Master
PD4.Signal=SPI2_MOSI
PD5.GPIOParameters=GPIO_Label
PD5.GPIO_Label=CARD_EN
PD5.Locked=true
PD5.Signal=GPIO_Output
PD6.GPIOParameters=GPIO_Label
PD6.GPIO_Label=KEY3
PD6.Locked=true
PD6.Signal=GPIO_Input
PD7.GPIOParameters=GPIO_Label
PD7.GPIO_Label=KEY2
PD7.Locked=true
PD7.Signal=GPIO_Input
PD8.GPIOParameters=GPIO_Label
PD8.GPIO_Label=AU_CTR
PD8.Locked=true
PD8.Signal=GPIO_Output
PD9.Locked=true
PD9.Mode=SAI_A_MasterWithClock
PD9.Signal=SAI2_MCLK_A
PE0.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
PE0.GPIO_Label=LED2
PE0.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PE0.Locked=true
PE0.PinState=GPIO_PIN_SET
PE0.Signal=GPIO_Output
PE1.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
PE1.GPIO_Label=LED1
PE1.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PE1.Locked=true
PE1.PinState=GPIO_PIN_SET
PE1.Signal=GPIO_Output
PE11.GPIOParameters=GPIO_Label
PE11.GPIO_Label=NB_EN
PE11.Locked=true
PE11.Signal=GPIO_Output
PE12.GPIOParameters=GPIO_Label
PE12.GPIO_Label=SEL1
PE12.Locked=true
PE12.Signal=GPIO_Input
PE13.GPIOParameters=GPIO_Label
PE13.GPIO_Label=SEL2
PE13.Locked=true
PE13.Signal=GPIO_Input
PE14.GPIOParameters=GPIO_Label
PE14.GPIO_Label=SEL3
PE14.Locked=true
PE14.Signal=GPIO_Input
PE15.GPIOParameters=GPIO_Label
PE15.GPIO_Label=KEY4
PE15.Locked=true
PE15.Signal=GPIO_Input
PE2.GPIOParameters=GPIO_Label
PE2.GPIO_Label=KEY1
PE2.Locked=true
PE2.Signal=GPIO_Input
PE3.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
PE3.GPIO_Label=LED5
PE3.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PE3.Locked=true
PE3.PinState=GPIO_PIN_SET
PE3.Signal=GPIO_Output
PE5.GPIOParameters=GPIO_Label
PE5.GPIO_Label=SENSOR_EN
PE5.Locked=true
PE5.Signal=GPIO_Output
PE6.GPIOParameters=GPIO_Label
PE6.GPIO_Label=SENSOR_INT1
PE6.Locked=true
PE6.Signal=GPXTI6
PE7.GPIOParameters=GPIO_Label
PE7.GPIO_Label=GPS_RST
PE7.Locked=true
PE7.Signal=GPIO_Output
PE8.GPIOParameters=GPIO_Label
PE8.GPIO_Label=NB_RST
PE8.Locked=true
PE8.Signal=GPIO_Output
PE9.GPIOParameters=GPIO_Label
PE9.GPIO_Label=NB_WKUP
PE9.Locked=true
PE9.Signal=GPIO_Output
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=3
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=false
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32L496VGTx
ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.12.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x8000
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=bdw01OS.ioc
ProjectManager.ProjectName=bdw01OS
ProjectManager.StackSize=0x8000
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_DAC1_Init-DAC1-false-HAL-true,6-MX_ADC1_Init-ADC1-false-HAL-true,7-MX_I2C2_Init-I2C2-false-HAL-true,8-MX_I2C3_Init-I2C3-false-HAL-true,9-MX_SAI2_Init-SAI2-false-HAL-true,10-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,11-MX_USB_HOST_Init-USB_HOST-false-HAL-true,12-MX_TIM2_Init-TIM2-false-HAL-true,13-MX_IWDG_Init-IWDG-false-HAL-true,14-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,15-MX_UART4_Init-UART4-false-HAL-true,16-MX_USART3_UART_Init-USART3-false-HAL-true,17-MX_USART2_UART_Init-USART2-false-HAL-true,18-MX_USART1_UART_Init-USART1-false-HAL-true
RCC.ADCFreq_Value=48000000
RCC.AHBFreq_Value=48000000
RCC.APB1Freq_Value=48000000
RCC.APB1TimFreq_Value=48000000
RCC.APB2Freq_Value=48000000
RCC.APB2TimFreq_Value=48000000
RCC.CortexFreq_Value=48000000
RCC.DFSDMFreq_Value=48000000
RCC.FCLKCortexFreq_Value=48000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=48000000
RCC.HSE_VALUE=16000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=48000000
RCC.I2C2Freq_Value=48000000
RCC.I2C3Freq_Value=48000000
RCC.I2C4Freq_Value=48000000
RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSIClockRange,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1P,PLLSAI1PoutputFreq_Value,PLLSAI1Q,PLLSAI1QoutputFreq_Value,PLLSAI1R,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
RCC.LPTIM1Freq_Value=48000000
RCC.LPTIM2Freq_Value=48000000
RCC.LPUART1Freq_Value=48000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=48000000
RCC.MSIClockRange=RCC_MSIRANGE_11
RCC.MSI_VALUE=48000000
RCC.PLLN=40
RCC.PLLPoutputFreq_Value=320000000
RCC.PLLQoutputFreq_Value=320000000
RCC.PLLRCLKFreq_Value=320000000
RCC.PLLSAI1N=12
RCC.PLLSAI1P=RCC_PLLP_DIV4
RCC.PLLSAI1PoutputFreq_Value=48000000
RCC.PLLSAI1Q=RCC_PLLQ_DIV4
RCC.PLLSAI1QoutputFreq_Value=48000000
RCC.PLLSAI1R=RCC_PLLR_DIV4
RCC.PLLSAI1RoutputFreq_Value=48000000
RCC.PLLSAI2PoutputFreq_Value=64000000
RCC.PLLSAI2RoutputFreq_Value=64000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.PWRFreq_Value=48000000
RCC.RNGFreq_Value=48000000
RCC.SAI1Freq_Value=48000000
RCC.SAI2Freq_Value=48000000
RCC.SDMMCFreq_Value=48000000
RCC.SWPMI1Freq_Value=48000000
RCC.SYSCLKFreq_VALUE=48000000
RCC.UART4Freq_Value=48000000
RCC.UART5Freq_Value=48000000
RCC.USART1Freq_Value=48000000
RCC.USART2Freq_Value=48000000
RCC.USART3Freq_Value=48000000
RCC.USBFreq_Value=48000000
RCC.VCOInputFreq_Value=16000000
RCC.VCOOutputFreq_Value=640000000
RCC.VCOSAI1OutputFreq_Value=192000000
RCC.VCOSAI2OutputFreq_Value=128000000
SAI2.IPParameters=Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,Synchro-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,InitProtocol-SAI_A_MasterWithClock,VirtualProtocol-SAI_A_BASIC
SAI2.InitProtocol-SAI_A_MasterWithClock=Enable
SAI2.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A
SAI2.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE
SAI2.Synchro-SAI_A_MasterWithClock=SAI_ASYNCHRONOUS
SAI2.VirtualMode-SAI_A_MasterWithClock=VM_MASTER
SAI2.VirtualProtocol-SAI_A_BASIC=VM_BASIC_PROTOCOL
SDMMC1.ClockDiv=4
SDMMC1.IPParameters=ClockDiv
SH.ADCx_IN3.0=ADC1_IN3,IN3-Single-Ended
SH.ADCx_IN3.ConfNb=1
SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1
SH.COMP_DAC11_group.ConfNb=1
SH.GPXTI13.0=GPIO_EXTI13
SH.GPXTI13.ConfNb=1
SH.GPXTI6.0=GPIO_EXTI6
SH.GPXTI6.ConfNb=1
SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
SPI2.CalculateBaudRate=24.0 MBits/s
SPI2.Direction=SPI_DIRECTION_2LINES
SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler
SPI2.Mode=SPI_MODE_MASTER
SPI2.VirtualNSS=VM_NSSHARD
SPI2.VirtualType=VM_MASTER
TIM2.IPParameters=Prescaler,Period
TIM2.Period=10
TIM2.Prescaler=13260
USART1.BaudRate=115200
USART1.IPParameters=VirtualMode-Asynchronous,BaudRate
USART1.VirtualMode-Asynchronous=VM_ASYNC
USART2.BaudRate=57600
USART2.IPParameters=VirtualMode-Asynchronous,BaudRate
USART2.VirtualMode-Asynchronous=VM_ASYNC
USART3.BaudRate=9600
USART3.IPParameters=VirtualMode-Asynchronous,BaudRate
USART3.VirtualMode-Asynchronous=VM_ASYNC
USB_HOST.IPParameters=VirtualModeFS,USBH_HandleTypeDef,USBH_MAX_NUM_ENDPOINTS,USBH_MAX_NUM_INTERFACES,USBH_DEBUG_LEVEL
USB_HOST.USBH_DEBUG_LEVEL=3
USB_HOST.USBH_HandleTypeDef=hUsbHostFS
USB_HOST.USBH_MAX_NUM_ENDPOINTS=3
USB_HOST.USBH_MAX_NUM_INTERFACES=5
USB_HOST.VirtualModeFS=Cdc
USB_OTG_FS.IPParameters=VirtualMode,phy_itface
USB_OTG_FS.VirtualMode=Host_Only
USB_OTG_FS.phy_itface=HCD_PHY_EMBEDDED
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_SAI2_VP_$IpInstance_SAIA_SAI_BASIC.Mode=SAI_A_BASIC
VP_SAI2_VP_$IpInstance_SAIA_SAI_BASIC.Signal=SAI2_VP_$IpInstance_SAIA_SAI_BASIC
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
VP_TIM2_VS_ClockSourceINT.Mode=Internal
VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
VP_USB_HOST_VS_USB_HOST_CDC_FS.Mode=CDC_FS
VP_USB_HOST_VS_USB_HOST_CDC_FS.Signal=USB_HOST_VS_USB_HOST_CDC_FS
board=custom

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@@ -1,58 +0,0 @@
#include "tos_k.h"
#include "stm32l4xx.h"
#define SECTOR_SIZE 2048 // sector size for stm32l431RCTX
int stm32l4_norflash_onchip_read(uint32_t addr, void *buf, size_t len)
{
memcpy(buf, (void *)addr, len);
return 0;
}
int stm32l4_norflash_onchip_write(uint32_t addr, const void *buf, size_t len)
{
int i = 0;
uint8_t *array = (uint8_t *)buf;
HAL_StatusTypeDef hal_status;
HAL_FLASH_Unlock();
tos_cpu_int_disable();
for (i = 0; i < len; i += 8) {
hal_status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD,
addr + i,
*(uint64_t *)&array[i]);
if (hal_status != HAL_OK) {
return -1;
}
}
HAL_FLASH_Lock();
tos_cpu_int_enable();
return 0;
}
int stm32l4_norflash_onchip_erase(uint32_t addr, size_t size)
{
uint32_t page_err = 0;
HAL_StatusTypeDef hal_status;
FLASH_EraseInitTypeDef erase_para;
erase_para.TypeErase = FLASH_TYPEERASE_PAGES;
erase_para.Banks = FLASH_BANK_1;
erase_para.Page = addr / SECTOR_SIZE;
erase_para.NbPages = size / SECTOR_SIZE;
HAL_FLASH_Unlock();
tos_cpu_int_disable();
hal_status = HAL_FLASHEx_Erase(&erase_para, &page_err);
HAL_FLASH_Lock();
tos_cpu_int_enable();
if (hal_status != HAL_OK) {
return -1;
}
return 0;
}

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@@ -1,13 +0,0 @@
#ifndef __ONCHIP_FLASH_H__
#define __ONCHIP_FLASH_H__
#include "stdint.h"
int stm32l4_norflash_onchip_read(uint32_t addr, void *buf, size_t len);
int stm32l4_norflash_onchip_write(uint32_t addr, const void *buf, size_t len);
int stm32l4_norflash_onchip_erase(uint32_t addr, size_t size);
#endif /* __ONCHIP_FLASH_H__ */

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@@ -1,20 +0,0 @@
#include "tos_kv.h"
#include "onchip_flash.h"
#define ONCHIP_FLASH_ADDR_START 0x08000000 // start address for onchip flash for stm32l431RCTX
#define ONCHIP_FLASH_ADDR_MAX 0x0803FFFF // 256K flash addr for stm32l431RCTX
#define SECTOR_SIZE 2048 // sector size for stm32l431RCTX
#define SECTOR_SIZE_LOG2 11 // 2 ^ 11 = 2048
kv_flash_drv_t stm32l4_norflash_onchip_drv = {
.write = stm32l4_norflash_onchip_write,
.read = stm32l4_norflash_onchip_read,
.erase = stm32l4_norflash_onchip_erase,
};
kv_flash_prop_t stm32l4_norflash_onchip_prop = {
.sector_size_log2 = SECTOR_SIZE_LOG2,
.pgm_type = KV_FLASH_PROGRAM_TYPE_DOUBLEWORD,
};

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@@ -1,23 +0,0 @@
#include "ota_flash.h"
#include "onchip_flash.h"
#define ONCHIP_FLASH_ADDR_START 0x08000000 // start address for onchip flash for stm32l431RCTX
#define ONCHIP_FLASH_ADDR_MAX 0x0803FFFF // 256K flash addr for stm32l431RCTX
#define SECTOR_SIZE 2048 // sector size for stm32l431RCTX
#define SECTOR_SIZE_LOG2 11 // 2 ^ 11 = 2048
#define FOR_OTA_FLASH_SIZE (2 * SECTOR_SIZE) // storage for OTA
#define FOR_OTA_FLASH_START 0x801e000
ota_flash_drv_t stm32l4_norflash_onchip_drv_ota = {
.write = stm32l4_norflash_onchip_write,
.read = stm32l4_norflash_onchip_read,
.erase = stm32l4_norflash_onchip_erase,
};
ota_flash_prop_t stm32l4_norflash_onchip_prop_ota = {
.sector_size_log2 = SECTOR_SIZE_LOG2,
.pgm_type = OTA_FLASH_PROGRAM_TYPE_DOUBLEWORD,
};

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@@ -1,57 +0,0 @@
/**
******************************************************************************
* File Name : gpio.h
* Description : This file contains all the functions prototypes for
* the gpio
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __gpio_H
#define __gpio_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_GPIO_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ pinoutConfig_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,50 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef __GPS_H__
#define __GPS_H__
#include "tos_at_gps.h"
//#define DEBUG_GPS_DATA 1
typedef struct
{
// GSV_item item[5];
char db1;//0-19
char db2;//20-29
char db3;//30-39
char db4;//40-
}GSV_;
typedef enum
{
ATGM336H_UNITE_GPS =1,
ATGM336H_UNITE_BDS =2,
ATGM336H_UNITE_GPS_BDS =3,
ATGM336H_UNITE_GLONASS =4,
ATGM336H_UNITE_GPS_GLONASS =5,
ATGM336H_UNITE_BDS_GLONASS =6,
ATGM336H_UNITE_GPS_BDS_GLONASS =7,
}Atgm336h_Unite;
int gps_read(int channel_id, void *buf, size_t len);
int gps_init(hal_uart_port_t uart_port);
#endif /* __GPS_H__ */

View File

@@ -1,60 +0,0 @@
/**
******************************************************************************
* File Name : I2C.h
* Description : This file provides code for the configuration
* of the I2C instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __i2c_H
#define __i2c_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern I2C_HandleTypeDef hi2c2;
extern I2C_HandleTypeDef hi2c3;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_I2C2_Init(void);
void MX_I2C3_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ i2c_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,135 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
void _Error_Handler(char *file, int line);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define KEY1_Pin GPIO_PIN_2
#define KEY1_GPIO_Port GPIOE
#define LED5_Pin GPIO_PIN_3
#define LED5_GPIO_Port GPIOE
#define SENSOR_EN_Pin GPIO_PIN_5
#define SENSOR_EN_GPIO_Port GPIOE
#define SENSOR_INT1_Pin GPIO_PIN_6
#define SENSOR_INT1_GPIO_Port GPIOE
#define SENSOR_INT2_Pin GPIO_PIN_13
#define SENSOR_INT2_GPIO_Port GPIOC
#define GPS_ON_Pin GPIO_PIN_1
#define GPS_ON_GPIO_Port GPIOB
#define BD_EN_Pin GPIO_PIN_2
#define BD_EN_GPIO_Port GPIOB
#define GPS_RST_Pin GPIO_PIN_7
#define GPS_RST_GPIO_Port GPIOE
#define NB_RST_Pin GPIO_PIN_8
#define NB_RST_GPIO_Port GPIOE
#define NB_WKUP_Pin GPIO_PIN_9
#define NB_WKUP_GPIO_Port GPIOE
#define NB_EN_Pin GPIO_PIN_11
#define NB_EN_GPIO_Port GPIOE
#define SEL1_Pin GPIO_PIN_12
#define SEL1_GPIO_Port GPIOE
#define SEL2_Pin GPIO_PIN_13
#define SEL2_GPIO_Port GPIOE
#define SEL3_Pin GPIO_PIN_14
#define SEL3_GPIO_Port GPIOE
#define KEY4_Pin GPIO_PIN_15
#define KEY4_GPIO_Port GPIOE
#define OLED_RST_Pin GPIO_PIN_12
#define OLED_RST_GPIO_Port GPIOB
#define OLED_EN_Pin GPIO_PIN_15
#define OLED_EN_GPIO_Port GPIOB
#define AU_CTR_Pin GPIO_PIN_8
#define AU_CTR_GPIO_Port GPIOD
#define AU_RST_Pin GPIO_PIN_13
#define AU_RST_GPIO_Port GPIOD
#define AU_EN_Pin GPIO_PIN_15
#define AU_EN_GPIO_Port GPIOD
#define CHARGE_STATE_Pin GPIO_PIN_6
#define CHARGE_STATE_GPIO_Port GPIOC
#define CARD_EN_Pin GPIO_PIN_7
#define CARD_EN_GPIO_Port GPIOC
#define PCIE_RST_Pin GPIO_PIN_8
#define PCIE_RST_GPIO_Port GPIOA
#define PCIE_EN_Pin GPIO_PIN_9
#define PCIE_EN_GPIO_Port GPIOA
#define CARD_END5_Pin GPIO_PIN_5
#define CARD_END5_GPIO_Port GPIOD
#define KEY3_Pin GPIO_PIN_6
#define KEY3_GPIO_Port GPIOD
#define KEY2_Pin GPIO_PIN_7
#define KEY2_GPIO_Port GPIOD
#define LED4_Pin GPIO_PIN_5
#define LED4_GPIO_Port GPIOB
#define LED3_Pin GPIO_PIN_8
#define LED3_GPIO_Port GPIOB
#define IR_OUT_Pin GPIO_PIN_9
#define IR_OUT_GPIO_Port GPIOB
#define LED2_Pin GPIO_PIN_0
#define LED2_GPIO_Port GPIOE
#define LED1_Pin GPIO_PIN_1
#define LED1_GPIO_Port GPIOE
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,21 +0,0 @@
#ifndef __MCU_INIT_H
#define __MCU_INIT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "main.h"
#include "stm32l4xx_hal.h"
#include "i2c.h"
#include "usart.h"
#include "gpio.h"
#include "tos_k.h"
void board_init(void);
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif /*__ __MCU_INIT_H */

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@@ -1,18 +0,0 @@
#ifndef __MYMATH_H
#define __MYMATH_H
void Ascii_to_hex_char(char *dstbuf,char*rstbuf);
void HexStrToByte(const char* source, unsigned char* dest, int sourceLen);
void ByteToHexStr(const unsigned char* source, char* dest, int sourceLen);
void Hex2Str( const char *sSrc, char *sDest, int nSrcLen );
int Myatoi(char *buf);
char * Myitoa(int val);
int str_to_hex(char *string, unsigned char *cbuf, int len);
void hex_to_str(char *ptr,unsigned char *buf,int len);
#endif

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@@ -1,59 +0,0 @@
/**
******************************************************************************
* File Name : SDMMC.h
* Description : This file provides code for the configuration
* of the SDMMC instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __sdmmc_H
#define __sdmmc_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32l4xx_hal.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern SD_HandleTypeDef hsd1;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_SDMMC1_SD_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ sdmmc_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,435 +0,0 @@
/**
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_CONF_H
#define __STM32L4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
#include "main.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
#define HAL_DAC_MODULE_ENABLED
/*#define HAL_DCMI_MODULE_ENABLED */
/*#define HAL_DMA2D_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */
/*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_FIREWALL_MODULE_ENABLED */
/*#define HAL_GFXMMU_MODULE_ENABLED */
#define HAL_HCD_MODULE_ENABLED
/*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/*#define HAL_LTDC_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_SWPMI_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
/*#define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_EXTI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)16000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal Multiple Speed oscillator (MSI) default value.
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)48000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/**
* @brief External clock source for SAI2 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32l4xx_hal_rcc.h"
#include "stm32l4xx_hal_rcc_ex.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32l4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32l4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32l4xx_hal_dma.h"
#include "stm32l4xx_hal_dma_ex.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32l4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32l4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32l4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32l4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l4xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32l4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32l4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32l4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32l4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32l4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32l4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_FIREWALL_MODULE_ENABLED
#include "stm32l4xx_hal_firewall.h"
#endif /* HAL_FIREWALL_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32l4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32l4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32l4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32l4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32l4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l4xx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32l4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32l4xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32l4xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32l4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32l4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32l4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32l4xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l4xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32l4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32l4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32l4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32l4xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,74 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_IT_H
#define __STM32L4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void USART1_IRQHandler(void);
void USART2_IRQHandler(void);
void USART3_IRQHandler(void);
void USART4_IRQHandler(void);
void LPUART1_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,56 +0,0 @@
/**
******************************************************************************
* File Name : SYS.h
* Description : This file provides code for the configuration
* of the SYS instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __sys_H
#define __sys_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_SYS_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ sys_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,83 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _TOS_AT_GPS_H_
#define _TOS_AT_GPS_H_
#include "tos_k.h"
#include "tos_hal.h"
#define AT_OUTPUT_MAX 128
#define AT_RX_BUFFER_SIZE 512
#define AT_PARSER_TASK_STACK_SIZE 2048
#define AT_PARSER_TASK_PRIO 0
#define AT_DATA_CHANNEL_NUM 3
#define AT_DATA_CHANNEL_FIFO_BUFFER_SIZE (2048 + 1024)
typedef void (*at_event_callback_t)(char * str);
typedef struct at_event_st {
const char *event_header;
at_event_callback_t event_callback;
} at_event_t;
typedef enum at_channel_status_en {
AT_CHANNEL_STATUS_NONE, /*< usually means we are try to get a channel status with invalid id */
AT_CHANNEL_STATUS_HANGING, /*< channel is not used */
AT_CHANNEL_STATUS_WORKING, /*< channel is being using */
AT_CHANNEL_STATUS_BROKEN, /*< channel is broken(module link to remote server is broken) */
} at_channel_status_t;
typedef struct at_data_channel_st {
uint8_t is_free;
k_chr_fifo_t rx_fifo;
uint8_t *rx_fifo_buffer;
k_mutex_t rx_lock;
at_channel_status_t status;
} at_data_channel_t;
typedef struct at_control_st {
at_data_channel_t data_channel[AT_DATA_CHANNEL_NUM];
k_task_t parser;
at_event_t *event_table;
size_t event_table_size;
char *cmd_buffer;
int cmd_buffer_size;
hal_uart_t uart;
k_sem_t at_rx_sem;
k_chr_fifo_t at_rx_fifo;
uint8_t *at_rx_fifo_buffer;
} at_agent_t;
#define AT_AGENT ((at_agent_t *)(&at_agent))
__API__ int tos_at_gps_init(hal_uart_port_t uart_port, at_event_t *event_table, size_t event_table_size);
__API__ void tos_at_gps_deinit(void);
__API__ void tos_at_gps_send(const char *format, ...);
__API__ void tos_at_gps_uart_input_byte(uint8_t data);
#endif /* _TOS_AT_GPS_H_ */

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@@ -1,67 +0,0 @@
/**
******************************************************************************
* File Name : USART.h
* Description : This file provides code for the configuration
* of the USART instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __usart_H
#define __usart_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern UART_HandleTypeDef huart1;
extern UART_HandleTypeDef huart2;
extern UART_HandleTypeDef huart3;
extern UART_HandleTypeDef huart4;
extern UART_HandleTypeDef hlpuart1;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_USART1_UART_Init(void);
void MX_USART2_UART_Init(void);
void MX_USART3_UART_Init(void);
void MX_USART4_UART_Init(void);
void MX_LPUART1_UART_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ usart_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,23 +0,0 @@
#ifndef __UART_H
#define __UART_H
#include "stm32l4xx_hal.h"
#define MAX_USBRX_BUFFER_LENGTH 128
#define CUSB_BUFFER_NUMBER 6
void Usb_Buff_Init(void);
uint8_t ReadUsbBuffData(uint8_t *dBuffer, uint8_t len);
//uint8_t saveUart2Data(void);
#endif

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@@ -1,172 +0,0 @@
/**
******************************************************************************
* File Name : gpio.c
* Description : This file provides code for the configuration
* of all used GPIO pins.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gpio.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure GPIO */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/** Configure pins as
* Analog
* Input
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, LED5_Pin|LED2_Pin|LED1_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, SENSOR_EN_Pin|GPS_RST_Pin|NB_RST_Pin|NB_WKUP_Pin
|NB_EN_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, GPS_ON_Pin|BD_EN_Pin|OLED_RST_Pin|OLED_EN_Pin
|LED3_Pin|IR_OUT_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, AU_CTR_Pin|AU_RST_Pin|AU_EN_Pin|CARD_END5_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(CARD_EN_GPIO_Port, CARD_EN_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(PCIE_RST_GPIO_Port, PCIE_RST_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(PCIE_EN_GPIO_Port, PCIE_EN_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET);
/*Configure GPIO pins : KEY1_Pin SEL1_Pin SEL2_Pin SEL3_Pin
KEY4_Pin */
GPIO_InitStruct.Pin = KEY1_Pin|SEL1_Pin|SEL2_Pin|SEL3_Pin
|KEY4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pins : LED5_Pin SENSOR_EN_Pin GPS_RST_Pin NB_RST_Pin
NB_WKUP_Pin NB_EN_Pin LED2_Pin LED1_Pin */
GPIO_InitStruct.Pin = LED5_Pin|SENSOR_EN_Pin|GPS_RST_Pin|NB_RST_Pin
|NB_WKUP_Pin|NB_EN_Pin|LED2_Pin|LED1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pin : SENSOR_INT1_Pin */
GPIO_InitStruct.Pin = SENSOR_INT1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(SENSOR_INT1_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : SENSOR_INT2_Pin */
GPIO_InitStruct.Pin = SENSOR_INT2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(SENSOR_INT2_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : PA5 PA6 */
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pin : PB0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : GPS_ON_Pin BD_EN_Pin OLED_RST_Pin OLED_EN_Pin
LED4_Pin LED3_Pin IR_OUT_Pin */
GPIO_InitStruct.Pin = GPS_ON_Pin|BD_EN_Pin|OLED_RST_Pin|OLED_EN_Pin
|LED4_Pin|LED3_Pin|IR_OUT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : AU_CTR_Pin AU_RST_Pin AU_EN_Pin CARD_END5_Pin */
GPIO_InitStruct.Pin = AU_CTR_Pin|AU_RST_Pin|AU_EN_Pin|CARD_END5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pin : CHARGE_STATE_Pin */
GPIO_InitStruct.Pin = CHARGE_STATE_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(CHARGE_STATE_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : CARD_EN_Pin */
GPIO_InitStruct.Pin = CARD_EN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(CARD_EN_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : PCIE_RST_Pin PCIE_EN_Pin */
GPIO_InitStruct.Pin = PCIE_RST_Pin|PCIE_EN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pins : KEY3_Pin KEY2_Pin */
GPIO_InitStruct.Pin = KEY3_Pin|KEY2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,437 +0,0 @@
#include "tos_k.h"
#include "tos_at_gps.h"
#include "tos_hal.h"
#include "stdio.h"
#include "stdbool.h"
#include "ctype.h"
#include "gps.h"
#include "mymath.h"
const char ATGM336H_GPS[]="$PCAS04,1*18\r\n";
const char ATGM336H_BDS[]="$PCAS04,2*1B\r\n";
const char ATGM336H_GPS_BDS[]="$PCAS04,3*1A\r\n";
const char ATGM336H_GLONASS[]="$PCAS04,4*1D\r\n";
const char ATGM336H_GPS_GLONASS[]="$PCAS04,5*1C\r\n";
const char ATGM336H_BDS_GLONASS[]="$PCAS04,6*1F\r\n";
const char ATGM336H_GPS_BDS_GLONASS[]="$PCAS04,7*1E\r\n";
const char ATGM336H_FREQ[]="$PCAS03,0,0,0,0,2,0,0,0,0,0,0,0,0,0*00\r\n";//"$PCAS03,2,0,0,2,2,0,0,0,0,0,0,0,0,0*00\r\n";
char* get_gpsrmc (char* buf)
{
char const *buff=buf;
char *p=NULL;
if(p= strstr(buff,"GNRMC")) //<2F><><EFBFBD><EFBFBD>
{
}
else if(p= strstr(buff,"GBRMC")){ //BDS
}
else if(p= strstr(buff,"GPRMC")){ //GPS
}
else if(p= strstr(buff,"BDRMC")){ //BDS
}
return p;
}
char* get_gpsgga(char* buf)
{
char const *buff=buf;
char *p=NULL;
if(p= strstr(buff,"GNGGA")){
}
else if(p= strstr(buff,"GBGGA")){
}
else if(p= strstr(buff,"GPGGA")){
}
else if(p= strstr(buff,"BDGGA")){
}
return p;
}
char* get_gpsgsv(char* buf)
{
char const *buff=buf;
char *p=NULL;
if(p= strstr(buff,"GNGSV")){
}
else if(p= strstr(buff,"GBGSV")){
}
else if(p= strstr(buff,"GPGSV")){
}
else if(p= strstr(buff,"BDGSV")){
}
return p;
}
//GBRMC,065730.00,V,2231.89755,N,11356.42786,E,0.206,,100919,,,N,V*08
void ParseGpsRmc(char *gpsdata)
{
uint16_t i,j,numtotal= 0;
uint8_t zero,first,second,third,fourth,fifth,sixth,sevevth;
char gpstestbuf[40];
char coordinate[25];
char rmcdatabuf[60];
char *buff_gprmc=NULL;
char tmp[10],tmp1[10],GPSChecksum[2],result;
char *test;
int len;
test = gpsdata;
j =0;
first =0; second=0;third=0;fourth=0;fifth=0;sixth=0;sevevth=0,result=0;
// printf("\r\n%s \n",test);
buff_gprmc = get_gpsrmc(test);
len = strlen(test);
if(buff_gprmc ==0){
// gpsFlag.Havetime2calitNb=0;
return;
}else{
// printf("len= %d\r\n",len);
// printf("%s",buff_gprmc);
// tos_kprintln("rmc\n");
for(i =0;i<len-2;i++){
// printf("%c",buff_gprmc[i]);
if(buff_gprmc[i] == '\n')break;
if(buff_gprmc[i] == ','){
numtotal++;
if(numtotal == 1){
zero = i;
} else if(numtotal == 3){
first = i;
} else if(numtotal == 4){
second = i;
} else if(numtotal == 5){
third = i;
} else if(numtotal == 6){
fourth = i;
} else if(numtotal == 7){
fifth = i;
} else if(numtotal == 8){
sixth = i;
} else if(numtotal == 9){
sevevth = i;
}
}
}
if(numtotal <12)
{
// gpsFlag.Havetime2calitNb=0;
return ;
}
if(buff_gprmc[first-1] != 65) //V
{
// gpsFlag.Havetime2calitNb=0;
return ;
}
}
if(((second-first)<2)||((third-second)<2)){
return;
}
for(result=buff_gprmc[0],i=1;buff_gprmc[i]!='*';i++)
{
result^=buff_gprmc[i];
}
memset(GPSChecksum,0,2);
ByteToHexStr(&result,GPSChecksum,2);
if((buff_gprmc[i+1]!=GPSChecksum[0]) || (buff_gprmc[i+2]!=GPSChecksum[1]))
{
return;
}
//--get gps time ---------------------------------------------------
for(i=zero+1,j=0;i<zero+7;i++,j++)
{
gpstestbuf[j] = buff_gprmc[i];
}
tos_at_gps_channel_write(0, gpstestbuf, 13);
// memset(gpsData.time,0,sizeof(gpsData.time));
// memcpy(gpsData.time,gpstestbuf,6);
#ifdef DEBUG_GPS_DATA
// printf("\r\nGps time:%.6s \r\n",gpsData.time);
#endif
//-------------------------------------------------------------------
memset(gpstestbuf,0,40);
memset(coordinate,0,25);
for(j =0,i = first+1;i<second;i++){
if((buff_gprmc[i] < 46) || (buff_gprmc[i] > 57) )
{
return;
}
gpstestbuf[j++] = buff_gprmc[i];
}
if((i-first-1)<10) //<2F><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
gpstestbuf[j++] = '0';
gpstestbuf[j++] = ',';
for(i = third+1;i<fourth;i++){
if((buff_gprmc[i] < 46) || (buff_gprmc[i] > 57) )
{
return;
}
gpstestbuf[j++] = buff_gprmc[i];
}
if((i-third-1)<11) //<2F><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
gpstestbuf[j++] = '0';
#ifdef DEBUG_GPS_DATA
printf("\r\nN AND E is \r\n");
#endif
// tos_kprintln(gpstestbuf);
tos_at_gps_channel_write(1, gpstestbuf, strlen(gpstestbuf));
j =0;
#ifdef DEBUG_GPS_DATA
printf("\r\nfindchar5 is \r\n");
#endif
memset(tmp,0,10);
for(i = fifth+1;i<sixth;i++){
if(buff_gprmc[i] =='.'){
break;
}
tmp[j++]= buff_gprmc[i];
}
i = atoi(tmp);
if(i>1)
{
// gpsFlag.gps_speed_non_zero=1;
}
else{
// gpsFlag.gps_speed_non_zero=0;
}
#ifdef DEBUG_GPS_DATA
printf("\r\nspeed is:%d\r\n",i);
#endif
j =0;
memset(tmp,0,10);
for(i = sixth+1;i<sevevth;i++){
if(buff_gprmc[i] =='.'){
break;
}
tmp[j++]= buff_gprmc[i];
}
i = atoi(tmp);
#ifdef DEBUG_GPS_DATA
printf("\r\ndirection is:%d\r\n",i);
#endif
#ifdef DEBUG_GPS_DATA
printf("\r\nparse data end \r\n");
#endif
}
//$GBGGA,032112.00,3924.40647,N,07556.84250,E,1,03,4.20,1333.7,M,-49.1,M,,*5B
void ParseGpsGga(char *gpsdata)
{
uint16_t i,j,numtotal= 0;
uint8_t sixth,sevevth;
char *buff_gpgga=NULL;
char tmp[10];
char *test;
int len;
test = gpsdata;
j =0;sixth=0;sevevth=0;
buff_gpgga = get_gpsgga(test);
len = strlen(test);
if(buff_gpgga ==0){
// gpsFlag.Havetime2calitNb=0;
return;
}
else
{
for(i =0;i<len-2;i++)
{
if(buff_gpgga[i] == '\n')break;
if(buff_gpgga[i] == ',')
{
numtotal++;
if(numtotal == 7)
sixth = i;
else if(numtotal == 8)
sevevth = i;
}
}
if(numtotal <14)
return ;
}
if(((sevevth-sixth)<2))
return;
for(j=0,i = sixth+1;i<sevevth;i++,j++)
{
if((buff_gpgga[i] < 48) || (buff_gpgga[i] > 57) )
{
printf("Data error \r\n");
return;
}
tmp[j]= buff_gpgga[i];
}
// printf("i:%d \r\n",ava_satellite);
}
//$BDGSV,4,1,15,01,47,123,42,02,47,235,36,03,64,189,44,07,74,092,41*66
GSV_ gsv;
void ParseGpsGsv(char *gsvdata)
{
char *buff_gpgga=NULL;
// char *test;
int i,len;
int num,num1,index,line,total,db;
char *revbuf[23] = {0};
// test = gpsdata;
// buff_gpgga = get_gpsgsv(gsvdata);
if(gsvdata ==NULL){
return;
}
else{
printf("%s\n",gsvdata);
split(gsvdata,",*",revbuf,&num);
// split(revbuf[num-1],"*",NULL,NULL);
for(i=1;i<num; i++)
{
if(revbuf[i]!=NULL)
printf("revbufval =%d\n",decstr_to_int(revbuf[i]));
else
printf("revbufval =NULL%d\n",i);
}
if(num>4)
{
line = decstr_to_int(revbuf[2]);//<2F><>ǰ<EFBFBD>ǵڼ<C7B5><DABC><EFBFBD>
total = decstr_to_int(revbuf[3]);//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if(line==1) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮ǰ<D6AE><C7B0>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><E3A3AC>ȡ
{
gsv.db1= 0;
gsv.db2= 0;
gsv.db3= 0;
gsv.db4= 0;
// gpsData.gsv = gsv;
}
index = (line-1)*4; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD><C5BA><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>,<2C><>Ϊÿһ<C3BF><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
for(i=0;i<4&&i<total-index; i++)
{
db = decstr_to_int(revbuf[7+4*i]);
if(db!=-1)
{
if(db>=40)
{
gsv.db4+=1;
}
else if(db>=30)
{
gsv.db3+=1;
}
else if(db>=20)
{
gsv.db2+=1;
}
else if(db>0)
{
gsv.db1+=1;
}
}
}
if(line==decstr_to_int(revbuf[1])) //<2F>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>
{
// gpsData.gsv = gsv;
// printf("gsv:%d,%d,%d,%d\n",gpsData.gsv.db1,gpsData.gsv.db2,gpsData.gsv.db3,gpsData.gsv.db4);
}
}
}
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϲ<EFBFBD><CFB9><EFBFBD>ģʽ
// 1GPS 2BDS 3GPS+BDS 4GLONASS 5GPS+GLONASS 6BDS+GLONASS 7GPS+BDS+GLONASS
void atgm336h_Unite(Atgm336h_Unite unite)
{
switch(unite)
{
case ATGM336H_UNITE_GPS:
tos_at_gps_send(ATGM336H_GPS);
break;
case ATGM336H_UNITE_BDS:
tos_at_gps_send(ATGM336H_BDS);
break;
case ATGM336H_UNITE_GPS_BDS:
tos_at_gps_send(ATGM336H_GPS_BDS);
break;
case ATGM336H_UNITE_GLONASS:
tos_at_gps_send(ATGM336H_GLONASS);
break;
case ATGM336H_UNITE_GPS_GLONASS:
tos_at_gps_send(ATGM336H_GPS_GLONASS);
break;
case ATGM336H_UNITE_BDS_GLONASS:
tos_at_gps_send(ATGM336H_BDS_GLONASS);
break;
case ATGM336H_UNITE_GPS_BDS_GLONASS:
tos_at_gps_send(ATGM336H_GPS_BDS_GLONASS);
break;
}
}
int gps_read(int channel_id, void *buf, size_t len)
{
return tos_at_gps_channel_read(channel_id, buf, len);
}
__STATIC__ void atgm336h_init(void)
{
printf("Init atgm336h ...\n" );
tos_task_delay(1000);
atgm336h_Unite(ATGM336H_UNITE_BDS);
tos_task_delay(200);
tos_at_gps_send(ATGM336H_FREQ);
}
__STATIC__ void gps_incoming_rmc(char * str)
{
// printf("gp\n" );
// printf(str);
ParseGpsRmc(str);
}
at_event_t gps_at_event[] = {
// { "$GPTXT,01,01,02,HW=ATGM336H", atgm336h_init },
{ "$BDRMC", gps_incoming_rmc },
};
int gps_init(hal_uart_port_t uart_port)
{
HAL_GPIO_WritePin(GPS_RST_GPIO_Port, GPS_RST_Pin, GPIO_PIN_RESET);
tos_task_delay(200);
HAL_GPIO_WritePin(GPS_RST_GPIO_Port, GPS_RST_Pin, GPIO_PIN_SET);
if (tos_at_gps_init(uart_port, gps_at_event,sizeof(gps_at_event) / sizeof(gps_at_event[0])) != 0) {
return -1;
}
atgm336h_init();
return 0;
}

View File

@@ -1,197 +0,0 @@
/**
******************************************************************************
* File Name : I2C.c
* Description : This file provides code for the configuration
* of the I2C instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "i2c.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
I2C_HandleTypeDef hi2c2;
I2C_HandleTypeDef hi2c3;
/* I2C2 init function */
void MX_I2C2_Init(void)
{
hi2c2.Instance = I2C2;
hi2c2.Init.Timing = 0x20303E5D;
hi2c2.Init.OwnAddress1 = 0;
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c2.Init.OwnAddress2 = 0;
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* I2C3 init function */
void MX_I2C3_Init(void)
{
hi2c3.Instance = I2C3;
hi2c3.Init.Timing = 0x2010091A;
hi2c3.Init.OwnAddress1 = 0;
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c3.Init.OwnAddress2 = 0;
hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(hi2c->Instance==I2C2)
{
/* USER CODE BEGIN I2C2_MspInit 0 */
/* USER CODE END I2C2_MspInit 0 */
/**I2C2 GPIO Configuration
PB13 ------> I2C2_SCL
PB14 ------> I2C2_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_I2C2_CLK_ENABLE();
/* USER CODE BEGIN I2C2_MspInit 1 */
/* USER CODE END I2C2_MspInit 1 */
}
else if(hi2c->Instance==I2C3)
{
/* USER CODE BEGIN I2C3_MspInit 0 */
/* USER CODE END I2C3_MspInit 0 */
/**I2C3 GPIO Configuration
PC0 ------> I2C3_SCL
PC1 ------> I2C3_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_I2C3_CLK_ENABLE();
/* USER CODE BEGIN I2C3_MspInit 1 */
/* USER CODE END I2C3_MspInit 1 */
}
}
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
{
if(hi2c->Instance==I2C2)
{
/* USER CODE BEGIN I2C2_MspDeInit 0 */
/* USER CODE END I2C2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C2_CLK_DISABLE();
/**I2C2 GPIO Configuration
PB13 ------> I2C2_SCL
PB14 ------> I2C2_SDA
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14);
/* USER CODE BEGIN I2C2_MspDeInit 1 */
/* USER CODE END I2C2_MspDeInit 1 */
}
else if(hi2c->Instance==I2C3)
{
/* USER CODE BEGIN I2C3_MspDeInit 0 */
/* USER CODE END I2C3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C3_CLK_DISABLE();
/**I2C3 GPIO Configuration
PC0 ------> I2C3_SCL
PC1 ------> I2C3_SDA
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1);
/* USER CODE BEGIN I2C3_MspDeInit 1 */
/* USER CODE END I2C3_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,23 +0,0 @@
#include "mcu_init.h"
#include "cmsis_os.h"
#define APPLICATION_TASK_STK_SIZE 1024
extern void application_entry(void *arg);
osThreadDef(application_entry, osPriorityNormal, 1, APPLICATION_TASK_STK_SIZE);
__weak void application_entry(void *arg)
{
while (1) {
printf("This is a demo task,please use your task entry!\r\n");
tos_task_delay(1000);
}
}
int main(void)
{
board_init();
printf("Welcome to TencentOS tiny\r\n");
osKernelInitialize();
osThreadCreate(osThread(application_entry), NULL);
osKernelStart();
}

View File

@@ -1,345 +0,0 @@
#include "mcu_init.h"
ADC_HandleTypeDef hadc1;
DAC_HandleTypeDef hdac1;
TIM_HandleTypeDef htim2;
SPI_HandleTypeDef hspi2;
IWDG_HandleTypeDef hiwdg;
SAI_HandleTypeDef hsai_BlockA2;
static void MX_DMA_Init(void);
static void MX_SPI2_Init(void);
static void MX_DAC1_Init(void);
static void MX_ADC1_Init(void);
static void MX_TIM2_Init(void);
static void MX_SAI2_Init(void);
int fputc(int ch, FILE *f)
{
if (ch == '\n') {
HAL_UART_Transmit(&huart1, (void *)"\r", 1,30000);
}
HAL_UART_Transmit(&huart1, (uint8_t *)&ch, 1, 0xFFFF);
return ch;
}
int _write(int fd, char *ptr, int len)
{
(void)HAL_UART_Transmit(&huart1, (uint8_t *)ptr, len, 0xFFFF);
return len;
}
int fgetc(FILE *f)
{
/* Place your implementation of fgetc here */
/* e.g. readwrite a character to the USART2 and Loop until the end of transmission */
uint8_t ch = 0;
HAL_UART_Receive(&huart1, &ch, 1,30000);
return ch;
}
void board_init(void)
{
HAL_Init();
SystemClock_Config();
MX_GPIO_Init();
MX_I2C2_Init();
MX_I2C3_Init();
MX_LPUART1_UART_Init();
MX_UART4_Init();
MX_USART3_UART_Init();
MX_USART2_UART_Init();
MX_USART1_UART_Init();
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInit;
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = 0;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2
|RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART4
|RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_SAI2
|RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_I2C3
|RCC_PERIPHCLK_USB|RCC_PERIPHCLK_SDMMC1
|RCC_PERIPHCLK_ADC;
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLLSAI1;
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLSAI1;
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV4;
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV4;
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV4;
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK
|RCC_PLLSAI1_ADC1CLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure the Systick interrupt time
*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
/**Configure the Systick
*/
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
}
/* ADC1 init function */
static void MX_ADC1_Init(void)
{
ADC_MultiModeTypeDef multimode;
ADC_ChannelConfTypeDef sConfig;
/**Common config
*/
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc1.Init.LowPowerAutoWait = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.NbrOfDiscConversion = 1;
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc1.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* DAC1 init function */
static void MX_DAC1_Init(void)
{
DAC_ChannelConfTypeDef sConfig;
/**DAC Initialization
*/
hdac1.Instance = DAC1;
if (HAL_DAC_Init(&hdac1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**DAC channel OUT1 config
*/
sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE;
sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* SPI2 init function */
static void MX_SPI2_Init(void)
{
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
hspi2.Init.Mode = SPI_MODE_MASTER;
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi2.Init.CRCPolynomial = 7;
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
if (HAL_SPI_Init(&hspi2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* TIM2 init function */
static void MX_TIM2_Init(void)
{
TIM_ClockConfigTypeDef sClockSourceConfig;
TIM_MasterConfigTypeDef sMasterConfig;
htim2.Instance = TIM2;
htim2.Init.Prescaler = 13260;
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
htim2.Init.Period = 10;
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_DMA2_CLK_ENABLE();
/* DMA interrupt init */
/* DMA2_Channel4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
/* DMA2_Channel5_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Channel5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Channel5_IRQn);
}
/* USER CODE BEGIN 4 */
void _Error_Handler(char *file, int line)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
printf("err %s,L%d\r\n",file,line);
}
/* USER CODE END Error_Handler_Debug */
}
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,245 +0,0 @@
#include <string.h>
#include "mymath.h"
#include <ctype.h>
void Ascii_to_hex_char(char *dstbuf,char*rstbuf)
{
//char *p = "jyh:abcdefghijklmnop";
unsigned char i,len;
len = strlen(rstbuf);
//printf(rstbuf);
for(i =0;i<len;i++)
{
sprintf(dstbuf+i*2,"%2x",rstbuf[i]);
}
dstbuf[i*2]=0;
//printf(dstbuf);
}
void HexStrToByte(const char* source, unsigned char* dest, int sourceLen)
{
short i;
unsigned char highByte, lowByte;
for (i = 0; i < sourceLen; i += 2)
{
highByte = toupper(source[i]);
lowByte = toupper(source[i + 1]);
highByte = source[i];
lowByte = source[i + 1];
if (highByte > 0x39)
highByte -= 0x37;
else
highByte -= 0x30;
if (lowByte > 0x39)
lowByte -= 0x37;
else
lowByte -= 0x30;
dest[i/2] = (highByte << 4) | lowByte;
}
return ;
}
//<2F>ֽ<EFBFBD><D6BD><EFBFBD>ת<EFBFBD><D7AA>Ϊʮ<CEAA><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
void ByteToHexStr(const unsigned char* source, char* dest, int sourceLen)
{
short i;
unsigned char highByte, lowByte;
for (i = 0; i < sourceLen; i++)
{
highByte = source[i] >> 4;
lowByte = source[i] & 0x0f ;
highByte += 0x30;
if (highByte > 0x39)
dest[i * 2] = highByte + 0x07;
else
dest[i * 2] = highByte;
lowByte += 0x30;
if (lowByte > 0x39)
dest[i * 2 + 1] = lowByte + 0x07;
else
dest[i * 2 + 1] = lowByte;
}
return ;
}
//<2F>ֽ<EFBFBD><D6BD><EFBFBD>ת<EFBFBD><D7AA>Ϊʮ<CEAA><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>ʵ<EFBFBD>ַ<EFBFBD>ʽ
void Hex2Str( const char *sSrc, char *sDest, int nSrcLen )
{
int i;
char szTmp[3];
for( i = 0; i < nSrcLen; i++ )
{
sprintf( szTmp, "%02X", (unsigned char) sSrc[i] );
memcpy( &sDest[i * 2], szTmp, 2 );
}
return ;
}
//<2F><><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊʮ<CEAA><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4>
int Myatoi(char *buf)
{
int result = 0;
char ch;
while((ch = *(buf++)) != '\0')
{
result = result*10 + ch-'0';
}
return result;
}
//<2F><>ʮ<EFBFBD><CAAE><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
char * Myitoa(int val)
{
static char szTmp[4];
memset(szTmp,0,4);
sprintf(szTmp, "%02d", val );
return szTmp;
}
/****************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: str_to_hex
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <20>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊʮ<CEAA><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: string <20>ַ<EFBFBD><D6B7><EFBFBD> cbuf ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD> len <20>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ij<EFBFBD><C4B3>ȡ<EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <20><>
*****************************************************************************/
int str_to_hex(char *string, unsigned char *cbuf, int len)
{
unsigned char high, low;
int idx, ii=0;
for (idx=0; idx<len; idx+=2)
{
high = string[idx];
low = string[idx+1];
if(high>='0' && high<='9')
high = high-'0';
else if(high>='A' && high<='F')
high = high - 'A' + 10;
else if(high>='a' && high<='f')
high = high - 'a' + 10;
else
return -1;
if(low>='0' && low<='9')
low = low-'0';
else if(low>='A' && low<='F')
low = low - 'A' + 10;
else if(low>='a' && low<='f')
low = low - 'a' + 10;
else
return -1;
cbuf[ii++] = high<<4 | low;
}
return 0;
}
/****************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: hex_to_str
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD> 0->30 1->31
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: ptr <20>ַ<EFBFBD><D6B7><EFBFBD> buf ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD> len ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ij<EFBFBD><C4B3>ȡ<EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <20><>
*****************************************************************************/
void hex_to_str(char *ptr,unsigned char *buf,int len)
{
for(int i = 0; i < len; i++)
{
sprintf(ptr, "%02x",buf[i]);
ptr += 2;
}
}
/****************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: hexstr_to_byte
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
*****************************************************************************/
int hexstr_to_byte(const unsigned char* source)
{
int i=0,ret=0;
char dest[2];
for(i=0;i<2;i++)
{
dest[i]=source[i]-'0';
if((dest[i] < 0) || (dest[i] > 54))
return 0;
if((dest[i]> 9) && (dest[i]< 23)) //A~F
dest[i] -= 7;
else if((dest[i]> 48) && (dest[i]<55)) //a~f
dest[i] -= 39;
// printf("dest[%d]:%d\r\n",i,dest[i]);
}
ret = dest[0]*16+dest[1];
return ret;
}
/****************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: decstr_to_int
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
*****************************************************************************/
int decstr_to_int(const unsigned char* src)
{
int i=0,ret=0;
int len = strlen(src);
for(i=0;i<len;i++)
{
if((src[i] < '0') || (src[i] > '9'))
return -1;
ret =ret*10+(src[i]-'0');
}
return ret;
}
/****************************************************************************
src Դ<>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׵<EFBFBD>ַ(buf<75>ĵ<EFBFBD>ַ)
separator ָ<><D6B8><EFBFBD>ķָ<C4B7><D6B8>ַ<EFBFBD>
dest <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
num <20>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD>
*****************************************************************************/
void split(char *src,const char *separator,char **dest,int *num) {
char *pNext;
int count = 0;
if (src == NULL || strlen(src) == 0) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵ<EFBFBD>ַΪ<D6B7>ջ򳤶<D5BB>Ϊ0<CEAA><30>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD>ֹ
return;
if (separator == NULL || strlen(separator) == 0) //<2F><>δָ<CEB4><D6B8><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD>ֹ
return;
pNext = (char *)strtok(src,separator); //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>(char *)<29><><EFBFBD><EFBFBD>ǿ<EFBFBD><C7BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>(<28><>Ȼ<EFBFBD><C8BB>д<EFBFBD>еı<D0B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>в<EFBFBD><D0B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
while(pNext != NULL) {
if(dest)
*dest++ = pNext;
++count;
pNext = (char *)strtok(NULL,separator); //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>(char *)<29><><EFBFBD><EFBFBD>ǿ<EFBFBD><C7BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>
}
if(num)
*num = count;
}

View File

@@ -1,119 +0,0 @@
/**
******************************************************************************
* File Name : SDMMC.c
* Description : This file provides code for the configuration
* of the SDMMC instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "sdmmc.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
SD_HandleTypeDef hsd1;
/* SDMMC1 init function */
void MX_SDMMC1_SD_Init(void)
{
hsd1.Instance = SDMMC1;
hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE;
hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
hsd1.Init.BusWide = SDMMC_BUS_WIDE_1B;
hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
hsd1.Init.ClockDiv = 0;
if (HAL_SD_Init(&hsd1) != HAL_OK)
{
// Error_Handler();
printf("HAL_SD_Init error\n");
}
}
void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(sdHandle->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspInit 0 */
/* USER CODE END SDMMC1_MspInit 0 */
/* SDMMC1 clock enable */
__HAL_RCC_SDMMC1_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**SDMMC1 GPIO Configuration
PC8 ------> SDMMC1_D0
PC12 ------> SDMMC1_CK
PD2 ------> SDMMC1_CMD
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USER CODE BEGIN SDMMC1_MspInit 1 */
/* USER CODE END SDMMC1_MspInit 1 */
}
}
void HAL_SD_MspDeInit(SD_HandleTypeDef* sdHandle)
{
if(sdHandle->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspDeInit 0 */
/* USER CODE END SDMMC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC1_CLK_DISABLE();
/**SDMMC1 GPIO Configuration
PC8 ------> SDMMC1_D0
PC12 ------> SDMMC1_CK
PD2 ------> SDMMC1_CMD
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_12);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
/* USER CODE BEGIN SDMMC1_MspDeInit 1 */
/* USER CODE END SDMMC1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,100 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : stm32f1xx_hal_msp.c
* Description : This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* System interrupt init*/
/* MemoryManagement_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
/* BusFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
/* UsageFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
/* SVCall_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
/* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,312 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f1xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32l4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "tos_k.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
//#define USE_WIFI
//#define USE_ROLA
//#define USE_2G
//#define USE_GPS
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern UART_HandleTypeDef huart1;
extern UART_HandleTypeDef huart2;
extern UART_HandleTypeDef huart3;
extern UART_HandleTypeDef huart4;
extern UART_HandleTypeDef hlpuart1;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M3 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
__weak void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
if(tos_knl_is_running())
{
tos_knl_irq_enter();
tos_tick_handler();
tos_knl_irq_leave();
}
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32F1xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f1xx.s). */
/******************************************************************************/
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
/**
* @brief This function handles USART2 global interrupt.
*/
void USART2_IRQHandler(void)
{
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
/**
* @brief This function handles USART3 global interrupt.
*/
void USART3_IRQHandler(void)
{
/* USER CODE BEGIN USART3_IRQn 0 */
/* USER CODE END USART3_IRQn 0 */
HAL_UART_IRQHandler(&huart3);
/* USER CODE BEGIN USART3_IRQn 1 */
/* USER CODE END USART3_IRQn 1 */
}
/**
* @brief This function handles USART4 global interrupt.
*/
void USART4_IRQHandler(void)
{
/* USER CODE BEGIN USART4_IRQn 0 */
/* USER CODE END USART4_IRQn 0 */
HAL_UART_IRQHandler(&huart4);
/* USER CODE BEGIN USART4_IRQn 1 */
/* USER CODE END USART4_IRQn 1 */
}
/**
* @brief This function handles LPUART1 global interrupt.
*/
void LPUART1_IRQHandler(void)
{
/* USER CODE BEGIN LPUART1_IRQn 0 */
/* USER CODE END LPUART1_IRQn 0 */
HAL_UART_IRQHandler(&hlpuart1);
/* USER CODE BEGIN LPUART1_IRQn 1 */
/* USER CODE END LPUART1_IRQn 1 */
}
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
extern uint8_t data2;
extern uint8_t data3;
if (huart->Instance == USART2) {
HAL_UART_Receive_IT(&huart2, &data2, 1);
#if defined(USE_WIFI)
tos_serialwifi_uart_input_byte(data2);
#elif defined(USE_ROLA)
tos_at_ra06_uart_input_byte(data2);
#elif defined(USE_2G)
tos_at_uart_input_byte(data2);
#endif
}
else if (huart->Instance == USART3) {
HAL_UART_Receive_IT(&huart3, &data3, 1);
#if defined(USE_GPS)
tos_at_gps_uart_input_byte(data3);
#endif
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,41 +0,0 @@
/**
******************************************************************************
* File Name : SYS.c
* Description : This file provides code for the configuration
* of the SYS instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "sys.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* SYS init function */
void MX_SYS_Init(void)
{
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,337 +0,0 @@
/**
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | MSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/** @addtogroup STM32L4xx_System_Private_Includes
* @{
*/
#include "stm32l4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000U;
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= 0xEAF6FFFFU;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000U;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
/* Get MSI Range frequency--------------------------------------------------*/
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
{ /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange;
break;
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource)
{
case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm);
break;
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr;
break;
default:
SystemCoreClock = msirange;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,386 +0,0 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include "tos_at_gps.h"
__STATIC__ at_agent_t at_agent;
__STATIC__ k_stack_t at_parser_task_stack[AT_PARSER_TASK_STACK_SIZE];
__STATIC__ int at_getchar(void)
{
uint8_t chr;
k_err_t err;
if (tos_sem_pend(&AT_AGENT->at_rx_sem, TOS_TIME_FOREVER) != K_ERR_NONE) {
return -1;
}
err = tos_chr_fifo_pop(&AT_AGENT->at_rx_fifo, &chr);
return err == K_ERR_NONE ? chr : -1;
}
__STATIC__ at_event_t *at_event_do_get(char *buffer, size_t buffer_len)
{
int i = 0;
at_event_t *event_table = K_NULL, *event = K_NULL;
size_t event_table_size = 0, event_len;
event_table = AT_AGENT->event_table;
event_table_size = AT_AGENT->event_table_size;
for (i = 0; i < event_table_size; ++i) {
event = &event_table[i];
event_len = strlen(event->event_header);
if (buffer_len < event_len) {
continue;
}
if (strncmp(event->event_header, buffer, event_len) == 0) {
return event;
}
}
return K_NULL;
}
__STATIC__ at_event_t *at_get_event(void)
{
char *buffer;
size_t buffer_len;
buffer = AT_AGENT->cmd_buffer;
buffer_len = strlen(AT_AGENT->cmd_buffer);
return at_event_do_get(buffer, buffer_len);
}
__STATIC__ int at_readline(void)
{
int chr, last_chr = 0;
at_event_t *at_event = K_NULL;
char *buf = AT_AGENT->cmd_buffer;
while (K_TRUE) {
if (buf - AT_AGENT->cmd_buffer >= (AT_AGENT->cmd_buffer_size - 1)) {
return -1;
}
chr = at_getchar();
if (chr < 0) {
return -1;
}
if (chr == '\n' && last_chr == '\r') {
*--buf = '\0';
// tos_kprintln(AT_AGENT->cmd_buffer);
at_event = at_get_event();
if (at_event && at_event->event_callback) {
at_event->event_callback(AT_AGENT->cmd_buffer);
}
return 0;
} else if (chr == '\n') {
*buf = '\0';
return 0;
}
*buf++ = chr;
last_chr = chr;
}
}
__STATIC__ void at_parser(void *arg)
{
while (K_TRUE) {
at_readline();
}
}
__STATIC__ at_data_channel_t *at_channel_get(int channel_id, int is_alloc)
{
/*
if is_alloc is K_TRUE, means we are allocating a channel with certain id,
data_channel[channel_id] must be free if return none K_NULL.
otherwise if is_alloc is K_FALSE, means we are trying to get a channel with
certain id, data_channel[channel_id] must be not free if return none K_NULL.
*/
at_data_channel_t *data_channel = K_NULL;
if (channel_id < 0 || channel_id >= AT_DATA_CHANNEL_NUM) {
return K_NULL;
}
data_channel = &AT_AGENT->data_channel[channel_id];
if (is_alloc && data_channel->is_free) {
return data_channel;
}
if (!is_alloc && !data_channel->is_free) {
return data_channel;
}
return K_NULL;
}
__API__ int tos_at_gps_channel_read(int channel_id, uint8_t *buffer, size_t buffer_len)
{
int read_len;
size_t total_read_len = 0;
at_data_channel_t *data_channel = K_NULL;
// printf("===\n");
data_channel = at_channel_get(channel_id, K_FALSE);
if (!data_channel || data_channel->status == AT_CHANNEL_STATUS_BROKEN) {
return -1;
}
// printf("==9\n");
if (tos_mutex_pend(&data_channel->rx_lock) != K_ERR_NONE) {
return total_read_len;
}
// printf("==8\n");
read_len = tos_chr_fifo_pop_stream(&data_channel->rx_fifo, buffer, buffer_len);
tos_mutex_post(&data_channel->rx_lock);
total_read_len += read_len;
return total_read_len;
}
__API__ int tos_at_gps_channel_write(int channel_id, uint8_t *buffer, size_t buffer_len)
{
int ret;
at_data_channel_t *data_channel = K_NULL;
// printf("++\n");
data_channel = at_channel_get(channel_id, K_FALSE);
if (!data_channel) {
// printf("+++\n");
return -1;
}
if (tos_mutex_pend(&data_channel->rx_lock) != K_ERR_NONE) {
return -1;
}
// printf("++9\n");
tos_chr_fifo_flush(&data_channel->rx_fifo);
ret = tos_chr_fifo_push_stream(&data_channel->rx_fifo, buffer, buffer_len);
tos_mutex_post(&data_channel->rx_lock);
return ret;
}
__STATIC_INLINE__ int at_channel_construct(at_data_channel_t *data_channel)
{
uint8_t *fifo_buffer = K_NULL;
fifo_buffer = tos_mmheap_alloc(AT_DATA_CHANNEL_FIFO_BUFFER_SIZE);
if (!fifo_buffer) {
return -1;
}
if (tos_mutex_create(&data_channel->rx_lock) != K_ERR_NONE) {
goto errout;
}
data_channel->rx_fifo_buffer = fifo_buffer;
tos_chr_fifo_create(&data_channel->rx_fifo, fifo_buffer, AT_DATA_CHANNEL_FIFO_BUFFER_SIZE);
data_channel->is_free = K_FALSE;
data_channel->status = AT_CHANNEL_STATUS_WORKING;
return 0;
errout:
tos_mmheap_free(fifo_buffer);
return -1;
}
__API__ int tos_at_gps_channel_alloc(void)
{
int id = 0;
at_data_channel_t *data_channel = K_NULL;
for (id = 0; id < AT_DATA_CHANNEL_NUM; ++id) {
data_channel = &AT_AGENT->data_channel[id];
if (data_channel->is_free) {
break;
}
}
if (id == AT_DATA_CHANNEL_NUM || !data_channel) {
return -1;
}
if (at_channel_construct(data_channel) != 0) {
return -1;
}
return id;
}
__API__ int tos_at_gps_channel_free(int channel_id)
{
at_data_channel_t *data_channel = K_NULL;
data_channel = at_channel_get(channel_id, K_FALSE);
if (!data_channel) {
return -1;
}
tos_mutex_destroy(&data_channel->rx_lock);
tos_mmheap_free(data_channel->rx_fifo_buffer);
tos_chr_fifo_destroy(&data_channel->rx_fifo);
memset(data_channel, 0, sizeof(at_data_channel_t));
data_channel->is_free = K_TRUE;
data_channel->status = AT_CHANNEL_STATUS_HANGING;
return 0;
}
__STATIC__ void at_channel_init(void)
{
int i = 0;
for (i = 0; i < AT_DATA_CHANNEL_NUM; ++i) {
memset(&AT_AGENT->data_channel[i], 0, sizeof(at_data_channel_t));
AT_AGENT->data_channel[i].is_free = K_TRUE;
AT_AGENT->data_channel[i].status = AT_CHANNEL_STATUS_HANGING;
}
for (i = 0; i < AT_DATA_CHANNEL_NUM; ++i) {
tos_at_gps_channel_alloc();
}
}
__STATIC__ void at_channel_deinit(void)
{
int i = 0;
for (i = 0; i < AT_DATA_CHANNEL_NUM; ++i) {
tos_at_gps_channel_free(i);
}
}
__STATIC__ void at_event_table_set(at_event_t *event_table, size_t event_table_size)
{
AT_AGENT->event_table = event_table;
AT_AGENT->event_table_size = event_table_size;
}
__API__ int tos_at_gps_init(hal_uart_port_t uart_port, at_event_t *event_table, size_t event_table_size)
{
void *buffer = K_NULL;
memset(AT_AGENT, 0, sizeof(at_agent_t));
at_event_table_set(event_table, event_table_size);
at_channel_init();
buffer = tos_mmheap_alloc(AT_RX_BUFFER_SIZE);
if (!buffer) {
return -1;
}
AT_AGENT->cmd_buffer = buffer;
AT_AGENT->cmd_buffer_size = AT_RX_BUFFER_SIZE;
buffer = tos_mmheap_alloc(AT_RX_BUFFER_SIZE * 2);
if (!buffer) {
return -1;
}
AT_AGENT->at_rx_fifo_buffer = (uint8_t *)buffer;
tos_chr_fifo_create(&AT_AGENT->at_rx_fifo, buffer, AT_RX_BUFFER_SIZE * 2);
if (tos_sem_create(&AT_AGENT->at_rx_sem, (k_sem_cnt_t)0u) != K_ERR_NONE) {
goto errout0;
}
if (tos_task_create(&AT_AGENT->parser, "at_parser", at_parser,
K_NULL, AT_PARSER_TASK_PRIO, at_parser_task_stack,
AT_PARSER_TASK_STACK_SIZE, 0) != K_ERR_NONE) {
goto errout1;
}
if (tos_hal_uart_init(&AT_AGENT->uart, uart_port) != 0) {
goto errout1;
}
return 0;
errout1:
tos_sem_destroy(&AT_AGENT->at_rx_sem);
errout0:
tos_mmheap_free(AT_AGENT->at_rx_fifo_buffer);
AT_AGENT->at_rx_fifo_buffer = K_NULL;
tos_chr_fifo_destroy(&AT_AGENT->at_rx_fifo);
return -1;
}
__API__ void tos_at_gps_deinit(void)
{
tos_task_destroy(&AT_AGENT->parser);
tos_sem_destroy(&AT_AGENT->at_rx_sem);
tos_hal_uart_deinit(&AT_AGENT->uart);
tos_mmheap_free(AT_AGENT->at_rx_fifo_buffer);
AT_AGENT->at_rx_fifo_buffer = K_NULL;
tos_chr_fifo_destroy(&AT_AGENT->at_rx_fifo);
at_channel_deinit();
}
__API__ void tos_at_gps_send(const char *format, ...)
{
va_list args;
size_t cmd_len = 0;
static char buffer[AT_OUTPUT_MAX];
va_start(args, format);
cmd_len =vsnprintf(buffer, sizeof(buffer), format, args);
va_end(args);
tos_hal_uart_write(&AT_AGENT->uart, buffer, cmd_len, 0xFFFF);
}
__API__ void tos_at_gps_uart_input_byte(uint8_t data)
{
if (tos_chr_fifo_push(&AT_AGENT->at_rx_fifo, data) == K_ERR_NONE) {
tos_sem_post(&AT_AGENT->at_rx_sem);
}
}

View File

@@ -1,374 +0,0 @@
/**
******************************************************************************
* File Name : USART.c
* Description : This file provides code for the configuration
* of the USART instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "usart.h"
/* USER CODE BEGIN 0 */
uint8_t data2;
uint8_t data3;
uint8_t data4;
uint8_t datal1;
/* USER CODE END 0 */
UART_HandleTypeDef huart1;
UART_HandleTypeDef huart2;
UART_HandleTypeDef huart3;
UART_HandleTypeDef huart4;
UART_HandleTypeDef hlpuart1;
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
Error_Handler();
}
}
/* USART2 init function */
void MX_USART2_UART_Init(void)
{
huart2.Instance = USART2;
huart2.Init.BaudRate = 57600;
huart2.Init.WordLength = UART_WORDLENGTH_8B;
huart2.Init.StopBits = UART_STOPBITS_1;
huart2.Init.Parity = UART_PARITY_NONE;
huart2.Init.Mode = UART_MODE_TX_RX;
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart2) != HAL_OK)
{
Error_Handler();
}
HAL_UART_Receive_IT(&huart2, &data2, 1);
}
/* USART3 init function */
void MX_USART3_UART_Init(void)
{
huart3.Instance = USART3;
huart3.Init.BaudRate = 9600;
huart3.Init.WordLength = UART_WORDLENGTH_8B;
huart3.Init.StopBits = UART_STOPBITS_1;
huart3.Init.Parity = UART_PARITY_NONE;
huart3.Init.Mode = UART_MODE_TX_RX;
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart3) != HAL_OK)
{
Error_Handler();
}
HAL_UART_Receive_IT(&huart3, &data3, 1);
}
/* UART4 init function */
void MX_UART4_Init(void)
{
huart4.Instance = UART4;
huart4.Init.BaudRate = 115200;
huart4.Init.WordLength = UART_WORDLENGTH_8B;
huart4.Init.StopBits = UART_STOPBITS_1;
huart4.Init.Parity = UART_PARITY_NONE;
huart4.Init.Mode = UART_MODE_TX_RX;
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart4) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
HAL_UART_Receive_IT(&huart4, &data4, 1);
}
/* LPUART1 init function */
void MX_LPUART1_UART_Init(void)
{
hlpuart1.Instance = LPUART1;
hlpuart1.Init.BaudRate = 209700;
hlpuart1.Init.WordLength = UART_WORDLENGTH_7B;
hlpuart1.Init.StopBits = UART_STOPBITS_1;
hlpuart1.Init.Parity = UART_PARITY_NONE;
hlpuart1.Init.Mode = UART_MODE_TX_RX;
hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&hlpuart1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
HAL_UART_Receive_IT(&hlpuart1, &datal1, 1);
}
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(huart->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspInit 0 */
/* USER CODE END LPUART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LPUART1_CLK_ENABLE();
/**LPUART1 GPIO Configuration
PB10 ------> LPUART1_RX
PB11 ------> LPUART1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN LPUART1_MspInit 1 */
/* USER CODE END LPUART1_MspInit 1 */
}
else if(huart->Instance==UART4)
{
/* USER CODE BEGIN UART4_MspInit 0 */
/* USER CODE END UART4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_UART4_CLK_ENABLE();
/**UART4 GPIO Configuration
PA0 ------> UART4_TX
PA1 ------> UART4_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN UART4_MspInit 1 */
/* USER CODE END UART4_MspInit 1 */
}
else if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
else if(huart->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
else if(huart->Instance==USART3)
{
/* USER CODE BEGIN USART3_MspInit 0 */
/* USER CODE END USART3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
/**USART3 GPIO Configuration
PC4 ------> USART3_TX
PC5 ------> USART3_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* USART3 interrupt Init */
HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspDeInit 0 */
/* USER CODE END LPUART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LPUART1_CLK_DISABLE();
/**LPUART1 GPIO Configuration
PB10 ------> LPUART1_RX
PB11 ------> LPUART1_TX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11);
/* USER CODE BEGIN LPUART1_MspDeInit 1 */
/* USER CODE END LPUART1_MspDeInit 1 */
}
else if(huart->Instance==UART4)
{
/* USER CODE BEGIN UART4_MspDeInit 0 */
/* USER CODE END UART4_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_UART4_CLK_DISABLE();
/**UART4 GPIO Configuration
PA0 ------> UART4_TX
PA1 ------> UART4_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);
/* USER CODE BEGIN UART4_MspDeInit 1 */
/* USER CODE END UART4_MspDeInit 1 */
}
else if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
else if(huart->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspDeInit 0 */
/* USER CODE END USART2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART2_CLK_DISABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
/* USART2 interrupt DeInit */
HAL_NVIC_DisableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspDeInit 1 */
/* USER CODE END USART2_MspDeInit 1 */
}
else if(huart->Instance==USART3)
{
/* USER CODE BEGIN USART3_MspDeInit 0 */
/* USER CODE END USART3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART3_CLK_DISABLE();
/**USART3 GPIO Configuration
PC4 ------> USART3_TX
PC5 ------> USART3_RX
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);
/* USART3 interrupt DeInit */
HAL_NVIC_DisableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspDeInit 1 */
/* USER CODE END USART3_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,77 +0,0 @@
#include <string.h>
#include <stdlib.h>
#include "user_usb_uart.h"
#include "usb_host.h"
#include "usbh_cdc.h"
uint8_t da_flag =0;
uint8_t aUsbRxBuffer[MAX_USBRX_BUFFER_LENGTH];
uint8_t bUsbRxBuffer[CUSB_BUFFER_NUMBER][MAX_USBRX_BUFFER_LENGTH+1];
uint8_t bUsbBufLength[CUSB_BUFFER_NUMBER];
uint8_t CurrentUsbBufNumPoint = 0;
extern USBH_HandleTypeDef hUsbHostFS;
extern uint8_t Recv_buf[MAX_USBRX_BUFFER_LENGTH];
void Usb_Buff_Init(void)
{
for(int ti=0; ti< CUSB_BUFFER_NUMBER; ti++)
{
bUsbBufLength[ti] = 0;
memset(bUsbRxBuffer[ti],0,sizeof(bUsbRxBuffer[ti]));
}
}
uint8_t ReadUsbBuffData(uint8_t *dBuffer, uint8_t len)
{
uint8_t buflen =0;
if(bUsbBufLength[CurrentUsbBufNumPoint]>0)
{
memset(dBuffer,0,len);
buflen = bUsbBufLength[CurrentUsbBufNumPoint];
memcpy(dBuffer,(const char *)bUsbRxBuffer[CurrentUsbBufNumPoint],buflen);
memset(bUsbRxBuffer[CurrentUsbBufNumPoint],0,sizeof(bUsbRxBuffer[CurrentUsbBufNumPoint]));
bUsbBufLength[CurrentUsbBufNumPoint] = 0;
CurrentUsbBufNumPoint++;
if(CurrentUsbBufNumPoint >= CUSB_BUFFER_NUMBER)
CurrentUsbBufNumPoint = 0;
}
return buflen;
}
//
void Check_empty_buffer()
{
uint8_t i;
for(i=0;i<CUSB_BUFFER_NUMBER;i++)
{
if(bUsbBufLength[CurrentUsbBufNumPoint]>0)
{
CurrentUsbBufNumPoint++;
if(CurrentUsbBufNumPoint >= CUSB_BUFFER_NUMBER)
CurrentUsbBufNumPoint=0;
}
else
break;
}
}
//
void USBH_CDC_ReceiveCallback(USBH_HandleTypeDef *phost)
{
uint32_t i,rec_len=0;
USBH_CDC_GetLastReceivedDataSize(phost);
rec_len = strlen(aUsbRxBuffer);
if(rec_len>0)
{
Check_empty_buffer();
memcpy(bUsbRxBuffer[CurrentUsbBufNumPoint],aUsbRxBuffer,rec_len);
bUsbBufLength[CurrentUsbBufNumPoint] = rec_len;
memset(aUsbRxBuffer,0,sizeof(aUsbRxBuffer));
}
}

View File

@@ -1,200 +0,0 @@
#include "stm32l4xx_hal.h"
#include "mcu_init.h"
#include "tos_k.h"
#include "mqttclient.h"
#include "cjson.h"
#include "sal_module_wrapper.h"
//#define USE_ESP8266
//#define USE_NB_BC35
//#define USE_BC26
//#define USE_EC200S
#define USE_M5313
#if defined(USE_ESP8266)
#include "esp8266.h"
#elif defined(USE_BC26)
#include "bc26.h"
#elif defined(USE_EC200S)
#include "ec200s.h"
#elif defined(USE_M5313)
#include "m5313.h"
#endif
uint8_t module_sel=0; //0---M5313; 1---wifi; 2---BT; 3---Lora
#ifdef USE_ESP8266
static hal_uart_port_t esp8266_port = HAL_UART_PORT_0;
void mqtt_set_esp8266_port(hal_uart_port_t port) {
esp8266_port = port;
}
#endif
k_event_t report_result_event;
k_event_flag_t report_success = 1<<0;
k_event_flag_t report_fail = 1<<1;
static void tos_topic_handler(void* client, message_data_t* msg)
{
(void) client;
cJSON* cjson_root = NULL;
cJSON* cjson_status = NULL;
char* status = NULL;
k_event_flag_t event_flag = report_fail;
/* <20><>ӡ<EFBFBD><D3A1>־ */
MQTT_LOG_I("-----------------------------------------------------------------------------------");
MQTT_LOG_I("%s:%d %s()...\ntopic: %s, qos: %d. \nmessage:\n\t%s\n", __FILE__, __LINE__, __FUNCTION__,
msg->topic_name, msg->message->qos, (char*)msg->message->payload);
MQTT_LOG_I("-----------------------------------------------------------------------------------\n");
/* ʹ<><CAB9>cjson<6F><6E><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD> */
cjson_root = cJSON_Parse((char*)msg->message->payload);
if (cjson_root == NULL) {
printf("report reply message parser fail\r\n");
event_flag = report_fail;
goto exit;
}
/* <20><>ȡstatus״̬ */
cjson_status = cJSON_GetObjectItem(cjson_root, "status");
status = cJSON_GetStringValue(cjson_status);
if (cjson_status == NULL || status == NULL) {
printf("report reply status parser fail\r\n");
event_flag = report_fail;
goto exit;
}
/* <20>ж<EFBFBD>status״̬ */
if (strstr(status,"success")) {
event_flag = report_success;
}else {
event_flag = report_fail;
}
exit:
cJSON_Delete(cjson_root);
cjson_root = NULL;
status = NULL;
tos_event_post(&report_result_event, event_flag);
return;
}
#define REPORT_DATA_TEMPLATE "{\"method\":\"report\",\"clientToken\":\"00000001\",\"params\":{\"brightness\":%d,\"name\":\"bedroom\"}}"
char report_buf[200];
void mqttclient_task(void)
{
int error;
int lightness = 0;
mqtt_client_t *client = NULL;
mqtt_message_t msg;
k_event_flag_t match_flag;
char host_ip[20];
memset(&msg, 0, sizeof(msg));
#ifdef USE_ESP8266
esp8266_sal_init(esp8266_port);
esp8266_join_ap("Supowang", "13975428888");
#endif
#ifdef USE_NB_BC35
int bc35_28_95_sal_init(hal_uart_port_t uart_port);
bc35_28_95_sal_init(HAL_UART_PORT_0);
#endif
#ifdef USE_BC26
bc26_sal_init(HAL_UART_PORT_2);
#endif
#ifdef USE_EC200S
ec200s_sal_init(HAL_UART_PORT_2);
#endif
#ifdef USE_M5313
m5313_sal_init(HAL_UART_PORT_2);
#endif
mqtt_log_init();
client = mqtt_lease();
tos_event_create(&report_result_event, (k_event_flag_t)0u);
/* Domain Format: <your product ID>.iotcloud.tencentdevices.com */
tos_sal_module_parse_domain("S7271EG5D8.iotcloud.tencentdevices.com",host_ip,sizeof(host_ip));
/*
These infomation is generated by mqtt_config_gen.py tool in "TencentOS-tiny\tools" directory.
*/
mqtt_set_port(client, "1883");
mqtt_set_host(client, host_ip);
mqtt_set_client_id(client, "S7271EG5D8bdw01_led");
mqtt_set_user_name(client, "S7271EG5D8bdw01_led;21010406;12365;4294967295");
mqtt_set_password(client, "5b5d6b05117634f199e65fb078acbcdabbdda063;hmacsha1");
mqtt_set_clean_session(client, 1);
error = mqtt_connect(client);
MQTT_LOG_D("mqtt connect error is %#0x", error);
error = mqtt_subscribe(client, "$thing/down/property/S7271EG5D8/bdw01_led", QOS0, tos_topic_handler);
MQTT_LOG_D("mqtt subscribe error is %#0x", error);
while (1) {
memset(&msg, 0, sizeof(msg));
snprintf(report_buf, sizeof(report_buf), REPORT_DATA_TEMPLATE, lightness++);
if (lightness > 100) {
lightness = 0;
}
msg.qos = QOS0;
msg.payload = (void *) report_buf;
error = mqtt_publish(client, "$thing/up/property/S7271EG5D8/bdw01_led", &msg);
MQTT_LOG_D("mqtt publish error is %#0x", error);
tos_event_pend(&report_result_event,
report_success|report_fail,
&match_flag,
TOS_TIME_FOREVER,
TOS_OPT_EVENT_PEND_ANY | TOS_OPT_EVENT_PEND_CLR);
if (match_flag == report_success) {
printf("report to Tencent IoT Explorer success\r\n");
}else if (match_flag == report_fail){
printf("report to Tencent IoT Explorer fail\r\n");
}
tos_task_delay(5000);
}
}
void application_entry(void *arg)
{
mqttclient_task();
while (1) {
printf("This is a mqtt demo!\r\n");
tos_task_delay(1000);
}
}

View File

@@ -1,273 +0,0 @@
#include "stm32l4xx_hal.h"
#include "mcu_init.h"
#include "tos_k.h"
#include "mqttclient.h"
#include "cjson.h"
#include "sal_module_wrapper.h"
//#define USE_ESP8266
//#define USE_NB_BC35
//#define USE_BC26
//#define USE_EC200S
#define USE_M5313
#if defined(USE_ESP8266)
#include "esp8266.h"
#elif defined(USE_BC26)
#include "bc26.h"
#elif defined(USE_EC200S)
#include "ec200s.h"
#elif defined(USE_M5313)
#include "m5313.h"
#endif
uint8_t module_sel=0; //0---M5313; 1---wifi; 2---BT; 3---Lora
#ifdef USE_ESP8266
static hal_uart_port_t esp8266_port = HAL_UART_PORT_0;
void mqtt_set_esp8266_port(hal_uart_port_t port) {
esp8266_port = port;
}
#endif
k_event_t report_result_event;
k_event_flag_t report_success = 1<<0;
k_event_flag_t report_fail = 1<<1;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>󻺴<EFBFBD><F3BBBAB4><EFBFBD><EFBFBD><EFBFBD> */
#define MESSAGE_MAX 5
typedef struct payload_mail_st {
void* client;
void* payload;
} payload_mail_t;
k_mail_q_t mail_q;
uint8_t mail_pool[MESSAGE_MAX * sizeof(payload_mail_t *)];
#define REPORT_DATA_TEMPLATE "{\"method\":\"report\",\"clientToken\":\"00000001\",\"params\":{\"location\":\"%s\"}}"
#define CONTROL_REPLY_DATA "{\"method\":\"control_reply\",\"clientToken\":\"%s\",\"code\":0,\"status\":\"success\"}"
char report_buf[1024];
char reply_buf[200];
static void tos_topic_handler(void* client, message_data_t* msg)
{
(void) client;
cJSON* cjson_root = NULL;
cJSON* cjson_status = NULL;
cJSON* cjson_method = NULL;
cJSON* cjson_params = NULL;
cJSON* cjson_relay_status = NULL;
cJSON* cjson_client_token = NULL;
int relay_status = 0;
char* status = NULL;
char* method = NULL;
char* client_token = NULL;
k_event_flag_t event_flag = report_fail;
int error;
mqtt_message_t reply_msg;
payload_mail_t payload_mail;
/* <20><>ӡ<EFBFBD><D3A1>־ */
MQTT_LOG_I("-----------------------------------------------------------------------------------");
MQTT_LOG_I("%s:%d %s()...\ntopic: %s, qos: %d. \nmessage:\n\t%s\n", __FILE__, __LINE__, __FUNCTION__,
msg->topic_name, msg->message->qos, (char*)msg->message->payload);
MQTT_LOG_I("-----------------------------------------------------------------------------------\n");
/* ʹ<><CAB9>cjson<6F><6E><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD> */
cjson_root = cJSON_Parse((char*)msg->message->payload);
if (cjson_root == NULL) {
printf("report reply message parser fail\r\n");
event_flag = report_fail;
goto exit;
}
/* <20><>ȡ<EFBFBD><C8A1>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD> */
cjson_method = cJSON_GetObjectItem(cjson_root, "method");
method = cJSON_GetStringValue(cjson_method);
/* <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD><CDB5><EFBFBD>Ϣ */
if (strstr(method, "report_reply")) {
/* <20><>ȡstatus״̬ */
cjson_status = cJSON_GetObjectItem(cjson_root, "status");
status = cJSON_GetStringValue(cjson_status);
if (cjson_status == NULL || status == NULL) {
printf("report reply status parser fail\r\n");
event_flag = report_fail;
goto exit;
}
/* <20>ж<EFBFBD>status״̬ */
if (strstr(status,"success")) {
event_flag = report_success;
}else {
event_flag = report_fail;
}
}else if (strstr(method, "control")) {
//<2F>յ<EFBFBD>ƽ̨<C6BD>·<EFBFBD><C2B7>Ŀ<EFBFBD><C4BF>Ʊ<EFBFBD><C6B1>ģ<EFBFBD><C4A3><EFBFBD>ȡclient_token<65><6E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD>Ӧ
cjson_client_token = cJSON_GetObjectItem(cjson_root, "clientToken");
client_token = cJSON_GetStringValue(cjson_client_token);
printf("parse client token:%s\r\n", client_token);
//<2F><>ȡ relay_status
cjson_params = cJSON_GetObjectItem(cjson_root, "params");
cjson_relay_status = cJSON_GetObjectItem(cjson_params, "led");
relay_status = cjson_relay_status->valueint;
//<2F><><EFBFBD><EFBFBD> relay_status ִ<><D6B4><EFBFBD><EFBFBD>Ӧ<EFBFBD>Ķ<EFBFBD><C4B6><EFBFBD>
if (relay_status == 0) {
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET);
} else if (relay_status == 1) {
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
}
memset(reply_buf, 0, sizeof(reply_buf));
sprintf(reply_buf, CONTROL_REPLY_DATA, client_token);
memset(&reply_msg, 0, sizeof(reply_msg));
reply_msg.qos = QOS0;
reply_msg.payload = (void *) reply_buf;
printf("control reply:\r\n\t%s\r\n", reply_buf);
error = mqtt_publish(payload_mail.client, "$thing/up/property/E2IGF491FP/dev001", &reply_msg);
MQTT_LOG_D("control reply publish error is %#0x", error);
}
exit:
cJSON_Delete(cjson_root);
cjson_root = NULL;
status = NULL;
tos_event_post(&report_result_event, event_flag);
return;
}
void mqttclient_task(void)
{
#define BUFFER_SIZE 128
int error;
int lightness = 0;
mqtt_client_t *client = NULL;
mqtt_message_t msg;
k_event_flag_t match_flag;
char host_ip[20];
int len;
uint8_t *buffer = K_NULL;
memset(&msg, 0, sizeof(msg));
gps_init(HAL_UART_PORT_3);
buffer = tos_mmheap_alloc(BUFFER_SIZE);
#ifdef USE_ESP8266
esp8266_sal_init(esp8266_port);
esp8266_join_ap("Supowang", "13975428888");
#endif
#ifdef USE_NB_BC35
int bc35_28_95_sal_init(hal_uart_port_t uart_port);
bc35_28_95_sal_init(HAL_UART_PORT_0);
#endif
#ifdef USE_BC26
bc26_sal_init(HAL_UART_PORT_2);
#endif
#ifdef USE_EC200S
ec200s_sal_init(HAL_UART_PORT_2);
#endif
#ifdef USE_M5313
m5313_sal_init(HAL_UART_PORT_2);
#endif
mqtt_log_init();
client = mqtt_lease();
tos_event_create(&report_result_event, (k_event_flag_t)0u);
/* Domain Format: <your product ID>.iotcloud.tencentdevices.com */
tos_sal_module_parse_domain("OKY0D78DP2.iotcloud.tencentdevices.com",host_ip,sizeof(host_ip));
/*
These infomation is generated by mqtt_config_gen.py tool in "TencentOS-tiny\tools" directory.
*/
mqtt_set_port(client, "1883");
mqtt_set_host(client, host_ip);
mqtt_set_client_id(client, "OKY0D78DP2bd_location");
mqtt_set_user_name(client, "OKY0D78DP2bd_location;21010406;12365;4294967295");
mqtt_set_password(client, "55ed32e6ce98deca02ea579954d05a8ba4c442e2;hmacsha1");
mqtt_set_clean_session(client, 1);
error = mqtt_connect(client);
MQTT_LOG_D("mqtt connect error is %#0x", error);
error = mqtt_subscribe(client, "$thing/down/property/OKY0D78DP2/bd_location", QOS0, tos_topic_handler);
MQTT_LOG_D("mqtt subscribe error is %#0x", error);
while (1) {
if((len =gps_read(1,buffer,BUFFER_SIZE))>0)
{
printf("gps:%s(%d)\n",buffer,len);
memset(&msg, 0, sizeof(msg));
snprintf(report_buf, sizeof(report_buf), REPORT_DATA_TEMPLATE, buffer);
msg.qos = QOS0;
msg.payload = (void *) report_buf;
error = mqtt_publish(client, "$thing/up/property/OKY0D78DP2/bd_location", &msg);
MQTT_LOG_D("mqtt publish error is %#0x", error);
tos_event_pend(&report_result_event,
report_success|report_fail,
&match_flag,
TOS_TIME_FOREVER,
TOS_OPT_EVENT_PEND_ANY | TOS_OPT_EVENT_PEND_CLR);
if (match_flag == report_success) {
printf("report to Tencent IoT Explorer success\r\n");
}else if (match_flag == report_fail){
printf("report to Tencent IoT Explorer fail\r\n");
}
}
tos_task_delay(5000);
}
}
void application_entry(void *arg)
{
mqttclient_task();
while (1) {
printf("This is a mqtt demo!\r\n");
tos_task_delay(1000);
}
}

View File

@@ -1,64 +0,0 @@
#include "m5313.h"
#include "mcu_init.h"
#include "sal_module_wrapper.h"
#include "cmsis_os.h"
#include "ota_download.h"
extern ota_flash_drv_t stm32l4_norflash_onchip_drv_ota;
extern ota_flash_prop_t stm32l4_norflash_onchip_prop_ota;
k_sem_t sem;
#define TASK1_STK_SIZE 1024
void user_task(void *arg);
osThreadDef(user_task, osPriorityNormal, 1, TASK1_STK_SIZE);
#define TASK2_STK_SIZE 1024
void ota_download_task(void *arg);
osThreadDef(ota_download_task, osPriorityNormal, 1, TASK2_STK_SIZE);
void user_task(void *arg)
{
int iter = 0;
while (K_TRUE) {
osDelay(2000);
printf("do sth(v0.1)...\n");
if (++iter == 2) {
printf("trigger ota download\n");
tos_sem_post(&sem);
}
}
}
void ota_download_task(void *arg)
{
tos_sem_pend(&sem, TOS_TIME_FOREVER);
m5313_sal_init(HAL_UART_PORT_2);
uint32_t partition_addr = 0x080ff800;
if (ota_env_init(OTA_UPDATE_IN_POSITION, partition_addr, &stm32l4_norflash_onchip_drv_ota, &stm32l4_norflash_onchip_prop_ota) < 0) {
printf("env init failed!\n");
return;
}
if (!ota_download_http("http://119.139.199.196:2899/patch.bin")) {
printf("download successfully!\n");
} else {
printf("download failed!\n");
}
}
void application_entry(void *arg)
{
tos_sem_create(&sem, 0);
osThreadCreate(osThread(user_task), NULL); // Create task1
osThreadCreate(osThread(ota_download_task), NULL); // Create task2
}

View File

@@ -1,133 +0,0 @@
#include "mcu_init.h"
#include "sal_module_wrapper.h"
#include "cmsis_os.h"
//#define USE_ESP8266
//#define USE_SIM800A
//#define USE_BC26
//#define USE_EC20
//#define USE_EC200S
#define USE_M5313
#ifdef USE_ESP8266
#include "esp8266.h"
#endif
#ifdef USE_SIM800A
#include "sim800a.h"
#endif
#ifdef USE_BC26
#include "bc26.h"
#endif
#ifdef USE_EC20
#include "ec20.h"
#endif
#ifdef USE_EC200S
#include "ec200s.h"
#endif
#ifdef USE_M5313
#include "m5313.h"
#endif
#define SERVER_TCP_IP "119.139.199.196"
#define TCP_TEST_TASK0_STK_SIZE 4096
void tcp_test0(void);
osThreadDef(tcp_test0, osPriorityNormal, 1, TCP_TEST_TASK0_STK_SIZE);
#define TCP_TEST_TASK1_STK_SIZE 4096
void tcp_test1(void);
osThreadDef(tcp_test1, osPriorityNormal, 1, TCP_TEST_TASK1_STK_SIZE);
int socket_id_0 = -1;
int socket_id_1 = -1;
#define RECV_LEN 1024
uint8_t recv_data_0[RECV_LEN];
uint8_t recv_data_1[RECV_LEN];
void tcp_test0(void)
{
int recv_len = -1;
while (1) {
tos_sal_module_send(socket_id_0, (const void*)"This is TCP Test!\r\n", strlen("This is TCP Test!\r\n"));
recv_len = tos_sal_module_recv_timeout(socket_id_0, recv_data_0, sizeof(recv_data_0), 8000);
if (recv_len < 0) {
printf("task0 receive error\n");
} else if (recv_len == 0) {
printf("task0 receive none\n");
} else {
recv_data_0[recv_len] = 0;
printf("task0: receive len: %d\nmsg from remote: %s\n", recv_len, recv_data_0);
}
tos_sleep_ms(2000);
}
}
void tcp_test1(void)
{
int recv_len = -1;
while (1) {
tos_sal_module_send(socket_id_1, (const void *)"Hello Tencent!\r\n", strlen("Hello Tencent!\r\n"));
recv_len = tos_sal_module_recv_timeout(socket_id_1, recv_data_1, sizeof(recv_data_1), 8000);
if (recv_len < 0) {
printf("task1 receive error\n\r");
} else if (recv_len == 0) {
printf("task1 receive none\n");
} else {
recv_data_1[recv_len] = 0;
printf("task1: receive len: %d\nmsg from remote: %s\n", recv_len, recv_data_1);
}
tos_sleep_ms(2000);
}
}
void application_entry(void *arg)
{
#if defined(USE_ESP8266)
esp8266_sal_init(HAL_UART_PORT_0);
esp8266_join_ap("SheldonDai", "srnr6x9xbhmb0");
#elif defined(USE_SIM800A)
sim800a_power_on();
sim800a_sal_init(HAL_UART_PORT_2);
#elif defined(USE_BC26)
bc26_sal_init(HAL_UART_PORT_2);
#elif defined(USE_EC20)
ec20_sal_init(HAL_UART_PORT_0);
#elif defined(USE_EC200S)
ec200s_sal_init(HAL_UART_PORT_2);
#elif defined(USE_M5313)
m5313_sal_init(HAL_UART_PORT_2);
#endif
socket_id_0 = tos_sal_module_connect(SERVER_TCP_IP, "2898", TOS_SAL_PROTO_TCP);
if (socket_id_0 == -1) {
printf("TCP0 connect failed\r\n");
} else {
printf("TCP0 connect success! fd: %d\n", socket_id_0);
}
socket_id_1 = tos_sal_module_connect(SERVER_TCP_IP, "2899", TOS_SAL_PROTO_TCP);
if (socket_id_1 == -1) {
printf("TCP1 connect failed\r\n");
} else {
printf("TCP1 connect success! fd: %d\n", socket_id_1);
}
osThreadCreate(osThread(tcp_test0), NULL);
osThreadCreate(osThread(tcp_test1), NULL);
}

View File

@@ -1,15 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00040000 { ; RW data
.ANY (+RW +ZI)
}
}

File diff suppressed because one or more lines are too long

View File

@@ -1,451 +0,0 @@
;*******************************************************************************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x8000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x8000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
DFSDM1_FLT3_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
COMP_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
OTG_FS_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
LPUART1_IRQHandler
QUADSPI_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SAI1_IRQHandler
SAI2_IRQHandler
SWPMI1_IRQHandler
TSC_IRQHandler
LCD_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
DCMI_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

View File

@@ -1,15 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00040000 { ; RW data
.ANY (+RW +ZI)
}
}

File diff suppressed because one or more lines are too long

View File

@@ -1,451 +0,0 @@
;*******************************************************************************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x8000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x8000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
DFSDM1_FLT3_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
COMP_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
OTG_FS_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
LPUART1_IRQHandler
QUADSPI_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SAI1_IRQHandler
SAI2_IRQHandler
SWPMI1_IRQHandler
TSC_IRQHandler
LCD_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
DCMI_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

View File

@@ -1,15 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00040000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@@ -1,451 +0,0 @@
;*******************************************************************************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x8000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x8000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
DFSDM1_FLT3_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
COMP_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
OTG_FS_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
LPUART1_IRQHandler
QUADSPI_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SAI1_IRQHandler
SAI2_IRQHandler
SWPMI1_IRQHandler
TSC_IRQHandler
LCD_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
DCMI_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

View File

@@ -1,887 +0,0 @@
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<Define>USE_HAL_DRIVER,STM32L496xx,</Define>
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</File>
<File>
<FileName>onchip_flash_ota.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\BSP\Hardware\ONCHIP_FLASH\onchip_flash_ota.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>kernel</GroupName>
<Files>
<File>
<FileName>tos_binary_heap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_binary_heap.c</FilePath>
</File>
<File>
<FileName>tos_char_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_char_fifo.c</FilePath>
</File>
<File>
<FileName>tos_completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_completion.c</FilePath>
</File>
<File>
<FileName>tos_countdownlatch.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
</File>
<File>
<FileName>tos_event.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_event.c</FilePath>
</File>
<File>
<FileName>tos_global.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_global.c</FilePath>
</File>
<File>
<FileName>tos_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_mmblk.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_mmblk.c</FilePath>
</File>
<File>
<FileName>tos_mmheap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
</File>
<File>
<FileName>tos_mutex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_mutex.c</FilePath>
</File>
<File>
<FileName>tos_pend.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_pend.c</FilePath>
</File>
<File>
<FileName>tos_priority_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
</File>
<File>
<FileName>tos_ring_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
</File>
<File>
<FileName>tos_robin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_robin.c</FilePath>
</File>
<File>
<FileName>tos_sched.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_sched.c</FilePath>
</File>
<File>
<FileName>tos_sem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_sem.c</FilePath>
</File>
<File>
<FileName>tos_sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_sys.c</FilePath>
</File>
<File>
<FileName>tos_task.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_task.c</FilePath>
</File>
<File>
<FileName>tos_tick.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_tick.c</FilePath>
</File>
<File>
<FileName>tos_time.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_time.c</FilePath>
</File>
<File>
<FileName>tos_timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_timer.c</FilePath>
</File>
<File>
<FileName>tos_barrier.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_barrier.c</FilePath>
</File>
<File>
<FileName>tos_bitmap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_bitmap.c</FilePath>
</File>
<File>
<FileName>tos_rwlock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_rwlock.c</FilePath>
</File>
<File>
<FileName>tos_stopwatch.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\kernel\core\tos_stopwatch.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>cpu</GroupName>
<Files>
<File>
<FileName>port_s.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S</FilePath>
</File>
<File>
<FileName>tos_cpu.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c</FilePath>
</File>
<File>
<FileName>port_c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>cmsis</GroupName>
<Files>
<File>
<FileName>cmsis_os.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\osal\cmsis_os\cmsis_os.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>config</GroupName>
<Files>
<File>
<FileName>tos_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\..\..\TOS_CONFIG\tos_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>at</GroupName>
<Files>
<File>
<FileName>tos_at.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\net\at\src\tos_at.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>devices</GroupName>
<Files>
<File>
<FileName>m5313.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\devices\m5313\m5313.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>sal_module_wrapper</GroupName>
<Files>
<File>
<FileName>sal_module_wrapper.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>hal</GroupName>
<Files>
<File>
<FileName>tos_hal_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\hal\st\stm32l4xx\src\tos_hal_uart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>ota_download</GroupName>
<Files>
<File>
<FileName>ota_download_http.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\ota\download\protocol\http\ota_download_http.c</FilePath>
</File>
<File>
<FileName>hal_tcp_module.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\ota\download\transport_layer\tcp\module\hal_tcp_module.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>ota_common</GroupName>
<Files>
<File>
<FileName>ota_flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\ota\common\flash\ota_flash.c</FilePath>
</File>
<File>
<FileName>crc8.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\ota\common\crc\crc8.c</FilePath>
</File>
<File>
<FileName>ota_image.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\ota\common\image\ota_image.c</FilePath>
</File>
<File>
<FileName>ota_partition.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\ota\common\partition\ota_partition.c</FilePath>
</File>
<File>
<FileName>ota_env.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\ota\common\env\ota_env.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>kv</GroupName>
<Files>
<File>
<FileName>tos_kv.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\components\fs\kv\tos_kv.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.3.0" condition="Cortex-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.5.0"/>
<targetInfos>
<targetInfo name="TencentOS_tiny"/>
</targetInfos>
</component>
</components>
<files/>
</RTE>
</Project>

View File

@@ -1,450 +0,0 @@
;*******************************************************************************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x8000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x8000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
DFSDM1_FLT3_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
COMP_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
OTG_FS_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
LPUART1_IRQHandler
QUADSPI_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SAI1_IRQHandler
SAI2_IRQHandler
SWPMI1_IRQHandler
TSC_IRQHandler
LCD_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
DCMI_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

View File

@@ -1,337 +0,0 @@
/**
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | MSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/** @addtogroup STM32L4xx_System_Private_Includes
* @{
*/
#include "stm32l4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x7800 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000U;
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= 0xEAF6FFFFU;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000U;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
/* Get MSI Range frequency--------------------------------------------------*/
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
{ /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange;
break;
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource)
{
case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm);
break;
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr;
break;
default:
SystemCoreClock = msirange;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,57 +0,0 @@
/**
******************************************************************************
* File Name : gpio.h
* Description : This file contains all the functions prototypes for
* the gpio
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __gpio_H
#define __gpio_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_GPIO_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ pinoutConfig_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,135 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
void _Error_Handler(char *file, int line);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define KEY1_Pin GPIO_PIN_2
#define KEY1_GPIO_Port GPIOE
#define LED5_Pin GPIO_PIN_3
#define LED5_GPIO_Port GPIOE
#define SENSOR_EN_Pin GPIO_PIN_5
#define SENSOR_EN_GPIO_Port GPIOE
#define SENSOR_INT1_Pin GPIO_PIN_6
#define SENSOR_INT1_GPIO_Port GPIOE
#define SENSOR_INT2_Pin GPIO_PIN_13
#define SENSOR_INT2_GPIO_Port GPIOC
#define GPS_ON_Pin GPIO_PIN_1
#define GPS_ON_GPIO_Port GPIOB
#define BD_EN_Pin GPIO_PIN_2
#define BD_EN_GPIO_Port GPIOB
#define GPS_RST_Pin GPIO_PIN_7
#define GPS_RST_GPIO_Port GPIOE
#define NB_RST_Pin GPIO_PIN_8
#define NB_RST_GPIO_Port GPIOE
#define NB_WKUP_Pin GPIO_PIN_9
#define NB_WKUP_GPIO_Port GPIOE
#define NB_EN_Pin GPIO_PIN_11
#define NB_EN_GPIO_Port GPIOE
#define SEL1_Pin GPIO_PIN_12
#define SEL1_GPIO_Port GPIOE
#define SEL2_Pin GPIO_PIN_13
#define SEL2_GPIO_Port GPIOE
#define SEL3_Pin GPIO_PIN_14
#define SEL3_GPIO_Port GPIOE
#define KEY4_Pin GPIO_PIN_15
#define KEY4_GPIO_Port GPIOE
#define OLED_RST_Pin GPIO_PIN_12
#define OLED_RST_GPIO_Port GPIOB
#define OLED_EN_Pin GPIO_PIN_15
#define OLED_EN_GPIO_Port GPIOB
#define AU_CTR_Pin GPIO_PIN_8
#define AU_CTR_GPIO_Port GPIOD
#define AU_RST_Pin GPIO_PIN_13
#define AU_RST_GPIO_Port GPIOD
#define AU_EN_Pin GPIO_PIN_15
#define AU_EN_GPIO_Port GPIOD
#define CHARGE_STATE_Pin GPIO_PIN_6
#define CHARGE_STATE_GPIO_Port GPIOC
#define CARD_EN_Pin GPIO_PIN_7
#define CARD_EN_GPIO_Port GPIOC
#define PCIE_RST_Pin GPIO_PIN_8
#define PCIE_RST_GPIO_Port GPIOA
#define PCIE_EN_Pin GPIO_PIN_9
#define PCIE_EN_GPIO_Port GPIOA
#define CARD_END5_Pin GPIO_PIN_5
#define CARD_END5_GPIO_Port GPIOD
#define KEY3_Pin GPIO_PIN_6
#define KEY3_GPIO_Port GPIOD
#define KEY2_Pin GPIO_PIN_7
#define KEY2_GPIO_Port GPIOD
#define LED4_Pin GPIO_PIN_5
#define LED4_GPIO_Port GPIOB
#define LED3_Pin GPIO_PIN_8
#define LED3_GPIO_Port GPIOB
#define IR_OUT_Pin GPIO_PIN_9
#define IR_OUT_GPIO_Port GPIOB
#define LED2_Pin GPIO_PIN_0
#define LED2_GPIO_Port GPIOE
#define LED1_Pin GPIO_PIN_1
#define LED1_GPIO_Port GPIOE
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,450 +0,0 @@
/**
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_CONF_H
#define __STM32L4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
#define HAL_CRC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_DCMI_MODULE_ENABLED */
/*#define HAL_DMA2D_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */
/*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_FIREWALL_MODULE_ENABLED */
/*#define HAL_GFXMMU_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LTDC_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_SWPMI_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_EXTI_MODULE_ENABLED */
/*#define HAL_PSSI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal Multiple Speed oscillator (MSI) default value.
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/**
* @brief External clock source for SAI2 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32l4xx_hal_rcc.h"
#include "stm32l4xx_hal_rcc_ex.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32l4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32l4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32l4xx_hal_dma.h"
#include "stm32l4xx_hal_dma_ex.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32l4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32l4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32l4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32l4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l4xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32l4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32l4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32l4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32l4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32l4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32l4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_FIREWALL_MODULE_ENABLED
#include "stm32l4xx_hal_firewall.h"
#endif /* HAL_FIREWALL_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32l4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32l4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32l4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32l4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32l4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32l4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l4xx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32l4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32l4xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32l4xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_PKA_MODULE_ENABLED
#include "stm32l4xx_hal_pka.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32l4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32l4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32l4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32l4xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l4xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32l4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32l4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32l4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32l4xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
#ifdef HAL_PSSI_MODULE_ENABLED
#include "stm32l4xx_hal_pssi.h"
#endif /* HAL_PSSI_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(char *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,69 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_IT_H
#define __STM32L4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -1,450 +0,0 @@
;*******************************************************************************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x6000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
DFSDM1_FLT3_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
COMP_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
OTG_FS_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
LPUART1_IRQHandler
QUADSPI_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SAI1_IRQHandler
SAI2_IRQHandler
SWPMI1_IRQHandler
TSC_IRQHandler
LCD_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
DCMI_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

View File

@@ -1,172 +0,0 @@
/**
******************************************************************************
* File Name : gpio.c
* Description : This file provides code for the configuration
* of all used GPIO pins.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gpio.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure GPIO */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/** Configure pins as
* Analog
* Input
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, LED5_Pin|LED2_Pin|LED1_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, SENSOR_EN_Pin|GPS_RST_Pin|NB_RST_Pin|NB_WKUP_Pin
|NB_EN_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, GPS_ON_Pin|BD_EN_Pin|OLED_RST_Pin|OLED_EN_Pin
|LED3_Pin|IR_OUT_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, AU_CTR_Pin|AU_RST_Pin|AU_EN_Pin|CARD_END5_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(CARD_EN_GPIO_Port, CARD_EN_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(PCIE_RST_GPIO_Port, PCIE_RST_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(PCIE_EN_GPIO_Port, PCIE_EN_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET);
/*Configure GPIO pins : KEY1_Pin SEL1_Pin SEL2_Pin SEL3_Pin
KEY4_Pin */
GPIO_InitStruct.Pin = KEY1_Pin|SEL1_Pin|SEL2_Pin|SEL3_Pin
|KEY4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pins : LED5_Pin SENSOR_EN_Pin GPS_RST_Pin NB_RST_Pin
NB_WKUP_Pin NB_EN_Pin LED2_Pin LED1_Pin */
GPIO_InitStruct.Pin = LED5_Pin|SENSOR_EN_Pin|GPS_RST_Pin|NB_RST_Pin
|NB_WKUP_Pin|NB_EN_Pin|LED2_Pin|LED1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pin : SENSOR_INT1_Pin */
GPIO_InitStruct.Pin = SENSOR_INT1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(SENSOR_INT1_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : SENSOR_INT2_Pin */
GPIO_InitStruct.Pin = SENSOR_INT2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(SENSOR_INT2_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : PA5 PA6 */
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pin : PB0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : GPS_ON_Pin BD_EN_Pin OLED_RST_Pin OLED_EN_Pin
LED4_Pin LED3_Pin IR_OUT_Pin */
GPIO_InitStruct.Pin = GPS_ON_Pin|BD_EN_Pin|OLED_RST_Pin|OLED_EN_Pin
|LED4_Pin|LED3_Pin|IR_OUT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : AU_CTR_Pin AU_RST_Pin AU_EN_Pin CARD_END5_Pin */
GPIO_InitStruct.Pin = AU_CTR_Pin|AU_RST_Pin|AU_EN_Pin|CARD_END5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pin : CHARGE_STATE_Pin */
GPIO_InitStruct.Pin = CHARGE_STATE_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(CHARGE_STATE_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : CARD_EN_Pin */
GPIO_InitStruct.Pin = CARD_EN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(CARD_EN_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : PCIE_RST_Pin PCIE_EN_Pin */
GPIO_InitStruct.Pin = PCIE_RST_Pin|PCIE_EN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pins : KEY3_Pin KEY2_Pin */
GPIO_InitStruct.Pin = KEY3_Pin|KEY2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,249 +0,0 @@
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#include "stdio.h"
#include "stm32l4xx_hal.h"
#include "ota_recovery.h"
#include "tos_kv.h"
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_USART1_UART_Init(void);
UART_HandleTypeDef huart1;
int fputc(int ch, FILE *f)
{
if (ch == '\n') {
HAL_UART_Transmit(&huart1, (void *)"\r", 1,30000);
}
HAL_UART_Transmit(&huart1, (uint8_t *)&ch, 1, 0xFFFF);
return ch;
}
extern ota_flash_drv_t stm32l4_norflash_onchip_drv_ota;
extern ota_flash_prop_t stm32l4_norflash_onchip_prop_ota;
int main(void)
{
ota_err_t ret;
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* Configure the system clock */
SystemClock_Config();
MX_GPIO_Init();
MX_USART1_UART_Init();
uint32_t partition_addr = 0x080FF800;
if ((ret = ota_env_init(OTA_UPDATE_IN_POSITION, partition_addr, &stm32l4_norflash_onchip_drv_ota, &stm32l4_norflash_onchip_prop_ota)) != OTA_ERR_NONE) {
printf("env init failed!OTA errcode = %d\n", ret);
return -1;
} else {
printf("env init successfully!\r\n");
printf("+-------------------------+\r\n");
printf("|Active APP | 0x%08x |\r\n", ota_partition_start(OTA_PARTITION_ACTIVE_APP));
printf("| OTA | 0x%08x |\r\n", ota_partition_start(OTA_PARTITION_OTA));
printf("| KV | 0x%08x |\r\n", ota_partition_start(OTA_PARTITION_KV));
printf("| Version | %d.%d |\r\n", ota_partition_init_version_get().major, ota_partition_init_version_get().minor);
printf("+-------------------------+\r\n");
}
// while(1)
// {;}
//ota_img_vs_t new_version;
//new_version.major = 0;
//new_version.minor = 2;
//tos_kv_set("new_version", &new_version, sizeof(ota_img_vs_t));
#if 0
if ((ret = ota_recovery_xip()) != OTA_ERR_NONE) {
printf("recovery failed, OTA errcode = %d!\r\n", ret);
} else {
printf("recovery successfully!\r\n");
}
#else
if ((ret = ota_recovery()) != OTA_ERR_NONE) {
printf("recovery failed, OTA errcode = %d!\r\n", ret);
} else {
printf("recovery successfully!\r\n");
}
#endif
uint32_t jmp_addr, app_addr = ota_partition_start(OTA_PARTITION_ACTIVE_APP);
/* test if user code is programmed starting from address app_addr */
if (((*(uint32_t *)app_addr) & 0x2FFE0000) == 0x20000000) {
/* Jump to user application */
jmp_addr = *(uint32_t *)(app_addr + 4);
/* Initialize user application's Stack Pointer */
__set_MSP(*(uint32_t *)app_addr);
((void (*)(void))jmp_addr)();
}
}
void _Error_Handler(char *file, int line)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
printf("err %s,L%d\r\n",file,line);
}
/* USER CODE END Error_Handler_Debug */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInit;
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = 0;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2
|RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART4
|RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_SAI2
|RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_I2C3
|RCC_PERIPHCLK_USB|RCC_PERIPHCLK_SDMMC1
|RCC_PERIPHCLK_ADC;
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLLSAI1;
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLSAI1;
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV4;
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV4;
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV4;
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK
|RCC_PLLSAI1_ADC1CLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure the Systick interrupt time
*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
/**Configure the Systick
*/
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
}
/**
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(char *file, uint32_t line)
{
}
#endif /* USE_FULL_ASSERT */

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@@ -1,153 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : stm32l4xx_hal_msp.c
* Description : This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#include "stm32l4xx_hal.h"
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief CRC MSP Initialization
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
/**
* @brief CRC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspDeInit 0 */
/* USER CODE END CRC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CRC_CLK_DISABLE();
/* USER CODE BEGIN CRC_MspDeInit 1 */
/* USER CODE END CRC_MspDeInit 1 */
}
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,202 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
__weak void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32L4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32l4xx.s). */
/******************************************************************************/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,337 +0,0 @@
/**
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | MSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/** @addtogroup STM32L4xx_System_Private_Includes
* @{
*/
#include "stm32l4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000U;
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= 0xEAF6FFFFU;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000U;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
/* Get MSI Range frequency--------------------------------------------------*/
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
{ /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange;
break;
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource)
{
case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm);
break;
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr;
break;
default:
SystemCoreClock = msirange;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,19 +0,0 @@
#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
#include "stm32l4xx.h"
#define TOS_CFG_EVENT_DRIVEN_EN 1u
#define TOS_CFG_MMHEAP_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x8000
#define TOS_CFG_PWR_MGR_EN 0u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
#endif

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@@ -1,48 +0,0 @@
/*
* @Author: jiejie
* @Github: https://github.com/jiejieTop
* @Date: 2019-12-15 00:42:16
* @LastEditTime: 2020-02-25 09:25:35
* @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
*/
#ifndef _MQTT_CONFIG_H_
#define _MQTT_CONFIG_H_
//#define LOG_IS_SALOF
#define LOG_LEVEL DEBUG_LEVEL //WARN_LEVEL DEBUG_LEVEL
#ifdef LOG_IS_SALOF
#define USE_LOG (1U)
#define USE_SALOF (1U)
#define SALOF_OS USE_TENCENTOS
#define USE_IDLE_HOOK (0U)
#define LOG_COLOR (0U)
#define LOG_TS (0U)
#define LOG_TAR (0U)
#define SALOF_BUFF_SIZE (512U)
#define SALOF_FIFO_SIZE (1024U)
#define SALOF_TASK_STACK_SIZE (1024U)
#define SALOF_TASK_TICK (50U)
#endif
#define MQTT_MAX_PACKET_ID (0xFFFF - 1)
#define MQTT_TOPIC_LEN_MAX 64
#define MQTT_ACK_HANDLER_NUM_MAX 64
#define MQTT_DEFAULT_BUF_SIZE 1024
#define MQTT_DEFAULT_CMD_TIMEOUT 4000
#define MQTT_MAX_CMD_TIMEOUT 20000
#define MQTT_MIN_CMD_TIMEOUT 1000
#define MQTT_KEEP_ALIVE_INTERVAL 100 // unit: second
#define MQTT_VERSION 4 // 4 is mqtt 3.1.1
#define MQTT_RECONNECT_DEFAULT_DURATION 1000
#define MQTT_THREAD_STACK_SIZE 2048
#define MQTT_THREAD_PRIO 5
#define MQTT_THREAD_TICK 50
#define MQTT_NETSOCKET_USE_AT
//#define MQTT_NETWORK_TYPE_TLS
#endif /* _MQTT_CONFIG_H_ */

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@@ -1,41 +0,0 @@
#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
#include "stm32l4xx.h"
#define TOS_CFG_TASK_PRIO_MAX 10u
#define TOS_CFG_ROUND_ROBIN_EN 1u
#define TOS_CFG_OBJECT_VERIFY_EN 1u
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
#define TOS_CFG_EVENT_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#define TOS_CFG_MMHEAP_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x6000
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 1u
#define TOS_CFG_TICKLESS_EN 1u
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_IDLE_TASK_STK_SIZE 512u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
#define TOS_CFG_TIMER_AS_PROC 1u
#endif

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@@ -1,55 +0,0 @@
#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
#include "stm32l4xx.h"
#define TOS_CFG_TASK_PRIO_MAX 10u
#define TOS_CFG_ROUND_ROBIN_EN 0u
#define TOS_CFG_OBJECT_VERIFY_EN 1u
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
#define TOS_CFG_EVENT_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#define TOS_CFG_MMHEAP_EN 0u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x2000
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_MESSAGE_QUEUE_EN 1u
#define TOS_CFG_MAIL_QUEUE_EN 1u
#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 0u
#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 0u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 0u
#define TOS_CFG_TICKLESS_EN 0u
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
#define TOS_CFG_TIMER_AS_PROC 1u
#endif

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@@ -1,15 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00040000 { ; RW data
.ANY (+RW +ZI)
}
}

File diff suppressed because one or more lines are too long

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@@ -1,48 +0,0 @@
/*
* @Author: jiejie
* @Github: https://github.com/jiejieTop
* @LastEditTime: 2020-06-17 19:31:41
* @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
*/
#ifndef _MQTT_CONFIG_H_
#define _MQTT_CONFIG_H_
//#define MQTT_LOG_IS_SALOF
#define MQTT_NETSOCKET_USING_AT
#define MQTT_LOG_LEVEL MQTT_LOG_DEBUG_LEVEL //MQTT_LOG_WARN_LEVEL MQTT_LOG_DEBUG_LEVEL
#ifdef MQTT_LOG_IS_SALOF
#define SALOF_USING_LOG (1U)
#define SALOF_USING_SALOF (1U)
#define SALOF_LOG_LEVEL MQTT_LOG_LEVEL
#define SALOF_OS SALOF_USING_TENCENTOS
#define SALOF_USING_IDLE_HOOK (0U)
#define SALOF_LOG_COLOR (1U)
#define SALOF_LOG_TS (0U)
#define SALOF_LOG_TAR (0U)
#define SALOF_BUFF_SIZE 512
#define SALOF_FIFO_SIZE 4096
#define SALOF_TASK_STACK_SIZE 1024
#define SALOF_TASK_TICK 50
#endif
#define MQTT_MAX_PACKET_ID (0xFFFF - 1)
#define MQTT_TOPIC_LEN_MAX 64
#define MQTT_ACK_HANDLER_NUM_MAX 64
#define MQTT_DEFAULT_BUF_SIZE 1024
#define MQTT_DEFAULT_CMD_TIMEOUT 10000
#define MQTT_MAX_CMD_TIMEOUT 20000
#define MQTT_MIN_CMD_TIMEOUT 10000
#define MQTT_KEEP_ALIVE_INTERVAL 50 // unit: second
#define MQTT_VERSION 4 // 4 is mqtt 3.1.1
#define MQTT_RECONNECT_DEFAULT_DURATION 1000
#define MQTT_THREAD_STACK_SIZE 2048
#define MQTT_THREAD_PRIO 5
#define MQTT_THREAD_TICK 50
#define MQTT_NETWORK_TYPE_NO_TLS
#endif /* _MQTT_CONFIG_H_ */

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@@ -1,62 +0,0 @@
#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
////#include "stm32l0xx_hal.h"
#include <stdio.h>
#include "stm32l4xx_hal.h"
#define TOS_CFG_TASK_PRIO_MAX 10u
#define TOS_CFG_ROUND_ROBIN_EN 0u
#define TOS_CFG_OBJECT_VERIFY_EN 0u
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
#define TOS_CFG_EVENT_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#define TOS_CFG_MMHEAP_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x8000
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_MESSAGE_QUEUE_EN 1u
#define TOS_CFG_LIBC_PRINTF_EN 1u
#define TOS_CFG_MAIL_QUEUE_EN 1u
#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 0u
#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 0u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 0u
#define TOS_CFG_TICKLESS_EN 0u
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 0u
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
#define TOS_CFG_TIMER_AS_PROC 1u
#endif

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@@ -1,120 +0,0 @@
# 开发板BDW01入门介绍
---
## 1. 开发板特性
BDW01物联网开发板的板载资源如下
![](./image/board.png)
主控芯片采用STM32L4VGTxFlash空间大小1MBSRAM空间大小320KB
- 板载中移物联NB-IOT模组M5313
- 板载中科微北斗定位模组ATGM336H
- 板载环境光检测传感器TMD27713;
- 板载压力传感器BMP280;
- 板载温湿度传感器SHT3X;
- 板载3D加速度陀螺仪传感器LSM6DSL;
- 板载磁力计传感器MMC3680KJ;
- 板载E43接口可扩展其他无线通信模块
- 板载E32接口可扩展其他定位模块
- 板载E53传感器标准接口方便连接各种E53传感器
- 板载0.91'OLED显示屏幕
- 板载新塘语离线音识别模块ISD9160
- 板载TF卡卡座方便扩展存储空间
- 板载MINI PCIE接口方便连接4G通信模块
- 板载18650锂电池插座方便移动时正常供电
- 板载CH340转串口连接可以使用一根USB线连接至电脑查看串口日志
关于开发板硬件电路的更多信息和详解请查看文档BDW01主板规格书和文档物联网开发板原理图。
## 2. 开发板硬件准备
### 2.1 连接LOG USB线
![](./image/logusb.png)
### 2.2 连接ST-Link烧录器
对照烧录器引脚图和开发板原理图找到开发板上的网络标号SW11,连接如下:
**注意电源正负极不要接反接错避免烧掉MCU和烧录器。**
![](./image/st-link.png)
- 开发板VCC(3v3) ---> STlink  3.3V
- 开发板ST_SWDIO ---> STlink  SWDIO
- 开发板ST_SWCLK ---> STlink  SWCLK
- 开发板GND ---> STlink  GND
## 3. 开发软件的环境准备
### 3.1 软件开发工具的下载安装
我们使用的软件开发工具是Keil公司的MDK(Microcontroller Development kit)MDK官网下载地址[http://www2.keil.com/mdk5](http://www2.keil.com/mdk5)
下载的版本最好在5.24或5.24以上本次介绍以5.25版本为例双击MDK524应用程序文件接着点击next>>。
![](./image/mtkdl01.png)
在I agree前面的小方框打勾表示同意该安装协议再点击next>>。
![](./image/mtkdl02.png)
选择安装路径默认情况下会安装在系统盘C盘建议在其他盘建立单独的文件夹并选择安装到该文件夹下。点击next>>。
![](./image/mtkdl03.png)
填上我们的信息后继续next>>。
![](./image/mtkdl04.png)
然后等待安装完成后点击Finish,接着会跳出器件支持包安装界面点OK再把弹框都叉掉后续再介绍。最后要激活MDK导入License,激活MDK后就可以使用了。
![](./image/mtkdl05.png)
特别提示一定要输入License激活MDK软件建议购买正版License。
### 3.2 安装器件支持包
MDK V4版本安装包里集成了器件的支持包而MDK V5版本是独立出来的可以自己下载安装。安装完开发工具MDK V5后我们需要安装开发板主芯片型号对应的芯片器件支持包。
#### 3.2.1 安装方式一
登录官网:[http://www.keil.com/dd2/pack/](http://www.keil.com/dd2/pack/)
下载Keil.STM32L4xx_DFP.x.x.x.pack 完成后,双击打开安装。
#### 3.2.2 安装方式二
MDK软件上在线安装一般下载速度会比较慢更新时间很长不推荐。
打开软件在导航栏打开Pack安装界面弹出包安装提示点击ok选项。
![](./image/mtkins01.png)
进入在线安装界面选择STM32L4XX Pack,点击Install进行安装。
![](./image/mtkins02.png)
### 3.3 CH340串口驱动安装
BDW01开发板板载USB转串口芯片所以使用USB线将开发板连接到电脑就在串口调试助手查看串口输出的LOG信息。使用串口调试助手之前需要下载安装CH340转串口芯片的驱动。直接在网上搜索下载CH340转串口芯片的驱动下载完成后打开驱动安装程序点击安装即可。
![](./image/ch340ins01.png)
### 3.4 串口调试助手的安装与使用
工具下载网址:[http://www.daxia.com/download/sscom.rar](http://www.daxia.com/download/sscom.rar)
下载完成后,解压,双击打开串口调试助手执行程序,直接使用。
![](./image/ch340ins02.png)
使用USB线一端接开发板LOG USB串口另一端连接到电脑前面安装完CH340转串口芯片的驱动打开电脑的设备管理器就可以在端口列表查看PC与开发板之间连接端口号然后在串口调试助手-端口号处选择PC和开发板之间的连接端口(我这里显示的是COM15所以要在串口调试助手中选择COM15)。
![](./image/ch340ins03.png)
再根据开发板串口波特率设置串口调试助手-波特率开发板程序波特率设置为115200所以在串口调试助手中选择115200波特率。最后打开串口就可以使用了。
### 3.5 ST-Link驱动的下载与安装
前面2.2介绍过开发板与ST-Link烧录器的接线方式在使用烧录器将程序烧录到开发板之前需要安装烧录器的驱动。
在ST官网下载ST-Link驱动STSW-LINK009下载网址
[https://www.st.com/content/st_com/zh/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-utilities/stsw-link009.html](https://www.st.com/content/st_com/zh/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-utilities/stsw-link009.html)
再根据电脑系统安装驱动32位电脑系统安装dpinst_x86.exe64位电脑系统安装dpinst_amd64.exe 。 
![](./image/st-link-dl01.png)
运行对应的驱动执行程序开始安装ST-Link V2驱动最后点击完成。
![](./image/st-link-dl02.png)
安装完成后, 将开发板电源打开将连着开发板的烧录器通过USB接口连至电脑。
打开电脑上的设备管理器。若可以看到通用串行总线设备-STM32 STLink,表示驱动安装成功,如下图所示。
![](./image/st-link-dl03.png)
## 4. 开发与调试
前面的软硬件工作准备好之后接下来就可以进行开发与调试了。示例工程hello_world的主要功能是创建两个任务两个任务循环输出打印 。
路径TencentOS-tiny\board\BDW01-STM32L496VG\KEIL\hello_world。
打开示例工程hello_world进入到MDK keil5主窗口界面
![](./image/helloword00.png)
点击 Build Target 编译工程目标:
![](./image/helloword01.png)
编译完成后查看消息窗口0 Error(s),表示代码没有语法错误。
![](./image/helloword02.png)
LOG USB线和烧录器ST-Link/v2都连接到电脑串口调试助手也配置好并打开。
点击 Download 下载程序到开发板。
下载完成后,在开发板上按下复位按钮,查看串口调试助手上接收数据的显示。
![](./image/helloword03.png)

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@@ -1,32 +0,0 @@
# TCP Socket 通讯测试
---
本示例会启动两个线程建立两个TCP链接分别发送数据
M5313可同时支持4个链接不过在代码默认定义的是3个有需要可以修改为4个或根据自己需要进行修改。
路径TencentOS-tiny\net\at\include\tos_at.h
![](./image/tcpsocket01.png)
## 1. 搭建TCP服务器
M5313 使用2G网络本地PC使用的是局域网这里做了一个服务器的内网穿透然后百度ip查看服务器的外网IP。
这里使用SocketTool建立TCP server。
## 2. 运行工程
使用 Keil-MDK 打开 tcp_through_module工程
路径TencentOS-tiny\board\BDW01-STM32L496VG\KEIL\tcp_through_module
![](./image/tcpsocket02.png)
打开2g模块M5313的串口接收
![](./image/tcpsocket03.png)
打开tcp_through_module.c文件根据自己的TCP服务器地址修改配置:
![](./image/tcpsocket04.png)
修改完成后点击编译按钮编译编译成功之后烧录到开发板默认使用ST-Link下载器
烧录之后按下开发板上的复位按钮,程序开始运行,在串口助手查看日志:
![](./image/tcpsocket05.png)
在TCP服务器上可查看收到的数据
![](./image/tcpsocket06.png)
![](./image/tcpsocket07.png)

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@@ -1,328 +0,0 @@
# 对接腾讯云与腾讯连连-测试
----------
本示例示范如何对接到腾讯云物联网开发平台IoT Explore和腾讯连连小程序
## 1.云端操作步骤
登录[腾讯云物联网开发平台IoT Explorer](https://cloud.tencent.com/product/iotexplorer "腾讯云物联网开发平台IoT Explorer"),点击“立即使用”进入控制台,个人开发可以使用微信进行登录。
### 1.1 新建项目
项目是为了用户面对不同的产品迭代或不同的项目角色而设计的一种隔离机制,便于用户清晰管理物联网项目,并能灵活地配置项目权限。
1. 项目下可以建立多个产品与应用,应用默认有权限访问该项目下的所有产品;
2. 每个项目会有自己的唯一 ID数据会根据项目进行隔离以确保数据安全
3. 项目删除后,该项目所属产品等数据都将被删除且不能恢复;
4. 开发平台提供资源级的权限控制,可为不同的子用户分配项目级、产品级的权限控制;
点击新建项目,填写项目名称和简介:
![](./image/iot01.png)
### 1.2. 产品开发
#### 1.2.1 新建产品
点击项目名称进入到该项目中,点击新建产品:
![](./image/iot02.png)
填写产品的一些信息:
1. 产品名称名称为中文、字母、数字、下划线的组合1 - 20位且不能为空。
2. 产品品类:选择您所创建产品的所属品类,不同类型产品的属性、事件等数据模板会有所不同。详情请参见 数据模板。
3. 设备类型设备使用2G/3G/4G/Wi-Fi无线通信或有线通信方式网关可提供云端通信能力帮助设备与平台通信。
4. 认证方式:物联网开发平台提供两种认证方式用于设备与平台之间鉴权认证。
证书认证:在创建设备时,平台将为设备生成一个证书文件和一个私钥文件,实现设备与云之间的双向认证。
密钥认证:在创建设备时,使用平台为设备随机生成的 PSK。
5. 通信方式:您可以选择 Wi-Fi、移动蜂窝2G/3G/4G和其他通信方式。
6. 数据协议:默认采用数据模板的数据协议,您也可以自定义协议进行透传。
7. 描述字数不能超过80个您可以根据需要选填。
![](./image/iot03.png)
产品新建成功后,可在产品列表页查看到“智能灯”。
![](./image/iot04.png)
#### 1.2.2 数据模版
数据模板是将物理实体设备进行数字化描述,构建其数字模型。在物联网开发平台定义数据模板即定义产品功能。完成功能定义后,系统将自动生成该产品的数据模板。
点击智能灯产品进入。
##### 1.2.2.1
选择“智能灯”类型后,系统会自动生成标准功能:
![](./image/iot05.png)
#### 1.2.2.2
下方的新建功能,可以增加新的功能,定义如下:
![](./image/iot06.png)
功能类型包含三元素:
1. 属性包括布尔型、整数型、字符型、浮点型、枚举型和时间型等6种基本数据类型
2. 事件包括告警、故障和信息三种类型事件型功能属性可以添加具体的事件参数这些参数可以由属性中6种基本数据类型组成
3. 行为用于实现更复杂的业务逻辑可包含输入参数和输出参数可用于让设备执行某项特定的任务。行为的输入参数和输出参数可添加上述6种属性的基本数据类型。
| 功能元素 | 功能描述 | 功能标识符 |
| -------- | --------- | ----------- |
| 属性 | 用于描述设备的实时状态,支持读取和设置,如模式、亮度、开关等。 | PropertiesId |
| 事件 | 用于描述设备运行时的事件,包括告警、信息和故障等三种事件类型,可添加多个输出参数,如环境传感器检测到空气质量很差,空调异常 | EventId |
| 行为 | 用于描述复杂的业务逻辑,可添加多个调用参数和返回参数,用于让设备执行某项定特定的任务,例如,开锁动作需要知道是哪个用户在什么时间开锁,锁的状态如何等。 | ActionId |
数据类型支持6种
1.布尔型:非真即假的二值型变量。例如,开关功能。
2.整数型:可用于线性调节的整数变量。例如,空调的温度。
3.字符型:以字符串形式表达的功能点,例如,灯的位置。
4.浮点型精度为浮点型的功能点。例如压力值的范围0.0 - 24.0。
5.枚举型:自定义的有限集合值。例如,灯的颜色:白色、红色、黄色等。
6.时间型string 类型的 UTC 时间戳(毫秒)。
#### 1.2.3
数据模板是一个 JSON 格式的文件使用数据模板协议用户的设备需按数据模板定义要求传输设备数据到云端并可使用基于数据模板的诸多业务功能点击查看json可以看到上面创建功能的json格式
![](./image/iot07.png)
```c
{
"version": "1.0",
"properties": [
{
"id": "power_switch",
"name": "电灯开关",
"desc": "控制电灯开灭",
"required": true,
"mode": "rw",
"define": {
"type": "bool",
"mapping": {
"0": "关",
"1": "开"
}
}
},
{
"id": "color",
"name": "颜色",
"desc": "灯光颜色",
"mode": "rw",
"define": {
"type": "enum",
"mapping": {
"0": "Red",
"1": "Green",
"2": "Blue"
}
}
},
{
"id": "brightness",
"name": "亮度",
"desc": "灯光亮度",
"mode": "rw",
"define": {
"type": "int",
"unit": "%",
"step": "1",
"min": "0",
"max": "100",
"start": "1"
}
},
{
"id": "name",
"name": "灯位置名称",
"desc": "灯位置名称:书房、客厅等",
"mode": "rw",
"required": false,
"define": {
"type": "string",
"min": "0",
"max": "64"
}
}
],
"events": [
{
"id": "status_report",
"name": "DeviceStatus",
"desc": "Report the device status",
"type": "info",
"required": false,
"params": [
{
"id": "status",
"name": "running_state",
"desc": "Report current device running state",
"define": {
"type": "bool",
"mapping": {
"0": "normal",
"1": "fault"
}
}
},
{
"id": "message",
"name": "Message",
"desc": "Some extra message",
"define": {
"type": "string",
"min": "0",
"max": "64"
}
}
]
},
{
"id": "low_voltage",
"name": "LowVoltage",
"desc": "Alert for device voltage is low",
"type": "alert",
"required": false,
"params": [
{
"id": "voltage",
"name": "Voltage",
"desc": "Current voltage",
"define": {
"type": "float",
"unit": "V",
"step": "1",
"min": "0.0",
"max": "24.0",
"start": "1"
}
}
]
},
{
"id": "hardware_fault",
"name": "Hardware_fault",
"desc": "Report hardware fault",
"type": "fault",
"required": false,
"params": [
{
"id": "name",
"name": "Name",
"desc": "Name like: memory,tf card, censors ...",
"define": {
"type": "string",
"min": "0",
"max": "64"
}
},
{
"id": "error_code",
"name": "Error_Code",
"desc": "Error code for fault",
"define": {
"type": "int",
"unit": "",
"step": "1",
"min": "0",
"max": "2000",
"start": "1"
}
}
]
}
],
"actions": [],
"profile": {
"ProductId": "S7271EG5D8",
"CategoryId": "3"
}
}
```
### 1.3. 创建测试设备
在【设备调试】页面中,单击【新建设备】,设备名为 bdw01_led
![](./image/iot08.png)
## 2. 设备侧操作
使用 Keil-MDK 打开 mqttclient_iot_explorer 工程:
TencentOS-tiny\board\BDW01-STM32L496VG\KEIL\mqttclient_iot_explorer
![](./image/iot09.png)
### 2.1 配置使用的网络设备
打开mqttclient_iot_explorer.c文件修改配置。
修改本工程所使用的通信模组打开USE_M5313如图
![](./image/iot10.png)
#### 2.1.1 修改MQTT对接参数
在腾讯云物联网开发平台可以看到一些产品ID、设备ID、设备秘钥三个参数如图
![](./image/iot11.png)
接下来进入TencentOS-tiny仓库中的tools目录使用python运行脚本mqtt_config_gen.py按照提示输出刚刚在平台查询到的三个参数脚本会自动生成mqtt配置参数
![](./image/iot12.png)
① 输入产品ID
② 输入设备名称;
③ 输入设备秘钥;
④ ⑤ 保持默认,直接回车;
⑥ 需要的生成信息。
接下来在代码中修改配置信息:
![](./image/iot13.png)
#### 2.1.2 修改mqtt对接topic
设备向云端上报数据的topic如下
上行请求 Topic $thing/up/property/{ProductID}/{DeviceName}
上行响应 Topic $thing/down/property/{ProductID}/{DeviceName}
这两个topic咋玩呢
首先订阅上行响应topic接着向上行请求topic上报数据上报数据时平台不仅规定了topic还规定了数据内容如下
```c
{
"method":"report",
"clientToken":"clientToken-145023f5-bc9b-4174-ba3b-430ba5956e5c",
"params":
{
"brightness":55,
"name":"bedroom",
"power_switch":1,
"color":2
}
}
```
其中每一项的意义如下:
| 参数 | 类型 | 说明 |
| -------- | --------- | ----------- |
| method | String | report 表示设备属性上报 |
| clientToken | String | 用于上下行消息配对标识 |
| timestamp | Integer | 属性上报的时间 |
| params | JSON | JSON 结构内为设备上报的属性值 |
同时因为订阅了上行响应topic所以模组会收到云端下发的响应并通过URC模式上报云端响应报文整理一下格式如下
```c
{
"method":"report_reply",
"clientToken":"clientToken-145023f5-bc9b-4174-ba3b-430ba5956e5c",
"code":0,
"status":"success"}
```
其中每一项也有具体的含义:
| 参数 | 类型 | 说明 |
| -------- | --------- | ----------- |
| method | String | report_reply 表示云端接收设备上报后的响应报文 |
| clientToken | String | 用于上下行消息配对标识 |
| code | Integer | 0表示云端成功收到设备上报的属性 |
| status | String | 当code非0的时候, 提示错误信息 |
接下来修改代码,首先**根据自己的产品ID和设备ID修改上报topic**
![](./image/iot14.png)
然后修改订阅topic
![](./image/iot15.png)
打开2g模块M5313的串口接收
![](./image/iot16.png)
#### 2.1.3 编译下载
修改完成之后编译工程,下载到开发板中,重新上电开始运行,在串口助手中查看打印日志:
![](./image/iot17.png)
在云端查看上报日志:
![](./image/iot18.png)
点击【设备属性】,点击亮度属性一栏的查看,可以查看曲线显示:
![](./image/iot19.png)
## 3. 腾讯连连小程序操作步骤
### 3.1 添加家庭
手机端在【微信】搜索【腾讯连连】小程序,首次使用需要进入后点击【我的】->【家庭管理】,添加一个你喜欢的名称即可。
### 3.2 添加设备
进入后在中下方点击➕号,开始扫描二维码
![](./image/iot20.png)
![](./image/iot21.png)
在腾讯云物联网开发平台进入【设备调试】,点击对应设备后的【二维码】:
![](./image/iot22.png)
腾讯连连扫描此二维码即可成功添加设备,添加成功之后如图:
![](./image/iot23.png)
给设备上电,等一会可以看到设备上线,点击进入可以看到代码上传的亮度数据
![](./image/iotpl.png)

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@@ -1,159 +0,0 @@
# 对接腾讯云与腾讯连连-电动车追踪
本示例示范如何对接到腾讯云物联网开发平台IoT Explore和腾讯连连小程序
并上传GPS定位和通过腾讯云与腾讯连连控制开发板上的LED。
## 1. 云端操作步骤
登录[腾讯云物联网开发平台IoT Explorer](https://cloud.tencent.com/product/iotexplorer "腾讯云物联网开发平台IoT Explorer"),点击“立即使用”进入控制台,个人开发可以使用微信进行登录。
### 1.1 新建项目
具体可参考《3.对接腾讯云与腾讯连连-测试》新建项目章节,根据文档已经创建了一个智能终端的项目
![](./image/elec01.png)
### 1.2 产品开发
#### 1.2.1 新建产品
点击项目名称进入到该项目中,点击新建产品:
![](./image/elec02.png)
![](./image/elec03.png)
产品新建成功后,可在产品列表页查看到“电动车追踪”。
![](./image/elec04.png)
#### 1.2.2 新建功能
点击电动车追踪产品进入。
##### 1.2.2.1
参照下图建立两个功能:灯和位置两个功能
![](./image/elec05.png)
##### 1.2.2.2
json格式为
![](./image/elec06.png)
```c
{
"version": "1.0",
"profile": {
"ProductId": "OKY0D78DP2",
"CategoryId": "1"
},
"properties": [
{
"id": "led",
"name": "灯",
"desc": "",
"mode": "rw",
"define": {
"type": "bool",
"mapping": {
"0": "关",
"1": "开"
}
},
"required": false
},
{
"id": "location",
"name": "位置",
"desc": "",
"mode": "r",
"define": {
"type": "string",
"min": "0",
"max": "1024"
},
"required": false
}
],
"events": [],
"actions": []
}
```
### 1.3 创建测试设备
在【设备调试】页面中,单击【新建设备】,设备名为 bd_location
![](./image/elec07.png)
## 2. 设备侧操作
使用 Keil-MDK 打开 mqttclient_iot_explorer_location 工程:
TencentOS-tiny\board\BDW01-STM32L496VG\KEIL\mqttclient_iot_explorer_location
![](./image/elec08.png)
### 2.1 配置使用的网络设备
打开mqttclient_iot_explorer_location.c文件修改配置。
路径为TencentOS-tiny\board\BDW01-STM32L496VG\BSP\app
修改本工程所使用的通信模组打开USE_M5313如图
![](./image/elec09.png)
#### 2.1.1 修改MQTT对接参数
在腾讯云物联网开发平台可以看到一些产品ID、设备ID、设备秘钥三个参数如图
![](./image/elec10.png)
接下来进入TencentOS-tiny仓库中的tools目录使用python运行脚本mqtt_config_gen.py按照提示输出刚刚在平台查询到的三个参数脚本会自动生成mqtt配置参数
![](./image/elec11.png)
① 输入产品ID
② 输入设备名称
③ 输入设备秘钥;
④ ⑤ 保持默认,直接回车;
⑥ 需要的生成信息。
接下来在代码中修改配置信息:
![](./image/elec12.png)
#### 2.1.2 修改mqtt对接topic
设备向云端上报数据的topic如下
上行请求 Topic $thing/up/property/{ProductID}/{DeviceName}
上行响应 Topic $thing/down/property/{ProductID}/{DeviceName}
首先订阅上行响应topic数据内容如下
```c
{
"method":"control",
"clientToken":"clientToken-9d2601f3-c36f-46a5-bdf6-1bd21c547406",
"params":
{
"led":1,
}
}
```
同时因为订阅了上行响应topic所以模组会收到云端下发的响应并通过URC模式上报云端响应报文整理一下格式如下
```c
{
"method":"report_reply",
"clientToken":"clientToken-9d2601f3-c36f-46a5-bdf6-1bd21c547406",
"code":0,
"status":"success"}
```
修改代码,首先**根据自己的产品ID和设备ID修改上报topic**
![](./image/elec13.png)
然后修改订阅topic
![](./image/elec14.png)
打开2g模块M5313的串口接收
![](./image/elec15.png)
#### 2.1.3 编译下载
修改完成之后编译工程,下载到开发板中,重新上电开始运行,在串口助手中查看打印日志:
![](./image/elec16.png)
#### 2.1.4 上报定位
GPS获取到定位时串口会打印GPS定位信息
![](./image/elec17.png)
同时将定位上传到云端,
在云端查看上报日志:
![](./image/elec18.png)
#### 2.1.5 LED控制
在设备调试里打开在线调试选择灯期望值选择打开状态然后点击发送成功控制板子上的LED并返回数据
![](./image/elec19.png)
## 3. 腾讯连连小程序操作步骤
### 3.1 添加家庭
手机端在【微信】搜索【腾讯连连】小程序,首次使用需要进入后点击【我的】->【家庭管理】,添加一个你喜欢的名称即可。
### 3.2 添加设备
进入后在中下方点击➕号,开始扫描二维码
![](./image/elec20.png)
![](./image/elec21.png)
在腾讯云物联网开发平台进入【设备调试】,点击对应设备后的【二维码】:
![](./image/elec22.png)
腾讯连连扫描此二维码即可成功添加设备,添加成功之后如图:
![](./image/elec23.png)
给设备上电等一会可以看到设备上线点进去可进行LED的控制
开发板上的LED会亮。
![](./image/elec24.png)
#### 3.2.1 面板配置
可以采用H5对小程序的显示页面进行编辑
![](./image/elec25.png)
![](./image/elec26.png)
上传文件index.js、index.css(在source文件夹里)
![](./image/elec27.png)
并将腾讯连连小程序里的帐号添加至白名单。
![](./image/elec28.png)
用小程序重新扫描设备二维码,给设备重新上电,当有定位时,效果如下:
![](./image/elec29.png)

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