492 lines
19 KiB
C
492 lines
19 KiB
C
/*!
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\file gd32f20x_sdram_eval.c
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\brief exmc sdram(MICRON 48LC16M16A2) driver
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\version 2015-07-15, V1.0.0, firmware for GD32F20x
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\version 2017-06-05, V2.0.0, firmware for GD32F20x
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\version 2018-10-31, V2.1.0, firmware for GD32F20x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "stdio.h"
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#include "gd32f20x_sdram_eval.h"
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/* Define mode register content */
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/* Burst Length */
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0003)
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/* Burst Type */
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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/* CAS Latency */
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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/* Write Mode */
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_TIMEOUT ((uint32_t)0x0000FFFF)
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#define SDRAM_DEVICE0_ADDR ((uint32_t)0xC0000000U)
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#define SDRAM_DEVICE1_ADDR ((uint32_t)0xD0000000U)
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//#define USE_SYSTICK_DELAY /* select coarse(software delay) or fine(systick delay) delay when sdram initialization */
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#ifdef USE_SYSTICK_DELAY
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#include "systick.h"
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#define DELAY_MS(x) delay_1ms(x)
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#else
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#define DELAY_MS(x) delay_1ms_coarse(x)
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extern uint32_t SystemCoreClock;
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static void delay_1ms_coarse(uint32_t count);
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/*!
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\brief delay a time in milliseconds
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\param[in] count: count in milliseconds
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\param[out] none
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\retval none
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*/
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static void delay_1ms_coarse(uint32_t count)
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{
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uint32_t delay;
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delay = (count * (SystemCoreClock / 1000U)) / 3U;
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while(delay != 0U){
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delay--;
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}
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}
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#endif /* USE_SYSTICK_DELAY */
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/*!
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\brief sdram peripheral initialize
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\param[in] sdram_device: specifie the SDRAM device
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\param[out] none
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\retval none
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*/
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void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
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{
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exmc_sdram_parameter_struct sdram_init_struct;
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exmc_sdram_timing_parameter_struct sdram_timing_init_struct;
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exmc_sdram_command_parameter_struct sdram_command_init_struct;
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uint32_t command_content = 0U, bank_select;
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uint32_t timeout = SDRAM_TIMEOUT;
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#ifdef USE_SYSTICK_DELAY
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/* systick clock configure */
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systick_config();
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#endif /* USE_SYSTICK_DELAY */
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/* enable EXMC clock*/
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rcu_periph_clock_enable(RCU_EXMC);
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rcu_periph_clock_enable(RCU_GPIOB);
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rcu_periph_clock_enable(RCU_GPIOC);
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rcu_periph_clock_enable(RCU_GPIOD);
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rcu_periph_clock_enable(RCU_GPIOE);
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rcu_periph_clock_enable(RCU_GPIOF);
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rcu_periph_clock_enable(RCU_GPIOG);
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rcu_periph_clock_enable(RCU_GPIOH);
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rcu_periph_clock_enable(RCU_AF);
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/* Common GPIO configuration */
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/* EXMC gpio pin PC0: EXMC_NWE remap */
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gpio_pin_remap1_config(GPIO_PCF5, GPIO_PCF5_EXMC_SDNWE_PC0_REMAP, ENABLE);
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gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0);
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/* D0(PD14),D1(PD15),D2(PD0),D3(PD1),D13(PD8),D14(PD9),D15(PD10) pin configuration */
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gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
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GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
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/* GPIOE configuration */
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/* NBL0(PE0),NBL1(PE1),D4(PE7),D5(PE8),D6(PE9),D7(PE10),D8(PE11),D9(PE12),D10(PE13),D11(PE14),D12(PE15) pin configuration */
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gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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/* GPIOF configuration */
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/* A0(PF0),A1(PF1),A2(PF2),A3(PF3),A4(PF4),A5(PF5),A6(PF12),A7(PF13),A8(PF14),A9(PF15),SDNRAS(PF11) pin configuration */
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gpio_init(GPIOF, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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/* GPIOG configuration */
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/* A10(PG0),A11(PG1),A12(PG2),BA0(PG4),BA1(PG5),SDCLK(PG8),SDNCAS(PG15) pin configuration */
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gpio_init(GPIOG, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
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/* GPIOH configuration */
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/* SDCKE0(PH2), SDNE0(PH3) pin configuration */
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gpio_init(GPIOH, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2 | GPIO_PIN_3);
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/* specify which SDRAM to read and write */
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if(EXMC_SDRAM_DEVICE0 == sdram_device){
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bank_select = EXMC_SDRAM_DEVICE0_SELECT;
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}else{
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bank_select = EXMC_SDRAM_DEVICE1_SELECT;
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}
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/* EXMC SDRAM device initialization sequence --------------------------------*/
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/* Step 1 : configure SDRAM timing registers --------------------------------*/
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/* LMRD: 2 clock cycles */
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sdram_timing_init_struct.load_mode_register_delay = 2U;
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/* XSRD: min = 67ns */
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sdram_timing_init_struct.exit_selfrefresh_delay = 7U;
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/* RASD: min=42ns , max=120k (ns) */
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sdram_timing_init_struct.row_address_select_delay = 5U;
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/* ARFD: min=60ns */
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sdram_timing_init_struct.auto_refresh_delay = 6U;
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/* WRD: min=1 Clock cycles +6ns */
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sdram_timing_init_struct.write_recovery_delay = 2U;
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/* RPD: min=18ns */
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sdram_timing_init_struct.row_precharge_delay = 2U;
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/* RCD: min=18ns */
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sdram_timing_init_struct.row_to_column_delay = 2U;
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/* step 2 : configure SDRAM control registers ---------------------------------*/
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sdram_init_struct.sdram_device = sdram_device;
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sdram_init_struct.column_address_width = EXMC_SDRAM_COW_ADDRESS_9;
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sdram_init_struct.row_address_width = EXMC_SDRAM_ROW_ADDRESS_13;
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sdram_init_struct.data_width = EXMC_SDRAM_DATABUS_WIDTH_16B;
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sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK;
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sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK;
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sdram_init_struct.write_protection = DISABLE;
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sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK;
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sdram_init_struct.brust_read_switch = ENABLE;
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sdram_init_struct.pipeline_read_delay = EXMC_PIPELINE_DELAY_1_HCLK;
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sdram_init_struct.timing = &sdram_timing_init_struct;
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/* EXMC SDRAM bank initialization */
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exmc_sdram_init(&sdram_init_struct);
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/* step 3 : configure CKE high command---------------------------------------*/
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sdram_command_init_struct.command = EXMC_SDRAM_CLOCK_ENABLE;
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sdram_command_init_struct.bank_select = bank_select;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
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sdram_command_init_struct.mode_register_content = 0U;
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/* wait until the SDRAM controller is ready */
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0U)){
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timeout--;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 4 : insert 10ms delay----------------------------------------------*/
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DELAY_MS(10U);
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/* step 5 : configure precharge all command----------------------------------*/
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sdram_command_init_struct.command = EXMC_SDRAM_PRECHARGE_ALL;
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sdram_command_init_struct.bank_select = bank_select;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
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sdram_command_init_struct.mode_register_content = 0U;
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0U)){
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timeout--;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 6 : configure Auto-Refresh command-----------------------------------*/
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sdram_command_init_struct.command = EXMC_SDRAM_AUTO_REFRESH;
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sdram_command_init_struct.bank_select = bank_select;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_8_SDCLK;
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sdram_command_init_struct.mode_register_content = 0U;
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0U)){
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timeout--;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 7 : configure load mode register command-----------------------------*/
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/* program mode register */
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command_content = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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sdram_command_init_struct.command = EXMC_SDRAM_LOAD_MODE_REGISTER;
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sdram_command_init_struct.bank_select = bank_select;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
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sdram_command_init_struct.mode_register_content = command_content;
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0U)){
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timeout--;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 8 : set the auto-refresh rate counter--------------------------------*/
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/* 64ms, 8192-cycle refresh, 64ms/8192=7.81us */
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/* SDCLK_Freq = SYS_Freq/2 */
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/* (7.81 us * SDCLK_Freq) - 20 */
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exmc_sdram_refresh_count_set(448U);
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0U)){
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timeout--;
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}
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}
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/*!
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\brief fill the buffer with specified value
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\param[in] pbuffer: pointer on the buffer to fill
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\param[in] buffersize: size of the buffer to fill
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\param[in] value: value to fill on the buffer
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\param[out] none
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\retval none
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*/
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void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t offset)
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{
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uint16_t index = 0U;
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uint32_t pbuffer_addr;
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pbuffer_addr = (uint32_t)pbuffer;
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/* put in global buffer same values */
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for (index = 0U; index < buffer_lengh; index++ ){
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*(uint8_t *)pbuffer_addr = (uint8_t)(index + offset);
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pbuffer_addr++;
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}
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}
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/*!
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\brief write a byte buffer(data is 8 bits) to the EXMC SDRAM memory
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\param[in] sdram_device: specify which a SDRAM memory block is written
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\param[in] pbuffer: pointer to buffer
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\param[in] writeaddr: SDRAM memory internal address from which the data will be written
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\param[in] numbyte_write: number of bytes to write
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\param[out] none
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\retval none
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*/
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void sdram_writebuffer_8(uint32_t sdram_device, uint8_t* pbuffer, uint32_t writeaddr, uint32_t numbyte_write)
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{
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uint32_t temp_addr;
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uint32_t pbuffer_addr;
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/* Select the base address according to EXMC_Bank */
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if(sdram_device == EXMC_SDRAM_DEVICE0){
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temp_addr = SDRAM_DEVICE0_ADDR;
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}else{
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temp_addr = SDRAM_DEVICE1_ADDR;
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}
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pbuffer_addr = (uint32_t)pbuffer;
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/* While there is data to write */
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for(; numbyte_write != 0U; numbyte_write--) {
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/* Transfer data to the memory */
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temp_addr = temp_addr + writeaddr;
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*(uint8_t *)(temp_addr) = *(uint8_t *)pbuffer_addr;
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/* Increment the address*/
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writeaddr += 1U;
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pbuffer_addr += 1U;
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}
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}
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/*!
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\brief read a block of 8-bit data from the EXMC SDRAM memory
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\param[in] sdram_device: specify which a SDRAM memory block is written
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\param[in] pbuffer: pointer to buffer
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\param[in] readaddr: SDRAM memory internal address to read from
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\param[in] numbyte_read: number of bytes to read
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\param[out] none
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\retval none
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*/
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void sdram_readbuffer_8(uint32_t sdram_device, uint8_t* pbuffer, uint32_t readaddr, uint32_t numbyte_read)
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{
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uint32_t temp_addr;
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uint32_t pbuffer_addr;
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/* select the base address according to EXMC_Bank */
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if(sdram_device == EXMC_SDRAM_DEVICE0){
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temp_addr = SDRAM_DEVICE0_ADDR;
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}else{
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temp_addr = SDRAM_DEVICE1_ADDR;
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}
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pbuffer_addr = (uint32_t)pbuffer;
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/* while there is data to read */
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for(; numbyte_read != 0U; numbyte_read--){
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/* read a byte from the memory */
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temp_addr = temp_addr + readaddr;
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*(uint8_t*)pbuffer_addr = *(uint8_t*)(temp_addr);
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/* increment the address */
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readaddr += 1U;
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pbuffer_addr += 1U;
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}
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}
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/*!
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\brief write a Half-word buffer(data is 16 bits) to the EXMC SDRAM memory
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\param[in] sdram_device: specify which a SDRAM memory block is written
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\param[in] pbuffer: pointer to buffer
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\param[in] writeaddr: SDRAM memory internal address from which the data will be written
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\param[in] numhalfbyte_write: number of half-words to write
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\param[out] none
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\retval none
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*/
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void sdram_writebuffer_16(uint32_t sdram_device, uint16_t* pbuffer, uint32_t writeaddr, uint32_t numhalfbyte_write)
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{
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uint32_t temp_addr;
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uint32_t pbuffer_addr;
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/* Select the base address according to EXMC_Bank */
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if(sdram_device == EXMC_SDRAM_DEVICE0){
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temp_addr = SDRAM_DEVICE0_ADDR;
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}else{
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temp_addr = SDRAM_DEVICE1_ADDR;
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}
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pbuffer_addr = (uint32_t)pbuffer;
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/* While there is data to write */
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for(; numhalfbyte_write != 0U; numhalfbyte_write--) {
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/* Transfer data to the memory */
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temp_addr = temp_addr + writeaddr;
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*(uint16_t *)(temp_addr) = *(uint16_t *)pbuffer_addr;
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/* Increment the address*/
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writeaddr += 2U;
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pbuffer_addr += 2U;
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}
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}
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/*!
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\brief read a block of 16-bit data from the EXMC SDRAM memory
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\param[in] sdram_device: specify which a SDRAM memory block is written
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\param[in] pbuffer: pointer to buffer
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\param[in] readaddr: SDRAM memory internal address to read from
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\param[in] numhalfbyte_read: number of half-word to read
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\param[out] none
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\retval none
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*/
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void sdram_readbuffer_16(uint32_t sdram_device, uint16_t* pbuffer, uint32_t readaddr, uint32_t numhalfbyte_read)
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{
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uint32_t temp_addr;
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uint32_t pbuffer_addr;
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/* select the base address according to EXMC_Bank */
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if(sdram_device == EXMC_SDRAM_DEVICE0){
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temp_addr = SDRAM_DEVICE0_ADDR;
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}else{
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temp_addr = SDRAM_DEVICE1_ADDR;
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}
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|
|
pbuffer_addr = (uint32_t)pbuffer;
|
|
/* while there is data to read */
|
|
for(; numhalfbyte_read != 0U; numhalfbyte_read--){
|
|
/* read a half-word from the memory */
|
|
temp_addr = temp_addr + readaddr;
|
|
*(uint16_t*)pbuffer_addr = *(uint16_t*)(temp_addr);
|
|
|
|
/* increment the address */
|
|
readaddr += 2U;
|
|
pbuffer_addr += 2U;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief write a word buffer(data is 32 bits) to the EXMC SDRAM memory
|
|
\param[in] sdram_device: specify which a SDRAM memory block is written
|
|
\param[in] pbuffer: pointer to buffer
|
|
\param[in] writeaddr: SDRAM memory internal address from which the data will be written
|
|
\param[in] numword_write: number of words to write
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void sdram_writebuffer_32(uint32_t sdram_device, uint32_t* pbuffer, uint32_t writeaddr, uint32_t numword_write)
|
|
{
|
|
uint32_t temp_addr;
|
|
uint32_t pbuffer_addr;
|
|
|
|
/* Select the base address according to EXMC_Bank */
|
|
if(sdram_device == EXMC_SDRAM_DEVICE0){
|
|
temp_addr = SDRAM_DEVICE0_ADDR;
|
|
}else{
|
|
temp_addr = SDRAM_DEVICE1_ADDR;
|
|
}
|
|
|
|
pbuffer_addr = (uint32_t)pbuffer;
|
|
/* While there is data to write */
|
|
for(; numword_write != 0U; numword_write--) {
|
|
/* Transfer data to the memory */
|
|
temp_addr = temp_addr + writeaddr;
|
|
*(uint32_t *)(temp_addr) = *(uint32_t *)pbuffer_addr;
|
|
|
|
/* Increment the address*/
|
|
pbuffer_addr += 4U;
|
|
writeaddr += 4U;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief read a block of 32-bit data from the EXMC SDRAM memory
|
|
\param[in] sdram_device: specify which a SDRAM memory block is written
|
|
\param[in] pbuffer: pointer to buffer
|
|
\param[in] readaddr: SDRAM memory internal address to read from
|
|
\param[in] numword_read: number of word to read
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void sdram_readbuffer_32(uint32_t sdram_device, uint32_t* pbuffer, uint32_t readaddr, uint32_t numword_read)
|
|
{
|
|
uint32_t temp_addr;
|
|
uint32_t pbuffer_addr;
|
|
|
|
/* select the base address according to EXMC_Bank */
|
|
if(sdram_device == EXMC_SDRAM_DEVICE0){
|
|
temp_addr = SDRAM_DEVICE0_ADDR;
|
|
}else{
|
|
temp_addr = SDRAM_DEVICE1_ADDR;
|
|
}
|
|
|
|
pbuffer_addr = (uint32_t)pbuffer;
|
|
/* while there is data to read */
|
|
for(; numword_read != 0U; numword_read--){
|
|
/* read a word from the memory */
|
|
temp_addr = temp_addr + readaddr;
|
|
*(uint32_t*)pbuffer_addr = *(uint32_t*)(temp_addr);
|
|
|
|
/* increment the address */
|
|
readaddr += 4U;
|
|
pbuffer_addr += 4U;
|
|
}
|
|
}
|