febcf10911
1. a true wear-leveling kv fs for norflash, especially optimize for some onchip norflash with "write once on one single write unit" like stm32l4, a true "no earse before write" flash algorithm. 2. an "as less as possible" gc strategy, do best to save norflash's life. 3. full "power down protection" support 4. see "examples" of kv, project in "TencentOS_tiny_EVB_MX_Plus", with onchip flash and qspiflash sample.
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/**
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******************************************************************************
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* File Name : QUADSPI.c
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* Description : This file provides code for the configuration
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* of the QUADSPI instances.
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******************************************************************************
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** This notice applies to any and all portions of this file
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* that are not between comment pairs USER CODE BEGIN and
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* USER CODE END. Other portions of this file, whether
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* inserted by the user or by software development tools
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* are owned by their respective copyright owners.
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*
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* COPYRIGHT(c) 2019 STMicroelectronics
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "quadspi.h"
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#include "gpio.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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QSPI_HandleTypeDef hqspi;
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/* QUADSPI init function */
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void MX_QUADSPI_Init(void)
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{
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hqspi.Instance = QUADSPI;
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hqspi.Init.ClockPrescaler = 0;
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hqspi.Init.FifoThreshold = 4;
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hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
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hqspi.Init.FlashSize = 25;
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hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE;
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hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
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hqspi.Init.FlashID = QSPI_FLASH_ID_1;
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hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
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if (HAL_QSPI_Init(&hqspi) != HAL_OK)
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{
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return;
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}
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}
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void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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if(qspiHandle->Instance==QUADSPI)
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{
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/* USER CODE BEGIN QUADSPI_MspInit 0 */
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/* USER CODE END QUADSPI_MspInit 0 */
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/* QUADSPI clock enable */
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__HAL_RCC_QSPI_CLK_ENABLE();
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/**QUADSPI GPIO Configuration
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PB0 ------> QUADSPI_BK1_IO1
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PB1 ------> QUADSPI_BK1_IO0
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PB10 ------> QUADSPI_CLK
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PB11 ------> QUADSPI_BK1_NCS
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*/
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GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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/* USER CODE BEGIN QUADSPI_MspInit 1 */
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/* USER CODE END QUADSPI_MspInit 1 */
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}
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}
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void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* qspiHandle)
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{
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if(qspiHandle->Instance==QUADSPI)
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{
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/* USER CODE BEGIN QUADSPI_MspDeInit 0 */
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/* USER CODE END QUADSPI_MspDeInit 0 */
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/* Peripheral clock disable */
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__HAL_RCC_QSPI_CLK_DISABLE();
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/**QUADSPI GPIO Configuration
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PB0 ------> QUADSPI_BK1_IO1
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PB1 ------> QUADSPI_BK1_IO0
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PB10 ------> QUADSPI_CLK
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PB11 ------> QUADSPI_BK1_NCS
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*/
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11);
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/* USER CODE BEGIN QUADSPI_MspDeInit 1 */
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/* USER CODE END QUADSPI_MspDeInit 1 */
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}
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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