196 lines
8.0 KiB
ArmAsm
196 lines
8.0 KiB
ArmAsm
/*****************************************************************************
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* Copyright (c) 2001, 2002 Rowley Associates Limited. *
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* *
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* This file may be distributed under the terms of the License Agreement *
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* provided with this software. *
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* *
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* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
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* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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*****************************************************************************
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* WARNING *
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*****************************************************************************
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* There have been a lot of modifications to this file for the FreeRTOS port *
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* for the following reason: *
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* *
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* - We need support for the interrupt vectors from the EIC. *
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* - The default file did only make a copy of the standard vectors when in *
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* FLASH mode. Because in the used EIC configuration the new programm *
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* counter value is loaded with a relative offset to the current pc the *
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* interrupt vectors must also be available in the RAM. *
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* - The clock source configuration did not fit for the specific *
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* needs of the author. *
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* *
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* All modifications copyright (c) 2006, Christian Walter <wolti@sil.at> *
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*****************************************************************************/
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#include "FreeRTOSConfig.h" /* import configUSE_PREEMPTION */
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.equ EIC_BASE, 0xFFFFF800 /* EIC base address. */
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.equ EIC_IVR_OFF, 0x18 /* EIC interrupt vector register. */
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.section .vectors, "ax"
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.code 32
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.align 0
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/*****************************************************************************
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* Exception vectors *
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*****************************************************************************/
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_vectors_start:
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ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
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ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
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ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
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ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
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ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
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nop
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ldr pc, [pc, #irq_handler_address - . - 8]
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ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */
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reset_handler_address: .word _reset_handler
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undef_handler_address: .word _undef_handler
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swi_handler_address: .word vPortYieldProcessor
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pabort_handler_address: .word _pabort_handler
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dabort_handler_address: .word _dabort_handler
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irq_handler_address: .word _irq_handler
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fiq_handler_address: .word _fiq_handler
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/*******************************************************************************
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* EIC interrupt vectors
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******************************************************************************/
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.global T0TIMI_address
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.global T0TIMI_Addr
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T0TIMI_Addr: /* for compatibility with STR71X library. */
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T0TIMI_address: .word _undef_IRQhandler
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FLASH_address: .word _undef_IRQhandler
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RCCU_address: .word _undef_IRQhandler
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RTC_Addr: .word _undef_IRQhandler
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#if configUSE_PREEMPTION == 0
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WDG_Addr: .word vPortNonPreemptiveTick
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#else
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WDG_Addr: .word vPortPreemptiveTick
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#endif
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XTI_Addr: .word _undef_IRQhandler
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USBHP_Addr: .word _undef_IRQhandler
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I2C0ITERR_Addr: .word _undef_IRQhandler
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I2C1ITERR_ADDR: .word _undef_IRQhandler
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UART0_ADDR: .word sio_uart0_irq
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UART1_ADDR: .word sio_uart1_irq
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UART2_ADDR: .word _undef_IRQhandler
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UART3_ADDR: .word _undef_IRQhandler
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BSPI0_ADDR: .word _undef_IRQhandler
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BSPI1_Addr: .word _undef_IRQhandler
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I2C0_Addr: .word _undef_IRQhandler
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I2C1_Addr: .word _undef_IRQhandler
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CAN_Addr: .word _undef_IRQhandler
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ADC12_Addr: .word _undef_IRQhandler
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T1TIMI_Addr: .word _undef_IRQhandler
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T2TIMI_Addr: .word _undef_IRQhandler
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T3TIMI_Addr: .word _undef_IRQhandler
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.word 0 /* reserved */
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.word 0 /* reserved */
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.word 0 /* reserved */
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HDLC_Addr: .word _undef_IRQhandler
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USBLP_Addr: .word _undef_IRQhandler
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.word 0 /* reserved */
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.word 0 /* reserved */
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T0TOI_Addr: .word _undef_IRQhandler
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T0OC1_Addr: .word _undef_IRQhandler
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T0OC2_Addr: .word _undef_IRQhandler
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_vectors_end:
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/*******************************************************************************
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* If flash execution is used and the RAM is mapped at address 0 we also need
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* to place a copy of the interrupt vector address table in the RAM.
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******************************************************************************/
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#ifdef __FLASH_BUILD
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.section .vectors_ram, "ax"
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.code 32
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.align 0
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_vectors_ram:
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.fill _vectors_end - _vectors_start
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#endif
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/******************************************************************************
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* Default exception handlers *
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******************************************************************************/
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.section .init, "ax"
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.code 32
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.align 0
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_reset_handler:
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#ifdef __FLASH_BUILD
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ldr r0, =_vectors_start
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ldr r1, =_vectors_end
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sub r1, r1, r0 /* r2 = number of bytes to copy */
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ldr r2, =0x20000000 /* r0 = start address to place copy */
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_vector_copy:
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ldr r3, [r0], #4 /* read a word from the source */
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str r3, [r2], #4 /* copy the word to destination */
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subs r1, r1, #4 /* decrement number of words to copy */
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bne _vector_copy
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#endif
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/* Configure system and jump to the _start entry point. */
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ldr r0, =0x6C000000
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ldr r1, =0x801D
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str r1, [r0, #4] /* set up the emi to 1 wait state */
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ldr r0, =0xA0000000
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ldr r1, =0x1c2
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str r1, [r0, #0x50] /* set up the internal RAM at 0x0 */
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/* After setup the folling clock configuration will be active. Note
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* that the value of CK is dependent on the target oscillator.
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*
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* CK = 4Mhz
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* CLK2 = 2Mhz (with DIV2 = 1)
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* RCLK = 16 * CLK2 / 1 = 32Mhz
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* MCLK = RCLK
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* PCLK1 = RCLK/2
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* PCLK2 = RCLK/2
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*/
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/* set RCLK to 16 * CLK2 / 1 = 32Mhz
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* (0x0071 = FREEN=1, FREF_RANGE=1, MX1:0=11b, DX2:0=000b) */
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ldr r1, =0x00F0
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str r1, [r0, #0x18]
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/* (0x8009 = DIV2=1, CK2_16=1, CKU_CKSEL=1) */
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ldr r1, =0x8009
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str r1, [r0, #0x8]
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/* cpu and memory clock div = 1 */
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ldr r1, =0x0
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str r1, [r0, #0x40]
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/* pclk1 = rclk/1 and pclk2 = rclk/1 = 32Mhz
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* (0x0101 = FACT2_9:8=01b, FACT1_1:0=01b) */
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ldr r1, =0x0000
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str r1, [r0, #0x44]
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/* Jump to the default C runtime startup code. */
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B _start
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_undef_handler:
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b _undef_handler
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_swi_handler:
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b vPortYieldProcessor
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_pabort_handler:
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b _pabort_handler
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_dabort_handler:
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b _dabort_handler
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_irq_handler:
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ldr pc, =(EIC_BASE + EIC_IVR_OFF)
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_fiq_handler:
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b _fiq_handler
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/******************************************************************************
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* Default IRQ handlers *
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******************************************************************************/
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_undef_IRQhandler:
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b _undef_IRQhandler
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