168 lines
4.2 KiB
ArmAsm
168 lines
4.2 KiB
ArmAsm
#include "port.h"
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.global irq_entry
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.global trap_entry
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.extern k_curr_task
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.extern k_next_task
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.extern k_task_irq_switch_flag
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.align 2
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irq_entry:
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addi sp, sp, -32*REGBYTES
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sw x1, 2*REGBYTES(sp)
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sw x3, 3*REGBYTES(sp)
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sw x4, 4*REGBYTES(sp)
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sw x5, 5*REGBYTES(sp)
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sw x6, 6*REGBYTES(sp)
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sw x7, 7*REGBYTES(sp)
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sw x8, 8*REGBYTES(sp)
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sw x9, 9*REGBYTES(sp)
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sw x10, 10*REGBYTES(sp)
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sw x11, 11*REGBYTES(sp)
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sw x12, 12*REGBYTES(sp)
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sw x13, 13*REGBYTES(sp)
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sw x14, 14*REGBYTES(sp)
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sw x15, 15*REGBYTES(sp)
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sw x16, 16*REGBYTES(sp)
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sw x17, 17*REGBYTES(sp)
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sw x18, 18*REGBYTES(sp)
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sw x19, 19*REGBYTES(sp)
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sw x20, 20*REGBYTES(sp)
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sw x21, 21*REGBYTES(sp)
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sw x22, 22*REGBYTES(sp)
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sw x23, 23*REGBYTES(sp)
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sw x24, 24*REGBYTES(sp)
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sw x25, 25*REGBYTES(sp)
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sw x26, 26*REGBYTES(sp)
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sw x27, 27*REGBYTES(sp)
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sw x28, 28*REGBYTES(sp)
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sw x29, 29*REGBYTES(sp)
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sw x30, 30*REGBYTES(sp)
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sw x31, 31*REGBYTES(sp)
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csrr t0, mepc
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sw t0, 0*REGBYTES(sp)
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csrr t0, mstatus
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sw t0, 1*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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lw t1, (t0)
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sw sp, (t1)
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csrr a0, mcause
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mv a1, sp
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slli a0, a0, 16
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srli a0, a0, 16
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call cpu_irq_entry
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la t0, k_task_irq_switch_flag
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lw t1, (t0)
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beqz t1, irq_restore
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sw zero,(t0)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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lw t1, (t0)
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sw sp, (t1)
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// switch task
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// k_curr_task = k_next_task
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la t1, k_next_task // t1 = &k_next_task
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lw t1, (t1) // t1 = k_next_task
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sw t1, (t0)
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// load new task sp
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lw sp, (t1)
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irq_restore:
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// restore context
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lw t0, 0*REGBYTES(sp)
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csrw mepc, t0
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lw t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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lw x1, 2*REGBYTES(sp)
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lw x3, 3*REGBYTES(sp)
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lw x4, 4*REGBYTES(sp)
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lw x5, 5*REGBYTES(sp)
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lw x6, 6*REGBYTES(sp)
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lw x7, 7*REGBYTES(sp)
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lw x8, 8*REGBYTES(sp)
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lw x9, 9*REGBYTES(sp)
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lw x10, 10*REGBYTES(sp)
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lw x11, 11*REGBYTES(sp)
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lw x12, 12*REGBYTES(sp)
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lw x13, 13*REGBYTES(sp)
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lw x14, 14*REGBYTES(sp)
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lw x15, 15*REGBYTES(sp)
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lw x16, 16*REGBYTES(sp)
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lw x17, 17*REGBYTES(sp)
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lw x18, 18*REGBYTES(sp)
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lw x19, 19*REGBYTES(sp)
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lw x20, 20*REGBYTES(sp)
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lw x21, 21*REGBYTES(sp)
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lw x22, 22*REGBYTES(sp)
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lw x23, 23*REGBYTES(sp)
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lw x24, 24*REGBYTES(sp)
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lw x25, 25*REGBYTES(sp)
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lw x26, 26*REGBYTES(sp)
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lw x27, 27*REGBYTES(sp)
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lw x28, 28*REGBYTES(sp)
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lw x29, 29*REGBYTES(sp)
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lw x30, 30*REGBYTES(sp)
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lw x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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.align 6
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trap_entry:
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addi sp, sp, -32*REGBYTES
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sw x1, 2*REGBYTES(sp)
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sw x3, 3*REGBYTES(sp)
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sw x4, 4*REGBYTES(sp)
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sw x5, 5*REGBYTES(sp)
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sw x6, 6*REGBYTES(sp)
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sw x7, 7*REGBYTES(sp)
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sw x8, 8*REGBYTES(sp)
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sw x9, 9*REGBYTES(sp)
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sw x10, 10*REGBYTES(sp)
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sw x11, 11*REGBYTES(sp)
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sw x12, 12*REGBYTES(sp)
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sw x13, 13*REGBYTES(sp)
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sw x14, 14*REGBYTES(sp)
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sw x15, 15*REGBYTES(sp)
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sw x16, 16*REGBYTES(sp)
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sw x17, 17*REGBYTES(sp)
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sw x18, 18*REGBYTES(sp)
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sw x19, 19*REGBYTES(sp)
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sw x20, 20*REGBYTES(sp)
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sw x21, 21*REGBYTES(sp)
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sw x22, 22*REGBYTES(sp)
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sw x23, 23*REGBYTES(sp)
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sw x24, 24*REGBYTES(sp)
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sw x25, 25*REGBYTES(sp)
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sw x26, 26*REGBYTES(sp)
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sw x27, 27*REGBYTES(sp)
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sw x28, 28*REGBYTES(sp)
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sw x29, 29*REGBYTES(sp)
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sw x30, 30*REGBYTES(sp)
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sw x31, 31*REGBYTES(sp)
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csrr t0, mepc
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sw t0, 0*REGBYTES(sp)
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csrr t0, mstatus
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sw t0, 1*REGBYTES(sp)
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call cpu_trap_entry
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1:
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j 1b
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