251 lines
7.0 KiB
C
251 lines
7.0 KiB
C
/*
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FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
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Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved
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FreeRTOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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#include "m523xbcc.h"
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void mcf523x_init( void );
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void mcf523x_wtm_init( void );
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void mcf523x_pll_init( void );
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void mcf523x_scm_init( void );
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void mcf523x_gpio_init( void );
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void mcf523x_cs_init( void );
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void mcf523x_sdram_init( void );
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void mcf523x_flexcan_init( void );
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void
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mcf523x_init( void )
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{
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extern char __DATA_ROM[];
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extern char __DATA_RAM[];
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extern char __DATA_END[];
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extern char __BSS_START[];
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extern char __BSS_END[];
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extern uint32 VECTOR_TABLE[];
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extern uint32 __VECTOR_RAM[];
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register uint32 n;
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mcf523x_flexcan_init( );
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mcf523x_wtm_init( );
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mcf523x_pll_init( );
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mcf523x_gpio_init( );
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mcf523x_scm_init( );
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mcf523x_cs_init( );
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mcf523x_sdram_init( );
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/* Turn Instruction Cache ON */
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mcf5xxx_wr_cacr( 0
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| MCF5XXX_CACR_CENB
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| MCF5XXX_CACR_CINV
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| MCF5XXX_CACR_DISD | MCF5XXX_CACR_CEIB | MCF5XXX_CACR_CLNF_00 );
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/* Copy the vector table to RAM */
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if( __VECTOR_RAM != VECTOR_TABLE )
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{
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for( n = 0; n < 256; n++ )
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__VECTOR_RAM[n] = VECTOR_TABLE[n];
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}
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mcf5xxx_wr_vbr( ( uint32 ) __VECTOR_RAM );
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}
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void
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mcf523x_wtm_init( void )
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{
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/*
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* Disable Software Watchdog Timer
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*/
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MCF_WTM_WCR = 0;
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}
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void
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mcf523x_pll_init( void )
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{
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/*
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* Multiply 25Mhz reference crystal to acheive system clock of 150Mhz
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*/
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MCF_FMPLL_SYNCR = MCF_FMPLL_SYNCR_MFD( 1 ) | MCF_FMPLL_SYNCR_RFD( 0 );
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while( !( MCF_FMPLL_SYNSR & MCF_FMPLL_SYNSR_LOCK ) )
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{
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};
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}
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void
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mcf523x_scm_init( void )
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{
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/*
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* Enable on-chip modules to access internal SRAM
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*/
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MCF_SCM_RAMBAR = ( 0 | MCF_SCM_RAMBAR_BA( SRAM_ADDRESS >> 16 ) | MCF_SCM_RAMBAR_BDE );
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}
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void
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mcf523x_gpio_init( void )
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{
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/*
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* When booting from external Flash, the port-size is less than
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* the port-size of SDRAM. In this case it is necessary to enable
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* Data[15:0] on Port Address/Data.
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*/
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MCF_GPIO_PAR_AD = ( 0
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| MCF_GPIO_PAR_AD_PAR_ADDR23
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| MCF_GPIO_PAR_AD_PAR_ADDR22
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| MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL );
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/*
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* Initialize PAR to enable SDRAM signals
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*/
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MCF_GPIO_PAR_SDRAM = 0x3F;
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/*
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* Initialize PAR to enable Ethernet signals
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*/
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MCF_GPIO_PAR_FECI2C = 0xF0;
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}
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void
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mcf523x_sdram_init( void )
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{
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int i;
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
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{
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/* Initialize DRAM Control Register: DCR */
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MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
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MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
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/* Initialize DACR0 */
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MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDRESS >> 18UL ) |
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MCF_SDRAMC_DACR0_CASL( 1 ) |
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MCF_SDRAMC_DACR0_CBM( 3 ) |
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MCF_SDRAMC_DACR0_PS( 0 ) );
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/*
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* Initialize DMR0
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*/
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MCF_SDRAMC_DMR0 = ( 0 | MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
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/*
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* Set IP (bit 3) in DACR
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*/
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MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
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/*
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* Wait 30ns to allow banks to precharge
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*/
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for( i = 0; i < 5; i++ )
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{
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#ifndef __MWERKS__
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asm( " nop" );
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#else
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asm( nop );
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#endif
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}
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/*
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* Write to this block to initiate precharge
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*/
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*( uint32 * ) ( SDRAM_ADDRESS ) = 0xA5A59696;
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/*
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* Set RE (bit 15) in DACR
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*/
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MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
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/*
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* Wait for at least 8 auto refresh cycles to occur
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*/
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for( i = 0; i < 2000; i++ )
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{
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#ifndef __MWERKS__
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asm( " nop" );
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#else
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asm( nop );
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#endif
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}
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/*
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* Finish the configuration by issuing the IMRS.
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*/
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MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
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/*
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* Write to the SDRAM Mode Register
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*/
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*( uint32 * ) ( SDRAM_ADDRESS + 0x400 ) = 0xA5A59696;
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}
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}
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void
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mcf523x_cs_init( void )
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{
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/*
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* ChipSelect 0 - External Flash
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*/
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MCF_CS_CSAR0 = MCF_CS_CSAR_BA( EXT_FLASH_ADDRESS );
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MCF_CS_CSCR0 = ( 0 | MCF_CS_CSCR_IWS( 6 ) | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
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MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
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}
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void
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mcf523x_flexcan_init( void )
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{
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/* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
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MCF_CAN_IMASK0 = 0;
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MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
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MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
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MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
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MCF_CAN_CANCTRL0 = 0;
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MCF_CAN_CANMCR0 =
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MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
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MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
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/* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
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MCF_CAN_IMASK1 = 0;
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MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
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MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
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MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
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MCF_CAN_CANCTRL1 = 0;
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MCF_CAN_CANMCR1 =
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MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
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MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
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}
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