813 lines
31 KiB
C
813 lines
31 KiB
C
/*
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* -------------------------------------------
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* MSP432 DriverLib - v3_40_00_10
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* -------------------------------------------
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*
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* --COPYRIGHT--,BSD,BSD
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* Copyright (c) 2016, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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#include <timer_a.h>
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#include <interrupt.h>
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#include <debug.h>
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static void privateTimer_AProcessClockSourceDivider(uint32_t timer,
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uint16_t clockSourceDivider)
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{
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TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_ID__8;
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TIMER_A_CMSIS(timer)->EX0 &= ~TIMER_A_EX0_IDEX_MASK;
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switch (clockSourceDivider)
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{
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case TIMER_A_CLOCKSOURCE_DIVIDER_1:
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case TIMER_A_CLOCKSOURCE_DIVIDER_2:
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TIMER_A_CMSIS(timer)->CTL |= ((clockSourceDivider - 1) << 6);
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TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
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break;
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case TIMER_A_CLOCKSOURCE_DIVIDER_4:
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TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
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TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
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break;
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case TIMER_A_CLOCKSOURCE_DIVIDER_8:
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TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
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TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
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break;
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case TIMER_A_CLOCKSOURCE_DIVIDER_3:
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case TIMER_A_CLOCKSOURCE_DIVIDER_5:
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case TIMER_A_CLOCKSOURCE_DIVIDER_6:
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case TIMER_A_CLOCKSOURCE_DIVIDER_7:
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TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__1;
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TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider - 1);
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break;
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case TIMER_A_CLOCKSOURCE_DIVIDER_10:
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case TIMER_A_CLOCKSOURCE_DIVIDER_12:
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case TIMER_A_CLOCKSOURCE_DIVIDER_14:
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case TIMER_A_CLOCKSOURCE_DIVIDER_16:
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TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__2;
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TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 2 - 1);
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break;
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case TIMER_A_CLOCKSOURCE_DIVIDER_20:
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case TIMER_A_CLOCKSOURCE_DIVIDER_24:
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case TIMER_A_CLOCKSOURCE_DIVIDER_28:
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case TIMER_A_CLOCKSOURCE_DIVIDER_32:
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TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
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TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 4 - 1);
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break;
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case TIMER_A_CLOCKSOURCE_DIVIDER_40:
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case TIMER_A_CLOCKSOURCE_DIVIDER_48:
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case TIMER_A_CLOCKSOURCE_DIVIDER_56:
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case TIMER_A_CLOCKSOURCE_DIVIDER_64:
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TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
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TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 8 - 1);
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break;
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}
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}
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void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode)
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{
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ASSERT(
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(TIMER_A_UPDOWN_MODE == timerMode)
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|| (TIMER_A_CONTINUOUS_MODE == timerMode)
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|| (TIMER_A_UP_MODE == timerMode));
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TIMER_A_CMSIS(timer)->CTL |= timerMode;
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}
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void Timer_A_configureContinuousMode(uint32_t timer,
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const Timer_A_ContinuousModeConfig *config)
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{
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ASSERT(
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(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
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== config->clockSource));
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ASSERT(
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(TIMER_A_DO_CLEAR == config->timerClear)
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|| (TIMER_A_SKIP_CLEAR == config->timerClear));
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ASSERT(
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(TIMER_A_TAIE_INTERRUPT_ENABLE == config->timerInterruptEnable_TAIE)
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|| (TIMER_A_TAIE_INTERRUPT_DISABLE
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== config->timerInterruptEnable_TAIE));
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ASSERT(
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(TIMER_A_CLOCKSOURCE_DIVIDER_1 == config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_2
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_4
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_8
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_3
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_5
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_6
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_7
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_10
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_12
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_14
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_16
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_20
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_24
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_28
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_32
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_40
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_48
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_56
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== config->clockSourceDivider)
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|| (TIMER_A_CLOCKSOURCE_DIVIDER_64
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== config->clockSourceDivider));
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privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
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TIMER_A_CMSIS(timer)->CTL = (TIMER_A_CMSIS(timer)->CTL
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& ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
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+ TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR
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+ TIMER_A_TAIE_INTERRUPT_ENABLE))
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| (config->clockSource + config->timerClear
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+ config->timerInterruptEnable_TAIE);
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}
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void Timer_A_configureUpMode(uint32_t timer, const Timer_A_UpModeConfig *config)
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{
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ASSERT(
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(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
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== config->clockSource));
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ASSERT(
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(TIMER_A_DO_CLEAR == config->timerClear)
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|| (TIMER_A_SKIP_CLEAR == config->timerClear));
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ASSERT(
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(TIMER_A_DO_CLEAR == config->timerClear)
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|| (TIMER_A_SKIP_CLEAR == config->timerClear));
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privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
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TIMER_A_CMSIS(timer)->CTL &=
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~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
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+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
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TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + config->timerClear
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+ config->timerInterruptEnable_TAIE);
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if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
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== config->captureCompareInterruptEnable_CCR0_CCIE)
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BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
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else
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BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
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TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
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}
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void Timer_A_configureUpDownMode(uint32_t timer,
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const Timer_A_UpDownModeConfig *config)
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{
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ASSERT(
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(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
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|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
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== config->clockSource));
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ASSERT(
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(TIMER_A_DO_CLEAR == config->timerClear)
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|| (TIMER_A_SKIP_CLEAR == config->timerClear));
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ASSERT(
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(TIMER_A_DO_CLEAR == config->timerClear)
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|| (TIMER_A_SKIP_CLEAR == config->timerClear));
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privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
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TIMER_A_CMSIS(timer)->CTL &=
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~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
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+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
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TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_STOP_MODE
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+ config->timerClear + config->timerInterruptEnable_TAIE);
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if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
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== config->captureCompareInterruptEnable_CCR0_CCIE)
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BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
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else
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BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
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TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
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}
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void Timer_A_initCapture(uint32_t timer,
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const Timer_A_CaptureModeConfig *config)
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{
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ASSERT(
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(TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
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== config->captureRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
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== config->captureRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
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== config->captureRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
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== config->captureRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
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== config->captureRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
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== config->captureRegister));
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ASSERT(
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(TIMER_A_CAPTUREMODE_NO_CAPTURE == config->captureMode)
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|| (TIMER_A_CAPTUREMODE_RISING_EDGE == config->captureMode)
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|| (TIMER_A_CAPTUREMODE_FALLING_EDGE == config->captureMode)
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|| (TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
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== config->captureMode));
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ASSERT(
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(TIMER_A_CAPTURE_INPUTSELECT_CCIxA == config->captureInputSelect)
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|| (TIMER_A_CAPTURE_INPUTSELECT_CCIxB
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== config->captureInputSelect)
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|| (TIMER_A_CAPTURE_INPUTSELECT_GND
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== config->captureInputSelect)
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|| (TIMER_A_CAPTURE_INPUTSELECT_Vcc
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== config->captureInputSelect));
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ASSERT(
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(TIMER_A_CAPTURE_ASYNCHRONOUS == config->synchronizeCaptureSource)
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|| (TIMER_A_CAPTURE_SYNCHRONOUS
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== config->synchronizeCaptureSource));
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ASSERT(
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(TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
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== config->captureInterruptEnable)
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|| (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
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== config->captureInterruptEnable));
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ASSERT(
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(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE_RESET
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== config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_SET_RESET
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== config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE == config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_RESET == config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE_SET
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== config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_RESET_SET
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== config->captureOutputMode));
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if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
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{
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//CaptureCompare register 0 only supports certain modes
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ASSERT(
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(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE
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== config->captureOutputMode)
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|| (TIMER_A_OUTPUTMODE_RESET
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== config->captureOutputMode));
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}
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uint8_t idx = (config->captureRegister>>1)-1;
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TIMER_A_CMSIS(timer)->CCTL[idx] =
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(TIMER_A_CMSIS(timer)->CCTL[idx]
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& ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
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| TIMER_A_CAPTURE_INPUTSELECT_Vcc
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| TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR
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| TIMER_A_TAIE_INTERRUPT_ENABLE | TIMER_A_CCTLN_CM_3))
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| (config->captureMode | config->captureInputSelect
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| config->synchronizeCaptureSource
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| config->captureInterruptEnable
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| config->captureOutputMode | TIMER_A_CCTLN_CAP);
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}
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void Timer_A_initCompare(uint32_t timer,
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const Timer_A_CompareModeConfig *config)
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{
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ASSERT(
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(TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
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== config->compareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
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== config->compareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
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== config->compareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
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== config->compareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
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== config->compareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
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== config->compareRegister));
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ASSERT(
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(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
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== config->compareInterruptEnable)
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|| (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
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== config->compareInterruptEnable));
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ASSERT(
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(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE_RESET
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== config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_SET_RESET
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== config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE_SET
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== config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_RESET_SET
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== config->compareOutputMode));
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if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
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{
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//CaptureCompare register 0 only supports certain modes
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ASSERT(
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(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_TOGGLE
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== config->compareOutputMode)
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|| (TIMER_A_OUTPUTMODE_RESET
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== config->compareOutputMode));
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}
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uint8_t idx = (config->compareRegister>>1)-1;
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TIMER_A_CMSIS(timer)->CCTL[idx] =
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(TIMER_A_CMSIS(timer)->CCTL[idx]
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& ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
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| TIMER_A_OUTPUTMODE_RESET_SET | TIMER_A_CCTLN_CAP))
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| (config->compareInterruptEnable + config->compareOutputMode);
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TIMER_A_CMSIS(timer)->CCR[idx] = config->compareValue;
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}
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uint16_t Timer_A_getCounterValue(uint32_t timer)
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{
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uint_fast16_t voteOne, voteTwo, res;
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voteTwo = TIMER_A_CMSIS(timer)->R;
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do
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{
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voteOne = voteTwo;
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voteTwo = TIMER_A_CMSIS(timer)->R;
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if (voteTwo > voteOne)
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res = voteTwo - voteOne;
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else if (voteOne > voteTwo)
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res = voteOne - voteTwo;
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else
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res = 0;
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} while (res > TIMER_A_THRESHOLD);
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return voteTwo;
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}
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void Timer_A_clearTimer(uint32_t timer)
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{
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BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL , TIMER_A_CTL_CLR_OFS) = 1;
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}
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uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
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uint_fast16_t captureCompareRegister, uint_fast16_t synchronizedSetting)
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{
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ASSERT(
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(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
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== captureCompareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
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== captureCompareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
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== captureCompareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
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== captureCompareRegister)
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|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
|
|
== captureCompareRegister));
|
|
|
|
ASSERT(
|
|
(TIMER_A_READ_CAPTURE_COMPARE_INPUT == synchronizedSetting)
|
|
|| (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT
|
|
== synchronizedSetting));
|
|
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
if (TIMER_A_CMSIS(timer)->CCTL[idx] & synchronizedSetting)
|
|
return TIMER_A_CAPTURECOMPARE_INPUT_HIGH;
|
|
else
|
|
return TIMER_A_CAPTURECOMPARE_INPUT_LOW;
|
|
}
|
|
|
|
uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister)
|
|
{
|
|
ASSERT(
|
|
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
|
|
== captureCompareRegister));
|
|
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_OUT_OFS))
|
|
return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH;
|
|
else
|
|
return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW;
|
|
}
|
|
|
|
uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister)
|
|
{
|
|
ASSERT(
|
|
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
|
|
== captureCompareRegister));
|
|
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
return (TIMER_A_CMSIS(timer)->CCR[idx]);
|
|
}
|
|
|
|
void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister,
|
|
uint_fast8_t outputModeOutBitValue)
|
|
{
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
TIMER_A_CMSIS(timer)->CCTL[idx] =
|
|
((TIMER_A_CMSIS(timer)->CCTL[idx])
|
|
& ~(TIMER_A_OUTPUTMODE_RESET_SET))
|
|
| (outputModeOutBitValue);
|
|
}
|
|
|
|
void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config)
|
|
{
|
|
ASSERT(
|
|
(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
|
|
|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
|
|
|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
|
|
|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
|
|
== config->clockSource));
|
|
|
|
ASSERT(
|
|
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
|
|
== config->compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
|
|
== config->compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
|
|
== config->compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
|
|
== config->compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
|
|
== config->compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
|
|
== config->compareRegister));
|
|
|
|
ASSERT(
|
|
(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
|
|
|| (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
|
|
|| (TIMER_A_OUTPUTMODE_TOGGLE_RESET
|
|
== config->compareOutputMode)
|
|
|| (TIMER_A_OUTPUTMODE_SET_RESET
|
|
== config->compareOutputMode)
|
|
|| (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
|
|
|| (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
|
|
|| (TIMER_A_OUTPUTMODE_TOGGLE_SET
|
|
== config->compareOutputMode)
|
|
|| (TIMER_A_OUTPUTMODE_RESET_SET
|
|
== config->compareOutputMode));
|
|
|
|
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
|
|
|
|
TIMER_A_CMSIS(timer)->CTL &=
|
|
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
|
|
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
|
|
|
|
TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_UP_MODE
|
|
+ TIMER_A_DO_CLEAR);
|
|
|
|
TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
|
|
|
|
TIMER_A_CMSIS(timer)->CCTL[0] &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
|
|
+ TIMER_A_OUTPUTMODE_RESET_SET);
|
|
|
|
uint8_t idx = (config->compareRegister>>1) - 1;
|
|
TIMER_A_CMSIS(timer)->CCTL[idx] |= config->compareOutputMode;
|
|
TIMER_A_CMSIS(timer)->CCR[idx] = config->dutyCycle;
|
|
}
|
|
|
|
void Timer_A_stopTimer(uint32_t timer)
|
|
{
|
|
TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_MC_3;
|
|
}
|
|
|
|
void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister,
|
|
uint_fast16_t compareValue)
|
|
{
|
|
ASSERT(
|
|
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1 == compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2 == compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3 == compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4 == compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister));
|
|
|
|
uint8_t idx = (compareRegister>>1) - 1;
|
|
TIMER_A_CMSIS(timer)->CCR[idx] = compareValue;
|
|
}
|
|
|
|
void Timer_A_clearInterruptFlag(uint32_t timer)
|
|
{
|
|
BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IFG_OFS) = 0;
|
|
}
|
|
|
|
void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister)
|
|
{
|
|
ASSERT(
|
|
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
|
|
== captureCompareRegister));
|
|
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIFG_OFS) = 0;
|
|
}
|
|
|
|
void Timer_A_enableInterrupt(uint32_t timer)
|
|
{
|
|
BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 1;
|
|
}
|
|
|
|
void Timer_A_disableInterrupt(uint32_t timer)
|
|
{
|
|
BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 0;
|
|
}
|
|
|
|
uint32_t Timer_A_getInterruptStatus(uint32_t timer)
|
|
{
|
|
return (TIMER_A_CMSIS(timer)->CTL) & TIMER_A_CTL_IFG;
|
|
}
|
|
|
|
void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister)
|
|
{
|
|
ASSERT(
|
|
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
|
|
== captureCompareRegister));
|
|
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 1;
|
|
}
|
|
|
|
void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister)
|
|
{
|
|
ASSERT(
|
|
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
|
|
== captureCompareRegister)
|
|
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
|
|
== captureCompareRegister));
|
|
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 0;
|
|
|
|
}
|
|
|
|
uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister, uint_fast16_t mask)
|
|
{
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
return (TIMER_A_CMSIS(timer)->CCTL[idx]) & mask;
|
|
}
|
|
|
|
uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer)
|
|
{
|
|
if (TIMER_A_CMSIS(timer)->CTL & TIMER_A_CTL_IE)
|
|
{
|
|
return Timer_A_getInterruptStatus(timer);
|
|
} else
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
}
|
|
|
|
uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
|
|
uint_fast16_t captureCompareRegister)
|
|
{
|
|
uint8_t idx = (captureCompareRegister>>1) - 1;
|
|
if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS))
|
|
return Timer_A_getCaptureCompareInterruptStatus(timer,
|
|
captureCompareRegister,
|
|
TIMER_A_CAPTURE_OVERFLOW |
|
|
TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
void Timer_A_registerInterrupt(uint32_t timer, uint_fast8_t interruptSelect,
|
|
void (*intHandler)(void))
|
|
{
|
|
if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
|
|
{
|
|
switch (timer)
|
|
{
|
|
case TIMER_A0_BASE:
|
|
Interrupt_registerInterrupt(INT_TA0_0, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA0_0);
|
|
break;
|
|
case TIMER_A1_BASE:
|
|
Interrupt_registerInterrupt(INT_TA1_0, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA1_0);
|
|
break;
|
|
case TIMER_A2_BASE:
|
|
Interrupt_registerInterrupt(INT_TA2_0, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA2_0);
|
|
break;
|
|
case TIMER_A3_BASE:
|
|
Interrupt_registerInterrupt(INT_TA3_0, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA3_0);
|
|
break;
|
|
default:
|
|
ASSERT(false);
|
|
}
|
|
} else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
|
|
{
|
|
switch (timer)
|
|
{
|
|
case TIMER_A0_BASE:
|
|
Interrupt_registerInterrupt(INT_TA0_N, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA0_N);
|
|
break;
|
|
case TIMER_A1_BASE:
|
|
Interrupt_registerInterrupt(INT_TA1_N, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA1_N);
|
|
break;
|
|
case TIMER_A2_BASE:
|
|
Interrupt_registerInterrupt(INT_TA2_N, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA2_N);
|
|
break;
|
|
case TIMER_A3_BASE:
|
|
Interrupt_registerInterrupt(INT_TA3_N, intHandler);
|
|
Interrupt_enableInterrupt(INT_TA3_N);
|
|
break;
|
|
default:
|
|
ASSERT(false);
|
|
}
|
|
} else
|
|
{
|
|
ASSERT(false);
|
|
}
|
|
}
|
|
|
|
void Timer_A_unregisterInterrupt(uint32_t timer, uint_fast8_t interruptSelect)
|
|
{
|
|
if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
|
|
{
|
|
switch (timer)
|
|
{
|
|
case TIMER_A0_BASE:
|
|
Interrupt_disableInterrupt(INT_TA0_0);
|
|
Interrupt_unregisterInterrupt(INT_TA0_0);
|
|
break;
|
|
case TIMER_A1_BASE:
|
|
Interrupt_disableInterrupt(INT_TA1_0);
|
|
Interrupt_unregisterInterrupt(INT_TA1_0);
|
|
break;
|
|
case TIMER_A2_BASE:
|
|
Interrupt_disableInterrupt(INT_TA2_0);
|
|
Interrupt_unregisterInterrupt(INT_TA2_0);
|
|
break;
|
|
case TIMER_A3_BASE:
|
|
Interrupt_disableInterrupt(INT_TA3_0);
|
|
Interrupt_unregisterInterrupt(INT_TA3_0);
|
|
break;
|
|
default:
|
|
ASSERT(false);
|
|
}
|
|
} else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
|
|
{
|
|
switch (timer)
|
|
{
|
|
case TIMER_A0_BASE:
|
|
Interrupt_disableInterrupt(INT_TA0_N);
|
|
Interrupt_unregisterInterrupt(INT_TA0_N);
|
|
break;
|
|
case TIMER_A1_BASE:
|
|
Interrupt_disableInterrupt(INT_TA1_N);
|
|
Interrupt_unregisterInterrupt(INT_TA1_N);
|
|
break;
|
|
case TIMER_A2_BASE:
|
|
Interrupt_disableInterrupt(INT_TA2_N);
|
|
Interrupt_unregisterInterrupt(INT_TA2_N);
|
|
break;
|
|
case TIMER_A3_BASE:
|
|
Interrupt_disableInterrupt(INT_TA3_N);
|
|
Interrupt_unregisterInterrupt(INT_TA3_N);
|
|
break;
|
|
default:
|
|
ASSERT(false);
|
|
}
|
|
} else
|
|
{
|
|
ASSERT(false);
|
|
}
|
|
}
|
|
|