281 lines
8.1 KiB
C
281 lines
8.1 KiB
C
/*
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* -------------------------------------------
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* MSP432 DriverLib - v3_40_00_10
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* -------------------------------------------
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*
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* --COPYRIGHT--,BSD,BSD
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* Copyright (c) 2016, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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/* Standard Includes */
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#include <stdint.h>
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#include <stdbool.h>
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/* DriverLib Includes */
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#include <sysctl.h>
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#include <debug.h>
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#ifdef DEBUG
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static bool SysCtlSRAMBankValid(uint8_t sramBank)
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{
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return(
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sramBank == SYSCTL_SRAM_BANK7 ||
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sramBank == SYSCTL_SRAM_BANK6 ||
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sramBank == SYSCTL_SRAM_BANK5 ||
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sramBank == SYSCTL_SRAM_BANK4 ||
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sramBank == SYSCTL_SRAM_BANK3 ||
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sramBank == SYSCTL_SRAM_BANK2 ||
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sramBank == SYSCTL_SRAM_BANK1
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);
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}
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static bool SysCtlSRAMBankValidRet(uint8_t sramBank)
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{
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sramBank &= ~(SYSCTL_SRAM_BANK7 & SYSCTL_SRAM_BANK6 &
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SYSCTL_SRAM_BANK5 & SYSCTL_SRAM_BANK4 &
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SYSCTL_SRAM_BANK3 & SYSCTL_SRAM_BANK2 &
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SYSCTL_SRAM_BANK1);
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return (sramBank == 0);
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}
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static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral)
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{
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hwPeripheral &= ~(SYSCTL_PERIPH_DMA & SYSCTL_PERIPH_WDT &
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SYSCTL_PERIPH_ADC & SYSCTL_PERIPH_EUSCIB3 &
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SYSCTL_PERIPH_EUSCIB2 & SYSCTL_PERIPH_EUSCIB1 &
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SYSCTL_PERIPH_EUSCIB0 & SYSCTL_PERIPH_EUSCIA3 &
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SYSCTL_PERIPH_EUSCIA2 & SYSCTL_PERIPH_EUSCIA1 &
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SYSCTL_PERIPH_EUSCIA0 & SYSCTL_PERIPH_TIMER32_0_MODULE &
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SYSCTL_PERIPH_TIMER16_3 & SYSCTL_PERIPH_TIMER16_2 &
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SYSCTL_PERIPH_TIMER16_2 & SYSCTL_PERIPH_TIMER16_1 &
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SYSCTL_PERIPH_TIMER16_0);
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return (hwPeripheral == 0);
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}
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#endif
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void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
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uint_fast8_t *length, uint32_t **data_address)
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{
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/* TLV Structure Start Address */
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uint32_t *TLV_address = (uint32_t *) TLV_START;
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while (((*TLV_address != tag)) // check for tag and instance
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&& (*TLV_address != TLV_TAGEND)) // do range check first
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{
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if (*TLV_address == tag)
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{
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if(instance == 0)
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{
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break;
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}
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/* Repeat until requested instance is reached */
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instance--;
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}
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TLV_address += (*(TLV_address + 1)) + 2;
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}
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/* Check if Tag match happened... */
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if (*TLV_address == tag)
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{
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/* Return length = Address + 1 */
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*length = (*(TLV_address + 1))*4;
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/* Return address of first data/value info = Address + 2 */
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*data_address = (uint32_t *) (TLV_address + 2);
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}
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// If there was no tag match and the end of TLV structure was reached..
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else
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{
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// Return 0 for TAG not found
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*length = 0;
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// Return 0 for TAG not found
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*data_address = 0;
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}
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}
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uint_least32_t SysCtl_getSRAMSize(void)
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{
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return SYSCTL->SRAM_SIZE;
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}
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uint_least32_t SysCtl_getFlashSize(void)
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{
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return SYSCTL->FLASH_SIZE;
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}
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void SysCtl_disableNMISource(uint_fast8_t flags)
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{
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SYSCTL->NMI_CTLSTAT &= ~(flags);
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}
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void SysCtl_enableNMISource(uint_fast8_t flags)
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{
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SYSCTL->NMI_CTLSTAT |= flags;
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}
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uint_fast8_t SysCtl_getNMISourceStatus(void)
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{
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return SYSCTL->NMI_CTLSTAT;
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}
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void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
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{
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ASSERT(SysCtlSRAMBankValid(sramBank));
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/* Waiting for SRAM Ready Bit to be set */
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while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
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;
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SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
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}
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void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
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{
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ASSERT(SysCtlSRAMBankValid(sramBank));
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/* Waiting for SRAM Ready Bit to be set */
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while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
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;
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switch (sramBank)
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{
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case SYSCTL_SRAM_BANK7:
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sramBank = SYSCTL_SRAM_BANK6 + SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
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+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
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+ SYSCTL_SRAM_BANK1;
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break;
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case SYSCTL_SRAM_BANK6:
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sramBank = SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
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+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
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+ SYSCTL_SRAM_BANK1;
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break;
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case SYSCTL_SRAM_BANK5:
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sramBank = SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3
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+ SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
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break;
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case SYSCTL_SRAM_BANK4:
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sramBank = SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
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+ SYSCTL_SRAM_BANK1;
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break;
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case SYSCTL_SRAM_BANK3:
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sramBank = SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
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break;
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case SYSCTL_SRAM_BANK2:
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sramBank = SYSCTL_SRAM_BANK1;
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break;
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case SYSCTL_SRAM_BANK1:
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sramBank = 0;
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break;
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default:
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return;
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}
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SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
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}
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void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
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{
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ASSERT(SysCtlSRAMBankValidRet(sramBank));
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/* Waiting for SRAM Ready Bit to be set */
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while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
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;
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SYSCTL->SRAM_BANKRET |= sramBank;
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}
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void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
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{
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ASSERT(SysCtlSRAMBankValidRet(sramBank));
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/* Waiting for SRAM Ready Bit to be set */
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while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
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;
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SYSCTL->SRAM_BANKRET &= ~sramBank;
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}
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void SysCtl_rebootDevice(void)
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{
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SYSCTL->REBOOT_CTL = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
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}
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void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
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{
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ASSERT(SysCtlPeripheralIsValid(devices));
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SYSCTL->PERIHALT_CTL &= ~devices;
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}
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void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
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{
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ASSERT(SysCtlPeripheralIsValid(devices));
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SYSCTL->PERIHALT_CTL |= devices;
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}
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void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
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{
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if (resetType)
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SYSCTL->WDTRESET_CTL |=
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SYSCTL_WDTRESET_CTL_TIMEOUT;
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else
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SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
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}
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void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
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{
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ASSERT(resetType <= SYSCTL_HARD_RESET);
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if (resetType)
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SYSCTL->WDTRESET_CTL |=
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SYSCTL_WDTRESET_CTL_VIOLATION;
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else
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SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
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}
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void SysCtl_enableGlitchFilter(void)
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{
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SYSCTL->DIO_GLTFLT_CTL |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
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}
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void SysCtl_disableGlitchFilter(void)
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{
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SYSCTL->DIO_GLTFLT_CTL &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
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}
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uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
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uint32_t temperature)
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{
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return HWREG16(TLV_BASE + refVoltage + temperature);
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}
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