539 lines
15 KiB
C
539 lines
15 KiB
C
/*
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* -------------------------------------------
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* MSP432 DriverLib - v3_40_00_10
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* -------------------------------------------
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*
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* --COPYRIGHT--,BSD,BSD
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* Copyright (c) 2016, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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/* Standard Includes */
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#include <stdint.h>
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/* DriverLib Includes */
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#include <debug.h>
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#include <cpu.h>
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#include <interrupt.h>
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//*****************************************************************************
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//
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// This is a mapping between priority grouping encodings and the number of
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// preemption priority bits.
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//
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//*****************************************************************************
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static const uint32_t g_pulPriority[] =
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{ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
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NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4,
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NVIC_APINT_PRIGROUP_5_3, NVIC_APINT_PRIGROUP_6_2,
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NVIC_APINT_PRIGROUP_7_1 };
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//*****************************************************************************
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//
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// This is a mapping between interrupt number and the register that contains
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// the priority encoding for that interrupt.
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//
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//*****************************************************************************
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static const uint32_t g_pulRegs[] =
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{ 0, NVIC_SYS_PRI1_R, NVIC_SYS_PRI2_R, NVIC_SYS_PRI3_R, NVIC_PRI0_R,
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NVIC_PRI1_R, NVIC_PRI2_R, NVIC_PRI3_R, NVIC_PRI4_R, NVIC_PRI5_R,
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NVIC_PRI6_R, NVIC_PRI7_R, NVIC_PRI8_R, NVIC_PRI9_R, NVIC_PRI10_R,
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NVIC_PRI11_R, NVIC_PRI12_R, NVIC_PRI13_R, NVIC_PRI14_R, NVIC_PRI15_R };
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//*****************************************************************************
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//
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// This is a mapping between interrupt number (for the peripheral interrupts
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// only) and the register that contains the interrupt enable for that
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// interrupt.
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//
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//*****************************************************************************
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static const uint32_t g_pulEnRegs[] =
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{ NVIC_EN0_R, NVIC_EN1_R };
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//*****************************************************************************
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//
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// This is a mapping between interrupt number (for the peripheral interrupts
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// only) and the register that contains the interrupt disable for that
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// interrupt.
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//
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//*****************************************************************************
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static const uint32_t g_pulDisRegs[] =
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{ NVIC_DIS0_R, NVIC_DIS1_R };
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//*****************************************************************************
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//
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// This is a mapping between interrupt number (for the peripheral interrupts
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// only) and the register that contains the interrupt pend for that interrupt.
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//
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//*****************************************************************************
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static const uint32_t g_pulPendRegs[] =
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{ NVIC_PEND0_R, NVIC_PEND1_R };
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//*****************************************************************************
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//
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// This is a mapping between interrupt number (for the peripheral interrupts
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// only) and the register that contains the interrupt unpend for that
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// interrupt.
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//
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//*****************************************************************************
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static const uint32_t g_pulUnpendRegs[] =
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{ NVIC_UNPEND0_R, NVIC_UNPEND1_R };
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//*****************************************************************************
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//
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//! \internal
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//! The default interrupt handler.
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//!
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//! This is the default interrupt handler for all interrupts. It simply loops
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//! forever so that the system state is preserved for observation by a
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//! debugger. Since interrupts should be disabled before unregistering the
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//! corresponding handler, this should never be called.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static void IntDefaultHandler(void)
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{
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//
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// Go into an infinite loop.
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//
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while (1)
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{
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}
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}
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//*****************************************************************************
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//
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// The processor vector table.
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//
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// This contains a list of the handlers for the various interrupt sources in
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// the system. The layout of this list is defined by the hardware; assertion
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// of an interrupt causes the processor to start executing directly at the
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// address given in the corresponding location in this list.
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//
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//*****************************************************************************
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#if defined(ewarm)
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#pragma data_alignment=1024
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static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) @ "VTABLE";
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#elif defined(ccs)
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#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
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#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
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void (*g_pfnRAMVectors[NUM_INTERRUPTS + 1])(void);
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#else
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static __attribute__((section("vtable")))
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void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) __attribute__((aligned(1024)));
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#endif
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bool Interrupt_enableMaster(void)
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{
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//
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// Enable processor interrupts.
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//
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return (CPU_cpsie());
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}
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bool Interrupt_disableMaster(void)
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{
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//
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// Disable processor interrupts.
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//
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return (CPU_cpsid());
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}
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void Interrupt_registerInterrupt(uint32_t interruptNumber,
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void (*intHandler)(void))
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{
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uint32_t ulIdx, ulValue;
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//
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// Check the arguments.
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//
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ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
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//
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// Make sure that the RAM vector table is correctly aligned.
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//
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ASSERT(((uint32_t) g_pfnRAMVectors & 0x000000ff) == 0);
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//
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// See if the RAM vector table has been initialized.
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//
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if (SCB->VTOR != (uint32_t) g_pfnRAMVectors)
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{
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//
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// Copy the vector table from the beginning of FLASH to the RAM vector
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// table.
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//
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ulValue = SCB->VTOR;
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for (ulIdx = 0; ulIdx < (NUM_INTERRUPTS + 1); ulIdx++)
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{
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g_pfnRAMVectors[ulIdx] = (void (*)(void)) HWREG32(
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(ulIdx * 4) + ulValue);
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}
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//
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// Point the NVIC at the RAM vector table.
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//
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SCB->VTOR = (uint32_t) g_pfnRAMVectors;
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}
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//
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// Save the interrupt handler.
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//
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g_pfnRAMVectors[interruptNumber] = intHandler;
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}
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void Interrupt_unregisterInterrupt(uint32_t interruptNumber)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
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//
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// Reset the interrupt handler.
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//
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g_pfnRAMVectors[interruptNumber] = IntDefaultHandler;
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}
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void Interrupt_setPriorityGrouping(uint32_t bits)
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{
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//
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// Check the arguments.
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//
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ASSERT(bits < NUM_PRIORITY);
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//
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// Set the priority grouping.
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//
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SCB->AIRCR = SCB_AIRCR_VECTKEY_Msk | g_pulPriority[bits];
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}
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uint32_t Interrupt_getPriorityGrouping(void)
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{
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uint32_t ulLoop, ulValue;
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//
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// Read the priority grouping.
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//
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ulValue = SCB->AIRCR & NVIC_APINT_PRIGROUP_M;
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//
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// Loop through the priority grouping values.
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//
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for (ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
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{
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//
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// Stop looping if this value matches.
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//
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if (ulValue == g_pulPriority[ulLoop])
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{
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break;
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}
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}
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//
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// Return the number of priority bits.
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//
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return (ulLoop);
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}
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void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority)
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{
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uint32_t ulTemp;
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//
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// Check the arguments.
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//
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ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
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//
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// Set the interrupt priority.
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//
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ulTemp = HWREG32(g_pulRegs[interruptNumber >> 2]);
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ulTemp &= ~(0xFF << (8 * (interruptNumber & 3)));
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ulTemp |= priority << (8 * (interruptNumber & 3));
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HWREG32 (g_pulRegs[interruptNumber >> 2]) = ulTemp;
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}
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uint8_t Interrupt_getPriority(uint32_t interruptNumber)
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{
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//
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// Check the arguments.
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//
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ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
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//
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// Return the interrupt priority.
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//
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return ((HWREG32(g_pulRegs[interruptNumber >> 2])
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>> (8 * (interruptNumber & 3))) & 0xFF);
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}
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void Interrupt_enableInterrupt(uint32_t interruptNumber)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
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//
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// Determine the interrupt to enable.
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//
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if (interruptNumber == FAULT_MPU)
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{
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//
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// Enable the MemManage interrupt.
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//
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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} else if (interruptNumber == FAULT_BUS)
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{
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//
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// Enable the bus fault interrupt.
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//
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SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
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} else if (interruptNumber == FAULT_USAGE)
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{
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//
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// Enable the usage fault interrupt.
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//
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
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} else if (interruptNumber == FAULT_SYSTICK)
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{
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//
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// Enable the System Tick interrupt.
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//
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SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
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} else if (interruptNumber >= 16)
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{
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//
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// Enable the general interrupt.
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//
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HWREG32 (g_pulEnRegs[(interruptNumber - 16) / 32]) = 1
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<< ((interruptNumber - 16) & 31);
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}
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}
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void Interrupt_disableInterrupt(uint32_t interruptNumber)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
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//
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// Determine the interrupt to disable.
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//
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if (interruptNumber == FAULT_MPU)
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{
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//
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// Disable the MemManage interrupt.
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//
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SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA_Msk);
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} else if (interruptNumber == FAULT_BUS)
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{
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//
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// Disable the bus fault interrupt.
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//
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SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA_Msk);
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} else if (interruptNumber == FAULT_USAGE)
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{
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//
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// Disable the usage fault interrupt.
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//
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SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA_Msk);
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} else if (interruptNumber == FAULT_SYSTICK)
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{
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//
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// Disable the System Tick interrupt.
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//
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SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
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} else if (interruptNumber >= 16)
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{
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//
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// Disable the general interrupt.
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//
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HWREG32 (g_pulDisRegs[(interruptNumber - 16) / 32]) = 1
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<< ((interruptNumber - 16) & 31);
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}
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}
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bool Interrupt_isEnabled(uint32_t interruptNumber)
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{
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uint32_t ulRet;
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//
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// Check the arguments.
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//
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ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
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//
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// Initialize the return value.
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//
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ulRet = 0;
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//
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// Determine the interrupt to disable.
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//
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if (interruptNumber == FAULT_MPU)
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{
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//
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// Check the MemManage interrupt.
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//
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ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA_Msk;
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} else if (interruptNumber == FAULT_BUS)
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{
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//
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// Check the bus fault interrupt.
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//
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ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA_Msk;
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} else if (interruptNumber == FAULT_USAGE)
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{
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//
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// Check the usage fault interrupt.
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//
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ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA_Msk;
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} else if (interruptNumber == FAULT_SYSTICK)
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{
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//
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// Check the System Tick interrupt.
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//
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ulRet = SysTick->CTRL & SysTick_CTRL_ENABLE_Msk;
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} else if (interruptNumber >= 16)
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{
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//
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// Check the general interrupt.
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//
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ulRet = HWREG32(g_pulEnRegs[(interruptNumber - 16) / 32])
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& (1 << ((interruptNumber - 16) & 31));
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}
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return (ulRet);
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}
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void Interrupt_pendInterrupt(uint32_t interruptNumber)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
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//
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// Determine the interrupt to pend.
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//
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if (interruptNumber == FAULT_NMI)
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{
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//
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// Pend the NMI interrupt.
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//
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SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk;
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} else if (interruptNumber == FAULT_PENDSV)
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{
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//
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// Pend the PendSV interrupt.
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//
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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} else if (interruptNumber == FAULT_SYSTICK)
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{
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//
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// Pend the SysTick interrupt.
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//
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SCB->ICSR |= SCB_ICSR_PENDSTSET_Msk;
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} else if (interruptNumber >= 16)
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{
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//
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// Pend the general interrupt.
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//
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HWREG32 (g_pulPendRegs[(interruptNumber - 16) / 32]) = 1
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<< ((interruptNumber - 16) & 31);
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}
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}
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void Interrupt_unpendInterrupt(uint32_t interruptNumber)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
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//
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// Determine the interrupt to unpend.
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//
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if (interruptNumber == FAULT_PENDSV)
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{
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//
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// Unpend the PendSV interrupt.
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//
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SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk;
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} else if (interruptNumber == FAULT_SYSTICK)
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{
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//
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// Unpend the SysTick interrupt.
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//
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SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
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} else if (interruptNumber >= 16)
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{
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//
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// Unpend the general interrupt.
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//
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HWREG32 (g_pulUnpendRegs[(interruptNumber - 16) / 32]) = 1
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<< ((interruptNumber - 16) & 31);
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}
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}
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void Interrupt_setPriorityMask(uint8_t priorityMask)
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{
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CPU_basepriSet(priorityMask);
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}
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uint8_t Interrupt_getPriorityMask(void)
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{
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return (CPU_basepriGet());
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}
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void Interrupt_setVectorTableAddress(uint32_t addr)
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{
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SCB->VTOR = addr;
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}
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uint32_t Interrupt_getVectorTableAddress(void)
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{
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return SCB->VTOR;
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}
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void Interrupt_enableSleepOnIsrExit(void)
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{
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SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
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}
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void Interrupt_disableSleepOnIsrExit(void)
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{
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SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
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}
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